4632 files changed, 349830 insertions, 0 deletions

diff --git a/testsuite/vests/.cvsignore b/testsuite/vests/.cvsignore
new file mode 100644
index 0000000..1e6f935
--- /dev/null
+++ b/testsuite/vests/.cvsignore
@@ -0,0 +1,2 @@
+*.log
+*.sum
diff --git a/testsuite/vests/COPYING b/testsuite/vests/COPYING
new file mode 100644
index 0000000..5b6e7c6
--- /dev/null
+++ b/testsuite/vests/COPYING
@@ -0,0 +1,340 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
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+  To protect your rights, we need to make restrictions that forbid
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+These restrictions translate to certain responsibilities for you if you
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+  Also, for each author's protection and ours, we want to make certain
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+  The precise terms and conditions for copying, distribution and
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+
+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+  0. This License applies to any program or other work which contains
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+		     END OF TERMS AND CONDITIONS
+
+	    How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
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+    Copyright (C) <year>  <name of author>
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+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
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+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
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+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.
diff --git a/testsuite/vests/LICENSE b/testsuite/vests/LICENSE
new file mode 100644
index 0000000..f84953f
--- /dev/null
+++ b/testsuite/vests/LICENSE
@@ -0,0 +1,35 @@
+
+                    LICENSE INFORMATION
+
+Copyright (c) 2001-2002 The University of Cincinnati.  All rights reserved.
+
+UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
+NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR DISTRIBUTING
+THIS SOFTWARE OR ITS DERIVATIVES.
+
+By using or copying this Software, Licensee agrees to abide by the
+intellectual property laws, and all other applicable laws of the U.S., and
+the terms of this license.
+
+You may modify, distribute, and use the software contained in this package
+under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, June
+1991. A copy of this license agreement can be found in the file "COPYING",
+distributed with this archive.
+
+VESTs is actually a collection of VHDL test files that have been
+contributed for collective distribution under the GNU Public License.  We
+encourage users to develop software and products with VESTs.  Whenever
+possible, we hope that users will also develop and contribute tests back
+for inclusion into VESTs.  Thank you.
+
+------------------------------------------------------------------------
+VESTs version 1.0
+Philip A. Wilsey 
+The University of Cincinnati
+vests@cliftonlabs.com
+------------------------------------------------------------------------
+Last Revised: March 27, 2002
+
diff --git a/testsuite/vests/README b/testsuite/vests/README
new file mode 100644
index 0000000..79a0d24
--- /dev/null
+++ b/testsuite/vests/README
@@ -0,0 +1,31 @@
+
+VESTs: Vhdl tESTs
+
+VESTs is a test suite for the VHDL language.  It is not intended to be a
+compliance suite or even a single unified test system for VHDL.  Instead
+it is designed be a public repository containing tests that can be
+meaningfully orgainized for the various versions or important subsets of
+the VHDL language.  We welcome and encourage contributions to VESTs with
+the restriction that the tests must be distributed under the GNU General
+Public License Version 2.  A copy of this license is in this directory
+in the file named COPYING.
+
+This directory contains the following subdirectories:
+
+vhdl-93:
+    Containing tests against the VHDL 1076-1993 language standard.
+
+vhdl-ams:
+    Containing tests against the VHDL 1076.1-1999 language standard.
+
+If you find errors or corrections to files contained herein or would
+like to submit additional tests for the VESTs suite, please contact us
+at vests@cliftonlabs.com.  Thank you.
+
+------------------------------------------------------------------------
+VESTs version 1.0
+Philip A. Wilsey 
+The University of Cincinnati
+vests@cliftonlabs.com
+------------------------------------------------------------------------
+Last Revised: March 27, 2002
diff --git a/testsuite/vests/testsuite.sh b/testsuite/vests/testsuite.sh
new file mode 100755
index 0000000..13593ca
--- /dev/null
+++ b/testsuite/vests/testsuite.sh
@@ -0,0 +1,180 @@
+#! /bin/sh
+
+. ../testenv.sh
+
+common_args="--std=93c"
+
+# Test number.
+test_num="1"
+
+do_inter_clean="no"
+
+# Functions used by tests.
+setup_test_group ()
+{
+  echo "Test: $1 $2"
+}
+
+end_test_group ()
+{
+  delete_lib work
+  echo "*** End of tests"
+}
+
+create_lib ()
+{
+  echo "create library: $1"
+}
+
+delete_lib ()
+{
+  echo "delete library: $1"
+  cmd="$GHDL --remove $common_args --work=$1"
+  echo $cmd
+  eval $cmd
+}
+
+# Usage: handle_test MODE FILE options...
+handle_test ()
+{
+  mode=$1
+  shift
+  file=$1
+  shift
+  args="$common_args"
+  # handle options.
+  for arg; do
+    case $arg in
+    LIBRARY=*)
+         lib=`echo $arg | sed -e s/LIBRARY=/--work=/`;
+         args="$args $lib";
+         ;;
+    INPUT=*)
+         input=$arg;
+         ;;
+    OUTPUT=*)
+         output=$arg;
+         ;;
+    *)
+         echo "build_compliant_test: unknown argument '$arg'";
+         exit 4;
+         ;;
+    esac
+  done
+  cmd="$GHDL -a $args $dir/$file"
+  echo "Test: $test_num"
+  echo $cmd
+
+  if [ $test_num -gt $skip ]; then
+    case $mode in
+    compile)
+         eval $cmd;
+         ;;
+    run)
+         eval $cmd
+         ;;
+    ana_err)
+         if eval $cmd; then
+           echo "Analyze error expected";
+           exit 1;
+         fi
+         ;;
+    run_err)
+         eval $cmd
+         ent=`sed -n -e "/^ENTITY \([a-zA-Z0-9]*\) IS$/p" < $dir/$file \
+              | cut -f 2 -d ' '`
+         cmd="$GHDL -e $ent"
+         echo "$cmd"
+         eval $cmd
+         cmd="$GHDL -r $ent --expect-failure --assert-level=error"
+         echo "$cmd"
+         eval $cmd
+         ;;
+    *)
+         echo "Unknown mode '$mode'";
+         exit 4;
+         ;;
+    esac
+  else
+    echo "skip";
+  fi
+  
+  # Increment test_num
+  test_num=`expr $test_num + 1`
+  
+  if [ $do_inter_clean = "yes" ]; then
+    if [ `expr $test_num % 16` = "0" ]; then
+       delete_lib work;
+    fi
+  fi
+}
+
+build_compliant_test ()
+{
+  handle_test compile $@
+}
+
+run_non_compliant_test ()
+{
+   handle_test ana_err $@
+}
+
+run_compliant_test ()
+{
+   handle_test run $@
+}
+
+
+# Decode options.
+skip=0
+
+while [ $# -gt 0 ]
+do
+  arg=$1;
+  case $arg in
+    -j)  shift;
+         skip=$1;
+         ;;
+    *) exit 1;
+         ;;
+  esac
+  shift;
+done
+
+# Test group
+
+# ashenden compliant
+# OK
+dir=vhdl-93/ashenden/compliant
+. $dir/compliant.exp
+
+# OK
+dir=vhdl-93/ashenden/non_compliant
+. $dir/non_compliant.exp
+
+
+# Clean frequently the work library.
+do_inter_clean="yes"
+
+# OK.
+dir=vhdl-93/billowitch/compliant
+. $dir/compliant.exp
+
+
+# OK but FIXMEs
+dir=vhdl-93/billowitch/non_compliant/analyzer_failure
+. $dir/non_compliant.exp
+
+run_non_compliant_test ()
+{
+   handle_test run_err $@
+}
+
+dir=vhdl-93/billowitch/non_compliant/simulator_failure
+. $dir/non_compliant.exp
+
+delete_lib project
+delete_lib random
+delete_lib utilities
+
+echo "Vests tests successful"
diff --git a/testsuite/vests/vhdl-93/README b/testsuite/vests/vhdl-93/README
new file mode 100644
index 0000000..9f57478
--- /dev/null
+++ b/testsuite/vests/vhdl-93/README
@@ -0,0 +1,28 @@
+
+This directory contains tests for the 1076-1993 standard.  It contains
+the following subdirectories:
+
+ad-hoc:
+    Containing tests collected from various sources.  In general tests
+    in this subdirectory are one-off constructions that have been
+    made available for us to include in VESTs.
+
+ashenden: 
+    Containing tests from The Designer's Guild to VHDL written by Peter
+    Ashenden and published by Morgan Kaufmann Publishers, Inc in 1996.
+
+billowitch: 
+    Containing tests that were originally developed by Bill Billowitch
+    for the VHDL 1076-1987 language standard.
+
+If you find errors or corrections to these files or would like to submit
+additional tests for the VESTs suite, please contact us at
+vests@cliftonlabs.com.  Thank you.
+
+------------------------------------------------------------------------
+Philip A. Wilsey 
+The University of Cincinnati
+vests@cliftonlabs.com
+------------------------------------------------------------------------
+Last Revised: March 27, 2002
+
diff --git a/testsuite/vests/vhdl-93/ashenden/README b/testsuite/vests/vhdl-93/ashenden/README
new file mode 100644
index 0000000..30d9eda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/README
@@ -0,0 +1,27 @@
+
+This directory contains copies of the VHDL files from The Designer's
+Guild to VHDL written by Peter Ashenden and published by Morgan Kaufmann
+Publishers, Inc in 1996.  Morgan Kaufmann has given the University of
+Cincinnati permission to release these files under the GNU Public
+License.
+
+In many cases the original figures contained incomplete VHDL.  We have
+added additional VHDL constructs we believed necessary to make the VHDL
+complete and processable by a VHDL '93 compliant analyzer.  As we made
+changes to the examples, comments were inserted to demarcate the changes
+we made.
+
+The VHDL files are organized into two subdirectories, fail_tests and
+pass_tests, corresponding to their being non-compliant or compliant to
+the 1076-1993 standard.
+
+If you find errors or corrections to these files, please submit them to
+us at vests@cliftonlabs.com.  Thank you.
+
+------------------------------------------------------------------------
+Philip A. Wilsey 
+The University of Cincinnati
+vests@cliftonlabs.com
+------------------------------------------------------------------------
+Last Revised: March 27, 2002
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_01.vhd
new file mode 100644
index 0000000..9444ed8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_01.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_01 is
+
+end entity ap_a_01;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_01 is
+
+  signal clk : std_ulogic;
+
+begin
+
+  process (clk) is
+
+                  -- code from book
+
+                  -- end code from book
+
+  begin
+
+    if
+
+      -- code from book
+
+      clk'event and (To_X01(clk) = '1') and (To_X01(clk'last_value) = '0')
+
+      -- end code from book
+
+    then
+      report "rising edge on clk";
+    end if;
+
+  end process;
+
+  clk <= '0', '1' after 10 ns, '0' after 20 ns,
+         '1' after 30 ns, '0' after 40 ns;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_02.vhd
new file mode 100644
index 0000000..c7a4a5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_02.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_02 is
+
+end entity ap_a_02;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_02 is
+
+  -- code from book
+
+  -- end code from book
+
+begin
+
+  b1 : block is
+               signal sulv : std_ulogic_vector(7 downto 0);
+             signal slv : std_logic_vector(7 downto 0);
+  begin
+    -- code from book
+
+    sulv <= To_stdulogicvector ( slv );
+
+    -- end code from book
+    slv <= "10101010";
+  end block b1;
+
+  b2 : block is
+               signal sulv : std_ulogic_vector(7 downto 0);
+             signal slv : std_logic_vector(7 downto 0);
+  begin
+    -- code from book
+
+    slv <= To_stdlogicvector ( sulv );
+
+    -- end code from book
+    sulv <= "00001111";
+  end block b2;
+
+  b3 : block is
+               signal a, ena, y : std_logic;
+  begin
+    -- code from book
+
+    y <= a when ena = '1' else
+         'Z';
+
+    -- end code from book
+    ena <= '0', '1' after 20 ns, '0' after 40 ns;
+    a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
+  end block b3;
+
+  b4 : block is
+               signal a, ena, y : std_logic;
+  begin
+    -- code from book
+
+    y <= a when ena = '1' else
+         'H';
+
+    -- end code from book
+    ena <= '0', '1' after 20 ns, '0' after 40 ns;
+    a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;
+  end block b4;
+
+  b5 : block is
+               signal a, b, x, s, y : std_logic;
+  begin
+    -- code from book
+
+    y <= a when x = '1' else
+         b when s = '1' else
+         '-';
+
+    -- end code from book
+    x <= '0', '1' after 20 ns, '0' after 40 ns;
+    s <= '0', '1' after 60 ns, '0' after 80 ns;
+    a <= '0', '1' after 10 ns, '0' after 30 ns,
+         '1' after 50 ns, '0' after 70 ns,
+         '1' after 90 ns;
+    b <= '0', '1' after 15 ns, '0' after 35 ns,
+         '1' after 55 ns, '0' after 75 ns,
+         '1' after 95 ns;
+  end block b5;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_03.vhd
new file mode 100644
index 0000000..87ddfbc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_03.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_03 is
+
+end entity ap_a_03;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.numeric_std.all;
+
+architecture test of ap_a_03 is
+begin
+
+  b1 : block is
+               -- code from book
+
+               type unsigned is array ( natural range <> ) of std_logic;
+             type signed is array ( natural range <> ) of std_logic;
+
+             -- end code from book
+  begin
+  end block b1;
+
+
+  b2 : block is
+               -- code from book
+
+               signal a: integer := 0;
+             signal b: signed (4 downto 0 );
+
+             -- end code from book
+  begin
+    a <= 0, 5 after 10 ns, -5 after 20 ns, 8 after 30 ns;
+    -- code from book
+
+    b <= To_signed ( a, b'length );
+
+    -- end code from book
+
+    process (b) is
+    begin
+
+      -- code from book
+
+      if std_match ( b, "0-000" ) then
+        -- . . .
+
+        -- end code from book
+        report "b matches";
+      else
+        report "b does not match";
+      end if;    
+    end process;
+
+    
+
+  end block b2;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_04.vhd
new file mode 100644
index 0000000..529feda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_04.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_04 is
+
+end entity ap_a_04;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_04 is
+
+  signal a, b, y : std_ulogic;
+
+begin
+
+  -- code from book
+
+  y <= a or b;
+
+  -- end code from book
+
+  a <= '0', '1' after 10 ns;
+  b <= '0', '1' after 5 ns, '0' after 10 ns, '1' after 15 ns;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_05.vhd
new file mode 100644
index 0000000..c2b8470
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_05.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_05 is
+
+end entity ap_a_05;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_05 is
+
+  signal a, b, y, x : std_ulogic;
+
+begin
+
+  -- code from book
+
+  y <= a when x = '1' else
+       b;
+
+  -- end code from book
+
+  x <= '0', '1' after 20 ns;
+  a <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
+  b <= '0', '1' after 15 ns, '0' after 25 ns, '1' after 35 ns;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_06.vhd
new file mode 100644
index 0000000..43daac2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_06.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_06.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_06 is
+
+end entity ap_a_06;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_06 is
+
+  signal a, ts, x : std_ulogic;
+
+begin
+
+  -- code from book
+
+  ts <= a when x = '1' else
+        'Z';
+
+  -- end code from book
+
+  x <= '0', '1' after 20 ns;
+  a <= '0', '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_07.vhd
new file mode 100644
index 0000000..d7481fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_07.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity bidir_buffer is
+                 port ( bidir : inout std_logic_vector;
+                        ena : in std_ulogic;
+                        going_out : in std_ulogic_vector;
+                        coming_in : out std_ulogic_vector );
+               end entity bidir_buffer;
+
+--------------------------------------------------
+
+               architecture behavior of bidir_buffer is
+-- code from book
+
+                 constant hi_impedance : std_logic_vector(bidir'range) := (others => 'Z');
+                 -- . . .
+
+-- end code from book
+               begin
+-- code from book
+
+                 bidir <= To_stdlogicvector(going_out) when ena = '1' else
+                          hi_impedance;
+                 coming_in <= To_stdulogicvector(bidir);
+
+-- end code from book
+               end architecture behavior;
+
+
+
+               entity ap_a_07 is
+               end entity ap_a_07;
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+               architecture test of ap_a_07 is
+
+                 signal bidir : std_logic_vector(3 downto 0);
+                 signal going_out, coming_in : std_ulogic_vector(3 downto 0);
+                 signal ena : std_ulogic;
+
+               begin
+
+                 dut : entity work.bidir_buffer
+                   port map ( bidir, ena, going_out, coming_in );
+
+                 ena <= '0', '1' after 10 ns, '0' after 30 ns;
+
+                 going_out <= "0000", "1111" after 20 ns;
+
+                 bidir <= "ZZZZ", "0000" after 40 ns, "1111" after 50 ns, "ZZZZ" after 60 ns;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_08.vhd
new file mode 100644
index 0000000..6d69213
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_08.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity entname is
+               end entity entname;
+
+
+
+               architecture rtl of entname is
+
+                 -- code from book
+
+                 subtype state_type is std_ulogic_vector(3 downto 0);
+                 constant s0 : state_type := "0001";
+                 constant s1 : state_type := "0010";
+                 constant s2 : state_type := "0100";
+                 constant s3 : state_type := "1000";
+
+                 -- end code from book
+
+                 signal state, next_state : state_type;
+                 signal con1, con2, con3 : std_ulogic;
+                 signal out1, out2 : std_ulogic;
+                 signal clk, reset : std_ulogic;
+
+               begin
+                 state_logic : process (state, con1, con2, con3) is
+                 begin
+                   case state is
+                     when s0 =>
+                       out1 <= '0';
+                       out2 <= '0';
+                       next_state <= s1; 
+                     when s1 =>
+                       out1 <= '1';
+                       if con1 = '1' then
+                         next_state <= s2;
+                       else
+                         next_state <= s1;
+                       end if;
+                     when s2 =>
+                       out2 <= '1';
+                       next_state <= s3;
+                     when s3 =>
+                       if con2 = '0' then
+                         next_state <= s3;
+                       elsif con3 = '0' then
+                         out1 <= '0';
+                         next_state <= s2;
+                       else
+                         next_state <= s1;
+                       end if;
+                     when others =>
+                       null;
+                   end case;
+                 end process state_logic;
+
+                 state_register : process (clk, reset) is
+                 begin
+                   if reset = '0' then
+                     state <= s0;
+                   elsif rising_edge(clk) then
+                     state <= next_state;
+                   end if;
+                 end process state_register;
+
+
+                 clk_gen : process is
+                 begin
+                   clk <= '0', '1' after 10 ns;
+                   wait for 20 ns;
+                 end process clk_gen;
+
+                 reset <= '0', '1' after 40 ns;
+
+                 con1 <= '0', '1' after 100 ns, '0' after 120 ns;
+
+                 con2 <= '0', '1' after 160 ns;
+
+                 con3 <= '0', '1' after 220 ns;
+
+
+               end architecture rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_09.vhd
new file mode 100644
index 0000000..52e558c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_09.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_09.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_09 is
+
+end entity ap_a_09;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ap_a_09 is
+
+  signal a, b, c, d : integer := 0;
+
+begin
+
+  b1 : block is
+               signal y : integer;
+  begin
+    -- code from book
+
+    y <= a + b + c + d;
+
+    -- end code from book
+  end block b1;
+
+  b2 : block is
+               signal y : integer;
+  begin
+    -- code from book
+
+    y <= ( a + b ) + ( c + d );
+
+    -- end code from book
+  end block b2;
+
+  stimulus : process is
+  begin
+    a <= 1; wait for 10 ns;
+    b <= 2; wait for 10 ns;
+    c <= 3; wait for 10 ns;
+    d <= 4; wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_10.vhd
new file mode 100644
index 0000000..198029e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_ap_a_10.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_ap_a_10.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ap_a_10 is
+end entity ap_a_10;
+
+library ieee;  
+use ieee.std_logic_1164.all;
+
+library stimulus;  
+use stimulus.stimulus_generators.all;
+
+architecture test of ap_a_10 is
+
+  signal a, b, c, d : std_ulogic;
+  signal test_vector : std_ulogic_vector(1 to 4);
+
+begin
+
+  b1 : block is
+               signal y : std_ulogic;
+  begin
+    -- code from book
+
+    y <= a or b or c or d;
+
+    -- end code from book
+  end block b1;
+
+  b2 : block is
+               signal y : std_ulogic;
+  begin
+    -- code from book
+
+    y <= ( a or b ) or ( c or d );
+
+    -- end code from book
+  end block b2;
+
+  b3 : block is
+               signal y : std_ulogic;
+  begin
+    -- code from book (syntax error)
+
+    -- y <= a or b or c and d;
+
+    -- end code from book
+  end block b3;
+
+  b4 : block is
+               signal y : std_ulogic;
+  begin
+    -- code from book
+
+    y <= ( a or b ) or ( c and d );
+
+    -- end code from book
+  end block b4;
+
+  stimulus : all_possible_values(test_vector, 10 ns);
+
+  (a, b, c, d) <= test_vector;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_01.vhd
new file mode 100644
index 0000000..9b7c90a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_01.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_01 is
+end entity fg_a_01;
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_01 is
+
+  signal clk, d : std_ulogic;
+
+begin
+
+  stimulus : process is
+  begin
+    clk <= '0';  d <= '0';  wait for 10 ns;
+    clk <= '1', '0' after 10 ns;  wait for 20 ns;
+    d <= '1';  wait for 10 ns;
+    clk <= '1', '0' after 20 ns;  d <= '0' after 10 ns;
+
+    wait;
+  end process stimulus;
+
+
+  b1 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    process (clk) is
+    begin
+      if rising_edge(clk) then
+        q <= d;
+      end if;
+    end process;
+
+    -- end code from book
+
+  end block b1;
+
+
+  b2 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    process is
+    begin
+      wait until rising_edge(clk);
+      q <= d;
+    end process;
+
+    -- end code from book
+
+  end block b2;
+
+
+  b3 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    q <= d when rising_edge(clk) else
+         q;
+
+    -- end code from book
+
+  end block b3;
+
+
+  b4 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    b : block ( rising_edge(clk)
+                and not clk'stable ) is
+    begin
+      q <= guarded d;
+    end block b;
+
+    -- end code from book
+
+  end block b4;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_02.vhd
new file mode 100644
index 0000000..f603f5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_02.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_02 is
+
+end entity fg_a_02;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_02 is
+
+  signal clk, a, b : std_ulogic;
+
+begin
+
+  stimulus : process is
+  begin
+    clk <= '0';  a <= '0';  b <= '0';  wait for 10 ns;
+    clk <= '1', '0' after 10 ns;  wait for 20 ns;
+    b <= '1';  wait for 10 ns;
+    clk <= '1', '0' after 20 ns;  a <= '0' after 10 ns;
+
+    wait;
+  end process stimulus;
+
+
+  b1 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    process (clk) is
+                    variable d : std_ulogic;
+    begin
+      if a = b then
+        d := '1';
+      else
+        d := '0';
+      end if;
+      if rising_edge(clk) then
+        q <= d;
+      end if;
+    end process;
+
+    -- end code from book
+
+  end block b1;
+
+
+
+  b2 : block is
+               signal q : std_ulogic;
+  begin
+
+    -- code from book
+
+    process (clk) is
+    begin
+      if rising_edge(clk) then
+        if a = b then
+          q <= '1';
+        else
+          q <= '0';
+        end if;
+      end if;
+    end process;
+
+    -- end code from book
+
+  end block b2;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_03.vhd
new file mode 100644
index 0000000..d3a6af0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_03.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity add_and_sub is
+                 port ( a, b, c : in natural;
+                        y : out natural;
+                        ovf : out std_ulogic );
+               end entity add_and_sub;
+
+--------------------------------------------------
+
+               library ieee;  use ieee.numeric_std.all;
+
+               architecture rtl of add_and_sub is
+                 signal stage2, stage3 : unsigned ( 8 downto 0 );
+               begin
+                 stage2 <= To_unsigned(a, 9) + to_unsigned(b, 9);  -- "+" from numeric_std
+                 stage3 <= stage2 - c;              -- "-" from numeric_std
+                 y <= To_integer(stage3) ;
+                 ovf <= stage3(8);
+               end rtl;
+
+-- end code from book
+
+
+
+               entity fg_a_03 is
+               end entity fg_a_03;
+
+
+               library ieee;
+               use ieee.std_logic_1164.all, ieee.numeric_std.all;
+
+               architecture test of fg_a_03 is
+
+                 signal a, b, c, y : natural := 0;
+                 signal ovf : std_ulogic;
+
+               begin
+
+                 dut : entity work.add_and_sub
+                   port map ( a, b, c, y, ovf );
+
+                 stimulus : process is
+                 begin
+                   wait for 10 ns;
+                   a <= 2;  b <= 5;  c <= 3;  wait for 10 ns;
+                   a <= 192;  b <= 192;  wait for 10 ns;
+                   a <= 10;  b <= 11;  c <= 22;  wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_04.vhd
new file mode 100644
index 0000000..1e1da2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_04.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_04 is
+
+end entity fg_a_04;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_04 is
+
+  signal clk, reset, d, q, q_n : std_ulogic;
+
+begin
+
+  -- code from book
+
+  ff1 : process (reset, clk) is
+  begin
+    if reset = '1' then
+      q <= '0';
+    elsif rising_edge(clk) then
+      q <= d;
+    end if;
+  end process ff1;
+
+  q_n <= not q;
+
+  -- end code from book
+
+  stimulus : process is
+  begin
+    reset <= '0';  clk <= '0';  d <= '1';  wait for 10 ns;
+    reset <= '1', '0' after 30 ns;
+    clk <= '1' after 10 ns, '0' after 20 ns;
+    wait for 40 ns;
+    clk <= '1', '0' after 20 ns;
+    d <= '0' after 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_05.vhd
new file mode 100644
index 0000000..7304b82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_05.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_05 is
+
+end entity fg_a_05;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_05 is
+
+  signal clk, reset, a, b, x, q : std_ulogic;
+
+begin
+
+  -- code from book
+
+  ff2 : process (reset, clk) is
+  begin
+    if reset = '1' then
+      q <= '0';
+    elsif rising_edge(clk) then
+      if x = '1' then
+        q <= a;
+      else
+        q <= b;
+      end if;
+    end if;
+  end process ff2;
+
+  -- end code from book
+
+  stimulus : process is
+  begin
+    reset <= '0';  clk <= '0';  x <= '1'; a <= '1'; b <= '0';  wait for 10 ns;
+    reset <= '1', '0' after 30 ns;
+    clk <= '1' after 10 ns, '0' after 20 ns;
+    wait for 40 ns;
+    clk <= '1', '0' after 2 ns,
+           '1' after 12 ns, '0' after 14 ns,
+           '1' after 17 ns, '0' after 19 ns,
+           '1' after 22 ns, '0' after 24 ns,
+           '1' after 27 ns, '0' after 29 ns,
+           '1' after 32 ns, '0' after 34 ns,
+           '1' after 37 ns, '0' after 39 ns,
+           '1' after 42 ns, '0' after 44 ns,
+           '1' after 47 ns, '0' after 49 ns;
+    a <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
+    b <= '0' after 15 ns, '1' after 25 ns, '0' after 35 ns, '1' after 45 ns;
+    x <= '0' after 30 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_06.vhd
new file mode 100644
index 0000000..bc62919
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_06.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_06.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_06 is
+
+end entity fg_a_06;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_06 is
+
+  -- code from book
+
+  constant terminal_count : integer := 2**6 - 1;
+  subtype counter_range is integer range 0 to terminal_count;
+  signal count : counter_range;
+  -- . . .
+
+  -- end code from book
+
+  signal clk, reset : std_ulogic;
+
+begin
+
+  -- code from book
+
+  counter6 : process (reset, clk)
+  begin
+    if reset = '0' then
+      count <= 0;
+    elsif rising_edge(clk) then
+      if count < terminal_count then
+        count <= count + 1;
+      else
+        count <= 0;
+      end if;
+    end if;
+  end process counter6;
+
+  -- end code from book
+
+  stimulus : process is
+  begin
+    reset <= '1';  clk <= '0';  wait for 10 ns;
+    clk <= '1', '0' after 10 ns;  wait for 20 ns;
+    clk <= '1', '0' after 10 ns;  wait for 20 ns;
+    clk <= '1', '0' after 10 ns;  wait for 20 ns;
+    reset <= '0', '1' after 30 ns;
+    clk <= '1' after 10 ns, '0' after 20 ns;
+    wait for 40 ns;
+    for i in 1 to terminal_count + 10 loop
+      clk <= '1', '0' after 10 ns;
+      wait for 20 ns;
+    end loop;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_07.vhd
new file mode 100644
index 0000000..ebf0574
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_07.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity bidir_buffer is
+                 port ( bidir : inout std_logic;
+                        ena : in std_ulogic;
+                        going_out : in std_ulogic;
+                        coming_in : out std_ulogic );
+               end entity bidir_buffer;
+
+--------------------------------------------------
+
+               architecture behavior of bidir_buffer is
+               begin
+                 bidir <= going_out when ena = '1' else
+                          'Z';
+                 coming_in <= bidir;
+               end architecture behavior;
+
+-- end code from book
+
+
+
+               entity fg_a_07 is
+               end entity fg_a_07;
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               architecture test of fg_a_07 is
+
+                 signal bidir : std_logic;
+                 signal ena, going_out, coming_in : std_ulogic;
+
+               begin
+
+                 dut : entity work.bidir_buffer
+                   port map ( bidir, ena, going_out, coming_in );
+
+                 ena <= '0', '1' after 10 ns, '0' after 30 ns;
+
+                 going_out <= '0', '1' after 20 ns;
+
+                 bidir <= 'Z', '0' after 40 ns, '1' after 50 ns, 'Z' after 60 ns;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_08.vhd
new file mode 100644
index 0000000..f11d4fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_08.vhd
@@ -0,0 +1,105 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity entname is
+               end entity entname;
+
+-- end not in book
+
+
+               architecture rtl of entname is
+
+                 type state_type is (s0, s1, s2, s3);
+                 signal state, next_state : state_type;
+                 signal con1, con2, con3 : std_ulogic;
+                 signal out1, out2 : std_ulogic;
+                 signal clk, reset : std_ulogic;
+                 -- . . .
+
+               begin
+                 state_logic : process (state, con1, con2, con3) is
+                 begin
+                   case state is
+                     when s0 =>
+                       out1 <= '0';
+                       out2 <= '0';
+                       next_state <= s1; 
+                     when s1 =>
+                       out1 <= '1';
+                       if con1 = '1' then
+                         next_state <= s2;
+                       else
+                         next_state <= s1;
+                       end if;
+                     when s2 =>
+                       out2 <= '1';
+                       next_state <= s3;
+                     when s3 =>
+                       if con2 = '0' then
+                         next_state <= s3;
+                       elsif con3 = '0' then
+                         out1 <= '0';
+                         next_state <= s2;
+                       else
+                         next_state <= s1;
+                       end if;
+                   end case;
+                 end process state_logic;
+
+                 state_register : process (clk, reset) is
+                 begin
+                   if reset = '0' then
+                     state <= s0;
+                   elsif rising_edge(clk) then
+                     state <= next_state;
+                   end if;
+                 end process state_register;
+
+                 -- . . .
+
+                 -- not in book
+
+                 clk_gen : process is
+                 begin
+                   clk <= '0', '1' after 10 ns;
+                   wait for 20 ns;
+                 end process clk_gen;
+
+                 reset <= '0', '1' after 40 ns;
+
+                 con1 <= '0', '1' after 100 ns, '0' after 120 ns;
+
+                 con2 <= '0', '1' after 160 ns;
+
+                 con3 <= '0', '1' after 220 ns;
+
+                 -- end not in book
+
+               end architecture rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_09.vhd
new file mode 100644
index 0000000..1baf1da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_09.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_09.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_09 is
+end entity fg_a_09;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_09 is
+
+  signal clk25M, resetl : std_ulogic;
+  signal data, odat : std_ulogic_vector(7 downto 0);
+
+begin
+
+  -- code from book
+
+  wrong_way : process ( clk25M, resetl, data )
+  begin
+    if resetl = '0' then
+      odat <= B"0000_0000";
+    elsif rising_edge(clk25M) then
+      odat <= data;
+    elsif data = B"0000_0000" then
+      odat <= B"0000_0001";
+    end if;
+  end process wrong_way;
+
+  -- end code from book
+
+  data <= odat(6 downto 0) & '0';
+
+  clk_gen : process is
+  begin
+    clk25M <= '0', '1' after 10 ns;
+    wait for 20 ns;
+  end process clk_gen;
+
+  resetl <= '1', '0' after 20 ns, '1' after 60 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_10.vhd
new file mode 100644
index 0000000..064d6c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_10.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_10.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_a_10 is
+end entity fg_a_10;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_a_10 is
+
+  signal clk25M, resetl : std_ulogic;
+  signal data, odat : std_ulogic_vector(7 downto 0);
+
+begin
+
+  -- code from book
+
+  right_way : process ( clk25M, resetl )
+  begin
+    if resetl = '0' then
+      odat <= B"0000_0000";
+    elsif rising_edge(clk25M) then
+      if data = B"0000_0000" then
+        odat <= B"0000_0001";
+      else
+        odat <= data;
+      end if;
+    end if;
+  end process right_way;
+
+  -- end code from book
+
+  data <= odat(6 downto 0) & '0';
+
+  clk_gen : process is
+  begin
+    clk25M <= '0', '1' after 10 ns;
+    wait for 20 ns;
+  end process clk_gen;
+
+  resetl <= '1', '0' after 20 ns, '1' after 60 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_11.vhd
new file mode 100644
index 0000000..cb4887d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ap_a_fg_a_11.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ap_a_fg_a_11.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity RAM16x1 is
+                 port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
+                        \d\, \we\ : in std_ulogic;
+                        \o\ : out std_ulogic );
+               end entity RAM16x1;
+
+
+               architecture a of RAM16x1 is
+               begin
+               end architecture a;
+
+
+
+               entity fg_a_11 is
+               end entity fg_a_11;
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               architecture test of fg_a_11 is
+
+                 -- code from book
+
+                 component RAM16x1 is
+                                     port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
+                                            \d\, \we\ : in std_ulogic;
+                                            \o\ : out std_ulogic );
+                 end component RAM16x1;
+                 -- . . .
+
+                 -- end code from book
+
+                 signal address : std_ulogic_vector(3 downto 0);
+                 signal raminp, ramout : std_ulogic_vector(15 downto 0);
+                 signal write_enable : std_ulogic;
+
+               begin
+
+                 -- code from book
+
+                 g1 : for i in 0 to 15 generate
+                   rama : component RAM16x1
+                     port map ( \a<0>\ => address(0),
+                                \a<1>\ => address(1),
+                                \a<2>\ => address(2),
+                                \a<3>\ => address(3),
+                                \d\ => raminp ( i ),
+                                \we\ => write_enable,
+                                \o\ => ramout ( i ) );
+                 end generate g1;
+
+                 -- end code from book
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic.vhd
new file mode 100644
index 0000000..064ff92
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bv_arithmetic.vhd,v 1.2 2001-10-25 01:24:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+--------------------------------------------------------------------------
+--
+--  Bit-vector arithmetic package interface.
+--  
+--  Does arithmetic and logical operations on bit vectors, treating them
+--  as either unsigned or signed (two's complement) integers.  Leftmost bit
+--  is most-significant or sign bit, rightmost bit is least-significant
+--  bit.  Dyadic operations need the two arguments to be of the same
+--  length; however, their index ranges and directions may differ.  Results
+--  must be of the same length as the operands.
+--  
+--------------------------------------------------------------------------
+
+package bv_arithmetic is
+
+  function bv_to_natural ( bv : in bit_vector ) return natural;
+
+  function natural_to_bv ( nat : in natural;
+      	      	      	   length : in natural ) return bit_vector;
+
+  function bv_to_integer ( bv : in bit_vector ) return integer;
+
+  function integer_to_bv ( int : in integer;
+      	      	      	   length : in natural ) return bit_vector;
+
+  procedure bv_add ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     overflow : out boolean );
+
+  function "+" ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_sub ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     overflow : out boolean );
+
+  function "-" ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_addu ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean );
+
+  function bv_addu ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_subu ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean );
+
+  function bv_subu ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_neg ( bv : in bit_vector;
+                     bv_result : out bit_vector;
+                     overflow : out boolean );
+
+  function "-" ( bv : in bit_vector ) return bit_vector;
+
+  procedure bv_mult ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean );
+
+  function "*" ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_multu ( bv1, bv2 : in bit_vector;
+      	       	       bv_result : out bit_vector;
+		       overflow : out boolean );
+
+  function bv_multu ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_div ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     div_by_zero : out boolean;
+                     overflow : out boolean );
+
+  function "/" ( bv1, bv2 : in bit_vector ) return bit_vector;
+
+  procedure bv_divu ( bv1, bv2 : in bit_vector;
+      	       	      bv_quotient : out bit_vector;
+		      bv_remainder : out bit_vector;
+		      div_by_zero : out boolean );
+
+  procedure bv_divu ( bv1, bv2 : in bit_vector;
+      	       	      bv_quotient : out bit_vector;
+		      div_by_zero : out boolean );
+
+  function bv_divu ( bv1, bv2 : in bit_vector )  return bit_vector;
+
+  function bv_lt ( bv1, bv2 : in bit_vector ) return boolean;
+
+  function bv_le ( bv1, bv2 : in bit_vector ) return boolean;
+
+  function bv_gt ( bv1, bv2 : in bit_vector ) return boolean;
+
+  function bv_ge ( bv1, bv2 : in bit_vector ) return boolean;
+
+  function bv_sext ( bv : in bit_vector;
+      	      	     length : in natural ) return bit_vector;
+
+  function bv_zext ( bv : in bit_vector;
+      	      	     length : in natural ) return bit_vector;
+
+end package bv_arithmetic;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic_body.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic_body.vhd
new file mode 100644
index 0000000..41267bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic_body.vhd
@@ -0,0 +1,647 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bv_arithmetic_body.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+package body bv_arithmetic is
+
+  ----------------------------------------------------------------
+  --  Type conversions
+  ----------------------------------------------------------------
+
+  function bv_to_natural ( bv : in bit_vector ) return natural is
+
+    variable result : natural := 0;
+
+  begin
+    for index in bv'range loop
+      result := result * 2 + bit'pos( bv(index) );
+    end loop;
+    return result;
+  end function bv_to_natural;
+
+  function natural_to_bv ( nat : in natural;
+      	      	      	   length : in natural ) return bit_vector is
+
+    variable temp : natural := nat;
+    variable result : bit_vector(length - 1 downto 0) := (others => '0');
+
+  begin
+    for index in result'reverse_range loop
+      result(index) := bit'val( temp rem 2 );
+      temp := temp / 2;
+      exit when temp = 0;
+    end loop;
+    return result;
+  end function natural_to_bv;
+
+  function bv_to_integer ( bv : in bit_vector ) return integer is
+
+    variable temp : bit_vector(bv'range);
+    variable result : integer := 0;
+
+  begin
+    if bv(bv'left) = '1' then	  -- negative number
+      temp := not bv;
+    else
+      temp := bv;
+    end if;
+    for index in bv'range loop	  -- sign bit of temp = '0'
+      result := result * 2 + bit'pos( temp(index) );
+    end loop;
+    if bv(bv'left) = '1' then
+      result := (-result) - 1;
+    end if;
+    return result;
+  end function bv_to_integer;
+
+  function integer_to_bv ( int : in integer;
+      	      	      	   length : in natural ) return bit_vector is
+
+    variable temp : integer;
+    variable result : bit_vector(length - 1 downto 0) := (others => '0');
+
+  begin
+    if int < 0 then
+      temp := - (int + 1);
+    else
+      temp := int;
+    end if;
+    for index in result'reverse_range loop
+      result(index) := bit'val( temp rem 2 );
+      temp := temp / 2;
+      exit when temp = 0;
+    end loop;
+    if int < 0 then
+      result := not result;
+      result(result'left) := '1';
+    end if;
+    return result;
+  end function integer_to_bv;
+
+  ----------------------------------------------------------------
+  --  Arithmetic operations
+  ----------------------------------------------------------------
+
+  procedure bv_add ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     overflow : out boolean ) is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv_result'length - 1 downto 0);
+    variable carry_in : bit;
+    variable carry_out : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_add: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        carry_in := carry_out;  -- of previous bit
+        result(index) := op1(index) xor op2(index) xor carry_in;
+        carry_out := (op1(index) and op2(index))
+                     or (carry_in and (op1(index) xor op2(index)));
+      end loop;
+      bv_result := result;
+      overflow := carry_out /= carry_in;
+    end if;
+  end procedure bv_add;
+
+  function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv1'length - 1 downto 0);
+    variable carry_in : bit;
+    variable carry_out : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report """+"": operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        carry_in := carry_out;  -- of previous bit
+        result(index) := op1(index) xor op2(index) xor carry_in;
+        carry_out := (op1(index) and op2(index))
+                     or (carry_in and (op1(index) xor op2(index)));
+      end loop;
+    end if;
+    return result;
+  end function "+";
+
+  procedure bv_sub ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     overflow : out boolean ) is
+
+    -- subtraction implemented by adding ((not bv2) + 1), ie -bv2
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv_result'length - 1 downto 0);
+    variable carry_in : bit;
+    variable carry_out : bit := '1';
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_sub: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        carry_in := carry_out;  -- of previous bit
+        result(index) := op1(index) xor (not op2(index)) xor carry_in;
+        carry_out := (op1(index) and (not op2(index)))
+                     or (carry_in and (op1(index) xor (not op2(index))));
+      end loop;
+      bv_result := result;
+      overflow := carry_out /= carry_in;
+    end if;
+  end procedure bv_sub;
+
+  function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    -- subtraction implemented by adding ((not bv2) + 1), ie -bv2
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv1'length - 1 downto 0);
+    variable carry_in : bit;
+    variable carry_out : bit := '1';
+
+  begin
+    if bv1'length /= bv2'length then
+      report """-"": operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        carry_in := carry_out;  -- of previous bit
+        result(index) := op1(index) xor (not op2(index)) xor carry_in;
+        carry_out := (op1(index) and (not op2(index)))
+                     or (carry_in and (op1(index) xor (not op2(index))));
+      end loop;
+    end if;
+    return result;
+  end function "-";
+
+  procedure bv_addu ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean ) is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv_result'length - 1 downto 0);
+    variable carry : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_addu: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        result(index) := op1(index) xor op2(index) xor carry;
+        carry := (op1(index) and op2(index))
+                 or (carry and (op1(index) xor op2(index)));
+      end loop;
+      bv_result := result;
+      overflow := carry = '1';
+    end if;
+  end procedure bv_addu;
+
+  function bv_addu ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv1'length - 1 downto 0);
+    variable carry : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report "bv_addu: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        result(index) := op1(index) xor op2(index) xor carry;
+        carry := (op1(index) and op2(index))
+                 or (carry and (op1(index) xor op2(index)));
+      end loop;
+    end if;
+    return result;
+  end function bv_addu;
+
+  procedure bv_subu ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean ) is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv_result'length - 1 downto 0);
+    variable borrow : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_subu: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        result(index) := op1(index) xor op2(index) xor borrow;
+        borrow := (not op1(index) and op2(index))
+                  or (borrow and not (op1(index) xor op2(index)));
+      end loop;
+      bv_result := result;
+      overflow := borrow = '1';
+    end if;
+  end procedure bv_subu;
+
+  function bv_subu ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    variable result : bit_vector(bv1'length - 1 downto 0);
+    variable borrow : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report "bv_subu: operands of different lengths"
+        severity failure;
+    else
+      for index in result'reverse_range loop
+        result(index) := op1(index) xor op2(index) xor borrow;
+        borrow := (not op1(index) and op2(index))
+                  or (borrow and not (op1(index) xor op2(index)));
+      end loop;
+    end if;
+    return result;
+  end function bv_subu;
+
+  procedure bv_neg ( bv : in bit_vector;
+                     bv_result : out bit_vector;
+                     overflow : out boolean ) is
+
+    constant zero : bit_vector(bv'range) := (others => '0');
+
+  begin
+    bv_sub( zero, bv, bv_result, overflow );
+  end procedure bv_neg;
+
+
+  function "-" ( bv : in bit_vector ) return bit_vector is
+
+    constant zero : bit_vector(bv'range) := (others => '0');
+
+  begin
+    return zero - bv;
+  end function "-";
+
+  procedure bv_mult ( bv1, bv2 : in bit_vector;
+      	       	      bv_result : out bit_vector;
+		      overflow : out boolean ) is
+
+    variable negative_result : boolean;
+    variable op1 : bit_vector(bv1'range) := bv1;
+    variable op2 : bit_vector(bv2'range) := bv2;
+    variable multu_result : bit_vector(bv1'range);
+    variable multu_overflow : boolean;
+    variable abs_min_int : bit_vector(bv1'range) := (others => '0');
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_mult: operands of different lengths"
+        severity failure;
+    else
+      abs_min_int(bv1'left) := '1';
+      negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
+      if op1(op1'left) = '1' then
+        op1 := - bv1;
+      end if;
+      if op2(op2'left) = '1' then
+        op2 := - bv2;
+      end if;
+      bv_multu(op1, op2, multu_result, multu_overflow);
+      if negative_result then
+        overflow := multu_overflow or (multu_result > abs_min_int);
+        bv_result := - multu_result;
+      else
+        overflow := multu_overflow or (multu_result(multu_result'left) = '1');
+        bv_result := multu_result;
+      end if;
+    end if;
+  end procedure bv_mult;
+
+  function "*" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    variable negative_result : boolean;
+    variable op1 : bit_vector(bv1'range) := bv1;
+    variable op2 : bit_vector(bv2'range) := bv2;
+    variable result : bit_vector(bv1'range);
+
+  begin
+    if bv1'length /= bv2'length then
+      report """*"": operands of different lengths"
+        severity failure;
+    else
+      negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
+      if op1(op1'left) = '1' then
+        op1 := - bv1;
+      end if;
+      if op2(op2'left) = '1' then
+        op2 := - bv2;
+      end if;
+      result := bv_multu(op1, op2);
+      if negative_result then
+        result := - result;
+      end if;
+    end if;
+    return result;
+  end function "*";
+
+  procedure bv_multu ( bv1, bv2 : in bit_vector;
+      	       	       bv_result : out bit_vector;
+		       overflow : out boolean ) is
+
+    alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
+    alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
+    constant len : natural := bv1'length;
+    constant accum_len : natural := len * 2;
+    variable accum : bit_vector(accum_len - 1 downto 0) := (others => '0');
+    constant zero : bit_vector(accum_len - 1 downto len):= (others => '0');
+    variable addu_overflow : boolean;
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_multu: operands of different lengths"
+        severity failure;
+    else
+      for count in 0 to len - 1 loop
+        if op2(count) = '1' then
+          bv_addu( accum(count + len - 1 downto count), op1,
+                   accum(count + len - 1 downto count), addu_overflow);
+          accum(count + len) := bit'val(boolean'pos(addu_overflow));
+        end if;
+      end loop;
+      bv_result := accum(len - 1 downto 0);
+      overflow := accum(accum_len-1 downto len) /= zero;
+    end if;
+  end procedure bv_multu;
+
+  function bv_multu ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    -- Use bv_multu with overflow detection, but ignore overflow flag
+
+    variable result : bit_vector(bv1'range);
+    variable tmp_overflow : boolean;
+
+  begin
+    bv_multu(bv1, bv2, result, tmp_overflow);
+    return result;
+  end function bv_multu;
+
+  procedure bv_div ( bv1, bv2 : in bit_vector;
+      	       	     bv_result : out bit_vector;
+		     div_by_zero : out boolean;
+                     overflow : out boolean ) is
+
+    --  Need overflow, in case divide b"10...0" (min_int) by -1
+    --  Don't use bv_to_int, in case size bigger than host machine!
+
+    variable negative_result : boolean;
+    variable op1 : bit_vector(bv1'range) := bv1;
+    variable op2 : bit_vector(bv2'range) := bv2;
+    variable divu_result : bit_vector(bv1'range);
+
+  begin
+    if bv1'length /= bv2'length or bv1'length /= bv_result'length then
+      report "bv_div: operands of different lengths"
+        severity failure;
+    else
+      negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
+      if op1(op1'left) = '1' then
+        op1 := - bv1;
+      end if;
+      if op2(op2'left) = '1' then
+        op2 := - bv2;
+      end if;
+      bv_divu(op1, op2, divu_result, div_by_zero);
+      if negative_result then
+        overflow := false;
+        bv_result := - divu_result;
+      else
+        overflow := divu_result(divu_result'left) = '1';
+        bv_result := divu_result;
+      end if;
+    end if;
+  end procedure bv_div;
+
+  function "/" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    variable negative_result : boolean;
+    variable op1 : bit_vector(bv1'range) := bv1;
+    variable op2 : bit_vector(bv2'range) := bv2;
+    variable result : bit_vector(bv1'range);
+
+  begin
+    if bv1'length /= bv2'length then
+      report """/"": operands of different lengths"
+        severity failure;
+    else
+      negative_result := (op1(op1'left) = '1') xor (op2(op2'left) = '1');
+      if op1(op1'left) = '1' then
+        op1 := - bv1;
+      end if;
+      if op2(op2'left) = '1' then
+        op2 := - bv2;
+      end if;
+      result := bv_divu(op1, op2);
+      if negative_result then
+        result := - result;
+      end if;
+    end if;
+    return result;
+  end function "/";
+
+  procedure bv_divu ( bv1, bv2 : in bit_vector;
+      	       	      bv_quotient : out bit_vector;
+		      bv_remainder : out bit_vector;
+		      div_by_zero : out boolean ) is
+
+    constant len : natural := bv1'length;
+    constant zero_divisor : bit_vector(len-1 downto 0) := (others => '0');
+    alias dividend : bit_vector(bv1'length-1 downto 0) is bv1;
+    variable divisor : bit_vector(bv2'length downto 0) := '0' & bv2;
+    variable quotient : bit_vector(len-1 downto 0);
+    variable remainder : bit_vector(len downto 0) := (others => '0');
+    variable ignore_overflow  : boolean;
+
+  begin
+    if bv1'length /= bv2'length
+      or bv1'length /= bv_quotient'length or bv1'length /= bv_remainder'length then
+      report "bv_divu: operands of different lengths"
+        severity failure;
+    else
+      --  check for zero divisor
+      if bv2 = zero_divisor then
+        div_by_zero := true;
+        return;
+      end if;
+      --  perform division
+      for iter in len-1 downto 0 loop
+        if remainder(len) = '0' then
+          remainder := remainder sll 1;
+          remainder(0) := dividend(iter);
+          bv_sub(remainder, divisor, remainder, ignore_overflow);
+        else
+          remainder := remainder sll 1;
+          remainder(0) := dividend(iter);
+          bv_add(remainder, divisor, remainder, ignore_overflow);
+        end if;
+        quotient(iter) := not remainder(len);
+      end loop;
+      if remainder(len) = '1' then
+        bv_add(remainder, divisor, remainder, ignore_overflow);
+      end if;
+      bv_quotient := quotient;
+      bv_remainder := remainder(len - 1 downto 0);
+      div_by_zero := false;
+    end if;
+  end procedure bv_divu;
+
+  procedure bv_divu ( bv1, bv2 : in bit_vector;
+      	       	      bv_quotient : out bit_vector;
+		      div_by_zero : out boolean ) is
+
+    variable ignore_remainder : bit_vector(bv_quotient'range);
+
+  begin
+    bv_divu(bv1, bv2, bv_quotient, ignore_remainder, div_by_zero);
+  end procedure bv_divu;
+
+  function bv_divu ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    variable result : bit_vector(bv1'range);
+    variable tmp_div_by_zero : boolean;
+
+  begin
+    bv_divu(bv1, bv2, result, tmp_div_by_zero);
+    return result;
+  end function bv_divu;
+
+  ----------------------------------------------------------------
+  --  Arithmetic comparison operators.
+  --  Perform comparisons on bit vector encoded signed integers.
+  --  (For unsigned integers, built in lexical comparison does
+  --  the required operation.)
+  ----------------------------------------------------------------
+
+  function bv_lt ( bv1, bv2 : in bit_vector ) return boolean is
+
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+
+  begin
+    assert bv1'length = bv2'length
+      report "bv_lt: operands of different lengths"
+      severity failure;
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return tmp1 < tmp2;
+  end function bv_lt;
+
+  function bv_le ( bv1, bv2 : in bit_vector ) return boolean is
+
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+
+  begin
+    assert bv1'length = bv2'length
+      report "bv_le: operands of different lengths"
+      severity failure;
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return tmp1 <= tmp2;
+  end function bv_le;
+
+  function bv_gt ( bv1, bv2 : in bit_vector ) return boolean is
+
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+
+  begin
+    assert bv1'length = bv2'length
+      report "bv_gt: operands of different lengths"
+      severity failure;
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return tmp1 > tmp2;
+  end function bv_gt;
+
+  function bv_ge ( bv1, bv2 : in bit_vector ) return boolean is
+
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+
+  begin
+    assert bv1'length = bv2'length
+      report "bv_ged: operands of different lengths"
+      severity failure;
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return tmp1 >= tmp2;
+  end function bv_ge;
+
+  ----------------------------------------------------------------
+  --  Extension operators - convert a bit vector to a longer one
+  ----------------------------------------------------------------
+
+  function bv_sext ( bv : in bit_vector;
+      	      	     length : in natural ) return bit_vector is
+
+    alias bv_norm : bit_vector(bv'length - 1 downto 0) is bv;
+    variable result : bit_vector(length - 1 downto 0) := (others => bv(bv'left));
+    variable src_length : natural := bv'length;
+
+  begin
+    if src_length > length then
+      src_length := length;
+    end if;
+    result(src_length - 1 downto 0) := bv_norm(src_length - 1 downto 0);
+    return result;
+  end function bv_sext;
+
+  function bv_zext ( bv : in bit_vector;
+      	      	     length : in natural ) return bit_vector is
+
+    alias bv_norm : bit_vector(bv'length - 1 downto 0) is bv;
+    variable result : bit_vector(length - 1 downto 0) := (others => '0');
+    variable src_length : natural := bv'length;
+
+  begin
+    if src_length > length then
+      src_length := length;
+    end if;
+    result(src_length - 1 downto 0) := bv_norm(src_length - 1 downto 0);
+    return result;
+  end function bv_zext;
+
+end package body bv_arithmetic;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/bv_images.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/bv_images.vhd
new file mode 100644
index 0000000..435d504
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/bv_images.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bv_images.vhd,v 1.2 2001-10-25 01:24:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+--------------------------------------------------------------------------
+--
+--  bv_images package specification.
+--
+--  Functions that return the string image of values.
+--  Each image is a correctly formed literal according to the
+--  rules of VHDL-93.
+--
+--------------------------------------------------------------------------
+
+package bv_images is
+
+  -- Image of bit vector as binary bit string literal
+  -- (in the format B"...")
+  -- Length of result is bv'length + 3
+
+  function image (bv : in bit_vector) return string;
+
+  -- Image of bit vector as octal bit string literal
+  -- (in the format O"...")
+  -- Length of result is (bv'length+2)/3 + 3
+
+  function image_octal (bv : in bit_vector) return string;
+
+  -- Image of bit vector as hex bit string literal
+  -- (in the format X"...")
+  -- Length of result is (bv'length+3)/4 + 3
+
+  function image_hex (bv : in bit_vector) return string;
+
+end bv_images;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/bv_images_body.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/bv_images_body.vhd
new file mode 100644
index 0000000..285bb55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/bv_images_body.vhd
@@ -0,0 +1,168 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bv_images_body.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+--------------------------------------------------------------------------
+--
+--  bv_images package body.
+--
+--  Functions that return the string image of values.
+--  Each image is a correctly formed literal according to the
+--  rules of VHDL-93.
+--
+--------------------------------------------------------------------------
+
+package body bv_images is
+
+
+  -- Image of bit vector as binary bit string literal
+  -- (in the format B"...")
+  -- Length of result is bv'length + 3
+
+  function image (bv : in bit_vector) return string is
+
+    alias bv_norm : bit_vector(1 to bv'length) is bv;
+    variable result : string(1 to bv'length + 3);
+
+  begin
+    result(1) := 'B';
+    result(2) := '"';
+    for index in bv_norm'range loop
+      if bv_norm(index) = '0' then
+        result(index + 2) := '0';
+      else
+        result(index + 2) := '1';
+      end if;
+    end loop;
+    result(bv'length + 3) := '"';
+    return result;
+  end image;
+
+  ----------------------------------------------------------------
+
+  -- Image of bit vector as octal bit string literal
+  -- (in the format O"...")
+  -- Length of result is (bv'length+2)/3 + 3
+
+  function image_octal (bv : in bit_vector) return string is
+
+    constant nr_digits : natural := (bv'length + 2) / 3;
+    variable result : string(1 to nr_digits + 3);
+    variable bits : bit_vector(0 to 3*nr_digits - 1) := (others => '0');
+    variable three_bits : bit_vector(0 to 2);
+    variable digit : character;
+
+  begin
+    result(1) := 'O';
+    result(2) := '"';
+    bits(bits'right - bv'length + 1 to bits'right) := bv;
+    for index in 0 to nr_digits - 1 loop
+      three_bits := bits(3*index to 3*index + 2);
+      case three_bits is
+	when b"000" =>
+	  digit := '0';
+	when b"001" =>
+	  digit := '1';
+	when b"010" =>
+	  digit := '2';
+	when b"011" =>
+	  digit := '3';
+	when b"100" =>
+	  digit := '4';
+	when b"101" =>
+	  digit := '5';
+	when b"110" =>
+	  digit := '6';
+	when b"111" =>
+	  digit := '7';
+      end case;
+      result(index + 3) := digit;
+    end loop;
+    result(nr_digits + 3) := '"';
+    return result;
+  end image_octal;
+
+  ----------------------------------------------------------------
+
+  -- Image of bit vector as hex bit string literal
+  -- (in the format X"...")
+  -- Length of result is (bv'length+3)/4 + 3
+
+  function image_hex (bv : in bit_vector) return string is
+
+    constant nr_digits : natural := (bv'length + 3) / 4;
+    variable result : string(1 to nr_digits + 3);
+    variable bits : bit_vector(0 to 4*nr_digits - 1) := (others => '0');
+    variable four_bits : bit_vector(0 to 3);
+    variable digit : character;
+
+  begin
+    result(1) := 'X';
+    result(2) := '"';
+    bits(bits'right - bv'length + 1 to bits'right) := bv;
+    for index in 0 to nr_digits - 1 loop
+      four_bits := bits(4*index to 4*index + 3);
+      case four_bits is
+	when b"0000" =>
+	  digit := '0';
+	when b"0001" =>
+	  digit := '1';
+	when b"0010" =>
+	  digit := '2';
+	when b"0011" =>
+	  digit := '3';
+	when b"0100" =>
+	  digit := '4';
+	when b"0101" =>
+	  digit := '5';
+	when b"0110" =>
+	  digit := '6';
+	when b"0111" =>
+	  digit := '7';
+	when b"1000" =>
+	  digit := '8';
+	when b"1001" =>
+	  digit := '9';
+	when b"1010" =>
+	  digit := 'A';
+	when b"1011" =>
+	  digit := 'B';
+	when b"1100" =>
+	  digit := 'C';
+	when b"1101" =>
+	  digit := 'D';
+	when b"1110" =>
+	  digit := 'E';
+	when b"1111" =>
+	  digit := 'F';
+      end case;
+      result(index + 3) := digit;
+    end loop;
+    result(nr_digits + 3) := '"';
+    return result;
+  end image_hex;
+
+
+end bv_images;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_07.vhd
new file mode 100644
index 0000000..557661e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_07.vhd
@@ -0,0 +1,30 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_07.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity reg4 is
+  port ( d0, d1, d2, d3, en, clk : in bit;
+         q0, q1, q2, q3 : out  bit );
+end entity reg4;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd
new file mode 100644
index 0000000..cfd5862
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_08.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behav of reg4 is
+begin
+
+  storage : process is
+                      variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
+  begin 
+    if en = '1' and clk = '1' then
+      stored_d0 := d0;
+      stored_d1 := d1;
+      stored_d2 := d2;
+      stored_d3 := d3;
+    end if;
+    q0 <= stored_d0 after 5 ns;
+    q1 <= stored_d1 after 5 ns;
+    q2 <= stored_d2 after 5 ns;
+    q3 <= stored_d3 after 5 ns;
+    wait on d0, d1, d2, d3, en, clk;
+  end process storage;
+
+end architecture behav;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_10.vhd
new file mode 100644
index 0000000..6f53a63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_10.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_10.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity d_latch is
+  port ( d, clk : in bit;  q : out bit );
+end d_latch;
+
+
+entity and2 is
+  port ( a, b : in bit;  y : out bit );
+end and2;
+
+
+architecture basic of d_latch is
+begin
+
+  latch_behavior : process is
+  begin
+    if clk = '1' then
+      q <= d after 2 ns;
+    end if;
+    wait on clk, d;
+  end process latch_behavior;
+
+end architecture basic;
+
+
+architecture basic of and2 is
+begin
+
+  and2_behavior : process is
+  begin
+    y <= a and b after 2 ns;
+    wait on a, b;
+  end process and2_behavior;
+
+end architecture basic;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_11.vhd
new file mode 100644
index 0000000..2ab34ce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_11.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_11.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture struct of reg4 is
+
+  signal int_clk : bit;
+
+begin
+
+  bit0 : entity work.d_latch(basic)
+    port map (d0, int_clk, q0);
+  bit1 : entity work.d_latch(basic)
+    port map (d1, int_clk, q1);
+  bit2 : entity work.d_latch(basic)
+    port map (d2, int_clk, q2);
+  bit3 : entity work.d_latch(basic)
+    port map (d3, int_clk, q3);
+
+  gate : entity work.and2(basic)
+    port map (en, clk, int_clk);
+
+end architecture struct;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_13.vhd
new file mode 100644
index 0000000..9925044
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_fg_01_13.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_fg_01_13.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench is
+end entity test_bench;
+
+architecture test_reg4 of test_bench is
+
+  signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
+
+begin
+
+  dut : entity work.reg4(behav)
+    port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );
+
+  stimulus : process is
+  begin
+    d0 <= '1';  d1 <= '1';  d2 <= '1';  d3 <= '1';
+    en <= '0';  clk <= '0';
+    wait for 20 ns;
+    en <= '1';  wait for 20 ns;
+    clk <= '1';  wait for 20 ns;
+    d0 <= '0';  d1 <= '0';  d2 <= '0';  d3 <= '0';  wait for 20 ns;
+    en <= '0';  wait for 20 ns;
+    -- . . .
+    wait;
+  end process stimulus;
+
+end architecture test_reg4;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_01.vhd
new file mode 100644
index 0000000..a1e2fcc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_01.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_tb_01_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_01_01 is
+
+end entity test_bench_01_01;
+
+architecture test_reg4_behav of test_bench_01_01 is
+
+  signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
+
+begin
+
+  dut : entity work.reg4(behav)
+    port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
+               q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
+
+  stimulus : process is
+  begin
+    wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("1010");	wait for 20 ns;
+    en <= '1';					wait for 20 ns;
+    clk <= '1';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("0101");	wait for 20 ns;
+    clk <= '0';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("0000");	wait for 20 ns;
+    en <= '1';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("1111");	wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_reg4_behav;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_02.vhd
new file mode 100644
index 0000000..e33d48f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_02.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_tb_01_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_01_02 is
+
+end entity test_bench_01_02;
+
+architecture test_reg4_struct of test_bench_01_02 is
+
+  signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;
+
+begin
+
+  dut : entity work.reg4(struct)
+    port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
+               q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
+
+  stimulus : process is
+  begin
+    wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("1010");	wait for 20 ns;
+    en <= '1';					wait for 20 ns;
+    clk <= '1';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("0101");	wait for 20 ns;
+    clk <= '0';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("0000");	wait for 20 ns;
+    en <= '1';					wait for 20 ns;
+    (d0, d1, d2, d3) <= bit_vector'("1111");	wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_reg4_struct;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_03.vhd
new file mode 100644
index 0000000..a20ad20
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_01_tb_01_03.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_01_tb_01_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity shift_adder is
+  port ( addend : in integer;  augend : in integer;
+  sum : out integer;
+  add_control : in bit );
+end entity shift_adder;
+
+architecture behavior of shift_adder is
+begin
+end architecture behavior;
+
+------------------------------------------------------------------------
+
+entity reg is
+  port ( d : in integer;  q : out integer;
+  en : in bit;  reset : in bit );
+end entity reg;
+
+architecture behavior of reg is
+begin
+end architecture behavior;
+
+------------------------------------------------------------------------
+
+entity shift_reg is
+  port ( d : in integer;  q : out bit;
+  load : in bit;  clk : in bit );
+end entity shift_reg;
+
+architecture behavior of shift_reg is
+begin
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_fg_02_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_fg_02_01.vhd
new file mode 100644
index 0000000..0358642
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_fg_02_01.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_02_fg_02_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture sample of ent is
+
+  constant pi : real := 3.14159;
+
+begin
+
+  process is
+            variable counter : integer;
+  begin
+    -- . . .         --  statements using pi and counter
+  end process;
+
+end architecture sample;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_tb_02_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_tb_02_01.vhd
new file mode 100644
index 0000000..226a855
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_02_tb_02_01.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_02_tb_02_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ent is
+
+end entity ent;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_01.vhd
new file mode 100644
index 0000000..c200d1b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_01.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_01.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_01 is
+end entity ch_03_01;
+
+architecture test of ch_03_01 is
+
+  signal en : bit := '0';
+  signal data_in : integer := 0;
+
+begin
+
+  process_3_1_a : process (en, data_in) is
+
+                                          variable stored_value : integer := 0;
+
+  begin
+
+    -- code from book:
+
+    if en = '1' then
+      stored_value := data_in;
+    end if;
+
+    -- end of code from book
+
+  end process process_3_1_a;
+
+  stimulus : process is
+  begin
+    en <= '1' after 10 ns, '0' after 20 ns;
+    data_in <= 1 after 5 ns, 2 after 15 ns, 3 after 25 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_02.vhd
new file mode 100644
index 0000000..b05946f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_02.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_02.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_02 is
+end entity ch_03_02;
+
+architecture test of ch_03_02 is
+
+  signal sel : integer range 0 to 1 := 0;
+  signal input_0 : integer := 0;
+  signal input_1 : integer := 10;
+  signal result : integer;
+
+begin
+
+  process_3_1_b : process (sel, input_0, input_1) is
+  begin
+
+    -- code from book:
+
+    if sel = 0 then
+      result <= input_0;  -- executed if sel = 0
+    else
+      result <= input_1;  -- executed if sel /= 0
+    end if;
+
+    -- end of code from book
+
+  end process process_3_1_b;
+
+  stimulus : process is
+  begin
+    sel <= 1 after 40 ns;
+    input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
+    input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_03.vhd
new file mode 100644
index 0000000..3882ce1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_03.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_03 is
+end entity ch_03_03;
+
+architecture test of ch_03_03 is
+begin
+
+  process_3_1_c : process is
+
+                            type mode_type is (immediate, other_mode);
+                          type opcode_type is (load, add, subtract, other_opcode);
+
+                          variable mode : mode_type;
+                          variable opcode : opcode_type;
+                          constant immed_operand : integer := 1;
+                          constant memory_operand : integer := 2;
+                          constant address_operand : integer := 3;
+                          variable operand : integer;
+
+                          procedure procedure_3_1_c is
+                          begin
+
+                            -- code from book:
+
+                            if mode = immediate then
+                              operand := immed_operand;
+                            elsif opcode = load or opcode = add or opcode = subtract then
+                              operand := memory_operand;
+                            else
+                              operand := address_operand;
+                            end if;
+
+                            -- end of code from book
+
+                          end procedure_3_1_c;
+
+  begin
+    mode := immediate;
+    procedure_3_1_c;
+
+    mode := other_mode;
+    opcode := load;
+    procedure_3_1_c;
+
+    opcode := add;
+    procedure_3_1_c;
+
+    opcode := subtract;
+    procedure_3_1_c;
+
+    opcode := other_opcode;
+    procedure_3_1_c;
+
+    wait;
+  end process process_3_1_c;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_04.vhd
new file mode 100644
index 0000000..439e463
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_04.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_04 is
+end entity ch_03_04;
+
+architecture test of ch_03_04 is
+
+  type opcode_type is (opcode_1, opcode_2, halt_opcode);
+  signal opcode : opcode_type := opcode_1;
+
+  signal halt_indicator : boolean := false;
+
+begin
+
+  process_3_1_d : process (opcode) is
+
+                                     variable PC : integer := 0;
+                                   constant effective_address : integer := 1;
+                                   variable executing : boolean := true;
+
+  begin
+
+    -- code from book:
+
+    if opcode = halt_opcode then
+      PC := effective_address;
+      executing := false;
+      halt_indicator <= true;
+    end if;
+
+    -- end of code from book
+
+  end process process_3_1_d;
+
+  stimulus : process is
+  begin
+    opcode <= opcode_2 after 100 ns, halt_opcode after 200 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_05.vhd
new file mode 100644
index 0000000..506ef5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_05.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_05.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_05 is
+end entity ch_03_05;
+
+architecture test of ch_03_05 is
+
+  type phase_type is (wash, other_phase);
+  signal phase : phase_type := other_phase;
+
+  type cycle_type is (delicate_cycle, other_cycle);
+  signal cycle_select : cycle_type := delicate_cycle;
+
+  type speed_type is (slow, fast);
+  signal agitator_speed : speed_type := slow;
+
+  signal agitator_on : boolean := false;
+
+begin
+
+  process_3_1_e : process (phase, cycle_select) is
+  begin
+
+    -- code from book:
+
+    if phase = wash then
+      if cycle_select = delicate_cycle then
+        agitator_speed <= slow;
+      else
+        agitator_speed <= fast;
+      end if;
+      agitator_on <= true;
+    end if;
+
+    -- end of code from book
+
+  end process process_3_1_e;
+
+  stimulus : process is
+  begin
+    cycle_select <= other_cycle;	wait for 100 ns;
+    phase <= wash;			wait for 100 ns;
+    cycle_select <= delicate_cycle;	wait for 100 ns;
+    cycle_select <= other_cycle;	wait for 100 ns;
+    phase <= other_phase;		wait for 100 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_06.vhd
new file mode 100644
index 0000000..49e2db4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_06.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_06.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_06 is
+end entity ch_03_06;
+
+architecture test of ch_03_06 is
+
+  -- code from book:
+  
+  type alu_func is (pass1, pass2, add, subtract);
+  
+  -- end of code from book
+  
+  signal func : alu_func := pass1;
+  signal operand1 : integer := 10;
+  signal operand2 : integer := 3;
+
+begin
+
+  process_03_2_a : process (func, operand1, operand2) is
+
+                                                        variable result : integer := 0;
+
+  begin
+
+    -- code from book:
+
+    case func is
+      when pass1 =>
+        result := operand1;
+      when pass2 =>
+        result := operand2;
+      when add =>
+        result := operand1 + operand2;
+      when subtract =>
+        result := operand1 - operand2;
+    end case;
+
+    -- end of code from book
+
+  end process process_03_2_a;
+
+  stimulus : process is
+  begin
+    func <= pass2 after 10 ns,
+	    add after 20 ns,
+	    subtract after 30 ns;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_07.vhd
new file mode 100644
index 0000000..cdc0639
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_07.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_07 is
+end entity ch_03_07;
+
+architecture test of ch_03_07 is
+begin
+
+  process_03_2_b : process is
+
+                             -- code from book:
+
+                             subtype index_mode is integer range 0 to 3;
+
+                           variable instruction_register : integer range 0 to 2**16 - 1;
+
+                           -- end of code from book
+
+                           variable index_value : integer;
+                           constant accumulator_A : integer := 1;
+                           constant accumulator_B : integer := 2;
+                           constant index_register : integer := 3;
+
+  begin
+
+    for i in index_mode loop
+      instruction_register := i * 2**12;
+
+      -- code from book:
+
+      case index_mode'((instruction_register / 2**12) rem 2**2) is
+        when 0 =>
+          index_value := 0;
+        when 1 =>
+          index_value := accumulator_A;
+        when 2 =>
+          index_value := accumulator_B;
+        when 3 =>
+          index_value := index_register;
+      end case;
+
+      -- end of code from book
+
+    end loop;
+
+    wait;
+  end process process_03_2_b;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_08.vhd
new file mode 100644
index 0000000..d81c77d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_08.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_08.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_08 is
+end entity ch_03_08;
+
+architecture test of ch_03_08 is
+begin
+
+  process_03_2_c : process is
+
+                             -- code from book:
+
+                             type opcodes is
+                           (nop, add, subtract, load, store, jump, jumpsub, branch, halt);
+
+                           subtype control_transfer_opcodes is opcodes range jump to branch;
+
+                           -- end of code from book
+
+                           variable opcode : opcodes;
+                           variable operand : integer;
+                           constant memory_operand : integer := 1;
+                           constant address_operand : integer := 2;
+
+  begin
+
+    for i in opcodes loop
+      opcode := i;
+
+      -- code from book:
+
+      case opcode is
+        when load | add | subtract =>
+          operand := memory_operand;
+        when store | jump | jumpsub | branch =>
+          operand := address_operand;
+        when others =>
+          operand := 0;
+      end case;
+
+      --
+
+      case opcode is
+        when add to load =>
+          operand := memory_operand;
+        when branch downto store =>
+          operand := address_operand;
+        when others =>
+          operand := 0;
+      end case;
+
+      -- end of code from book
+
+      case opcode is
+        when add to load =>
+          operand := memory_operand;
+          -- code from book: (MTI bug mt011)
+          -- when control_transfer_opcodes | store =>
+          --   operand := address_operand;
+          -- end of code from book
+        when others =>
+          operand := 0;
+      end case;
+
+    end loop;
+
+    wait;
+  end process process_03_2_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_10.vhd
new file mode 100644
index 0000000..36b7a48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_10.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_10.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_10 is
+end entity ch_03_10;
+
+architecture test of ch_03_10 is
+
+  type opcode_type is (nop, add, subtract);
+
+  signal opcode : opcode_type := nop;
+
+begin
+
+  process_3_3_a : process (opcode) is
+
+                                     variable Acc : integer := 0;
+                                   constant operand : integer := 1;
+
+  begin
+
+    -- code from book:
+
+    case opcode is
+      when add =>
+        Acc := Acc + operand;
+      when subtract =>
+        Acc := Acc - operand;
+      when nop =>
+        null;
+    end case;
+
+    -- end of code from book
+
+  end process process_3_3_a;
+
+  stimulus : process is
+  begin
+    opcode <= add after 10 ns, subtract after 20 ns, nop after 30 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_11.vhd
new file mode 100644
index 0000000..3bce6fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_11.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_11.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_11 is
+end entity ch_03_11;
+
+architecture test of ch_03_11 is
+
+  signal sensitivity_list : bit := '0';
+
+begin
+
+  -- code from book:
+
+  -- make "sensitivity_list" roman italic
+  control_section : process ( sensitivity_list ) is
+  begin
+    null;
+  end process control_section;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    sensitivity_list <= '1' after 10 ns, '0' after 20 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_12.vhd
new file mode 100644
index 0000000..4583ac9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_12.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_12.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_12 is
+end entity ch_03_12;
+
+architecture test of ch_03_12 is
+begin
+
+  process_3_4_a : process is
+
+                            constant condition, condition_1,
+                          condition_2, condition_3 : boolean := true;
+                          variable index : integer;
+
+  begin
+
+    -- code from book: syntax check only
+
+    -- change "condition" to roman italic
+
+    -- not in book:
+    loop
+      -- end not in book
+
+      if condition then
+        exit;
+      end if;
+
+      -- not in book:
+    end loop;
+    -- end not in book
+
+    --
+
+    -- change "condition" to roman italic
+
+    loop
+      -- . . .
+      exit when condition;
+      -- . . .
+    end loop;
+    -- . . .      -- control transferred to here
+    -- when condition becomes true within the loop
+
+    --
+
+    loop_name : loop
+      -- . . .
+      exit loop_name;
+      -- . . .
+    end loop loop_name ;
+
+    --
+
+    -- change conditions to roman italic with hyphens
+
+    outer : loop
+      -- . . .
+      inner : loop
+        -- . . .
+        exit outer when condition_1; -- exit 1
+        -- . . .
+        exit when condition_2;       -- exit 2
+        -- . . .
+      end loop inner;
+      -- . . .                      -- target A
+      exit outer when condition_3;   -- exit 3
+      -- . . .
+    end loop outer;
+    -- . . .                        -- target B
+
+    --
+
+    -- "statement..." in roman italic with hyphens
+
+    loop
+      -- statement_1;
+      next when condition;
+      -- statement_2;
+    end loop;
+
+    --
+
+    -- "statement..." in roman italic with hyphens
+
+    loop
+      -- statement_1;
+      if not condition then
+        -- statement_2;
+      end if;
+    end loop;
+
+    --
+
+    while index > 0 loop
+      -- . . .      -- statement A: do something with index
+    end loop;
+    -- . . .    -- statement B
+
+
+    -- end of code from book
+
+    wait;
+  end process process_3_4_a;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_13.vhd
new file mode 100644
index 0000000..d06e8c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_13.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_13.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_13 is
+end entity ch_03_13;
+
+architecture test of ch_03_13 is
+
+  signal count_out : integer;
+
+begin
+
+  process_3_4_b : process is
+  begin
+
+    -- code from book:
+
+    for count_value in 0 to 127 loop
+      count_out <= count_value;
+      wait for 5 ns;
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_4_b;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_14.vhd
new file mode 100644
index 0000000..4d03128
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_14.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_14.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_14 is
+end entity ch_03_14;
+
+architecture test of ch_03_14 is
+
+  -- code from book:
+
+  type controller_state is (initial, idle, active, error);
+
+  -- end of code from book
+
+  signal current_state : controller_state := initial;
+
+begin
+
+  process_3_4_c : process is
+  begin
+
+    -- code from book:
+
+    for state in controller_state loop
+      -- . . .
+      -- not in book:
+      current_state <= state;
+      wait for 10 ns;
+      -- end not in book
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_4_c;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_16.vhd
new file mode 100644
index 0000000..0974eda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_16.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_16.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_16 is
+end entity ch_03_16;
+
+architecture test of ch_03_16 is
+begin
+
+  -- code from book:
+
+  hiding_example : process is
+                             variable a, b : integer;
+  begin
+    a := 10;
+    for a in 0 to 7 loop
+      b := a;
+    end loop;
+    -- a = 10, and b = 7
+    -- . . .
+    -- not in book:
+    wait;
+    -- end not in book
+  end process hiding_example;
+
+  -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_17.vhd
new file mode 100644
index 0000000..fe89441
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_17.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_17.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_17 is
+end entity ch_03_17;
+
+architecture test of ch_03_17 is
+begin
+
+  process_3_4_f : process is
+  begin
+
+    -- code from book:
+
+    for i in 10 to 1 loop
+      -- . . .
+    end loop;
+
+    for i in 10 downto 1 loop
+      -- . . .
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_4_f;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_18.vhd
new file mode 100644
index 0000000..b5c1e34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_18.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_18.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_18 is
+end entity ch_03_18;
+
+architecture test of ch_03_18 is
+begin
+
+  process_3_5_a : process is
+
+                            constant initial_value : natural := 10;
+                          constant max_value : natural := 8;
+                          constant current_character : character := 'A';
+                          constant input_string : string := "012ABC";
+                          constant free_memory : natural := 0;
+                          constant low_water_limit : natural := 1024;
+                          constant packet_length : natural := 0;
+                          constant clock_pulse_width : delay_length := 10 ns;
+                          constant min_clock_width : delay_length := 20 ns;
+                          constant last_position : natural := 10;
+                          constant first_position : natural := 5;
+                          constant number_of_entries : natural := 0;
+
+  begin
+
+    -- code from book:
+
+    assert initial_value <= max_value;
+
+    --
+
+    assert initial_value <= max_value
+                            report "initial value too large";
+
+    --
+
+    assert current_character >= '0' and current_character <= '9'
+                                                             report "Input number " & input_string & " contains a non-digit";
+
+    --
+
+    assert free_memory >= low_water_limit
+      report "low on memory, about to start garbage collect"
+      severity note;
+
+    --
+
+    assert packet_length /= 0
+      report "empty network packet received"
+      severity warning;
+
+    --
+
+    assert clock_pulse_width >= min_clock_width
+      severity error;
+
+    --
+
+    assert (last_position - first_position + 1) = number_of_entries
+      report "inconsistency in buffer model"
+      severity failure;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_5_a;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_19.vhd
new file mode 100644
index 0000000..0cfa747
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_19.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_19.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_19 is
+end entity ch_03_19;
+
+architecture test of ch_03_19 is
+
+  subtype data_type is integer;
+
+  signal transmit_data : data_type := 0;
+
+begin
+
+  -- code from book:
+  
+  transmit_element : process (transmit_data) is
+                                               -- . . .      -- variable declarations
+  begin
+    report "transmit_element: data = "
+      & data_type'image(transmit_data);
+    -- . . .
+  end process transmit_element;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    transmit_data <= 10 after 10 ns, 20 after 20 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_20.vhd
new file mode 100644
index 0000000..e94699f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_20.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_20.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_20 is
+end entity ch_03_20;
+
+architecture test of ch_03_20 is
+begin
+
+  process_3_5_c : process is
+  begin
+
+    -- code from book:
+
+    assert false
+      report "Initialization complete" severity note;
+
+    --
+
+    report "Initialization complete";
+
+    -- end of code from book
+
+    wait;
+  end process process_3_5_c;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_01.vhd
new file mode 100644
index 0000000..68f3bb5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_01.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity thermostat is
+  port ( desired_temp, actual_temp : in integer;
+         heater_on : out boolean );
+end entity thermostat;
+
+architecture example of thermostat is
+begin
+
+  controller : process (desired_temp, actual_temp) is
+  begin
+    if actual_temp < desired_temp - 2 then
+      heater_on <= true;
+    elsif actual_temp > desired_temp + 2 then
+      heater_on <= false;
+    end if;
+  end process controller;
+
+end architecture example;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_02.vhd
new file mode 100644
index 0000000..d7efef6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_02.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_02.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- test code:
+
+use work.test_bench_03_02.all;
+
+-- end test code
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity mux4 is
+                 port ( sel : in sel_range;
+                        d0, d1, d2, d3 : in std_ulogic;
+                        z : out std_ulogic );
+               end entity mux4;
+
+               architecture demo of mux4 is
+               begin
+
+                 out_select : process (sel, d0, d1, d2, d3) is
+                 begin
+                   case sel is
+                     when 0 => 
+                       z <= d0;
+                     when 1 => 
+                       z <= d1;
+                     when 2 => 
+                       z <= d2;
+                     when 3 => 
+                       z <= d3;
+                   end case;
+                 end process out_select;
+
+               end architecture demo;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_03.vhd
new file mode 100644
index 0000000..b1b8053
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_03.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity counter is
+  port ( clk : in bit;  count : out natural );
+end entity counter;
+
+architecture behavior of counter is
+begin
+
+  incrementer : process is
+                          variable count_value : natural := 0;
+  begin
+    count <= count_value;
+    loop
+      wait until clk = '1';
+      count_value := (count_value + 1) mod 16;
+      count <= count_value;
+    end loop;
+  end process incrementer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_04.vhd
new file mode 100644
index 0000000..25ffb55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_04.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity counter is
+  port ( clk, reset : in bit;  count : out natural );
+end entity counter;
+
+architecture behavior of counter is
+begin
+
+  incrementer : process is
+                          variable count_value : natural := 0;
+  begin
+    count <= count_value;
+    loop
+      loop
+        wait until clk = '1' or reset = '1';
+        exit when reset = '1';
+        count_value := (count_value + 1) mod 16;
+        count <= count_value;
+      end loop;
+      -- at this point, reset = '1'
+      count_value := 0;
+      count <= count_value;
+      wait until reset = '0';
+    end loop;
+  end process incrementer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_05.vhd
new file mode 100644
index 0000000..773bd6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_05.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_05.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity cos is
+  port ( theta : in real;  result : out real );
+end entity cos;
+
+architecture series of cos is
+begin
+
+  summation : process (theta) is
+                                variable sum, term : real;
+                              variable n : natural;
+  begin
+    sum := 1.0;
+    term := 1.0;
+    n := 0;
+    while abs term > abs (sum / 1.0E6) loop
+      n := n + 2;
+      term := (-term) * theta**2 / real(((n-1) * n));
+      sum := sum + term;
+    end loop;
+    result <= sum;
+  end process summation;
+
+end architecture series;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_06.vhd
new file mode 100644
index 0000000..5536560
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_06.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture fixed_length_series of cos is
+begin
+
+  summation : process (theta) is
+                                variable sum, term : real;
+  begin
+    sum := 1.0;
+    term := 1.0;
+    for n in 1 to 9 loop
+      term := (-term) * theta**2 / real(((2*n-1) * 2*n));
+      sum := sum + term;
+    end loop;
+    result <= sum;
+  end process summation;
+
+end architecture fixed_length_series;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_07.vhd
new file mode 100644
index 0000000..3460c94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_07.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity SR_flipflop is
+  port ( S, R : in bit;  Q : out bit );
+end entity SR_flipflop;
+
+architecture checking of SR_flipflop is
+begin
+
+  set_reset : process (S, R) is
+  begin
+    assert S = '1' nand R = '1';
+    if S = '1' then
+      Q <= '1';
+    end if;
+    if R = '1' then
+      Q <= '0';
+    end if;
+  end process set_reset;
+
+end architecture checking;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_08.vhd
new file mode 100644
index 0000000..23e8738
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_08.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_08.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity max3 is
+  port ( a, b, c : in integer;  z : out integer );
+end entity max3;
+
+architecture check_error of max3 is
+begin
+
+  maximizer : process (a, b, c)
+    variable result : integer;
+  begin
+    if a > b then
+      if a > c then
+        result := a;
+      else
+        result := a;  -- Oops!  Should be: result := c;
+      end if;
+    elsif  b > c then
+      result := b;
+    else
+      result := c;
+    end if;
+    assert result >= a and result >= b and result >= c
+      report "inconsistent result for maximum"
+      severity failure;
+    z <= result;
+  end process maximizer;
+
+end architecture check_error;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_09.vhd
new file mode 100644
index 0000000..b54fc47
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_fg_03_09.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_fg_03_09.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity edge_triggered_register is
+  port ( clock : in bit; 
+         d_in : in real;  d_out : out real );
+end entity edge_triggered_register;
+
+architecture check_timing of edge_triggered_register is
+begin
+
+  store_and_check : process (clock) is
+                                      variable stored_value : real;
+                                    variable pulse_start : time;
+  begin
+    case clock is
+      when '1' =>
+        pulse_start := now;
+        stored_value := d_in;
+        d_out <= stored_value;
+      when '0' =>
+        assert now = 0 ns or (now - pulse_start) >= 5 ns
+          report "clock pulse too short"; 
+    end case;
+  end process store_and_check;
+
+end architecture check_timing;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_01.vhd
new file mode 100644
index 0000000..8d34304
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_01.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_01 is
+end entity test_bench_03_01;
+
+architecture test_thermostat_example of test_bench_03_01 is
+
+  signal desired_temp, actual_temp : integer := 25;
+  signal heater_on : boolean := false;
+
+begin
+
+  dut : entity work.thermostat(example)
+    port map ( desired_temp => desired_temp, actual_temp => actual_temp,
+               heater_on => heater_on );
+
+  stimulus : process is
+  begin
+    wait for 5 sec;
+    actual_temp <= 24;		wait for 5 sec;
+    actual_temp <= 23;		wait for 5 sec;
+    actual_temp <= 22;		wait for 5 sec;
+    actual_temp <= 21;		wait for 5 sec;
+    actual_temp <= 22;		wait for 5 sec;
+    actual_temp <= 23;		wait for 5 sec;
+    actual_temp <= 24;		wait for 5 sec;
+    actual_temp <= 25;		wait for 5 sec;
+    actual_temp <= 26;		wait for 5 sec;
+    actual_temp <= 27;		wait for 5 sec;
+    actual_temp <= 28;		wait for 5 sec;
+    actual_temp <= 29;		wait for 5 sec;
+    actual_temp <= 28;		wait for 5 sec;
+    actual_temp <= 27;		wait for 5 sec;
+    actual_temp <= 26;		wait for 5 sec;
+    actual_temp <= 25;		wait for 5 sec;
+    actual_temp <= 24;		wait for 5 sec;
+    actual_temp <= 23;		wait for 5 sec;
+    actual_temp <= 22;		wait for 5 sec;
+    actual_temp <= 21;		wait for 5 sec;
+    actual_temp <= 22;		wait for 5 sec;
+    actual_temp <= 23;		wait for 5 sec;
+    actual_temp <= 24;		wait for 5 sec;
+    actual_temp <= 25;		wait for 5 sec;
+    actual_temp <= 26;		wait for 5 sec;
+    actual_temp <= 27;		wait for 5 sec;
+    actual_temp <= 28;		wait for 5 sec;
+    actual_temp <= 29;		wait for 5 sec;
+    actual_temp <= 28;		wait for 5 sec;
+    actual_temp <= 27;		wait for 5 sec;
+    actual_temp <= 26;		wait for 5 sec;
+
+    desired_temp <= 30;		wait for 5 sec;
+    actual_temp <= 25;		wait for 5 sec;
+    actual_temp <= 26;		wait for 5 sec;
+    actual_temp <= 27;		wait for 5 sec;
+    actual_temp <= 28;		wait for 5 sec;
+    actual_temp <= 29;		wait for 5 sec;
+    actual_temp <= 30;		wait for 5 sec;
+    actual_temp <= 31;		wait for 5 sec;
+    actual_temp <= 32;		wait for 5 sec;
+    actual_temp <= 33;		wait for 5 sec;
+    actual_temp <= 34;		wait for 5 sec;
+    actual_temp <= 35;		wait for 5 sec;
+    actual_temp <= 34;		wait for 5 sec;
+    actual_temp <= 33;		wait for 5 sec;
+    actual_temp <= 32;		wait for 5 sec;
+    actual_temp <= 31;		wait for 5 sec;
+    actual_temp <= 30;		wait for 5 sec;
+
+    wait;
+  end process stimulus;
+
+end architecture test_thermostat_example;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_02.vhd
new file mode 100644
index 0000000..27369e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_02.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package test_bench_03_02 is
+
+  -- following type used in Figure 3-02
+
+  -- code from book:
+
+  type sel_range is range 0 to 3;
+
+  -- end of code from book
+
+end package test_bench_03_02;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_03.vhd
new file mode 100644
index 0000000..1f802b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_03.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_03 is
+end entity test_bench_03_03;
+
+library ieee;  
+use ieee.std_logic_1164.all;
+
+architecture test_mux4_demo of test_bench_03_03 is
+
+  signal sel : work.test_bench_03_02.sel_range := 0;
+  signal d0, d1, d2, d3, z : std_ulogic;
+
+begin
+
+  dut : entity work.mux4(demo)
+    port map ( sel => sel,
+               d0 => d0, d1 => d1, d2 => d2, d3 => d3,
+               z => z );
+
+  stimulus : process is
+  begin
+    wait for 5 ns;
+    d0 <= '1';			wait for 5 ns;
+    d1 <= 'H';			wait for 5 ns;
+    sel <= 1;	wait for 5 ns;
+    d1 <= 'L';			wait for 5 ns;
+    sel <= 2;	wait for 5 ns;
+    d0 <= '0';			wait for 5 ns;
+    d2 <= '1';			wait for 5 ns;
+    d2 <= '0';			wait for 5 ns;
+    sel <= 3;	wait for 5 ns;
+    d3 <= '1';			wait for 5 ns;
+    d3 <= '0';			wait for 5 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_mux4_demo;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_04.vhd
new file mode 100644
index 0000000..618a5f1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_04.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_04.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_04 is
+end entity test_bench_03_04;
+
+architecture test_counter_behavior of test_bench_03_04 is
+
+  signal clk : bit := '0';
+  signal count : natural;
+
+begin
+
+  dut : entity work.counter(behavior)
+    port map ( clk => clk, count => count );
+
+  stimulus : process is
+  begin
+    for cycle_count in 1 to 100 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    wait;
+  end process stimulus;
+
+end architecture test_counter_behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_05.vhd
new file mode 100644
index 0000000..0fb83ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_05.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_05.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_05 is
+end entity test_bench_03_05;
+
+architecture test_counter_behavior of test_bench_03_05 is
+
+  signal clk, reset : bit := '0';
+  signal count : natural;
+
+begin
+
+  dut : entity work.counter(behavior)
+    port map ( clk => clk, reset => reset, count => count );
+
+  stimulus : process is
+  begin
+
+    for cycle_count in 1 to 5 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    reset <= '1' after 15 ns;
+    for cycle_count in 1 to 5 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    reset <= '0' after 15 ns;
+    for cycle_count in 1 to 30 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    wait;
+  end process stimulus;
+
+end architecture test_counter_behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_06.vhd
new file mode 100644
index 0000000..9dacdd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_06.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_06.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_06 is
+end entity test_bench_03_06;
+
+architecture test_cos_series of test_bench_03_06 is
+
+  signal theta, result : real := 0.0;
+
+begin
+
+  dut : entity work.cos(series)
+    port map ( theta => theta, result => result );
+
+  stimulus : process is
+
+                       constant pi : real := 3.1415927;
+
+  begin
+    wait for 10 ns;
+    theta <= pi / 6.0;		wait for 10 ns;
+    theta <= pi / 4.0;		wait for 10 ns;
+    theta <= pi / 3.0;		wait for 10 ns;
+    theta <= pi / 2.0;		wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_cos_series;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_07.vhd
new file mode 100644
index 0000000..a9ec05d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_07.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_07 is
+end entity test_bench_03_07;
+
+architecture test_cos_fixed_length_series of test_bench_03_07 is
+
+  signal theta, result : real := 0.0;
+
+begin
+
+  dut : entity work.cos(fixed_length_series)
+    port map ( theta => theta, result => result );
+
+  stimulus : process is
+
+                       constant pi : real := 3.1415927;
+
+  begin
+    wait for 10 ns;
+    theta <= pi / 6.0;		wait for 10 ns;
+    theta <= pi / 4.0;		wait for 10 ns;
+    theta <= pi / 3.0;		wait for 10 ns;
+    theta <= pi / 2.0;		wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_cos_fixed_length_series;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_08.vhd
new file mode 100644
index 0000000..62b9640
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_08.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_08.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_08 is
+end entity test_bench_03_08;
+
+architecture test_SR_flipflop_checking of test_bench_03_08 is
+
+  signal S, R, Q : bit := '0';
+
+begin
+
+  dut : entity work.SR_flipflop(checking)
+    port map ( S => S, R => R, Q => Q );
+
+  stumulus : process is
+
+  begin
+    wait for 10 ns;
+    S <= '1';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+    S <= '1';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+    R <= '1';			wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    R <= '1';			wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    S <= '1';	R <= '1';	wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_SR_flipflop_checking;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_09.vhd
new file mode 100644
index 0000000..be67916
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_09.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_09.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_09 is
+end entity test_bench_03_09;
+
+architecture test_max3_check_error of test_bench_03_09 is
+
+  signal a, b, c, z : integer := 0;
+
+begin
+
+  dut : entity work.max3(check_error)
+    port map ( a => a, b => b, c => c, z => z );
+
+  stumulus : process is
+
+  begin
+    wait for 10 ns;
+    a <= 7;				wait for 10 ns;
+    b <= 10;		wait for 10 ns;
+    c <= 15;	wait for 10 ns;
+    a <= 12;				wait for 10 ns;
+    a <= 20;				wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_max3_check_error;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_10.vhd
new file mode 100644
index 0000000..82a549e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_10.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_tb_03_10.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_03_10 is
+end entity test_bench_03_10;
+
+architecture test_edge_triggered_register_check_timing of test_bench_03_10 is
+
+  signal clock : bit := '0'; 
+  signal d_in, d_out : real := 0.0;
+
+begin
+
+  dut : entity work.edge_triggered_register(check_timing)
+    port map ( clock => clock, d_in => d_in, d_out => d_out );
+
+  stumulus : process is
+
+  begin
+    wait for 20 ns;
+
+    d_in <= 1.0;			wait for 10 ns;
+    clock <= '1', '0' after 10 ns;	wait for 20 ns;
+
+    d_in <= 2.0;			wait for 10 ns;
+    clock <= '1', '0' after 5 ns;	wait for 20 ns;
+
+    d_in <= 3.0;			wait for 10 ns;
+    clock <= '1', '0' after 4 ns;	wait for 20 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_edge_triggered_register_check_timing;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_01.vhd
new file mode 100644
index 0000000..f9922f8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_01.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_01 is
+
+end entity ch_04_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_01 is
+begin
+
+
+  block_04_1_a : block is
+
+                         -- code from book:
+
+                         type word is array (0 to 31) of bit;
+
+                       --
+
+                       type controller_state is (initial, idle, active, error);
+
+                       type state_counts is array (idle to error) of natural;
+
+                       -- end of code from book
+
+  begin
+  end block block_04_1_a;
+
+
+  process_04_1_a : process is
+
+                             -- code from book:
+
+                             type word is array (31 downto 0) of bit;
+
+                           --
+
+                           type controller_state is (initial, idle, active, error);
+
+                           --
+
+                           type state_counts is
+                             array (controller_state range idle to error) of natural;
+
+                           --
+
+                           subtype coeff_ram_address is integer range 0 to 63;
+                           type coeff_array is array (coeff_ram_address) of real;
+
+                           --
+
+                           variable buffer_register, data_register : word;
+                           variable counters : state_counts;
+                           variable coeff : coeff_array;
+
+                           -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    coeff(0) := 0.0;
+
+    counters(active) := counters(active) + 1;
+
+    data_register := buffer_register;
+
+    -- end of code from book
+
+    wait;
+  end process process_04_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_02.vhd
new file mode 100644
index 0000000..b3360e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_02.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_02 is
+
+end entity ch_04_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_02 is
+begin
+
+
+  process_04_1_b : process is
+
+                             -- code from book:
+
+                             type symbol is ('a', 't', 'd', 'h', digit, cr, error);
+                           type state is range 0 to 6;
+
+                           type transition_matrix is array (state, symbol) of state;
+
+                           variable transition_table : transition_matrix;
+
+                           -- end of code from book
+
+                           variable next_state : state;
+
+                           -- code from book:
+
+                           type point is array (1 to 3) of real;
+                           type matrix is array (1 to 3, 1 to 3) of real;
+
+                           variable p, q : point;
+                           variable transform : matrix;
+
+                           -- end of code from book
+
+  begin
+
+    next_state := 
+      -- code from book:
+
+      transition_table(5, 'd');
+
+
+    -- end of code from book
+
+    for i in 1 to 3 loop
+      for j in 1 to 3 loop
+        if i = j then
+          transform(i, j) := -1.0;
+        else
+          transform(i, j) := 0.0;
+        end if;
+      end loop;
+    end loop;
+    p := (1.0, 2.0, 3.0);
+
+    -- code from book:
+
+    for i in 1 to 3 loop
+      q(i) := 0.0;
+      for j in 1 to 3 loop
+        q(i) := q(i) + transform(i, j) * p(j);
+      end loop;
+    end loop;
+    -- end of code from book
+
+    wait;
+  end process process_04_1_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_04.vhd
new file mode 100644
index 0000000..d30cad7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_04.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_04.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_04 is
+
+end entity ch_04_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_04 is
+begin
+
+
+  process_04_1_i : process is
+
+                             -- code from book:
+
+                             type A is array (1 to 4, 31 downto 0) of boolean;
+
+                           -- end of code from book
+
+                           variable free_map : bit_vector(1 to 10) := "0011010110";
+                           variable count : natural;
+
+  begin
+
+    -- code from book (just the conditions):
+
+    assert A'left(1) = 1;      assert A'low(1) = 1;
+    assert A'right(2) = 0 ;    assert A'high(2) = 31;
+
+    assert A'length(1) = 4;    assert A'length(2) = 32;
+
+    assert A'ascending(1) = true;    assert A'ascending(2) = false;
+
+    assert A'low = 1;    assert A'length = 4;
+
+    --
+
+    count := 0;
+    for index in free_map'range loop
+      if free_map(index) = '1' then
+        count := count + 1;
+      end if;
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_04_1_i;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_05.vhd
new file mode 100644
index 0000000..cfe1ea8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_05.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_05.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_05 is
+
+end entity ch_04_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_05 is
+begin
+
+
+  process_04_2_a : process is
+
+                             -- code from book:
+
+                             type sample is array (natural range <>) of integer;
+
+                           variable short_sample_buf : sample(0 to 63);
+
+                           subtype long_sample is sample(0 to 255);
+                           variable new_sample_buf, old_sample_buf : long_sample;
+
+
+                           constant lookup_table : sample := ( 1 => 23, 3 => -16, 2 => 100, 4 => 11);
+
+                           constant beep_sample : sample := ( 127, 63, 0, -63, -127, -63, 0, 63 );
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_04_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_06.vhd
new file mode 100644
index 0000000..e1bcf87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_06.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_06 is
+
+end entity ch_04_06;
+
+
+----------------------------------------------------------------
+
+
+--library ieee;  use ieee.std_logic_1164.std_ulogic;
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ch_04_06 is
+
+  -- code from book:
+
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+  
+  --
+  
+  subtype std_ulogic_word is std_ulogic_vector(0 to 31);
+  
+  --
+  
+  signal csr_offset : std_ulogic_vector(2 downto 1);
+
+  -- end of code from book
+
+begin
+
+
+  process_04_2_b : process is
+
+                             -- code from book:
+
+                             type string is array (positive range <>) of character;
+
+                           --
+
+                           constant LCD_display_len : positive := 20;
+                           subtype LCD_display_string is string(1 to LCD_display_len);
+                           variable LCD_display : LCD_display_string := (others => ' ');
+
+                           --
+
+                           type bit_vector is array (natural range <>) of bit;
+
+                           --
+
+                           subtype byte is bit_vector(7 downto 0);
+
+                           --
+
+                           variable channel_busy_register : bit_vector(1 to 4);
+
+                           --
+
+                           constant ready_message  : string := "Ready     ";
+
+                           --
+
+                           variable current_test : std_ulogic_vector(0 to 13) := "ZZZZZZZZZZ----";
+
+                           --
+
+                           constant all_ones : std_ulogic_vector(15 downto 0) := X"FFFF";
+
+                           -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    channel_busy_register := b"0000";
+
+    -- end of code from book
+
+    wait;
+  end process process_04_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_07.vhd
new file mode 100644
index 0000000..675f609
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_07.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_07 is
+
+end entity ch_04_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_07 is
+begin
+
+
+  process_04_3_a : process is
+
+                             -- code from book:
+
+                             subtype pixel_row is bit_vector (0 to 15);
+                           variable current_row, mask : pixel_row;
+
+                           -- end of code from book
+
+  begin
+
+    current_row := "0000000011111111";
+    mask := "0000111111110000";
+
+    -- code from book:
+
+    current_row := current_row and not mask;
+    current_row := current_row xor X"FFFF";
+
+    -- end of code from book
+
+    -- code from book (conditions only):
+
+    assert B"10001010" sll 3  =  B"01010000";
+    assert B"10001010" sll -2  =  B"00100010";
+
+    assert B"10010111" srl 2  = B"00100101";
+    assert B"10010111" srl -6  =  B"11000000";
+
+    assert B"01001011" sra 3  =  B"00001001";
+    assert B"10010111" sra 3  =  B"11110010";
+    assert B"00001100" sla 2  =  B"00110000";
+    assert B"00010001" sla 2  =  B"01000111";
+
+    assert B"00010001" sra -2  =  B"01000111";
+    assert B"00110000" sla -2  =  B"00001100";
+
+    assert B"10010011" rol 1  =  B"00100111";
+    assert B"10010011" ror 1  =  B"11001001";
+
+    assert "abc" & 'd'  =  "abcd";
+    assert 'w' & "xyz"  =  "wxyz";
+    assert 'a' & 'b'  =  "ab";
+
+    -- end of code from book
+
+    wait;
+  end process process_04_3_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_08.vhd
new file mode 100644
index 0000000..de777a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_08.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_08 is
+
+end entity ch_04_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_08 is
+begin
+
+
+  process_04_3_b : process is
+
+                             -- code from book:
+
+                             type array1 is array (1 to 100) of integer;
+                           type array2 is array (100 downto 1) of integer;
+
+                           variable a1 : array1;
+                           variable a2 : array2;
+
+                           -- end of code from book
+
+  begin
+
+    a1(11 to 20) := a1(11 to 20);
+    a2(50 downto 41) := a2(50 downto 41);
+
+    a1(10 to 1) := a1(10 to 1);
+    a2(1 downto 10) := a2(1 downto 10);
+
+    a1(10 downto 1) := a1(10 downto 1);  -- illegal
+    a2(1 to 10) := a2(1 to 10);  -- illegal;
+
+    wait;
+  end process process_04_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_10.vhd
new file mode 100644
index 0000000..debb3e2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_ch_04_10.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_10.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_10 is
+
+end entity ch_04_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_10 is
+
+  -- code from book:
+
+  type time_stamp is record
+                       seconds : integer range 0 to 59;
+                       minutes : integer range 0 to 59;
+                       hours : integer range 0 to 23;
+                     end record time_stamp;
+
+  -- end of code from book
+
+begin
+
+
+  process_04_4_a : process is
+
+                             -- code from book:
+
+                             variable sample_time, current_time : time_stamp;
+
+                           --
+
+                           constant midday : time_stamp := (0, 0, 12);
+
+                           -- end of code from book
+
+                           constant clock : integer := 79;
+                           variable sample_hour : integer;
+
+  begin
+
+    current_time := (30, 15, 2);
+
+    -- code from book:
+
+    sample_time := current_time;
+
+    sample_hour := sample_time.hours;
+
+    current_time.seconds := clock mod 60;
+
+    -- end of code from book
+
+    wait;
+  end process process_04_4_a;
+
+
+  process_04_4_b : process is
+
+                             type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop);
+                           type reg_number is range 0 to 31;
+
+                           type instruction is record
+                                                 opcode : opcodes;
+                                                 source_reg1, source_reg2, dest_reg : reg_number;
+                                                 displacement : integer;
+                                               end record instruction;
+
+                           -- code from book:
+
+                           constant midday : time_stamp := (hours => 12, minutes => 0, seconds => 0);
+
+                           --
+
+                           constant nop_instr : instruction :=
+                             ( opcode => addu,
+                               source_reg1 | source_reg2 | dest_reg => 0,
+                               displacement => 0 );
+
+                           variable latest_event : time_stamp := (others => 0); -- initially midnight
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_04_4_b;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_01.vhd
new file mode 100644
index 0000000..d595916
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_01.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_fg_04_01.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book:
+library ch4_pkgs;
+use ch4_pkgs.pk_04_01.all;
+-- end not in book
+
+
+entity coeff_ram is
+  port ( rd, wr : in bit;  addr : in coeff_ram_address;
+  d_in : in real;  d_out : out real );
+end entity coeff_ram;
+
+--------------------------------------------------
+
+architecture abstract of coeff_ram is
+begin
+
+  memory : process is
+                     type coeff_array is array (coeff_ram_address) of real;
+                   variable coeff : coeff_array;
+  begin
+    for index in coeff_ram_address loop
+      coeff(index) := 0.0;
+    end loop;
+    loop
+      wait on rd, wr, addr, d_in; 
+      if rd = '1' then
+        d_out <= coeff(addr);
+      end if;
+      if wr = '1' then
+        coeff(addr) := d_in;
+      end if;
+    end loop;
+  end process memory;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_03.vhd
new file mode 100644
index 0000000..300f15a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_03.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_fg_04_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_04_03 is
+
+end entity fg_04_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of fg_04_03 is
+begin
+
+  -- code from book:
+
+  modem_controller : process is
+
+                               type symbol is ('a', 't', 'd', 'h', digit, cr, other);
+                             type symbol_string is array (1 to 20) of symbol;
+                             type state is range 0 to 6;
+                             type transition_matrix is array (state, symbol) of state;
+
+                             constant next_state : transition_matrix :=
+                               ( 0 => ('a' => 1, others => 6),
+                                 1 => ('t' => 2, others => 6),
+                                 2 => ('d' => 3, 'h' => 5, others => 6),
+                                 3 => (digit => 4, others => 6),
+                                 4 => (digit => 4, cr => 0, others => 6),
+                                 5 => (cr => 0, others => 6),
+                                 6 => (cr => 0, others => 6) );
+
+                             variable command : symbol_string;
+                             variable current_state : state := 0;
+
+                             -- not in book:
+                             type sample_array is array (positive range <>) of symbol_string;
+                             constant sample_command : sample_array :=
+                               ( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ),
+                                 2 => ( 'a', 't', 'h', cr, others => other ),
+                                 3 => ( 'a', 't', other, other, cr, others => other ) );
+                             -- end not in book
+
+  begin
+    -- . . .
+    -- not in book:
+    for command_index in sample_command'range loop
+      command := sample_command(command_index);
+      -- end not in book
+      for index in 1 to 20 loop
+        current_state := next_state( current_state, command(index) );
+        case current_state is
+          -- . . .
+          -- not in book:
+          when 0 => exit;
+          when others => null;
+                         -- end not in book
+        end case;
+      end loop;
+      -- . . .
+      -- not in book:
+    end loop;
+    wait;
+    -- end not in book
+  end process modem_controller;
+
+  -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_04.vhd
new file mode 100644
index 0000000..6be89a3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_04.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_fg_04_04.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity and_multiple is
+  port ( i : in bit_vector;  y : out bit );
+end entity and_multiple;
+
+--------------------------------------------------
+
+architecture behavioral of and_multiple is
+begin
+
+  and_reducer : process ( i ) is
+                                variable result : bit;
+  begin
+    result := '1';
+    for index in i'range loop
+      result := result and i(index);
+    end loop;
+    y <= result;
+  end process and_reducer;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_05.vhd
new file mode 100644
index 0000000..7bab6ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_05.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_fg_04_05.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book:
+library ch4_pkgs;
+use ch4_pkgs.pk_04_02.all;
+-- end not in book:
+
+
+entity byte_swap is
+  port (input : in halfword;  output : out halfword);
+end entity byte_swap;
+
+--------------------------------------------------
+
+architecture behavior of byte_swap is
+
+begin
+
+  swap : process (input)
+  begin
+    output(8 to 15) <= input(0 to 7);
+    output(0 to 7) <= input(8 to 15);
+  end process swap;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_06.vhd
new file mode 100644
index 0000000..9e6ca87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_fg_04_06.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_fg_04_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture system_level of computer is
+
+  type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, -- . . .);
+                   -- not in book:
+                   nop);
+  -- end not in book
+  type reg_number is range 0 to 31;
+  constant r0 : reg_number := 0;  constant r1 : reg_number := 1;  -- . . .
+  -- not in book:
+  constant r2 : reg_number := 2;
+  -- end not in book
+
+  type instruction is record
+                        opcode : opcodes;
+                        source_reg1, source_reg2, dest_reg : reg_number;
+                        displacement : integer;
+                      end record instruction;
+
+  type word is record
+                 instr : instruction;
+                 data : bit_vector(31 downto 0);
+               end record word;
+
+  signal address : natural;
+  signal read_word, write_word : word;
+  signal mem_read, mem_write : bit := '0';
+  signal mem_ready : bit := '0';
+
+begin
+
+  cpu : process is
+                  variable instr_reg : instruction;
+                variable PC : natural;
+                -- . . .    -- other declarations for register file, etc.
+  begin
+    address <= PC;
+    mem_read <= '1';
+    wait until mem_ready = '1';
+    instr_reg := read_word.instr;
+    mem_read <= '0';
+    -- not in book:
+    wait until mem_ready = '0';
+    -- end not in book
+    PC := PC + 4;
+    case instr_reg.opcode is  -- execute the instruction
+      -- . . .
+      -- not in book:
+      when others => null;
+                     -- end not in book
+    end case;
+  end process cpu;
+
+  memory : process is
+                     type memory_array is array (0 to 2**14 - 1) of word;
+                   variable store : memory_array :=
+                     (  0  => ( ( ld, r0, r0, r2, 40 ), X"00000000" ),
+                        1  => ( ( breq, r2, r0, r0, 5 ), X"00000000" ),
+                        -- . . .
+                        40  => ( ( nop, r0, r0, r0, 0 ), X"FFFFFFFE"),
+                        others => ( ( nop, r0, r0, r0, 0 ), X"00000000") );
+  begin
+    -- . . .
+    -- not in book:
+    wait until mem_read = '1';
+    read_word <= store(address);
+    mem_ready <= '1';
+    wait until mem_read = '0';
+    mem_ready <= '0';
+    -- end not in book
+  end process memory;
+
+end architecture system_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_01.vhd
new file mode 100644
index 0000000..a713f84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_01.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_pk_04_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package pk_04_01 is
+
+  subtype coeff_ram_address is integer range 0 to 63;
+
+end package pk_04_01;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_02.vhd
new file mode 100644
index 0000000..e749a9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_pk_04_02.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_pk_04_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package pk_04_02 is
+
+  subtype halfword is bit_vector(0 to 15);
+
+end package pk_04_02;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_01.vhd
new file mode 100644
index 0000000..7fa037a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_01.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_tb_04_01.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_04_01 is
+end entity test_bench_04_01;
+
+library ch4_pkgs;
+use ch4_pkgs.pk_04_02.all;
+
+architecture test_coeff_ram_abstract of test_bench_04_01 is
+
+  signal rd, wr : bit := '0';
+  signal addr : coeff_ram_address := 0;
+  signal d_in, d_out : real := 0.0;
+
+begin
+
+  dut : entity work.coeff_ram(abstract)
+    port map ( rd => rd, wr => wr,
+	       addr => addr,
+	       d_in => d_in, d_out => d_out );
+
+  stumulus : process is
+
+  begin
+    wait for 100 ns;
+
+    addr <= 10;  d_in <= 10.0;  wait for 10 ns;
+    wr <= '1';			wait for 10 ns;
+    d_in <= 20.0;  		wait for 10 ns;
+    wr <= '0';			wait for 70 ns;
+
+    addr <= 20;			wait for 10 ns;
+    rd <= '1';			wait for 10 ns;
+    addr <= 10;			wait for 10 ns;
+    rd <= '0';			wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_coeff_ram_abstract;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_02.vhd
new file mode 100644
index 0000000..a7181df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_02.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_tb_04_02.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_04_02 is
+
+end entity test_bench_04_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test_and_multiple_behavioral of test_bench_04_02 is
+
+  -- code from book:
+
+  signal count_value : bit_vector(7 downto 0);
+  signal terminal_count : bit;
+
+  -- end of code from book
+
+begin
+
+  -- code from book:
+
+  tc_gate : entity work.and_multiple(behavioral)
+    port map ( i => count_value, y => terminal_count);
+
+  -- end of code from book
+
+  stumulus : process is
+  begin
+    wait for 10 ns;
+    count_value <= "10000000";	wait for 10 ns;
+    count_value <= "11111110";	wait for 10 ns;
+    count_value <= "01111111";	wait for 10 ns;
+    count_value <= "11111111";	wait for 10 ns;
+    count_value <= "00000000";	wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_and_multiple_behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_03.vhd
new file mode 100644
index 0000000..3a49f5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_03.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_tb_04_03.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench_04_03 is
+end entity test_bench_04_03;
+
+library ch4_pkgs;
+use ch4_pkgs.pk_04_02.all;
+
+architecture test_byte_swap_behavior of test_bench_04_03 is
+
+  signal input, output : halfword := x"0000";
+
+begin
+
+  dut : entity work.byte_swap(behavior)
+    port map ( input => input, output => output );
+
+  stumulus : process is
+  begin
+    wait for 10 ns;
+    input <= x"ff00";	wait for 10 ns;
+    input <= x"00ff";	wait for 10 ns;
+    input <= x"aa33";	wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_byte_swap_behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_04.vhd
new file mode 100644
index 0000000..c6665ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_04.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_tb_04_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity computer is
+
+end entity computer;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_01.vhd
new file mode 100644
index 0000000..6a01c62
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_01.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+use work.tb_05_13.all;
+
+-- end not in book
+
+entity adder is
+  port ( a : in word;
+         b : in word;
+         sum : out word );
+end entity adder;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_02.vhd
new file mode 100644
index 0000000..3ce3bb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_02.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_02.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+use work.tb_05_13.all;
+
+-- end not in book
+
+entity adder is
+  port ( a, b : in word;
+         sum : out word );
+end entity adder;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_03.vhd
new file mode 100644
index 0000000..326c8fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_03.vhd
@@ -0,0 +1,30 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_03.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity and_or_inv is
+  port ( a1, a2, b1, b2 : in bit := '1';
+         y : out bit );
+end entity and_or_inv;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_04.vhd
new file mode 100644
index 0000000..556c4b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_04.vhd
@@ -0,0 +1,28 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_04.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity top_level is
+end entity top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_05.vhd
new file mode 100644
index 0000000..2afe050
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_05.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture abstract of adder is
+begin
+
+  add_a_b : process (a, b) is
+  begin
+    sum <= a + b;
+  end process add_a_b;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_06.vhd
new file mode 100644
index 0000000..e7c1c06
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_06.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_06 is
+
+end entity ch_05_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_06 is
+
+  signal y : bit := '0';
+  signal or_a_b : bit := '0';
+  signal clk : bit := '0';
+
+begin
+
+
+  process_05_3_a : process is
+  begin
+
+    -- code from book:
+
+    y <= not or_a_b after 5 ns;
+
+    -- end of code from book
+
+    wait on or_a_b;
+  end process process_05_3_a;
+
+
+  stimulus_05_3_a : process is
+  begin
+    or_a_b <= '1' after 20 ns,
+              '0' after 40 ns;
+    wait;
+  end process stimulus_05_3_a;
+
+
+  process_05_3_b : process is
+                             constant T_pw : delay_length := 10 ns;
+  begin
+
+    -- code from book:
+
+    clk <= '1' after T_pw, '0' after 2*T_pw;
+
+    -- end of code from book
+
+    wait for 2*T_pw;
+  end process process_05_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_07.vhd
new file mode 100644
index 0000000..1f69586
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_07.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_07 is
+
+end entity ch_05_07;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ch_05_07 is
+
+  signal clk, d : std_ulogic;
+
+  constant Tpw_clk : delay_length := 10 ns;
+  constant Tsu : delay_length := 4 ns;
+
+begin
+
+
+  process_05_3_c : process (clk, d) is
+  begin
+
+    -- code from book:
+
+    if clk'event and (clk = '1' or clk = 'H')
+      and (clk'last_value = '0' or clk'last_value = 'L') 
+    then
+      assert d'last_event >= Tsu
+        report "Timing error: d changed within setup time of clk";
+    end if;
+
+    -- end of code from book
+
+  end process process_05_3_c;
+
+
+  ----------------
+
+
+  process_05_3_d : process (clk, d) is
+  begin
+
+    -- code from book:
+
+    assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
+      report "Clock frequency too high";
+
+    -- end of code from book
+
+  end process process_05_3_d;
+
+
+  ----------------
+
+
+  process_05_3_e : process is
+  begin
+
+    -- code from book:
+
+    wait until clk = '1';
+
+    -- end of code from book
+
+    report "clk changed to '1'";
+  end process process_05_3_e;
+
+
+  ----------------
+
+
+  stimulus_05_3_c_d : process is
+  begin
+
+    clk <= '1' after  15 ns,
+           '0' after  30 ns,
+           '1' after  40 ns,
+           '0' after  50 ns,
+           'H' after  60 ns,
+           '0' after  70 ns,
+           '1' after  80 ns,
+           'L' after  90 ns,
+           'H' after 100 ns,
+           'L' after 120 ns,
+           '1' after 125 ns, -- should cause error
+           '0' after 130 ns; -- should cause error
+
+    d <= '1' after  35 ns,
+         '0' after  77 ns, -- should cause error
+         '1' after 102 ns;
+
+    wait;
+  end process stimulus_05_3_c_d;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_08.vhd
new file mode 100644
index 0000000..eb76352
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_08.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_08.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_08 is
+
+end entity ch_05_08;
+
+library stimulus;
+
+architecture test of ch_05_08 is
+
+  constant T_pd : delay_length := 5 ns;
+
+  signal a, b : bit := '0';
+  signal test_inputs : bit_vector(1 to 2);
+
+  use stimulus.stimulus_generators.all;
+
+begin
+
+  block_05_3_f : block is
+
+                         signal sum, carry : bit;
+
+  begin
+
+    -- code from book:
+
+    half_add : process is
+    begin
+      sum <= a xor b after T_pd;
+      carry <= a and b after T_pd;
+      wait on a, b;
+    end process half_add;
+
+    -- end of code from book
+
+  end block block_05_3_f;
+
+  block_05_3_g : block is
+
+                         signal sum, carry : bit;
+
+  begin
+
+    -- code from book:
+
+    half_add : process (a, b) is
+    begin
+      sum <= a xor b after T_pd;
+      carry <= a and b after T_pd;
+    end process half_add;
+
+    -- end of code from book
+
+  end block block_05_3_g;
+
+  stimulus_05_3_f_g :
+    all_possible_values(test_inputs, 20 ns);
+
+  (a, b) <= test_inputs;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_09.vhd
new file mode 100644
index 0000000..fae70e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_09.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_09.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_09 is
+
+end entity ch_05_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_09 is
+
+  signal clk, reset, trigger, test0, test1 : bit := '0';
+
+begin
+
+
+  process_05_3_h : process is
+  begin
+
+    -- code from book:
+
+    wait until clk = '1';
+
+    -- end of code from book
+
+    report "clk rising edge detected";
+
+  end process process_05_3_h;
+
+
+  ----------------
+
+
+  process_05_3_i : process is
+  begin
+
+    -- code from book:
+
+    wait on clk until reset = '0';
+
+    -- end of code from book
+
+    report "synchronous reset detected";
+
+  end process process_05_3_i;
+
+
+  ----------------
+
+
+  process_05_3_j : process is
+  begin
+
+    -- code from book:
+
+    wait until trigger = '1' for 1 ms;
+
+    -- end of code from book
+
+    if trigger'event and trigger = '1' then
+      report "trigger rising edge detected";
+    else
+      report "trigger timeout";
+    end if;
+
+  end process process_05_3_j;
+
+
+  ----------------
+
+
+  -- code from book:
+
+  test_gen : process is
+  begin
+    test0 <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
+    test1 <= '0' after 10 ns, '1' after 30 ns;
+    wait;
+  end process test_gen;
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus_05_3_h_i_j : process is
+  begin
+    clk <= '1' after 10 ns, '0' after 20 ns,
+           '1' after 30 ns, '0' after 40 ns,
+           '1' after 50 ns, '0' after 60 ns,
+           '1' after 70 ns, '0' after 80 ns;
+    reset <= '1' after 45 ns, '0' after 75 ns;
+    trigger <= '1' after 10 ns, '0' after 20 ns,
+               '1' after 30 ns, '0' after 40 ns;
+    
+    wait;
+  end process stimulus_05_3_h_i_j;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_10.vhd
new file mode 100644
index 0000000..dba7d3f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_10.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_10.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_10 is
+
+end entity ch_05_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_10 is
+
+  signal data : bit_vector(7 downto 0) := X"FF";
+  signal s : bit := '0';
+
+begin
+
+
+  process_05_3_l : process is
+  begin
+    wait for 10 ns;
+
+    -- code from book:
+
+    data <= X"00";
+
+    -- end of code from book
+
+    wait for 10 ns;
+
+    -- code from book:
+
+    s <= '1';
+    -- . . .
+    if s = '1' then -- . . .
+      -- not in book
+      report "s is '1'";
+    else
+      report "s is '0'";
+    end if;
+    -- end not in boook
+
+    -- end of code from book
+
+    wait;
+  end process process_05_3_l;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_11.vhd
new file mode 100644
index 0000000..ea1a103
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_11.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_11.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_11 is
+
+end entity ch_05_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_11 is
+
+  signal line_in, line_out : bit := '0';
+
+begin
+
+
+  -- code from book:
+
+  transmission_line : process (line_in) is
+  begin
+    line_out <= transport line_in after 500 ps;
+  end process transmission_line;
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    line_in <= '1' after 2000 ps,
+               '0' after 4000 ps,
+               '1' after 6000 ps,
+               '0' after 6200 ps,
+               '1' after 8000 ps,
+               '0' after 8200 ps,
+               '1' after 8300 ps,
+               '0' after 8400 ps;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_12.vhd
new file mode 100644
index 0000000..4e0b997
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_12.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_12 is
+
+end entity ch_05_12;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_12 is
+
+  signal top_a, bottom_a : bit := '0';
+  signal top_y, bottom_y : bit;
+
+begin
+
+
+  block_05_3_m : block is
+                         port ( a : in bit;  y : out bit := '1' );
+                       port map ( a => top_a, y => top_y );
+
+  begin
+
+    -- code from book:
+
+    inv : process (a) is
+    begin
+      y <= inertial not a after 3 ns;
+    end process inv;
+
+    -- end of code from book
+
+  end block block_05_3_m;
+
+
+  ----------------
+
+
+  block_05_3_n : block is
+                         port ( a : in bit;  y : out bit := '1' );
+                       port map ( a => bottom_a, y => bottom_y);
+
+  begin
+
+    -- code from book:
+
+    inv : process (a) is
+    begin
+      y <= reject 2 ns inertial not a after 3 ns;
+    end process inv;
+
+    -- end of code from book
+
+  end block block_05_3_n;
+
+
+  ----------------
+
+
+  stimulus_05_3_m_n : process is
+  begin
+    top_a <= '1' after 1 ns,
+             '0' after 6 ns,
+             '1' after 8 ns;
+    bottom_a <= '1' after 1 ns,
+                '0' after 6 ns,
+                '1' after 9 ns,
+                '0' after 11.5 ns,
+                '1' after 16 ns,
+                '0' after 18 ns,
+                '1' after 19 ns,
+                '0' after 20 ns;
+
+    wait;
+  end process stimulus_05_3_m_n;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_13.vhd
new file mode 100644
index 0000000..59c39e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_13.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_13.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_13 is
+
+end entity ch_05_13;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of ch_05_13 is
+
+  signal s : std_ulogic;
+
+begin
+
+
+  process_05_3_o : process is
+  begin
+    s <= '1' after 11 ns,
+         'X' after 12 ns,
+         '1' after 14 ns,
+         '0' after 15 ns,
+         '1' after 16 ns,
+         '1' after 17 ns,
+         '1' after 20 ns,
+         '0' after 25 ns;
+    wait for 10 ns;
+
+    -- code from book:
+
+    s <= reject 5 ns inertial '1' after 8 ns;
+
+    -- end of code from book
+
+    wait;
+  end process process_05_3_o;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_14.vhd
new file mode 100644
index 0000000..8e54df6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_14.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_14.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_14 is
+
+end entity ch_05_14;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_14 is
+
+  signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
+
+begin
+
+
+  block_05_3_p : block is
+                         port ( next_PC : out integer );
+                       port map ( next_PC => functional_next_PC );
+  begin
+
+    -- code from book:
+
+    PC_incr : next_PC <= PC + 4 after 5 ns;
+
+    -- end of code from book
+
+  end block block_05_3_p;
+
+
+  ----------------
+
+
+  block_05_3_q : block is
+                         port ( next_PC : out integer );
+                       port map ( next_PC => equivalent_next_PC );
+  begin
+
+    -- code from book:
+
+    PC_incr : process is
+    begin
+      next_PC <= PC + 4 after 5 ns;
+      wait on PC;
+    end process PC_incr;
+
+    -- end of code from book
+
+  end block block_05_3_q;
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    for i in 1 to 10 loop
+      PC <= i after 20 ns;
+      wait for 20 ns;
+    end loop;
+    wait;
+  end process stimulus;
+
+  verifier :
+    assert functional_next_PC = equivalent_next_PC
+      report "Functional and equivalent models give different results";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_15.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_15.vhd
new file mode 100644
index 0000000..ce65681
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_15.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_15.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_15 is
+  generic ( extended_reset : boolean := false );
+end entity ch_05_15;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_15 is
+
+  signal functional_reset, equivalent_reset : bit := '0';
+
+begin
+
+
+  block_05_3_r : block is
+                         port ( reset : out bit );
+                       port map ( reset => functional_reset );
+  begin
+
+    -- code from book:
+
+    reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
+                         '1', '0' after 50 ns;
+
+    -- end of code from book
+
+  end block block_05_3_r;
+
+
+  ----------------
+
+
+  block_05_3_s : block is
+                         port ( reset : out bit );
+                       port map ( reset => equivalent_reset );
+  begin
+
+    -- code from book:
+
+    reset_gen : process is
+    begin
+      if extended_reset then
+        reset <= '1', '0' after 200 ns;
+      else
+        reset <= '1', '0' after 50 ns;
+      end if;
+      wait;
+    end process reset_gen;
+
+    -- end of code from book
+
+  end block block_05_3_s;
+
+
+  ----------------
+
+
+  verifier :
+    assert functional_reset = equivalent_reset
+      report "Functional and equivalent models give different results";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_16.vhd
new file mode 100644
index 0000000..2bb7ce4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_16.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_16 is
+
+end entity ch_05_16;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_16 is
+
+  constant Tpd_01 : time := 800 ps;
+  constant Tpd_10 : time := 500 ps;
+
+  signal a, z : bit;
+
+begin
+
+
+  -- code from book:
+
+  asym_delay : z <= transport a after Tpd_01 when a = '1' else
+                    a after Tpd_10;
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    a <= '1' after 2000 ps,
+         '0' after 4000 ps,
+         '1' after 6000 ps,
+         '0' after 6200 ps;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_17.vhd
new file mode 100644
index 0000000..ac43d35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_17.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_17.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_17 is
+
+end entity ch_05_17;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_17 is
+
+  signal s, r, q, q_n : bit := '0';
+
+begin
+
+  q <= '1' when s = '1' else
+       '0' when r = '1';
+
+  q_n <= '0' when s = '1' else
+         '1' when r = '1';
+
+
+  -- code from book:
+
+  check : process is
+  begin
+    assert not (s = '1' and r = '1')
+      report "Incorrect use of S_R_flip_flop: s and r both '1'";
+    wait on s, r;
+  end process check;
+
+  -- end of code from book
+
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_18.vhd
new file mode 100644
index 0000000..a4317ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_18.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+entity DRAM_controller is
+  port ( rd, wr, mem : in bit;
+         ras, cas, we, ready : out bit  );
+end entity DRAM_controller;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture fpld of DRAM_controller is
+begin
+end architecture fpld;
+
+
+----------------------------------------------------------------
+
+
+entity ch_05_18 is
+
+end entity ch_05_18;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_18 is
+
+
+
+begin
+
+
+  block_05_4_a : block is
+                         signal cpu_rd, cpu_wr, cpu_mem,
+                       mem_ras, mem_cas, mem_we, cpu_rdy : bit;
+  begin
+
+    -- code from book:
+
+    main_mem_controller : entity work.DRAM_controller(fpld)
+      port map ( cpu_rd, cpu_wr, cpu_mem,
+                 mem_ras, mem_cas, mem_we, cpu_rdy );
+
+    -- end of code from book
+
+  end block block_05_4_a;
+
+
+  ----------------
+
+
+  block_05_4_b : block is
+                         signal cpu_rd, cpu_wr, cpu_mem,
+                       mem_ras, mem_cas, mem_we, cpu_rdy : bit;
+  begin
+
+    -- code from book:
+
+    main_mem_controller : entity work.DRAM_controller(fpld)
+      port map ( rd => cpu_rd, wr => cpu_wr,
+                 mem => cpu_mem, ready => cpu_rdy,
+                 ras => mem_ras, cas => mem_cas, we => mem_we );
+
+    -- end of code from book
+
+  end block block_05_4_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_19.vhd
new file mode 100644
index 0000000..0c7a5cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_19.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_19.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_05_19 is
+
+  -- code from book:
+
+  subtype digit is bit_vector(3 downto 0);
+
+  -- end of code from book
+
+end package ch_05_19;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_20.vhd
new file mode 100644
index 0000000..54f8ca9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_20.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_20.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package pk_05_20 is
+
+  -- code from book:
+
+  type FIFO_status is record
+                        nearly_full, nearly_empty, full, empty : bit;
+                      end record FIFO_status;
+
+  -- end of code from book
+
+end package pk_05_20;
+
+
+----------------------------------------------------------------
+
+
+use work.pk_05_20.all;
+
+entity FIFO is
+  port ( status : out FIFO_status;
+         other_ports : out bit );
+end entity FIFO;
+
+
+----------------------------------------------------------------
+
+
+entity ch_05_20 is
+
+end entity ch_05_20;
+
+
+----------------------------------------------------------------
+
+
+use work.pk_05_20.all;
+
+architecture test of ch_05_20 is
+
+  signal start_flush, end_flush, DMA_buffer_full, DMA_buffer_empty : bit;
+
+begin
+
+  -- code from book:
+
+  DMA_buffer : entity work.FIFO
+    port map ( -- . . ., 
+      status.nearly_full => start_flush,
+      status.nearly_empty => end_flush,
+      status.full => DMA_buffer_full,
+      status.empty => DMA_buffer_empty, -- . . . );
+      -- not in book
+      other_ports => open );
+  -- end not in book
+
+  -- end of code from book
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_21.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_21.vhd
new file mode 100644
index 0000000..c53d4b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_21.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+entity and_gate is
+  port ( i : in bit_vector;  y : out bit );
+end entity and_gate;
+
+-- end of code from book
+
+architecture behavioral of and_gate is
+begin
+
+  reducer : process (i) is
+                          constant Tpd : delay_length := 2 ns;
+                        variable result : bit;
+  begin
+    result := '1';
+    for index in i'range loop
+      result := result and i(index);
+    end loop;
+    y <= result after Tpd;
+  end process reducer;
+
+end architecture behavioral;
+
+entity ch_05_21 is
+
+end entity ch_05_21;
+
+library stimulus;
+
+architecture test of ch_05_21 is
+
+  -- code from book:
+
+  signal serial_select, write_en, bus_clk, serial_wr : bit;
+
+  -- end of code from book
+
+  use stimulus.stimulus_generators.all;
+
+  signal test_input : bit_vector(2 downto 0);
+
+begin
+
+  -- code from book:
+
+  serial_write_gate : entity work.and_gate
+    port map ( i(1) => serial_select,
+               i(2) => write_en,
+               i(3) => bus_clk,
+               y => serial_wr );
+
+  -- end of code from book
+
+  stimulus : all_possible_values( bv => test_input,
+                                  delay_between_values => 10 ns );
+
+  (serial_select, write_en, bus_clk) <= test_input;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_22.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_22.vhd
new file mode 100644
index 0000000..bf12b3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_22.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+entity mux4 is
+  port ( i0, i1, i2, i3, sel0, sel1 : in bit;
+         z : out bit );
+end entity mux4;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture functional of mux4 is
+begin
+
+  out_select : process (sel0, sel1, i0, i1, i2, i3) is
+                                                      subtype bits_2 is bit_vector(1 downto 0);
+  begin
+    case bits_2'(sel1, sel0) is
+      when "00" =>  z <= i0;
+      when "01" =>  z <= i1;
+      when "10" =>  z <= i2;
+      when "11" =>  z <= i3;
+    end case;
+  end process out_select;
+
+end architecture functional;
+
+
+----------------------------------------------------------------
+
+
+entity ch_05_22 is
+
+end entity ch_05_22;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_22 is
+
+  signal select_line, line0, line1, result_line : bit;
+
+begin
+
+
+  -- code from book:
+
+  a_mux : entity work.mux4
+    port map ( sel0 => select_line, i0 => line0, i1 => line1,
+               z => result_line,
+               sel1 => '0', i2 => '1', i3 => '1' );
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    wait for 5 ns;
+    line0 <= '1';				wait for 5 ns;
+    line1 <= '1';				wait for 5 ns;
+    select_line <= '1';	wait for 5 ns;
+    line1 <= '0';				wait for 5 ns;
+    line0 <= '0';				wait for 5 ns;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_23.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_23.vhd
new file mode 100644
index 0000000..858efe1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_23.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_23.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+entity and_or_inv is
+  port ( a1, a2, b1, b2 : in bit := '1';
+         y : out bit );
+end entity and_or_inv;
+
+-- end of code from book
+
+architecture functional of and_or_inv is
+begin
+
+  func : y <= not ((a1 and a2) or (b1 and b2));
+
+end architecture functional;
+
+entity ch_05_23 is
+
+end entity ch_05_23;
+
+library stimulus;
+
+architecture test of ch_05_23 is
+
+  signal A, B, C, F : bit;
+  signal test_input : bit_vector(2 downto 0);
+
+  use stimulus.stimulus_generators.all;
+
+begin
+
+  -- code from book:
+
+  f_cell : entity work.and_or_inv
+    port map (a1 => A, a2 => B, b1 => C, b2 => open, y => F);
+
+  -- end of code from book
+
+  stimulus : all_possible_values( bv => test_input,
+				  delay_between_values => 10 ns );
+
+  (A, B, C) <= test_input;
+
+  verifier :
+    postponed assert F = not ((A and B) or C)
+      report "function model produced unexpected result";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_24.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_24.vhd
new file mode 100644
index 0000000..f2ef085
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_24.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_24.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+entity and3 is
+  port ( a, b, c : in bit := '1';
+         z, not_z : out bit);
+end entity and3;
+
+-- end of code from book
+
+architecture functional of and3 is
+begin
+
+  non_inverting:
+    z <= a and b and c;
+
+  inverting:
+    not_z <= not (a and b and c);
+
+end architecture functional;
+
+entity ch_05_24 is
+
+end entity ch_05_24;
+
+library stimulus;
+
+architecture test of ch_05_24 is
+
+  signal s1, s2, ctrl1_a, ctrl1_b : bit;
+  signal test_input : bit_vector(1 to 2);
+
+  use stimulus.stimulus_generators.all;
+
+begin
+
+
+  block_05_4_a : block is
+                         port ( ctrl1 : out bit );
+                       port map ( ctrl1 => ctrl1_a );
+  begin
+
+    -- code from book:
+
+    g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1);
+
+    -- end of code from book
+
+  end block block_05_4_a;
+
+  block_05_4_b : block is
+                         port ( ctrl1 : out bit );
+                       port map ( ctrl1 => ctrl1_b );
+  begin
+
+    -- code from book:
+
+    g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1,
+                                    c => open, z => open);
+
+    -- end of code from book
+
+  end block block_05_4_b;
+
+  stimulus : all_possible_values( bv => test_input,
+				  delay_between_values => 10 ns );
+
+  (s1, s2) <= test_input;
+
+  verifier :
+    assert ctrl1_a = ctrl1_b
+      report "versions differ";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_25.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_25.vhd
new file mode 100644
index 0000000..d295388
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_25.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_25.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- VHDL-87
+
+
+entity mux4 is
+  port ( i0, i1, i2, i3, sel0, sel1 : in bit;
+         z : out bit );
+end mux4;
+
+
+----------------------------------------------------------------
+
+
+architecture functional of mux4 is
+begin
+
+  out_select : process (sel0, sel1, i0, i1, i2, i3)
+    subtype bits_2 is bit_vector(1 downto 0);
+  begin
+    case bits_2'(sel1, sel0) is
+      when "00" =>  z <= i0;
+      when "01" =>  z <= i1;
+      when "10" =>  z <= i2;
+      when "11" =>  z <= i3;
+    end case;
+  end process out_select;
+
+end functional;
+
+
+----------------------------------------------------------------
+
+
+entity ch_05_25 is
+
+end ch_05_25;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_05_25 is
+
+  signal select_line, line0, line1, result_line : bit;
+
+  -- code from book:
+
+  signal tied_0 : bit := '0';
+  signal tied_1 : bit := '1';
+
+  -- end of code from book
+
+  component mux4
+    port ( i0, i1, i2, i3, sel0, sel1 : in bit;
+           z : out bit );
+  end component;
+
+  for all : mux4
+    use entity work.mux4;
+
+begin
+
+
+  a_mux : mux4
+
+    -- code from book:
+
+    port map ( sel0 => select_line, i0 => line0, i1 => line1,
+               z => result_line,
+               sel1 => tied_0, i2 => tied_1, i3 => tied_1 );
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process
+  begin
+    wait for 5 ns;
+    line0 <= '1';				wait for 5 ns;
+    line1 <= '1';				wait for 5 ns;
+    select_line <= '1';	wait for 5 ns;
+    line1 <= '0';				wait for 5 ns;
+    line0 <= '0';				wait for 5 ns;
+
+    wait;
+  end process stimulus;
+
+
+end test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_26.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_26.vhd
new file mode 100644
index 0000000..988994e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_26.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_26.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_26 is
+end entity ch_05_26;
+
+-- code from book:
+
+library widget_cells, wasp_lib;
+
+use widget_cells.reg32;
+
+-- end of code from book
+
+
+architecture test of ch_05_26 is
+
+  signal filter_clk, accum_en : bit;
+  signal sum, result : bit_vector(31 downto 0);
+
+begin
+
+
+  -- code from book:
+
+  accum : entity reg32
+    port map ( en => accum_en, clk => filter_clk, d => sum,
+               q => result );
+
+  -- end of code from book
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_27.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_27.vhd
new file mode 100644
index 0000000..52727c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_27.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_ch_05_27.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_05_27 is
+end entity ch_05_27;
+
+library wasp_lib;
+
+-- code from book:
+use wasp_lib.all;
+-- end of code from book
+
+architecture test of ch_05_27 is
+
+  signal clk, filter_clk : bit;
+
+begin
+
+  clk_pad : entity wasp_lib.in_pad
+    port map ( i => clk, z => filter_clk );
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_01.vhd
new file mode 100644
index 0000000..86b9932
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_01.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+-- end not in book
+
+
+               entity program_ROM is
+                 port ( address : in std_ulogic_vector(14 downto 0);
+                        data : out std_ulogic_vector(7 downto 0);
+                        enable : in std_ulogic );
+
+                 subtype instruction_byte is bit_vector(7 downto 0);
+                 type program_array is array (0 to 2**14 - 1) of instruction_byte;
+                 constant program : program_array
+                   := ( X"32", X"3F", X"03",  -- LDA  $3F03
+                        X"71", X"23",         -- BLT    $23
+                        -- not in book
+                        others => X"00"
+                        -- end not in book
+                        -- . . .
+                        );
+
+               end entity program_ROM;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_02.vhd
new file mode 100644
index 0000000..6473ed1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_02.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture primitive of and_or_inv is
+
+  signal and_a, and_b : bit;
+  signal or_a_b : bit;
+
+begin
+
+  and_gate_a : process (a1, a2) is
+  begin
+    and_a <= a1 and a2;
+  end process and_gate_a;
+
+  and_gate_b : process (b1, b2) is
+  begin
+    and_b <= b1 and b2;
+  end process and_gate_b;
+
+  or_gate : process (and_a, and_b) is
+  begin
+    or_a_b <= and_a or and_b;
+  end process or_gate;
+
+  inv : process (or_a_b) is
+  begin
+    y <= not or_a_b;
+  end process inv;
+
+end architecture primitive;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_03.vhd
new file mode 100644
index 0000000..46e7b63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_03.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_03 is
+end entity fg_05_03;
+
+architecture test of fg_05_03 is
+
+  constant T_pw : time := 10 ns;
+
+  signal clk : bit;
+
+begin
+
+  -- code from book
+
+  clock_gen : process (clk) is
+  begin
+    if clk = '0' then
+      clk <= '1' after T_pw, '0' after 2*T_pw;
+    end if;
+  end process clock_gen;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_04.vhd
new file mode 100644
index 0000000..b4885e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_04.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_04 is
+end entity fg_05_04;
+
+architecture test of fg_05_04 is
+
+  constant prop_delay : time := 5 ns;
+
+  signal a, b, sel, z : bit;
+
+begin
+
+  -- code from book
+
+  mux : process (a, b, sel) is
+  begin
+    case sel is
+      when '0' =>
+	z <= a after prop_delay;
+      when '1' =>
+	z <= b after prop_delay;
+    end case;
+  end process mux;
+
+  -- end code from book
+
+
+  stimulus : process is
+                       subtype stim_vector_type is bit_vector(0 to 3);
+                     type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+                     constant stim_vector : stim_vector_array
+                       := ( "0000",
+                            "0010",
+                            "0100",
+                            "0111",
+                            "1001",
+                            "1010",
+                            "1101",
+                            "1111" );
+  begin
+    for i in stim_vector'range loop
+      (a, b, sel) <= stim_vector(i)(0 to 2);
+      wait for 10 ns;
+      assert z = stim_vector(i)(3);
+    end loop;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_05.vhd
new file mode 100644
index 0000000..ce2ff17
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_05.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_05.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity edge_triggered_Dff is
+  port ( D : in bit;  clk : in bit;  clr : in bit;
+  Q : out bit );
+end entity edge_triggered_Dff;
+
+architecture behavioral of edge_triggered_Dff is
+begin
+
+  state_change : process (clk, clr) is
+  begin
+    if clr = '1' then
+      Q <= '0' after 2 ns;
+    elsif clk'event and clk = '1' then
+      Q <= D after 2 ns;
+    end if;
+  end process state_change;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_06.vhd
new file mode 100644
index 0000000..995f997
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_06.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity mux2 is
+  port ( a, b, sel : in bit;
+         z : out bit );
+end entity mux2;
+
+--------------------------------------------------
+
+architecture behavioral of mux2 is
+
+  constant prop_delay : time := 2 ns;
+
+begin
+
+  slick_mux : process is
+  begin
+    case sel is
+      when '0' =>
+        z <= a after prop_delay;
+        wait on sel, a;
+      when '1' =>
+        z <= b after prop_delay;
+        wait on sel, b;
+    end case;
+  end process slick_mux;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_07.vhd
new file mode 100644
index 0000000..2197e8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_07.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_07 is
+end entity fg_05_07;
+
+architecture test of fg_05_07 is
+
+  constant T_pw : time := 10 ns;
+
+  signal clk : bit;
+
+begin
+
+  -- code from book
+
+  clock_gen : process is
+  begin
+    clk <= '1' after T_pw, '0' after 2*T_pw;
+    wait until clk = '0';
+  end process clock_gen;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_08.vhd
new file mode 100644
index 0000000..c2406c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_08.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_08 is
+end entity fg_05_08;
+
+architecture test of fg_05_08 is
+
+  constant T_pw : time := 10 ns;
+
+  signal clk : bit;
+
+begin
+
+  -- code from book
+
+  clock_gen : process is
+  begin
+    clk <= '1' after T_pw, '0' after 2*T_pw;
+    wait for 2*T_pw;
+  end process clock_gen;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_09.vhd
new file mode 100644
index 0000000..1d5119a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_09.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+architecture abstract of computer_system is
+
+  subtype word is bit_vector(31 downto 0);
+
+  signal address : natural;
+  signal read_data, write_data : word;
+  signal mem_read, mem_write : bit := '0';
+  signal mem_ready : bit := '0';
+
+begin
+
+  cpu : process is
+                  variable instr_reg : word;
+                variable PC : natural;
+                -- . . .    -- other declarations
+  begin
+    loop
+      address <= PC;
+      mem_read <= '1';
+      wait until mem_ready = '1';
+      instr_reg := read_data;
+      mem_read <= '0';
+      wait until mem_ready = '0';
+      PC := PC + 4;
+      -- . . .    -- execute the instruction
+    end loop;
+  end process cpu;
+
+  memory : process is
+                     type memory_array is array (0 to 2**14 - 1) of word;
+                   variable store : memory_array := (
+                     -- . . .
+                     -- not in book
+                     0 => X"0000_0000",
+                     1 => X"0000_0004",
+                     2 => X"0000_0008",
+                     3 => X"0000_000C",
+                     4 => X"0000_0010",
+                     5 => X"0000_0014",
+                     others => X"0000_0000"
+				        -- end not in book
+                     );
+  begin
+    wait until mem_read = '1' or mem_write = '1';
+    if mem_read = '1' then
+      read_data <= store( address / 4 );
+      mem_ready <= '1';
+      wait until mem_read = '0';
+      mem_ready <= '0';
+    else
+      -- . . .    -- perform write access
+    end if;
+  end process memory;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_12.vhd
new file mode 100644
index 0000000..0aca507
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_12.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_12 is
+end entity fg_05_12;
+
+
+
+architecture test of fg_05_12 is
+
+  signal a, z : bit;
+
+begin
+
+  -- code from book
+
+  asym_delay : process (a) is
+                             constant Tpd_01 : time := 800 ps;
+                           constant Tpd_10 : time := 500 ps;
+  begin
+    if a = '1' then
+      z <= transport a after Tpd_01;
+    else  -- a = '0'
+      z <= transport a after Tpd_10;
+    end if;
+  end process asym_delay;
+
+  -- end code from book
+
+
+  stimulus : process is
+  begin
+    a <= '1' after 2000 ps,
+         '0' after 4000 ps,
+         '1' after 6000 ps,
+         '0' after 6200 ps;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_16.vhd
new file mode 100644
index 0000000..953f982
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_16.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity and2 is
+                 port ( a, b : in std_ulogic;  y : out std_ulogic );
+               end entity and2;
+
+--------------------------------------------------
+
+               architecture detailed_delay of and2 is
+
+                 signal result : std_ulogic;
+
+               begin
+
+                 gate : process (a, b) is
+                 begin
+                   result <= a and b;
+                 end process gate;
+
+                 delay : process (result) is
+                 begin
+                   if result = '1' then
+                     y <= reject 400 ps inertial '1' after 1.5 ns;
+                   elsif result = '0' then
+                     y <= reject 300 ps inertial '0' after 1.2 ns;
+                   else
+                     y <= reject 300 ps inertial 'X' after 500 ps;
+                   end if;
+                 end process delay;
+
+               end architecture detailed_delay;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_17.vhd
new file mode 100644
index 0000000..52c312b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_17.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_17.vhd,v 1.5 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.5 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_17 is
+end entity fg_05_17;
+
+library stimulus;
+
+architecture test of fg_05_17 is
+
+  use stimulus.stimulus_generators.all;
+
+  signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
+  signal functional_z, equivalent_z : bit;
+
+begin
+
+  functional_mux : block is
+                           port ( z : out bit );
+                         port map ( z => functional_z );
+  begin
+
+    -- code from book
+
+    zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
+                d1 when sel1 = '0' and sel0 = '1' else
+                d2 when sel1 = '1' and sel0 = '0' else
+                d3 when sel1 = '1' and sel0 = '1';
+
+    -- end code from book
+
+  end block functional_mux;
+
+  equivalent_mux : block is
+                           port ( z : out bit );
+                         port map ( z => equivalent_z );
+  begin
+
+    -- code from book
+
+    zmux : process is
+    begin
+      if sel1 = '0' and sel0 = '0' then
+        z <= d0;
+      elsif sel1 = '0' and sel0 = '1' then
+        z <= d1;
+      elsif sel1 = '1' and sel0 = '0' then
+        z <= d2;
+      elsif sel1 = '1' and sel0 = '1' then
+        z <= d3;
+      end if;
+      wait on d0, d1, d2, d3, sel0, sel1;
+    end process zmux;
+
+    -- end code from book
+
+  end block equivalent_mux;
+
+  stimulus :
+    all_possible_values( bv(0) => sel0, bv(1) => sel1,
+			 bv(2) => d0, bv(3) => d1,
+			 bv(4) => d2, bv(5) => d3,
+			 delay_between_values => 10 ns );
+
+  verifier :
+    assert functional_z = equivalent_z
+      report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_18.vhd
new file mode 100644
index 0000000..8b6e22f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_18.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_18.vhd,v 1.5 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.5 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_18 is
+end entity fg_05_18;
+
+library stimulus;
+
+architecture test of fg_05_18 is
+
+  use stimulus.stimulus_generators.all;
+
+  signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
+  signal functional_z, equivalent_z : bit;
+
+begin
+
+  functional_mux : block is
+                           port ( z : out bit );
+                         port map ( z => functional_z );
+  begin
+
+    -- code from book
+
+    zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
+                d1 when sel1 = '0' and sel0 = '1' else
+                d2 when sel1 = '1' and sel0 = '0' else
+                d3;
+
+    -- end code from book
+
+  end block functional_mux;
+
+  equivalent_mux : block is
+                           port ( z : out bit );
+                         port map ( z => equivalent_z );
+  begin
+
+    -- code from book
+
+    zmux : process is
+    begin
+      if sel1 = '0' and sel0 = '0' then
+        z <= d0;
+      elsif sel1 = '0' and sel0 = '1' then
+        z <= d1;
+      elsif sel1 = '1' and sel0 = '0' then
+        z <= d2;
+      else
+        z <= d3;
+      end if;
+      wait on d0, d1, d2, d3, sel0, sel1;
+    end process zmux;
+
+    -- end code from book
+
+  end block equivalent_mux;
+
+  stimulus :
+    all_possible_values( bv(0) => sel0, bv(1) => sel1,
+			 bv(2) => d0, bv(3) => d1,
+			 bv(4) => d2, bv(5) => d3,
+			 delay_between_values => 10 ns );
+
+  verifier :
+    assert functional_z = equivalent_z
+      report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_19.vhd
new file mode 100644
index 0000000..99e4c16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_19.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_19 is
+end entity fg_05_19;
+
+
+architecture test of fg_05_19 is
+
+  constant scheduling_delay : delay_length := 5 ns;
+
+  subtype request_type is natural range 0 to 20;
+  type server_status_type is (ready, busy);
+
+  signal first_priority_request,
+    first_normal_request,
+    reset_request : request_type := 0;
+  signal functional_request, equivalent_request : request_type;
+  signal priority_waiting : boolean := false;
+  signal server_status : server_status_type := busy;
+
+begin
+
+  functional_scheduler : block is
+                                 port ( request : out request_type );
+                               port map ( request => functional_request );
+  begin
+
+    -- code from book
+
+    scheduler :
+      request <= first_priority_request after scheduling_delay
+                 when priority_waiting and server_status = ready else
+                 first_normal_request after scheduling_delay
+                 when not priority_waiting and server_status = ready else
+                 unaffected
+                 when server_status = busy else
+                 reset_request after scheduling_delay;
+
+    -- end code from book
+
+  end block functional_scheduler;
+
+  --------------------------------------------------
+
+  equivalent_scheduler : block is
+                                 port ( request : out request_type );
+                               port map ( request => equivalent_request );
+  begin
+
+    -- code from book
+
+    scheduler : process is
+    begin
+      if priority_waiting and server_status = ready then
+        request <= first_priority_request after scheduling_delay;
+      elsif not priority_waiting and server_status = ready then
+        request <= first_normal_request after scheduling_delay;
+      elsif server_status = busy then
+        null;
+      else
+        request <= reset_request after scheduling_delay;
+      end if;
+      wait on first_priority_request, priority_waiting, server_status,
+        first_normal_request, reset_request;
+    end process scheduler;
+
+    -- end code from book
+
+  end block equivalent_scheduler;
+
+  --------------------------------------------------
+
+  stimulus : process is
+  begin
+    first_priority_request <= 10;	wait for 20 ns;
+    first_normal_request <= 5;		wait for 20 ns;
+    server_status <= ready;		wait for 20 ns;
+    server_status <= busy;		wait for 20 ns;
+    priority_waiting <= true;		wait for 20 ns;
+    server_status <= ready;		wait for 20 ns;
+    first_normal_request <= 7;		wait for 20 ns;
+    first_priority_request <= 12;	wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  verifier :
+    assert functional_request = equivalent_request
+      report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_20.vhd
new file mode 100644
index 0000000..8c39d0d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_20.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_20.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_05_20 is
+end entity fg_05_20;
+
+
+architecture test of fg_05_20 is
+
+  constant Tpd : delay_length := 2 ns;
+
+  function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    alias op1 : bit_vector(1 to bv1'length) is bv1;
+    alias op2 : bit_vector(1 to bv2'length) is bv2;  
+    variable result : bit_vector(1 to bv1'length);
+    variable carry_in : bit;
+    variable carry_out : bit := '0';
+
+  begin
+    for index in result'reverse_range loop
+      carry_in := carry_out;  -- of previous bit
+      result(index) := op1(index) xor op2(index) xor carry_in;
+      carry_out := (op1(index) and op2(index))
+      	      	   or (carry_in and (op1(index) xor op2(index)));
+    end loop;
+    return result;
+  end function "+";
+
+  function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    -- subtraction implemented by adding ((not bv2) + 1), ie -bv2
+
+    alias op1 : bit_vector(1 to bv1'length) is bv1;
+    alias op2 : bit_vector(1 to bv2'length) is bv2;  
+    variable result : bit_vector(1 to bv1'length);
+    variable carry_in : bit;
+    variable carry_out : bit := '1';
+
+  begin
+    for index in result'reverse_range loop
+      carry_in := carry_out;  -- of previous bit
+      result(index) := op1(index) xor (not op2(index)) xor carry_in;
+      carry_out := (op1(index) and (not op2(index)))
+      	      	   or (carry_in and (op1(index) xor (not op2(index))));
+    end loop;
+    return result;
+  end function "-";
+
+  type alu_function_type is (alu_pass_a, alu_add, alu_sub,
+			     alu_add_unsigned, alu_sub_unsigned,
+			     alu_and, alu_or);
+
+  signal alu_function : alu_function_type := alu_pass_a;
+  signal a, b : bit_vector(15 downto 0);
+  signal functional_result, equivalent_result : bit_vector(15 downto 0);
+
+begin
+
+  functional_alu : block is
+                           port ( result : out bit_vector(15 downto 0) );
+                         port map ( result => functional_result );
+  begin
+
+    -- code from book
+
+    alu : with alu_function select
+      result <=  a + b after Tpd   when alu_add | alu_add_unsigned,
+      a - b after Tpd   when alu_sub | alu_sub_unsigned,
+      a and b after Tpd when alu_and,
+      a or b after Tpd  when alu_or,
+      a after Tpd       when alu_pass_a;
+
+    -- end code from book
+
+  end block functional_alu;
+
+  --------------------------------------------------
+  
+  equivalent_alu : block is
+                           port ( result : out bit_vector(15 downto 0) );
+                         port map ( result => equivalent_result );
+  begin
+
+    -- code from book
+
+    alu : process is
+    begin
+      case alu_function is
+        when alu_add | alu_add_unsigned =>  result <= a + b after Tpd;
+        when alu_sub | alu_sub_unsigned =>  result <= a - b after Tpd;
+        when alu_and                    =>  result <= a and b after Tpd;
+        when alu_or                     =>  result <= a or b after Tpd;
+        when alu_pass_a                 =>  result <= a after Tpd;
+      end case;
+      wait on alu_function, a, b;
+    end process alu;
+
+    -- end code from book
+
+  end block equivalent_alu;
+
+  --------------------------------------------------
+
+  stimulus : process is
+  begin
+    alu_function <= alu_add;	wait for 10 ns;
+    a <= X"000A";		wait for 10 ns;
+    b <= X"0003";		wait for 10 ns;
+    alu_function <= alu_sub;	wait for 10 ns;
+    alu_function <= alu_and;	wait for 10 ns;
+    alu_function <= alu_or;	wait for 10 ns;
+    alu_function <= alu_pass_a;	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  verifier :
+    assert functional_result = equivalent_result
+      report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_21.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_21.vhd
new file mode 100644
index 0000000..72eba37
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_21.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_21.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity full_adder is
+  port ( a, b, c_in : bit;  s, c_out : out bit );
+end entity full_adder;
+
+architecture truth_table of full_adder is
+begin
+
+  with bit_vector'(a, b, c_in) select
+    (c_out, s) <= bit_vector'("00") when "000",
+    bit_vector'("01") when "001",
+    bit_vector'("01") when "010",
+    bit_vector'("10") when "011",
+    bit_vector'("01") when "100",
+    bit_vector'("10") when "101",
+    bit_vector'("10") when "110",
+    bit_vector'("11") when "111";
+
+end architecture truth_table;
+
+-- not in book
+
+entity fg_05_21 is
+end entity fg_05_21;
+
+library stimulus;
+use stimulus.stimulus_generators.all;
+
+architecture test of fg_05_21 is
+
+  signal a, b, c_in, s, c_out : bit;
+  signal test_vector : bit_vector(1 to 3);
+
+begin
+
+  dut : entity work.full_adder
+    port map ( a => a, b => b, c_in => c_in, s => s, c_out => c_out );
+
+  all_possible_values ( test_vector, 10 ns );
+
+  (a, b, c_in) <= test_vector;
+
+end architecture test;
+
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_22.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_22.vhd
new file mode 100644
index 0000000..b0bbd0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_22.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity S_R_flipflop is
+  port ( s, r : in bit;  q, q_n : out bit );
+end entity S_R_flipflop;
+
+--------------------------------------------------
+
+architecture functional of S_R_flipflop is
+
+begin
+
+  q <= '1' when s = '1' else
+       '0' when r = '1';
+
+  q_n <= '0' when s = '1' else
+         '1' when r = '1';
+
+  check : assert not (s = '1' and r = '1')
+    report "Incorrect use of S_R_flip_flop: s and r both '1'";
+
+end architecture functional;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_23.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_23.vhd
new file mode 100644
index 0000000..70e4026
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_23.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_23.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity S_R_flipflop is
+  port ( s, r : in bit;  q, q_n : out bit );
+
+begin
+
+  check : assert not (s = '1' and r = '1')
+    report "Incorrect use of S_R_flip_flop: s and r both '1'";
+
+end entity S_R_flipflop;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_24.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_24.vhd
new file mode 100644
index 0000000..5c4e06c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_24.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_24.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ROM is
+  port ( address : in natural;
+         data : out bit_vector(0 to 7);
+         enable : in bit );
+
+begin
+
+  trace_reads : process (enable) is
+  begin
+    if enable = '1' then
+      report "ROM read at time " & time'image(now)
+        & " from address " & natural'image(address);
+    end if;
+  end process trace_reads;
+
+end entity ROM;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_25.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_25.vhd
new file mode 100644
index 0000000..a608cc4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_25.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_25.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity reg4 is
+  port ( clk, clr, d0, d1, d2, d3 : in bit;
+         q0, q1, q2, q3 : out bit );
+end entity reg4;
+
+architecture struct of reg4 is
+begin
+
+  bit0 : entity work.edge_triggered_Dff(behavioral)
+    port map (d0, clk, clr, q0);
+  bit1 : entity work.edge_triggered_Dff(behavioral)
+    port map (d1, clk, clr, q1);
+  bit2 : entity work.edge_triggered_Dff(behavioral)
+    port map (d2, clk, clr, q2);
+  bit3 : entity work.edge_triggered_Dff(behavioral)
+    port map (d3, clk, clr, q3);
+
+end architecture struct;
+
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_27.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_27.vhd
new file mode 100644
index 0000000..c4596e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_27.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_27.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+use work.counter_types.all;
+
+-- end not in book
+
+
+entity counter is
+  port ( clk, clr : in bit;
+         q0, q1 : out digit );
+end entity counter;
+
+--------------------------------------------------
+
+architecture registered of counter is
+
+  signal current_val0, current_val1, next_val0, next_val1 : digit;
+
+begin
+
+  val0_reg : entity work.reg4(struct)
+    port map ( d0 => next_val0(0), d1 => next_val0(1),
+               d2 => next_val0(2), d3 => next_val0(3),
+               q0 => current_val0(0), q1 => current_val0(1),
+               q2 => current_val0(2), q3 => current_val0(3),
+               clk => clk, clr => clr );
+
+  val1_reg : entity work.reg4(struct)
+    port map ( d0 => next_val1(0), d1 => next_val1(1),
+               d2 => next_val1(2), d3 => next_val1(3),
+               q0 => current_val1(0), q1 => current_val1(1),
+               q2 => current_val1(2), q3 => current_val1(3),
+               clk => clk, clr => clr );
+
+  incr0 : entity work.add_1(boolean_eqn) -- . . .;
+    -- not in book
+    port map ( d0 => current_val0(0), d1 => current_val0(1),
+               d2 => current_val0(2), d3 => current_val0(3),
+	       y0 => next_val0(0), y1 => next_val0(1),
+               y2 => next_val0(2), y3 => next_val0(3) );
+  -- end not in book
+
+  incr1 : entity work.add_1(boolean_eqn) -- . . .;
+    -- not in book
+    port map ( d0 => current_val1(0), d1 => current_val1(1),
+               d2 => current_val1(2), d3 => current_val1(3),
+	       y0 => next_val1(0), y1 => next_val1(1),
+               y2 => next_val1(2), y3 => next_val1(3) );
+  -- end not in book
+
+  buf0 : entity work.buf4(basic) -- . . .;
+    -- not in book
+    port map ( a0 => current_val0(0), a1 => current_val0(1),
+               a2 => current_val0(2), a3 => current_val0(3),
+	       y0 => q0(0), y1 => q0(1),
+               y2 => q0(2), y3 => q0(3) );
+  -- end not in book
+
+  buf1 : entity work.buf4(basic) -- . . .;
+    -- not in book
+    port map ( a0 => current_val1(0), a1 => current_val1(1),
+               a2 => current_val1(2), a3 => current_val1(3),
+	       y0 => q1(0), y1 => q1(1),
+               y2 => q1(2), y3 => q1(3) );
+  -- end not in book
+
+end architecture registered;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_28.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_28.vhd
new file mode 100644
index 0000000..78ebc0f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_28.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_28.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity reg is
+  port ( d : in bit_vector(7 downto 0);
+         q : out bit_vector(7 downto 0);
+         clk : in bit );
+end entity reg;
+
+--------------------------------------------------
+
+-- not in book
+
+entity microprocessor is
+end entity microprocessor;
+
+-- end not in book
+
+architecture RTL of microprocessor is
+
+  signal interrupt_req : bit;
+  signal interrupt_level : bit_vector(2 downto 0);
+  signal carry_flag, negative_flag, overflow_flag, zero_flag : bit;
+  signal program_status : bit_vector(7 downto 0);
+  signal clk_PSR : bit;
+  -- . . .
+
+begin
+
+  PSR : entity work.reg
+    port map ( d(7) => interrupt_req,
+               d(6 downto 4) => interrupt_level,
+               d(3) => carry_flag,     d(2) => negative_flag,
+               d(1) => overflow_flag,  d(0) => zero_flag,
+               q => program_status,
+               clk => clk_PSR );
+  -- . . .
+
+end architecture RTL;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_30.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_30.vhd
new file mode 100644
index 0000000..4237bc8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_fg_05_30.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_fg_05_30.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+library widget_cells, wasp_lib;
+
+architecture cell_based of filter is
+
+  -- declaration of signals, etc
+  -- . . .
+
+  -- not in book
+
+  signal clk, filter_clk, accum_en, carry : bit;
+  signal sum, alu_op1, alu_op2, result : bit_vector(31 downto 0);
+
+  -- end not in book
+
+begin
+
+  clk_pad : entity wasp_lib.in_pad
+    port map ( i => clk, z => filter_clk );
+
+  accum : entity widget_cells.reg32
+    port map ( en => accum_en, clk => filter_clk, d => sum,
+               q => result );
+
+  alu : entity work.adder
+    port map ( a => alu_op1, b => alu_op2, y => sum, c => carry );
+
+  -- other component instantiations
+  -- . . .
+
+end architecture cell_based;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_pk_test.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_pk_test.vhd
new file mode 100644
index 0000000..0771d81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_pk_test.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_pk_test.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package stimulus_generators is
+
+  procedure all_possible_values ( signal bv : out bit_vector;
+				  delay_between_values : in delay_length );
+
+end package stimulus_generators;
+
+package body stimulus_generators is
+
+  type digit_table is array ( natural range 0 to 1 ) of bit;
+  constant digit : digit_table := ( '0', '1' );
+
+  function natural_to_bv ( nat : in natural;
+      	      	      	   length : in natural ) return bit_vector is
+
+    variable temp : natural := nat;
+    variable result : bit_vector(0 to length - 1);
+
+  begin
+    for index in result'reverse_range loop
+      result(index) := digit( temp rem 2 );
+      temp := temp / 2;
+    end loop;
+    return result;
+  end function natural_to_bv;
+
+  procedure all_possible_values ( signal bv : out bit_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= natural_to_bv(0, bv'length);
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= natural_to_bv(value, bv'length);
+    end loop;
+  end procedure all_possible_values;
+
+end package body stimulus_generators;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_01.vhd
new file mode 100644
index 0000000..764d324
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_01.vhd
@@ -0,0 +1,30 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity and_or_inv is
+  port ( a1, a2, b1, b2 : in bit := '1';
+	 y : out bit );
+end entity and_or_inv;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_02.vhd
new file mode 100644
index 0000000..f3e942e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_02.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_02 is
+end entity tb_05_02;
+
+
+architecture test of tb_05_02 is
+
+  signal a1, a2, b1, b2, y : bit;
+
+begin
+
+  dut : entity work.and_or_inv(primitive)
+    port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2,
+	       y => y );
+
+  stimulus : process is
+                       subtype stim_vector_type is bit_vector(0 to 3);
+                     type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+                     constant stim_vector : stim_vector_array
+                       := ( "0000",
+                            "0001",
+                            "0010",
+                            "0011",
+                            "0100",
+                            "0101",
+                            "0110",
+                            "0111",
+                            "1000",
+                            "1001",
+                            "1010",
+                            "1011",
+                            "1100",
+                            "1101",
+                            "1110",
+                            "1111" );
+  begin
+    for i in stim_vector'range loop
+      (a1, a2, b1, b2) <= stim_vector(i);
+      wait for 10 ns;
+      assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1))
+	               or (stim_vector(i)(2) and stim_vector(i)(3)) );
+    end loop;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_03.vhd
new file mode 100644
index 0000000..0539399
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_03.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_03 is
+end entity tb_05_03;
+
+
+architecture test of tb_05_03 is
+
+  signal D, clk, clr, Q : bit := '0';
+
+begin
+
+  dut : entity work.edge_triggered_Dff(behavioral)
+    port map ( D => D, clk => clk, clr => clr,
+	       Q => Q );
+
+  stimulus : process is
+  begin
+    D <= '1';	wait for 10 ns;
+    clk <= '1';	wait for 10 ns;
+    D <= '0';	wait for 10 ns;
+    clk <= '0';	wait for 10 ns;
+    D <= '1';	wait for 10 ns;
+    clr <= '1';	wait for 10 ns;
+    clk <= '1';	wait for 10 ns;
+    clr <= '0';	wait for 10 ns;
+    clk <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_04.vhd
new file mode 100644
index 0000000..0eb5f3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_04.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_04 is
+end entity tb_05_04;
+
+architecture test of tb_05_04 is
+
+  signal a, b, sel, z : bit;
+
+begin
+
+  dut : entity work.mux2(behavioral)
+    port map ( a => a, b => b, sel => sel, z => z );
+
+  stimulus : process is
+                       subtype stim_vector_type is bit_vector(0 to 3);
+                     type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+                     constant stim_vector : stim_vector_array
+                       := ( "0000",
+                            "0100",
+                            "1001",
+                            "1101",
+                            "0010",
+                            "0111",
+                            "1010",
+                            "1111" );
+  begin
+    for i in stim_vector'range loop
+      (a, b, sel) <= stim_vector(i)(0 to 2);
+      wait for 10 ns;
+      assert z = stim_vector(i)(3);
+    end loop;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_05.vhd
new file mode 100644
index 0000000..1c90118
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_05.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_05 is
+end entity tb_05_05;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of tb_05_05 is
+
+  signal a, b : std_ulogic := '0';
+  signal y : std_ulogic;
+
+begin
+
+  dut : entity work.and2(detailed_delay)
+    port map ( a => a, b => b, y => y );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    a <= '1';	wait for 10 ns;
+    b <= '1';	wait for 10 ns;
+    b <= '0';	wait for 10 ns;
+
+    b <= '1', '0' after  250 ps;   wait for 10 ns;
+    b <= '1', '0' after  350 ps;   wait for 10 ns;
+    b <= '1', '0' after  450 ps;   wait for 10 ns;
+    b <= '1', '0' after  550 ps;   wait for 10 ns;
+    b <= '1', '0' after  650 ps;   wait for 10 ns;
+    b <= '1', '0' after  750 ps;   wait for 10 ns;
+    b <= '1', '0' after  850 ps;   wait for 10 ns;
+
+    b <= '1';	wait for 10 ns;
+    b <= '0', '1' after  250 ps;   wait for 10 ns;
+    b <= '0', '1' after  350 ps;   wait for 10 ns;
+    b <= '0', '1' after  450 ps;   wait for 10 ns;
+
+    b <= 'X';  wait for 10 ns;
+    b <= '0';  wait for 10 ns;
+    b <= 'X', '0' after 250 ps;   wait for 10 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_06.vhd
new file mode 100644
index 0000000..22e466d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_06.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_06 is
+end entity tb_05_06;
+
+
+architecture test of tb_05_06 is
+
+  signal s, r : bit := '0';
+  signal q, q_n : bit;
+
+begin
+
+  dut : entity work.S_R_flipflop(functional)
+    port map ( s => s, r => r, q => q, q_n => q_n );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd
new file mode 100644
index 0000000..8e4ecdc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture functional of S_R_flipflop is
+
+begin
+
+  q <= '1' when s = '1' else
+       '0' when r = '1';
+
+  q_n <= '0' when s = '1' else
+         '1' when r = '1';
+
+end architecture functional;
+
+
+entity tb_05_07 is
+end entity tb_05_07;
+
+
+architecture test of tb_05_07 is
+
+  signal s, r : bit := '0';
+  signal q, q_n : bit;
+
+begin
+
+  dut : entity work.S_R_flipflop(functional)
+    port map ( s => s, r => r, q => q, q_n => q_n );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_08.vhd
new file mode 100644
index 0000000..09be1b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_08.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture do_nothing of ROM is
+begin
+end architecture do_nothing;
+
+
+entity tb_05_08 is
+end entity tb_05_08;
+
+
+architecture test of tb_05_08 is
+
+  signal address : natural := 0;
+  signal data : bit_vector(0 to 7);
+  signal enable : bit := '0';
+
+begin
+
+  dut : entity work.ROM(do_nothing)
+    port map ( address => address, data => data, enable => enable );
+
+  stimulus : process is
+  begin
+    wait for 100 ns;
+    address <= 1000;  wait for 10 ns;
+    enable <= '1', '0' after 10 ns;  wait for 90 ns;
+    address <= 1004;  wait for 10 ns;
+    enable <= '1', '0' after 10 ns;  wait for 90 ns;
+    address <= 1008;  wait for 10 ns;
+    enable <= '1', '0' after 10 ns;  wait for 90 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_09.vhd
new file mode 100644
index 0000000..67ea946
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_09.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_09 is
+end entity tb_05_09;
+
+
+architecture test of tb_05_09 is
+
+  signal clk, clr, d0, d1, d2, d3 : bit := '0';
+  signal q0, q1, q2, q3 : bit;
+
+begin
+
+  dut : entity work.reg4(struct)
+    port map ( clk => clk, clr => clr,
+	       d0 => d0, d1 => d1, d2 => d2, d3 => d3,
+	       q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
+
+  stimulus : process is
+  begin
+    (d3, d2, d1, d0) <= bit_vector'(b"1010");	wait for 10 ns;
+    clk <= '1';					wait for 10 ns;
+    (d3, d2, d1, d0) <= bit_vector'(b"0101");	wait for 10 ns;
+    clk <= '0';					wait for 10 ns;
+    (d3, d2, d1, d0) <= bit_vector'(b"1111");	wait for 10 ns;
+    clr <= '1';					wait for 10 ns;
+    clk <= '1';					wait for 10 ns;
+    clr <= '0';					wait for 10 ns;
+    clk <= '0';					wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_10.vhd
new file mode 100644
index 0000000..9a82004
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_10.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity add_1 is
+  port ( d0, d1, d2, d3 : in bit;
+         y0, y1, y2, y3 : out  bit );
+end entity add_1;
+
+
+architecture boolean_eqn of add_1 is
+begin
+
+  y0 <= not d0 after 4 ns;
+
+  y1 <= (not d1 and d0)
+        or (d1 and not d0) after 4 ns;
+
+  y2 <= (not d2 and d1 and d0)
+	or (d2 and not (d1 and d0)) after 4 ns;
+
+  y3 <= (not d3 and d2 and d1 and d0)
+	or (d3 and not (d2 and d1 and d0)) after 4 ns;
+
+end architecture boolean_eqn;
+
+
+entity buf4 is
+  port ( a0, a1, a2, a3 : in bit;
+         y0, y1, y2, y3 : out  bit );
+end entity buf4;
+
+
+architecture basic of buf4 is
+begin
+
+  y0 <= a0 after 2 ns;
+  y1 <= a1 after 2 ns;
+  y2 <= a2 after 2 ns;
+  y3 <= a3 after 2 ns;
+
+end architecture basic;
+
+
+package counter_types is
+
+  subtype digit is bit_vector(3 downto 0);
+
+end package counter_types;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_11.vhd
new file mode 100644
index 0000000..4c11758
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_11.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity tb_05_11 is
+end entity tb_05_11;
+
+
+use work.counter_types.all;
+
+architecture test of tb_05_11 is
+
+  signal clk, clr : bit := '0';
+  signal q0, q1 : digit;
+
+begin
+
+  dut : entity work.counter(registered)
+    port map ( clk => clk, clr => clr,
+               q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 20 ns;
+
+  clr_gen : clr <= '1' after 95 ns,
+		   '0' after 135 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_12.vhd
new file mode 100644
index 0000000..2410f1c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_12.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity in_pad is
+  port ( i : in bit;  z : out bit );
+end entity in_pad;
+
+
+entity reg32 is
+  port ( en : in bit;  clk : in bit;  d : in bit_vector(31 downto 0);
+  q : out bit_vector(31 downto 0) );
+end entity reg32;
+
+
+entity adder is
+  port ( a, b : in bit_vector(31 downto 0);
+         y : out bit_vector(31 downto 0);
+	 c : out bit );
+end entity adder;
+
+
+entity filter is
+end entity filter;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_13.vhd
new file mode 100644
index 0000000..337443a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_13.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_05_tb_05_13.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package tb_05_13 is
+
+  subtype word is integer;
+
+end package tb_05_13;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca-b.vhd
new file mode 100644
index 0000000..dbdeec0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca-b.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_acca-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of accumulator_adder is
+begin
+
+  behavior : process (a, b) is
+
+                              constant Tpd_in_out : time := 3 ns;
+                            variable carry_in : std_ulogic;
+                            variable carry_out : std_ulogic := '0';
+
+  begin
+    for index in 0 to 21 loop
+      carry_in := carry_out;  -- of previous bit
+      s(index) <= a(index) xor b(index) xor carry_in after Tpd_in_out;
+      carry_out := (a(index) and b(index))
+      	      	   or (carry_in and (a(index) xor b(index)));
+    end loop;
+    ovf <= carry_out xor carry_in after Tpd_in_out;  -- ovf is carry_out /= carry_in
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca.vhd
new file mode 100644
index 0000000..450ca29
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_acca.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_acca.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity accumulator_adder is
+  port ( a, b : in std_ulogic_vector(21 downto 0);
+         s : out std_ulogic_vector(21 downto 0);
+         ovf : out std_ulogic );
+end entity accumulator_adder;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd
new file mode 100644
index 0000000..2e9a327
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr-b.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_accr-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of accumulator_reg is
+begin
+
+  behavior : process (clk) is
+
+                             constant Tpd_clk_out : time := 3 ns;
+
+  begin
+    if rising_edge(clk) then
+      if To_X01(clr) = '1' then
+        q <= (others => '0') after Tpd_clk_out;
+      else
+        q <= d after Tpd_clk_out;
+      end if;
+    end if;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr.vhd
new file mode 100644
index 0000000..96cb4ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_accr.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_accr.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity accumulator_reg is
+                 port ( clk : in std_ulogic;
+                        clr : in std_ulogic;
+                        d : in std_ulogic_vector(21 downto 0);
+                        q : out std_ulogic_vector(21 downto 0) );
+               end entity accumulator_reg;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-b.vhd
new file mode 100644
index 0000000..6fb77e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-b.vhd
@@ -0,0 +1,114 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mac-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of mac is
+
+  constant Tpd_clk_out : time := 3 ns;
+
+  signal fp_x_real, fp_x_imag,
+    fp_y_real, fp_y_imag,
+    fp_s_real, fp_s_imag : real := 0.0;
+
+begin
+
+  x_real_converter : entity work.to_fp(behavioral)
+    port map ( x_real, fp_x_real );
+
+  x_imag_converter : entity work.to_fp(behavioral)
+    port map ( x_imag, fp_x_imag );
+
+  y_real_converter : entity work.to_fp(behavioral)
+    port map ( y_real, fp_y_real );
+
+  y_imag_converter : entity work.to_fp(behavioral)
+    port map ( y_imag, fp_y_imag );
+
+  behavior : process (clk) is
+
+                             variable input_x_real, input_x_imag, input_y_real, input_y_imag : real := 0.0;
+                           variable real_part_product_1, real_part_product_2,
+                             imag_part_product_1, imag_part_product_2 : real := 0.0;
+                           variable real_product, imag_product : real := 0.0;
+                           variable real_sum, imag_sum : real := 0.0;
+                           variable real_accumulator_ovf, imag_accumulator_ovf : boolean := false;
+
+                           type boolean_to_stdulogic_table is array (boolean) of std_ulogic;
+                           constant boolean_to_stdulogic : boolean_to_stdulogic_table
+                             := (false => '0', true => '1');
+
+  begin
+    if rising_edge(clk) then
+      -- work from the end of the pipeline back to the start, so as
+      -- not to overwrite previous results in pipeline registers before
+      -- they are used
+
+      -- update accumulator and generate outputs
+      if To_X01(clr) = '1' then
+        real_sum := 0.0;
+        real_accumulator_ovf := false;
+        imag_sum := 0.0;
+        imag_accumulator_ovf := false;
+      else
+        real_sum := real_product + real_sum;
+        real_accumulator_ovf := real_accumulator_ovf
+                                or real_sum < -16.0 or real_sum >= +16.0;
+        imag_sum := imag_product + imag_sum;
+        imag_accumulator_ovf := imag_accumulator_ovf 
+                                or imag_sum < -16.0 or imag_sum >= +16.0;
+      end if;
+      fp_s_real <= real_sum after Tpd_clk_out;
+      fp_s_imag <= imag_sum after Tpd_clk_out;
+      ovf <= boolean_to_stdulogic(
+        real_accumulator_ovf or imag_accumulator_ovf
+        or real_sum < -1.0 or real_sum >= +1.0
+        or imag_sum < -1.0 or imag_sum >= +1.0 )
+             after Tpd_clk_out;
+
+      -- update product registers using partial products
+      real_product := real_part_product_1 - real_part_product_2;
+      imag_product := imag_part_product_1 + imag_part_product_2;
+
+      -- update partial product registers using latched inputs
+      real_part_product_1 := input_x_real * input_y_real;
+      real_part_product_2 := input_x_imag * input_y_imag;
+      imag_part_product_1 := input_x_real * input_y_imag;
+      imag_part_product_2 := input_x_imag * input_y_real;
+
+      -- update input registers using MAC inputs
+      input_x_real := fp_x_real;
+      input_x_imag := fp_x_imag;
+      input_y_real := fp_y_real;
+      input_y_imag := fp_y_imag;
+    end if;
+  end process behavior;
+
+  s_real_converter : entity work.to_vector(behavioral)
+    port map ( fp_s_real, s_real );
+
+  s_imag_converter : entity work.to_vector(behavioral)
+    port map ( fp_s_imag, s_imag );
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-r.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-r.vhd
new file mode 100644
index 0000000..a0f61b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac-r.vhd
@@ -0,0 +1,167 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mac-r.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture rtl of mac is
+
+  signal pipelined_x_real,
+    pipelined_x_imag,
+    pipelined_y_real, 
+    pipelined_y_imag : std_ulogic_vector(15 downto 0);
+  signal real_part_product_1, 
+    real_part_product_2,
+    imag_part_product_1, 
+    imag_part_product_2 : std_ulogic_vector(31 downto 0);
+  signal pipelined_real_part_product_1,
+    pipelined_real_part_product_2,
+    pipelined_imag_part_product_1,
+    pipelined_imag_part_product_2 : std_ulogic_vector(31 downto 0);
+  signal real_product, 
+    imag_product : std_ulogic_vector(32 downto 0);
+  signal pipelined_real_product,
+    pipelined_imag_product : std_ulogic_vector(19 downto 0);
+  signal real_sum,
+    imag_sum : std_ulogic_vector(21 downto 0);
+  signal real_accumulator_ovf,
+    imag_accumulator_ovf : std_ulogic;
+  signal pipelined_real_sum,
+    pipelined_imag_sum : std_ulogic_vector(21 downto 0);
+  signal pipelined_real_accumulator_ovf,
+    pipelined_imag_accumulator_ovf : std_ulogic;
+
+begin
+
+  x_real_input_reg : entity work.reg(behavioral)
+    port map ( clk => clk, d => x_real, q => pipelined_x_real );
+
+  x_imag_input_reg : entity work.reg(behavioral)
+    port map ( clk => clk, d => x_imag, q => pipelined_x_imag );
+
+  y_real_input_reg : entity work.reg(behavioral)
+    port map ( clk => clk, d => y_real, q => pipelined_y_real );
+
+  y_imag_input_reg : entity work.reg(behavioral)
+    port map ( clk => clk, d => y_imag, q => pipelined_y_imag );
+
+  real_mult_1 : entity work.multiplier(behavioral)
+    port map ( a => pipelined_x_real, b => pipelined_y_real,
+	       p => real_part_product_1 );
+
+  real_mult_2 : entity work.multiplier(behavioral)
+    port map ( a => pipelined_x_imag, b => pipelined_y_imag,
+	       p => real_part_product_2 );
+
+  imag_mult_1 : entity work.multiplier(behavioral)
+    port map ( a => pipelined_x_real, b => pipelined_y_imag,
+	       p => imag_part_product_1 );
+
+  imag_mult_2 : entity work.multiplier(behavioral)
+    port map ( a => pipelined_x_imag, b => pipelined_y_real,
+	       p => imag_part_product_2 );
+
+  real_part_product_reg_1 : entity work.reg(behavioral)
+    port map ( clk => clk, d => real_part_product_1,
+	       q => pipelined_real_part_product_1 );
+
+  real_part_product_reg_2 : entity work.reg(behavioral)
+    port map ( clk => clk, d => real_part_product_2,
+	       q => pipelined_real_part_product_2 );
+
+  imag_part_product_reg_1 : entity work.reg(behavioral)
+    port map ( clk => clk, d => imag_part_product_1,
+	       q => pipelined_imag_part_product_1 );
+
+  imag_part_product_reg_2 : entity work.reg(behavioral)
+    port map ( clk => clk, d => imag_part_product_2,
+	       q => pipelined_imag_part_product_2 );
+
+  real_product_subtracter : entity work.product_adder_subtracter(behavioral)
+    port map ( mode => '1',
+               a => pipelined_real_part_product_1,
+	       b => pipelined_real_part_product_2,
+	       s => real_product );
+
+  imag_product_adder : entity work.product_adder_subtracter(behavioral)
+    port map ( mode => '0',
+               a => pipelined_imag_part_product_1,
+	       b => pipelined_imag_part_product_2,
+	       s => imag_product );
+
+  real_product_reg : entity work.reg(behavioral)
+    port map ( clk => clk,
+	       d => real_product(32 downto 13),
+	       q => pipelined_real_product );
+
+  imag_product_reg : entity work.reg(behavioral)
+    port map ( clk => clk,
+	       d => imag_product(32 downto 13),
+	       q => pipelined_imag_product );
+
+  real_accumulator : entity work.accumulator_adder(behavioral)
+    port map ( a(19 downto 0) => pipelined_real_product(19 downto 0),
+	       a(20) => pipelined_real_product(19),
+	       a(21) => pipelined_real_product(19),
+	       b => pipelined_real_sum,
+	       s => real_sum,
+	       ovf => real_accumulator_ovf );
+
+  imag_accumulator : entity work.accumulator_adder(behavioral)
+    port map ( a(19 downto 0) => pipelined_imag_product(19 downto 0),
+	       a(20) => pipelined_imag_product(19),
+	       a(21) => pipelined_imag_product(19),
+	       b => pipelined_imag_sum,
+	       s => imag_sum,
+	       ovf => imag_accumulator_ovf );
+
+  real_accumulator_reg : entity work.accumulator_reg(behavioral)
+    port map ( clk => clk, clr => clr,
+	       d => real_sum,  q => pipelined_real_sum );
+
+  imag_accumulator_reg : entity work.accumulator_reg(behavioral)
+    port map ( clk => clk, clr => clr,
+	       d => imag_sum,  q => pipelined_imag_sum );
+
+  real_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
+    port map ( clk => clk,
+               set => real_accumulator_ovf, clr => clr,
+	       q => pipelined_real_accumulator_ovf );
+
+  imag_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
+    port map ( clk => clk,
+               set => imag_accumulator_ovf, clr => clr,
+	       q => pipelined_imag_accumulator_ovf );
+
+  s_real <= pipelined_real_sum(21) & pipelined_real_sum(16 downto 2);
+
+  s_imag <= pipelined_imag_sum(21) & pipelined_imag_sum(16 downto 2);
+
+  result_overflow_logic : entity work.overflow_logic(behavioral)
+    port map ( real_accumulator_ovf => pipelined_real_accumulator_ovf,
+	       imag_accumulator_ovf => pipelined_imag_accumulator_ovf,
+	       real_sum => pipelined_real_sum(21 downto 17),
+	       imag_sum => pipelined_imag_sum(21 downto 17),
+	       ovf => ovf );
+
+end architecture rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac.vhd
new file mode 100644
index 0000000..7519f5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mac.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mac.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mac is
+  port ( clk, clr : in std_ulogic;
+         x_real : in std_ulogic_vector(15 downto 0);
+         x_imag : in std_ulogic_vector(15 downto 0);
+         y_real : in std_ulogic_vector(15 downto 0);
+         y_imag : in std_ulogic_vector(15 downto 0);
+         s_real : out std_ulogic_vector(15 downto 0);
+         s_imag : out std_ulogic_vector(15 downto 0);
+         ovf : out std_ulogic );
+end entity mac;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bb.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bb.vhd
new file mode 100644
index 0000000..1d85d4b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bb.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mact-bb.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture bench_behavioral of mac_test is
+
+  signal clk, clr, ovf : std_ulogic := '0';
+  signal x_real, x_imag,
+    y_real, y_imag,
+    s_real, s_imag : std_ulogic_vector(15 downto 0);
+
+  type complex is record
+                    re, im : real;
+                  end record;
+
+  signal x, y, s : complex := (0.0, 0.0);
+
+  constant Tpw_clk : time := 50 ns;
+
+begin
+
+  x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
+  x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
+  y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
+  y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
+
+  dut : entity work.mac(behavioral)
+    port map ( clk, clr,
+               x_real, x_imag, y_real, y_imag, s_real, s_imag,
+               ovf );
+
+  s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
+  s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
+
+
+  clock_gen : process is
+  begin
+    clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
+    wait for 2 * Tpw_clk;
+  end process clock_gen;
+
+
+  stimulus : process is
+  begin
+    -- first sequence
+    clr <= '1';  wait until clk = '0';
+    x <= (+0.5, +0.5);  y <= (+0.5, +0.5);  clr <= '1';  wait until clk = '0';
+    x <= (+0.2, +0.2);  y <= (+0.2, +0.2);  clr <= '1';  wait until clk = '0';
+    x <= (+0.1, -0.1);  y <= (+0.1, +0.1);  clr <= '1';  wait until clk = '0';
+    x <= (+0.1, -0.1);  y <= (+0.1, +0.1);  clr <= '0';  wait until clk = '0';
+
+    -- should be (0.4, 0.58) when it falls out the other end
+
+    clr <= '0';  wait until clk = '0';
+    x <= (+0.5, +0.5);  y <= (+0.5, +0.5);  clr <= '0';  wait until clk = '0';
+    x <= (+0.5, +0.5);  y <= (+0.1, +0.1);  clr <= '0';  wait until clk = '0';
+    x <= (+0.5, +0.5);  y <= (+0.5, +0.5);  clr <= '1';  wait until clk = '0';
+    x <= (-0.5, +0.5);  y <= (-0.5, +0.5);  clr <= '0';  wait until clk = '0';
+    clr <= '0';  wait until clk = '0';
+    clr <= '0';  wait until clk = '0';
+    clr <= '0';  wait until clk = '0';
+    clr <= '1';  wait until clk = '0';
+
+    wait;
+  end process stimulus;
+
+end architecture bench_behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-br.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-br.vhd
new file mode 100644
index 0000000..c6d3f56
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-br.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mact-br.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture bench_rtl of mac_test is
+
+  signal clk, clr, ovf : std_ulogic := '0';
+  signal x_real, x_imag,
+    y_real, y_imag,
+    s_real, s_imag : std_ulogic_vector(15 downto 0);
+
+  type complex is record
+                    re, im : real;
+                  end record;
+
+  signal x, y, s : complex := (0.0, 0.0);
+
+  constant Tpw_clk : time := 50 ns;
+
+begin
+
+  x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
+  x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
+  y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
+  y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
+
+  dut : entity work.mac(rtl)
+    port map (clk, clr,
+              x_real, x_imag, y_real, y_imag, s_real, s_imag,
+              ovf );
+
+  s_real_converter : entity work.to_fp(behavioral) port map (s_real, s.re);
+  s_imag_converter : entity work.to_fp(behavioral) port map (s_imag, s.im);
+
+
+  clock_gen : process is
+  begin
+    clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
+    wait for 2 * Tpw_clk;
+  end process clock_gen;
+
+
+  stimulus : process is
+  begin
+    -- first sequence
+    clr <= '1';	wait until clk = '0';
+    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);	clr <= '1';	wait until clk = '0';
+    x <= (+0.2, +0.2);	y <= (+0.2, +0.2);	clr <= '1';	wait until clk = '0';
+    x <= (+0.1, -0.1);	y <= (+0.1, +0.1);	clr <= '1';	wait until clk = '0';
+    x <= (+0.1, -0.1);	y <= (+0.1, +0.1);	clr <= '0';	wait until clk = '0';
+
+    -- should be (0.4, 0.58) when it falls out the other end
+
+    clr <= '0';	wait until clk = '0';
+    x <= ( 0.5,  0.5);	y <= ( 0.5,  0.5);	clr <= '0';	wait until clk = '0';
+    x <= ( 0.5,  0.5);	y <= ( 0.1,  0.1);	clr <= '0';	wait until clk = '0';
+    x <= ( 0.5,  0.5);	y <= ( 0.5,  0.5);	clr <= '1';	wait until clk = '0';
+    x <= (-0.5,  0.5);	y <= (-0.5,  0.5);	clr <= '0';	wait until clk = '0';
+    clr <= '0';	wait until clk = '0';
+    clr <= '0';	wait until clk = '0';
+    clr <= '0';	wait until clk = '0';
+    clr <= '1';	wait until clk = '0';
+
+    wait;
+  end process stimulus;
+
+end architecture bench_rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bv.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bv.vhd
new file mode 100644
index 0000000..92685e1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact-bv.vhd
@@ -0,0 +1,122 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mact-bv.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture bench_verify of mac_test is
+
+  signal clk, clr, behavioral_ovf, rtl_ovf : std_ulogic := '0';
+  signal x_real, x_imag,
+    y_real, y_imag,
+    behavioral_s_real, behavioral_s_imag,
+    rtl_s_real, rtl_s_imag : std_ulogic_vector(15 downto 0);
+
+  type complex is record
+                    re, im : real;
+                  end record;
+
+  signal x, y, behavioral_s, rtl_s : complex := (0.0, 0.0);
+
+  constant Tpw_clk : time := 50 ns;
+
+begin
+
+  x_real_converter : entity work.to_vector(behavioral) port map (x.re, x_real);
+  x_imag_converter : entity work.to_vector(behavioral) port map (x.im, x_imag);
+  y_real_converter : entity work.to_vector(behavioral) port map (y.re, y_real);
+  y_imag_converter : entity work.to_vector(behavioral) port map (y.im, y_imag);
+
+  dut_behavioral : entity work.mac(behavioral)
+    port map ( clk, clr,
+               x_real, x_imag, y_real, y_imag,
+               behavioral_s_real, behavioral_s_imag, behavioral_ovf );
+
+  dut_rtl : entity work.mac(rtl)
+    port map ( clk, clr,
+               x_real, x_imag, y_real, y_imag,
+               rtl_s_real, rtl_s_imag, rtl_ovf );
+
+  behavioral_s_real_converter :
+    entity work.to_fp(behavioral) port map (behavioral_s_real, behavioral_s.re);
+  behavioral_s_imag_converter :
+    entity work.to_fp(behavioral) port map (behavioral_s_imag, behavioral_s.im);
+
+  rtl_s_real_converter :
+    entity work.to_fp(behavioral) port map (rtl_s_real, rtl_s.re);
+  rtl_s_imag_converter :
+    entity work.to_fp(behavioral) port map (rtl_s_imag, rtl_s.im);
+
+
+  clock_gen : process is
+  begin
+    clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
+    wait for 2 * Tpw_clk;
+  end process clock_gen;
+
+
+  stimulus : process is
+  begin
+    -- first sequence
+    clr <= '1';  wait until clk = '0';
+    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);  clr <= '1';	 wait until clk = '0';
+    x <= (+0.2, +0.2);	y <= (+0.2, +0.2);  clr <= '1';	 wait until clk = '0';
+    x <= (+0.1, -0.1);	y <= (+0.1, +0.1);  clr <= '1';	 wait until clk = '0';
+    x <= (+0.1, -0.1);	y <= (+0.1, +0.1);  clr <= '0';	 wait until clk = '0';
+
+    -- should be (0.4, 0.58) when it falls out the other end
+
+    clr <= '0';	 wait until clk = '0';
+    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);  clr <= '0';	 wait until clk = '0';
+    x <= (+0.5, +0.5);	y <= (+0.1, +0.1);  clr <= '0';	 wait until clk = '0';
+    x <= (+0.5, +0.5);	y <= (+0.5, +0.5);  clr <= '1';	 wait until clk = '0';
+    x <= (-0.5, +0.5);	y <= (-0.5, +0.5);  clr <= '0';	 wait until clk = '0';
+    clr <= '0';	 wait until clk = '0';
+    clr <= '0';	 wait until clk = '0';
+    clr <= '0';	 wait until clk = '0';
+    clr <= '1';	 wait until clk = '0';
+
+    wait;
+  end process stimulus;
+
+
+  verifier : process
+
+    constant epsilon : real := 4.0E-5;  -- 1-bit error in 15-bit mantissa
+
+  begin
+    wait until clk = '0';
+    assert behavioral_ovf = rtl_ovf
+      report "Overflow flags differ" severity error;
+    if behavioral_ovf = '0' and rtl_ovf = '0' then
+      assert abs (behavioral_s.re - rtl_s.re) < epsilon
+        report "Real sums differ" severity error;
+      assert abs (behavioral_s.im - rtl_s.im) < epsilon
+        report "Imag sums differ" severity error;
+    end if;
+  end process verifier;
+
+end architecture bench_verify;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact.vhd
new file mode 100644
index 0000000..34d8bf2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mact.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mact.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity mac_test is
+
+end entity mac_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult-b.vhd
new file mode 100644
index 0000000..c8b6cec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult-b.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mult-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of multiplier is
+begin
+
+  behavior : process (a, b) is
+
+                              constant Tpd_in_out : time := 40 ns;
+                            variable negative_result  : boolean;
+                            variable op1 : std_ulogic_vector(15 downto 0);
+                            variable op2 : std_ulogic_vector(15 downto 0);
+                            variable result : std_ulogic_vector(31 downto 0);
+                            variable carry_in, carry : std_ulogic;
+
+  begin
+    op1 := to_X01(a);
+    op2 := to_X01(b);
+    -- make both operands positive, remembering sign of result
+    negative_result := (op1(15) = '1') xor (op2(15) = '1');
+    if (op1(15) = '1') then
+      carry := '1';
+      for index in 0 to 15 loop
+        carry_in := carry;
+        carry := carry_in and not op1(index);
+        op1(index) := not op1(index) xor carry_in;
+      end loop;
+    end if;
+    if (op2(15) = '1') then
+      carry := '1';
+      for index in 0 to 15 loop
+        carry_in := carry;
+        carry := carry_in and not op2(index);
+        op2(index) := not op2(index) xor carry_in;
+      end loop;
+    end if;
+    -- do long multiplication
+    result := (others => '0');
+    for count in 0 to 15 loop
+      carry := '0';
+      if (op2(count) = '1') then
+        for index in 0 to 15 loop
+          carry_in := carry;
+          carry := (result(index+count) and op1(index))
+                   or (carry_in and (result(index+count) xor op1(index)));
+          result(index+count) := result(index+count) xor op1(index) xor carry_in;
+        end loop;
+        result(count+16) := carry;
+      end if;
+    end loop;
+    -- result now contains unsigned product, with binary point
+    -- between bits 30 and 29.  assign output with sign adjusted.
+    if negative_result then
+      carry := '1';
+      for index in 0 to 31 loop
+        carry_in := carry;
+        carry := carry_in and not result(index);
+        result(index) := not result(index) xor carry_in;
+      end loop;
+    end if;
+    p <= result after Tpd_in_out;
+  end process behavior;
+
+end architecture behavioral;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult.vhd
new file mode 100644
index 0000000..f6b2ea1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_mult.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_mult.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity multiplier is
+                 port ( a, b : in std_ulogic_vector(15 downto 0);
+                        p : out std_ulogic_vector(31 downto 0) );
+               end entity multiplier;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt-b.vhd
new file mode 100644
index 0000000..8edb61e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt-b.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_multt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               architecture bench of multiplier_test is
+
+                 signal a, b : std_ulogic_vector(15 downto 0) := (others => '0');
+                 signal p : std_ulogic_vector(31 downto 0);
+
+               begin
+
+                 dut : entity work.multiplier(behavioral)
+                   port map (a, b, p);
+
+                 stimulus : process is
+                 begin
+                   a <= X"8000";  b <= X"8000";  --  -1 * -1
+                   wait for 50 ns;
+                   a <= X"0001";  b <= X"0001";  --  2**-15 * 2**-15
+                   wait for 50 ns;
+                   a <= X"0001";  b <= X"0000";  --  2**-15 * 0
+                   wait for 50 ns;
+                   a <= X"0000";  b <= X"0001";  --  0 * 2**-15
+                   wait for 50 ns;
+                   a <= X"0001";  b <= X"8000";  --  2**-15 * -1
+                   wait for 50 ns;
+                   a <= X"8000";  b <= X"0001";  --  -1 * 2**-15
+                   wait for 50 ns;
+                   a <= X"4000";  b <= X"4000";  --  0.5 * 0.5
+                   wait for 50 ns;
+                   a <= X"C000";  b <= X"4000";  --  -0.5 * 0.5
+                   wait for 50 ns;
+                   a <= X"4000";  b <= X"C000";  --  0.5 * -0.5
+                   wait for 50 ns;
+                   a <= X"C000";  b <= X"C000";  --  -0.5 * -0.5
+                   wait for 50 ns;
+                   wait;
+                 end process stimulus;
+
+               end architecture bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt.vhd
new file mode 100644
index 0000000..3befc73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_multt.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_multt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity multiplier_test is
+
+end entity multiplier_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl-b.vhd
new file mode 100644
index 0000000..34d6d18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl-b.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_ovfl-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of overflow_logic is
+
+  constant Tpd_in_out : time := 3 ns;
+
+begin
+
+  ovf <= real_accumulator_ovf or imag_accumulator_ovf
+	 or ( real_sum(21) xor real_sum(20) )
+	 or ( real_sum(21) xor real_sum(19) )
+	 or ( real_sum(21) xor real_sum(18) )
+	 or ( real_sum(21) xor real_sum(17) )
+	 or ( imag_sum(21) xor imag_sum(20) )
+	 or ( imag_sum(21) xor imag_sum(19) )
+	 or ( imag_sum(21) xor imag_sum(18) )
+	 or ( imag_sum(21) xor imag_sum(17) ) after Tpd_in_out;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl.vhd
new file mode 100644
index 0000000..dcaa16c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_ovfl.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_ovfl.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity overflow_logic is
+                 port ( real_accumulator_ovf, imag_accumulator_ovf : in std_ulogic;
+                        real_sum, imag_sum : std_ulogic_vector(21 downto 17);
+                        ovf : out std_ulogic );
+               end entity overflow_logic;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas-b.vhd
new file mode 100644
index 0000000..8d0dfd2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas-b.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_pas-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of product_adder_subtracter is
+begin
+
+  behavior : process (a, b) is
+
+                              constant Tpd_in_out : time := 3 ns;
+                            variable op2 : std_ulogic_vector(b'range);
+                            variable carry_in : std_ulogic;
+                            variable carry_out : std_ulogic;
+
+  begin
+    carry_out := To_X01(mode);
+    if To_X01(mode) = '1' then
+      op2 := not b;
+    else
+      op2 := b;
+    end if;
+    for index in 0 to 31 loop
+      carry_in := carry_out;  -- of previous bit
+      s(index) <= a(index) xor op2(index) xor carry_in after Tpd_in_out;
+      carry_out := (a(index) and op2(index))
+      	      	   or (carry_in and (a(index) xor op2(index)));
+    end loop;
+    s(32) <= a(31) xor op2(31) xor carry_out after Tpd_in_out;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas.vhd
new file mode 100644
index 0000000..04e13bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_pas.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_pas.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity product_adder_subtracter is
+                 port ( mode : in std_ulogic;
+                        a, b : in std_ulogic_vector(31 downto 0);
+                        s : out std_ulogic_vector(32 downto 0) );
+               end entity product_adder_subtracter;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg-b.vhd
new file mode 100644
index 0000000..25081a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg-b.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_reg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of reg is
+begin
+
+  behavior : process (clk) is
+  begin
+    if rising_edge(clk) then
+      q <= d;
+    end if;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg.vhd
new file mode 100644
index 0000000..9ea7c89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_reg.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_reg.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity reg is
+                 port ( clk : in std_ulogic;
+                        d : in std_ulogic_vector;
+                        q : out std_ulogic_vector );
+               end entity reg;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff-b.vhd
new file mode 100644
index 0000000..d1312f8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff-b.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_srff-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of synch_sr_ff is
+begin
+
+  behavior : process (clk) is
+
+                             constant Tpd_clk_out : time := 3 ns;
+
+  begin
+    if rising_edge(clk) then
+      if To_X01(clr) = '1' then
+        q <= '0' after Tpd_clk_out;
+      elsif To_X01(set) = '1' then
+        q <= '1' after Tpd_clk_out;
+      end if;
+    end if;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff.vhd
new file mode 100644
index 0000000..03f0fa2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_srff.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_srff.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity synch_sr_ff is
+                 port ( clk : in std_ulogic;
+                        set, clr : in std_ulogic;
+                        q : out std_ulogic );
+               end entity synch_sr_ff;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp-b.vhd
new file mode 100644
index 0000000..b516476
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp-b.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tofp-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of to_fp is
+
+begin
+
+  behavior : process (vec) is
+
+                             variable temp : bit_vector(vec'range);
+                           variable negative : boolean;
+                           variable int_result : integer;
+
+  begin
+    temp := to_bitvector(vec);
+    negative := temp(temp'left) = '1';
+    if negative then
+      temp := not temp;
+    end if;
+    int_result := 0;
+    for index in vec'range loop	  -- sign bit of temp = '0'
+      int_result := int_result * 2 + bit'pos(temp(index));
+    end loop;
+    if negative then
+      int_result := (-int_result) - 1;
+    end if;
+    -- convert to floating point and scale to [-1, +1)
+    r <= real(int_result) / real(2**15);
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp.vhd
new file mode 100644
index 0000000..05934bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tofp.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity to_fp is
+                 port ( vec : in std_ulogic_vector(15 downto 0);
+                        r : out real );
+               end entity to_fp;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt-b.vhd
new file mode 100644
index 0000000..8feb4ca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt-b.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tofpt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               architecture bench of to_fp_test is
+
+                 signal vec : std_ulogic_vector(15 downto 0);
+                 signal r : real;
+
+               begin
+
+                 dut : entity work.to_fp(behavioral)
+                   port map (vec, r);
+
+                 stimulus : process is
+                 begin
+                   vec <= X"0000";  wait for 10 ns;
+                   vec <= X"8000";  wait for 10 ns;
+                   vec <= X"7FFF";  wait for 10 ns;
+                   vec <= X"4000";  wait for 10 ns;
+                   vec <= X"C000";  wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+               end architecture bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt.vhd
new file mode 100644
index 0000000..8e47204
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofpt.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tofpt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity to_fp_test is
+
+end entity to_fp_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec-b.vhd
new file mode 100644
index 0000000..4574192
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec-b.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tovec-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of to_vector is
+
+begin
+
+  behavior : process (r) is
+
+                           variable temp : integer range -2**15 to 2**15 - 1;
+                         variable negative : boolean;
+                         variable result : std_ulogic_vector(vec'range);
+
+  begin
+    -- scale to [-2**15, +2**15) and convert to integer
+    if r * real(2**15) < real(-2**15) then
+      temp := -2**15;
+    elsif r * real(2**15) >= real(2**15 - 1) then
+      temp := 2**15 - 1;
+    else
+      temp := integer(r * real(2**15));
+    end if;
+    negative := temp < 0;
+    if negative then
+      temp := -(temp + 1);
+    end if;
+    result := (others => '0');
+    for index in result'reverse_range loop
+      result(index) := to_X01(bit'val(temp rem 2));
+      temp := temp / 2;
+      exit when temp = 0;
+    end loop;
+    if negative then
+      result := not result;
+      result(result'left) := '1';
+    end if;
+    vec <= result;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec.vhd
new file mode 100644
index 0000000..1ae6b64
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovec.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tovec.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity to_vector is
+                 port ( r : in real;
+                        vec : out std_ulogic_vector(15 downto 0) );
+               end entity to_vector;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect-b.vhd
new file mode 100644
index 0000000..2f14d5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect-b.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tovect-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               architecture bench of to_vector_test is
+
+                 signal vec : std_ulogic_vector(15 downto 0);
+                 signal r : real := 0.0;
+
+               begin
+
+                 dut : entity work.to_vector(behavioral)
+                   port map (r, vec);
+
+                 stimulus : process is
+                 begin
+                   r <=  0.0;		wait for 10 ns;
+                   r <= -1.0;		wait for 10 ns;
+                   r <= -2.0;		wait for 10 ns;
+                   r <= +0.9999;	wait for 10 ns;
+                   r <= +2.0;		wait for 10 ns;
+                   r <= -0.5;		wait for 10 ns;
+                   r <= +0.5;		wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+               end architecture bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect.vhd
new file mode 100644
index 0000000..7bac2fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tovect.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_06_tovect.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity to_vector_test is
+
+end entity to_vector_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_01.vhd
new file mode 100644
index 0000000..0e49262
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_01.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_01 is
+
+end entity ch_07_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_07_01 is
+begin
+
+
+  process_07_2_a : process is
+
+                             type t1 is (t1_1, t1_2);
+                           type t2 is (t2_1, t2_2);
+                           type t3 is (t3_1, t3_2);
+                           type t4 is (t4_1, t4_2);
+
+                           constant v4 : t4 := t4_1;
+
+                           constant val1 : t1 := t1_1;
+                           constant val2 : t2 := t2_1;
+                           variable var3 : t3 := t3_1;
+                           constant val4 : t4 := t4_1;
+
+                           -- code from book:
+
+                           procedure p ( f1 : in t1;  f2 : in t2;  f3 : out t3;  f4 : in t4 := v4 ) is
+                           begin
+                             -- . . .
+                           end procedure p;
+
+                           -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    p ( val1, val2, var3, val4 );
+    p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 );
+    p ( val1, val2, f4 => open, f3 => var3 );
+    p ( val1, val2, var3 );
+
+    -- end of code from book
+
+    wait;
+  end process process_07_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_02.vhd
new file mode 100644
index 0000000..74ac110
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_02.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_02 is
+
+end entity ch_07_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_07_02 is
+
+  constant val1 : integer := 1;
+
+  procedure p ( signal s1, s2 : in bit;  val1 : in integer ) is
+  begin
+    null;
+  end procedure p;
+
+begin
+
+
+  block_07_3_a : block is
+
+                         signal s1, s2 : bit;
+
+  begin
+
+    -- code from book:
+
+    call_proc : p ( s1, s2, val1 );
+
+    -- end of code from book
+
+  end block block_07_3_a;
+
+
+  ----------------
+
+
+  block_07_3_b : block is
+
+                         signal s1, s2 : bit;
+
+  begin
+
+    -- code from book:
+
+    call_proc : process is
+    begin
+      p ( s1, s2, val1 );
+      wait on s1, s2;
+    end process call_proc;
+
+    -- end of code from book
+
+  end block block_07_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_03.vhd
new file mode 100644
index 0000000..8cc3aa2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_03.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_03 is
+end entity ch_07_03;
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture test of ch_07_03 is
+
+  constant T_delay_adder : delay_length := 10 ns;
+
+  -- code from book:
+
+  function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is
+  begin
+    -- . . .
+    -- not in book
+    return bv1 + bv2;
+    -- end not in book
+  end function bv_add;
+
+  signal source1, source2, sum : bit_vector(0 to 31);
+
+  -- end of code from book
+
+begin
+
+  -- code from book:
+
+  adder : sum <= bv_add(source1, source2) after T_delay_adder;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    wait for 50 ns;
+    source1 <= X"00000002";  source2 <= X"00000003";  wait for 50 ns;
+    source2 <= X"FFFFFFF0";  wait for 50 ns;
+    source1 <= X"00000010";                           wait for 50 ns;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_04.vhd
new file mode 100644
index 0000000..3c39a15
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_04.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_04 is
+
+  -- code from book:
+
+  impure function now return delay_length;
+
+  -- end of code from book
+
+  impure function now return delay_length is
+  begin
+    return std.standard.now;
+  end function now;
+
+  -- end of code from book
+
+end entity ch_07_04;
+
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_05.vhd
new file mode 100644
index 0000000..2ee0eec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_05.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_05.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_05 is
+end entity ch_07_05;
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture test of ch_07_05 is
+
+begin
+
+  process_07_5_a : process is
+
+                             -- code from book:
+
+                             procedure increment ( a : inout integer;   n : in integer := 1 ) is -- . . .
+    -- not in book
+  begin
+    a := a + n;
+  end procedure increment;
+  -- end not in book;
+
+  procedure increment ( a : inout bit_vector;  n : in bit_vector := B"1" ) is -- . . .
+    -- not in book
+  begin
+    a := a + n;
+  end procedure increment;
+  -- end not in book;
+
+  procedure increment ( a : inout bit_vector;  n : in integer := 1 ) is -- . . .
+    -- not in book
+  begin
+    a := a + integer_to_bv(n, a'length);
+  end procedure increment;
+  -- end not in book;
+
+  variable count_int : integer := 2;
+  variable count_bv : bit_vector (15 downto 0) := X"0002";
+
+  -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    increment ( count_int, 2 );
+    increment ( count_int );
+
+    increment ( count_bv, X"0002");
+    increment ( count_bv, 1 );
+
+    -- increment ( count_bv );
+
+    -- end of code from book
+
+    wait;
+  end process process_07_5_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_06.vhd
new file mode 100644
index 0000000..874852c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_06.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_ch_07_06.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_07_06 is
+end entity ch_07_06;
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic;
+
+architecture test of ch_07_06 is
+begin
+
+  process_07_5_b : process is
+
+                             -- code from book:
+
+                             function "+" ( left, right : in bit_vector ) return bit_vector is
+  begin
+    -- . . .
+    -- not in book
+    return bv_arithmetic."+"(left, right);
+    -- end not in book
+  end function "+";
+
+  variable addr_reg : bit_vector(31 downto 0);
+  -- . . .
+
+  -- end of code from book
+
+  -- code from book:
+
+  function "abs" ( right : in bit_vector ) return bit_vector is
+  begin
+    -- . . .
+    -- not in book
+    if right(right'left) = '0' then
+      return right;
+    else
+      return bv_arithmetic."-"(right);
+    end if;
+    -- end not in book
+  end function "abs";
+
+  variable accumulator : bit_vector(31 downto 0);
+  -- . . .
+
+  -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    addr_reg := addr_reg + X"0000_0004";
+
+    -- end of code from book
+
+    accumulator := X"000000FF";
+
+    -- code from book:
+
+    accumulator := abs accumulator;
+
+    -- end of code from book
+
+    accumulator := X"FFFFFFFE";
+    accumulator := abs accumulator;
+
+    wait;
+  end process process_07_5_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_01.vhd
new file mode 100644
index 0000000..d632901
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_01.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_01 is
+end entity fg_07_01;
+
+
+
+architecture test of fg_07_01 is
+
+  shared variable average : real := 0.0;
+  type sample_array is array (positive range <>) of real;
+  constant samples : sample_array :=
+    ( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0 );
+
+  -- code from book
+
+  procedure average_samples is
+    variable total : real := 0.0;
+  begin
+    assert samples'length > 0 severity failure;
+    for index in samples'range loop
+      total := total + samples(index);
+    end loop;
+    average := total / real(samples'length);
+  end procedure average_samples;
+
+  -- end code from book
+
+begin
+
+  -- code from book (in text)
+
+  average_samples;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_02.vhd
new file mode 100644
index 0000000..814f49b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_02.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity control_processor is
+  generic ( Tpd : delay_length := 3 ns );
+end entity control_processor;
+
+-- end not in book
+
+
+
+architecture rtl of control_processor is
+
+  type func_code is (add, subtract);
+
+  signal op1, op2, dest : integer;
+  signal Z_flag : boolean;
+  signal func : func_code;
+  -- . . .
+
+begin
+
+  alu : process is
+
+                  procedure do_arith_op is
+    variable result : integer;
+  begin
+    case func is
+      when add =>
+        result := op1 + op2;
+      when subtract =>
+        result := op1 - op2;
+    end case;
+    dest  <=  result after Tpd;
+    Z_flag  <=  result = 0 after Tpd;
+  end procedure do_arith_op;
+
+  begin
+    -- . . .
+    do_arith_op;
+    -- . . .
+    -- not in book
+    wait on op1, op2, func;
+    -- end not in book
+  end process alu;
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    op1 <= 0;  op2 <= 0;	wait for 10 ns;
+    op1 <= 10; op2 <= 3;	wait for 10 ns;
+    func <= subtract;		wait for 10 ns;
+    op2 <= 10;			wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_03.vhd
new file mode 100644
index 0000000..e993b39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_03.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_03 is
+end entity fg_07_03;
+
+library bv_utilities;
+
+architecture interpreter of fg_07_03 is
+
+  subtype word is bit_vector(31 downto 0);
+
+  signal address_bus, data_bus_in : word := X"0000_0000";
+  signal mem_read, mem_request, mem_ready : bit := '0';
+
+begin
+
+  -- code from book
+
+  instruction_interpreter : process is
+
+                                      variable mem_address_reg, mem_data_reg,
+                                    prog_counter, instr_reg, accumulator, index_reg : word;
+                                    -- . . .
+                                    -- not in book
+                                    type opcode_type is (load_mem);
+                                    constant opcode : opcode_type := load_mem;
+                                    constant displacement : word := X"0000_0010";
+                                    use bv_utilities.bv_arithmetic.all;
+                                    -- end not in book
+
+                                    procedure read_memory is
+                                    begin
+                                      address_bus <= mem_address_reg;
+                                      mem_read <= '1';
+                                      mem_request <= '1';
+                                      wait until mem_ready = '1';
+                                      mem_data_reg := data_bus_in;
+                                      mem_request <= '0';
+                                      wait until mem_ready = '0';
+                                    end procedure read_memory;
+
+  begin
+    -- . . .  -- initialization
+    loop
+      -- fetch next instruction
+      mem_address_reg := prog_counter;
+      read_memory;                           -- call procedure
+      instr_reg := mem_data_reg;
+      -- . . .
+      case opcode is
+        -- . . .
+        when load_mem =>
+          mem_address_reg := index_reg + displacement;
+          read_memory;                        -- call procedure
+          accumulator := mem_data_reg;
+          -- . . .
+      end case;
+    end loop;
+  end process instruction_interpreter;
+
+  -- end code from book
+
+
+  memory : process is
+  begin
+    wait until mem_request = '1';
+    data_bus_in <= X"1111_1111";
+    mem_ready <= '1';
+    wait until mem_request = '0';
+    mem_ready <= '0';
+  end process memory;
+
+end architecture interpreter;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_04.vhd
new file mode 100644
index 0000000..51f5154
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_04.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_04 is
+end entity fg_07_04;
+
+
+
+architecture test of fg_07_04 is
+
+  signal phase1, phase2, reg_file_write_en,
+    A_reg_out_en, B_reg_out_en, C_reg_load_en : bit := '0';
+
+begin
+
+  -- code from book
+
+  control_sequencer : process is
+
+                                procedure control_write_back is
+  begin
+    wait until phase1 = '1';
+    reg_file_write_en <= '1';
+    wait until phase2 = '0';
+    reg_file_write_en <= '0';
+  end procedure control_write_back;
+
+  procedure control_arith_op is
+  begin
+    wait until phase1 = '1';
+    A_reg_out_en <= '1';
+    B_reg_out_en <= '1';
+    wait until phase1 = '0';
+    A_reg_out_en <= '0';
+    B_reg_out_en <= '0';
+    wait until phase2 = '1';
+    C_reg_load_en <= '1';
+    wait until phase2 = '0';
+    C_reg_load_en <= '0';
+    control_write_back;        -- call procedure
+  end procedure control_arith_op;
+
+  -- . . .
+
+  begin
+    -- . . .
+    control_arith_op;          -- call procedure
+    -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process control_sequencer;
+
+  -- end code from book
+
+
+  clock_gen : process is
+  begin
+    phase1 <= '1' after 10 ns, '0' after 20 ns;
+    phase2 <= '1' after 30 ns, '0' after 40 ns;
+    wait for 40 ns;
+  end process clock_gen;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_05.vhd
new file mode 100644
index 0000000..4d07810
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_05.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_05 is
+end entity fg_07_05;
+
+
+architecture interpreter of fg_07_05 is
+
+  subtype word is bit_vector(31 downto 0);
+
+  signal address_bus, data_bus_in : word := X"0000_0000";
+  signal mem_read, mem_request, mem_ready, reset : bit := '0';
+
+begin
+
+  -- code from book
+
+  instruction_interpreter : process is
+
+                                      -- . . .
+
+                                      -- not in book
+                                      variable mem_address_reg, mem_data_reg : word;
+                                    -- end not in book
+
+                                    procedure read_memory is
+                                    begin
+                                      address_bus <= mem_address_reg;
+                                      mem_read <= '1';
+                                      mem_request <= '1';
+                                      wait until mem_ready = '1' or reset = '1';
+                                      if reset = '1' then
+                                        return;
+                                      end if;
+                                      mem_data_reg := data_bus_in;
+                                      mem_request <= '0';
+                                      wait until mem_ready = '0';
+                                    end procedure read_memory;
+
+  begin
+    -- . . .    -- initialization
+    -- not in book
+    if reset = '1' then
+      wait until reset = '0';
+    end if;
+    -- end not in book
+    loop
+      -- . . .
+      read_memory;
+      exit when reset = '1';
+      -- . . .
+    end loop;
+  end process instruction_interpreter;
+
+  -- end code from book
+
+
+  memory : process is
+  begin
+    wait until mem_request = '1';
+    data_bus_in <= X"1111_1111";
+    mem_ready <= '1' after 10 ns;
+    wait until mem_request = '0';
+    mem_ready <= '0' after 10 ns;
+  end process memory;
+
+  reset <= '1' after 85 ns;
+
+end architecture interpreter;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_06.vhd
new file mode 100644
index 0000000..95eb598
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_06.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_06.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_06 is
+end entity fg_07_06;
+
+
+architecture test of fg_07_06 is
+
+  type func_code is (add, subtract);
+
+  signal op1 : integer := 10;
+  signal op2 : integer := 3;
+  signal dest : integer := 0;
+  signal func : func_code := add;
+
+  signal Z_flag : boolean := false;
+
+  constant Tpd : delay_length := 3 ns;
+
+begin
+
+  stimulus : process is
+
+                       -- code from book
+
+                       procedure do_arith_op ( op : in func_code ) is
+    variable result : integer;
+  begin
+    case op is
+      when add =>
+        result := op1 + op2;
+      when subtract =>
+        result := op1 - op2;
+    end case;
+    dest  <=  result after Tpd;
+    Z_flag  <=  result = 0 after Tpd;
+  end procedure do_arith_op;
+
+  -- end code from book
+
+  begin
+    wait for 10 ns;
+
+    -- code from book (in text)
+
+    do_arith_op ( add );
+
+    -- end code from book
+
+    wait for 10 ns;
+
+    -- code from book (in text)
+
+    do_arith_op ( func );
+
+    -- end code from book
+
+    wait for 10 ns;
+    do_arith_op ( subtract );
+    wait for 10 ns;
+    op2 <= 10;
+    wait for 10 ns;
+    do_arith_op ( subtract );
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_07.vhd
new file mode 100644
index 0000000..72b5d81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_07.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_07.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_07 is
+end entity fg_07_07;
+
+
+architecture test of fg_07_07 is
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  -- code in book
+
+  procedure addu ( a, b : in word32;
+                   result : out word32;  overflow : out boolean ) is
+    variable sum : word32;
+    variable carry : bit := '0';
+  begin
+    for index in sum'reverse_range loop
+      sum(index) := a(index) xor b(index) xor carry;
+      carry := ( a(index) and b(index) ) or ( carry and ( a(index) xor b(index) ) );
+    end loop;
+    result := sum;
+    overflow := carry = '1';
+  end procedure addu;
+
+  -- end code in book
+
+begin
+
+  stimulus : process is
+
+                       -- code in book (in text)
+
+                       variable PC, next_PC : word32;
+                     variable overflow_flag : boolean;
+                     -- . . .
+
+                     -- end code in book
+
+  begin
+    PC := X"0000_0010";
+
+    -- code in book (in text)
+
+    addu ( PC, X"0000_0004", next_PC, overflow_flag);
+
+    -- end code in book
+
+    PC := X"FFFF_FFFC";
+    addu ( PC, X"0000_0004", next_PC, overflow_flag);
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_08.vhd
new file mode 100644
index 0000000..2f04590
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_08.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_08.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_08 is
+end entity fg_07_08;
+
+
+architecture test of fg_07_08 is
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  -- code in book
+
+  procedure negate ( a : inout word32 ) is
+    variable carry_in : bit := '1';
+    variable carry_out : bit;
+  begin
+    a := not a;
+    for index in a'reverse_range loop
+      carry_out :=  a(index) and carry_in;
+      a(index) := a(index) xor carry_in;
+      carry_in := carry_out;
+    end loop;
+  end procedure negate;
+
+  -- end code in book
+
+begin
+
+  stimulus : process is
+
+                       -- code in book (in text)
+
+                       variable op1 : word32;
+                     -- . . .
+
+                     -- end code in book
+
+  begin
+    op1 := X"0000_0002";
+
+    -- code in book (in text)
+
+    negate ( op1 );
+
+    -- end code in book
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_09.vhd
new file mode 100644
index 0000000..96ea3dd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_09.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity receiver is
+end entity receiver;
+
+
+-- code from book
+
+architecture behavioral of receiver is
+
+  -- . . .    -- type declarations, etc
+
+  -- not in book
+
+  subtype packet_index_range is integer range 1 to 8;
+  type packet_array is array (packet_index_range) of bit;
+
+  -- end not in book
+
+  signal recovered_data : bit;
+  signal recovered_clock : bit;
+  -- . . .
+
+  procedure receive_packet ( signal rx_data : in bit;
+                             signal rx_clock : in bit;
+                             data_buffer : out packet_array ) is
+  begin
+    for index in packet_index_range loop
+      wait until rx_clock = '1';
+      data_buffer(index) := rx_data;
+    end loop;
+  end procedure receive_packet;
+
+begin
+
+  packet_assembler : process is
+                               variable packet : packet_array;
+  begin
+    -- . . .
+    receive_packet ( recovered_data, recovered_clock, packet );
+    -- . . .
+  end process packet_assembler;
+
+  -- . . .
+
+
+  -- not in book
+
+  data_generator : recovered_data <= '1' after 5 ns,
+                                     '0' after 15 ns,
+                                     '1' after 25 ns,
+                                     '0' after 35 ns,
+                                     '0' after 45 ns,
+                                     '1' after 55 ns,
+                                     '0' after 65 ns,
+                                     '1' after 75 ns;
+
+  clock_generator : process is
+  begin
+    recovered_clock <= '0' after 2 ns, '1' after 10 ns;
+    wait for 10 ns;
+  end process clock_generator;
+
+  -- end not in book
+
+end architecture behavioral;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_10.vhd
new file mode 100644
index 0000000..5eabc8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_10.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity signal_generator is
+  generic ( period : delay_length := 20 ns;
+            pulse_count : natural := 5 );
+end entity signal_generator;
+
+-- end not in book
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture top_level of signal_generator is
+
+  signal raw_signal : std_ulogic;
+  -- . . .
+
+  procedure generate_pulse_train ( width, separation : in delay_length;
+                                   number : in natural;
+                                   signal s : out std_ulogic ) is
+  begin
+    for count in 1 to number loop
+      s <= '1', '0' after width;
+      wait for width + separation;
+    end loop;
+  end procedure generate_pulse_train;
+
+begin
+
+  raw_signal_generator : process is
+  begin
+    -- . . .
+    generate_pulse_train ( width => period / 2,
+                           separation => period - period / 2,
+                           number => pulse_count,
+                           s => raw_signal );
+    -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process raw_signal_generator;
+
+  -- . . .
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_11.vhd
new file mode 100644
index 0000000..ff33899
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_11.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_11.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_11 is
+end entity fg_07_11;
+
+
+
+architecture test of fg_07_11 is
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  -- code from book
+
+  procedure increment ( a : inout word32;  by : in word32 := X"0000_0001" ) is
+    variable sum : word32;
+    variable carry : bit := '0';
+  begin
+    for index in a'reverse_range loop
+      sum(index) := a(index) xor by(index) xor carry;
+      carry := ( a(index) and by(index) ) or ( carry and ( a(index) xor by(index) ) );
+    end loop;
+    a := sum;
+  end procedure increment;
+
+  -- end code from book
+
+begin
+
+  stimulus : process is
+
+                       variable count : word32 := X"0001_1100";
+
+  begin
+
+    -- code from book (in text)
+
+    increment(count, X"0000_0004");
+
+    increment(count);
+
+    increment(count, by => open);
+
+    -- end code from book
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_12.vhd
new file mode 100644
index 0000000..5a2499d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_12.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_12.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_12 is
+end entity fg_07_12;
+
+
+
+architecture test of fg_07_12 is
+
+  -- code from book
+
+  procedure find_first_set ( v : in bit_vector;
+                             found : out boolean;
+                             first_set_index : out natural ) is
+  begin
+    for index in v'range loop
+      if v(index) = '1' then
+        found := true;
+        first_set_index := index;
+        return;
+      end if;
+    end loop;
+    found := false;
+  end procedure find_first_set;
+
+  -- end code from book
+
+begin
+
+  stimulus : process is
+
+                       -- code from book (in text)
+
+                       variable int_req : bit_vector (7 downto 0);
+                     variable top_priority : natural;
+                     variable int_pending : boolean;
+                     -- . . .
+
+                     -- end code from book
+
+                     constant block_count : natural := 16;
+
+                     -- code from book (in text)
+
+                     variable free_block_map : bit_vector(0 to block_count-1);
+                     variable first_free_block : natural;
+                     variable free_block_found : boolean;
+                     -- . . .
+
+                     -- end code from book
+
+  begin
+    int_req := "00010000";
+
+    -- code from book (in text)
+
+    find_first_set ( int_req, int_pending, top_priority );
+
+    -- end code from book
+
+    free_block_map := (others => '0');
+
+    -- code from book (in text)
+
+    find_first_set ( free_block_map, free_block_found, first_free_block );
+
+    -- end code from book
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_13.vhd
new file mode 100644
index 0000000..ee18696
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_13.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_13.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_13 is
+end entity fg_07_13;
+
+
+
+architecture test of fg_07_13 is
+
+  -- code from book
+
+  procedure bv_lt ( bv1, bv2 : in bit_vector;  result : out boolean ) is
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+  begin
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    result :=  tmp1 < tmp2;
+  end procedure bv_lt;
+
+  -- end code from book
+
+begin
+
+  stimulus : process is
+
+                       subtype byte is bit_vector(0 to 7);
+                     variable result : boolean;
+
+  begin
+    bv_lt( byte'(X"02"), byte'(X"04"), result );
+    assert result;
+
+    bv_lt( byte'(X"02"), byte'(X"02"), result );
+    assert not result;
+
+    bv_lt( byte'(X"02"), byte'(X"02"), result );
+    assert not result;
+
+    bv_lt( byte'(X"FC"), byte'(X"04"), result );
+    assert result;
+
+    bv_lt( byte'(X"04"), byte'(X"FC"), result );
+    assert not result;
+
+    bv_lt( byte'(X"FC"), byte'(X"FC"), result );
+    assert not result;
+
+    bv_lt( byte'(X"FC"), byte'(X"FE"), result );
+    assert result;
+
+    bv_lt( byte'(X"FE"), byte'(X"FC"), result );
+    assert not result;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_14.vhd
new file mode 100644
index 0000000..f610e58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_14.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_14.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_14 is
+end entity fg_07_14;
+
+
+
+architecture test of fg_07_14 is
+
+  -- code from book
+
+  procedure check_setup ( signal data, clock : in bit;
+                          constant Tsu : in time ) is
+  begin
+    if clock'event and clock = '1' then
+      assert data'last_event >= Tsu
+        report "setup time violation" severity error;
+    end if;
+  end procedure check_setup;
+
+  -- end code from book
+
+  signal ready, phi2 : bit := '0';
+  constant Tsu_rdy_clk : delay_length := 4 ns;
+
+begin
+
+  -- code from book (in text)
+
+  check_ready_setup : check_setup ( data => ready, clock => phi2,
+                                    Tsu => Tsu_rdy_clk );
+
+  -- end code from book
+
+  clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0';
+
+  stimulus : ready <= '1' after 4 ns,
+                      '0' after 56 ns,
+                      '1' after 87 ns,
+                      '0' after 130 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_15.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_15.vhd
new file mode 100644
index 0000000..b54a85b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_15.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_15.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_15 is
+end entity fg_07_15;
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of fg_07_15 is
+
+  -- code from book
+
+  procedure generate_clock ( signal clk : out std_ulogic;
+                             constant Tperiod, Tpulse, Tphase : in time ) is
+  begin
+    wait for Tphase;
+    loop
+      clk <= '1', '0' after Tpulse;
+      wait for Tperiod;
+    end loop;
+  end procedure generate_clock;
+
+  -- end code from book
+
+  -- code from book (in text)
+
+  signal phi1, phi2 : std_ulogic := '0';
+  -- . . .
+
+  -- end code from book
+
+begin
+
+  -- code from book (in text)
+
+  gen_phi1 : generate_clock ( phi1, Tperiod => 50 ns, Tpulse => 20 ns,
+                              Tphase => 0 ns );
+
+  gen_phi2 : generate_clock ( phi2, Tperiod => 50 ns, Tpulse => 20 ns,
+                              Tphase => 25 ns );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_16.vhd
new file mode 100644
index 0000000..4069cc7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_16.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_16 is
+end entity fg_07_16;
+
+
+
+architecture test of fg_07_16 is
+
+  -- code from book
+
+  function limit ( value, min, max : integer ) return integer is
+  begin
+    if value > max then
+      return max;
+    elsif value < min then
+      return min;
+    else
+      return value;
+    end if;
+  end function limit;
+
+  -- end code from book
+
+begin
+
+  tester : process is
+
+                     variable new_temperature, current_temperature, increment : integer;
+                   variable new_motor_speed, old_motor_speed,
+                     scale_factor, error : integer;
+
+  begin
+
+    current_temperature := 75;
+    increment := 10;
+
+    -- code from book (in text)
+
+    new_temperature := limit ( current_temperature + increment, 10, 100 );
+
+    -- end code from book
+
+    increment := 60;
+    new_temperature := limit ( current_temperature + increment, 10, 100 );
+    increment := -100;
+    new_temperature := limit ( current_temperature + increment, 10, 100 );
+
+    old_motor_speed := 1000;
+    scale_factor := 5;
+    error := 5;
+
+    -- code from book (in text)
+
+    new_motor_speed := old_motor_speed
+                       + scale_factor * limit ( error, -10, +10 );
+
+    -- end code from book
+
+    error := 15;
+    new_motor_speed := old_motor_speed
+                       + scale_factor * limit ( error, -10, +10 );
+
+    error := -20;
+    new_motor_speed := old_motor_speed
+                       + scale_factor * limit ( error, -10, +10 );
+
+    wait;
+  end process tester;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_17.vhd
new file mode 100644
index 0000000..ec60445
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_17.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_17.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_17 is
+end entity fg_07_17;
+
+
+
+architecture test of fg_07_17 is
+
+  -- code from book
+
+  function bv_to_natural ( bv : in bit_vector ) return natural is
+    variable result : natural := 0;
+  begin
+    for index in bv'range loop
+      result := result * 2 + bit'pos(bv(index));
+    end loop;
+    return result;
+  end function bv_to_natural;
+
+  -- end code from book
+
+  signal data : bit_vector(0 to 7);
+  constant address : bit_vector(0 to 3) := "0101";
+  constant Taccess : delay_length := 80 ns;
+
+begin
+
+  tester : process is
+
+                     constant rom_size : natural := 8;
+                   constant word_size : natural := 8;
+
+                   -- code from book (in text)
+
+                   type rom_array is array (natural range 0 to rom_size-1)
+                     of bit_vector(0 to word_size-1);
+                   variable rom_data : rom_array;
+
+                   -- end code from book
+
+  begin
+
+    rom_data := (X"00", X"01", X"02", X"03", X"04", X"05", X"06", X"07");
+
+    -- code from book (in text)
+
+    data <= rom_data ( bv_to_natural(address) ) after Taccess;
+
+    -- end code from book
+
+    wait;
+  end process tester;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_18.vhd
new file mode 100644
index 0000000..13a03b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_18.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_18 is
+end entity fg_07_18;
+
+
+architecture test of fg_07_18 is
+
+  constant target_host_id : natural := 10;
+  constant my_host_id : natural := 5;
+  type pkt_types is (control_pkt, other_pkt);
+  type pkt_header is record
+                       dest, src : natural;
+                       pkt_type : pkt_types;
+                       seq : natural;
+                     end record;
+
+begin
+
+  -- code from book
+
+  network_driver : process is
+
+                             constant seq_modulo : natural := 2**5;
+                           subtype seq_number is natural range 0 to seq_modulo-1;
+                           variable next_seq_number : seq_number := 0;
+                           -- . . .
+                           -- not in book
+                           variable new_header : pkt_header;
+                           -- end not in book
+
+                           impure function generate_seq_number return seq_number is
+                             variable number : seq_number;
+                           begin
+                             number := next_seq_number;
+                             next_seq_number := (next_seq_number + 1) mod seq_modulo;
+                             return number;
+                           end function generate_seq_number;
+
+  begin  -- network_driver
+    -- not in book
+    wait for 10 ns;
+    -- end not in book
+    -- . . .
+    new_header := pkt_header'( dest => target_host_id,
+                               src => my_host_id,
+                               pkt_type => control_pkt,
+                               seq => generate_seq_number );
+    -- . . .
+  end process network_driver;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_19.vhd
new file mode 100644
index 0000000..2201bfd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_19.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_07_19 is
+end entity fg_07_19;
+
+
+
+architecture test of fg_07_19 is
+
+  constant Thold_d_clk : delay_length := 3 ns;
+
+  signal clk, d : bit := '0';
+
+begin
+
+  -- code from book
+
+  hold_time_checker : process ( clk, d ) is
+                                           variable last_clk_edge_time : time := 0 fs;
+  begin
+    if clk'event and clk = '1' then
+      last_clk_edge_time := now;
+    end if;
+    if d'event then
+      assert now - last_clk_edge_time >= Thold_d_clk
+        report "hold time violation";
+    end if;
+  end process hold_time_checker;
+
+  -- end code from book
+
+  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+
+  stimulus : d <= '1' after 15 ns,
+                  '0' after 53 ns,
+                  '1' after 72 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_20.vhd
new file mode 100644
index 0000000..793570c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_20.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_20.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+library ieee;  
+use ieee.std_logic_1164.all;
+
+entity reg_ctrl is
+  port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
+         reg_rd, reg_wr : out std_ulogic );
+end entity reg_ctrl;
+
+architecture bool_eqn of reg_ctrl is
+begin
+
+  rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
+
+  rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
+                      and not cpu_clk;
+
+end architecture bool_eqn;
+
+-- end code from book
+
+entity fg_07_20 is
+
+end entity fg_07_20;
+
+library ieee;  
+use ieee.std_logic_1164.all;
+library stimulus;
+
+architecture test of fg_07_20 is
+
+  signal reg_addr_decoded, rd, wr, io_en,
+    cpu_clk, reg_rd, reg_wr : std_ulogic := '0';
+  signal test_vector : std_ulogic_vector(1 to 5);
+
+  use stimulus.stimulus_generators.all;
+
+begin
+
+  dut : entity work.reg_ctrl
+    port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr );
+
+  stimulus : process is
+  begin
+    all_possible_values( bv => test_vector,
+                         delay_between_values => 10 ns );
+    wait;
+  end process stimulus;
+
+  (reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_22.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_22.vhd
new file mode 100644
index 0000000..e74497f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_07_fg_07_22.vhd
@@ -0,0 +1,118 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_07_fg_07_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity cache is
+end entity cache;
+
+-- end not in book
+
+
+
+architecture behavioral of cache is
+  -- not in book
+  subtype word is bit_vector(0 to 31);
+  signal mem_addr : natural;
+  signal mem_data_in : word;
+  signal mem_read, mem_ack : bit := '0';
+  -- end not in book
+begin
+
+  behavior : process is
+
+                       -- not in book
+                       constant block_size : positive := 4;
+                     type cache_block is array (0 to block_size - 1) of word;
+                     type store_array is array (0 to 15) of cache_block;
+                     variable data_store : store_array;
+                     variable entry_index : natural := 1;
+                     variable miss_base_address : natural := 16;
+                     -- end not in book
+
+                     -- . . .
+
+                     procedure read_block( start_address : natural;
+                                           entry : out cache_block ) is
+
+                       variable memory_address_reg : natural;
+                       variable memory_data_reg : word;
+
+                       procedure read_memory_word is
+                       begin
+                         mem_addr <= memory_address_reg;
+                         mem_read <= '1';
+                         wait until mem_ack = '1';
+                         memory_data_reg := mem_data_in;
+                         mem_read <= '0';
+                         wait until mem_ack = '0';
+                       end procedure read_memory_word;
+
+                     begin  -- read_block
+                       for offset in 0 to block_size - 1 loop
+                         memory_address_reg := start_address + offset;
+                         read_memory_word;
+                         entry(offset) := memory_data_reg;
+                       end loop;
+                     end procedure read_block;
+
+  begin  -- behavior
+    -- . . .
+    read_block( miss_base_address, data_store(entry_index) );
+    -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process behavior;
+
+
+  -- not in book
+
+  memory : process is
+
+                     type store_array is array (0 to 31) of word;
+                   constant store : store_array :=
+                     ( X"00000000", X"00000001", X"00000002", X"00000003",
+                       X"00000004", X"00000005", X"00000006", X"00000007",
+                       X"00000008", X"00000009", X"0000000a", X"0000000b",
+                       X"0000000c", X"0000000d", X"0000000e", X"0000000f",
+                       X"00000010", X"00000011", X"00000012", X"00000013",
+                       X"00000014", X"00000015", X"00000016", X"00000017",
+                       X"00000018", X"00000019", X"0000001a", X"0000001b",
+                       X"0000001c", X"0000001d", X"0000001e", X"0000001f" );
+
+  begin
+    wait until mem_read = '1';
+    mem_data_in <= store(mem_addr);
+    mem_ack <= '1';
+    wait until mem_read = '0';
+    mem_ack <= '0';
+  end process memory;
+
+  -- end not in book
+
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_01.vhd
new file mode 100644
index 0000000..0ceb91b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_01.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_ch_08_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_08_01 is
+
+end entity ch_08_01;
+
+
+----------------------------------------------------------------
+
+
+library ieee;
+
+architecture test of ch_08_01 is
+begin
+
+
+  process_08_1_a : process is
+
+                             -- code from book:
+
+                             variable stored_state : ieee.std_logic_1164.std_ulogic;
+
+                           -- end of code from book
+
+  begin
+
+    wait;
+  end process process_08_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_02.vhd
new file mode 100644
index 0000000..1dc7826
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_02.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_ch_08_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_08_02 is
+
+  -- code from book
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  procedure add ( a, b : in word32;
+                  result : out word32;  overflow : out boolean );
+
+  function "<" ( a, b : in word32 ) return boolean;
+
+  constant max_buffer_size : positive;
+
+  -- end code from book
+
+end package ch_08_02;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_03.vhd
new file mode 100644
index 0000000..0ab34d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_03.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_ch_08_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_08_03 is
+
+end entity ch_08_03;
+
+
+----------------------------------------------------------------
+
+
+library ieee;
+
+architecture test of ch_08_03 is
+begin
+
+
+  process_08_3_a : process is
+
+                             -- code from book:
+
+                             use work.cpu_types;
+
+                           variable data_word : cpu_types.word;
+                           variable next_address : cpu_types.address;
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_08_3_a;
+
+
+  ----------------
+
+
+  process_08_3_b : process is
+
+                             -- code from book:
+
+                             use work.cpu_types.word, work.cpu_types.address;
+
+                           variable data_word : word;
+                           variable next_address : address;
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_08_3_b;
+
+
+  ----------------
+
+
+  block_08_3_c : block is
+
+                         -- code from book:
+
+                         use ieee.std_logic_1164.all;
+
+                       -- end of code from book
+
+  begin
+  end block block_08_3_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_04.vhd
new file mode 100644
index 0000000..8128cc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_04.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_ch_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+--library ieee;  use ieee.std_logic_1164.std_ulogic;
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity logic_block is
+                 port ( a, b : in std_ulogic;
+                        y, z : out std_ulogic );
+               end entity logic_block;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_05.vhd
new file mode 100644
index 0000000..d349359
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_05.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_ch_08_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book:
+
+library std, work;  use std.standard.all;
+
+-- end of code from book
+
+
+                    entity ch_08_05 is
+
+                    end entity ch_08_05;
+
+
+----------------------------------------------------------------
+
+
+                    architecture test of ch_08_05 is
+                    begin
+
+
+                      process_08_4_a : process is
+
+                                                 constant a : integer := 10;
+                                               constant b : integer := 20;
+                                               variable result : boolean;
+
+                      begin
+
+                        -- code from book:
+
+                        result := std.standard."<" ( a, b );
+
+                        -- end of code from book
+
+                        wait;
+                      end process process_08_4_a;
+
+
+                    end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_01.vhd
new file mode 100644
index 0000000..ec531cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_01.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+package cpu_types is
+
+  constant word_size : positive := 16;
+  constant address_size : positive := 24;
+
+  subtype word is bit_vector(word_size - 1 downto 0);
+  subtype address is bit_vector(address_size - 1 downto 0);
+
+  type status_value is ( halted, idle, fetch, mem_read, mem_write,
+                         io_read, io_write, int_ack );
+
+end package cpu_types;
+
+-- end code from book
+
+
+
+package fg_08_01 is
+
+  constant status :
+    -- code from book
+    work.cpu_types.status_value
+    -- end code from book
+    :=
+    -- code from book
+    work.cpu_types.status_value'(work.cpu_types.fetch)
+    -- end code from book
+    ;
+
+end package fg_08_01;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_02.vhd
new file mode 100644
index 0000000..b81d636
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_02.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity address_decoder is
+  port ( addr : in work.cpu_types.address;
+         status : in work.cpu_types.status_value;
+         mem_sel, int_sel, io_sel : out bit );
+end entity address_decoder;
+
+--------------------------------------------------
+
+architecture functional of address_decoder is
+
+  constant mem_low : work.cpu_types.address := X"000000";
+  constant mem_high : work.cpu_types.address := X"EFFFFF";
+  constant io_low : work.cpu_types.address := X"F00000";
+  constant io_high : work.cpu_types.address := X"FFFFFF";
+
+begin
+
+  mem_decoder :
+    mem_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.fetch)
+                          or work.cpu_types."="(status, work.cpu_types.mem_read)
+                          or work.cpu_types."="(status, work.cpu_types.mem_write) )
+               and addr >= mem_low
+   and addr <= mem_high else
+               '0';
+
+  int_decoder :
+    int_sel <= '1' when work.cpu_types."="(status, work.cpu_types.int_ack) else
+               '0';
+
+  io_decoder :
+    io_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.io_read)
+                         or work.cpu_types."="(status, work.cpu_types.io_write) )
+              and addr >= io_low
+  and addr <= io_high else
+              '0';
+
+end architecture functional;
+
+
+-- not in book
+
+entity fg_08_02 is
+end entity fg_08_02;
+
+
+architecture test of fg_08_02 is
+
+  use work.cpu_types.all;
+
+  signal addr : address := X"000000";
+  signal status : status_value := idle;
+  signal mem_sel, int_sel, io_sel : bit;
+
+begin
+
+  dut : entity work.address_decoder
+    port map ( addr => addr, status => status,
+               mem_sel => mem_sel, int_sel => int_sel, io_sel => io_sel );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    addr <= X"EFFFFF";    wait for 10 ns;
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    addr <= X"F00000";    wait for 10 ns;
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    addr <= X"FFFFFF";    wait for 10 ns;
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_03.vhd
new file mode 100644
index 0000000..3847664
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_03.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package clock_pkg is
+
+                 constant Tpw : delay_length := 4 ns;
+
+                 signal clock_phase1, clock_phase2 : std_ulogic;
+
+               end package clock_pkg;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_04.vhd
new file mode 100644
index 0000000..cf53a42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_04.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity phase_locked_clock_gen is
+                 port ( reference : in std_ulogic;
+                        phi1, phi2 : out std_ulogic );
+               end entity phase_locked_clock_gen;
+
+
+               architecture std_cell of phase_locked_clock_gen is
+
+                 --use work.clock_pkg.Tpw;
+                 use work.clock_pkg.all;
+
+               begin
+
+                 phi1_gen : phi1 <= '1', '0' after Tpw when rising_edge(reference);
+
+                 phi2_gen : phi2 <= '1', '0' after Tpw when falling_edge(reference);
+
+               end architecture std_cell;
+
+-- end not in book
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity io_controller is
+                 port ( ref_clock : in std_ulogic;  -- . . . );
+                        -- not in book
+                        other_port : in std_ulogic );
+                 -- end not in book
+               end entity io_controller;
+
+--------------------------------------------------
+
+               architecture top_level of io_controller is
+
+                 -- . . .
+
+                 -- not in book
+                 signal rd, wr, sel, width, burst : std_ulogic;
+                 signal addr : std_ulogic_vector(1 downto 0);
+                 signal ready : std_ulogic;
+                 signal control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+                   other_signal : std_ulogic;
+                 -- end not in book
+
+               begin
+
+                 internal_clock_gen : entity work.phase_locked_clock_gen(std_cell)
+                   port map ( reference => ref_clock,
+                              phi1 => work.clock_pkg.clock_phase1,
+                              phi2 => work.clock_pkg.clock_phase2 );
+
+                 the_bus_sequencer : entity work.bus_sequencer(fsm)
+                   port map ( rd, wr, sel, width, burst, addr(1 downto 0), ready,
+                              control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+                              -- . . . );
+                              other_signal );
+                 -- not in book
+
+                 -- . . .
+
+               end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_05.vhd
new file mode 100644
index 0000000..e23e66c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_05.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity bus_sequencer is
+                 port ( rd, wr, sel, width, burst : out std_ulogic;
+                        addr_low_2 : out std_ulogic_vector(1 downto 0);
+                        ready : out std_ulogic;
+                        control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+                        other_signal : out std_ulogic );
+               end entity bus_sequencer;
+
+----------------
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity state_register is
+                 port ( phi1, phi2 : in std_ulogic;
+                        next_state : in std_ulogic_vector(3 downto 0);
+                        current_state : out std_ulogic_vector(3 downto 0) );
+               end entity state_register;
+
+
+               architecture std_cell of state_register is
+
+               begin
+
+               end architecture std_cell;
+
+-- end not in book
+
+
+
+
+               architecture fsm of bus_sequencer is
+
+                 -- This architecture implements the sequencer as a finite state machine.
+                 -- NOTE: it uses the clock signals from clock_pkg to synchronize the fsm.
+
+                 signal next_state_vector : -- . . .;
+                   -- not in book
+                   std_ulogic_vector(3 downto 0);
+                 signal current_state_vector : std_ulogic_vector(3 downto 0);
+                 -- end not in book
+
+               begin
+
+                 bus_sequencer_state_register : entity work.state_register(std_cell)
+                   port map ( phi1 => work.clock_pkg.clock_phase1,
+                              phi2 => work.clock_pkg.clock_phase2,
+                              next_state => next_state_vector,
+                              -- . . . );
+                              -- not in book
+                              current_state => current_state_vector );
+                 -- end not in book
+
+                 -- . . .
+
+               end architecture fsm;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_06.vhd
new file mode 100644
index 0000000..a8070f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_06.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package cpu_types is
+
+  constant word_size : positive := 16;
+  constant address_size : positive := 24;
+
+  subtype word is bit_vector(word_size - 1 downto 0);
+  subtype address is bit_vector(address_size - 1 downto 0);
+
+  type status_value is ( halted, idle, fetch, mem_read, mem_write,
+                         io_read, io_write, int_ack );
+
+  subtype opcode is bit_vector(5 downto 0);
+
+  function extract_opcode ( instr_word : word ) return opcode;
+
+  constant op_nop : opcode := "000000";
+  constant op_breq : opcode := "000001";
+  constant op_brne : opcode := "000010";
+  constant op_add : opcode := "000011";
+  -- . . .
+
+end package cpu_types;
+
+
+
+-- not in book
+
+package body cpu_types is
+
+  function extract_opcode ( instr_word : word ) return opcode is
+  begin
+    return work.cpu_types.op_nop;
+  end function extract_opcode;
+
+end package body cpu_types;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_07.vhd
new file mode 100644
index 0000000..089cc34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_07.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_07.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity cpu is
+end entity cpu;
+
+-- end not in book
+
+
+
+
+architecture behavioral of cpu is
+begin
+
+  interpreter : process is
+
+                          variable instr_reg : work.cpu_types.word;
+                        variable instr_opcode : work.cpu_types.opcode;
+
+  begin
+    -- . . .    -- initialize
+    loop
+      -- . . .    -- fetch instruction
+      instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
+      case instr_opcode is
+        when work.cpu_types.op_nop => null;
+        when work.cpu_types.op_breq => -- . . .
+          -- . . .
+          -- not in book
+        when others => null;
+                       -- end not in book
+      end case;
+    end loop;
+  end process interpreter;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_08.vhd
new file mode 100644
index 0000000..a272ed2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_08.vhd
@@ -0,0 +1,120 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_08.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+package bit_vector_signed_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+  function "-" ( bv : bit_vector ) return bit_vector;
+
+  function "*" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+  -- . . .
+
+end package bit_vector_signed_arithmetic;
+
+-- not in book
+library bv_utilities;
+use bv_utilities.bv_arithmetic;
+-- end not in book
+
+package body bit_vector_signed_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
+    -- not in book
+  begin
+    return bv_arithmetic."+"(bv1, bv2);
+  end function "+";
+  -- end not in book
+
+  function "-" ( bv : bit_vector ) return bit_vector is -- . . .
+    -- not in book
+  begin
+    return bv_arithmetic."-"(bv);
+  end function "-";
+  -- end not in book
+
+  function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is
+    -- . . .
+  begin
+    -- not in book
+    -- . . .
+    return bv_arithmetic.bv_multu(bv1, bv2);
+    -- end not in book
+  end function mult_unsigned;
+
+  function "*" ( bv1, bv2 : bit_vector ) return bit_vector is
+  begin
+    if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then
+      return mult_unsigned(bv1, bv2);
+    elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then
+      return -mult_unsigned(bv1, -bv2);
+    elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then
+      return -mult_unsigned(-bv1, bv2);
+    else
+      return mult_unsigned(-bv1, -bv2);
+    end if;
+  end function "*";
+
+  -- . . .
+
+end package body bit_vector_signed_arithmetic;
+
+-- not in book
+
+entity fg_08_08 is
+end entity fg_08_08;
+
+library bv_utilities;
+use bv_utilities.bit_vector_signed_arithmetic.all;
+
+use std.textio.all;
+
+architecture test of fg_08_08 is
+begin
+
+  stimulus : process is
+                       variable L : line;
+  begin
+    write(L, X"0002" + X"0005");
+    writeline(output, L);
+    write(L, X"0002" + X"FFFE");
+    writeline(output, L);
+    write(L, - X"0005");
+    writeline(output, L);
+    write(L, - X"FFFE");
+    writeline(output, L);
+    write(L, X"0002" * X"0005");
+    writeline(output, L);
+    write(L, X"0002" * X"FFFD");
+    writeline(output, L);
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_09.vhd
new file mode 100644
index 0000000..c1f91a6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_09.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_09.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity cpu is
+end entity cpu;
+
+-- end not in book
+
+
+
+
+architecture behavioral of cpu is
+begin
+
+  interpreter : process is
+
+                          use work.cpu_types.all;
+
+                        variable instr_reg : word;
+                        variable instr_opcode : opcode;
+
+  begin
+    -- . . .    -- initialize
+    loop
+      -- . . .    -- fetch instruction
+      instr_opcode := extract_opcode ( instr_reg );
+      case instr_opcode is
+        when op_nop => null;
+        when op_breq => -- . . .
+          -- . . .
+          -- not in book
+        when others => null;
+                       -- end not in book
+      end case;
+    end loop;
+  end process interpreter;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_10.vhd
new file mode 100644
index 0000000..85bca11
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_08_fg_08_10.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_08_fg_08_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_08_10 is
+end entity fg_08_10;
+
+
+
+architecture test of fg_08_10 is
+
+  -- code from book
+
+  function "<" ( a, b : bit_vector ) return boolean is
+    variable tmp1 : bit_vector(a'range) := a;
+    variable tmp2 : bit_vector(b'range) := b;
+  begin
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return std.standard."<" ( tmp1, tmp2 );
+  end function "<";
+
+  -- end code from book
+
+  signal a, b : bit_vector(7 downto 0);
+  signal result : boolean;
+
+begin
+
+  dut : result <= a < b;
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    a <= X"02";  b <= X"04";  wait for 10 ns;
+    a <= X"02";  b <= X"02";  wait for 10 ns;
+    a <= X"02";  b <= X"01";  wait for 10 ns;
+    a <= X"02";  b <= X"FE";  wait for 10 ns;
+    a <= X"FE";  b <= X"02";  wait for 10 ns;
+    a <= X"FE";  b <= X"FE";  wait for 10 ns;
+    a <= X"FE";  b <= X"FC";  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_01.vhd
new file mode 100644
index 0000000..4055f30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_01.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_ch_09_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_09_01 is
+
+end entity ch_09_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_09_01 is
+begin
+
+
+  process_09_1_a : process is
+
+                             -- code from book:
+
+                             type register_array is array (0 to 15) of bit_vector(31 downto 0);
+
+                           type register_set is record
+                                                  general_purpose_registers : register_array;
+                                                  program_counter : bit_vector(31 downto 0);
+                                                  program_status : bit_vector(31 downto 0);
+                                                end record;
+
+                           variable CPU_registers : register_set;
+
+                           -- code revised to work around MTI bugs mt015 and mt016
+                           -- alias PSW is CPU_registers.program_status;
+                           -- alias PC is CPU_registers.program_counter;
+                           -- alias GPR is CPU_registers.general_purpose_registers;
+
+                           alias PSW : bit_vector(31 downto 0) is CPU_registers.program_status;
+                           alias PC : bit_vector(31 downto 0) is CPU_registers.program_counter;
+                           alias GPR : register_array is CPU_registers.general_purpose_registers;
+
+                           -- alias SP is CPU_registers.general_purpose_registers(15);
+
+                           alias SP : bit_vector(31 downto 0) is CPU_registers.general_purpose_registers(15);
+
+                           -- alias interrupt_level is PSW(30 downto 26);
+
+                           alias interrupt_level : bit_vector(30 downto 26) is PSW(30 downto 26);
+
+                           -- end revision
+
+                           -- end of code from book
+
+                           procedure procedure_09_1_b is
+
+                             -- code from book:
+
+                             -- code revised to work around MTI bug mt016
+                             -- alias SP is GPR(15);
+
+                             alias SP : bit_vector(31 downto 0) is GPR(15);
+
+                             -- end revision
+
+                             alias interrupt_level : bit_vector(4 downto 0) is PSW(30 downto 26);
+
+                             -- end of code from book
+
+                           begin
+                           end procedure procedure_09_1_b;
+
+  begin
+    wait;
+  end process process_09_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_02.vhd
new file mode 100644
index 0000000..39124a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_02.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_ch_09_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_09_02 is
+
+end entity ch_09_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_09_02 is
+begin
+
+
+  process_09_2_a : process is
+
+                             -- code from book:
+
+                             alias binary_string is bit_vector;
+
+                           variable s1, s2 : binary_string(0 to 7);
+                           -- . . .
+
+                           -- end of code from book
+
+  begin
+
+    s1 := "10101010";
+    s2 := "11110000";
+
+    -- code from book:
+
+    s1 := s1 and not s2;
+
+    -- end of code from book
+
+    wait;
+  end process process_09_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_03.vhd
new file mode 100644
index 0000000..8b29747
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_03.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_ch_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package system_types is
+
+  -- code from book
+
+  type system_status is (idle, active, overloaded);
+
+  -- end code from book
+
+end package system_types;
+
+
+
+
+entity ch_09_03 is
+
+end entity ch_09_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_09_03 is
+
+  -- code from book
+
+  alias status_type is work.system_types.system_status;
+
+  -- end code from book
+
+begin
+
+
+  process_09_2_b : process is
+
+                             variable status : status_type := idle;
+
+  begin
+    wait for 10 ns;
+    status := active;
+    wait for 10 ns;
+    status := overloaded;
+
+    wait;
+  end process process_09_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_04.vhd
new file mode 100644
index 0000000..d4ef534
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_ch_09_04.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_ch_09_04.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package arithmetic_ops is
+
+  -- code from book
+
+  procedure increment ( bv : inout bit_vector;  by : in integer := 1 );
+
+  procedure increment ( int : inout integer;  by : in integer := 1 );
+
+  -- end code from book
+
+end package arithmetic_ops;
+
+package body arithmetic_ops is
+
+  procedure increment ( bv : inout bit_vector;  by : in integer := 1 ) is
+  begin
+  end procedure increment;
+
+  procedure increment ( int : inout integer;  by : in integer := 1 ) is
+  begin
+  end procedure increment;
+
+end package body arithmetic_ops;
+
+
+entity ch_09_04 is
+
+end entity ch_09_04;
+
+library stimulus;
+use stimulus.stimulus_generators.all;
+
+architecture test of ch_09_04 is
+
+  -- code from book
+
+  -- MTI bug mt017
+  -- alias bv_increment is work.arithmetic_ops.increment [ bit_vector, integer ];
+
+  alias int_increment is work.arithmetic_ops.increment [ integer, integer ];
+
+  -- workaround to avoid MTI bug mt018
+  -- alias "*" is "and" [ bit, bit return bit ];
+
+  alias "*" is std.standard."and" [ bit, bit return bit ];
+
+  -- alias "+" is "or" [ bit, bit return bit ];
+
+  alias "+" is std.standard."or" [ bit, bit return bit ];
+
+  -- alias "-" is "not" [ bit return bit ];
+
+  alias "-" is std.standard."not" [ bit return bit ];
+
+  -- end workaround
+
+  alias high is std.standard.'1' [ return bit ];
+
+  -- end code from book
+
+  signal a, b, c, s : bit := '0';
+  signal test_vector : bit_vector(1 to 3);
+  signal test_high : bit := high;
+
+begin
+
+  -- code from book
+
+  -- workaround to avoid MTI bug mt018
+  -- s <= a * b + (-a) * c;
+
+  s <= (a and b) or ((not a) and c);
+
+  -- end workaround
+
+  -- end code from book
+
+  stimulus : all_possible_values ( bv => test_vector,
+				   delay_between_values => 10 ns );
+
+  (a, b, c) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_01.vhd
new file mode 100644
index 0000000..f87aefa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_01.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_fg_09_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+package alu_types is
+
+  constant data_width : positive := 32;
+
+end package alu_types;
+
+
+package io_types is
+
+  constant data_width : positive := 32;
+
+end package io_types;
+
+
+entity controller_system is
+end entity controller_system;
+
+-- end not in book
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.alu_types.all, work.io_types.all;
+
+architecture structural of controller_system is
+
+  alias alu_data_width is work.alu_types.data_width;
+  alias io_data_width is work.io_types.data_width;
+
+  signal alu_in1, alu_in2,
+    alu_result : std_logic_vector(0 to alu_data_width - 1);
+  signal  io_data : std_logic_vector(0 to io_data_width - 1);
+  -- . . .
+
+  -- not in book
+  -- following should not analyze: data_width not directly visible
+  -- constant test : positive := data_width;
+  -- end not in book
+
+begin
+
+  -- . . .
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_02.vhd
new file mode 100644
index 0000000..1bcc30c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_02.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_fg_09_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package fg_09_02_a is
+
+  -- code from book (in text)
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+  -- end code from book
+
+end package fg_09_02_a;
+
+
+
+package body fg_09_02_a is
+
+  -- code from book
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
+
+    alias norm1 : bit_vector(1 to bv1'length) is bv1;
+    alias norm2 : bit_vector(1 to bv2'length) is bv2;
+
+    variable result : bit_vector(1 to bv1'length);
+    variable carry : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report "arguments of different length" severity failure;
+    else
+      for index in norm1'reverse_range loop
+        result(index) := norm1(index) xor norm2(index) xor carry;
+        carry := ( norm1(index) and norm2(index) )
+                 or ( carry and ( norm1(index) or norm2(index) ) );
+      end loop;
+    end if;
+    return result;
+  end function "+";
+
+  -- end code from book
+
+end package body fg_09_02_a;
+
+
+
+
+entity fg_09_02_b is
+end entity fg_09_02_b;
+
+
+architecture test of fg_09_02_b is
+
+  use work.fg_09_02_a.all;
+
+begin
+
+  stimulus : process is
+                       use std.textio.all;
+                     variable L : line;
+  begin
+    write(L, X"0002" + X"0000");
+    writeline(output, L);
+    write(L, X"0002" + X"0005");
+    writeline(output, L);
+    write(L, X"0002" + X"FFFE");
+    writeline(output, L);
+    
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_03.vhd
new file mode 100644
index 0000000..d2cc16e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_03.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_fg_09_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package cpu_types is
+
+  constant word_size : positive := 16;
+  constant address_size : positive := 32;
+
+  subtype word is bit_vector(word_size - 1 downto 0);
+  subtype address is bit_vector(address_size - 1 downto 0);
+
+  type status_value is ( halted, idle, fetch, mem_read, mem_write,
+                         io_read, io_write, int_ack );
+
+end package cpu_types;
+
+
+
+package bit_vector_unsigned_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+end package bit_vector_unsigned_arithmetic;
+
+
+package body bit_vector_unsigned_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
+
+    alias norm1 : bit_vector(1 to bv1'length) is bv1;
+    alias norm2 : bit_vector(1 to bv2'length) is bv2;
+
+    variable result : bit_vector(1 to bv1'length);
+    variable carry : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report "arguments of different length" severity failure;
+    else
+      for index in norm1'reverse_range loop
+        result(index) := norm1(index) xor norm2(index) xor carry;
+        carry := ( norm1(index) and norm2(index) )
+                 or ( carry and ( norm1(index) or norm2(index) ) );
+      end loop;
+    end if;
+    return result;
+  end function "+";
+
+end package  body bit_vector_unsigned_arithmetic;
+
+
+
+
+-- code from book
+
+package DMA_controller_types_and_utilities is
+
+  alias word is work.cpu_types.word;
+  alias address is work.cpu_types.address;
+  alias status_value is work.cpu_types.status_value;
+
+  alias "+" is work.bit_vector_unsigned_arithmetic."+"
+    [ bit_vector, bit_vector return bit_vector ];
+
+  -- . . .
+
+end package DMA_controller_types_and_utilities;
+
+-- end code from book
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_04.vhd
new file mode 100644
index 0000000..260eaf1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_09_fg_09_04.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_09_fg_09_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity DMA_controller is
+end entity DMA_controller;
+
+-- end not in book
+
+
+
+architecture behavioral of DMA_controller is
+
+  use work.DMA_controller_types_and_utilities.all;
+
+begin
+
+  behavior : process is
+
+                       variable address_reg0, address_reg1 : address;
+                     variable count_reg0, count_reg1 : word;
+                     -- . . .
+
+  begin
+    -- . . .
+    address_reg0 := address_reg0 + X"0000_0004";
+    -- . . .
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu-b.vhd
new file mode 100644
index 0000000..ff9d5c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu-b.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_alu-b.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture behavior of alu is
+begin
+
+  alu_op: process (s1, s2, func) is
+
+                                   constant Tpd : delay_length := 10 ns;
+
+                                 variable bv_s1 : bit_vector(s1'range) := To_bitvector(s1);
+                                 variable bv_s2 : bit_vector(s2'range) := To_bitvector(s2);
+                                 variable temp_result : bit_vector(result'range);
+                                 constant zero_result : bit_vector(result'range) := (others => '0');
+                                 variable temp_overflow : boolean;
+
+                                 type boolean_to_X01_table is array (boolean) of X01;
+                                 constant boolean_to_X01 : boolean_to_X01_table
+                                   := ( false => '0', true => '1' );
+
+  begin
+    case func is
+      when alu_add =>
+        bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_addu =>
+        bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_sub =>
+        bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_subu =>
+        bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
+      when others =>
+        report "alu: illegal function code" severity error;
+        temp_result := X"0000_0000";
+    end case;
+    result <= To_X01(temp_result) after Tpd;
+    zero <= boolean_to_X01(temp_result = zero_result) after Tpd;
+    negative <= To_X01(temp_result(temp_result'left)) after Tpd;
+    overflow <= boolean_to_X01(temp_overflow) after Tpd;
+  end process alu_op;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu.vhd
new file mode 100644
index 0000000..a9fadd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alu.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_alu.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+               use work.alu_types.all;
+
+               entity alu is
+                 port ( s1, s2 : in std_ulogic_vector;
+                        result : out std_ulogic_vector;
+                        func : in alu_func;
+                        zero, negative, overflow : out std_ulogic );
+               end entity alu;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alut.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alut.vhd
new file mode 100644
index 0000000..359cdf5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_alut.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_alut.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package alu_types is
+
+                 subtype alu_func is std_ulogic_vector(3 downto 0);
+
+                 constant alu_add : alu_func := "0000";
+                 constant alu_addu : alu_func := "0001";
+                 constant alu_sub : alu_func := "0010";
+                 constant alu_subu : alu_func := "0011";
+
+               end package alu_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat-b.vhd
new file mode 100644
index 0000000..0e81119
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat-b.vhd
@@ -0,0 +1,1034 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_bvat-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+use std.textio.all, bv_utilities.bv_arithmetic.all;
+
+architecture bench of bv_test is
+  
+begin
+
+  process is
+
+            variable L : line;
+          variable byte : bit_vector(0 to 7);
+          variable word : bit_vector(1 to 32);
+          variable half_byte : bit_vector(1 to 4);
+          variable overflow, div_by_zero, result : boolean;
+
+  begin
+    wait for 1 ns;
+
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+    -- test bit_vector to numeric conversions
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+
+    write(L, string'("Testing bv_to_natural:"));
+    writeline(output, L);
+
+    write(L, string'("  bv_to_natural(X""02"") = "));
+    write(L, bv_to_natural(X"02"));
+    writeline(output, L);
+    assert bv_to_natural(X"02") = 2;
+
+    write(L, string'("  bv_to_natural(X""FE"") = "));
+    write(L, bv_to_natural(X"FE"));
+    writeline(output, L);
+    assert bv_to_natural(X"FE") = 254;
+
+    ----------------------------------------------------------------
+
+    write(L, string'("Testing natural_to_bv:"));
+    writeline(output, L);
+
+    write(L, string'("  natural_to_bv(2) = "));
+    write(L, natural_to_bv(2, 8));
+    writeline(output, L);
+    assert natural_to_bv(2, 8) = X"02";
+
+    write(L, string'("  natural_to_bv(254) = "));
+    write(L, natural_to_bv(254, 8));
+    writeline(output, L);
+    assert natural_to_bv(254, 8) = X"FE";
+
+    ----------------------------------------------------------------
+
+    write(L, string'("Testing bv_to_integer:"));
+    writeline(output, L);
+
+    write(L, string'("  bv_to_integer(X""02"") = "));
+    write(L, bv_to_integer(X"02"));
+    writeline(output, L);
+    assert bv_to_integer(X"02") = 2;
+
+    write(L, string'("  bv_to_integer(X""FE"") = "));
+    write(L, bv_to_integer(X"FE"));
+    writeline(output, L);
+    assert bv_to_integer(X"FE") = -2;
+
+    ----------------------------------------------------------------
+
+    write(L, string'("Testing integer_to_bv:"));
+    writeline(output, L);
+
+    write(L, string'("  integer_to_bv(2) = "));
+    write(L, integer_to_bv(2, 8));
+    writeline(output, L);
+    assert integer_to_bv(2, 8) = X"02";
+
+    write(L, string'("  integer_to_bv(-2) = "));
+    write(L, integer_to_bv(-2, 8));
+    writeline(output, L);
+    assert integer_to_bv(-2, 8) = X"FE";
+
+
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+    --  Arithmetic operations
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+
+    ----------------------------------------------------------------
+    -- bv_add: Signed addition with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_add with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2+2 = "));
+    bv_add(X"02", X"02", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"04" and not overflow;
+
+    write(L, string'("  2+(-3) = "));
+    bv_add(X"02", X"FD", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"FF" and not overflow;
+
+    write(L, string'("  64+64 = "));
+    bv_add(X"40", X"40", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and overflow;
+
+    write(L, string'("  -64+(-64) = "));
+    bv_add(X"C0", X"C0", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not overflow;
+
+    ----------------------------------------------------------------
+    -- "+": Signed addition without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing ""+"" without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2+2 = "));
+    byte := X"02" + X"02";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"04";
+
+    write(L, string'("  2+(-3) = "));
+    byte := X"02" + X"FD";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FF";
+
+    write(L, string'("  64+64 = "));
+    byte := X"40" + X"40";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  -64+(-64) = "));
+    byte := X"C0" + X"C0";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    ----------------------------------------------------------------
+    -- bv_sub: Signed subtraction with overflow detection
+    ----------------------------------------------------------------
+    
+    writeline(output, L);
+    write(L, string'("Testing bv_sub with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2-2 = "));
+    bv_sub(X"02", X"02", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and not overflow;
+
+    write(L, string'("  2-(-3) = "));
+    bv_sub(X"02", X"FD", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"05" and not overflow;
+
+    write(L, string'("  64-(-64) = "));
+    bv_sub(X"40", X"C0", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and overflow;
+
+    write(L, string'("  -64-64 = "));
+    bv_sub(X"C0", X"40", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not overflow;
+
+    ----------------------------------------------------------------
+    -- "-": Signed subtraction without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing ""-"" without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2-2 = "));
+    byte := X"02" - X"02";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    write(L, string'("  2-(-3) = "));
+    byte := X"02" - X"FD";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"05";
+
+    write(L, string'("  64-(-64) = "));
+    byte := X"40" - X"C0";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  -64-64 = "));
+    byte := X"C0" - X"40";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    ----------------------------------------------------------------
+    -- bv_addu:  Unsigned addition with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_addu with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2+2 = "));
+    bv_addu(X"02", X"02", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"04" and not overflow;
+
+    write(L, string'("  64+64 = "));
+    bv_addu(X"40", X"40", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not overflow;
+
+    write(L, string'("  128+128 = "));
+    bv_addu(X"80", X"80", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and overflow;
+
+    ----------------------------------------------------------------
+    -- bv_addu: Unsigned addition without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_addu without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  2+2 = "));
+    byte := bv_addu(X"02", X"02");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"04";
+
+    write(L, string'("  64+64 = "));
+    byte := bv_addu(X"40", X"40");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  128+128 = "));
+    byte := bv_addu(X"80", X"80");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    ----------------------------------------------------------------
+    -- bv_subu: Unsigned subtraction with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_subu with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  3-2 = "));
+    bv_subu(X"03", X"02", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"01" and not overflow;
+
+    write(L, string'("  64-64 = "));
+    bv_subu(X"40", X"40", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and not overflow;
+
+    write(L, string'("  64-128 = "));
+    bv_subu(X"40", X"80", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"C0" and overflow;
+
+    ----------------------------------------------------------------
+    -- bv_subu: Unsigned subtraction without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_subu without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  3-2 = "));
+    byte := bv_subu(X"03", X"02");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"01";
+
+    write(L, string'("  64-64 = "));
+    byte := bv_subu(X"40", X"40");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    write(L, string'("  64-128 = "));
+    byte := bv_subu(X"40", X"80");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"C0";
+
+    ----------------------------------------------------------------
+    -- bv_neg: Signed negation with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_neg with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  -(3) = "));
+    bv_neg(X"03", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"FD" and not overflow;
+
+    write(L, string'("  -(-3) = "));
+    bv_neg(X"FD", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"03" and not overflow;
+
+    write(L, string'("  -(127) = "));
+    bv_neg(X"7F", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"81" and not overflow;
+
+    write(L, string'("  -(-128) = "));
+    bv_neg(X"80", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and overflow;
+
+    ----------------------------------------------------------------
+    -- "-": Signed negation without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing ""-"" without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  -(3) = "));
+    byte := - X"03";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FD";
+
+    write(L, string'("  -(-3) = "));
+    byte := - X"FD";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"03";
+
+    write(L, string'("  -(127) = "));
+    byte := - X"7F";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"81";
+
+    write(L, string'("  -(-128) = "));
+    byte := - X"80";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    ----------------------------------------------------------------
+    -- bv_mult: Signed multiplication with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_mult with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  5*(-3) = "));
+    bv_mult(X"05", X"FD", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"F1" and not overflow;
+
+    write(L, string'("  (-5)*(-3) = "));
+    bv_mult(X"FB", X"FD", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"0F" and not overflow;
+
+    write(L, string'("  16*8 = "));
+    bv_mult(X"10", X"08", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and overflow;
+
+    write(L, string'("  16*16 = "));
+    bv_mult(X"10", X"10", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and overflow;
+
+    write(L, string'("  16*(-8) = "));
+    bv_mult(X"10", X"F8", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not overflow;
+
+    write(L, string'("  16*(-16) = "));
+    bv_mult(X"10", X"F0", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and overflow;
+
+    ----------------------------------------------------------------
+    -- "*":  Signed multiplication without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing ""*"" without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  5*(-3) = "));
+    byte := X"05" * X"FD";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"F1";
+
+    write(L, string'("  (-5)*(-3) = "));
+    byte := X"FB" * X"FD";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"0F";
+
+    write(L, string'("  16*8 = "));
+    byte := X"10" * X"08";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  16*16 = "));
+    byte := X"10" * X"10";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    write(L, string'("  16*(-8) = "));
+    byte := X"10" * X"F8";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  16*(-16) = "));
+    byte := X"10" * X"F0";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    ----------------------------------------------------------------
+    -- bv_multu:  Unsigned multiplication with overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_multu with overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  5*7 = "));
+    bv_multu(X"05", X"07", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"23" and not overflow;
+
+    write(L, string'("  16*8 = "));
+    bv_multu(X"10", X"08", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not overflow;
+
+    write(L, string'("  16*16 = "));
+    bv_multu(X"10", X"10", byte, overflow);
+    write(L, byte);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and overflow;
+
+    ----------------------------------------------------------------
+    --  bv_multu: Unsigned multiplication without overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_multu without overflow:"));
+    writeline(output, L);
+
+    write(L, string'("  5*7 = "));
+    byte := bv_multu(X"05", X"07");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"23";
+
+    write(L, string'("  16*8 = "));
+    byte := bv_multu(X"10", X"08");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  16*16 = "));
+    byte := bv_multu(X"10", X"10");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    ----------------------------------------------------------------
+    -- bv_div: Signed division with divide by zero and overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_div with flags:"));
+    writeline(output, L);
+
+    write(L, string'("  7/2 = "));
+    bv_div(X"07", X"02", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"03" and not div_by_zero and not overflow;
+
+    write(L, string'("  -7/2 = "));
+    bv_div(X"F9", X"02", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"FD" and not div_by_zero and not overflow;
+
+    write(L, string'("  7/-2 = "));
+    bv_div(X"07", X"FE", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"FD" and not div_by_zero and not overflow;
+
+    write(L, string'("  -7/-2 = "));
+    bv_div(X"F9", X"FE", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"03" and not div_by_zero and not overflow;
+
+    write(L, string'("  -128/1 = "));
+    bv_div(X"80", X"01", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not div_by_zero and not overflow;
+
+    write(L, string'("  -128/-1 = "));
+    bv_div(X"80", X"FF", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"80" and not div_by_zero and overflow;
+
+    write(L, string'("  -16/0 = "));
+    bv_div(X"F0", X"00", byte, div_by_zero, overflow);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    write(L, string'(", overflow = "));  write(L, overflow);
+    writeline(output, L);
+    assert byte = X"00" and div_by_zero and not overflow;
+
+    ----------------------------------------------------------------
+    -- "/": Signed division without divide by zero and overflow detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing ""/"" without flags:"));
+    writeline(output, L);
+
+    write(L, string'("  7/2 = "));
+    byte := X"07" / X"02";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"03";
+
+    write(L, string'("  -7/2 = "));
+    byte := X"F9" / X"02";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FD";
+
+    write(L, string'("  7/-2 = "));
+    byte := X"07" / X"FE";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FD";
+
+    write(L, string'("  -7/-2 = "));
+    byte := X"F9" / X"FE";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"03";
+
+    write(L, string'("  -128/1 = "));
+    byte := X"80" / X"01";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  -128/-1 = "));
+    byte := X"80" / X"FF";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"80";
+
+    write(L, string'("  -16/0 = "));
+    byte := X"F0" / X"00";
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    ----------------------------------------------------------------
+    -- bv_divu: Unsigned division with divide by zero detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_divu with flag:"));
+    writeline(output, L);
+
+    write(L, string'("  7/2 = "));
+    bv_divu(X"07", X"02", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"03" and not div_by_zero;
+
+    write(L, string'("  14/7 = "));
+    bv_divu(X"0E", X"07", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"02" and not div_by_zero;
+
+    write(L, string'("  16/1 = "));
+    bv_divu(X"10", X"01", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"10" and not div_by_zero;
+
+    write(L, string'("  16/0 = "));
+    bv_divu(X"10", X"00", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"10" and div_by_zero;
+
+    write(L, string'("  16/16 = "));
+    bv_divu(X"10", X"10", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"01" and not div_by_zero;
+
+    write(L, string'("  1/16 = "));
+    bv_divu(X"01", X"10", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"00" and not div_by_zero;
+
+    write(L, string'("  255/1 = "));
+    bv_divu(X"FF", X"01", byte, div_by_zero);
+    write(L, byte);
+    write(L, string'(", div_by_zero = "));  write(L, div_by_zero);
+    writeline(output, L);
+    assert byte = X"FF" and not div_by_zero;
+
+    ----------------------------------------------------------------
+    -- bv_divu: Unsigned division without divide by zero detection
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_divu without flag:"));
+    writeline(output, L);
+
+    write(L, string'("  7/2 = "));
+    byte := bv_divu(X"07", X"02");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"03";
+
+    write(L, string'("  14/7 = "));
+    byte := bv_divu(X"0E", X"07");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"02";
+
+    write(L, string'("  16/1 = "));
+    byte := bv_divu(X"10", X"01");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"10";
+
+    write(L, string'("  16/0 = "));
+    byte := bv_divu(X"10", X"00");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    write(L, string'("  16/16 = "));
+    byte := bv_divu(X"10", X"10");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"01";
+
+    write(L, string'("  1/16 = "));
+    byte := bv_divu(X"01", X"10");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"00";
+
+    write(L, string'("  255/1 = "));
+    byte := bv_divu(X"FF", X"01");
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FF";
+
+
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+    --  Arithmetic comparison operators.
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+
+    ----------------------------------------------------------------
+    -- bv_lt: Signed less than comparison
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_lt:"));
+    writeline(output, L);
+
+    write(L, string'("  2 < 2 = "));
+    result := bv_lt(X"02", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    write(L, string'("  2 < 3 = "));
+    result := bv_lt(X"02", X"03");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  -2 < 2 = "));
+    result := bv_lt(X"FE", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  2 < -3 = "));
+    result := bv_lt(X"02", X"FD");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    ----------------------------------------------------------------
+    -- bv_le: Signed less than or equal comparison
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_le:"));
+    writeline(output, L);
+
+    write(L, string'("  2 <= 2 = "));
+    result := bv_le(X"02", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  2 <= 3 = "));
+    result := bv_le(X"02", X"03");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  -2 <= 2 = "));
+    result := bv_le(X"FE", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  2 <= -3 = "));
+    result := bv_le(X"02", X"FD");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    ----------------------------------------------------------------
+    -- bv_gt: Signed greater than comparison
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_gt:"));
+    writeline(output, L);
+
+    write(L, string'("  2 > 2 = "));
+    result := bv_gt(X"02", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    write(L, string'("  3 > 2 = "));
+    result := bv_gt(X"03", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  2 > -2 = "));
+    result := bv_gt(X"02", X"FE");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  -3 > 2 = "));
+    result := bv_gt(X"FD", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    ----------------------------------------------------------------
+    -- bv_ge: Signed greater than or equal comparison
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_ge:"));
+    writeline(output, L);
+
+    write(L, string'("  2 >= 2 = "));
+    result := bv_ge(X"02", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  3 >= 2 = "));
+    result := bv_ge(X"03", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  2 >= -2 = "));
+    result := bv_ge(X"02", X"FE");
+    write(L, result);
+    writeline(output, L);
+    assert result;
+
+    write(L, string'("  -3 >= 2 = "));
+    result := bv_ge(X"FD", X"02");
+    write(L, result);
+    writeline(output, L);
+    assert NOT result;
+
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+    --  Extension operators - convert a bit vector to a longer one
+    ----------------------------------------------------------------
+    ----------------------------------------------------------------
+
+    ----------------------------------------------------------------
+    -- bv_sext: Sign extension
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_sext:"));
+    writeline(output, L);
+
+    write(L, string'("  sext(X""02"", 32) = "));
+    word := bv_sext(X"02", 32);
+    write(L, word);
+    writeline(output, L);
+    assert word = X"00000002";
+
+    write(L, string'("  sext(X""FE"", 32) = "));
+    word := bv_sext(X"FE", 32);
+    write(L, word);
+    writeline(output, L);
+    assert word = X"FFFFFFFE";
+
+    write(L, string'("  sext(X""02"", 8) = "));
+    byte := bv_sext(X"02", 8);
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"02";
+
+    write(L, string'("  sext(X""FE"", 8) = "));
+    byte := bv_sext(X"FE", 8);
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FE";
+
+    write(L, string'("  sext(X""02"", 4) = "));
+    half_byte := bv_sext(X"02", 4);
+    write(L, half_byte);
+    writeline(output, L);
+    assert half_byte = X"2";
+
+    write(L, string'("  sext(X""FE"", 4) = "));
+    half_byte := bv_sext(X"FE", 4);
+    write(L, half_byte);
+    writeline(output, L);
+    assert half_byte = X"E";
+
+    ----------------------------------------------------------------
+    -- bv_zext" Zero extension
+    ----------------------------------------------------------------
+
+    writeline(output, L);
+    write(L, string'("Testing bv_zext:"));
+    writeline(output, L);
+
+    write(L, string'("  zext(X""02"", 32) = "));
+    word := bv_zext(X"02", 32);
+    write(L, word);
+    writeline(output, L);
+    assert word = X"00000002";
+
+    write(L, string'("  zext(X""FE"", 32) = "));
+    word := bv_zext(X"FE", 32);
+    write(L, word);
+    writeline(output, L);
+    assert word = X"000000FE";
+
+    write(L, string'("  zext(X""02"", 8) = "));
+    byte := bv_zext(X"02", 8);
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"02";
+
+    write(L, string'("  zext(X""FE"", 8) = "));
+    byte := bv_zext(X"FE", 8);
+    write(L, byte);
+    writeline(output, L);
+    assert byte = X"FE";
+
+    write(L, string'("  zext(X""02"", 4) = "));
+    half_byte := bv_zext(X"02", 4);
+    write(L, half_byte);
+    writeline(output, L);
+    assert half_byte = X"2";
+
+    write(L, string'("  zext(X""FE"", 4) = "));
+    half_byte := bv_zext(X"FE", 4);
+    write(L, half_byte);
+    writeline(output, L);
+    assert half_byte = X"E";
+
+
+    wait;
+  end process;
+
+end architecture bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat.vhd
new file mode 100644
index 0000000..14e2590
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_bvat.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_bvat.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity bv_test is
+  
+end entity bv_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkdiv.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkdiv.vhd
new file mode 100644
index 0000000..f0cc387
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkdiv.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_chkdiv.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity check_div is
+end entity check_div;
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture behav of check_div is
+
+begin
+
+  checker : process is
+
+                      variable bv_a, bv_b, bv_quotient, bv_remainder : bit_vector(3 downto 0);
+                    variable div_by_zero : boolean;
+
+  begin
+    for a in 0 to 15 loop
+      for b in 0 to 15 loop
+	bv_a := natural_to_bv(a, bv_a'length);
+        bv_b := natural_to_bv(b, bv_b'length);
+        bv_divu(bv_a, bv_b, bv_quotient, bv_remainder, div_by_zero);
+	if b = 0 then
+	  assert div_by_zero
+	    report integer'image(a) & '/' & integer'image(b)
+            & ": div_by_zero not true";
+	else
+	  assert not div_by_zero
+	    report integer'image(a) & '/' & integer'image(b)
+            & ": div_by_zero not false";
+	  assert bv_to_natural(bv_quotient) = a / b
+	    report integer'image(a) & '/' & integer'image(b)
+            & ": quotient = " & integer'image(bv_to_natural(bv_quotient));
+	  assert bv_to_natural(bv_remainder) = a rem b
+	    report integer'image(a) & '/' & integer'image(b)
+            & ": remainder = " & integer'image(bv_to_natural(bv_remainder));
+	end if;
+      end loop;
+    end loop;
+    wait;
+  end process checker;
+
+end architecture behav;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkmult.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkmult.vhd
new file mode 100644
index 0000000..588a0fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_10_chkmult.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_10_chkmult.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity check_mult is
+end entity check_mult;
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture behav of check_mult is
+
+begin
+
+  checker : process is
+
+                      variable bv_a, bv_b, bv_product : bit_vector(3 downto 0);
+                    variable overflow : boolean;
+
+  begin
+    for a in 0 to 15 loop
+      for b in 0 to 15 loop
+	bv_a := natural_to_bv(a, bv_a'length);
+        bv_b := natural_to_bv(b, bv_b'length);
+        bv_multu(bv_a, bv_b, bv_product, overflow);
+	if a * b > 15 then
+	  assert overflow
+	    report integer'image(a) & '*' & integer'image(b)
+            & ": overflow not true";
+	else
+	  assert not overflow
+	    report integer'image(a) & '*' & integer'image(b)
+            & ": overflow not false";
+	  assert bv_to_natural(bv_product) = a * b
+	    report integer'image(a) & '*' & integer'image(b)
+            & ": product = " & integer'image(bv_to_natural(bv_product));
+	end if;
+      end loop;
+    end loop;
+    wait;
+  end process checker;
+
+end architecture behav;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_01.vhd
new file mode 100644
index 0000000..cfa42c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_01.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_ch_11_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_11_01 is
+
+end entity ch_11_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_11_01 is
+
+  type MVL4_ulogic is ('X', '0', '1', 'Z');  -- unresolved logic type
+
+  -- code from book:
+
+  type small_int is range 1 to 4;
+  type small_array is array (small_int range <>) of -- . . . ;
+    -- not in book
+    MVL4_ulogic;
+  -- end not in book
+
+  -- end of code from book
+
+  type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
+  constant resolution_table : table :=
+    --  'X'  '0'  '1'  'Z'
+    --  ------------------
+    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
+      ( 'X', '0', 'X', '0' ),    -- '0'
+      ( 'X', 'X', '1', '1' ),    -- '1'
+      ( 'X', '0', '1', 'Z' ) );  -- 'Z'
+
+  function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is
+    variable result : MVL4_ulogic := 'Z';
+  begin
+    for index in contribution'range loop
+      result := resolution_table(result, contribution(index));
+    end loop;
+    return result;
+  end function resolve_MVL4;
+
+  subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
+
+  signal s : MVL4_logic;
+
+begin
+
+  driver_1 : s <= 'Z';
+
+  driver_2 : s <= 'Z';
+
+  driver_3 : s <= 'Z';
+
+  driver_4 : s <= 'Z';
+
+  driver_5 : s <= 'Z';
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_02.vhd
new file mode 100644
index 0000000..9f4b2e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_02.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_ch_11_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_11_02 is
+
+  -- code from book
+
+  type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
+
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+
+  function resolved ( s : std_ulogic_vector ) return std_ulogic;
+
+  subtype std_logic is resolved std_ulogic;
+
+  type std_logic_vector is array ( natural range <>) of std_logic;
+
+  subtype X01 is resolved std_ulogic range 'X' to '1'; -- ('X','0','1')
+  subtype X01Z is resolved std_ulogic range 'X' to 'Z'; -- ('X','0','1','Z')
+  subtype UX01 is resolved std_ulogic range 'U' to '1'; -- ('U','X','0','1')
+  subtype UX01Z is resolved std_ulogic range 'U' to 'Z'; -- ('U','X','0','1','Z')
+
+  -- end code from book
+
+end package ch_11_02;
+
+
+
+package body ch_11_02 is
+
+  function resolved ( s : std_ulogic_vector ) return std_ulogic is
+  begin
+  end function resolved;
+
+end package body ch_11_02;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_03.vhd
new file mode 100644
index 0000000..db6fda4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_ch_11_03.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_ch_11_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity IO_section is
+                 port ( data_ack : inout std_logic;  -- . . . );
+                        -- not in book
+                        other_port : in std_ulogic := 'U' );
+                 -- end not in book
+               end entity IO_section;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_01.vhd
new file mode 100644
index 0000000..f422f83
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_01.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_11_01 is
+end entity fg_11_01;
+
+
+
+architecture test of fg_11_01 is
+
+  -- code from book (in text)
+
+  type tri_state_logic is ('0', '1', 'Z');
+
+  type tri_state_logic_array is array (integer range <>) of tri_state_logic;
+
+  -- end code from book
+
+
+  -- code from book
+
+  function resolve_tri_state_logic ( values : in tri_state_logic_array )
+    return tri_state_logic is
+    variable result : tri_state_logic := 'Z';
+  begin
+    for index in values'range loop
+      if values(index) /= 'Z' then
+        result := values(index);
+      end if;
+    end loop;
+    return result;
+  end function resolve_tri_state_logic;
+
+  -- end code from book
+
+
+  -- code from book (in text)
+
+  signal s1 : resolve_tri_state_logic tri_state_logic;
+
+  subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
+
+  signal s2, s3 : resolved_logic;
+
+  -- end code from book
+
+begin
+
+  source_1 : s1 <= 'Z',
+                   '0' after 10 ns,
+                   'Z' after 20 ns,
+                   '1' after 30 ns,
+                   'Z' after 40 ns,
+	           '1' after 200 ns,
+	           'Z' after 220 ns;
+
+  source_2 : s1 <= 'Z',
+                   '0' after 110 ns,
+                   'Z' after 120 ns,
+                   '1' after 130 ns,
+                   'Z' after 140 ns,
+	           '1' after 200 ns,
+	           '0' after 210 ns,
+	           'Z' after 220 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_02.vhd
new file mode 100644
index 0000000..79d85da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_02.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package MVL4 is
+
+  type MVL4_ulogic is ('X', '0', '1', 'Z');  -- unresolved logic type
+
+  type MVL4_ulogic_vector is array (natural range <>) of MVL4_ulogic;
+
+  function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
+    return MVL4_ulogic;
+
+  subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
+
+  -- code from book (in text)
+
+  type MVL4_logic_vector is array (natural range <>) of MVL4_logic;
+
+  -- end code from book
+
+end package MVL4;
+
+--------------------------------------------------
+
+package body MVL4 is
+
+  type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
+
+  constant resolution_table : table :=
+    --  'X'  '0'  '1'  'Z'
+    --  ------------------
+    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
+      ( 'X', '0', 'X', '0' ),    -- '0'
+      ( 'X', 'X', '1', '1' ),    -- '1'
+      ( 'X', '0', '1', 'Z' ) );  -- 'Z'
+
+  function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
+    return MVL4_ulogic is
+    variable result : MVL4_ulogic := 'Z';
+  begin
+    for index in contribution'range loop
+      result := resolution_table(result, contribution(index));
+    end loop;
+    return result;
+  end function resolve_MVL4;
+
+end package body MVL4;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_03.vhd
new file mode 100644
index 0000000..34bd076
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_03.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+use work.MVL4.all;
+
+entity tri_state_buffer is
+  port ( a, enable : in MVL4_ulogic;  y : out MVL4_ulogic );
+end entity tri_state_buffer;
+
+--------------------------------------------------
+
+architecture behavioral of tri_state_buffer is
+begin
+
+  y <= 'Z' when enable = '0' else
+       a   when enable = '1' and (a = '0' or a = '1') else
+       'X';
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_04.vhd
new file mode 100644
index 0000000..c350711
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_04.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_04.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity misc_logic is
+end entity misc_logic;
+
+-- end not in book
+
+
+
+use work.MVL4.all;
+
+architecture gate_level of misc_logic is
+
+  signal src1, src1_enable : MVL4_ulogic;
+  signal src2, src2_enable : MVL4_ulogic;
+  signal selected_val : MVL4_logic;
+  -- . . .
+
+begin
+
+  src1_buffer : entity work.tri_state_buffer(behavioral)
+    port map ( a => src1, enable => src1_enable, y => selected_val );
+
+  src2_buffer : entity work.tri_state_buffer(behavioral)
+    port map ( a => src2, enable => src2_enable, y => selected_val );
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    src1_enable <= '0';  src2_enable <= '0';  wait for 10 ns;
+    src1 <= '0';         src2 <= '1';         wait for 10 ns;
+    src1_enable <= '1';                       wait for 10 ns;
+    src1 <= 'Z';                              wait for 10 ns;
+    src1 <= '1';                              wait for 10 ns;
+    src1_enable <= '0';                       wait for 10 ns;
+    src2_enable <= '1';  wait for 10 ns;
+    src2 <= 'Z';         wait for 10 ns;
+    src2 <= '0';         wait for 10 ns;
+    src2_enable <= '0';  wait for 10 ns;
+    src1_enable <= '1';  src2_enable <= '1';  wait for 10 ns;
+    src1 <= '0';                              wait for 10 ns;
+    src1 <= 'X';                              wait for 10 ns;
+    src1 <= '1';         src2 <= '1';         wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture gate_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_05.vhd
new file mode 100644
index 0000000..91c13bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_05.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package words is
+
+  type X01Z is ('X', '0', '1', 'Z');
+  type uword is array (0 to 31) of X01Z;
+
+  type uword_vector is array (natural range <>) of uword;
+
+  function resolve_word ( contribution : uword_vector ) return uword;
+
+  subtype word is resolve_word uword;
+
+  -- not in book
+  type ubyte is array (0 to 7) of X01Z;
+  -- end not in book
+
+end package words;
+
+--------------------------------------------------
+
+package body words is
+
+  type table is array (X01Z, X01Z) of X01Z;
+
+  constant resolution_table : table :=
+    --  'X'  '0'  '1'  'Z'
+    --  ------------------
+    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
+      ( 'X', '0', 'X', '0' ),    -- '0'
+      ( 'X', 'X', '1', '1' ),    -- '1'
+      ( 'X', '0', '1', 'Z' ) );  -- 'Z'
+
+  function resolve_word ( contribution : uword_vector ) return uword is
+    variable result : uword := (others => 'Z');
+  begin
+    for index in contribution'range loop
+      for element in uword'range loop
+        result(element) :=
+          resolution_table( result(element), contribution(index)(element) );
+      end loop;
+    end loop;
+    return result;
+  end function resolve_word;
+
+end package body words;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_06.vhd
new file mode 100644
index 0000000..ab8b380
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_06.vhd
@@ -0,0 +1,125 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+use work.words.all;
+
+entity cpu is
+  port ( address : out uword;  data : inout uword;  -- . . . );
+  -- not in book
+  other_port : in X01Z := 'Z' );
+  -- end not in book
+end entity cpu;
+
+
+-- not in book
+
+architecture behavioral of cpu is
+begin
+end architecture behavioral;
+
+-- end not in book
+
+
+--------------------------------------------------
+
+use work.words.all;
+
+entity memory is
+  port ( address : in uword;  data : inout uword; -- . . . );
+  -- not in book
+  other_port : in X01Z := 'Z' );
+  -- end not in book
+end entity memory;
+
+
+-- not in book
+
+architecture behavioral of memory is
+begin
+end architecture behavioral;
+
+-- end not in book
+
+
+--------------------------------------------------
+
+
+-- not in book
+
+use work.words.all;
+
+entity ROM is
+  port ( a : in uword;  d : out ubyte;  other_port : in X01Z := 'Z' );
+end entity ROM;
+
+
+architecture behavioral of ROM is
+begin
+end architecture behavioral;
+
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+
+architecture top_level of computer_system is
+
+  use work.words.all;
+
+  signal address : uword;
+  signal data : word;
+  -- . . .
+
+begin
+
+  the_cpu : entity work.cpu(behavioral)
+    port map ( address, data, -- . . . );
+               -- not in book
+               open );
+  -- end not in book
+
+  the_memory : entity work.memory(behavioral)
+    port map ( address, data, -- . . . );
+               -- not in book
+               open );
+  -- end not in book
+
+  -- . . .
+
+  -- code from book (in text)
+
+--   boot_rom : entity work.ROM(behavioral)
+--     port map ( a => address, d => data(24 to 31), -- . . . );  -- illegal
+--     -- not in book
+--                other_port => open );
+--     -- end not in book
+
+  -- end code from book
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_07.vhd
new file mode 100644
index 0000000..6740056
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_07.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_07.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+use work.MVL4.all;
+
+entity ROM is
+  port ( a : in MVL4_ulogic_vector(15 downto 0);
+         d : inout MVL4_logic_vector(7 downto 0);
+         rd : in MVL4_ulogic );
+end entity ROM;
+
+-- not in book
+architecture behavioral of ROM is
+begin
+end architecture behavioral;
+-- end not in book
+
+--------------------------------------------------
+
+use work.MVL4.all;
+
+entity SIMM is
+  port ( a : in MVL4_ulogic_vector(9 downto 0);
+         d : inout MVL4_logic_vector(31 downto 0);
+         ras, cas, we, cs : in MVL4_ulogic );
+end entity SIMM;
+
+-- not in book
+architecture behavioral of SIMM is
+begin
+end architecture behavioral;
+-- end not in book
+
+--------------------------------------------------
+
+-- not in book
+
+use work.MVL4.all;
+
+entity memory_subsystem is
+end entity memory_subsystem;
+
+-- end not in book
+
+architecture detailed of memory_subsystem is
+
+  signal internal_data : MVL4_logic_vector(31 downto 0);
+  -- . . .
+
+  -- not in book
+  signal internal_addr : MVL4_ulogic_vector(31 downto 0);
+  signal main_mem_addr : MVL4_ulogic_vector(9 downto 0);
+  signal ROM_select : MVL4_ulogic;
+  -- end not in book
+
+begin
+
+  boot_ROM : entity work.ROM(behavioral)
+    port map ( a => internal_addr(15 downto 0),
+               d => internal_data(7 downto 0),
+               rd => ROM_select );
+
+  main_mem : entity work.SIMM(behavioral)
+    port map ( a => main_mem_addr, d => internal_data, -- . . . );
+               -- not in book
+               ras => '0', cas => '0', we => '0', cs => '0' );
+  -- end not in book
+
+  -- . . .
+
+end architecture detailed;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_08.vhd
new file mode 100644
index 0000000..9f417d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_08.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_08.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package fg_11_08 is
+
+  type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+  function resolved ( s : std_ulogic_vector ) return std_ulogic;
+
+end package fg_11_08;
+
+
+package body fg_11_08 is
+
+  -- code from book
+
+  type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
+  constant resolution_table : stdlogic_table :=
+    -- ---------------------------------------------
+    --  'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
+    -- ---------------------------------------------
+    ( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ),  --  'U'
+      ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),  --  'X'
+      ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ),  --  '0'
+      ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ),  --  '1'
+      ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ),  --  'Z'
+      ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ),  --  'W'
+      ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ),  --  'L'
+      ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ),  --  'H'
+      ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )   --  '-'
+      );
+
+  function resolved ( s : std_ulogic_vector ) return std_ulogic is
+    variable result : std_ulogic := 'Z';  -- weakest state default
+  begin
+    if s'length = 1 then
+      return s(s'low);
+    else
+      for i in s'range loop
+        result := resolution_table(result, s(i));
+      end loop;
+    end if;
+    return result;
+  end function resolved;
+
+  -- end code from book
+
+end package body fg_11_08;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_09.vhd
new file mode 100644
index 0000000..d06a9a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_09.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_09.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity bus_module is
+                 port ( synch : inout std_ulogic;  -- . . . );
+                        -- not in book
+                        other_port : in std_ulogic := 'U' );
+                 -- end not in book
+               end entity bus_module;
+
+--------------------------------------------------
+
+-- not in book
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity bus_based_system is
+               end entity bus_based_system;
+
+-- end not in book
+
+
+               architecture top_level of bus_based_system is
+
+                 signal synch_control : std_logic;
+                 -- . . .
+
+               begin
+
+                 synch_control_pull_up : synch_control <= 'H';
+
+                 bus_module_1 : entity work.bus_module(behavioral)
+                   port map ( synch => synch_control, -- . . . );
+                              -- not in book
+                              other_port => open );
+                 -- end not in book
+
+                 bus_module_2 : entity work.bus_module(behavioral)
+                   port map ( synch => synch_control, -- . . . );
+                              -- not in book
+                              other_port => open );
+                 -- end not in book
+
+                 -- . . .
+
+               end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_10.vhd
new file mode 100644
index 0000000..822cfdc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_10.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavioral of bus_module is
+begin
+
+  behavior : process is
+                       -- . . .
+                       -- not in book
+                       constant Tdelay_synch : delay_length := 10 ns;
+                     constant wait_delay : delay_length := 100 ns;
+                     -- end not in book
+  begin
+    synch <= '0'  after Tdelay_synch;
+    -- . . .
+    -- not in book
+    wait for wait_delay;
+    -- end not in book
+    -- ready to start operation
+    synch <= 'Z' after Tdelay_synch;
+    wait until synch = 'H';
+    -- . . .    -- proceed with operation
+    -- . . .
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_12.vhd
new file mode 100644
index 0000000..e2330c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_12.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package fg_11_12 is
+
+                 procedure init_synchronize ( signal synch : out std_logic );
+
+                 procedure begin_synchronize ( signal synch : inout std_logic;
+                                               Tdelay : in delay_length := 0 fs );
+
+                 procedure end_synchronize ( signal synch : inout std_logic;
+                                             Tdelay : in delay_length := 0 fs );
+
+               end package fg_11_12;
+
+
+
+               package body fg_11_12 is
+
+                 -- code from book
+
+                 procedure init_synchronize ( signal synch : out std_logic ) is
+                 begin
+                   synch <= '0';
+                 end procedure init_synchronize;
+
+                 procedure begin_synchronize ( signal synch : inout std_logic;
+                                               Tdelay : in delay_length := 0 fs ) is
+                 begin
+                   synch <= 'Z' after Tdelay;
+                   wait until synch = 'H';
+                 end procedure begin_synchronize;
+
+                 procedure end_synchronize ( signal synch : inout std_logic;
+                                             Tdelay : in delay_length := 0 fs ) is
+                 begin
+                   synch <= '0' after Tdelay;
+                   wait until synch = '0';
+                 end procedure end_synchronize;
+
+                 -- end code from book
+
+               end package body fg_11_12;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_13.vhd
new file mode 100644
index 0000000..c3943b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_11_fg_11_13.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_11_fg_11_13.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_11_13 is
+               end entity fg_11_13;
+
+
+
+               architecture test of fg_11_13 is
+
+                 use work.fg_11_12.all;
+
+                 signal barrier : std_logic;
+
+               begin
+
+                 pullup : barrier <= 'H';
+
+                 -- code from book
+
+                 synchronized_module : process is
+                                                 -- . . .
+                 begin
+                   init_synchronize(barrier);
+                   -- . . .
+                   loop
+                     -- . . .
+                     begin_synchronize(barrier);
+                     -- . . .    -- perform operation, synchronized with other processes
+                     end_synchronize(barrier);
+                     -- . . .
+                   end loop;
+                 end process synchronized_module;
+
+                 -- end code from book
+
+                 another_synchronized_module : process is
+                 begin
+                   init_synchronize(barrier);
+                   loop
+                     wait for 10 ns;
+                     begin_synchronize(barrier);
+                     -- . . .    -- perform operation, synchronized with other processes
+                     end_synchronize(barrier);
+                   end loop;
+                 end process another_synchronized_module;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_01.vhd
new file mode 100644
index 0000000..32dbe5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_01.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_ch_12_01.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity and2 is
+  generic ( Tpd : time );
+  port ( a, b : in bit;  y : out bit );
+end entity and2;
+
+architecture simple of and2 is
+begin
+
+  and2_function :
+    y <= a and b after Tpd;
+
+end architecture simple;
+
+-- end code from book
+
+entity ch_12_01 is
+
+end entity ch_12_01;
+
+library stimulus;
+use stimulus.stimulus_generators.all;
+
+architecture test of ch_12_01 is
+
+  signal a1, b1, sig1, sig2, sig_out : bit;
+  signal test_vector : bit_vector(1 to 3);
+
+begin
+
+  -- code from book
+
+  gate1 : entity work.and2(simple)
+    generic map ( Tpd => 2 ns )
+    port map ( a => sig1,  b => sig2,  y => sig_out );
+
+  gate2 : entity work.and2(simple)
+    generic map ( Tpd => 3 ns )
+    port map ( a => a1,  b => b1,  y => sig1 );
+
+  -- end code from book
+
+  stimulus : all_possible_values ( bv => test_vector,
+				   delay_between_values => 10 ns );
+
+  (sig2, a1, b1) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_02.vhd
new file mode 100644
index 0000000..17a3a97
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_02.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_ch_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity reg is
+  port ( d : in bit_vector;  q : out bit_vector;  -- . . . );
+  -- not in book
+  other_port : in bit := '0' );
+  -- end not in book
+end entity reg;
+
+-- end code from book
+
+
+architecture test of reg is
+begin
+  q <= d;
+end architecture test;
+
+
+
+entity ch_12_02 is
+
+end entity ch_12_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_12_02 is
+
+  -- code from book
+
+  signal small_data : bit_vector(0 to 7);
+  signal large_data : bit_vector(0 to 15);
+  -- . . .
+
+  -- end code from book
+
+
+begin
+
+  -- code from book
+
+  problem_reg : entity work.reg
+    port map ( d => small_data,  q => large_data, -- . . . );
+               -- not in book
+               other_port => open );
+  -- end not in book
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_03.vhd
new file mode 100644
index 0000000..e41f815
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_ch_12_03.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_ch_12_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity reg is
+  generic ( width : positive );
+  port ( d : in bit_vector(0 to width - 1);
+         q : out bit_vector(0 to width - 1);
+         -- . . . );
+         -- not in book
+         other_port : in bit := '0' );
+  -- end not in book
+end entity reg;
+
+-- end code from book
+
+
+architecture test of reg is
+begin
+  q <= d;
+end architecture test;
+
+
+
+entity ch_12_03 is
+
+end entity ch_12_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_12_03 is
+
+  constant bus_size : positive := 16;
+
+  -- code from book
+
+  signal in_data, out_data : bit_vector(0 to bus_size - 1);
+  -- . . .
+
+  -- end code from book
+
+
+begin
+
+  -- code from book
+
+  ok_reg : entity work.reg
+    generic map ( width => bus_size )
+    port map ( d => in_data,  q => out_data, -- . . . );
+               -- not in book
+               other_port => open );
+  -- end not in book
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_01.vhd
new file mode 100644
index 0000000..11a1a65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_01.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_fg_12_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity control_unit is
+
+  generic ( Tpd_clk_out, Tpw_clk : delay_length;
+            debug : boolean := false );
+
+  port ( clk : in bit;
+         ready : in bit;
+         control1, control2 : out bit );
+
+end entity control_unit;
+
+-- end code from book
+
+
+
+architecture test of control_unit is
+begin
+end architecture test;
+
+
+
+
+entity fg_12_01 is
+end entity fg_12_01;
+
+
+
+architecture test of fg_12_01 is
+
+  signal clk, ready : bit;
+
+begin
+
+  dut1 : entity work.control_unit
+    -- code from book (in text)
+    generic map ( 200 ps, 1500 ps, false )
+    -- end code from book
+    port map ( clk, ready, open, open );
+
+  dut2 : entity work.control_unit
+    -- code from book (in text)
+    generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
+    -- end code from book
+    port map ( clk, ready, open, open );
+
+  dut3 : entity work.control_unit
+    -- code from book (in text)
+    generic map ( 200 ps, 1500 ps, debug => open )
+    -- end code from book
+    port map ( clk, ready, open, open );
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_02.vhd
new file mode 100644
index 0000000..a57b894
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_02.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_fg_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity D_flipflop is
+  generic ( Tpd_clk_q, Tsu_d_clk, Th_d_clk : delay_length );
+  port ( clk, d : in bit;  q : out bit );
+end entity D_flipflop;
+
+--------------------------------------------------
+
+architecture basic of D_flipflop is
+begin
+
+  behavior : q <= d after Tpd_clk_q when clk = '1' and clk'event;
+
+  check_setup : process is
+  begin
+    wait until clk = '1';
+    assert d'last_event >= Tsu_d_clk
+      report "setup violation";
+  end process check_setup;
+
+  check_hold : process is
+  begin
+    wait until clk'delayed(Th_d_clk) = '1';
+    assert d'delayed'last_event >= Th_d_clk
+      report "hold violation";
+  end process check_hold;
+
+end architecture basic;
+
+-- end code from book
+
+
+
+entity fg_12_02 is
+end entity fg_12_02;
+
+
+
+architecture test of fg_12_02 is
+
+  signal system_clock, request, request_pending : bit := '0';
+
+begin
+
+  -- code from book (in text)
+
+  request_flipflop : entity work.D_flipflop(basic)
+    generic map ( Tpd_clk_q => 4 ns,
+                  Tsu_d_clk => 3 ns, Th_d_clk => 1 ns )
+    port map ( clk => system_clock,
+               d => request, q => request_pending );
+
+  -- end code from book
+
+  clock_gen : system_clock <= '1' after 10 ns,
+                              '0' after 20 ns when system_clock = '0';
+
+  stimulus :  request <= '1' after  25 ns, '0' after  35 ns,
+                         '1' after  67 ns, '0' after  71 ns,
+                         '1' after 108 ns, '0' after 110.5 ns;
+  
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_03.vhd
new file mode 100644
index 0000000..cdbb699
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_12_fg_12_03.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_12_fg_12_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+entity reg is
+  generic ( width : positive );
+  port ( d :  in  bit_vector(0 to width - 1);
+         q :  out  bit_vector(0 to width - 1);
+         clk, reset : in bit );
+end entity reg;
+
+--------------------------------------------------
+
+architecture behavioral of reg is
+begin
+
+  behavior : process (clk, reset) is
+                                    constant zero : bit_vector(0 to width - 1) := (others => '0');
+  begin
+    if reset = '1' then
+      q <= zero;
+    elsif clk'event and clk = '1' then
+      q <= d;
+    end if;
+  end process behavior;
+
+end architecture behavioral;
+
+-- end code from book
+
+
+
+entity fg_12_03 is
+end entity fg_12_03;
+
+
+architecture test of fg_12_03 is
+
+  -- code from book
+
+  subtype state_vector is bit_vector(1 to 5);
+
+  -- end code from book
+
+  signal clk, reset : bit := '0';
+  signal word_in, word_out : bit_vector(0 to 31);
+  signal state_in, state_out : state_vector;
+
+begin
+
+  -- code from book
+
+  word_reg : entity work.reg(behavioral)
+    generic map ( width => 32 )
+    port map ( -- . . . );
+      -- not in book
+      d => word_in, q => word_out, clk => clk, reset => reset );
+  -- end not in book
+
+  state_reg : entity work.reg(behavioral)
+    generic map ( width => state_vector'length )
+    port map ( -- . . . );
+      -- not in book
+      d => state_in, q => state_out, clk => clk, reset => reset );
+
+  -- end code from book
+
+  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+
+  reset_gen : reset <= '1' after 80 ns, '0' after 105 ns;
+
+  stimulus_word : word_in <= X"11111111" after 25 ns,
+                             X"22222222" after 65 ns,
+		             X"33333333" after 85 ns,
+		             X"44444444" after 125 ns;
+
+  stimulus_state : state_in <= "00001" after 25 ns,
+                               "00010" after 65 ns,
+		               "00011" after 85 ns,
+		               "00100" after 125 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_ch_13_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_ch_13_01.vhd
new file mode 100644
index 0000000..fae8a96
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_ch_13_01.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_ch_13_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_13_01 is
+end entity ch_13_01;
+
+
+architecture test of ch_13_01 is
+
+  -- code from book
+
+  component nand3 is
+                    port ( a, b, c : in bit := '1';  y : out bit );
+  end component nand3;
+
+  -- end code from book
+
+  signal s1, s2, s3 : bit;
+
+begin
+
+  -- code from book
+
+  gate1 : component nand3
+    port map ( a => s1, b => s2, c => open, y => s3 );
+
+  -- end code from book
+
+end architecture test;
+
+
+
+-- code from book
+
+entity nand2 is
+  port ( a, b : in bit := '1';  y : out bit );
+end entity nand2;
+
+-- end code from book
+
+
+configuration ch_13_01_test of ch_13_01 is
+
+  for test
+
+    -- code from book
+
+    for gate1 : nand3
+      use entity work.nand2(basic);
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration ch_13_01_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_01.vhd
new file mode 100644
index 0000000..eb0d1fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_01.vhd
@@ -0,0 +1,119 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity edge_triggered_Dff is
+  generic ( Tprop, Tsetup, Thold : delay_length );
+  port ( clk : in bit;  clr : in bit; d : in bit;
+  q : out bit );
+end entity edge_triggered_Dff;
+
+
+architecture basic of edge_triggered_Dff is
+begin
+
+  state_change : process (clk, clr) is
+  begin
+    if clr = '1' then
+      q <= '0' after Tprop;
+    elsif clk'event and clk = '1' then
+      q <= d after Tprop;
+    end if;
+  end process state_change;
+
+end architecture basic;
+
+
+architecture hi_fanout of edge_triggered_Dff is
+begin
+
+  state_change : process (clk, clr) is
+  begin
+    if clr = '1' then
+      q <= '0' after Tprop;
+    elsif clk'event and clk = '1' then
+      q <= d after Tprop;
+    end if;
+  end process state_change;
+
+end architecture hi_fanout;
+
+
+-- code from book
+
+entity reg4 is
+  port ( clk, clr : in bit;  d : in bit_vector(0 to 3);
+  q : out bit_vector(0 to 3) );
+end entity reg4;
+
+--------------------------------------------------
+
+architecture struct of reg4 is
+
+  component flipflop is
+                       generic ( Tprop, Tsetup, Thold : delay_length );
+                     port ( clk : in bit;  clr : in bit;  d : in bit;
+                     q : out bit );
+  end component flipflop;
+
+begin
+
+  bit0 : component flipflop
+    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
+    port map ( clk => clk, clr => clr, d => d(0), q => q(0) );
+
+  bit1 : component flipflop
+    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
+    port map ( clk => clk, clr => clr, d => d(1), q => q(1) );
+
+  bit2 : component flipflop
+    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
+    port map ( clk => clk, clr => clr, d => d(2), q => q(2) );
+
+  bit3 : component flipflop
+    generic map ( Tprop => 2 ns, Tsetup => 2 ns, Thold => 1 ns )
+    port map ( clk => clk, clr => clr, d => d(3), q => q(3) );
+
+end architecture struct;
+
+-- end code from book
+
+
+
+configuration fg_13_01 of reg4 is
+
+  for struct
+
+    -- code from book (in text)
+
+    for bit0, bit1 : flipflop
+      use entity work.edge_triggered_Dff(basic);
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration fg_13_01;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_02.vhd
new file mode 100644
index 0000000..a4ca0eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_02.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package serial_interface_defs is
+
+                 subtype reg_address_vector is std_logic_vector(1 downto 0);
+
+                 constant status_reg_address : reg_address_vector := B"00";
+                 constant control_reg_address : reg_address_vector := B"01";
+                 constant rx_data_register : reg_address_vector := B"10";
+                 constant tx_data_register : reg_address_vector := B"11";
+
+                 subtype data_vector is std_logic_vector(7 downto 0);
+
+                 -- . . .    -- other useful declarations
+
+                 component serial_interface is
+                                              port ( clock_phi1, clock_phi2 : in std_logic;
+                                                     serial_select : in std_logic;
+                                                     reg_address : in reg_address_vector;
+                                                     data : inout data_vector;
+                                                     interrupt_request : out std_logic;
+                                                     rx_serial_data : in std_logic;
+                                                     tx_serial_data : out std_logic );
+                 end component serial_interface;
+
+               end package serial_interface_defs;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_03.vhd
new file mode 100644
index 0000000..1ad9033
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_03.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               use work.serial_interface_defs.all;
+
+               entity serial_interface is
+                 port ( clock_phi1, clock_phi2 : in std_logic;
+                        serial_select : in std_logic;
+                        reg_address : in reg_address_vector;
+                        data : inout data_vector;
+                        interrupt_request : out std_logic;
+                        rx_serial_data : in std_logic;
+                        tx_serial_data : out std_logic );
+               end entity serial_interface;
+
+
+-- not in book
+
+               architecture test of serial_interface is
+               begin
+               end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_04.vhd
new file mode 100644
index 0000000..e702c81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_04.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+use work.serial_interface_defs.all;
+
+entity microcontroller is
+end entity microcontroller;
+
+-- end not in book
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture structure of microcontroller is
+
+  use work.serial_interface_defs.serial_interface;
+
+  -- . . .    -- declarations of other components, signals, etc
+
+  -- not in book
+  signal buffered_phi1, buffered_phi2, serial_a_select : std_logic;
+  signal internal_addr : std_logic_vector(1 downto 0);
+  signal internal_data_bus : data_vector;
+  signal serial_a_int_req, rx_data_a, tx_data_a : std_logic;
+  -- end not in book
+
+begin
+
+  serial_a : component serial_interface
+    port map ( clock_phi1 => buffered_phi1,
+               clock_phi2 => buffered_phi2,
+               serial_select => serial_a_select,
+               reg_address => internal_addr(1 downto 0),
+               data => internal_data_bus,
+               interrupt_request => serial_a_int_req,
+               rx_serial_data => rx_data_a,
+               tx_serial_data => tx_data_a );
+
+  -- . . .    -- other component instances
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_05.vhd
new file mode 100644
index 0000000..f09e364
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_05.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_05.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book
+
+library star_lib;
+--use star_lib.edge_triggered_Dff;
+use star_lib.all;
+
+configuration reg4_gate_level of reg4 is
+
+  for struct  -- architecture of reg4
+
+    for bit0 : flipflop
+      use entity star_lib.edge_triggered_Dff(hi_fanout);
+    end for;
+
+    for others : flipflop
+      use entity star_lib.edge_triggered_Dff(basic);
+    end for;
+
+  end for;  -- end of architecture struct
+
+end configuration reg4_gate_level;
+
+-- end code from book
+
+
+entity fg_13_05 is
+end entity fg_13_05;
+
+
+architecture test of fg_13_05 is
+
+  component reg4 is
+                   port ( clk, clr : in bit;  d : in bit_vector(0 to 3);
+                   q : out bit_vector(0 to 3) );
+  end component reg4;
+
+  signal clk, clr : bit;
+  signal d, q : bit_vector(0 to 3);
+
+begin
+
+  flag_reg : component reg4
+    port map ( clk => clk, clr => clr, d => d, q => q );
+
+end architecture test;
+
+
+configuration fg_13_05_test of fg_13_05 is
+
+  for test
+
+    -- code from book (in text)
+
+    for flag_reg : reg4
+      use configuration work.reg4_gate_level;
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration fg_13_05_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_06.vhd
new file mode 100644
index 0000000..db630d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_06.vhd
@@ -0,0 +1,135 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package counter_types is
+
+  -- code from book (in text)
+
+  subtype digit is bit_vector(3 downto 0);
+
+  -- end code from book
+
+end package counter_types;
+
+
+
+use work.counter_types.digit;
+
+entity add_1 is
+  port ( d : in digit;  y : out digit );
+end entity add_1;
+
+
+architecture boolean_eqn of add_1 is
+begin
+
+  y(0) <= not d(0) after 4 ns;
+
+  y(1) <= (not d(1) and d(0))
+          or (d(1) and not d(0)) after 4 ns;
+
+  y(2) <= (not d(2) and d(1) and d(0))
+	  or (d(2) and not (d(1) and d(0))) after 4 ns;
+
+  y(3) <= (not d(3) and d(2) and d(1) and d(0))
+	  or (d(3) and not (d(2) and d(1) and d(0))) after 4 ns;
+
+end architecture boolean_eqn;
+
+
+use work.counter_types.digit;
+
+entity buf4 is
+  port ( a : in digit;  y : out digit );
+end entity buf4;
+
+
+architecture basic of buf4 is
+begin
+
+  y(0) <= a(0) after 2 ns;
+  y(1) <= a(1) after 2 ns;
+  y(2) <= a(2) after 2 ns;
+  y(3) <= a(3) after 2 ns;
+
+end architecture basic;
+
+
+
+
+-- code from book
+
+use work.counter_types.digit;
+
+entity counter is
+  port ( clk, clr : in bit;
+         q0, q1 : out digit );
+end entity counter;
+
+--------------------------------------------------
+
+architecture registered of counter is
+
+  component digit_register is
+                             port ( clk, clr : in bit;
+                                    d : in digit;
+                                    q : out digit );
+  end component digit_register;
+
+  signal current_val0, current_val1, next_val0, next_val1 : digit;
+
+begin
+
+  val0_reg : component digit_register
+    port map ( clk => clk, clr => clr, d => next_val0,
+               q => current_val0 );
+
+  val1_reg : component digit_register
+    port map ( clk => clk, clr => clr, d => next_val1,
+               q => current_val1 );
+
+  -- other component instances
+  -- . . .
+
+  -- not in book
+
+  incr0 : entity work.add_1(boolean_eqn)
+    port map ( d => current_val0, y => next_val0 );
+
+  incr1 : entity work.add_1(boolean_eqn)
+    port map ( d => current_val1, y => next_val1 );
+
+  buf0 : entity work.buf4(basic)
+    port map ( a => current_val0, y => q0 );
+
+  buf1 : entity work.buf4(basic)
+    port map ( a => current_val1, y => q1 );
+
+  -- end not in book
+
+end architecture registered;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_07.vhd
new file mode 100644
index 0000000..d8bb53a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_07.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration counter_down_to_gate_level of counter is
+
+  for registered
+
+    for all : digit_register
+      use configuration work.reg4_gate_level;
+    end for;
+
+    -- . . .    -- bindings for other component instances
+
+  end for;  -- end of architecture registered
+
+end configuration counter_down_to_gate_level;
+
+
+
+-- not in book
+
+entity fg_13_07 is
+end entity fg_13_07;
+
+
+use work.counter_types.all;
+
+architecture test of fg_13_07 is
+
+  signal clk, clr : bit := '0';
+  signal q0, q1 : digit;
+
+begin
+
+  dut : configuration work.counter_down_to_gate_level
+    port map ( clk => clk, clr => clr,
+               q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 20 ns;
+
+  clr_gen : clr <= '1' after 95 ns,
+		   '0' after 135 ns;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_08.vhd
new file mode 100644
index 0000000..92068dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_08.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+library star_lib;
+--use star_lib.edge_triggered_dff;
+use star_lib.all;
+
+configuration full of counter is
+
+  for registered  -- architecture of counter
+
+    for all : digit_register
+      use entity work.reg4(struct);
+
+      for struct  -- architecture of reg4
+
+        for bit0 : flipflop
+          use entity edge_triggered_Dff(hi_fanout);
+        end for;
+
+        for others : flipflop
+          use entity edge_triggered_Dff(basic);
+        end for;
+
+      end for;  -- end of architecture struct
+
+    end for;
+
+    -- . . .    -- bindings for other component instances
+
+  end for;  -- end of architecture registered
+
+end configuration full;
+
+
+
+-- not in book
+
+entity fg_13_08 is
+end entity fg_13_08;
+
+
+use work.counter_types.all;
+
+architecture test of fg_13_08 is
+
+  signal clk, clr : bit := '0';
+  signal q0, q1 : digit;
+
+begin
+
+  dut : configuration work.full
+    port map ( clk => clk, clr => clr,
+               q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 20 ns;
+
+  clr_gen : clr <= '1' after 95 ns,
+		   '0' after 135 ns;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_09.vhd
new file mode 100644
index 0000000..10dc09b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_09.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity alarm_clock is
+end entity alarm_clock;
+
+-- end not in book
+
+
+architecture top_level of alarm_clock is
+
+  --use work.counter_types.digit;
+  use work.counter_types.all;
+
+  signal reset_to_midnight, seconds_clk : bit;
+  signal seconds_units, seconds_tens : digit;
+  -- . . .
+
+begin
+
+  seconds : configuration work.counter_down_to_gate_level
+    port map ( clk => seconds_clk, clr => reset_to_midnight,
+               q0 => seconds_units, q1 => seconds_tens );
+
+  -- . . .
+
+  -- not in book
+
+  clk_gen : seconds_clk <= not seconds_clk after 20 ns;
+
+  clr_gen : reset_to_midnight <= '1' after 95 ns,
+		                 '0' after 135 ns;
+
+  -- end not in book;
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_10.vhd
new file mode 100644
index 0000000..9c7314e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_10.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity reg is
+                 generic ( t_setup, t_hold, t_pd : delay_length;
+                           width : positive );
+                 port ( clock : in std_logic;
+                        data_in : in std_logic_vector(0 to width - 1);
+                        data_out : out std_logic_vector(0 to width - 1) );
+               end entity reg;
+
+
+
+-- not in book
+
+               architecture gate_level of reg is
+               begin
+               end architecture gate_level;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_11.vhd
new file mode 100644
index 0000000..bc4a155
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_11.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_11.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity controller is
+               end entity controller;
+
+-- end not in book
+
+
+               architecture structural of controller is
+
+                 component reg is
+                                 generic ( width : positive );
+                               port ( clock : in std_logic;
+                                      data_in : in std_logic_vector(0 to width - 1);
+                                      data_out : out std_logic_vector(0 to width - 1) );
+                 end component reg;
+
+                 -- . . .
+
+                 -- not in book
+                 subtype state_type is std_logic_vector(0 to 5);
+                 signal clock_phase1 : std_logic;
+                 signal next_state, current_state : state_type;
+                 -- end not in book
+
+               begin
+
+                 state_reg : component reg
+                   generic map ( width => state_type'length )
+                   port map ( clock => clock_phase1,
+                              data_in => next_state,
+                              data_out => current_state );
+
+                 -- . . .
+
+               end architecture structural;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_12.vhd
new file mode 100644
index 0000000..02ae148
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_12.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration controller_with_timing of controller is
+
+  for structural
+
+    for state_reg : reg
+      use entity work.reg(gate_level)
+        generic map ( t_setup => 200 ps, t_hold => 150 ps, t_pd => 150 ps,
+                      width => width );
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration controller_with_timing;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_13.vhd
new file mode 100644
index 0000000..0868c64
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_13.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_13.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+
+library stimulus;  
+use stimulus.stimulus_generators.all;
+
+-- end not in book
+
+architecture structure of computer_system is
+
+  component decoder_2_to_4 is
+                             generic ( prop_delay : delay_length );
+                           port ( in0, in1 : in bit;
+                                  out0, out1, out2, out3 : out bit );
+  end component decoder_2_to_4;
+
+  -- . . .
+
+  -- not in book
+
+  signal addr : bit_vector(5 downto 4);
+  signal interface_a_select, interface_b_select,
+    interface_c_select, interface_d_select : bit;
+  -- end not in book
+
+begin
+
+  interface_decoder : component decoder_2_to_4
+    generic map ( prop_delay => 4 ns )
+    port map ( in0 => addr(4), in1 => addr(5),
+               out0 => interface_a_select, out1 => interface_b_select,
+               out2 => interface_c_select, out3 => interface_d_select );
+
+  -- . . .
+
+  -- not in book
+
+  all_possible_values(addr, 10 ns);
+
+  -- end not in book
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_14.vhd
new file mode 100644
index 0000000..b03f1d2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_14.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_14.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity decoder_3_to_8 is
+  generic ( Tpd_01, Tpd_10 : delay_length );
+  port ( s0, s1, s2 : in bit;
+         enable : in bit;
+         y0, y1, y2, y3, y4, y5, y6, y7 : out bit );
+end entity decoder_3_to_8;
+
+
+-- not in book
+
+architecture basic of decoder_3_to_8 is
+begin
+
+  process (enable, s2, s1, s0) is
+  begin
+    if enable = '0' then
+      (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000000");
+    else
+      case bit_vector'(s2, s1, s0) is
+        when "000" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000001");
+        when "001" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000010");
+        when "010" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000100");
+        when "011" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00001000");
+        when "100" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00010000");
+        when "101" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00100000");
+        when "110" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("01000000");
+        when "111" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("10000000");
+      end case;
+    end if;
+  end process;
+
+end architecture basic;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_15.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_15.vhd
new file mode 100644
index 0000000..a8bed90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_15.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_15.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration computer_structure of computer_system is
+
+  for structure
+
+    for interface_decoder : decoder_2_to_4
+      use entity work.decoder_3_to_8(basic)
+        generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
+        port map ( s0 => in0, s1 => in1, s2 => '0',
+                   enable => '1',
+                   y0 => out0, y1 => out1, y2 => out2, y3 => out3,
+                   y4 => open, y5 => open, y6 => open, y7 => open );
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration computer_structure;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_17.vhd
new file mode 100644
index 0000000..0617981
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_17.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_17.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+entity single_board_computer is
+end entity single_board_computer;
+-- end not in book
+
+
+architecture structural of single_board_computer is
+
+  -- . . .    -- type and signal declarations
+
+  -- not in book
+
+  subtype word is bit_vector(31 downto 0);
+  signal sys_clk : bit;
+  signal cpu_a_d, latched_addr : word;
+
+  -- end not in book
+
+  component processor is
+                        port ( clk : in bit;  a_d : inout word; -- . . . );
+                        -- not in book
+                        other_port : in bit := '0' );
+                      -- end not in book
+  end component processor;
+
+  component memory is
+                     port ( addr : in bit_vector(25 downto 0); -- . . . );
+                            -- not in book
+                            other_port : in bit := '0' );
+                   -- end not in book
+  end component memory;
+
+  component serial_interface is
+                               port ( clk : in bit;  address : in bit_vector(3 downto 0); -- . . . );
+                               -- not in book
+                               other_port : in bit := '0' );
+                             -- end not in book
+  end component serial_interface;
+
+begin
+
+  cpu : component processor
+    port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . );
+               -- not in book
+               other_port => open );
+  -- end not in book
+
+  main_memory : component memory
+    port map ( addr => latched_addr(25 downto 0), -- . . . );
+               -- not in book
+               other_port => open );
+  -- end not in book
+
+  serial_interface_a : component serial_interface
+    port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . );
+               -- not in book
+               other_port => open );
+  -- end not in book
+
+  -- . . .
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd
new file mode 100644
index 0000000..e7ba617
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_18.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_18.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity XYZ3000_cpu is
+  port ( clock : in bit;  addr_data : inout bit_vector(31 downto 0);
+  other_port : in bit := '0' );
+end entity XYZ3000_cpu;
+
+architecture full_function of XYZ3000_cpu is
+begin
+end architecture full_function;
+
+
+entity memory_array is
+  port ( addr : in bit_vector(25 downto 0);  other_port : in bit := '0' );
+end entity memory_array;
+
+
+architecture behavioral of memory_array is
+begin
+end architecture behavioral;
+
+-- code from book
+
+library chips;
+
+configuration intermediate of single_board_computer is
+
+  for structural
+
+    for cpu : processor
+      use entity chips.XYZ3000_cpu(full_function)
+        port map ( clock => clk, addr_data => a_d, -- . . . );
+                   -- not in book
+                   other_port => open );
+      -- end not in book
+    end for;
+
+    for main_memory : memory
+      use entity work.memory_array(behavioral);
+    end for;
+
+    for all : serial_interface
+      use open;
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration intermediate;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_19.vhd
new file mode 100644
index 0000000..bcd3ee4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_19.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_19.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book (in text)
+
+entity nand3 is
+  port ( a, b, c : in bit;  y : out bit );
+end entity nand3;
+
+-- end code from book
+
+architecture behavioral of nand3 is
+begin
+  y <= not (a and b and c);
+end architecture behavioral;
+
+
+entity logic_block is
+end entity logic_block;
+
+
+-- code from book
+
+library gate_lib;
+
+architecture ideal of logic_block is
+
+  component nand2 is
+                    port ( in1, in2 : in bit;  result : out bit );
+  end component nand2;
+
+  for all : nand2
+    use entity gate_lib.nand3(behavioral)
+    port map ( a => in1, b => in2, c => '1', y => result );
+
+  -- . . .    -- other declarations
+
+  -- not in book
+  signal s1, s2, s3 : bit := '0';
+
+begin
+
+  gate1 : component nand2
+    port map ( in1 => s1, in2 => s2, result => s3 );
+
+  -- . . .    -- other concurrent statements
+
+  -- not in book
+
+  s1 <= '1' after 20 ns;
+
+  s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
+
+  -- end not in book
+
+end architecture ideal;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_20.vhd
new file mode 100644
index 0000000..18e9e4c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_20.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_20.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity control_section is
+               end entity control_section;
+
+-- end not in book
+
+
+               architecture structural of control_section is
+
+                 component reg is
+                                 generic ( width : positive );
+                               port ( clk : in std_logic;
+                                      d : in std_logic_vector(0 to width - 1);
+                                      q : out std_logic_vector(0 to width - 1) );
+                 end component reg;
+
+                 for flag_reg : reg
+                   use entity work.reg(gate_level)
+                   -- workaround for MTI bug mt023
+                   -- port map ( clock => clk, data_in => d, data_out => q );
+                   port map ( clock => clk, data_in => d, data_out => q, reset_n => '1' );
+                 -- end workaround
+
+                 -- . . .
+
+                 -- not in book
+                 signal clock_phase1, zero_result, neg_result, overflow_result,
+                   zero_flag, neg_flag, overflow_flag : std_logic;
+                 -- end not in book
+
+               begin
+
+                 flag_reg : component reg
+                   generic map ( width => 3 )
+                   port map ( clk => clock_phase1,
+                              d(0) => zero_result, d(1) => neg_result,
+                              d(2) => overflow_result,
+                              q(0) => zero_flag, q(1) => neg_flag,
+                              q(2) => overflow_flag );
+
+                 -- . . .
+
+                 -- not in book
+
+                 stimulus : process is
+                 begin
+                   clock_phase1 <= '0';
+                   zero_result <= '0'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '0'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '0'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '0'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '1'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '1'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '1'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+                   zero_result <= '1'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
+                   clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+                 -- end not in book
+
+               end architecture structural;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_21.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_21.vhd
new file mode 100644
index 0000000..0042431
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_21.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_21.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity reg is
+                 generic ( t_setup, t_hold, t_pd : delay_length;
+                           width : positive );
+                 port ( clock : in std_logic;
+                        reset_n : in std_logic;
+                        data_in : in std_logic_vector(0 to width - 1);
+                        data_out : out std_logic_vector(0 to width - 1) );
+               end entity reg;
+
+
+
+-- not in book
+
+               architecture gate_level of reg is
+
+               begin
+
+                 store : process (clock, reset_n) is
+                 begin
+                   if reset_n = '0' or reset_n = 'L' then
+                     data_out <= (others => '0') after t_pd;
+                   elsif rising_edge(clock) then
+                     data_out <= data_in after t_pd;
+                   end if;
+                 end process store;
+
+               end architecture gate_level;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_22.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_22.vhd
new file mode 100644
index 0000000..632a10a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_22.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_22.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration controller_with_timing of control_section is
+
+  for structural
+
+    for flag_reg : reg
+      generic map ( t_setup => 200 ps, t_hold => 150 ps,
+                    t_pd => 150 ps, width => width )
+        -- workaround for MTI bug mt023
+        -- port map ( reset_n => '1');
+        ;
+      -- end workaround
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration controller_with_timing;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_23.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_23.vhd
new file mode 100644
index 0000000..a35bddb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_23.vhd
@@ -0,0 +1,121 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_23.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity nor_gate is
+                 generic ( width : positive;
+                           Tpd01, Tpd10 : delay_length );
+                 port ( input : in std_logic_vector(0 to width - 1);
+                        output : out std_logic );
+               end entity nor_gate;
+
+
+               architecture primitive of nor_gate is
+
+                 function max ( a, b : delay_length ) return delay_length is
+                 begin
+                   if a > b then
+                     return a;
+                   else
+                     return b;
+                   end if;
+                 end function max;
+
+               begin
+
+                 reducer : process (input) is
+                                             variable result : std_logic;
+                 begin
+                   result := '0';
+                   for index in input'range loop
+                     result := result or input(index);
+                   end loop;
+                   if not result = '1' then
+                     output <= not result after Tpd01;
+                   elsif not result = '0' then
+                     output <= not result after Tpd10;
+                   else
+                     output <= not result after max(Tpd01, Tpd10);
+                   end if;
+                 end process reducer;
+
+               end architecture primitive;
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+               library cell_lib;
+
+               entity interlock_control is
+               end entity interlock_control;
+
+
+-- code from book
+
+               architecture detailed_timing of interlock_control is
+
+                 component nor_gate is
+                                      generic ( input_width : positive );
+                                    port ( input : in std_logic_vector(0 to input_width - 1);
+                                           output : out std_logic );
+                 end component nor_gate;
+
+                 for ex_interlock_gate : nor_gate
+                   use entity cell_lib.nor_gate(primitive)
+                   generic map ( width => input_width,
+                                 Tpd01 => 250 ps, Tpd10 => 200 ps );  -- estimates
+
+                 -- . . .
+
+                 -- not in book
+                 signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
+                 -- end not in book
+
+               begin
+
+                 ex_interlock_gate : component nor_gate
+                   generic map ( input_width => 2 )
+                   port map ( input(0) => reg_access_hazard,
+                              input(1) => load_hazard,
+                              output => stall_ex_n);
+
+                 -- . . .
+
+                 -- not in book
+
+                 reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;
+
+                 load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
+                                '0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
+                                '0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
+                                '0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;
+
+                 -- end not in book
+
+               end architecture detailed_timing;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_24.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_24.vhd
new file mode 100644
index 0000000..cca5943
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_24.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_24.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration interlock_control_with_estimates of interlock_control is
+
+  for detailed_timing
+
+  end for;
+
+  -- . . .
+
+end configuration interlock_control_with_estimates;
+
+--------------------------------------------------
+
+configuration interlock_control_with_actual of interlock_control is
+
+  for detailed_timing
+
+    for ex_interlock_gate : nor_gate
+      generic map ( Tpd01 => 320 ps, Tpd10 => 230 ps );
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration interlock_control_with_actual;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_25.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_25.vhd
new file mode 100644
index 0000000..8e24ede
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_25.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity nand3 is
+  generic ( Tpd : delay_length );
+  port ( a, b, c : in bit;  y : out bit );
+end entity nand3;
+
+architecture basic of nand3 is
+begin
+  y <= not (a and b and c) after Tpd;
+end architecture basic;
+
+
+library project_lib;
+library stimulus;  
+use stimulus.stimulus_generators.all;
+
+entity misc_logic is
+end entity misc_logic;
+
+-- code from book
+
+architecture gate_level of misc_logic is
+
+  component nand3 is
+                    generic ( Tpd : delay_length );
+                  port ( a, b, c : in bit;  y : out bit );
+  end component nand3;
+
+  for all : nand3
+    use entity project_lib.nand3(basic);
+
+  -- . . .
+
+  -- not in book
+  signal sig1, sig2, sig3, out_sig : bit;
+  signal test_vector : bit_vector(1 to 3);
+  -- end not in book
+
+begin
+
+  gate1 : component nand3
+    generic map ( Tpd => 2 ns )
+    port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
+
+  -- . . .
+
+  -- not in book
+
+  all_possible_values(test_vector, 10 ns);
+
+  (sig1, sig2, sig3) <= test_vector;
+
+  -- end not in book
+
+end architecture gate_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_26.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_26.vhd
new file mode 100644
index 0000000..f7e3c10
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_13_fg_13_26.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_13_fg_13_26.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration misc_logic_reconfigured of misc_logic is
+
+  for gate_level
+
+    for gate1 : nand3
+      generic map ( Tpd => 1.6 ns )
+        port map ( a => c, c => a, b => b, y => y );
+    end for;
+
+  end for;
+
+end configuration misc_logic_reconfigured;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_ch_14_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_ch_14_01.vhd
new file mode 100644
index 0000000..e6704b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_ch_14_01.vhd
@@ -0,0 +1,144 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_ch_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity buf is
+                 port ( a : in std_logic;  y : out std_logic );
+               end buf;
+
+
+               architecture basic of buf is
+               begin
+                 y <= a;
+               end basic;
+
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fanout_tree is
+                 generic ( height : natural );
+                 port ( input : in std_logic;
+                        output : out std_logic_vector (0 to 2**height - 1) );
+               end fanout_tree;
+
+--------------------------------------------------
+
+               architecture recursive of fanout_tree is
+
+                 component buf
+                   port ( a : in std_logic;  y : out std_logic );
+                 end component;
+
+                 component fanout_tree
+                   generic ( height : natural );
+                   port ( input : in std_logic;
+                          output : out std_logic_vector (0 to 2**height - 1) );
+                 end component;
+
+                 signal buffered_input_0, buffered_input_1 : std_logic;
+
+               begin
+
+                 degenerate_tree : if height = 0 generate
+                   output(0) <= input;
+                 end generate degenerate_tree;
+
+                 compound_tree : if height > 0 generate
+
+                   buf_0 : buf
+                     port map ( a => input, y => buffered_input_0 );
+
+                   -- code from book
+
+                   block_0 : block
+                     for subtree_0 : fanout_tree
+                       use entity work.fanout_tree(recursive);
+                   begin
+                     subtree_0 : fanout_tree
+                       generic map ( height => height - 1 )
+                       port map (  input => buffered_input_0,
+                                   output => output(0 to 2**(height - 1) - 1) );
+                   end block block_0;
+
+                   -- end code from book
+
+                   buf_1 : buf
+                     port map ( a => input, y => buffered_input_1 );
+
+                   block_1 : block
+                     for subtree_1 : fanout_tree
+                       use entity work.fanout_tree(recursive);
+                   begin
+                     subtree_1 : fanout_tree
+                       generic map ( height => height - 1 )
+                       port map ( input => buffered_input_1,
+                                  output => output(2**(height - 1) to 2**height - 1) );
+                   end block block_1;
+
+                 end generate compound_tree;
+
+               end recursive;
+
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity ch_14_01 is
+               end ch_14_01;
+
+
+               architecture test of ch_14_01 is
+
+                 component fanout_tree
+                   generic ( height : natural );
+                   port ( input : in std_logic;
+                          output : out std_logic_vector (0 to 2**height - 1) );
+                 end component;
+
+                 for clock_buffer_tree : fanout_tree
+                   use entity work.fanout_tree(recursive);
+
+                 signal unbuffered_clock : std_logic;
+                 signal buffered_clock_array : std_logic_vector(0 to 7);
+
+               begin
+
+                 clock_buffer_tree : fanout_tree
+                   generic map ( height => 3 )
+                   port map ( input => unbuffered_clock,
+                              output => buffered_clock_array );
+
+                 clock_gen : process
+                 begin
+                   unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
+                   wait for 10 ns;
+                 end process clock_gen;
+
+               end test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_01.vhd
new file mode 100644
index 0000000..74fa3e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_01.vhd
@@ -0,0 +1,171 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity D_flipflop is
+                 port ( clk : in std_logic;  d : in std_logic;
+                 q : out std_logic );
+               end entity D_flipflop;
+
+
+               architecture synthesized of D_flipflop is
+               begin
+                 q <= d when not clk'stable and (To_X01(clk) = '1') and 
+                      (To_X01(clk'last_value) = '0');
+               end architecture synthesized;
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity tristate_buffer is
+                 port ( a : in std_logic;
+                        en : in std_logic;
+                        y : out std_logic );
+               end entity tristate_buffer;
+
+
+               architecture synthesized of tristate_buffer is
+               begin
+                 y <= 'X' when is_X(en) else
+                      a  when To_X01(en) = '1' else
+                      'Z';
+               end architecture synthesized;
+
+
+
+-- code from book (in Figure 14-1)
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity register_tristate is
+                 generic ( width : positive );
+                 port ( clock : in std_logic;
+                        out_enable : in std_logic;
+                        data_in : in std_logic_vector(0 to width - 1);
+                        data_out : out std_logic_vector(0 to width - 1) );
+               end entity register_tristate;
+
+--------------------------------------------------
+
+               architecture cell_level of register_tristate is
+
+                 component D_flipflop is
+                                        port ( clk : in std_logic;  d : in std_logic;
+                                        q : out std_logic );
+                 end component D_flipflop;
+
+                 component tristate_buffer is
+                                             port ( a : in std_logic;
+                                                    en : in std_logic;
+                                                    y : out std_logic );
+                 end component tristate_buffer;
+
+               begin
+
+                 cell_array : for bit_index in 0 to width - 1 generate
+
+                   signal data_unbuffered : std_logic;
+
+                 begin
+
+                   cell_storage : component D_flipflop
+                     port map ( clk => clock, d => data_in(bit_index),
+                                q => data_unbuffered );
+
+                   cell_buffer : component tristate_buffer
+                     port map ( a => data_unbuffered, en => out_enable,
+                                y => data_out(bit_index) );
+
+                 end generate cell_array;
+
+               end architecture cell_level;
+
+-- end code from book (in Figure 14-1)
+
+
+-- code from book (in Figure 14-11)
+
+               library cell_lib;
+
+               configuration identical_cells of register_tristate is
+
+                 for cell_level
+
+                   for cell_array
+
+                   for cell_storage : D_flipflop
+                   use entity cell_lib.D_flipflop(synthesized);
+               end for;
+
+               for cell_buffer : tristate_buffer
+                 use entity cell_lib.tristate_buffer(synthesized);
+               end for;
+
+               end for;
+
+               end for;
+
+               end configuration identical_cells;
+
+-- code from book (in Figure 14-11)
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_14_01 is
+               end entity fg_14_01;
+
+
+               architecture test of fg_14_01 is
+
+                 signal clk, en : std_logic;
+                 signal d_in, d_out : std_logic_vector(0 to 3);
+
+               begin
+
+                 dut : configuration work.identical_cells
+                   generic map ( width => d_in'length )
+                   port map ( clock => clk, out_enable => en,
+                              data_in => d_in, data_out => d_out );
+
+                 stimulus : process is
+                 begin
+                   wait for 10 ns;
+                   d_in <= "0000";  en <= '0';  clk <= '0';  wait for 10 ns;
+                   clk <= '1', '0' after 5 ns;  wait for 10 ns;
+                   en <= '1', '0' after 5 ns;   wait for 10 ns;
+                   d_in <= "0101";              wait for 10 ns;
+                   clk <= '1', '0' after 5 ns;  wait for 10 ns;
+                   en <= 'H', '0' after 5 ns;   wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+               end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_02.vhd
new file mode 100644
index 0000000..11fec16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_02.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity graphics_engine is
+end entity graphics_engine;
+
+-- end not in book
+
+
+architecture behavioral of graphics_engine is
+
+  type point is array (1 to 3) of real;
+  type transformation_matrix is array (1 to 3, 1 to 3) of real;
+
+  signal p, transformed_p : point;
+  signal a : transformation_matrix;
+  signal clock : bit;
+  -- . . .
+
+begin
+
+  transform_stage : for i in 1 to 3 generate
+  begin
+
+    cross_product_transform : process is
+                                        variable result1, result2, result3 : real := 0.0;
+    begin
+      wait until clock = '1';
+      transformed_p(i) <= result3;
+      result3 := result2;
+      result2 := result1;
+      result1 :=  a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
+    end process cross_product_transform;
+
+  end generate transform_stage;
+
+  -- . . .    -- other stages in the pipeline, etc
+
+  -- not in book
+
+  clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
+
+  stimulus : process is
+  begin
+    a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
+    p <= ( 10.0, 10.0, 10.0 );
+    wait until clock = '0';
+    p <= ( 20.0, 20.0, 20.0 );
+    wait until clock = '0';
+    p <= ( 30.0, 30.0, 30.0 );
+    wait until clock = '0';
+    p <= ( 40.0, 40.0, 40.0 );
+    wait until clock = '0';
+    p <= ( 50.0, 50.0, 50.0 );
+    wait until clock = '0';
+    p <= ( 60.0, 60.0, 60.0 );
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_04.vhd
new file mode 100644
index 0000000..d0d828c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_04.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_04.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity DRAM is
+                 port ( a :  in std_logic_vector(0 to 10);
+                        d :  inout std_logic_vector(0 to 3);
+                        cs, we, ras, cas : in std_logic );
+               end entity DRAM;
+
+
+               architecture empty of DRAM is
+               begin
+                 d <= (others => 'Z');
+               end architecture empty;
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity memory_board is
+               end entity memory_board;
+
+-- end not in book
+
+
+               architecture chip_level of memory_board is
+
+                 component DRAM is
+                                  port ( a :  in std_logic_vector(0 to 10);
+                                         d :  inout std_logic_vector(0 to 3);
+                                         cs, we, ras, cas : in std_logic );
+                 end component DRAM;
+
+                 signal buffered_address : std_logic_vector(0 to 10);
+                 signal DRAM_data : std_logic_vector(0 to 31);
+                 signal bank_select : std_logic_vector(0 to 3);
+                 signal buffered_we, buffered_ras, buffered_cas : std_logic;
+
+                 -- . . .    -- other declarations
+
+               begin
+
+                 bank_array : for bank_index in 0 to 3 generate
+                 begin
+
+                   nibble_array : for nibble_index in 0 to 7 generate
+
+                     constant data_lo : natural := nibble_index * 4;
+                     constant data_hi : natural := nibble_index * 4 + 3;
+
+                   begin
+
+                     a_DRAM : component DRAM
+                       port map ( a => buffered_address,
+                                  d => DRAM_data(data_lo to data_hi),
+                                  cs => bank_select(bank_index),
+                                  we => buffered_we,
+                                  ras => buffered_ras,
+                                  cas => buffered_cas );
+
+                   end generate nibble_array;
+
+                 end generate bank_array;
+
+                 -- . . .    -- other component instances, etc
+
+                 -- not in book
+
+                 buffered_address <= "01010101010";
+                 DRAM_data <= X"01234567";
+
+                 -- end not in book
+
+               end architecture chip_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_05.vhd
new file mode 100644
index 0000000..e0784d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_05.vhd
@@ -0,0 +1,152 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_05.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity master_slave_flipflop is
+                 port ( phi1, phi2 : in std_logic;
+                        d : in std_logic;
+                        q : out std_logic );
+               end entity master_slave_flipflop;
+
+
+               architecture behavioral of master_slave_flipflop is
+
+                 signal master_d : std_logic;
+
+               begin
+
+                 master_d <= d when phi1 = '1';
+
+                 q <= master_d when phi2 = '1';
+
+               end architecture behavioral;
+
+
+
+
+
+-- code from book
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity shift_reg is
+                 port ( phi1, phi2 : in std_logic;
+                        serial_data_in : in std_logic;
+                        parallel_data : inout std_logic_vector );
+               end entity shift_reg;
+
+--------------------------------------------------
+
+               architecture cell_level of shift_reg is
+
+                 alias normalized_parallel_data :
+                   std_logic_vector(0 to parallel_data'length - 1)
+                   is parallel_data;
+
+                 component master_slave_flipflop is
+                                                   port ( phi1, phi2 : in std_logic;
+                                                          d : in std_logic;
+                                                          q : out std_logic );
+                 end component master_slave_flipflop;
+
+               begin
+
+                 reg_array : for index in normalized_parallel_data'range generate
+                 begin
+
+                   first_cell : if index = 0 generate
+                   begin
+                     cell : component master_slave_flipflop
+                       port map ( phi1, phi2,
+                                  d => serial_data_in,
+                                  q => normalized_parallel_data(index) );
+                   end generate first_cell;
+
+                   other_cell : if index /= 0 generate
+                   begin
+                     cell : component master_slave_flipflop
+                       port map ( phi1, phi2,
+                                  d => normalized_parallel_data(index - 1),
+                                  q => normalized_parallel_data(index) );
+                   end generate other_cell;
+
+                 end generate reg_array;
+
+               end architecture cell_level;
+
+-- end code from book
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_14_05 is
+               end entity fg_14_05;
+
+
+               architecture test of fg_14_05 is
+
+                 signal phi1, phi2, serial_data_in : std_logic := '0';
+                 signal parallel_data : std_logic_vector(3 downto 0);
+
+               begin
+
+                 dut : entity work.shift_reg(cell_level)
+                   port map ( phi1 => phi1, phi2 => phi2,
+                              serial_data_in => serial_data_in,
+                              parallel_data => parallel_data );
+
+                 clock_gen : process is
+                 begin
+                   phi1 <= '1', '0' after 4 ns;
+                   phi2 <= '1' after 5 ns, '0' after 9 ns;
+                   wait for 10 ns;
+                 end process clock_gen;
+
+                 stimulus : process is
+                 begin
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';
+
+                   wait;
+                 end process stimulus;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_06.vhd
new file mode 100644
index 0000000..eb19069
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_06.vhd
@@ -0,0 +1,175 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book (in text)
+
+entity computer_system is
+  generic ( instrumented : boolean := false );
+  port ( -- . . . );
+    -- not in book
+    other_port : in bit := '0' );
+  -- end not in book
+end entity computer_system;
+
+-- end code from book
+
+
+-- code from book
+
+architecture block_level of computer_system is
+
+  -- . . .    -- type and component declarations for cpu and memory, etc
+
+  signal clock : bit;    -- the system clock
+  signal mem_req : bit;  -- cpu access request to memory
+  signal ifetch : bit;   -- indicates access is to fetch an instruction
+  signal write : bit;    -- indicates access is a write
+  -- . . .                  -- other signal declarations
+
+begin
+
+  -- . . .    -- component instances for cpu and memory, etc
+
+  instrumentation : if instrumented generate
+
+    signal ifetch_freq, write_freq, read_freq : real := 0.0;
+
+  begin
+
+    access_monitor : process is
+                               variable access_count, ifetch_count,
+                             write_count, read_count : natural := 0;
+    begin
+      wait until mem_req = '1';
+      if ifetch = '1' then
+        ifetch_count := ifetch_count + 1;
+      elsif write = '1' then
+        write_count := write_count + 1;
+      else
+        read_count := read_count + 1;
+      end if;
+      access_count := access_count + 1;
+      ifetch_freq <= real(ifetch_count) / real(access_count);
+      write_freq <= real(write_count) / real(access_count);
+      read_freq <= real(read_count) / real(access_count);
+    end process access_monitor;
+
+  end generate instrumentation;
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    ifetch <= '1';  write <= '0';
+    mem_req <= '1', '0' after 10 ns;
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '1';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture block_level;
+
+-- end code from book
+
+
+
+entity fg_14_06 is
+end entity fg_14_06;
+
+
+architecture test of fg_14_06 is
+
+  component computer_system is
+                              port ( other_port : in bit := '0' );
+  end component computer_system;
+
+begin
+
+  system_under_test : component computer_system
+    port map ( other_port => open );
+
+end architecture test;
+
+
+
+configuration fg_14_06_test of fg_14_06 is
+
+  for test
+
+    -- code from book (in text)
+
+    for system_under_test : computer_system
+      use entity work.computer_system(block_level)
+        generic map ( instrumented => true )
+        -- . . .
+        -- not in book
+        ;
+      -- end not in book
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration fg_14_06_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_08.vhd
new file mode 100644
index 0000000..321ab2b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_08.vhd
@@ -0,0 +1,119 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_08.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity buf is
+                 port ( a : in std_logic;  y : out std_logic );
+               end entity buf;
+
+
+               architecture basic of buf is
+               begin
+                 y <= a;
+               end architecture basic;
+
+
+
+
+-- code from book
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fanout_tree is
+                 generic ( height : natural );
+                 port ( input : in std_logic;
+                        output : out std_logic_vector (0 to 2**height - 1) );
+               end entity fanout_tree;
+
+--------------------------------------------------
+
+               architecture recursive of fanout_tree is
+
+               begin
+
+                 degenerate_tree : if height = 0 generate
+                 begin
+                   output(0) <= input;
+                 end generate degenerate_tree;
+
+                 compound_tree : if height > 0 generate
+                   signal buffered_input_0, buffered_input_1 : std_logic;
+                 begin
+
+                   buf_0 : entity work.buf(basic)
+                     port map ( a => input, y => buffered_input_0 );
+
+                   subtree_0 : entity work.fanout_tree(recursive)
+                     generic map ( height => height - 1 )
+                     port map ( input => buffered_input_0,
+                                output => output(0 to 2**(height - 1) - 1) );
+
+                   buf_1 : entity work.buf(basic)
+                     port map ( a => input, y => buffered_input_1 );
+
+                   subtree_1 : entity work.fanout_tree(recursive)
+                     generic map ( height => height - 1 )
+                     port map ( input => buffered_input_1,
+                                output => output(2**(height - 1) to 2**height - 1) );
+
+                 end generate compound_tree;
+
+               end architecture recursive;
+
+-- end code from book
+
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_14_08 is
+               end entity fg_14_08;
+
+
+               architecture test of fg_14_08 is
+
+                 signal unbuffered_clock : std_logic;
+                 signal buffered_clock_array : std_logic_vector(0 to 7);
+
+               begin
+
+                 -- code from book (in text)
+
+                 clock_buffer_tree : entity work.fanout_tree(recursive)
+                   generic map ( height => 3 )
+                   port map ( input => unbuffered_clock,
+                              output => buffered_clock_array );
+
+                 -- end code from book
+
+                 clock_gen : process is
+                 begin
+                   unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
+                   wait for 10 ns;
+                 end process clock_gen;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_09.vhd
new file mode 100644
index 0000000..4063ca2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_09.vhd
@@ -0,0 +1,182 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_09.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package bus_monitor_pkg is
+
+  type stats_type is record
+                       ifetch_freq, write_freq, read_freq : real;
+                     end record stats_type;
+
+  component bus_monitor is
+                          generic ( verbose, dump_stats : boolean := false );
+                        port ( mem_req, ifetch, write : in bit;
+                               bus_stats : out stats_type );
+  end component bus_monitor;
+
+end package bus_monitor_pkg;
+
+
+use work.bus_monitor_pkg.all;
+
+entity bus_monitor is
+  generic ( verbose, dump_stats : boolean := false );
+  port ( mem_req, ifetch, write : in bit;
+         bus_stats : out stats_type );
+end entity bus_monitor;
+
+
+architecture general_purpose of bus_monitor is
+begin
+
+  access_monitor : process is
+
+                             variable access_count, ifetch_count,
+                           write_count, read_count : natural := 0;
+                           use std.textio;
+                           variable L : textio.line;
+
+  begin
+    wait until mem_req = '1';
+    if ifetch = '1' then
+      ifetch_count := ifetch_count + 1;
+      if verbose then
+        textio.write(L, string'("Ifetch"));
+        textio.writeline(textio.output, L);
+      end if;
+    elsif write = '1' then
+      write_count := write_count + 1;
+      if verbose then
+        textio.write(L, string'("Write"));
+        textio.writeline(textio.output, L);
+      end if;
+    else
+      read_count := read_count + 1;
+      if verbose then
+        textio.write(L, string'("Read"));
+        textio.writeline(textio.output, L);
+      end if;
+    end if;
+    access_count := access_count + 1;
+    bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count);
+    bus_stats.write_freq <= real(write_count) / real(access_count);
+    bus_stats.read_freq <= real(read_count) / real(access_count);
+    if dump_stats and access_count mod 5 = 0 then
+      textio.write(L, string'("Ifetch frequency = "));
+      textio.write(L, real(ifetch_count) / real(access_count));
+      textio.writeline(textio.output, L);
+      textio.write(L, string'("Write frequency = "));
+      textio.write(L, real(write_count) / real(access_count));
+      textio.writeline(textio.output, L);
+      textio.write(L, string'("Read frequency = "));
+      textio.write(L, real(read_count) / real(access_count));
+      textio.writeline(textio.output, L);
+    end if;
+  end process access_monitor;
+
+end architecture general_purpose;
+
+
+
+-- code from book
+
+architecture block_level of computer_system is
+
+  -- . . .    -- type and component declarations for cpu and memory, etc.
+
+  signal clock : bit;    -- the system clock
+  signal mem_req : bit;  -- cpu access request to memory
+  signal ifetch : bit;   -- indicates access is to fetch an instruction
+  signal write : bit;    -- indicates access is a write
+  -- . . .                  -- other signal declarations
+
+begin
+
+  -- . . .    -- component instances for cpu and memory, etc.
+
+  instrumentation : if instrumented generate
+
+    use work.bus_monitor_pkg;
+    signal bus_stats : bus_monitor_pkg.stats_type;
+
+  begin
+
+    cpu_bus_monitor : component bus_monitor_pkg.bus_monitor
+      port map ( mem_req, ifetch, write, bus_stats );
+
+  end generate instrumentation;
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    ifetch <= '1';  write <= '0';
+    mem_req <= '1', '0' after 10 ns;
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '1';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture block_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_10.vhd
new file mode 100644
index 0000000..c611f1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_10.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_10.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration architectural of computer_system is
+
+  for block_level
+
+    -- . . .    -- component configurations for cpu and memory, etc
+
+    for instrumentation
+
+      for cpu_bus_monitor : bus_monitor_pkg.bus_monitor
+                                             use entity work.bus_monitor(general_purpose)
+                                             generic map ( verbose => true, dump_stats => true );
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration architectural;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_11.vhd
new file mode 100644
index 0000000..f86d520
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_11.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+library cell_lib;
+
+configuration identical_cells of register_tristate is
+
+  for cell_level
+
+    for cell_array
+
+      for cell_storage : D_flipflop
+        use entity cell_lib.D_flipflop(synthesized);
+      end for;
+
+      for cell_buffer : tristate_buffer
+        use entity cell_lib.tristate_buffer(synthesized);
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration identical_cells;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_12.vhd
new file mode 100644
index 0000000..3a523bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_12.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity DRAM_4M_by_4 is
+                 port ( a :  in std_logic_vector(0 to 10);
+                        d :  inout std_logic_vector(0 to 3);
+                        cs, we, ras, cas : in std_logic );
+               end entity DRAM_4M_by_4;
+
+
+               architecture chip_function of DRAM_4M_by_4 is
+               begin
+                 d <= (others => 'Z');
+               end architecture chip_function;
+
+
+-- code from book
+
+               library chip_lib;  use chip_lib.all;
+
+               configuration down_to_chips of memory_board is
+
+                 for chip_level
+
+                   for bank_array
+
+                   for nibble_array
+
+                   for a_DRAM : DRAM
+                   use entity DRAM_4M_by_4(chip_function);
+               end for;
+
+               end for;
+
+               end for;
+
+               -- . . .    -- configurations of other component instances
+
+               end for;
+
+               end configuration down_to_chips;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_13.vhd
new file mode 100644
index 0000000..bdfa833
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_13.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_14_fg_14_13.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity ms_flipflop is
+                 port ( phi1, phi2 : in std_logic;
+                        d : in std_logic;
+                        q : out std_logic );
+               end entity ms_flipflop;
+
+
+               architecture normal_drive of ms_flipflop is
+                 signal master_d : std_logic;
+               begin
+                 master_d <= d when phi1 = '1';
+                 q <= master_d when phi2 = '1';
+               end architecture normal_drive;
+
+
+               architecture high_drive of ms_flipflop is
+                 signal master_d : std_logic;
+               begin
+                 master_d <= d when phi1 = '1';
+                 q <= master_d when phi2 = '1';
+               end architecture high_drive;
+
+
+
+-- code from book
+
+               library cell_lib;
+
+               configuration last_high_drive of shift_reg is
+
+                 for cell_level
+
+                   -- workaround for MTI bug mt026
+                   -- for reg_array ( 0 to parallel_data'length - 2 )
+                   for reg_array ( 0 to 2 )
+                   -- end workaround
+
+                   for first_cell
+                   for cell : master_slave_flipflop
+                   use entity cell_lib.ms_flipflop(normal_drive);
+               end for;
+               end for;
+
+               for other_cell
+                 for cell : master_slave_flipflop
+                 use entity cell_lib.ms_flipflop(normal_drive);
+               end for;
+               end for;
+
+               end for;
+
+               -- workaround for MTI bug mt026
+               -- for reg_array ( parallel_data'length - 1 )
+               for reg_array ( 3 )
+                 -- end workaround
+
+                 for other_cell
+                 for cell : master_slave_flipflop
+                 use entity cell_lib.ms_flipflop(high_drive);
+               end for;
+               end for;
+
+               end for;
+
+               end for;
+
+               end configuration last_high_drive;
+
+-- end code from book
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_14_13 is
+               end entity fg_14_13;
+
+
+               architecture test of fg_14_13 is
+
+                 signal phi1, phi2, serial_data_in : std_logic := '0';
+                 signal parallel_data : std_logic_vector(3 downto 0);
+
+               begin
+
+                 dut : configuration work.last_high_drive
+                   port map ( phi1 => phi1, phi2 => phi2,
+                              serial_data_in => serial_data_in,
+                              parallel_data => parallel_data );
+
+                 clock_gen : process is
+                 begin
+                   phi1 <= '1', '0' after 4 ns;
+                   phi2 <= '1' after 5 ns, '0' after 9 ns;
+                   wait for 10 ns;
+                 end process clock_gen;
+
+                 stimulus : process is
+                 begin
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '1';  wait until phi2 = '1';
+                   serial_data_in <= '0';
+
+                   wait;
+                 end process stimulus;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu-b.vhd
new file mode 100644
index 0000000..a4e0a19
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu-b.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_alu-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+architecture behavior of alu is
+
+begin
+
+  alu_op: process ( s1, s2, func ) is
+
+                                     variable bv_s1, bv_s2 : dlx_bv_word;
+                                   variable temp_result : dlx_bv_word;
+                                   variable temp_overflow : boolean;
+
+                                   type boolean_to_X01_table is array (boolean) of X01;
+                                   constant boolean_to_X01 : boolean_to_X01_table := ( '0', '1' );
+
+  begin
+    bv_s1 := To_bitvector(s1);
+    bv_s2 := To_bitvector(s2);
+    temp_overflow := false;
+    case func is
+      when alu_pass_s1 =>
+        temp_result := bv_s1;
+      when alu_pass_s2 =>
+        temp_result := bv_s2;
+      when alu_and =>
+        temp_result := bv_s1 and bv_s2;
+      when alu_or =>
+        temp_result := bv_s1 or bv_s2;
+      when alu_xor =>
+        temp_result := bv_s1 xor bv_s2;
+      when alu_sll =>
+        temp_result := bv_s1 sll bv_to_natural(bv_s2(27 to 31));
+      when alu_srl =>
+        temp_result := bv_s1 srl bv_to_natural(bv_s2(27 to 31));
+      when alu_sra =>
+        temp_result := bv_s1 sra bv_to_natural(bv_s2(27 to 31));
+      when alu_add =>
+        bv_add(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_addu =>
+        bv_addu(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_sub =>
+        bv_sub(bv_s1, bv_s2, temp_result, temp_overflow);
+      when alu_subu =>
+        bv_subu(bv_s1, bv_s2, temp_result, temp_overflow);
+      when others =>
+	report "illegal function code" severity error;
+	temp_result := X"0000_0000";
+    end case;
+    result <= To_X01(temp_result) after Tpd;
+    zero <= boolean_to_X01(temp_result = X"0000_0000") after Tpd;
+    negative <= To_X01(temp_result(0)) after Tpd;
+    overflow <= boolean_to_X01(temp_overflow) after Tpd;
+  end process alu_op;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu.vhd
new file mode 100644
index 0000000..f3cc532
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alu.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_alu.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all,
+  work.alu_types.all;
+
+entity alu is
+  generic ( Tpd : delay_length );
+  port ( s1 : in dlx_word;
+         s2 : in dlx_word;
+         result : out dlx_word;
+         func : in alu_func;
+         zero, negative, overflow : out std_logic );
+end entity alu;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alut.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alut.vhd
new file mode 100644
index 0000000..f776434
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_alut.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_alut.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package alu_types is
+
+  subtype alu_func is std_logic_vector(3 downto 0);
+
+  constant alu_add :     alu_func := "0000";
+  constant alu_addu :    alu_func := "0001";
+  constant alu_sub :     alu_func := "0010";
+  constant alu_subu :    alu_func := "0011";
+  constant alu_and :     alu_func := "0100";
+  constant alu_or :      alu_func := "0101";
+  constant alu_xor :     alu_func := "0110";
+  constant alu_sll :     alu_func := "1000";
+  constant alu_srl :     alu_func := "1001";
+  constant alu_sra :     alu_func := "1010";
+  constant alu_pass_s1 : alu_func := "1100";
+  constant alu_pass_s2 : alu_func := "1101";
+
+end package alu_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg-b.vhd
new file mode 100644
index 0000000..306c48d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg-b.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_cg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of clock_gen is
+
+  constant clock_period : delay_length := 2 * (Tpw + Tps);
+
+begin
+
+  reset_driver : 
+    reset <= '1', '0' after 2.5 * clock_period + Tps;
+
+  clock_driver : process is
+  begin
+    phi1 <= '0';
+    phi2 <= '0';
+    wait for clock_period / 2;
+    loop
+      phi1 <= '1', '0' after Tpw;
+      phi2 <= '1' after clock_period / 2,
+              '0' after clock_period / 2 + Tpw;
+      wait for clock_period;
+    end loop;
+  end process clock_driver;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg.vhd
new file mode 100644
index 0000000..d04b7c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_cg.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_cg.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity clock_gen is
+
+                 generic ( Tpw : delay_length;
+                           Tps : delay_length );
+
+                 port ( phi1, phi2 : out std_logic;
+                        reset : out std_logic );
+
+               end entity clock_gen;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_crtl.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_crtl.vhd
new file mode 100644
index 0000000..3bb331a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_crtl.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_crtl.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all,
+  work.alu_types.all,
+  work.reg_file_types.all;
+
+entity controller is
+  generic ( Tpd_clk_ctrl, Tpd_clk_const : delay_length;
+            debug : dlx_debug_control := none );
+  port ( phi1, phi2 : in std_logic;
+         reset : in std_logic;
+         halt : out std_logic;
+         width : out dlx_mem_width;
+         write_enable : out std_logic;
+         mem_enable : out std_logic;
+         ifetch : out std_logic;
+         ready : in std_logic;
+         alu_in_latch_en : out std_logic;
+         alu_function : out alu_func;
+         alu_zero, alu_negative, alu_overflow : in std_logic;
+         reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
+         reg_write : out std_logic;
+         c_latch_en : out std_logic;
+         a_latch_en, a_out_en : out std_logic;
+         b_latch_en, b_out_en : out std_logic;
+         temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
+         iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
+         pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
+         mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
+         mem_addr_mux_sel : out std_logic;
+         mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
+         mdr_mux_sel : out std_logic;
+         ir_latch_en : out std_logic;
+         ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
+         ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
+         ir_immed1_en, ir_immed2_en : out std_logic;
+         current_instruction : in dlx_word;
+         mem_addr : std_logic_vector(1 downto 0);
+         const1, const2 : out dlx_word );
+end entity controller;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ctrl-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ctrl-b.vhd
new file mode 100644
index 0000000..7f773c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ctrl-b.vhd
@@ -0,0 +1,913 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_ctrl-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+library work;
+use work.dlx_instr.all;
+
+architecture behavior of controller is
+
+begin -- behavior
+
+  sequencer : process is
+
+                        variable current_instruction_bv : dlx_bv_word;
+
+                      alias IR_opcode : dlx_opcode is current_instruction_bv(0 to 5);
+                      alias IR_sp_func : dlx_sp_func is current_instruction_bv(26 to 31);
+                      alias IR_fp_func : dlx_fp_func is current_instruction_bv(27 to 31);
+
+                      alias IR_rs1 : reg_file_addr is current_instruction(6 to 10);
+                      alias IR_rs2 : reg_file_addr is current_instruction(11 to 15);
+                      alias IR_Itype_rd : reg_file_addr is current_instruction(11 to 15);
+                      alias IR_Rtype_rd : reg_file_addr is current_instruction(16 to 20);
+
+                      variable result_of_set_is_1, branch_taken : boolean;
+
+                      variable disassembled_instr : string(1 to 40);
+                      variable disassembled_instr_len : positive;
+
+                      variable instr_count : natural := 0;
+
+                      procedure bus_instruction_fetch is
+                      begin
+                        -- use PC as address
+                        mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
+                        -- set up memory control signals
+                        width <= dlx_mem_width_word after Tpd_clk_ctrl;
+                        ifetch <= '1' after Tpd_clk_ctrl;
+                        write_enable <= '0' after Tpd_clk_ctrl;
+                        mem_enable <= '1' after Tpd_clk_ctrl;
+                        -- wait until phi2, then enable IR input
+                        wait until rising_edge(phi2);
+                        ir_latch_en <= '1' after Tpd_clk_ctrl;
+                        -- wait until memory is ready at end of phi2
+                        loop 
+                          wait until falling_edge(phi2);
+                          if To_bit(reset) = '1' then
+                            return;
+                          end if;
+                          exit when To_bit(ready) = '1';
+                        end loop;
+                        -- disable IR input and memory control signals
+                        ir_latch_en <= '0' after Tpd_clk_ctrl;
+                        mem_enable <= '0' after Tpd_clk_ctrl;
+                      end procedure bus_instruction_fetch;
+
+                      procedure bus_data_read ( read_width : in dlx_mem_width ) is
+                      begin
+                        -- use MAR as address
+                        mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
+                        -- set up memory control signals
+                        width <= read_width after Tpd_clk_ctrl;
+                        ifetch <= '0' after Tpd_clk_ctrl;
+                        write_enable <= '0' after Tpd_clk_ctrl;
+                        mem_enable <= '1' after Tpd_clk_ctrl;
+                        -- wait until phi2, then enable MDR input
+                        wait until rising_edge(phi2);
+                        mdr_mux_sel <= '1' after Tpd_clk_ctrl;
+                        mdr_latch_en <= '1' after Tpd_clk_ctrl;
+                        -- wait until memory is ready at end of phi2
+                        loop 
+                          wait until falling_edge(phi2);
+                          if To_bit(reset) = '1' then
+                            return;
+                          end if;
+                          exit when To_bit(ready) = '1';
+                        end loop;
+                        -- disable MDR input and memory control signals
+                        mdr_latch_en <= '0' after Tpd_clk_ctrl;
+                        mem_enable <= '0' after Tpd_clk_ctrl;
+                      end procedure bus_data_read;
+
+                      procedure bus_data_write ( write_width : in dlx_mem_width ) is
+                      begin
+                        -- use MAR as address
+                        mem_addr_mux_sel <= '1' after Tpd_clk_ctrl;
+                        -- enable MDR output
+                        mdr_out_en3 <= '1' after Tpd_clk_ctrl;
+                        -- set up memory control signals
+                        width <= write_width after Tpd_clk_ctrl;
+                        ifetch <= '0' after Tpd_clk_ctrl;
+                        write_enable <= '1' after Tpd_clk_ctrl;
+                        mem_enable <= '1' after Tpd_clk_ctrl;
+                        -- wait until memory is ready at end of phi2
+                        loop 
+                          wait until falling_edge(phi2);
+                          if To_bit(reset) = '1' then
+                            return;
+                          end if;
+                          exit when To_bit(ready) = '1';
+                        end loop;
+                        -- disable MDR output and memory control signals
+                        write_enable <= '0' after Tpd_clk_ctrl;
+                        mem_enable <= '0' after Tpd_clk_ctrl;
+                        mdr_out_en3 <= '0' after Tpd_clk_ctrl;
+                      end procedure bus_data_write;
+
+                      procedure do_set_result is
+                      begin
+                        wait until rising_edge(phi1);
+                        if result_of_set_is_1 then
+                          const2 <= X"0000_0001" after Tpd_clk_const;
+                        else
+                          const2 <= X"0000_0000" after Tpd_clk_const;
+                        end if;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        const2 <= disabled_dlx_word after Tpd_clk_const;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_set_result;    
+
+                      procedure do_EX_set_unsigned ( immed : boolean ) is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        if immed then
+                          ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+                          ir_immed2_unsigned <= '1' after Tpd_clk_ctrl;
+                          ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        else
+                          b_out_en <= '1' after Tpd_clk_ctrl;
+                        end if;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_subu after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+                        if immed then
+                          ir_immed2_en <= '0' after Tpd_clk_ctrl;
+                        else
+                          b_out_en <= '0' after Tpd_clk_ctrl;
+                        end if;
+
+                        wait until falling_edge(phi2);
+                        if immed then
+                          case IR_opcode is
+                            when op_sequi => 
+                              result_of_set_is_1 := To_bit(alu_zero) = '1';
+                            when op_sneui =>
+                              result_of_set_is_1 := To_bit(alu_zero) /= '1';
+                            when op_sltui =>
+                              result_of_set_is_1 := To_bit(alu_overflow) = '1';
+                            when op_sgtui => 
+                              result_of_set_is_1 := To_bit(alu_overflow) /= '1' and To_bit(alu_zero) /= '1';
+                            when op_sleui => 
+                              result_of_set_is_1 := To_bit(alu_overflow) = '1' or To_bit(alu_zero) = '1';
+                            when op_sgeui => 
+                              result_of_set_is_1 := To_bit(alu_overflow) /= '1';
+                            when others =>
+                              null;
+                          end case;
+                        else
+                          case IR_sp_func is
+                            when sp_func_sequ => 
+                              result_of_set_is_1 := To_bit(alu_zero) = '1';
+                            when sp_func_sneu =>
+                              result_of_set_is_1 := To_bit(alu_zero) /= '1';
+                            when sp_func_sltu =>
+                              result_of_set_is_1 := To_bit(alu_overflow) = '1';
+                            when sp_func_sgtu =>
+                              result_of_set_is_1 := To_bit(alu_overflow) /= '1' and To_bit(alu_zero) /= '1';
+                            when sp_func_sleu => 
+                              result_of_set_is_1 := To_bit(alu_overflow) = '1' or To_bit(alu_zero) = '1';
+                            when sp_func_sgeu => 
+                              result_of_set_is_1 := To_bit(alu_overflow) /= '1';
+                            when others =>
+                              null;
+                          end case;
+                        end if;
+
+                        do_set_result;
+                      end procedure do_EX_set_unsigned;
+
+                      procedure do_EX_set_signed ( immed : boolean ) is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        if immed then
+                          ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+                          ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+                          ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        else
+                          b_out_en <= '1' after Tpd_clk_ctrl;
+                        end if;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_sub after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+                        if immed then
+                          ir_immed2_en <= '0' after Tpd_clk_ctrl;
+                        else
+                          b_out_en <= '0' after Tpd_clk_ctrl;
+                        end if;
+
+                        wait until falling_edge(phi2);
+                        if immed then
+                          case IR_opcode is
+                            when op_seqi => 
+                              result_of_set_is_1 := To_bit(alu_zero) = '1';
+                            when op_snei =>
+                              result_of_set_is_1 := To_bit(alu_zero) /= '1';
+                            when op_slti =>
+                              result_of_set_is_1 := To_bit(alu_negative) = '1';
+                            when op_sgti => 
+                              result_of_set_is_1 := To_bit(alu_negative) /= '1' and To_bit(alu_zero) /= '1';
+                            when op_slei => 
+                              result_of_set_is_1 := To_bit(alu_negative) = '1' or To_bit(alu_zero) = '1';
+                            when op_sgei => 
+                              result_of_set_is_1 := To_bit(alu_negative) /= '1';
+                            when others =>
+                              null;
+                          end case;
+                        else
+                          case IR_sp_func is
+                            when sp_func_seq => 
+                              result_of_set_is_1 := To_bit(alu_zero) = '1';
+                            when sp_func_sne =>
+                              result_of_set_is_1 := To_bit(alu_zero) /= '1';
+                            when sp_func_slt =>
+                              result_of_set_is_1 := To_bit(alu_negative) = '1';
+                            when sp_func_sgt => 
+                              result_of_set_is_1 := To_bit(alu_negative) /= '1' and To_bit(alu_zero) /= '1';
+                            when sp_func_sle => 
+                              result_of_set_is_1 := To_bit(alu_negative) = '1' or To_bit(alu_zero) = '1';
+                            when sp_func_sge => 
+                              result_of_set_is_1 := To_bit(alu_negative) /= '1';
+                            when others =>
+                              null;
+                          end case;
+                        end if;
+
+                        do_set_result;
+                      end procedure do_EX_set_signed;
+
+                      procedure do_EX_arith_logic is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        b_out_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        case IR_sp_func is
+                          when sp_func_add =>
+                            alu_function <= alu_add after Tpd_clk_ctrl;
+                          when sp_func_addu =>
+                            alu_function <= alu_addu after Tpd_clk_ctrl;
+                          when sp_func_sub =>
+                            alu_function <= alu_sub after Tpd_clk_ctrl;
+                          when sp_func_subu =>
+                            alu_function <= alu_subu after Tpd_clk_ctrl;
+                          when sp_func_and =>
+                            alu_function <= alu_and after Tpd_clk_ctrl;
+                          when sp_func_or =>
+                            alu_function <= alu_or after Tpd_clk_ctrl;
+                          when sp_func_xor =>
+                            alu_function <= alu_xor after Tpd_clk_ctrl;
+                          when sp_func_sll =>
+                            alu_function <= alu_sll after Tpd_clk_ctrl;
+                          when sp_func_srl =>
+                            alu_function <= alu_srl after Tpd_clk_ctrl;
+                          when sp_func_sra =>
+                            alu_function <= alu_sra after Tpd_clk_ctrl;
+                          when others =>
+                            null;
+                        end case;                  --  IR_sp_func
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+                        b_out_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_EX_arith_logic;
+
+                      procedure do_EX_arith_logic_immed is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+                        if IR_opcode = op_addi or IR_opcode = op_subi then
+                          ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+                        else
+                          ir_immed2_unsigned <= '1' after Tpd_clk_ctrl;
+                        end if;
+                        ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        case IR_opcode is
+                          when op_addi =>
+                            alu_function <= alu_add after Tpd_clk_ctrl;
+                          when op_subi =>
+                            alu_function <= alu_sub after Tpd_clk_ctrl;
+                          when op_addui =>
+                            alu_function <= alu_addu after Tpd_clk_ctrl;
+                          when op_subui =>
+                            alu_function <= alu_subu after Tpd_clk_ctrl;
+                          when op_andi =>
+                            alu_function <= alu_and after Tpd_clk_ctrl;
+                          when op_ori =>
+                            alu_function <= alu_or after Tpd_clk_ctrl;
+                          when op_xori =>
+                            alu_function <= alu_xor after Tpd_clk_ctrl;
+                          when op_slli =>
+                            alu_function <= alu_sll after Tpd_clk_ctrl;
+                          when op_srli =>
+                            alu_function <= alu_srl after Tpd_clk_ctrl;
+                          when op_srai =>
+                            alu_function <= alu_sra after Tpd_clk_ctrl;
+                          when others =>
+                            null;
+                        end case;                      --  IR_opcode
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_EX_arith_logic_immed;
+
+                      procedure do_EX_link is
+                      begin
+                        wait until rising_edge(phi1);
+                        pc_out_en1 <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        pc_out_en1 <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_EX_link;
+
+                      procedure do_EX_lhi is
+                      begin
+                        wait until rising_edge(phi1);
+                        ir_immed1_size_26 <= '0' after Tpd_clk_ctrl;
+                        ir_immed1_unsigned <= '1' after Tpd_clk_ctrl;
+                        ir_immed1_en <= '1' after Tpd_clk_ctrl;
+                        const2 <= X"0000_0010" after Tpd_clk_const;         -- shift by 16 bits
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_sll after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        ir_immed1_en <= '0' after Tpd_clk_ctrl;
+                        const2 <= disabled_dlx_word after Tpd_clk_const;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_EX_lhi;    
+
+                      procedure do_EX_branch is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        if IR_opcode = op_beqz then
+                          branch_taken := To_bit(alu_zero) = '1';
+                        else
+                          branch_taken := To_bit(alu_zero) /= '1';
+                        end if;
+                      end procedure do_EX_branch;
+
+                      procedure do_EX_load_store is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_add after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        mar_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        mar_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_EX_load_store;
+
+                      procedure do_MEM_jump is
+                      begin
+                        wait until rising_edge(phi1);
+                        pc_out_en1 <= '1' after Tpd_clk_ctrl;
+                        ir_immed2_size_26 <= '1' after Tpd_clk_ctrl;
+                        ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_add after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        pc_out_en1 <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        pc_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        pc_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_MEM_jump;
+
+                      procedure do_MEM_jump_reg is
+                      begin
+                        wait until rising_edge(phi1);
+                        a_out_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_pass_s1 after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        a_out_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        pc_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        pc_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_MEM_jump_reg;
+
+                      procedure do_MEM_branch is
+                      begin
+                        wait until rising_edge(phi1);
+                        pc_out_en1 <= '1' after Tpd_clk_ctrl;
+                        ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '1' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_add after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+                        pc_out_en1 <= '0' after Tpd_clk_ctrl;
+                        ir_immed2_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        pc_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        pc_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_MEM_branch;
+
+                      procedure do_MEM_load is
+                        subtype ls_2_addr_bits is bit_vector(1 downto 0);
+                      begin
+                        wait until rising_edge(phi1);
+                        if IR_opcode = op_lb or IR_opcode = op_lbu then
+                          bus_data_read(dlx_mem_width_byte);
+                        elsif IR_opcode = op_lh or IR_opcode = op_lhu then
+                          bus_data_read(dlx_mem_width_halfword);
+                        else
+                          bus_data_read(dlx_mem_width_word);
+                        end if;
+                        if To_bit(reset) = '1' then
+                          return;
+                        end if;
+
+                        if ( (IR_opcode = op_lb or IR_opcode = op_lbu) and To_bitvector(mem_addr) /= "00" )
+                          or ( (IR_opcode = op_lh or IR_opcode = op_lhu) and To_bit(mem_addr(1)) /= '0' ) then
+                          -- first step of extension: left-justify byte or halfword -> mdr
+                          wait until rising_edge(phi1);
+                          mdr_out_en1 <= '1' after Tpd_clk_ctrl;
+                          if IR_opcode = op_lb or IR_opcode = op_lbu then
+                            case ls_2_addr_bits'(To_bitvector(mem_addr)) is
+                              when "00" => 
+                                null;
+                              when "01" => 
+                                const2 <= X"0000_0008" after Tpd_clk_const;
+                              when "10" => 
+                                const2 <= X"0000_0010" after Tpd_clk_const;
+                              when "11" => 
+                                const2 <= X"0000_0018" after Tpd_clk_const;
+                            end case;
+                          else
+                            const2 <= X"0000_0010" after Tpd_clk_const;
+                          end if;
+                          alu_function <= alu_sll after Tpd_clk_ctrl;
+                          alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+
+                          wait until falling_edge(phi1);
+                          mdr_out_en1 <= '0' after Tpd_clk_ctrl;
+                          const2 <= disabled_dlx_word after Tpd_clk_const;
+                          alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+
+                          wait until rising_edge(phi2);
+                          mdr_mux_sel <= '0' after Tpd_clk_ctrl;
+                          mdr_latch_en <= '1' after Tpd_clk_ctrl;
+
+                          wait until falling_edge(phi2);
+                          mdr_latch_en <= '0' after Tpd_clk_ctrl;
+                        end if;
+
+                        wait until rising_edge(phi1);
+                        mdr_out_en1 <= '1' after Tpd_clk_ctrl;
+                        if IR_opcode = op_lb or IR_opcode = op_lbu then
+                          const2 <= X"0000_0018" after Tpd_clk_const;
+                        elsif IR_opcode = op_lh or IR_opcode = op_lhu then
+                          const2 <= X"0000_0010" after Tpd_clk_const;
+                        else
+                          const2 <= X"0000_0000" after Tpd_clk_const;
+                        end if;
+                        if IR_opcode = op_lbu or IR_opcode = op_lhu then
+                          alu_function <= alu_srl after Tpd_clk_ctrl;
+                        else
+                          alu_function <= alu_sra after Tpd_clk_ctrl;
+                        end if;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        mdr_out_en1 <= '0' after Tpd_clk_ctrl;
+                        const2 <= disabled_dlx_word after Tpd_clk_const;
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        c_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        c_latch_en <= '0' after Tpd_clk_ctrl;
+                      end procedure do_MEM_load;    
+
+                      procedure do_MEM_store is
+                        subtype ls_2_addr_bits is bit_vector(1 downto 0);
+                      begin
+                        wait until rising_edge(phi1);
+                        b_out_en <= '1' after Tpd_clk_ctrl;
+                        alu_function <= alu_pass_s2 after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi1);
+                        b_out_en <= '0' after Tpd_clk_ctrl;
+                        alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+
+                        wait until rising_edge(phi2);
+                        mdr_mux_sel <= '0' after Tpd_clk_ctrl;
+                        mdr_latch_en <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        mdr_latch_en <= '0' after Tpd_clk_ctrl;
+
+                        if ( IR_opcode = op_sb and To_bitvector(mem_addr) /= "11" )
+                          or ( IR_opcode = op_sh and To_bit(mem_addr(1)) /= '1' ) then
+                          -- align byte or halfword -> mdr
+                          wait until rising_edge(phi1);
+                          mdr_out_en1 <= '1' after Tpd_clk_ctrl;
+                          if IR_opcode = op_sb then
+                            case ls_2_addr_bits'(To_bitvector(mem_addr)) is
+                              when "00" => 
+                                const2 <= X"0000_0018" after Tpd_clk_const;
+                              when "01" => 
+                                const2 <= X"0000_0010" after Tpd_clk_const;
+                              when "10" => 
+                                const2 <= X"0000_0008" after Tpd_clk_const;
+                              when "11" => 
+                                null;
+                            end case;
+                          else
+                            const2 <= X"0000_0010" after Tpd_clk_const;
+                          end if;
+                          alu_function <= alu_sll after Tpd_clk_ctrl;
+                          alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+
+                          wait until falling_edge(phi1);
+                          mdr_out_en1 <= '0' after Tpd_clk_ctrl;
+                          const2 <= disabled_dlx_word after Tpd_clk_const;
+                          alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+
+                          wait until rising_edge(phi2);
+                          mdr_mux_sel <= '0' after Tpd_clk_ctrl;
+                          mdr_latch_en <= '1' after Tpd_clk_ctrl;
+
+                          wait until falling_edge(phi2);
+                          mdr_latch_en <= '0' after Tpd_clk_ctrl;
+                        end if;
+
+                        wait until rising_edge(phi1);
+                        if IR_opcode = op_sb then
+                          bus_data_write(dlx_mem_width_byte);
+                        elsif IR_opcode = op_sh then
+                          bus_data_write(dlx_mem_width_halfword);
+                        else
+                          bus_data_write(dlx_mem_width_word);
+                        end if;
+                      end procedure do_MEM_store;
+
+                      procedure do_WB ( Rd : reg_file_addr ) is
+                      begin
+                        wait until rising_edge(phi1);
+                        reg_dest_addr <= Rd after Tpd_clk_ctrl;
+                        reg_write <= '1' after Tpd_clk_ctrl;
+
+                        wait until falling_edge(phi2);
+                        reg_write <= '0' after Tpd_clk_ctrl;
+                      end procedure do_WB;
+
+                      procedure execute_op_special is
+                      begin
+                        case IR_sp_func is
+                          when sp_func_nop =>
+                            null;
+                          when sp_func_add | sp_func_addu | sp_func_sub | sp_func_subu
+                            | sp_func_sll | sp_func_srl | sp_func_sra
+                            | sp_func_and | sp_func_or | sp_func_xor =>
+                            do_EX_arith_logic;
+                            do_WB(IR_Rtype_rd);
+                          when sp_func_sequ | sp_func_sneu | sp_func_sltu
+                            | sp_func_sgtu | sp_func_sleu | sp_func_sgeu => 
+                            do_EX_set_unsigned(immed => false);
+                            do_WB(IR_Rtype_rd);
+                          when sp_func_seq | sp_func_sne | sp_func_slt
+                            | sp_func_sgt | sp_func_sle | sp_func_sge => 
+                            do_EX_set_signed(immed => false);
+                            do_WB(IR_Rtype_rd);
+                          when sp_func_movi2s | sp_func_movs2i
+                            | sp_func_movf | sp_func_movd
+                            | sp_func_movfp2i | sp_func_movi2fp  => 
+                            report sp_func_names(bv_to_natural(IR_sp_func))
+                              & " instruction not implemented" severity warning;
+                          when others =>
+                            report "undefined special instruction function" severity error;
+                        end case;  
+                      end procedure execute_op_special;
+
+                      procedure execute_op_fparith is
+                      begin
+                        case IR_fp_func is
+                          when fp_func_mult | fp_func_multu | fp_func_div | fp_func_divu
+                            | fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf
+                            | fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd
+                            | fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f
+                            | fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d
+                            | fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf
+                            | fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned
+                            | fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged => 
+                            report fp_func_names(bv_to_natural(IR_fp_func))
+                              & " instruction not implemented" severity warning;
+                          when others =>
+                            report "undefined floating point instruction function" severity error;
+                        end case;
+                      end procedure execute_op_fparith;
+
+  begin -- sequencer
+
+    ----------------------------------------------------------------
+    -- initialize all control signals
+    ----------------------------------------------------------------
+    if debug > none then
+      report "initializing";
+    end if;
+
+    halt <= '0' after Tpd_clk_ctrl;
+    width <= dlx_mem_width_word after Tpd_clk_ctrl;
+    write_enable <= '0' after Tpd_clk_ctrl;
+    mem_enable <= '0' after Tpd_clk_ctrl;
+    ifetch <= '0' after Tpd_clk_ctrl;
+    alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+    alu_function <= alu_add after Tpd_clk_ctrl;
+    reg_s1_addr <= B"00000" after Tpd_clk_ctrl;
+    reg_s2_addr <= B"00000" after Tpd_clk_ctrl;
+    reg_dest_addr <= B"00000" after Tpd_clk_ctrl;
+    reg_write <= '0' after Tpd_clk_ctrl;
+    c_latch_en <= '0' after Tpd_clk_ctrl;
+    a_latch_en <= '0' after Tpd_clk_ctrl;
+    a_out_en <= '0' after Tpd_clk_ctrl;
+    b_latch_en <= '0' after Tpd_clk_ctrl;
+    b_out_en <= '0' after Tpd_clk_ctrl;
+    temp_latch_en <= '0' after Tpd_clk_ctrl;
+    temp_out_en1 <= '0' after Tpd_clk_ctrl;
+    temp_out_en2 <= '0' after Tpd_clk_ctrl;
+    iar_latch_en <= '0' after Tpd_clk_ctrl;
+    iar_out_en1 <= '0' after Tpd_clk_ctrl;
+    iar_out_en2 <= '0' after Tpd_clk_ctrl;
+    pc_latch_en <= '0' after Tpd_clk_ctrl;
+    pc_out_en1 <= '0' after Tpd_clk_ctrl;
+    pc_out_en2 <= '0' after Tpd_clk_ctrl;
+    mar_latch_en <= '0' after Tpd_clk_ctrl;
+    mar_out_en1 <= '0' after Tpd_clk_ctrl;
+    mar_out_en2 <= '0' after Tpd_clk_ctrl;
+    mem_addr_mux_sel <= '0' after Tpd_clk_ctrl;
+    mdr_latch_en <= '0' after Tpd_clk_ctrl;
+    mdr_out_en1 <= '0' after Tpd_clk_ctrl;
+    mdr_out_en2 <= '0' after Tpd_clk_ctrl;
+    mdr_out_en3 <= '0' after Tpd_clk_ctrl;
+    mdr_mux_sel <= '0' after Tpd_clk_ctrl;
+    ir_latch_en <= '0' after Tpd_clk_ctrl;
+    ir_immed1_size_26 <= '0' after Tpd_clk_ctrl;
+    ir_immed2_size_26 <= '0' after Tpd_clk_ctrl;
+    ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+    ir_immed2_unsigned <= '0' after Tpd_clk_ctrl;
+    ir_immed1_en <= '0' after Tpd_clk_ctrl;
+    ir_immed2_en <= '0' after Tpd_clk_ctrl;
+    const1 <= disabled_dlx_word after Tpd_clk_const;
+    const2 <= disabled_dlx_word after Tpd_clk_const;
+
+    instr_count := 0;
+
+    wait on phi2 until falling_edge(phi2) and To_bit(reset) = '0';
+
+    ----------------------------------------------------------------
+    -- control loop
+    ----------------------------------------------------------------
+    loop
+      exit when To_bit(reset) = '1';
+
+      ----------------------------------------------------------------
+      -- fetch next instruction (IF)
+      ----------------------------------------------------------------
+      wait until rising_edge(phi1);
+
+      instr_count := instr_count + 1;
+      if debug = msg_every_100_instructions and instr_count mod 100 = 0 then
+        report "instruction count = " & natural'image(instr_count);
+      end if;
+
+      if debug >= msg_each_instruction then
+        report "fetching instruction";
+      end if;
+
+      bus_instruction_fetch;
+      exit when To_bit(reset) = '1';
+      current_instruction_bv := To_bitvector(current_instruction);
+
+      if debug >= trace_each_instruction then
+        disassemble(current_instruction_bv, disassembled_instr, disassembled_instr_len);
+        report disassembled_instr(1 to disassembled_instr_len);
+      end if;
+
+      ----------------------------------------------------------------
+      -- instruction decode, source register read and PC increment (ID)
+      ----------------------------------------------------------------
+      wait until rising_edge(phi1);
+
+      if debug = trace_each_step then
+        report "decode, source register read and PC increment";
+      end if;
+
+      reg_s1_addr <= IR_rs1 after Tpd_clk_ctrl;
+      reg_s2_addr <= IR_rs2 after Tpd_clk_ctrl;
+      a_latch_en <= '1' after Tpd_clk_ctrl;
+      b_latch_en <= '1' after Tpd_clk_ctrl;
+
+      pc_out_en1 <= '1' after Tpd_clk_ctrl;
+      const2 <= X"0000_0004" after Tpd_clk_const;
+      alu_in_latch_en <= '1' after Tpd_clk_ctrl;
+      alu_function <= alu_addu after Tpd_clk_ctrl;
+
+      wait until falling_edge(phi1);
+      a_latch_en <= '0' after Tpd_clk_ctrl;
+      b_latch_en <= '0' after Tpd_clk_ctrl;
+      alu_in_latch_en <= '0' after Tpd_clk_ctrl;
+      pc_out_en1 <= '0' after Tpd_clk_ctrl;
+      const2 <= disabled_dlx_word after Tpd_clk_const;
+
+      wait until rising_edge(phi2);
+      pc_latch_en <= '1' after Tpd_clk_ctrl;
+
+      wait until falling_edge(phi2);
+      pc_latch_en <= '0' after Tpd_clk_ctrl;
+
+      ----------------------------------------------------------------
+      -- execute instruction, (EX, MEM, WB)
+      ----------------------------------------------------------------
+      if debug = trace_each_step then
+        report "execute";
+      end if;
+
+      case IR_opcode is
+        when op_special =>
+          execute_op_special;
+        when op_fparith => 
+          execute_op_fparith;
+        when op_j =>
+          do_MEM_jump;
+        when op_jal =>
+          do_EX_link;
+          do_MEM_jump;
+          do_WB(To_X01(natural_to_bv(link_reg, 5)));
+        when op_jr =>
+          do_MEM_jump_reg;
+        when op_jalr =>
+          do_EX_link;
+          do_MEM_jump_reg;
+          do_WB(To_X01(natural_to_bv(link_reg, 5)));
+        when op_beqz | op_bnez => 
+          do_EX_branch;
+          if branch_taken then
+            do_MEM_branch;
+          end if;
+        when op_addi | op_subi | op_addui | op_subui 
+          | op_slli | op_srli | op_srai
+          | op_andi | op_ori | op_xori =>
+          do_EX_arith_logic_immed;
+          do_WB(IR_Itype_rd);
+        when op_lhi =>
+          do_EX_lhi;
+          do_WB(IR_Itype_rd);
+        when op_sequi | op_sneui | op_sltui
+          | op_sgtui | op_sleui | op_sgeui => 
+          do_EX_set_unsigned(immed => true);
+          do_WB(IR_Itype_rd);
+        when op_seqi | op_snei | op_slti
+          | op_sgti | op_slei | op_sgei => 
+          do_EX_set_signed(immed => true);
+          do_WB(IR_Itype_rd);
+        when op_trap =>
+          report "TRAP instruction encountered, execution halted"
+            severity note;
+          wait until rising_edge(phi1);
+          halt <= '1' after Tpd_clk_ctrl;
+          wait until reset = '1';
+          exit;
+        when op_lb | op_lh | op_lw | op_lbu | op_lhu => 
+          do_EX_load_store;
+          do_MEM_load;
+          exit when reset = '1';
+          do_WB(IR_Itype_rd);
+        when op_sb | op_sh | op_sw =>
+          do_EX_load_store;
+          do_MEM_store;
+          exit when reset = '1';
+        when op_rfe | op_bfpt | op_bfpf | op_lf | op_ld | op_sf | op_sd =>
+          report opcode_names(bv_to_natural(IR_opcode))
+            & " instruction not implemented" severity warning;
+        when others =>
+          report "undefined instruction" severity error;
+      end case;
+
+      -- overflow and divide-by-zero exception handing
+      -- (not implemented)
+
+      if debug = trace_each_step then
+        report "end of execution";
+      end if;
+
+    end loop;
+    -- loop is only exited when reset active:
+    -- process interpreter starts again from beginning
+  end process sequencer;
+
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-b.vhd
new file mode 100644
index 0000000..c1bcb5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-b.vhd
@@ -0,0 +1,476 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlx-b.vhd,v 1.4 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.4 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+use bv_utilities.bv_arithmetic.all;
+
+library work;
+use work.dlx_instr.all;
+
+architecture behavior of dlx is
+begin
+
+  interpreter : process
+    is
+
+    type reg_array is array (reg_index) of dlx_bv_word;
+    variable reg : reg_array;
+    variable fp_reg : reg_array;
+
+    variable PC : dlx_bv_word;
+    constant PC_incr : dlx_bv_word := X"0000_0004";
+
+    variable IR : dlx_bv_word;
+    alias IR_opcode : dlx_opcode is IR(0 to 5);
+    alias IR_sp_func : dlx_sp_func is IR(26 to 31);
+    alias IR_fp_func : dlx_fp_func is IR(27 to 31);
+    alias IR_rs1 : dlx_reg_addr is IR(6 to 10);
+    alias IR_rs2 : dlx_reg_addr is IR(11 to 15);
+    alias IR_Itype_rd : dlx_reg_addr is IR(11 to 15);
+    alias IR_Rtype_rd : dlx_reg_addr is IR(16 to 20);
+    alias IR_immed16 : dlx_immed16 is IR(16 to 31);
+    alias IR_immed26 : dlx_immed26 is IR(6 to 31);
+
+    variable disassembled_instr : string(1 to 40);
+    variable disassembled_instr_len : positive;
+
+    variable rs1, rs2, Itype_rd, Rtype_rd : reg_index;
+
+    variable mem_addr_reg : dlx_bv_address;
+    variable mem_data_reg : dlx_bv_word;
+
+    variable overflow : boolean;
+
+    -- lookup table for result of set instructions
+    type set_result_table is array (boolean) of dlx_bv_word;
+    constant set_if : set_result_table := ( false => X"0000_0000",
+                                            true => X"0000_0001" );
+    variable instr_count : natural;
+
+
+    -- local procedures for use within the interpreter
+
+
+    procedure bus_read ( address : in dlx_bv_address;
+                         data_width : in dlx_mem_width;
+                         instr_fetch : in std_logic;
+                         data : out dlx_bv_word ) is
+
+    begin
+      wait until rising_edge(phi1);
+      if To_bit(reset) = '1' then
+        return;
+      end if;
+      a <= To_X01(address) after Tpd_clk_out;
+      width <= data_width after Tpd_clk_out;
+      ifetch <= instr_fetch after Tpd_clk_out;
+      mem_enable <= '1' after Tpd_clk_out;
+      loop 
+        wait until falling_edge(phi2);
+        if To_bit(reset) = '1' then
+          return;
+        end if;
+        exit when To_bit(ready) = '1';
+      end loop;
+      assert not Is_X(d) report "Bus read data contains unknown bits";
+      data := To_bitvector(d);
+      mem_enable <= '0' after Tpd_clk_out;
+    end procedure bus_read;
+
+
+    procedure bus_write ( address : in dlx_bv_address;
+                          data_width : in dlx_mem_width;
+                          data : in dlx_bv_word ) is
+
+    begin
+      wait until rising_edge(phi1);
+      if To_bit(reset) = '1' then
+        return;
+      end if;
+      a <= To_X01(address) after Tpd_clk_out;
+      ifetch <= '0' after Tpd_clk_out;
+      width <= data_width after Tpd_clk_out;
+      d <= To_X01Z(data) after Tpd_clk_out;
+      write_enable <= '1' after Tpd_clk_out;
+      mem_enable <= '1' after Tpd_clk_out;
+      loop 
+        wait until falling_edge(phi2);
+        if To_bit(reset) = '1' then
+          return;
+        end if;
+        exit when To_bit(ready) = '1';
+      end loop;
+      d <= disabled_dlx_word after Tpd_clk_out;
+      write_enable <= '0' after Tpd_clk_out;
+      mem_enable <= '0' after Tpd_clk_out;
+    end procedure bus_write;
+
+
+    procedure execute_op_special is
+    begin
+      case IR_sp_func is
+        when sp_func_nop =>
+          null;
+        when sp_func_add => 
+          bv_add(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
+        when sp_func_addu => 
+          bv_addu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
+        when sp_func_sub => 
+          bv_sub(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
+        when sp_func_subu => 
+          bv_subu(reg(rs1), reg(rs2), reg(Rtype_rd), overflow);
+        when sp_func_sll => 
+          reg(Rtype_rd) := reg(rs1) sll bv_to_natural(reg(rs2)(27 to 31));
+        when sp_func_srl => 
+          reg(Rtype_rd) := reg(rs1) srl bv_to_natural(reg(rs2)(27 to 31));
+        when sp_func_sra => 
+          reg(Rtype_rd) := reg(rs1) sra bv_to_natural(reg(rs2)(27 to 31));
+        when sp_func_and => 
+          reg(Rtype_rd) := reg(rs1) and reg(rs2);
+        when sp_func_or => 
+          reg(Rtype_rd) := reg(rs1) or reg(rs2);
+        when sp_func_xor => 
+          reg(Rtype_rd) := reg(rs1) xor reg(rs2);
+        when sp_func_sequ =>
+          reg(Rtype_rd) := set_if( reg(rs1) = reg(rs2) );
+        when sp_func_sneu => 
+          reg(Rtype_rd) := set_if( reg(rs1) /= reg(rs2) );
+        when sp_func_sltu => 
+          reg(Rtype_rd) := set_if( reg(rs1) < reg(rs2) );
+        when sp_func_sgtu => 
+          reg(Rtype_rd) := set_if( reg(rs1) > reg(rs2) );
+        when sp_func_sleu => 
+          reg(Rtype_rd) := set_if( reg(rs1) <= reg(rs2) );
+        when sp_func_sgeu => 
+          reg(Rtype_rd) := set_if( reg(rs1) >= reg(rs2) );
+        when sp_func_seq => 
+          reg(Rtype_rd) := set_if( reg(rs1) = reg(rs2) );
+        when sp_func_sne => 
+          reg(Rtype_rd) := set_if( reg(rs1) /= reg(rs2) );
+        when sp_func_slt => 
+          reg(Rtype_rd) := set_if( bv_lt(reg(rs1), reg(rs2)) );
+        when sp_func_sgt => 
+          reg(Rtype_rd) := set_if( bv_gt(reg(rs1), reg(rs2)) );
+        when sp_func_sle => 
+          reg(Rtype_rd) := set_if( bv_le(reg(rs1), reg(rs2)) );
+        when sp_func_sge => 
+          reg(Rtype_rd) := set_if( bv_ge(reg(rs1), reg(rs2)) );
+        when sp_func_movi2s | sp_func_movs2i
+          | sp_func_movf | sp_func_movd
+          | sp_func_movfp2i | sp_func_movi2fp => 
+          report sp_func_names(bv_to_natural(IR_sp_func))
+            & " instruction not implemented" severity warning;
+        when others =>
+          report "undefined special instruction function" severity error;
+      end case;
+    end procedure execute_op_special;
+
+
+    procedure execute_op_fparith is
+    begin
+      case IR_fp_func is
+        when fp_func_mult | fp_func_multu | fp_func_div | fp_func_divu
+          | fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf
+          | fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd
+          | fp_func_cvtf2d | fp_func_cvtf2i | fp_func_cvtd2f
+          | fp_func_cvtd2i | fp_func_cvti2f | fp_func_cvti2d
+          | fp_func_eqf | fp_func_nef | fp_func_ltf | fp_func_gtf
+          | fp_func_lef | fp_func_gef | fp_func_eqd | fp_func_ned
+          | fp_func_ltd | fp_func_gtd | fp_func_led | fp_func_ged =>
+          report fp_func_names(bv_to_natural(IR_fp_func))
+            & " instruction not implemented" severity warning;
+        when others =>
+          report "undefined floating point instruction function" severity error;
+      end case;
+    end procedure execute_op_fparith;
+
+
+    procedure execute_load ( data_width : dlx_mem_width; unsigned : boolean ) is
+
+      variable temp : dlx_bv_word;
+
+      -- type for least-significant two bits of address
+      subtype ls_2_addr_bits is bit_vector(1 downto 0);
+
+    begin
+      mem_addr_reg := reg(rs1) + bv_sext(IR_immed16, 32);
+      bus_read(mem_addr_reg, data_width, '0', mem_data_reg);
+      if To_bit(reset) = '1' then
+        return;
+      end if;
+      case data_width is
+        when dlx_mem_width_byte =>
+          case ls_2_addr_bits'(mem_addr_reg(1 downto 0)) is
+            when B"00" =>
+              temp(0 to 7) := mem_data_reg(0 to 7);
+            when B"01" =>
+              temp(0 to 7) := mem_data_reg(8 to 15);
+            when B"10" =>
+              temp(0 to 7) := mem_data_reg(16 to 23);
+            when B"11" =>
+              temp(0 to 7) := mem_data_reg(24 to 31);
+          end case;
+          if unsigned then
+            reg(Itype_rd) := bv_zext(temp(0 to 7), 32);
+          else
+            reg(Itype_rd) := bv_sext(temp(0 to 7), 32);
+          end if;
+        when dlx_mem_width_halfword =>
+          if mem_addr_reg(1) = '0' then
+            temp(0 to 15) := mem_data_reg(0 to 15);
+          else
+            temp(0 to 15) := mem_data_reg(16 to 31);
+          end if;
+          if unsigned then
+            reg(Itype_rd) := bv_zext(temp(0 to 15), 32);
+          else
+            reg(Itype_rd) := bv_sext(temp(0 to 15), 32);
+          end if;
+        when dlx_mem_width_word =>
+          reg(Itype_rd) := mem_data_reg;
+        when others =>
+          null;
+      end case;
+    end procedure execute_load;
+
+
+    procedure execute_store ( data_width : dlx_mem_width ) is
+
+      variable temp : dlx_bv_word;
+
+      -- type for least-significant two bits of address
+      subtype ls_2_addr_bits is bit_vector(1 downto 0);
+
+    begin
+      mem_addr_reg := reg(rs1) + bv_sext(IR_immed16, 32);
+      mem_data_reg := X"0000_0000";
+      case data_width is
+        when dlx_mem_width_byte =>
+          case ls_2_addr_bits'(mem_addr_reg(1 downto 0)) is
+            when B"00" =>
+              mem_data_reg(0 to 7) := reg(Itype_rd)(0 to 7);
+            when B"01" =>
+              mem_data_reg(8 to 15) := reg(Itype_rd)(0 to 7);
+            when B"10" =>
+              mem_data_reg(16 to 23) := reg(Itype_rd)(0 to 7);
+            when B"11" =>
+              mem_data_reg(24 to 31) := reg(Itype_rd)(0 to 7);
+          end case;
+        when dlx_mem_width_halfword =>
+          if mem_addr_reg(1) = '0' then
+            mem_data_reg(0 to 15) := reg(Itype_rd)(0 to 15);
+          else
+            mem_data_reg(16 to 31) := reg(Itype_rd)(0 to 15);
+          end if;
+        when dlx_mem_width_word =>
+          mem_data_reg := reg(Itype_rd);
+        when others =>
+          null;
+      end case;
+      bus_write(mem_addr_reg, data_width, mem_data_reg);
+    end procedure execute_store;
+
+
+  begin -- interpreter
+
+    -- reset the processor
+    d <= disabled_dlx_word;
+    halt <= '0';
+    write_enable <= '0';
+    mem_enable <= '0';
+    reg(0) := X"0000_0000";
+    PC := X"0000_0000";
+    instr_count := 0;
+    wait on phi2 until falling_edge(phi2) and To_bit(reset) = '0';
+
+    -- fetch-decode-execute loop
+    while To_bit(reset) /= '1' loop
+      -- fetch next instruction
+      instr_count := instr_count + 1;
+      if debug = msg_every_100_instructions and instr_count mod 100 = 0 then
+        report "instruction count = " & natural'image(instr_count);
+      end if;
+
+      if debug >= msg_each_instruction then
+        report "fetching instruction";
+      end if;
+
+      bus_read( address => PC, data_width => dlx_mem_width_word,
+                instr_fetch => '1', data => IR );
+      exit when To_bit(reset) = '1';
+
+      if debug >= trace_each_instruction then
+	disassemble(IR, disassembled_instr, disassembled_instr_len);
+        report disassembled_instr(1 to disassembled_instr_len);
+      end if;
+
+      wait until rising_edge(phi1);
+
+      -- increment the PC to point to the following instruction
+      if debug = trace_each_step then
+        report "incrementing PC";
+      end if;
+
+      PC := bv_addu(PC, PC_incr);
+
+      -- decode the instruction
+      if debug = trace_each_step then
+        report "decoding instruction";
+      end if;
+
+      rs1 := bv_to_natural(IR_rs1);
+      rs2 := bv_to_natural(IR_rs2);
+      Itype_rd := bv_to_natural(IR_Itype_rd);
+      Rtype_rd := bv_to_natural(IR_Rtype_rd);
+
+      -- execute the instruction
+      if debug = trace_each_step then
+        report "executing instruction";
+      end if;
+
+      overflow := false;
+
+      case IR_opcode is
+        when op_special =>
+          execute_op_special;
+        when op_fparith =>
+          execute_op_fparith;
+        when op_j  => 
+          PC := PC + bv_sext(IR_immed26, 32);
+        when op_jal => 
+          reg(link_reg) := PC;
+          PC := PC + bv_sext(IR_immed26, 32);
+        when op_jr => 
+          PC := reg(rs1);
+        when op_jalr => 
+          reg(link_reg) := PC;
+          PC := reg(rs1);
+        when op_beqz => 
+          if reg(rs1) = X"0000_0000" then
+            PC := PC + bv_sext(IR_immed16, 32);
+          end if;
+        when op_bnez => 
+          if reg(rs1) /= X"0000_0000" then
+            PC := PC + bv_sext(IR_immed16, 32);
+          end if;
+        when op_addi =>
+          bv_add(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
+        when op_addui => 
+          bv_addu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
+        when op_subi => 
+          bv_sub(reg(rs1), bv_sext(IR_immed16, 32), reg(Itype_rd), overflow);
+        when op_subui => 
+          bv_subu(reg(rs1), bv_zext(IR_immed16, 32), reg(Itype_rd), overflow);
+        when op_slli => 
+          reg(Itype_rd) := reg(rs1) sll bv_to_natural(IR_immed16(11 to 15));
+        when op_srli =>
+          reg(Itype_rd) := reg(rs1) srl bv_to_natural(IR_immed16(11 to 15));
+        when op_srai => 
+          reg(Itype_rd) := reg(rs1) sra bv_to_natural(IR_immed16(11 to 15));
+        when op_andi => 
+          reg(Itype_rd) := reg(rs1) and bv_zext(IR_immed16, 32);
+        when op_ori => 
+          reg(Itype_rd) := reg(rs1) or bv_zext(IR_immed16, 32);
+        when op_xori => 
+          reg(Itype_rd) := reg(rs1) xor bv_zext(IR_immed16, 32);
+        when op_lhi => 
+          reg(Itype_rd) := IR_immed16 & X"0000";
+        when op_sequi => 
+          reg(Itype_rd) := set_if( reg(rs1) = bv_zext(IR_immed16, 32) );
+        when op_sneui => 
+          reg(Itype_rd) := set_if( reg(rs1) /= bv_zext(IR_immed16, 32) );
+        when op_sltui => 
+          reg(Itype_rd) := set_if( reg(rs1) < bv_zext(IR_immed16, 32) );
+        when op_sgtui => 
+          reg(Itype_rd) := set_if( reg(rs1) > bv_zext(IR_immed16, 32) );
+        when op_sleui => 
+          reg(Itype_rd) := set_if( reg(rs1) <= bv_zext(IR_immed16, 32) );
+        when op_sgeui => 
+          reg(Itype_rd) := set_if( reg(rs1) >= bv_zext(IR_immed16, 32) );
+        when op_seqi => 
+          reg(Itype_rd) := set_if( reg(rs1) = bv_sext(IR_immed16, 32) );
+        when op_snei => 
+          reg(Itype_rd) := set_if( reg(rs1) /= bv_sext(IR_immed16, 32) );
+        when op_slti => 
+          reg(Itype_rd) := set_if( bv_lt(reg(rs1), bv_sext(IR_immed16, 32)) );
+        when op_sgti => 
+          reg(Itype_rd) := set_if( bv_gt(reg(rs1), bv_sext(IR_immed16, 32)) );
+        when op_slei => 
+          reg(Itype_rd) := set_if( bv_le(reg(rs1), bv_sext(IR_immed16, 32)) );
+        when op_sgei => 
+          reg(Itype_rd) := set_if( bv_ge(reg(rs1), bv_sext(IR_immed16, 32)) );
+        when op_trap =>
+          report "TRAP instruction encountered, execution halted" severity note;
+          halt <= '1' after Tpd_clk_out;
+          wait until To_bit(reset) = '1';
+          exit;
+        when op_lb =>
+          execute_load(data_width => dlx_mem_width_byte, unsigned => false);
+          exit when To_bit(reset) = '1';
+        when op_lh => 
+          execute_load(data_width => dlx_mem_width_halfword, unsigned => false);
+          exit when To_bit(reset) = '1';
+        when op_lw => 
+          execute_load(data_width => dlx_mem_width_word, unsigned => false);
+          exit when To_bit(reset) = '1';
+        when op_lbu => 
+          execute_load(data_width => dlx_mem_width_byte, unsigned => true);
+          exit when To_bit(reset) = '1';
+        when op_lhu => 
+          execute_load(data_width => dlx_mem_width_halfword, unsigned => true);
+          exit when To_bit(reset) = '1';
+        when op_sb => 
+          execute_store ( data_width => dlx_mem_width_byte );
+          exit when To_bit(reset) = '1';
+        when op_sh => 
+          execute_store ( data_width => dlx_mem_width_halfword );
+          exit when To_bit(reset) = '1';
+        when op_sw => 
+          execute_store ( data_width => dlx_mem_width_word );
+          exit when To_bit(reset) = '1';
+        when op_rfe | op_bfpt | op_bfpf | op_lf | op_ld | op_sf | op_sd => 
+          report opcode_names(bv_to_natural(IR_opcode))
+            & " instruction not implemented" severity warning;
+        when others =>
+          report "undefined instruction" severity error;
+      end case;
+
+      -- fix up R0 in case it was overwritten
+      reg(0) := X"0000_0000";
+
+      -- overflow and divide-by-zero exception handing
+      -- (not implemented)
+
+      if debug = trace_each_step then
+        report "end of execution";
+      end if;
+
+    end loop;
+    -- loop is only exited when reset active:
+    -- process interpreter starts again from beginning
+  end process interpreter;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-r.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-r.vhd
new file mode 100644
index 0000000..27b6ae2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx-r.vhd
@@ -0,0 +1,281 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlx-r.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+use work.alu_types.all,
+  work.reg_file_types.all;
+
+architecture rtl of dlx is
+
+  component alu is
+                  port ( s1 : in dlx_word;
+                         s2 : in dlx_word;
+                         result : out dlx_word;
+                         func : in alu_func;
+                         zero, negative, overflow : out std_logic );
+  end component alu;
+
+  component reg_file is
+                       port ( a1 : in reg_file_addr;
+                              q1 : out dlx_word;
+                              a2 : in reg_file_addr;
+                              q2 : out dlx_word;
+                              a3 : in reg_file_addr;
+                              d3 : in dlx_word;
+                              write_en : in std_logic );
+  end component reg_file;
+
+  component latch is
+                    port ( d : in dlx_word;
+                           q : out dlx_word;
+                           latch_en : in std_logic );
+  end component latch;
+
+  component ir_extender is
+                          port ( d : in dlx_word;
+                                 q : out dlx_word;
+                                 immed_size_26 : in std_logic;
+                                 immed_unsigned : in std_logic;
+                                 immed_en : in std_logic );
+  end component ir_extender;
+
+  component reg_multiple_out is
+                               generic ( num_outputs : positive );
+                             port ( d : in dlx_word;
+                                    q : out dlx_word_array(1 to num_outputs);
+                                    latch_en : in std_logic;
+                                    out_en : in std_logic_vector(1 to num_outputs) );
+  end component reg_multiple_out;
+
+  component reg_multiple_plus_one_out is
+                                        generic ( num_outputs : positive );
+                                      port ( d : in dlx_word;
+                                             q0 : out dlx_word;
+                                             q : out dlx_word_array(1 to num_outputs);
+                                             latch_en : in std_logic;
+                                             out_en : in std_logic_vector(1 to num_outputs) );
+  end component reg_multiple_plus_one_out;
+
+  component reg_multiple_plus_one_out_reset is
+                                              generic ( num_outputs : positive );
+                                            port ( d : in dlx_word;
+                                                   q0 : out dlx_word;
+                                                   q : out dlx_word_array(1 to num_outputs);
+                                                   latch_en : in std_logic;
+                                                   out_en : in std_logic_vector(1 to num_outputs);
+                                                   reset : in std_logic );
+  end component reg_multiple_plus_one_out_reset;
+
+  component mux2 is
+                   port ( i0, i1 : in dlx_word;
+                          y : out dlx_word;
+                          sel : in std_logic);
+  end component mux2;
+
+  component controller is
+                         port ( phi1, phi2 : in std_logic;
+                                reset : in std_logic;
+                                halt : out std_logic;
+                                width : out dlx_mem_width;
+                                write_enable : out std_logic;
+                                mem_enable : out std_logic;
+                                ifetch : out std_logic;
+                                ready : in std_logic;
+                                alu_in_latch_en : out std_logic;
+                                alu_function : out alu_func;
+                                alu_zero, alu_negative, alu_overflow : in std_logic;
+                                reg_s1_addr, reg_s2_addr, reg_dest_addr : out reg_file_addr;
+                                reg_write : out std_logic;
+                                c_latch_en : out std_logic;
+                                a_latch_en, a_out_en : out std_logic;
+                                b_latch_en, b_out_en : out std_logic;
+                                temp_latch_en, temp_out_en1, temp_out_en2 : out std_logic;
+                                iar_latch_en, iar_out_en1, iar_out_en2 : out std_logic;
+                                pc_latch_en, pc_out_en1, pc_out_en2 : out std_logic;
+                                mar_latch_en, mar_out_en1, mar_out_en2 : out std_logic;
+                                mem_addr_mux_sel : out std_logic;
+                                mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out std_logic;
+                                mdr_mux_sel : out std_logic;
+                                ir_latch_en : out std_logic;
+                                ir_immed1_size_26, ir_immed2_size_26 : out std_logic;
+                                ir_immed1_unsigned, ir_immed2_unsigned : out std_logic;
+                                ir_immed1_en, ir_immed2_en : out std_logic;
+                                current_instruction : in dlx_word;
+                                mem_addr : std_logic_vector(1 downto 0);
+                                const1, const2 : out dlx_word );
+  end component controller;
+
+
+  signal s1_bus, s2_bus : dlx_word;
+  signal dest_bus : dlx_word;
+  signal alu_in1, alu_in2 : dlx_word;
+  signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
+  signal mdr_in : dlx_word;
+  signal current_instruction : dlx_word;
+  signal pc_to_mem : dlx_address;
+  signal mar_to_mem : dlx_address;
+
+  signal alu_in_latch_en : std_logic;
+  signal alu_function : alu_func;
+  signal alu_zero, alu_negative, alu_overflow : std_logic;
+  signal reg_s1_addr, reg_s2_addr, reg_dest_addr : reg_file_addr;
+  signal reg_write : std_logic;
+  signal a_out_en, a_latch_en : std_logic;
+  signal b_out_en, b_latch_en : std_logic;
+  signal c_latch_en : std_logic;
+  signal temp_out_en1, temp_out_en2, temp_latch_en : std_logic;
+  signal iar_out_en1, iar_out_en2, iar_latch_en : std_logic;
+  signal pc_out_en1, pc_out_en2, pc_latch_en : std_logic;
+  signal mar_out_en1, mar_out_en2, mar_latch_en : std_logic;
+  signal mem_addr_mux_sel : std_logic;
+  signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : std_logic;
+  signal mdr_mux_sel : std_logic;
+  signal ir_latch_en : std_logic;
+  signal ir_immed1_size_26, ir_immed2_size_26 : std_logic;
+  signal ir_immed1_unsigned, ir_immed2_unsigned : std_logic;
+  signal ir_immed1_en, ir_immed2_en : std_logic;
+
+begin
+
+  alu_s1_reg : component latch
+    port map ( d => s1_bus, q => alu_in1, latch_en => alu_in_latch_en );
+
+  alu_s2_reg : component latch
+    port map ( d => s2_bus, q => alu_in2, latch_en => alu_in_latch_en );
+
+  the_alu : component alu
+    port map ( s1 => alu_in1, s2 => alu_in2, result => dest_bus,
+               func => alu_function,
+               zero => alu_zero, negative => alu_negative, overflow => alu_overflow );
+
+  the_reg_file : component reg_file
+    port map ( a1 => reg_s1_addr, q1 => reg_file_out1,
+               a2 => reg_s2_addr, q2 => reg_file_out2,
+               a3 => reg_dest_addr, d3 => reg_file_in,
+               write_en => reg_write );
+
+  c_reg : component latch
+    port map ( d => dest_bus, q => reg_file_in, latch_en => c_latch_en );
+
+  a_reg : component reg_multiple_out
+    generic map ( num_outputs => 1 )
+    port map ( d => reg_file_out1, q(1) => s1_bus,
+               latch_en => a_latch_en, out_en(1) => a_out_en );
+
+  b_reg : component reg_multiple_out
+    generic map ( num_outputs => 1 )
+    port map ( d => reg_file_out2, q(1) => s2_bus,
+               latch_en => b_latch_en, out_en(1) => b_out_en );
+
+  temp_reg : component reg_multiple_out
+    generic map ( num_outputs => 2 )
+    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
+               latch_en => temp_latch_en,
+               out_en(1) => temp_out_en1, out_en(2) => temp_out_en2 );
+
+  iar_reg : component reg_multiple_out
+    generic map ( num_outputs => 2 )
+    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus,
+               latch_en => iar_latch_en,
+               out_en(1) => iar_out_en1, out_en(2) => iar_out_en2 );
+
+  pc_reg : component reg_multiple_plus_one_out_reset
+    generic map ( num_outputs => 2 )
+    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => pc_to_mem,
+               latch_en => pc_latch_en,
+               out_en(1) => pc_out_en1, out_en(2) => pc_out_en2,
+	       reset => reset );
+
+  mar_reg : component reg_multiple_plus_one_out
+    generic map ( num_outputs => 2 )
+    port map ( d => dest_bus, q(1) => s1_bus, q(2) => s2_bus, q0 => mar_to_mem,
+               latch_en => mar_latch_en,
+               out_en(1) => mar_out_en1, out_en(2) => mar_out_en2 );
+
+  mem_addr_mux : component mux2
+    port map ( i0 => pc_to_mem, i1 => mar_to_mem, y => a,
+               sel => mem_addr_mux_sel );
+
+  mdr_reg : component reg_multiple_out
+    generic map ( num_outputs => 3 )
+    port map ( d => mdr_in, q(1) => s1_bus, q(2) => s2_bus, q(3) => d,
+               latch_en => mdr_latch_en,
+               out_en(1) => mdr_out_en1, out_en(2) => mdr_out_en2,
+	       out_en(3) => mdr_out_en3 );
+
+  mdr_mux : component mux2
+    port map ( i0 => dest_bus, i1 => d, y => mdr_in,
+               sel => mdr_mux_sel );
+
+  instr_reg : component latch
+    port map ( d => d, q => current_instruction,
+               latch_en => ir_latch_en );
+
+  ir_extender1 : component ir_extender
+    port map ( d => current_instruction, q => s1_bus,
+               immed_size_26 => ir_immed1_size_26,
+	       immed_unsigned => ir_immed1_unsigned,
+               immed_en => ir_immed1_en );
+
+  ir_extender2 : component ir_extender
+    port map ( d => current_instruction, q => s2_bus,
+               immed_size_26 => ir_immed2_size_26,
+	       immed_unsigned => ir_immed2_unsigned,
+               immed_en => ir_immed2_en );
+
+  the_controller : component controller
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt, 
+      	       width => width, write_enable => write_enable, mem_enable => mem_enable,
+	       ifetch => ifetch, ready => ready, 
+               alu_in_latch_en => alu_in_latch_en, alu_function => alu_function,
+	       alu_zero => alu_zero, alu_negative => alu_negative,
+	       alu_overflow => alu_overflow,
+               reg_s1_addr => reg_s1_addr, reg_s2_addr => reg_s2_addr,
+	       reg_dest_addr => reg_dest_addr, reg_write => reg_write, 
+               c_latch_en => c_latch_en,
+	       a_latch_en => a_latch_en, a_out_en => a_out_en,
+	       b_latch_en => b_latch_en, b_out_en =>  b_out_en, 
+               temp_latch_en => temp_latch_en,
+	       temp_out_en1 => temp_out_en1, temp_out_en2 => temp_out_en2, 
+               iar_latch_en => iar_latch_en,
+	       iar_out_en1 => iar_out_en1, iar_out_en2 => iar_out_en2, 
+               pc_latch_en => pc_latch_en,
+	       pc_out_en1 => pc_out_en1, pc_out_en2 => pc_out_en2, 
+               mem_addr_mux_sel => mem_addr_mux_sel, mar_latch_en => mar_latch_en,
+	       mar_out_en1 => mar_out_en1, mar_out_en2 => mar_out_en2,
+               mdr_mux_sel => mdr_mux_sel, mdr_latch_en => mdr_latch_en,
+	       mdr_out_en1 => mdr_out_en1, mdr_out_en2 => mdr_out_en2, 
+	       mdr_out_en3 => mdr_out_en3, 
+               ir_latch_en => ir_latch_en,
+	       ir_immed1_size_26 => ir_immed1_size_26,
+	       ir_immed2_size_26 => ir_immed2_size_26,
+	       ir_immed1_unsigned => ir_immed1_unsigned,
+	       ir_immed2_unsigned => ir_immed2_unsigned,
+	       ir_immed1_en => ir_immed1_en, ir_immed2_en => ir_immed2_en,  
+               current_instruction => current_instruction,
+	       mem_addr => mar_to_mem(1 downto 0),
+	       const1 => s1_bus, const2 => s2_bus );
+
+end architecture rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx.vhd
new file mode 100644
index 0000000..a261921
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlx.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlx.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+               use work.dlx_types.all;
+
+               entity dlx is
+
+                 generic ( Tpd_clk_out : delay_length;
+                           debug : dlx_debug_control := none );
+
+                 port ( phi1, phi2 : in std_logic;
+                        reset : in std_logic;
+                        halt : out std_logic;
+                        a : out dlx_address;
+                        d : inout dlx_word;
+                        width : out dlx_mem_width;
+                        write_enable : out std_logic;
+                        ifetch : out std_logic;
+                        mem_enable : out std_logic;
+                        ready : in std_logic );
+
+               end entity dlx;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi-b.vhd
new file mode 100644
index 0000000..3194fad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi-b.vhd
@@ -0,0 +1,320 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxi-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+package body dlx_instr is
+
+  use bv_utilities.bv_arithmetic.all;
+
+  constant opcode_names : opcode_name_array
+    := ( "SPECIAL ",   "FPARITH ",   "J       ",   "JAL     ",
+         "BEQZ    ",   "BNEZ    ",   "BFPT    ",   "BFPF    ",
+         "ADDI    ",    "ADDUI   ",   "SUBI    ",   "SUBUI   ",
+         "ANDI    ",   "ORI     ",   "XORI    ",   "LHI     ",
+         "RFE     ",   "TRAP    ",   "JR      ",   "JALR    ",
+         "SLLI    ",   "UNDEF_15",   "SRLI    ",   "SRAI    ",
+         "SEQI    ",   "SNEI    ",   "SLTI    ",   "SGTI    ",
+         "SLEI    ",   "SGEI    ",   "UNDEF_1E",   "UNDEF_1F",
+         "LB      ",   "LH      ",   "UNDEF_22",   "LW      ",
+         "LBU     ",   "LHU     ",   "LF      ",   "LD      ",
+         "SB      ",   "SH      ",   "UNDEF_2A",   "SW      ",
+         "UNDEF_2C",   "UNDEF_2D",   "SF      ",   "SD      ",
+         "SEQUI   ",   "SNEUI   ",   "SLTUI   ",   "SGTUI   ",
+         "SLEUI   ",   "SGEUI   ",   "UNDEF_36",   "UNDEF_37",
+         "UNDEF_38",   "UNDEF_39",   "UNDEF_3A",   "UNDEF_3B",
+         "UNDEF_3C",   "UNDEF_3D",   "UNDEF_3E",   "UNDEF_3F" );
+
+  constant sp_func_names : sp_func_name_array
+    := ( "NOP     ",   "UNDEF_01",   "UNDEF_02",   "UNDEF_03",
+         "SLL     ",   "UNDEF_05",   "SRL     ",   "SRA     ",
+         "UNDEF_08",   "UNDEF_09",   "UNDEF_0A",   "UNDEF_0B",
+         "UNDEF_0C",   "UNDEF_0D",   "UNDEF_0E",   "UNDEF_0F",
+         "SEQU    ",   "SNEU    ",   "SLTU    ",   "SGTU    ",
+         "SLEU    ",   "SGEU    ",   "UNDEF_16",   "UNDEF_17",
+         "UNDEF_18",   "UNDEF_19",   "UNDEF_1A",   "UNDEF_1B",
+         "UNDEF_1C",   "UNDEF_1D",   "UNDEF_1E",   "UNDEF_1F",
+         "ADD     ",   "ADDU    ",   "SUB     ",   "SUBU    ",
+         "AND     ",   "OR      ",   "XOR     ",   "UNDEF_27",
+         "SEQ     ",   "SNE     ",   "SLT     ",   "SGT     ",
+         "SLE     ",   "SGE     ",   "UNDEF_2E",   "UNDEF_2F",
+         "MOVI2S  ",   "MOVS2I  ",   "MOVF    ",   "MOVD    ",
+         "MOVFP2I ",   "MOVI2FP ",   "UNDEF_36",   "UNDEF_37",
+         "UNDEF_38",   "UNDEF_39",   "UNDEF_3A",   "UNDEF_3B",
+         "UNDEF_3C",   "UNDEF_3D",   "UNDEF_3E",   "UNDEF_3F" );
+
+  constant fp_func_names : fp_func_name_array
+    := ( "ADDF    ",   "SUBF    ",   "MULTF   ",   "DIVF    ",
+         "ADDD    ",   "SUBD    ",   "MULTD   ",   "DIVD    ",
+         "CVTF2D  ",   "CVTF2I  ",   "CVTD2F  ",   "CVTD2I  ",
+         "CVTI2F  ",   "CVTI2D  ",   "MULT    ",   "DIV     ",
+         "EQF     ",   "NEF     ",   "LTF     ",   "GTF     ",
+         "LEF     ",   "GEF     ",   "MULTU   ",   "DIVU    ",
+         "EQD     ",   "NED     ",   "LTD     ",   "GTD     ",
+         "LED     ",   "GED     ",   "UNDEF_1E",   "UNDEF_1F" );
+
+
+  procedure disassemble ( instr : dlx_bv_word;
+			  disassembled_instr : out string;  len : out positive ) is
+
+    alias norm_disassembled_instr : string(1 to disassembled_instr'length)
+      is disassembled_instr;
+
+    alias instr_opcode : dlx_opcode is instr(0 to 5);
+    alias instr_sp_func : dlx_sp_func is instr(26 to 31);
+    alias instr_fp_func : dlx_fp_func is instr(27 to 31);
+    alias instr_rs1 : dlx_reg_addr is instr(6 to 10);
+    alias instr_rs2 : dlx_reg_addr is instr(11 to 15);
+    alias instr_Itype_rd : dlx_reg_addr is instr(11 to 15);
+    alias instr_Rtype_rd : dlx_reg_addr is instr(16 to 20);
+    alias instr_immed16 : dlx_immed16 is instr(16 to 31);
+    alias instr_immed26 : dlx_immed26 is instr(6 to 31);
+
+    variable instr_opcode_num : dlx_opcode_num;
+    variable instr_sp_func_num : dlx_sp_func_num;
+    variable instr_fp_func_num : dlx_fp_func_num;
+    variable rs1 : reg_index;
+    variable rs2 : reg_index;
+    variable Itype_rd : reg_index;
+    variable Rtype_rd : reg_index;
+    variable result : string(1 to 40)	-- long enough for longest instruction
+		:= (others => ' ');
+    variable index : positive range 1 to 41 := 1;  -- position for next char in result
+
+    procedure disassemble_reg ( reg : reg_index;  reg_prefix : character ) is
+    begin
+      result(index) := reg_prefix;
+      index := index + 1;
+      if reg < 10 then
+        result(index to index) := integer'image(reg);
+        index := index + 1;
+      else
+        result(index to index + 1) := integer'image(reg);
+        index := index + 2;
+      end if;
+    end procedure disassemble_reg;
+
+    procedure disassemble_special_reg ( reg : reg_index ) is
+    begin
+      case reg is
+        when 0 =>
+          result(index to index + 2) := "IAR";
+          index := index + 3;
+        when 1 =>
+          result(index to index + 2) := "FSR";
+          index := index + 3;
+        when others =>
+          disassemble_reg(reg, 'S');
+      end case;
+    end procedure disassemble_special_reg;
+
+    procedure disassemble_integer ( int : integer ) is
+      constant int_image_length : natural := integer'image(int)'length;
+    begin
+      result(index to index + int_image_length - 1) := integer'image(int);
+      index := index + int_image_length;
+    end procedure disassemble_integer;
+
+  begin
+    instr_opcode_num := bv_to_natural(instr_opcode);
+    instr_sp_func_num := bv_to_natural(instr_sp_func);
+    instr_fp_func_num := bv_to_natural(instr_fp_func);
+    rs1 := bv_to_natural(instr_rs1);
+    rs2 := bv_to_natural(instr_rs2);
+    Itype_rd := bv_to_natural(instr_Itype_rd);
+    Rtype_rd := bv_to_natural(instr_Rtype_rd);
+    if (instr_opcode /= op_special) and (instr_opcode /= op_fparith) then
+      result(index to index + instr_name'length - 1) := opcode_names(instr_opcode_num);
+      index := index + instr_name'length + 1;  -- include space after opcode name
+    end if;
+    case instr_opcode is
+      when op_special =>
+	result(index to index + instr_name'length - 1) := sp_func_names(instr_sp_func_num);
+        index := index + instr_name'length + 1;  -- include space after function name
+        case instr_sp_func is
+          when sp_func_nop =>
+            null;
+          when sp_func_sll | sp_func_srl | sp_func_sra
+            | sp_func_sequ | sp_func_sneu | sp_func_sltu
+            | sp_func_sgtu | sp_func_sleu | sp_func_sgeu
+            | sp_func_add | sp_func_addu | sp_func_sub | sp_func_subu
+            | sp_func_and | sp_func_or | sp_func_xor
+            | sp_func_seq | sp_func_sne | sp_func_slt
+            | sp_func_sgt | sp_func_sle | sp_func_sge =>
+	    disassemble_reg(Rtype_rd, 'R');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'R');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs2, 'R');
+          when sp_func_movi2s =>
+	    disassemble_special_reg(Rtype_rd);
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'R');
+          when sp_func_movs2i =>
+	    disassemble_reg(Rtype_rd, 'R');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_special_reg(rs1);
+          when sp_func_movf | sp_func_movd =>
+	    disassemble_reg(Rtype_rd, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'F');
+          when sp_func_movfp2i =>
+	    disassemble_reg(Rtype_rd, 'R');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'F');
+          when sp_func_movi2fp =>
+	    disassemble_reg(Rtype_rd, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'R');
+          when others =>
+            null;
+        end case;
+      when op_fparith =>
+	result(index to index + instr_name'length - 1) := fp_func_names(instr_fp_func_num);
+        index := index + instr_name'length + 1;  -- include space after function name
+        case instr_fp_func is
+          when fp_func_addf | fp_func_subf | fp_func_multf | fp_func_divf
+            | fp_func_addd | fp_func_subd | fp_func_multd | fp_func_divd
+            | fp_func_mult | fp_func_div | fp_func_multu | fp_func_divu =>
+	    disassemble_reg(Rtype_rd, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs2, 'F');
+          when fp_func_cvtf2d | fp_func_cvtd2f =>
+	    disassemble_reg(Rtype_rd, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'F');
+          when fp_func_cvtf2i | fp_func_cvtd2i =>
+	    disassemble_reg(Rtype_rd, 'R');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'F');
+          when fp_func_cvti2f | fp_func_cvti2d =>
+	    disassemble_reg(Rtype_rd, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs1, 'R');
+          when fp_func_eqf | fp_func_nef | fp_func_ltf
+            | fp_func_gtf | fp_func_lef | fp_func_gef
+            | fp_func_eqd | fp_func_ned | fp_func_ltd
+            | fp_func_gtd | fp_func_led | fp_func_ged =>
+	    disassemble_reg(rs1, 'F');
+	    result(index) := ',';
+	    index := index + 2;  -- include space after comma
+	    disassemble_reg(rs2, 'F');
+          when others =>
+            null;
+        end case;
+      when op_j  | op_jal =>
+        disassemble_integer(bv_to_integer(instr_immed26));
+      when op_beqz | op_bnez =>
+	disassemble_reg(rs1, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_integer(instr_immed16));
+      when op_bfpt | op_bfpf =>
+	disassemble_integer(bv_to_integer(instr_immed16));
+      when op_slli | op_srli | op_srai =>
+	disassemble_reg(Itype_rd, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_reg(rs1, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_natural(instr_immed16(11 to 15)));
+      when op_addi | op_subi
+        | op_seqi | op_snei | op_slti | op_sgti | op_slei | op_sgei =>
+	disassemble_reg(Itype_rd, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_reg(rs1, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_integer(instr_immed16));
+      when op_addui | op_subui | op_andi | op_ori | op_xori
+        | op_sequi | op_sneui | op_sltui | op_sgtui | op_sleui | op_sgeui =>
+	disassemble_reg(Itype_rd, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_reg(rs1, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_natural(instr_immed16));
+      when op_lhi =>
+	disassemble_reg(Itype_rd, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_natural(instr_immed16));
+      when op_rfe =>
+        null;
+      when op_trap =>
+	disassemble_integer(bv_to_natural(instr_immed26));
+      when op_jr | op_jalr =>
+	disassemble_reg(rs1, 'R');
+      when op_lb | op_lh | op_lw | op_lbu | op_lhu | op_lf | op_ld =>
+	disassemble_reg(Itype_rd, 'R');
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_integer(bv_to_integer(instr_immed16));
+        result(index) := '(';
+                           index := index + 1;
+                           disassemble_reg(rs1, 'R');
+                           result(index) := ')';
+	index := index + 1;
+      when op_sb | op_sh | op_sw | op_sf | op_sd =>
+	disassemble_integer(bv_to_integer(instr_immed16));
+        result(index) := '(';
+                           index := index + 1;
+                           disassemble_reg(rs1, 'R');
+                           result(index) := ')';
+	index := index + 1;
+	result(index) := ',';
+	index := index + 2;  -- include space after comma
+	disassemble_reg(Itype_rd, 'R');
+      when others =>
+        null;  -- remaining opcodes have no operands to disassemble
+    end case;
+    if index > norm_disassembled_instr'length then
+      index := norm_disassembled_instr'length;  -- limit to out parameter length
+    else
+      index := index - 1;  -- index points to last result character
+    end if;
+    norm_disassembled_instr(1 to index) := result(1 to index);
+    len := index;
+  end procedure disassemble;
+
+end package body dlx_instr;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi.vhd
new file mode 100644
index 0000000..f4436fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxi.vhd
@@ -0,0 +1,228 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxi.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+use work.dlx_types.all;
+
+package dlx_instr is
+
+  subtype dlx_opcode is bit_vector(0 to 5);
+  subtype dlx_sp_func is bit_vector(0 to 5);
+  subtype dlx_fp_func is bit_vector(0 to 4);
+  subtype dlx_reg_addr is bit_vector(0 to 4);
+  subtype dlx_immed16 is bit_vector(0 to 15);
+  subtype dlx_immed26 is bit_vector(0 to 25);
+
+  constant op_special   : dlx_opcode := B"000000";
+  constant op_fparith   : dlx_opcode := B"000001";
+  constant op_j         : dlx_opcode := B"000010";
+  constant op_jal       : dlx_opcode := B"000011";
+  constant op_beqz      : dlx_opcode := B"000100";
+  constant op_bnez      : dlx_opcode := B"000101";
+  constant op_bfpt      : dlx_opcode := B"000110";
+  constant op_bfpf      : dlx_opcode := B"000111";
+  constant op_addi      : dlx_opcode := B"001000";
+  constant op_addui     : dlx_opcode := B"001001";
+  constant op_subi	: dlx_opcode := B"001010";
+  constant op_subui	: dlx_opcode := B"001011";
+  constant op_andi	: dlx_opcode := B"001100";
+  constant op_ori	: dlx_opcode := B"001101";
+  constant op_xori	: dlx_opcode := B"001110";
+  constant op_lhi	: dlx_opcode := B"001111";
+
+  constant op_rfe	: dlx_opcode := B"010000";
+  constant op_trap	: dlx_opcode := B"010001";
+  constant op_jr	: dlx_opcode := B"010010";
+  constant op_jalr	: dlx_opcode := B"010011";
+  constant op_slli	: dlx_opcode := B"010100";
+  constant op_undef_15	: dlx_opcode := B"010101";
+  constant op_srli	: dlx_opcode := B"010110";
+  constant op_srai	: dlx_opcode := B"010111";
+  constant op_seqi	: dlx_opcode := B"011000";
+  constant op_snei	: dlx_opcode := B"011001";
+  constant op_slti	: dlx_opcode := B"011010";
+  constant op_sgti	: dlx_opcode := B"011011";
+  constant op_slei	: dlx_opcode := B"011100";
+  constant op_sgei	: dlx_opcode := B"011101";
+  constant op_undef_1E	: dlx_opcode := B"011110";
+  constant op_undef_1F	: dlx_opcode := B"011111";
+
+  constant op_lb	: dlx_opcode := B"100000";
+  constant op_lh	: dlx_opcode := B"100001";
+  constant op_undef_22	: dlx_opcode := B"100010";
+  constant op_lw	: dlx_opcode := B"100011";
+  constant op_lbu	: dlx_opcode := B"100100";
+  constant op_lhu	: dlx_opcode := B"100101";
+  constant op_lf	: dlx_opcode := B"100110";
+  constant op_ld	: dlx_opcode := B"100111";
+  constant op_sb	: dlx_opcode := B"101000";
+  constant op_sh	: dlx_opcode := B"101001";
+  constant op_undef_2A	: dlx_opcode := B"101010";
+  constant op_sw	: dlx_opcode := B"101011";
+  constant op_undef_2C	: dlx_opcode := B"101100";
+  constant op_undef_2D	: dlx_opcode := B"101101";
+  constant op_sf	: dlx_opcode := B"101110";
+  constant op_sd	: dlx_opcode := B"101111";
+
+  constant op_sequi	: dlx_opcode := B"110000";
+  constant op_sneui	: dlx_opcode := B"110001";
+  constant op_sltui	: dlx_opcode := B"110010";
+  constant op_sgtui	: dlx_opcode := B"110011";
+  constant op_sleui	: dlx_opcode := B"110100";
+  constant op_sgeui	: dlx_opcode := B"110101";
+  constant op_undef_36	: dlx_opcode := B"110110";
+  constant op_undef_37	: dlx_opcode := B"110111";
+  constant op_undef_38	: dlx_opcode := B"111000";
+  constant op_undef_39	: dlx_opcode := B"111001";
+  constant op_undef_3A	: dlx_opcode := B"111010";
+  constant op_undef_3B	: dlx_opcode := B"111011";
+  constant op_undef_3C	: dlx_opcode := B"111100";
+  constant op_undef_3D	: dlx_opcode := B"111101";
+  constant op_undef_3E	: dlx_opcode := B"111110";
+  constant op_undef_3F  : dlx_opcode := B"111111";
+
+  constant sp_func_nop       : dlx_sp_func := B"000000";
+  constant sp_func_undef_01  : dlx_sp_func := B"000001";
+  constant sp_func_undef_02  : dlx_sp_func := B"000010";
+  constant sp_func_undef_03  : dlx_sp_func := B"000011";
+  constant sp_func_sll       : dlx_sp_func := B"000100";
+  constant sp_func_undef_05  : dlx_sp_func := B"000101";
+  constant sp_func_srl	     : dlx_sp_func := B"000110";
+  constant sp_func_sra	     : dlx_sp_func := B"000111";
+  constant sp_func_undef_08  : dlx_sp_func := B"001000";
+  constant sp_func_undef_09  : dlx_sp_func := B"001001";
+  constant sp_func_undef_0A  : dlx_sp_func := B"001010";
+  constant sp_func_undef_0B  : dlx_sp_func := B"001011";
+  constant sp_func_undef_0C  : dlx_sp_func := B"001100";
+  constant sp_func_undef_0D  : dlx_sp_func := B"001101";
+  constant sp_func_undef_0E  : dlx_sp_func := B"001110";
+  constant sp_func_undef_0F  : dlx_sp_func := B"001111";
+  
+  constant sp_func_sequ	     : dlx_sp_func := B"010000";
+  constant sp_func_sneu	     : dlx_sp_func := B"010001";
+  constant sp_func_sltu	     : dlx_sp_func := B"010010";
+  constant sp_func_sgtu	     : dlx_sp_func := B"010011";
+  constant sp_func_sleu	     : dlx_sp_func := B"010100";
+  constant sp_func_sgeu	     : dlx_sp_func := B"010101";
+  constant sp_func_undef_16  : dlx_sp_func := B"010110";
+  constant sp_func_undef_17  : dlx_sp_func := B"010111";
+  constant sp_func_undef_18  : dlx_sp_func := B"011000";
+  constant sp_func_undef_19  : dlx_sp_func := B"011001";
+  constant sp_func_undef_1A  : dlx_sp_func := B"011010";
+  constant sp_func_undef_1B  : dlx_sp_func := B"011011";
+  constant sp_func_undef_1C  : dlx_sp_func := B"011100";
+  constant sp_func_undef_1D  : dlx_sp_func := B"011101";
+  constant sp_func_undef_1E  : dlx_sp_func := B"011110";
+  constant sp_func_undef_1F  : dlx_sp_func := B"011111";
+  
+  constant sp_func_add	     : dlx_sp_func := B"100000";
+  constant sp_func_addu	     : dlx_sp_func := B"100001";
+  constant sp_func_sub	     : dlx_sp_func := B"100010";
+  constant sp_func_subu	     : dlx_sp_func := B"100011";
+  constant sp_func_and	     : dlx_sp_func := B"100100";
+  constant sp_func_or	     : dlx_sp_func := B"100101";
+  constant sp_func_xor	     : dlx_sp_func := B"100110";
+  constant sp_func_undef_27  : dlx_sp_func := B"100111";
+  constant sp_func_seq	     : dlx_sp_func := B"101000";
+  constant sp_func_sne	     : dlx_sp_func := B"101001";
+  constant sp_func_slt	     : dlx_sp_func := B"101010";
+  constant sp_func_sgt	     : dlx_sp_func := B"101011";
+  constant sp_func_sle	     : dlx_sp_func := B"101100";
+  constant sp_func_sge	     : dlx_sp_func := B"101101";
+  constant sp_func_undef_2E  : dlx_sp_func := B"101110";
+  constant sp_func_undef_2F  : dlx_sp_func := B"101111";
+  
+  constant sp_func_movi2s    : dlx_sp_func := B"110000";
+  constant sp_func_movs2i    : dlx_sp_func := B"110001";
+  constant sp_func_movf	     : dlx_sp_func := B"110010";
+  constant sp_func_movd	     : dlx_sp_func := B"110011";
+  constant sp_func_movfp2i   : dlx_sp_func := B"110100";
+  constant sp_func_movi2fp   : dlx_sp_func := B"110101";
+  constant sp_func_undef_36  : dlx_sp_func := B"110110";
+  constant sp_func_undef_37  : dlx_sp_func := B"110111";
+  constant sp_func_undef_38  : dlx_sp_func := B"111000";
+  constant sp_func_undef_39  : dlx_sp_func := B"111001";
+  constant sp_func_undef_3A  : dlx_sp_func := B"111010";
+  constant sp_func_undef_3B  : dlx_sp_func := B"111011";
+  constant sp_func_undef_3C  : dlx_sp_func := B"111100";
+  constant sp_func_undef_3D  : dlx_sp_func := B"111101";
+  constant sp_func_undef_3E  : dlx_sp_func := B"111110";
+  constant sp_func_undef_3F  : dlx_sp_func := B"111111";
+  
+  constant fp_func_addf      : dlx_fp_func := B"00000";
+  constant fp_func_subf      : dlx_fp_func := B"00001";
+  constant fp_func_multf     : dlx_fp_func := B"00010";
+  constant fp_func_divf	     : dlx_fp_func := B"00011";
+  constant fp_func_addd	     : dlx_fp_func := B"00100";
+  constant fp_func_subd	     : dlx_fp_func := B"00101";
+  constant fp_func_multd     : dlx_fp_func := B"00110";
+  constant fp_func_divd	     : dlx_fp_func := B"00111";
+  constant fp_func_cvtf2d    : dlx_fp_func := B"01000";
+  constant fp_func_cvtf2i    : dlx_fp_func := B"01001";
+  constant fp_func_cvtd2f    : dlx_fp_func := B"01010";
+  constant fp_func_cvtd2i    : dlx_fp_func := B"01011";
+  constant fp_func_cvti2f    : dlx_fp_func := B"01100";
+  constant fp_func_cvti2d    : dlx_fp_func := B"01101";
+  constant fp_func_mult	     : dlx_fp_func := B"01110";
+  constant fp_func_div	     : dlx_fp_func := B"01111";
+  
+  constant fp_func_eqf	     : dlx_fp_func := B"10000";
+  constant fp_func_nef	     : dlx_fp_func := B"10001";
+  constant fp_func_ltf	     : dlx_fp_func := B"10010";
+  constant fp_func_gtf	     : dlx_fp_func := B"10011";
+  constant fp_func_lef	     : dlx_fp_func := B"10100";
+  constant fp_func_gef	     : dlx_fp_func := B"10101";
+  constant fp_func_multu     : dlx_fp_func := B"10110";
+  constant fp_func_divu	     : dlx_fp_func := B"10111";
+  constant fp_func_eqd	     : dlx_fp_func := B"11000";
+  constant fp_func_ned	     : dlx_fp_func := B"11001";
+  constant fp_func_ltd	     : dlx_fp_func := B"11010";
+  constant fp_func_gtd	     : dlx_fp_func := B"11011";
+  constant fp_func_led	     : dlx_fp_func := B"11100";
+  constant fp_func_ged	     : dlx_fp_func := B"11101";
+  constant fp_func_undef_1E  : dlx_fp_func := B"11110";
+  constant fp_func_undef_1F  : dlx_fp_func := B"11111";
+
+  subtype dlx_opcode_num is natural range 0 to 63;
+  subtype dlx_sp_func_num is natural range 0 to 63;
+  subtype dlx_fp_func_num is natural range 0 to 31;
+
+  subtype instr_name is string(1 to 8);
+  type opcode_name_array is array (dlx_opcode_num) of instr_name;
+  type sp_func_name_array is array (dlx_sp_func_num) of instr_name;
+  type fp_func_name_array is array (dlx_fp_func_num) of instr_name;
+
+  constant opcode_names : opcode_name_array;
+  constant sp_func_names : sp_func_name_array;
+  constant fp_func_names : fp_func_name_array;
+
+  subtype reg_index is natural range 0 to 31;
+
+  constant link_reg : reg_index := 31;
+
+  procedure disassemble ( instr : dlx_bv_word;
+			  disassembled_instr : out string;  len : out positive );
+
+end package dlx_instr;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxr.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxr.vhd
new file mode 100644
index 0000000..a00dc21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxr.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration dlx_rtl of dlx is
+
+  for rtl
+
+    for alu_s1_reg : latch
+      use entity work.latch(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for alu_s2_reg : latch
+      use entity work.latch(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for the_alu : alu
+      use entity work.alu(behavior)
+        generic map ( Tpd => 4 ns );
+    end for;
+
+    for the_reg_file : reg_file
+      use entity work.reg_file(behavior)
+        generic map ( Tac => 4 ns );
+    end for;
+
+    for c_reg : latch
+      use entity work.latch(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for a_reg : reg_multiple_out
+      use entity work.reg_multiple_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for b_reg : reg_multiple_out
+      use entity work.reg_multiple_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for temp_reg : reg_multiple_out
+      use entity work.reg_multiple_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for iar_reg : reg_multiple_out
+      use entity work.reg_multiple_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for pc_reg :reg_multiple_plus_one_out_reset
+      use entity work.reg_multiple_plus_one_out_reset(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for mar_reg : reg_multiple_plus_one_out
+      use entity work.reg_multiple_plus_one_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for mem_addr_mux : mux2
+      use entity work.mux2(behavior)
+        generic map ( Tpd => 1 ns );
+    end for;
+
+    for mdr_reg : reg_multiple_out
+      use entity work.reg_multiple_out(behavior)
+        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
+    end for;
+
+    for mdr_mux : mux2
+      use entity work.mux2(behavior)
+        generic map ( Tpd => 1 ns );
+    end for;
+
+    for instr_reg : latch
+      use entity work.latch(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for ir_extender1 : ir_extender
+      use entity work.ir_extender(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for ir_extender2 : ir_extender
+      use entity work.ir_extender(behavior)
+        generic map ( Tpd => 2 ns );
+    end for;
+
+    for the_controller : controller
+      use entity work.controller(behavior)
+        generic map ( Tpd_clk_ctrl => 2 ns, Tpd_clk_const => 4 ns,
+                      debug => debug );
+    end for;
+
+  end for;  -- rtl of dlx
+
+end configuration dlx_rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxstsv.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxstsv.vhd
new file mode 100644
index 0000000..0a211df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxstsv.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxstsv.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration dlx_test_verifier of dlx_test is
+
+  for verifier
+
+    for cg : clock_gen
+      use entity work.clock_gen(behavior)
+        generic map ( Tpw => 8 ns, Tps => 2 ns );
+    end for;
+
+    for mem : memory
+      use entity work.memory(preloaded)
+        generic map ( mem_size => 65536,
+                      Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
+    end for;
+
+    for proc_behav : dlx
+      use entity work.dlx(behavior)
+        generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
+    end for;
+
+    for proc_rtl : dlx
+      use configuration work.dlx_rtl
+        generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
+    end for;
+
+  end for;  -- verifier of dlx_test
+
+end configuration dlx_test_verifier;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxt.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxt.vhd
new file mode 100644
index 0000000..190ea0c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxt.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxt.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package dlx_types is
+
+  -- little-endian addresses
+  subtype dlx_address is std_logic_vector(31 downto 0);
+  subtype dlx_bv_address is bit_vector(31 downto 0);
+
+  -- big-endian data words
+  subtype dlx_word is std_logic_vector(0 to 31);
+  subtype dlx_bv_word is bit_vector(0 to 31);
+
+  type dlx_word_array is array (natural range <>) of dlx_word;
+
+  -- tristate bus driving value
+  constant disabled_dlx_word : dlx_word := ( others => 'Z' );
+
+  -- type for specifying data width on the data bus
+  subtype dlx_mem_width is std_logic_vector(1 downto 0);
+
+  constant dlx_mem_width_byte : dlx_mem_width := "01";
+  constant dlx_mem_width_halfword : dlx_mem_width := "10";
+  constant dlx_mem_width_word : dlx_mem_width := "00";
+
+  -- type for controlling trace information generated by model
+  type dlx_debug_control is
+    ( none,
+      msg_every_100_instructions, msg_each_instruction,
+      trace_each_instruction, trace_each_step );
+
+end package dlx_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-b.vhd
new file mode 100644
index 0000000..65e91af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-b.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxtst-b.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture bench of dlx_test is
+
+  use work.dlx_types.all;
+
+  component clock_gen is
+                        port ( phi1, phi2 : out std_logic;
+                               reset : out std_logic );
+  end component clock_gen;
+
+  component memory is
+                     port ( phi1, phi2 : in std_logic;
+                            a : in dlx_address;
+                            d : inout dlx_word;
+                            width : in dlx_mem_width;
+                            write_enable : in std_logic;
+                            burst : in std_logic := '0';
+                            mem_enable : in std_logic;
+                            ready : out std_logic );
+  end component memory;
+
+  component dlx is
+                  port ( phi1, phi2 : in std_logic;
+                         reset : in std_logic;
+                         halt : out std_logic;
+                         a : out dlx_address;
+                         d : inout dlx_word;
+                         width : out dlx_mem_width;
+                         write_enable : out std_logic;
+                         ifetch : out std_logic;
+                         mem_enable : out std_logic;
+                         ready : in std_logic );
+  end component dlx;
+
+  signal phi1, phi2, reset : std_logic;
+  signal a : dlx_address;
+  signal d : dlx_word;
+  signal halt : std_logic;
+  signal width : dlx_mem_width;
+  signal write_enable, mem_enable, ifetch, ready : std_logic;
+
+begin
+
+  cg : component clock_gen
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset );
+
+  mem : component memory
+    port map ( phi1 => phi1, phi2 => phi2,
+               a => a, d => d,
+               width => width, write_enable => write_enable, burst => open,
+               mem_enable => mem_enable, ready => ready );
+
+  proc : component dlx
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt,
+               a => a, d => d,
+               width => width, write_enable => write_enable, ifetch => ifetch,
+               mem_enable => mem_enable, ready => ready );
+
+end architecture bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-v.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-v.vhd
new file mode 100644
index 0000000..b031296
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst-v.vhd
@@ -0,0 +1,156 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxtst-v.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture verifier of dlx_test is
+
+  use work.dlx_types.all;
+
+  component clock_gen is
+                        port ( phi1, phi2 : out std_logic;
+                               reset : out std_logic );
+  end component clock_gen;
+
+  component memory is
+                     port ( phi1, phi2 : in std_logic;
+                            a : in dlx_address;
+                            d : inout dlx_word;
+                            width : in dlx_mem_width;
+                            write_enable : in std_logic;
+                            burst : in std_logic := '0';
+                            mem_enable : in std_logic;
+                            ready : out std_logic );
+  end component memory;
+
+  component dlx is
+                  port ( phi1, phi2 : in std_logic;
+                         reset : in std_logic;
+                         halt : out std_logic;
+                         a : out dlx_address;
+                         d : inout dlx_word;
+                         width : out dlx_mem_width;
+                         write_enable : out std_logic;
+                         ifetch : out std_logic;
+                         mem_enable : out std_logic;
+                         ready : in std_logic );
+  end component dlx;
+
+  signal phi1, phi2, reset : std_logic;
+
+  signal a_behav : dlx_address;
+  signal d_behav : dlx_word;
+  signal halt_behav : std_logic;
+  signal width_behav : dlx_mem_width;
+  signal write_enable_behav, mem_enable_behav, ifetch_behav : std_logic;
+
+  signal a_rtl : dlx_address;
+  signal d_rtl : dlx_word;
+  signal halt_rtl : std_logic;
+  signal width_rtl : dlx_mem_width;
+  signal write_enable_rtl, mem_enable_rtl, ifetch_rtl : std_logic;
+
+  signal ready_mem : std_logic;
+
+begin
+
+  cg : component clock_gen
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset );
+
+  mem : component memory
+    port map ( phi1 => phi1, phi2 => phi2,
+               a => a_behav, d => d_behav,
+               width => width_behav, write_enable => write_enable_behav,
+               burst => open,
+               mem_enable => mem_enable_behav, ready => ready_mem );
+
+  proc_behav : component dlx
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_behav,
+               a => a_behav, d => d_behav,
+               width => width_behav, write_enable => write_enable_behav,
+               ifetch => ifetch_behav,
+               mem_enable => mem_enable_behav, ready => ready_mem );
+
+  proc_rtl : component dlx
+    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_rtl,
+               a => a_rtl, d => d_rtl,
+               width => width_rtl, write_enable => write_enable_rtl,
+               ifetch => ifetch_rtl,
+               mem_enable => mem_enable_rtl, ready => ready_mem );
+
+  verification_section : block is
+  begin
+
+    fwd_data_from_mem_to_rtl : 
+      d_rtl <= d_behav when mem_enable_rtl = '1'
+               and write_enable_rtl = '0' else
+               disabled_dlx_word;
+
+    monitor : process
+
+      variable write_command_behav : boolean;
+      variable write_command_rtl : boolean;
+
+    begin
+      monitor_loop : loop
+        -- wait for a command, valid on leading edge of phi2
+        wait until rising_edge(phi2)
+          and mem_enable_behav = '1' and mem_enable_rtl = '1';
+        --
+        -- capture the command information
+        write_command_behav := write_enable_behav = '1';
+        write_command_rtl := write_enable_rtl = '1';
+        assert a_behav = a_rtl
+          report "addresses differ";
+        assert write_enable_behav = write_enable_rtl
+          report "write enable states differ";
+        assert ifetch_behav = ifetch_rtl
+          report "instruction fetch states differ";
+        assert width_behav = width_rtl
+          report "widths differ";
+        if write_command_behav and write_command_rtl then
+          assert d_behav = d_rtl
+            report "write data differs";
+        end if;
+        --
+        -- wait for the response from memory
+        ready_loop : loop 
+          wait until falling_edge(phi2);
+          exit monitor_loop when reset = '1';
+          exit ready_loop when ready_mem = '1';
+        end loop ready_loop;
+      end loop monitor_loop;
+      --
+      -- get here when reset is asserted
+      wait until reset = '0';
+      --
+      -- process monitor now starts again from beginning
+    end process monitor;
+
+  end block verification_section;
+
+end architecture verifier;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst.vhd
new file mode 100644
index 0000000..bc7087c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtst.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxtst.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity dlx_test is
+
+end entity dlx_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstb.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstb.vhd
new file mode 100644
index 0000000..e5bb8b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstb.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxtstb.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration dlx_test_behavior of dlx_test is
+
+  for bench
+
+    for cg : clock_gen
+      use entity work.clock_gen(behavior)
+        generic map ( Tpw => 8 ns, Tps => 2 ns );
+    end for;
+
+    for mem : memory
+      use entity work.memory(preloaded)
+        generic map ( mem_size => 65536,
+                      Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
+    end for;
+
+    for proc : dlx
+      use entity work.dlx(behavior)
+        generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
+    end for;
+
+  end for;
+
+end configuration dlx_test_behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstr.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstr.vhd
new file mode 100644
index 0000000..2a590db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_dlxtstr.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_dlxtstr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+configuration dlx_test_rtl of dlx_test is
+
+  for bench
+
+    for cg : clock_gen
+      use entity work.clock_gen(behavior)
+        generic map ( Tpw => 8 ns, Tps => 2 ns );
+    end for;
+
+    for mem : memory
+      use entity work.memory(preloaded)
+        generic map ( mem_size => 65536,
+                      Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
+    end for;
+
+    for proc : dlx
+      use configuration work.dlx_rtl
+        generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
+    end for;
+
+  end for;  -- bench of dlx_test
+
+end configuration dlx_test_rtl;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire-b.vhd
new file mode 100644
index 0000000..39813af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire-b.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_ire-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+use work.dlx_instr.all;
+
+architecture behavior of ir_extender is
+
+  subtype upper_6_bits is std_logic_vector(0 to 5);
+  subtype upper_16_bits is std_logic_vector(0 to 15);
+
+begin
+
+  extender : process ( d, immed_en, immed_size_26, immed_unsigned ) is
+  begin
+    if To_bit(immed_en) = '1' then
+      if To_bit(immed_size_26) = '1' then  -- 26-bit immediate
+      	if To_bit(immed_unsigned) = '1' then
+	  q <= upper_6_bits'(others => '0') & d(6 to 31) after Tpd;
+	else
+	  q <= upper_6_bits'(others => d(6)) & d(6 to 31) after Tpd;
+	end if;
+      else -- 16-bit immediate
+      	if To_bit(immed_unsigned) = '1' then
+	  q <= upper_16_bits'(others => '0') & d(16 to 31) after Tpd;
+	else
+	  q <= upper_16_bits'(others => d(16)) & d(16 to 31) after Tpd;
+	end if;
+      end if;
+    else
+      q <= disabled_dlx_word after Tpd;
+    end if;
+  end process extender;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire.vhd
new file mode 100644
index 0000000..21d1a19
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_ire.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               use work.dlx_types.all;
+
+               entity ir_extender is
+                 generic ( Tpd : delay_length );
+                 port ( d : in dlx_word;
+                        q : out dlx_word;
+                        immed_size_26 : in std_logic;
+                        immed_unsigned : in std_logic;
+                        immed_en : in std_logic );
+               end entity ir_extender;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch-b.vhd
new file mode 100644
index 0000000..cbd72a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch-b.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_latch-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of latch is
+
+begin 
+
+  q <= d after Tpd when To_bit(latch_en) = '1';
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch.vhd
new file mode 100644
index 0000000..d8c287b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_latch.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_latch.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all;
+
+entity latch is
+  generic ( Tpd : delay_length );
+  port ( d : in dlx_word;
+         q : out dlx_word;
+         latch_en : in std_logic );
+end entity latch;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-fl.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-fl.vhd
new file mode 100644
index 0000000..60a8767
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-fl.vhd
@@ -0,0 +1,193 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_mem-fl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+use bv_utilities.bv_arithmetic.all,
+  std.textio.all;
+
+architecture file_loaded of memory is
+begin
+
+  mem_behavior : process is
+
+                           constant high_address : natural := mem_size - 1;
+
+                         type memory_array is
+                           array (natural range 0 to high_address / 4) of dlx_bv_word;
+
+                         variable mem : memory_array;
+
+                         variable byte_address, word_address : natural;
+                         variable write_access : boolean;
+
+                         procedure load is
+
+                           file binary_file : text open read_mode is load_file_name;
+                           variable L : line;
+                           variable ch : character;
+                           variable line_number : natural := 0;
+                           variable addr : natural;
+                           variable word : dlx_bv_word;
+
+                           procedure read_hex_natural ( L : inout line;  n : out natural ) is
+                             variable result : natural := 0;
+                           begin
+                             for i in 1 to 8 loop
+                               read(L, ch);
+                               if '0' <= ch and ch <= '9' then
+                                 result := result*16 + character'pos(ch) - character'pos('0');
+                               elsif 'A' <= ch and ch <= 'F' then
+                                 result := result*16 + character'pos(ch) - character'pos('A') + 10;
+                               elsif 'a' <= ch and ch <= 'f' then
+                                 result := result*16 + character'pos(ch) - character'pos('a') + 10;
+                               else
+                                 report "Format error in file " & load_file_name
+                                   & " on line " & integer'image(line_number) severity error;
+                               end if;
+                             end loop;
+                             n := result;
+                           end read_hex_natural;
+
+                           procedure read_hex_word ( L : inout line;  word : out dlx_bv_word ) is
+                             variable digit : natural;
+                             variable r : natural := 0;
+                           begin
+                             for i in 1 to 8 loop
+                               read(L, ch);
+                               if '0' <= ch and ch <= '9' then
+                                 digit := character'pos(ch) - character'pos('0');
+                               elsif 'A' <= ch and ch <= 'F' then
+                                 digit := character'pos(ch) - character'pos('A') + 10;
+                               elsif 'a' <= ch and ch <= 'f' then
+                                 digit := character'pos(ch) - character'pos('a') + 10;
+                               else
+                                 report "Format error in file " & load_file_name
+                                   & " on line " & integer'image(line_number)
+                                   severity error;
+                               end if;
+                               word(r to r+3) := natural_to_bv(digit, 4);
+                               r := r + 4;
+                             end loop;
+                           end read_hex_word;
+
+                         begin
+                           while not endfile(binary_file) loop
+                             readline(binary_file, L);
+                             line_number := line_number + 1;
+                             read_hex_natural(L, addr);
+                             read(L, ch);  -- the space between addr and data
+                             read_hex_word(L, word);
+                             mem(addr / 4) := word;
+                           end loop;
+                         end load;
+
+                         procedure do_write is
+                           subtype ls_2_bits is bit_vector(1 downto 0);
+                         begin
+                           case width is
+                             when dlx_mem_width_word =>
+                               mem(word_address) := to_bitvector(d);
+                             when dlx_mem_width_halfword =>
+                               if To_bit(a(1)) = '0' then  -- ms half word
+                                 mem(word_address)(0 to 15) := to_bitvector( d(0 to 15) );
+                               else  -- ls half word
+                                 mem(word_address)(16 to 31) := to_bitvector( d(16 to 31) );
+                               end if;
+                             when dlx_mem_width_byte =>
+                               case ls_2_bits'(To_bitvector(a(1 downto 0))) is
+                                 when b"00" =>
+                                   mem(word_address)(0 to 7) := to_bitvector( d(0 to 7) );
+                                 when b"01" =>
+                                   mem(word_address)(8 to 15) := to_bitvector( d(8 to 15) );
+                                 when b"10" =>
+                                   mem(word_address)(16 to 23) := to_bitvector( d(16 to 23) );
+                                 when b"11" =>
+                                   mem(word_address)(24 to 31) := to_bitvector( d(24 to 31) );
+                               end case;
+                             when others =>
+                               report "illegal width indicator in write" severity error;
+                           end case;
+                         end do_write;
+
+                         procedure do_read is
+                         begin
+                           d <= To_X01( mem(word_address) );
+                         end do_read;
+
+  begin
+    load;  -- read binary memory image into memory array
+    -- initialize outputs
+    d <= disabled_dlx_word;
+    ready <= '0';
+
+    -- process memory cycles
+    loop
+      -- wait for a command, valid on leading edge of phi2
+      wait on phi2 until rising_edge(phi2) and To_bit(mem_enable) = '1';
+
+      -- decode address and perform command if selected
+      byte_address := bv_to_natural(To_bitvector(a));
+      write_access := To_bit(write_enable) = '1';
+      if byte_address <= high_address then
+        word_address := byte_address / 4;
+        if write_access then -- write cycle
+          do_write;
+          wait for Tac_first;  -- write access time, 1st cycle
+        else -- read cycle
+          wait for Tac_first;  -- read access time, 1st cycle
+          do_read;
+        end if;
+        -- ready synchronous with phi2
+        wait until rising_edge(phi2);
+        ready <= '1' after Tpd_clk_out;
+        wait until falling_edge(phi2);
+        ready <= '0' after Tpd_clk_out;
+        --  do subsequent cycles in burst
+        while To_bit(burst) = '1' loop
+          word_address := (word_address + 1) mod (mem_size / 4);
+          wait until rising_edge(phi2);
+          if write_access then -- write cycle
+            do_write;
+            wait for Tac_burst;  -- write access time, burst cycle
+          else -- read cycle
+            wait for Tac_burst;  -- read access time, burst cycle
+            do_read;
+          end if;
+          -- ready synchronous with phi2
+          wait until rising_edge(phi2);
+          ready <= '1' after Tpd_clk_out;
+          wait until falling_edge(phi2);
+          ready <= '0' after Tpd_clk_out;
+        end loop;
+        if not write_access then  -- was read
+          d <= disabled_dlx_word after Tpd_clk_out;
+        end if;
+      end if;
+    end loop;
+  end process mem_behavior;
+
+end architecture file_loaded;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-pl.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-pl.vhd
new file mode 100644
index 0000000..5322a8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem-pl.vhd
@@ -0,0 +1,140 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_mem-pl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+use bv_utilities.bv_arithmetic.all;
+
+architecture preloaded of memory is
+
+begin 
+
+  mem_behavior : process is
+
+                           constant high_address : natural := mem_size - 1;
+
+                         type memory_array is
+                           array (natural range 0 to high_address / 4) of dlx_bv_word;
+
+                         variable mem : memory_array
+                           := ( X"20020000",	 --           addi  r2, r0, 0
+                                X"ac020018",  -- loop:     sw    counter(r0), r2
+                                X"20420001",  --           addi  r2, r2, 1
+                                X"6441000a",  --           snei  r1, r2, 10
+                                X"1420fff0",  --           bnez  r1, loop
+                                X"44000000",  --           trap  0
+                                X"00000000",  -- counter:  .word 0
+                                others => X"00000000" );
+
+                         variable byte_address, word_address : natural;
+                         variable write_access : boolean;
+
+
+                         procedure do_write is
+                           subtype ls_2_bits is bit_vector(1 downto 0);
+                         begin
+                           case width is
+                             when dlx_mem_width_word =>
+                               mem(word_address) := to_bitvector(d);
+                             when dlx_mem_width_halfword =>
+                               if To_bit(a(1)) = '0' then  -- ms half word
+                                 mem(word_address)(0 to 15) := to_bitvector( d(0 to 15) );
+                               else  -- ls half word
+                                 mem(word_address)(16 to 31) := to_bitvector( d(16 to 31) );
+                               end if;
+                             when dlx_mem_width_byte =>
+                               case ls_2_bits'(To_bitvector(a(1 downto 0))) is
+                                 when b"00" =>
+                                   mem(word_address)(0 to 7) := to_bitvector( d(0 to 7) );
+                                 when b"01" =>
+                                   mem(word_address)(8 to 15) := to_bitvector( d(8 to 15) );
+                                 when b"10" =>
+                                   mem(word_address)(16 to 23) := to_bitvector( d(16 to 23) );
+                                 when b"11" =>
+                                   mem(word_address)(24 to 31) := to_bitvector( d(24 to 31) );
+                               end case;
+                             when others =>
+                               report "illegal width indicator in write" severity error;
+                           end case;
+                         end do_write;
+
+                         procedure do_read is
+                         begin
+                           d <= To_X01( mem(word_address) );
+                         end do_read;
+
+  begin
+    -- initialize outputs
+    d <= disabled_dlx_word;
+    ready <= '0';
+
+    -- process memory cycles
+    loop
+      -- wait for a command, valid on leading edge of phi2
+      wait on phi2 until rising_edge(phi2) and To_bit(mem_enable) = '1';
+
+      -- decode address and perform command if selected
+      byte_address := bv_to_natural(To_bitvector(a));
+      write_access := To_bit(write_enable) = '1';
+      if byte_address <= high_address then
+        word_address := byte_address / 4;
+        if write_access then -- write cycle
+          do_write;
+          wait for Tac_first;  -- write access time, 1st cycle
+        else -- read cycle
+          wait for Tac_first;  -- read access time, 1st cycle
+          do_read;
+        end if;
+        -- ready synchronous with phi2
+        wait until rising_edge(phi2);
+        ready <= '1' after Tpd_clk_out;
+        wait until falling_edge(phi2);
+        ready <= '0' after Tpd_clk_out;
+        --  do subsequent cycles in burst
+        while To_bit(burst) = '1' loop
+	  word_address := (word_address + 1) mod (mem_size / 4);
+          wait until rising_edge(phi2);
+          if write_access then -- write cycle
+            do_write;
+            wait for Tac_burst;  -- write access time, burst cycle
+          else -- read cycle
+            wait for Tac_burst;  -- read access time, burst cycle
+            do_read;
+          end if;
+          -- ready synchronous with phi2
+          wait until rising_edge(phi2);
+          ready <= '1' after Tpd_clk_out;
+          wait until falling_edge(phi2);
+          ready <= '0' after Tpd_clk_out;
+        end loop;
+        if not write_access then  -- was read
+          d <= disabled_dlx_word after Tpd_clk_out;
+        end if;
+      end if;
+    end loop;
+  end process mem_behavior;
+
+end architecture preloaded;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem.vhd
new file mode 100644
index 0000000..d69c778
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mem.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_mem.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee. std_logic_1164.all;
+
+               use work.dlx_types.all;
+
+               entity memory is
+
+                 generic ( mem_size : positive;
+                           Tac_first : delay_length;
+                           Tac_burst : delay_length;
+                           Tpd_clk_out : delay_length;
+                           load_file_name : string := "dlx.out" );
+
+                 port ( phi1, phi2 : in std_logic;
+                        a : in dlx_address;
+                        d : inout dlx_word;
+                        width : in dlx_mem_width;
+                        write_enable : in std_logic;
+                        burst : in std_logic := '0';
+                        mem_enable : in std_logic;
+                        ready : out std_logic );
+
+               end entity memory;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2-b.vhd
new file mode 100644
index 0000000..39d13b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2-b.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_mux2-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of mux2 is
+
+begin
+
+  with To_bit(sel) select
+    y <=  i0 after Tpd when '0',
+    i1 after Tpd when '1';
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2.vhd
new file mode 100644
index 0000000..f690795
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_mux2.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_mux2.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               use work.dlx_types.all;
+
+               entity mux2 is
+                 generic ( Tpd : delay_length );
+                 port ( i0, i1 : in dlx_word;
+                        y : out dlx_word;
+                        sel : in std_logic );
+               end mux2;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm-b.vhd
new file mode 100644
index 0000000..551b9eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm-b.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regm-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of reg_multiple_out is
+
+begin
+
+  reg: process ( d, latch_en, out_en ) is
+
+                                         variable latched_value : dlx_word;
+
+  begin
+    if To_bit(latch_en) = '1' then
+      latched_value := To_X01(d);
+    end if;
+    for index in out_en'range loop
+      if To_bit(out_en(index)) = '1' then
+	q(index) <= latched_value after Tpd;
+      else
+	q(index) <= disabled_dlx_word after Tpd;
+      end if;
+    end loop;
+  end process reg;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm.vhd
new file mode 100644
index 0000000..790fe50
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regm.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regm.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all;
+
+entity reg_multiple_out is
+  generic ( num_outputs : positive;
+            Tpd : delay_length );
+  port ( d : in dlx_word;
+         q : out dlx_word_array(1 to num_outputs);
+         latch_en : in std_logic;
+         out_en : in std_logic_vector(1 to num_outputs) );
+end entity reg_multiple_out;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp-b.vhd
new file mode 100644
index 0000000..9dfc31d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp-b.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regmp-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of reg_multiple_plus_one_out is
+
+begin
+
+  reg: process ( d, latch_en, out_en ) is
+
+                                         variable latched_value : dlx_word;
+
+  begin
+    if To_bit(latch_en) = '1' then
+      latched_value := To_X01(d);
+    end if;
+    q0 <= latched_value after Tpd;
+    for index in out_en'range loop
+      if To_bit(out_en(index)) = '1' then
+	q(index) <= latched_value after Tpd;
+      else
+	q(index) <= disabled_dlx_word after Tpd;
+      end if;
+    end loop;
+  end process reg;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp.vhd
new file mode 100644
index 0000000..d1ccb05
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmp.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regmp.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all;
+
+entity reg_multiple_plus_one_out is
+  generic ( num_outputs : positive;
+            Tpd : delay_length );
+  port ( d : in dlx_word;
+         q0 : out dlx_word;
+         q : out dlx_word_array(1 to num_outputs);
+         latch_en : in std_logic;
+         out_en : in std_logic_vector(1 to num_outputs) );
+end entity reg_multiple_plus_one_out;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr-b.vhd
new file mode 100644
index 0000000..6400914
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr-b.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regmpr-b.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of reg_multiple_plus_one_out_reset is
+
+begin
+
+  reg: process ( d, latch_en, out_en, reset )
+    is
+
+      variable latched_value : dlx_word;
+
+  begin
+    if To_bit(reset) = '1' then
+      latched_value := X"0000_0000";
+    elsif To_bit(latch_en) = '1' then
+      latched_value := To_X01(d);
+    end if;
+    q0 <= latched_value after Tpd;
+    for index in out_en'range loop
+      if To_bit(out_en(index)) = '1' then
+	q(index) <= latched_value after Tpd;
+      else
+	q(index) <= disabled_dlx_word after Tpd;
+      end if;
+    end loop;
+  end process reg;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr.vhd
new file mode 100644
index 0000000..1b21ca7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_regmpr.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_regmpr.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.dlx_types.all;
+
+entity reg_multiple_plus_one_out_reset is
+  generic ( num_outputs : positive;
+            Tpd : delay_length );
+  port ( d : in dlx_word;
+         q0 : out dlx_word;
+         q : out dlx_word_array(1 to num_outputs);
+         latch_en : in std_logic;
+         out_en : in std_logic_vector(1 to num_outputs);
+         reset : in std_logic );
+end entity reg_multiple_plus_one_out_reset;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf-b.vhd
new file mode 100644
index 0000000..c80b6b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf-b.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_rf-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+architecture behavior of reg_file is
+
+begin
+
+  reg: process ( a1, a2, a3, d3, write_en ) is
+
+                                              use work.dlx_instr.reg_index,
+                                              bv_utilities.bv_arithmetic.bv_to_natural;
+
+                                            constant all_zeros : dlx_word := X"0000_0000";
+
+                                            type register_array is array (reg_index range 1 to 31) of dlx_word;
+
+                                            variable register_file : register_array;
+                                            variable reg_index1, reg_index2, reg_index3 : reg_index;
+
+  begin
+    -- do write first if enabled
+    --
+    if To_bit(write_en) = '1' then
+      reg_index3 := bv_to_natural(To_bitvector(a3));
+      if reg_index3 /= 0 then
+        register_file(reg_index3) := To_X01(d3);
+      end if;
+    end if;
+    --
+    -- read port 1
+    --
+    reg_index1 := bv_to_natural(To_bitvector(a1));
+    if reg_index1 /= 0 then
+      q1 <= register_file(reg_index1) after Tac;
+    else
+      q1 <= all_zeros after Tac;
+    end if;
+    --
+    -- read port 2
+    --
+    reg_index2 := bv_to_natural(To_bitvector(a2));
+    if reg_index2 /= 0 then
+      q2 <= register_file(reg_index2) after Tac;
+    else
+      q2 <= all_zeros after Tac;
+    end if;
+  end process reg;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf.vhd
new file mode 100644
index 0000000..fa29d4b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rf.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_rf.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               use work.dlx_types.all,
+                 work.reg_file_types.all;
+
+               entity reg_file is
+                 generic ( Tac : delay_length );
+                 port ( a1 : in reg_file_addr;
+                        q1 : out dlx_word;
+                        a2 : in reg_file_addr;
+                        q2 : out dlx_word;
+                        a3 : in reg_file_addr;
+                        d3 : in dlx_word;
+                        write_en : in std_logic );
+               end entity reg_file;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rft.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rft.vhd
new file mode 100644
index 0000000..ba29d11
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_15_rft.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_15_rft.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--use work.dlx_instr.dlx_reg_addr;
+use work.dlx_instr.all;
+
+package reg_file_types is
+
+  subtype reg_file_addr is std_logic_vector(dlx_reg_addr'range);
+
+end package reg_file_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_01.vhd
new file mode 100644
index 0000000..e07996e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_01.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_01 is
+
+end entity ch_16_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_01 is
+
+  function pulled_up ( drivers : bit_vector ) return bit is
+  begin
+    for index in drivers'range loop
+      if drivers(index) = '0' then
+        return '0';
+      end if;
+    end loop;
+    return '1';
+  end function pulled_up;
+
+  type state_type is (init_state, state1, state2, state3);
+  type state_vector is array (integer range <>) of state_type;
+
+  function resolve_state ( drivers : state_vector ) return state_type is
+  begin
+    return drivers(drivers'left);
+  end function resolve_state;
+
+
+  -- code from book:
+
+  signal interrupt_request : pulled_up bit bus;
+
+  signal stored_state : resolve_state state_type register := init_state;
+
+  -- end of code from book
+
+begin
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_02.vhd
new file mode 100644
index 0000000..d080b4f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_02.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_02 is
+
+end entity ch_16_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_02 is
+
+  -- code from book:
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word;
+
+  signal s : resolve_words word bus;
+
+  -- end of code from book
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  constant T_delay : delay_length := 2 ns;
+
+begin
+
+
+  process is
+  begin
+
+    -- code from book (should fail)
+
+    s(0 to 15) <= X"003F" after T_delay;
+    s(16 to 31) <= null after T_delay;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_03.vhd
new file mode 100644
index 0000000..5896cd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_03.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_03 is
+
+end entity ch_16_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_03 is
+
+  function pulled_up ( drivers : bit_vector ) return bit is
+  begin
+    for index in drivers'range loop
+      if drivers(index) = '0' then
+        return '0';
+      end if;
+    end loop;
+    return '1';
+  end function pulled_up;
+
+  signal s : pulled_up bit bus;
+
+begin
+
+
+  process is
+  begin
+
+    s <= '1' after 11 ns, '0' after 16 ns, '1' after 18 ns,
+         null after 19 ns, '0' after 25 ns;
+    wait for 10 ns;
+
+    -- code from book:
+
+    s <= reject 3 ns inertial null after 10 ns;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_04.vhd
new file mode 100644
index 0000000..6bff359
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_04.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_04 is
+
+end entity ch_16_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_04 is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  subtype resolved_word is resolve_words word;
+
+  -- code from book:
+
+  signal memory_data_bus : resolved_word bus;
+  disconnect memory_data_bus : resolved_word after 3 ns;
+
+  -- end of code from book
+
+  signal mem_sel, mem_write : boolean;
+  signal cache_data_bus : word;
+
+begin
+
+
+  -- code from book:
+
+  mem_write_buffer : block (mem_sel and mem_write) is
+  begin
+    memory_data_bus <=
+      guarded reject 2 ns inertial cache_data_bus after 4 ns;
+  end block mem_write_buffer;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    cache_data_bus <= X"DDDDDDDD";
+    wait for 10 ns;
+    mem_sel <= true;  mem_write <= true;
+    wait for 10 ns;
+    cache_data_bus <= X"AAAAAAAA";
+    wait for 10 ns;
+    mem_sel <= false;  mem_write <= false;
+    wait for 10 ns;
+    cache_data_bus <= X"11111111";
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd
new file mode 100644
index 0000000..4303bd9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_05.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_05 is
+
+end entity ch_16_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_05 is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  subtype resolved_word is resolve_words word;
+
+  -- code from book:
+
+  signal source_bus_1, source_bus_2 : resolved_word bus;
+  signal address_bus : resolved_word bus;
+
+  disconnect all : resolved_word after 2 ns;
+
+  -- end of code from book
+
+  signal s : word;
+  signal g : boolean;
+
+begin
+
+
+  b : block (g) is
+  begin
+    source_bus_1 <= guarded s after 4 ns;
+    source_bus_2 <= guarded s after 4 ns;
+    address_bus <= guarded s after 4 ns;
+  end block b;
+
+  stimulus : process is
+  begin
+    s <= X"DDDDDDDD";
+    wait for 10 ns;
+    g <= true;
+    wait for 10 ns;
+    s <= X"AAAAAAAA";
+    wait for 10 ns;
+    g <= false;
+    wait for 10 ns;
+    s <= X"11111111";
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_06.vhd
new file mode 100644
index 0000000..29d4158
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_ch_16_06.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_ch_16_06.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_16_06 is
+
+end entity ch_16_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_16_06 is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  subtype resolved_word is resolve_words word;
+
+  signal source_bus_1, source_bus_2 : resolved_word bus;
+  signal address_bus : resolved_word bus;
+
+  -- code from book:
+
+  disconnect address_bus : resolved_word after 3 ns;
+
+  disconnect others : resolved_word after 2 ns;
+
+  -- end of code from book
+
+  signal s : word;
+  signal g : boolean;
+
+begin
+
+
+  b : block (g) is
+  begin
+    source_bus_1 <= guarded s after 4 ns;
+    source_bus_2 <= guarded s after 4 ns;
+    address_bus <= guarded s after 4 ns;
+  end block b;
+
+  stimulus : process is
+  begin
+    s <= X"DDDDDDDD";
+    wait for 10 ns;
+    g <= true;
+    wait for 10 ns;
+    s <= X"AAAAAAAA";
+    wait for 10 ns;
+    g <= false;
+    wait for 10 ns;
+    s <= X"11111111";
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_01.vhd
new file mode 100644
index 0000000..f5a3631
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_01.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+architecture top_level of computer_system is
+
+  function resolve_bits ( bits : bit_vector ) return bit is
+    variable result : bit := '0';
+  begin
+    for index in bits'range loop
+      result := result or bits(index);
+      exit when result = '1';
+    end loop;
+    return result;
+  end function resolve_bits;
+
+  signal write_en : resolve_bits bit bus;
+  -- . . .
+
+  -- not in book
+  constant Tpd : delay_length := 2 ns;
+  signal clock, hold_req : bit := '0';
+  -- end not in book
+
+begin
+
+  CPU : process is
+                  -- . . .
+  begin
+    write_en <= '0' after Tpd;
+    -- . . .
+    loop
+      wait until clock = '1';
+      if hold_req = '1' then
+        write_en <= null after Tpd;
+        wait on clock until clock = '1' and hold_req = '0';
+        write_en <= '0' after Tpd;
+      end if;
+      -- . . .
+    end loop;
+  end process CPU;
+
+  -- . . .
+
+  -- not in book
+
+  clock_gen : clock <= '1' after 5 ns, '0' after 10 ns when clock = '0';
+
+  stimulus : hold_req <= '1' after 40 ns, '0' after 80 ns;
+
+  process is
+  begin
+    write_en <= null, '1' after 50 ns, '0' after 60 ns, null after 70 ns;
+    wait;
+  end process;
+
+  -- end not in book
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_02.vhd
new file mode 100644
index 0000000..ca84bc1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_02.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity processor is
+end entity processor;
+
+
+
+-- code from book
+
+architecture rtl of processor is
+
+  subtype word is bit_vector(0 to 31);
+  type word_vector is array (natural range <>) of word;
+
+  function resolve_unique ( drivers : word_vector ) return word is
+  begin
+    return drivers(drivers'left);
+  end function resolve_unique;
+
+  signal source1, source2 : resolve_unique word register;
+  -- . . .
+
+  -- not in book
+
+  type alu_op_type is (pass1, pass2, add, subtract);
+
+  procedure perform_alu_op ( signal alu_opcode : in alu_op_type;
+			     signal source1, source2 : in word;
+			     signal destination : out word;
+			     constant ignored : in integer := 0 ) is
+  begin
+    null;
+  end procedure perform_alu_op;
+
+  signal phase1, source1_reg_out_en,other_signal : bit;
+  signal alu_opcode : alu_op_type;
+  signal destination : word;
+
+  -- end not in book
+
+begin
+
+  source1_reg : process (phase1, source1_reg_out_en, -- . . .) is
+                         -- not in book
+                         other_signal) is
+                                         -- end not in book
+                                         variable stored_value : word;
+  begin
+    -- . . .
+    if source1_reg_out_en = '1' and phase1 = '1' then
+      source1 <= stored_value;
+      -- not in book
+      stored_value := not stored_value;
+      -- end not in book
+    else
+      source1 <= null;
+    end if;
+  end process source1_reg;
+
+  alu : perform_alu_op ( alu_opcode, source1, source2, destination, -- . . . );
+                         -- not in book
+                         open );
+  -- end not in book
+
+  -- . . .
+
+  -- not in book
+
+  process is
+  begin
+    wait for 10 ns;
+    source1_reg_out_en <= '1';
+    phase1 <= '1', '0' after 10 ns;
+    wait for 20 ns;
+    source1_reg_out_en <= '1';
+    phase1 <= '1', '0' after 10 ns;
+    wait;
+  end process;
+
+  -- end not in book
+
+end architecture rtl;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_04.vhd
new file mode 100644
index 0000000..52deb9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_04.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package fg_16_04 is
+
+  -- code from book (in text)
+
+  subtype byte is bit_vector(0 to 7);
+  type byte_array is array (integer range <>) of byte;
+  function resolve ( bytes : byte_array ) return byte;
+  subtype resolved_byte is resolve byte;
+
+  -- end code from book
+
+end package fg_16_04;
+
+
+package body fg_16_04 is
+
+  -- code from book
+
+  function resolve ( bytes : byte_array ) return byte is
+    variable result : byte := b"0000_0000";
+  begin
+    for index in bytes'range loop
+      result := result or bytes(index);
+    end loop;
+    return result;
+  end function resolve;
+
+  -- end code from book
+
+end package body fg_16_04;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_05.vhd
new file mode 100644
index 0000000..d857953
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_05.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+use work.fg_16_04.all;
+
+-- code from book (in text)
+
+entity tri_state_reg is
+  port ( d : in resolved_byte;
+         q : out resolved_byte bus;
+         clock, out_enable : in bit );
+end entity tri_state_reg;
+
+-- end code from book
+
+
+
+-- code from book
+
+architecture behavioral of tri_state_reg is
+begin
+
+  reg_behavior : process (d, clock, out_enable) is
+                                                  variable stored_byte : byte;
+  begin
+    if clock'event and clock = '1' then
+      stored_byte := d;
+    end if;
+    if out_enable = '1' then
+      q <= stored_byte;
+    else
+      q <= null;
+    end if;
+  end process reg_behavior;
+
+end architecture behavioral;
+
+-- end code from book
+
+
+
+use work.fg_16_04.all;
+
+entity fg_16_05 is
+end entity fg_16_05;
+
+
+architecture test of fg_16_05 is
+
+  signal d1, d2, q : resolved_byte := X"00";
+  signal clk1, clk2, oe1, oe2 : bit := '0';
+
+begin
+
+  dut1 : entity work.tri_state_reg(behavioral)
+    port map ( d => d1, q => q, clock => clk1, out_enable => oe1 );
+
+  dut2 : entity work.tri_state_reg(behavioral)
+    port map ( d => d2, q => q, clock => clk2, out_enable => oe2 );
+
+  stimulus : process is
+  begin
+    d1 <= X"11";  clk1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    oe1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    d2 <= X"21";  clk2 <= '1', '0' after 5 ns;  wait for 10 ns;
+    oe2 <= '1', '0' after 5 ns;  wait for 10 ns;
+    oe1 <= '1', '0' after 5 ns;
+    oe2 <= '1', '0' after 5 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_06.vhd
new file mode 100644
index 0000000..ba7a774
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_06.vhd
@@ -0,0 +1,105 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity data_logger is
+end entity data_logger;
+
+
+-- code from book
+
+architecture high_level of data_logger is
+
+  subtype byte is bit_vector(7 downto 0);
+
+  type byte_array is array (integer range <>) of byte;
+
+  function resolver ( bytes : byte_array ) return byte is
+  begin
+    if bytes'length > 0 then
+      return bytes( bytes'left );
+    else
+      return X"00";
+    end if;
+  end function resolver;
+
+  subtype resolved_byte is resolver byte;
+
+  procedure reg ( signal clock, out_enable : in bit;
+                  signal d : in byte;
+                  -- workaround for MTI bugs mt027/mt028
+                  -- signal q : out resolved_byte ) is
+                  signal q : out resolved_byte bus ) is
+    -- end workaround
+    variable stored_byte : byte;
+  begin
+    loop
+      if clock = '1' then
+        stored_byte := d;
+      end if;
+      if out_enable = '1' then
+        q <= stored_byte;
+      else
+        q <= null;
+      end if;
+      wait on clock, out_enable, d;
+    end loop;
+  end procedure reg;
+
+  signal data_bus : resolved_byte bus;
+  -- . . .
+
+  -- not in book
+  signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0';
+  signal port_a, port_b : byte := X"00";
+  -- end not in book
+
+begin
+
+  a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus);
+
+  b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus);
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    port_a <= X"11";  a_reg_clk <= '1', '0' after 5 ns;  wait for 10 ns;
+    a_reg_read <= '1', '0' after 5 ns;  wait for 10 ns;
+    port_b <= X"21";  b_reg_clk <= '1', '0' after 5 ns;  wait for 10 ns;
+    b_reg_read <= '1', '0' after 5 ns;  wait for 10 ns;
+    a_reg_read <= '1', '0' after 5 ns;
+    b_reg_read <= '1', '0' after 5 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture high_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_07.vhd
new file mode 100644
index 0000000..f7388b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_07.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_16_07 is
+               end entity fg_16_07;
+
+
+               architecture test of fg_16_07 is
+
+                 constant reg0 : std_logic_vector(7 downto 0) := "00000000";
+                 constant reg1 : std_logic_vector(7 downto 0) := "11111111";
+                 signal dbus : std_logic_vector(7 downto 0);
+                 signal reg_sel, read, reg_addr : X01 := '0';
+
+               begin
+
+                 -- code from book
+
+                 reg_read_selector : block (reg_sel = '1' and read = '1') is
+                 begin
+                   dbus <= reg0 when guard and reg_addr = '0' else
+                           reg1 when guard and reg_addr = '1' else
+                           "ZZZZZZZZ";
+                 end block reg_read_selector;
+
+                 -- end code from book
+
+                 stimulus : process is
+                 begin
+                   reg_sel <= '1';  wait for 10 ns;
+                   read <= '1', '0' after 5 ns;  wait for 10 ns;
+                   reg_sel <= '0';  wait for 10 ns;
+                   read <= '1', '0' after 5 ns;  wait for 10 ns;
+                   reg_addr <= '1';  wait for 10 ns;
+                   reg_sel <= '1';  wait for 10 ns;
+                   read <= '1', '0' after 5 ns;  wait for 10 ns;
+
+                   wait;
+                 end process stimulus;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_08.vhd
new file mode 100644
index 0000000..fed1762
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_08.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity processor_node is
+end entity processor_node;
+
+
+-- code from book
+
+architecture dataflow of processor_node is
+
+  -- not in book
+
+  subtype word is bit_vector(31 downto 0);
+  type word_vector is array (natural range <>) of word;
+
+  function resolve_unique ( drivers : word_vector ) return word is
+  begin
+    if drivers'length > 0 then
+      return drivers(drivers'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_unique;
+
+  -- end not in book
+
+  signal address_bus : resolve_unique word bus;
+  -- . . .
+
+  -- not in book
+  signal cache_miss, dirty, replace_section,
+    snoop_hit, flag_update : bit := '0';
+  constant tag_section0 : bit_vector(11 downto 0) := X"000";
+  constant tag_section1 : bit_vector(11 downto 0) := X"001";
+  constant set_index : bit_vector(15 downto 0) := X"6666";
+  constant snoop_address : word := X"88888888";
+  -- end not in book
+
+begin
+
+  cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is
+  begin
+    address_bus <= guarded
+                   tag_section0 & set_index & B"0000" when replace_section = '0' else
+                   tag_section1 & set_index & B"0000";
+  end block cache_to_address_buffer;
+
+  snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is
+  begin
+    address_bus <= guarded snoop_address(31 downto 4) & B"0000";
+  end block snoop_to_address_buffer;
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    dirty <= '0';  cache_miss <= '1', '0' after 5 ns;  wait for 10 ns;
+    dirty <= '1';  cache_miss <= '1', '0' after 5 ns;  wait for 10 ns;
+    replace_section <= '1';
+    cache_miss <= '1', '0' after 5 ns;  wait for 10 ns;
+    flag_update <= '0'; snoop_hit <= '1', '0' after 5 ns;  wait for 10 ns;
+    flag_update <= '1'; snoop_hit <= '1', '0' after 5 ns;  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture dataflow;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_09.vhd
new file mode 100644
index 0000000..907e8ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_09.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity latch is
+  generic ( width : positive );
+  port ( enable : in bit;
+         d : in bit_vector(0 to width - 1);
+         q : out bit_vector(0 to width - 1) );
+end entity latch;
+
+--------------------------------------------------
+
+architecture behavioral of latch is
+begin
+
+  transfer_control : block ( enable = '1' ) is
+  begin
+    q <= guarded d;
+  end block transfer_control;
+
+end architecture behavioral;
+
+
+-- not in book
+
+entity fg_16_09 is
+end entity fg_16_09;
+
+
+architecture test of fg_16_09 is
+
+  signal enable : bit := '0';
+  signal d, q : bit_vector(0 to 7);
+
+begin
+
+  dut : entity work.latch(behavioral)
+    generic map ( width => 8 )
+    port map ( enable => enable, d => d, q => q );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    d <= X"11";  wait for 10 ns;
+    enable <= '1';  wait for 10 ns;
+    d <= X"AA";  wait for 10 ns;
+    enable <= '0';  wait for 10 ns;
+    d <= X"00";  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_10.vhd
new file mode 100644
index 0000000..25866f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_10.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity computer_system is
+end entity computer_system;
+
+
+-- code from book
+
+architecture abstract of computer_system is
+
+  -- not in book
+
+  subtype word is bit_vector(31 downto 0);
+  type word_vector is array (natural range <>) of word;
+
+  function resolve_word ( drivers : word_vector ) return word is
+  begin
+    if drivers'length > 0 then
+      return drivers(drivers'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_word;
+
+  -- end not in book
+
+  -- . . .
+
+  signal address_bus : resolve_word word bus;
+  signal hold_req : bit;
+  -- . . .
+
+  -- not in book
+  signal clk : bit := '0';
+  -- end not in book
+
+begin
+
+  cpu : block is
+
+                signal guard : boolean := false;
+              signal cpu_internal_address : word;
+              -- . . .
+
+  begin
+
+    cpu_address_driver:
+      address_bus <= guarded cpu_internal_address;
+
+    -- . . .    -- other bus drivers
+
+    controller : process is
+                           -- . . .
+    begin
+      -- . . .
+      -- . . .    -- determine when to disable cpu bus drivers
+      guard <= false;
+      wait on clk until hold_req = '0' and clk = '1';
+      guard <= true;  -- re-enable cpu bus drivers
+      -- . . .
+      -- not in book
+      wait until clk = '1';
+      -- end not in book
+    end process controller;
+
+    -- . . .    -- cpu datapath processes
+
+    -- not in book
+    cpu_internal_address <= X"11111111";
+    -- end not in book
+
+  end block cpu;
+
+  -- . . .    -- blocks for DMA and other modules
+
+  -- not in book
+  clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+  -- end not in book
+
+end architecture abstract;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_12.vhd
new file mode 100644
index 0000000..ba0d4a0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_12.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_12.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity counter is
+
+  generic ( tipd_reset,                   -- input prop delay on reset
+            tipd_clk,                     -- input prop delay on clk
+            topd_q : delay_length;        -- output prop delay on q
+            tsetup_reset,                 -- setup: reset before clk
+            thold_reset : delay_length ); -- hold time: reset after clk
+
+  port ( reset,                           -- synchronous reset input
+         clk : in bit;                    -- edge triggered clock input
+         q : out bit_vector );            -- counter output
+
+end entity counter;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_13.vhd
new file mode 100644
index 0000000..df8cbb0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_13.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture detailed_timing of counter is
+
+  signal reset_ipd,                   -- data input port delayed
+    clk_ipd : bit;               -- clock input port delayed
+  signal q_zd : bit_vector(q'range);  -- q output with zero delay
+
+begin
+
+  input_port_delay : block is
+  begin
+    reset_ipd <= reset after tipd_reset;
+    clk_ipd <= clk after tipd_clk;
+  end block input_port_delay;
+
+  functionality : block is
+
+                          function increment ( bv : bit_vector ) return bit_vector is
+    variable result : bit_vector(bv'range) := bv;
+    variable carry : bit := '1';
+  begin
+    for index in result'reverse_range loop
+      result(index) := bv(index) xor carry;
+      carry :=  bv(index) and carry;
+      exit when carry = '0';
+    end loop;
+    return result;
+  end function increment;
+
+  signal next_count : bit_vector(q'range);
+
+  begin
+    next_count <= increment(q_zd) when reset_ipd = '0' else
+                  (others => '0');
+    q_zd <= next_count when clk_ipd = '1' and clk_ipd'event;
+  end block functionality;
+
+  output_port_delay : block is
+  begin
+    q <= q_zd after topd_q;
+  end block output_port_delay;
+
+  timing_checks : block is
+  begin
+    -- check setup time: reset before clk
+    -- . . .
+    -- check hold time: reset after clk
+    -- . . .
+  end block timing_checks;
+
+end architecture detailed_timing;
+
+
+-- not in book
+
+entity fg_16_13 is
+end entity fg_16_13;
+
+
+architecture test of fg_16_13 is
+
+  signal reset, clk : bit := '0';
+  signal q : bit_vector(3 downto 0);
+
+begin
+
+  dut : entity work.counter(detailed_timing)
+    generic map ( tipd_reset => 2 ns,
+                  tipd_clk => 3 ns,
+                  topd_q => 4 ns,
+                  tsetup_reset => 3 ns,
+                  thold_reset => 1 ns )
+    port map ( reset => reset, clk => clk, q => q );
+
+  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+
+  reset <= '1' after 62 ns, '0' after 106 ns;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_14.vhd
new file mode 100644
index 0000000..9b9c543
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_14.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_14.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity example_entity is
+end entity example_entity;
+
+-- end not in book
+
+
+architecture contrived of example_entity is
+
+  constant sig_width : positive := 16;
+  signal s1, s2, s3 : bit_vector (0 to sig_width - 1);
+  signal sel : bit;
+  -- . . .
+
+begin
+
+  mux : block is
+                generic ( width : positive );
+              generic map ( width => sig_width );
+              port ( d0, d1 : in bit_vector(0 to width - 1);
+                     y : out bit_vector(0 to width - 1);
+                     sel : in bit);
+              port map ( d0 => s1, d1=> s2, y => s3, sel => sel );
+
+              constant zero : bit_vector(0 to width - 1) := ( others => '0' );
+              signal gated_d0, gated_d1 : bit_vector(0 to width - 1);
+
+  begin
+    gated_d0 <= d0 when sel = '0' else zero;
+    gated_d1 <= d1 when sel = '1' else zero;
+    y <= gated_d0 or gated_d1;
+  end block mux;
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    s1 <= X"1111";  s2 <= X"2222";  sel <= '0';  wait for 10 ns;
+    s1 <= X"0101";  wait for 10 ns;
+    s2 <= X"0202";  wait for 10 ns;
+    sel <= '1';  wait for 10 ns;
+    s1 <= X"0001";  wait for 10 ns;
+    s2 <= X"0002";  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture contrived;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_15.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_15.vhd
new file mode 100644
index 0000000..d92ac85
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_15.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity circuit is
+  generic ( inpad_delay, outpad_delay : delay_length );
+  port ( in1, in2, in3 : in bit;  out1, out2 : out bit );
+end entity circuit;
+
+--------------------------------------------------
+
+architecture with_pad_delays of circuit is
+
+  component subcircuit is
+                         port ( a, b : in bit;  y1, y2 : out bit );
+  end component subcircuit;
+
+  signal delayed_in1, delayed_in2, delayed_in3 : bit;
+  signal undelayed_out1, undelayed_out2 : bit;
+
+begin
+
+  input_delays : block is
+  begin
+    delayed_in1 <= in1 after inpad_delay;
+    delayed_in2 <= in2 after inpad_delay;
+    delayed_in3 <= in3 after inpad_delay;
+  end block input_delays;
+
+  functionality : block is
+                          signal intermediate : bit;
+  begin
+    cell1 : component subcircuit
+      port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate );
+    cell2 : component subcircuit
+      port map ( intermediate, delayed_in3, undelayed_out2, open );
+  end block functionality;
+
+  output_delays : block is
+  begin
+    out1 <= undelayed_out1 after outpad_delay;
+    out2 <= undelayed_out2 after outpad_delay;
+  end block output_delays;
+
+end architecture with_pad_delays;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_16.vhd
new file mode 100644
index 0000000..5efc7f5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_16.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_16_fg_16_16.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity real_subcircuit is
+  port ( a, b : in bit;  y1, y2 : out bit );
+end entity real_subcircuit;
+
+
+architecture basic of real_subcircuit is
+begin
+  y1 <= a and b after 10 ns;
+  y2 <= a nand b after 10 ns;
+end architecture basic;
+
+-- code from book
+
+configuration full of circuit is
+
+  for with_pad_delays  -- configure the architecture
+
+    for functionality    -- configure the block
+
+      for all : subcircuit
+        use entity work.real_subcircuit(basic);
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration full;
+
+-- end code from book
+
+entity fg_16_16 is
+end entity fg_16_16;
+
+library stimulus;
+use stimulus.stimulus_generators.all;
+
+architecture test of fg_16_16 is
+
+  signal in1, in2, in3, out1, out2 : bit;
+  signal test_vector : bit_vector(1 to 3);
+
+begin
+
+  dut : configuration work.full
+    generic map ( inpad_delay => 2 ns, outpad_delay => 3 ns )
+    port map ( in1 => in1, in2 => in2, in3 => in3, out1 => out1, out2 => out2 );
+
+  stimulus : all_possible_values ( test_vector, 50 ns );
+
+  (in1, in2, in3) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_01.vhd
new file mode 100644
index 0000000..77c95a9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_01.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_01 is
+
+end entity ch_17_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_01 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type natural_ptr is access natural;
+
+          variable count : natural_ptr;
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    count := new natural;
+
+    count.all := 10;
+
+    if count.all = 0 then
+      -- . . .
+      -- not in book
+      report "count.all = 0";
+      -- end not in book
+    end if;
+
+    -- end of code from book
+
+    if count.all /= 0 then
+      report "count.all /= 0";
+    end if;
+
+    -- code from book:
+
+    count := new natural'(10);
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_02.vhd
new file mode 100644
index 0000000..cdf4ae7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_02.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_02 is
+
+end entity ch_17_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_02 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type stimulus_record is record
+                                      stimulus_time : time;
+                                      stimulus_value : bit_vector(0 to 3);
+                                    end record stimulus_record;
+
+          type stimulus_ptr is access stimulus_record;
+
+          variable bus_stimulus : stimulus_ptr;
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    bus_stimulus := new stimulus_record'( 20 ns, B"0011" );
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_03.vhd
new file mode 100644
index 0000000..7ef3705
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_03.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_03 is
+
+end entity ch_17_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_03 is
+begin
+
+
+  process is
+
+            type natural_ptr is access natural;
+
+          -- code from book:
+
+          variable count1, count2 : natural_ptr;
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    count1 := new natural'(5);
+    count2 := new natural'(10);
+
+    count2 := count1;
+
+    count1.all := 20;
+
+    -- end of code from book
+
+    assert
+      -- code from book:
+      count1 = count2
+      -- end of code from book
+      ;
+
+    -- code from book:
+
+    count1 := new natural'(30);
+    count2 := new natural'(30);
+
+    -- end of code from book
+
+    assert count1 = count2;
+
+    assert
+      -- code from book:
+      count1.all = count2.all
+      -- end of code from book
+      ;
+
+    -- code from book:
+
+    if count1 /= null then
+      count1.all := count1.all + 1;
+    end if;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_04.vhd
new file mode 100644
index 0000000..043cc7b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_04.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_04 is
+
+end entity ch_17_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_04 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type stimulus_record is record
+                                      stimulus_time : time;
+                                      stimulus_value : bit_vector(0 to 3);
+                                    end record stimulus_record;
+
+          type stimulus_ptr is access stimulus_record;
+
+          variable bus_stimulus : stimulus_ptr;
+
+          -- end of code from book
+
+  begin
+
+    bus_stimulus := new stimulus_record;
+
+    bus_stimulus.all := stimulus_record'(20 ns, B"0011");
+
+    report time'image(bus_stimulus.all.stimulus_time);
+
+    report time'image(bus_stimulus.stimulus_time);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_05.vhd
new file mode 100644
index 0000000..b567349
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_05.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_05 is
+
+end entity ch_17_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_05 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type coordinate is array (1 to 3) of real;
+          type coordinate_ptr is access coordinate;
+
+          variable origin : coordinate_ptr := new coordinate'(0.0, 0.0, 0.0);
+
+          type time_array is array (positive range <>) of time;
+          variable activation_times : time_array(1 to 100);
+
+          -- end of code from book
+
+  begin
+
+    report real'image( origin(1) );
+    report real'image( origin(2) );
+    report real'image( origin(3) );
+    report real'image( origin.all(1) );
+
+    wait;
+  end process;
+
+
+  process is
+
+            type time_array is array (positive range <>) of time;
+
+          -- code from book:
+
+          type time_array_ptr is access time_array;
+
+          variable activation_times : time_array_ptr;
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    activation_times := new time_array'(10 us, 15 us, 40 us);
+
+    activation_times := new time_array'( activation_times.all
+                                         & time_array'(70 us, 100 us) );
+
+    activation_times := new time_array(1 to 10);
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_06.vhd
new file mode 100644
index 0000000..5ef2bac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_06.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_06 is
+
+end entity ch_17_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_06 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type value_cell is record
+                                 value : bit_vector(0 to 3);
+                                 next_cell : value_ptr;
+                               end record value_cell;
+
+          type value_ptr is access value_cell;
+
+          -- end of code from book
+
+  begin
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_07.vhd
new file mode 100644
index 0000000..e2d8426
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_07.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_07 is
+
+end entity ch_17_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_07 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type value_cell;
+
+          type value_ptr is access value_cell;
+
+          type value_cell is record
+                               value : bit_vector(0 to 3);
+                               next_cell : value_ptr;
+                             end record value_cell;
+
+          variable value_list : value_ptr;
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    if value_list /= null then
+      -- . . .       -- do something with the list
+      -- not in book
+      report "value_list /= null";
+      -- end not in book
+    end if;
+
+    value_list := new value_cell'( B"1000", value_list );
+
+    value_list := new value_cell'( B"0010", value_list );
+
+    value_list := new value_cell'( B"0000", value_list );
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_08.vhd
new file mode 100644
index 0000000..b47fc7e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_08.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_08.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_08 is
+
+end entity ch_17_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_08 is
+
+  type T is (t1, t2, t3);
+
+  -- code from book:
+
+  type T_ptr is access T;
+
+  procedure deallocate ( P : inout T_ptr );
+
+  -- end of code from book
+
+  procedure deallocate ( P : inout T_ptr ) is
+  begin
+    null;
+  end procedure deallocate;
+
+  -- end of code from book
+
+begin
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_09.vhd
new file mode 100644
index 0000000..5797333
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_ch_17_09.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_ch_17_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_17_09 is
+
+end entity ch_17_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_17_09 is
+
+begin
+
+  process is
+
+            type value_cell;
+
+          type value_ptr is access value_cell;
+
+          type value_cell is record
+                               value : bit_vector(0 to 3);
+                               next_cell : value_ptr;
+                             end record value_cell;
+
+          variable value_list, cell_to_be_deleted : value_ptr;
+
+  begin
+    value_list := new value_cell'( B"1000", value_list );
+    value_list := new value_cell'( B"0010", value_list );
+    value_list := new value_cell'( B"0000", value_list );
+
+    -- code from book:
+
+    cell_to_be_deleted := value_list;
+    value_list := value_list.next_cell;
+    deallocate(cell_to_be_deleted);
+
+    while value_list /= null loop
+      cell_to_be_deleted := value_list;
+      value_list := value_list.next_cell;
+      deallocate(cell_to_be_deleted);
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_05.vhd
new file mode 100644
index 0000000..0ba75ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_05.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_17_05 is
+
+end entity fg_17_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of fg_17_05 is
+
+  signal s : bit_vector(0 to 3);
+
+begin
+
+  process is
+
+            type value_cell;
+
+          type value_ptr is access value_cell;
+
+          type value_cell is record
+                               value : bit_vector(0 to 3);
+                               next_cell : value_ptr;
+                             end record value_cell;
+
+          variable value_list, current_cell : value_ptr;
+
+  begin
+    value_list := new value_cell'( B"1000", value_list );
+    value_list := new value_cell'( B"0010", value_list );
+    value_list := new value_cell'( B"0000", value_list );
+
+    -- code from book:
+
+    current_cell := value_list;
+    while current_cell /= null loop
+      s <= current_cell.value;
+      wait for 10 ns;
+      current_cell := current_cell.next_cell;
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_07.vhd
new file mode 100644
index 0000000..695419f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_07.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_17_07 is
+
+end entity fg_17_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of fg_17_07 is
+
+  signal s : bit_vector(0 to 3);
+
+begin
+
+  process is
+
+            type value_cell;
+
+          type value_ptr is access value_cell;
+
+          type value_cell is record
+                               value : bit_vector(0 to 3);
+                               next_cell : value_ptr;
+                             end record value_cell;
+
+          variable value_list, current_cell : value_ptr;
+          variable search_value : bit_vector(0 to 3);
+
+  begin
+    value_list := new value_cell'( B"1000", value_list );
+    value_list := new value_cell'( B"0010", value_list );
+    value_list := new value_cell'( B"0000", value_list );
+
+    search_value := B"0010";
+
+    -- code from book:
+
+    current_cell := value_list;
+    while current_cell /= null
+      and current_cell.value /= search_value loop
+      current_cell := current_cell.next_cell;
+    end loop;
+    assert current_cell /= null
+      report "search for value failed";
+
+    -- end of code from book
+
+    search_value := B"1111";
+
+    current_cell := value_list;
+    while current_cell /= null
+      and current_cell.value /= search_value loop
+      current_cell := current_cell.next_cell;
+    end loop;
+    assert current_cell /= null
+      report "search for value failed";
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_08.vhd
new file mode 100644
index 0000000..a934c82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_08.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package bounded_buffer_adt is
+
+  subtype byte is bit_vector(0 to 7);
+
+  type bounded_buffer_object;  -- private
+
+  type bounded_buffer is access bounded_buffer_object;
+
+  function new_bounded_buffer ( size : in positive ) return bounded_buffer;
+  -- creates a bounded buffer object with 'size' bytes of storage
+
+  procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
+                         is_empty : out boolean );
+  -- tests whether the bounded buffer is empty (i.e., no data to read)
+
+  procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
+                        is_full : out boolean );
+  -- tests whether the bounded buffer is full (i.e., no data can be written)
+
+  procedure write ( the_bounded_buffer : inout bounded_buffer;  data : in byte );
+  -- if the bounded buffer is not full, writes the data
+  -- if it is full, assertion violation with severity failure
+
+  procedure read ( the_bounded_buffer : inout bounded_buffer;  data : out byte );
+  -- if the bounded buffer is not empty, read the first byte of data
+  -- if it is empty, assertion violation with severity failure
+
+  --------------------------------------------------
+
+  -- the following types are private to the ADT
+
+  type store_array is array (natural range <>) of byte;
+
+  type store_ptr is access store_array;
+
+  type bounded_buffer_object is record
+                                  byte_count : natural;
+                                  head_index, tail_index : natural;
+                                  store : store_ptr;
+                                end record bounded_buffer_object;
+
+end package bounded_buffer_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_09.vhd
new file mode 100644
index 0000000..d9e3a4c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_09.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_17_09 is
+end entity fg_17_09;
+
+
+
+architecture test of fg_17_09 is
+begin
+
+  -- code from book
+
+  receiver : process is
+
+                       use work.bounded_buffer_adt.all;
+
+                     variable receive_buffer : bounded_buffer := new_bounded_buffer(2048);
+                     variable buffer_overrun, buffer_underrun : boolean;
+                     -- . . .
+
+                     -- not in book
+                     variable received_byte, check_byte : byte;
+                     -- end not in book
+
+  begin
+    -- . . .
+
+    test_full(receive_buffer, buffer_overrun);
+    if not buffer_overrun then
+      write(receive_buffer, received_byte);
+    end if;
+    -- . . .
+
+    test_empty(receive_buffer, buffer_underrun);
+    if not buffer_underrun then
+      read(receive_buffer, check_byte);
+    end if;
+    -- . . .
+
+  end process receiver;
+
+  -- end code from book
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_11.vhd
new file mode 100644
index 0000000..cac8c5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_11.vhd
@@ -0,0 +1,164 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package body bounded_buffer_adt is
+
+  function new_bounded_buffer ( size : in positive ) return bounded_buffer is
+  begin
+    return new bounded_buffer_object'(
+      byte_count => 0, head_index => 0, tail_index => 0,
+      store => new store_array(0 to size - 1) );
+  end function new_bounded_buffer;
+
+  procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
+                         is_empty : out boolean ) is
+  begin
+    is_empty := the_bounded_buffer.byte_count = 0;
+  end procedure test_empty;
+
+  procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
+                        is_full : out boolean ) is
+  begin
+    is_full := the_bounded_buffer.byte_count = the_bounded_buffer.store'length;
+  end procedure test_full;
+
+  procedure write ( the_bounded_buffer : inout bounded_buffer;  data : in byte ) is
+    variable buffer_full : boolean;
+  begin
+    test_full(the_bounded_buffer, buffer_full);
+    if buffer_full then
+      report "write to full bounded buffer" severity failure;
+    else
+      the_bounded_buffer.store(the_bounded_buffer.tail_index) := data;
+      the_bounded_buffer.tail_index := (the_bounded_buffer.tail_index + 1)
+                                       mod the_bounded_buffer.store'length;
+      the_bounded_buffer.byte_count := the_bounded_buffer.byte_count + 1;
+    end if;
+  end procedure write;
+
+  procedure read ( the_bounded_buffer : inout bounded_buffer;  data : out byte ) is
+    variable buffer_empty : boolean;
+  begin
+    test_empty(the_bounded_buffer, buffer_empty);
+    if buffer_empty then
+      report "read from empty bounded buffer" severity failure;
+    else
+      data := the_bounded_buffer.store(the_bounded_buffer.head_index);
+      the_bounded_buffer.head_index := (the_bounded_buffer.head_index + 1)
+                                       mod the_bounded_buffer.store'length;
+      the_bounded_buffer.byte_count := the_bounded_buffer.byte_count - 1;
+    end if;
+  end procedure read;
+
+end package body bounded_buffer_adt;
+
+
+
+-- not in book
+
+entity fg_17_11 is
+end entity fg_17_11;
+
+
+architecture test of fg_17_11 is
+begin
+
+  process is
+
+            use work.bounded_buffer_adt.all;
+
+          variable buf : bounded_buffer := new_bounded_buffer(4);
+          variable empty, full : boolean;
+          variable d : byte;
+
+  begin
+    test_empty(buf, empty);
+    assert empty;
+    test_full(buf, full);
+    assert not full;
+
+    write(buf, X"01");
+    write(buf, X"02");
+
+    test_empty(buf, empty);
+    assert not empty;
+    test_full(buf, full);
+    assert not full;
+
+    write(buf, X"03");
+    write(buf, X"04");
+
+    test_empty(buf, empty);
+    assert not empty;
+    test_full(buf, full);
+    assert full;
+
+    write(buf, X"05");
+
+    read(buf, d);
+    read(buf, d);
+
+    test_empty(buf, empty);
+    assert not empty;
+    test_full(buf, full);
+    assert not full;
+
+    read(buf, d);
+    read(buf, d);
+
+    test_empty(buf, empty);
+    assert empty;
+    test_full(buf, full);
+    assert not full;
+
+    read(buf, d);
+
+    write(buf, X"06");
+    write(buf, X"07");
+    write(buf, X"08");
+    read(buf, d);
+    read(buf, d);
+    write(buf, X"09");
+    read(buf, d);
+    write(buf, X"0A");
+    read(buf, d);
+    write(buf, X"0B");
+    read(buf, d);
+    write(buf, X"0C");
+    read(buf, d);
+    write(buf, X"0D");
+    read(buf, d);
+    write(buf, X"0E");
+    read(buf, d);
+    write(buf, X"0F");
+    read(buf, d);
+
+    wait;
+  end process;
+
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_13.vhd
new file mode 100644
index 0000000..a40f080
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_17_fg_17_13.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package stimulus_types is
+
+                 constant stimulus_vector_length : positive := 10;
+
+                 type stimulus_element is record
+                                            application_time : delay_length;
+                                            pattern : std_logic_vector(0 to stimulus_vector_length - 1);
+                                          end record stimulus_element;
+
+                 function stimulus_key ( stimulus : stimulus_element ) return delay_length;
+
+               end package stimulus_types;
+
+--------------------------------------------------
+
+               package body stimulus_types is
+
+                 function stimulus_key ( stimulus : stimulus_element ) return delay_length is
+                 begin
+                   return stimulus.application_time;
+                 end function stimulus_key;
+
+               end package body stimulus_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_01.vhd
new file mode 100644
index 0000000..8d37eb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_01.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_01 is
+
+end entity ch_18_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_01 is
+begin
+
+
+  process is
+
+            -- code from book:
+
+            type integer_file is file of integer;
+
+          file lookup_table_file : integer_file is "lookup-values";
+
+          -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            -- code from book:
+
+            type file_open_kind is (read_mode, write_mode, append_mode);
+
+          -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            type element_type is (t1, t2, t3);
+
+          -- code from book:
+
+          type file_type is file of element_type;
+
+          procedure read ( file f : file_type;  value : out element_type );
+
+          function endfile ( file f : file_type ) return boolean;
+
+          -- end of code from book
+
+          procedure read ( file f : file_type;  value : out element_type ) is
+          begin
+          end;
+
+          function endfile ( file f : file_type ) return boolean is
+          begin
+          end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_02.vhd
new file mode 100644
index 0000000..727c908
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_02.vhd
@@ -0,0 +1,133 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_02_a is
+end entity ch_18_02_a;
+
+
+architecture writer of ch_18_02_a is
+begin
+
+  process is
+            type bit_vector_file is file of bit_vector;
+          file vectors : bit_vector_file open write_mode is "vectors.dat";
+  begin
+    write(vectors, bit_vector'(""));
+    write(vectors, bit_vector'("1"));
+    write(vectors, bit_vector'("10"));
+    write(vectors, bit_vector'("011"));
+    write(vectors, bit_vector'("0100"));
+    write(vectors, bit_vector'("00101"));
+    write(vectors, bit_vector'("000110"));
+    write(vectors, bit_vector'("0000111"));
+    write(vectors, bit_vector'("00001000"));
+    write(vectors, bit_vector'("111111111111111111111111111111111111111111111111111111111111111111111111"));
+    wait;
+  end process;
+
+end architecture writer;
+
+
+----------------------------------------------------------------
+
+
+
+entity ch_18_02 is
+
+end entity ch_18_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_02 is
+begin
+
+
+  process is
+
+            type element_type is (t1, t2, t3);
+          type file_type is file of element_type;
+
+          -- code from book:
+
+          type bit_vector_file is file of bit_vector;
+
+          procedure read ( file f : file_type;
+                           value : out element_type;  length : out natural );
+
+          -- end of code from book
+
+          procedure read ( file f : file_type;
+                           value : out element_type;  length : out natural ) is
+          begin
+          end;
+
+          -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            type bit_vector_file is file of bit_vector;
+
+          -- code from book:
+
+          file vectors : bit_vector_file open read_mode is "vectors.dat";
+          variable next_vector : bit_vector(63 downto 0);
+          variable actual_len : natural;
+
+          -- end of code from book
+
+          variable lost : boolean;
+
+  begin
+    while not endfile(vectors) loop
+
+      -- code from book:
+
+      read(vectors, next_vector, actual_len);
+
+      -- end of code from book
+
+      lost :=
+        -- code from book:
+
+        actual_len > next_vector'length
+
+        -- end of code from book
+        ;
+
+    end loop;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_03.vhd
new file mode 100644
index 0000000..ead25f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_03.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_03 is
+
+end entity ch_18_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_03 is
+begin
+
+
+  process is
+
+            type element_type is (t1, t2, t3);
+
+          type file_type is file of element_type;
+
+          -- code from book:
+
+          procedure write ( file f : file_type;  value : in element_type );
+
+          -- end of code from book
+
+          procedure write ( file f : file_type;  value : in element_type ) is
+          begin
+          end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_04.vhd
new file mode 100644
index 0000000..655ab0d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_04.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_04 is
+
+end entity ch_18_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_04 is
+begin
+
+
+  process is
+
+            type data_file_type is file of character;
+          variable ch : character;
+
+          -- code from book:
+
+          procedure write_to_file is
+            file data_file : data_file_type open write_mode is "datafile";
+          begin
+            -- . . .
+            -- not in book
+            write(data_file, ch);
+            -- end not in book
+          end procedure write_to_file;
+
+          -- end of code from book
+
+  begin
+    ch := 'A';
+    write_to_file;
+    ch := 'B';
+    write_to_file;
+    ch := 'C';
+    write_to_file;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_05.vhd
new file mode 100644
index 0000000..65a345f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_05.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_05 is
+
+end entity ch_18_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_05 is
+
+  type log_file is file of string;
+
+  -- code from book:
+
+  file log_info : log_file open write_mode is "logfile";
+
+  -- end of code from book
+
+begin
+
+
+  process is
+  begin
+    write(log_info, string'("AAAA"));
+    wait for 1 ns;
+    write(log_info, string'("BBBB"));
+    wait;
+  end process;
+
+
+  process is
+  begin
+    write(log_info, string'("CCCC"));
+    wait for 1 ns;
+    write(log_info, string'("DDDD"));
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_06.vhd
new file mode 100644
index 0000000..7d324a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_06.vhd
@@ -0,0 +1,149 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_06 is
+
+end entity ch_18_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_06 is
+
+  type integer_file is file of integer;
+
+begin
+
+
+  process is
+
+            -- code from book:
+
+            file lookup_table_file, result_file : integer_file;
+
+          -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            type element_type is (t1, t2, t3);
+
+          -- code from book:
+
+          type file_type is file of element_type;
+
+          procedure file_open ( file f : file_type;
+                                external_name : in string;
+                                open_kind : in file_open_kind := read_mode );
+
+          -- end of code from book
+
+          procedure file_open ( file f : file_type;
+                                external_name : in string;
+                                open_kind : in file_open_kind := read_mode ) is
+          begin
+          end;
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            -- code from book:
+
+            file lookup_table_file : integer_file open read_mode is "lookup-values";
+
+          -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+            -- code from book:
+
+            file lookup_table_file : integer_file;
+          -- . . .
+
+          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    file_open ( lookup_table_file,
+                external_name => "lookup-values", open_kind => read_mode );
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+  process is
+
+            type element_type is (t1, t2, t3);
+          type file_type is file of element_type;
+
+          -- code from book:
+
+          type file_open_status is (open_ok, status_error, name_error, mode_error);
+
+          procedure file_open ( status : out file_open_status;
+                                file f : file_type;
+                                external_name : in string;
+                                open_kind : in file_open_kind := read_mode );
+
+          procedure file_close ( file f : file_type );
+
+          -- end of code from book
+
+          procedure file_open ( status : out file_open_status;
+                                file f : file_type;
+                                external_name : in string;
+                                open_kind : in file_open_kind := read_mode ) is
+          begin
+          end;
+
+          procedure file_close ( file f : file_type ) is
+          begin
+          end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_07.vhd
new file mode 100644
index 0000000..5b41bc6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_07.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_07_a is
+end ch_18_07_a;
+
+
+architecture writer of ch_18_07_a is
+begin
+
+  process
+    type transform_file is file of real;
+--    file initial_transforms : transform_file is out "transforms.ini";
+    file initial_transforms : transform_file open WRITE_MODE is "transforms.ini";
+  begin
+    for i in 1 to 12 loop
+      write(initial_transforms, real(i));
+    end loop;
+    wait;
+  end process;
+
+end writer;
+
+
+
+
+entity ch_18_07 is
+end ch_18_07;
+
+
+architecture test of ch_18_07 is
+begin
+
+  process
+
+    type transform_array is array (1 to 3, 1 to 3) of real;
+    variable transform1, transform2 : transform_array;
+
+    type transform_file is file of real;
+--    file initial_transforms : transform_file is in "transforms.ini";
+    file initial_transforms: transform_file open READ_MODE is "transforms.ini";
+
+    -- code from book
+
+    procedure read_transform
+      ( variable f : in transform_file;
+        variable transform : out transform_array ) is -- . . .
+
+      -- end code from book
+
+    begin
+      for i in transform'range(1) loop
+        for j in transform'range(2) loop
+          if endfile(f) then
+            assert false
+              report "unexpected end of file in read_transform - "
+              & "some array elements not read"
+              severity error;
+            return;
+          end if;
+          read ( f, transform(i, j) );
+        end loop;
+      end loop;
+    end read_transform;
+
+  begin
+
+    read_transform ( initial_transforms, transform1 );
+    read_transform ( initial_transforms, transform2 );
+
+    wait;
+  end process;
+
+end test;
+
+
+
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_08.vhd
new file mode 100644
index 0000000..9410949
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_08.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_08 is
+
+end entity ch_18_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_08 is
+begin
+
+
+  process is
+
+            use std.textio.all;
+          file f : text open read_mode is "ch_18_08.dat";
+          variable L : line;
+          variable ch : character;
+          variable s : string(1 to 5);
+          variable i : integer;
+          variable r : real;
+
+  begin
+
+    readline(f, L);
+    read(L, ch);
+    report character'image(ch);
+    read(L, ch);
+    report character'image(ch);
+
+    readline(f, L);
+    read(L, s);
+    report '"' & s & '"';
+    read(L, s);
+    report '"' & s & '"';
+
+    readline(f, L);
+
+    -- code from book:
+
+    if L'length < s'length then
+      read(L, s(1 to L'length));
+    else
+      read(L, s);
+    end if;
+
+    -- end of code from book
+
+    report '"' & s & '"';
+
+    readline(f, L);
+    read(L, i);
+    report integer'image(i);
+    read(L, r);
+    report real'image(r);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_09.vhd
new file mode 100644
index 0000000..b93e134
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_09.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_09 is
+
+end entity ch_18_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_09 is
+begin
+
+
+  process is
+
+            use std.textio.all;
+          variable L : line;
+
+  begin
+
+    write(L, 42, justified => left, field => 5);
+    writeline(output, L);
+    write(L, 42, justified => right, field => 5);
+    writeline(output, L);
+    write(L, 123, field => 2);
+    writeline(output, L);
+
+    -- code from book:
+
+    write ( L, string'( "fred" ) );
+    write ( L, ' ' );
+    write ( L, bit_vector'( X"3A" ) );
+
+    -- end of code from book
+
+    writeline(output, L);
+
+    write(L, 3.14159, digits => 2);
+    writeline(output, L);
+    write(L, 123.4567, digits => 0);
+    writeline(output, L);
+
+    write(L, 40 ns, unit => ps);
+    writeline(output, L);
+    write(L, 23 us, unit => ms);
+    writeline(output, L);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_10.vhd
new file mode 100644
index 0000000..93a2cb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_ch_18_10.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_ch_18_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_18_10 is
+
+end entity ch_18_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_18_10 is
+begin
+
+
+  process is
+
+            use std.textio.all;
+          variable L : line;
+
+          -- code from book:
+
+          type speed_category is (stopped, slow, fast, maniacal);
+          variable speed : speed_category;
+
+          -- end of code from book
+
+  begin
+
+    speed := stopped;
+
+    -- code from book:
+
+    write ( L, speed_category'image(speed) );
+
+    -- end of code from book
+
+    writeline(output, L);
+
+    speed := slow;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+    speed := fast;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+    speed := maniacal;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+
+    -- code from book:
+
+    readline( input, L );
+    speed := speed_category'value(L.all);
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_01.vhd
new file mode 100644
index 0000000..0b7bf14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_01.vhd
@@ -0,0 +1,139 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_18_01_a is
+               end entity fg_18_01_a;
+
+
+               architecture writer of fg_18_01_a is
+               begin
+
+                 process is
+
+                           subtype word is std_logic_vector(0 to 7);
+                         type load_file_type is file of word;
+                         file load_file : load_file_type open write_mode is "fg_18_01.dat";
+
+                 begin
+                   write(load_file, word'(X"00"));
+                   write(load_file, word'(X"01"));
+                   write(load_file, word'(X"02"));
+                   write(load_file, word'(X"03"));
+                   write(load_file, word'(X"04"));
+                   write(load_file, word'(X"05"));
+                   write(load_file, word'(X"06"));
+                   write(load_file, word'(X"07"));
+                   write(load_file, word'(X"08"));
+                   write(load_file, word'(X"09"));
+                   write(load_file, word'(X"0A"));
+                   write(load_file, word'(X"0B"));
+                   write(load_file, word'(X"0C"));
+                   write(load_file, word'(X"0D"));
+                   write(load_file, word'(X"0E"));
+                   write(load_file, word'(X"0F"));
+
+                   wait;
+                 end process;
+
+               end architecture writer;
+
+-- end not in book
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity ROM is
+                 generic ( load_file_name : string );
+                 port ( sel : in std_logic;
+                        address : in std_logic_vector;
+                        data : inout std_logic_vector );
+               end entity ROM;
+
+--------------------------------------------------
+
+               architecture behavioral of ROM is
+
+               begin
+
+                 behavior : process is
+
+                                      subtype word is std_logic_vector(0 to data'length - 1);
+                                    type storage_array is
+                                      array (natural range 0 to 2**address'length - 1) of word;
+                                    variable storage : storage_array;
+                                    variable index : natural;
+                                    -- . . .    -- other declarations
+
+                                    type load_file_type is file of word;
+                                    file load_file : load_file_type open read_mode is load_file_name;
+
+                 begin
+
+                   -- load ROM contents from load_file
+                   index := 0;
+                   while not endfile(load_file) loop
+                     read(load_file, storage(index));
+                     index := index + 1;
+                   end loop;
+
+                   -- respond to ROM accesses
+                   loop
+                     -- . . .
+                   end loop;
+
+                 end process behavior;
+
+               end architecture behavioral;
+
+
+
+-- not in book
+
+               library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_18_01 is
+               end entity fg_18_01;
+
+
+               architecture test of fg_18_01 is
+
+                 signal sel : std_logic;
+                 signal address : std_logic_vector(3 downto 0);
+                 signal data : std_logic_vector(0 to 7);
+
+               begin
+
+                 dut : entity work.ROM(behavioral)
+                   generic map ( load_file_name => "fg_18_01.dat" )
+                   port map ( sel, address, data );
+
+               end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_02.vhd
new file mode 100644
index 0000000..f00f099
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_02.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_18_02_a is
+end entity fg_18_02_a;
+
+
+architecture writer of fg_18_02_a is
+begin
+
+  process is
+            type packet_file is file of bit_vector;
+          file stimulus_file : packet_file open write_mode is "test packets";
+  begin
+    write(stimulus_file, X"6C");
+    write(stimulus_file, X"05");
+    write(stimulus_file, X"3");
+
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+entity fg_18_02 is
+end entity fg_18_02;
+
+
+architecture test of fg_18_02 is
+
+  signal stimulus_network, stimulus_clock : bit;
+
+begin
+
+  clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
+
+  -- code from book
+
+  stimulate_network : process is
+
+                                type packet_file is file of bit_vector;
+                              file stimulus_file : packet_file open read_mode is "test packets";
+
+                              -- variable packet : bit_vector(1 to 2048);
+                              -- not in book (for testing only)
+                              variable packet : bit_vector(1 to 8);
+                              -- end not in book
+                              variable packet_length : natural;
+
+  begin
+
+    while not endfile(stimulus_file) loop
+
+      read(stimulus_file, packet, packet_length);
+      if packet_length > packet'length then
+        report "stimulus packet too long - ignored" severity warning;
+      else
+        for bit_index in 1 to packet_length loop
+          wait until stimulus_clock = '1';
+          stimulus_network <= not stimulus_network;
+          wait until stimulus_clock = '0';
+          stimulus_network <= stimulus_network xor packet(bit_index);
+        end loop;
+      end if;
+
+    end loop;
+
+    wait;  -- end of stimulation: wait forever
+
+  end process stimulate_network;
+
+  -- code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_03.vhd
new file mode 100644
index 0000000..b496231
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_03.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_03.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+package CPU_types is
+
+  subtype word is bit_vector(0 to 31);
+  subtype byte is bit_vector(0 to 7);
+
+  alias convert_to_natural is
+    bv_utilities.bv_arithmetic.bv_to_natural [ bit_vector return natural ];
+
+  constant halt_opcode : byte := "00000000";
+
+  type code_array is array (natural range <>) of word;
+  constant code : code_array := ( X"01000000", X"01000000", X"02000000",
+				  X"01000000", X"01000000", X"02000000",
+				  X"00000000" );
+
+end package CPU_types;
+
+use work.CPU_types.all;
+
+entity CPU is
+end entity CPU;
+
+-- code from book
+
+architecture instrumented of CPU is
+
+  type count_file is file of natural;
+  file instruction_counts : count_file open write_mode is "instructions";
+
+begin
+
+  interpreter : process is
+
+                          variable IR : word;
+                        alias opcode : byte is IR(0 to 7);
+                        variable opcode_number : natural;
+                        type counter_array is array (0 to 2**opcode'length - 1) of natural;
+                        variable counters : counter_array := (others => 0);
+                        -- . . .
+
+                        -- not in book
+                        variable code_index : natural := 0;
+                        -- end not in book
+
+  begin
+
+    -- . . .    -- initialize the instruction set interpreter
+
+    instruction_loop : loop
+
+      -- . . .    -- fetch the next instruction into IR
+
+      -- not in book
+      IR := code(code_index);
+      code_index := code_index + 1;
+      -- end not in book
+
+      -- decode the instruction
+      opcode_number := convert_to_natural(opcode);
+      counters(opcode_number) := counters(opcode_number) + 1;
+      -- . . .
+
+      -- execute the decoded instruction
+      case opcode is
+        -- . . .
+        when halt_opcode => exit instruction_loop;
+                            -- . . .
+                            -- not in book
+        when others => null;
+                       -- end not in book
+      end case;
+
+    end loop instruction_loop;
+
+    for index in counters'range loop
+      write(instruction_counts, counters(index));
+    end loop;
+    wait;  -- program finished, wait forever
+
+  end process interpreter;
+
+end architecture instrumented;
+
+-- code from book
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_04.vhd
new file mode 100644
index 0000000..bfe6f09
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_04.vhd
@@ -0,0 +1,155 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity cache is
+  generic ( cache_size, block_size, associativity : positive;
+            benchmark_name : string(1 to 10) );
+  port ( halt : in bit );
+end entity cache;
+
+
+
+architecture instrumented of cache is
+
+begin
+
+  -- code from book
+
+  cache_monitor : process is
+
+                            type measurement_record is
+                          record
+                            cache_size, block_size, associativity : positive;
+                            benchmark_name : string(1 to 10);
+                            miss_rate : real;
+                            ave_access_time : delay_length;
+                          end record;
+                          type measurement_file is file of measurement_record;
+                          file measurements : measurement_file
+                            open append_mode is "cache-measurements";
+                          -- . . .
+
+                          -- not in book
+                          constant miss_count : natural := 100;
+                          constant total_accesses : natural := 1000;
+                          constant total_delay : delay_length := 2400 ns;
+                          -- end not in book
+
+  begin
+    -- . . .
+    loop
+      -- . . .
+      -- not in book
+      wait on halt;
+      -- end not in book
+      exit when halt = '1';
+      -- . . .
+    end loop;
+
+    write ( measurements,
+            measurement_record'(
+              -- write values of generics for this run
+              cache_size, block_size, associativity, benchmark_name,
+              -- calculate performance metrics
+              miss_rate => real(miss_count) / real(total_accesses),
+              ave_access_time => total_delay / total_accesses ) );
+    wait;
+
+  end process cache_monitor;
+
+  -- end code from book
+
+end architecture instrumented;
+
+
+
+entity fg_18_04 is
+end entity fg_18_04;
+
+
+
+architecture test of fg_18_04 is
+
+  signal halt : bit := '0';
+
+begin
+
+  dut : entity work.cache(instrumented)
+    generic map ( cache_size => 128*1024, block_size => 16,
+                  associativity => 2, benchmark_name => "dhrystone " )
+    port map ( halt => halt );
+
+  halt <= '1' after 10 ns;
+
+end architecture test;
+
+
+
+entity fg_18_04_a is
+end entity fg_18_04_a;
+
+
+architecture reader of fg_18_04_a is
+begin
+
+  process is
+
+            type measurement_record is
+          record
+            cache_size, block_size, associativity : positive;
+            benchmark_name : string(1 to 10);
+            miss_rate : real;
+            ave_access_time : delay_length;
+          end record;
+          type measurement_file is file of measurement_record;
+          file measurements : measurement_file open read_mode is "cache-measurements";
+          variable measurement : measurement_record;
+
+          use std.textio.all;
+          variable L : line;
+
+  begin
+    while not endfile(measurements) loop
+      read(measurements, measurement);
+      write(L, measurement.cache_size);
+      write(L, ' ');
+      write(L, measurement.block_size);
+      write(L, ' ');
+      write(L, measurement.associativity);
+      write(L, ' ');
+      write(L, measurement.benchmark_name);
+      write(L, ' ');
+      write(L, measurement.miss_rate);
+      write(L, ' ');
+      write(L, measurement.ave_access_time);
+      writeline(output, L);
+
+    end loop;
+
+    wait;
+  end process;
+
+end architecture reader;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_05.vhd
new file mode 100644
index 0000000..e20b30f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_05.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_18_05_a is
+end entity fg_18_05_a;
+
+
+architecture writer of fg_18_05_a is
+begin
+
+  process is
+
+            type integer_file is file of integer;
+          file data_file : integer_file open write_mode is "coeff-data";
+
+  begin
+    write(data_file, 0);
+    write(data_file, 1);
+    write(data_file, 2);
+    write(data_file, 3);
+    write(data_file, 4);
+    write(data_file, 5);
+    write(data_file, 6);
+    write(data_file, 7);
+    write(data_file, 8);
+    write(data_file, 9);
+    write(data_file, 10);
+    write(data_file, 11);
+    write(data_file, 12);
+    write(data_file, 13);
+    write(data_file, 14);
+    write(data_file, 15);
+    write(data_file, 16);
+    write(data_file, 17);
+    write(data_file, 18);
+
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+entity fg_18_05 is
+end entity fg_18_05;
+
+
+architecture test of fg_18_05 is
+begin
+
+  process is
+
+            -- code from book (in text)
+
+            type integer_vector is array (integer range <>) of integer;
+
+          -- end code from book
+
+          -- code from book (Figure 18-5)
+
+          impure function read_array ( file_name : string;  array_length : natural )
+            return integer_vector is
+            type integer_file is file of integer;
+            file data_file : integer_file open read_mode is file_name;
+            variable result : integer_vector(1 to array_length) := (others => 0);
+            variable index : integer := 1;
+          begin
+            while not endfile(data_file) and index <= array_length loop
+              read(data_file, result(index));
+              index := index + 1;
+            end loop;
+            return result;
+          end function read_array;
+
+          -- end code from book
+
+          -- code from book (in text)
+
+          constant coeffs : integer_vector := read_array("coeff-data", 16);
+
+          -- end code from book
+
+  begin
+    wait;
+  end process;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_06.vhd
new file mode 100644
index 0000000..9f4e500
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_06.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity fg_18_06 is
+               end entity fg_18_06;
+
+
+               architecture test of fg_18_06 is
+
+
+
+               begin
+
+                 -- code from book
+
+                 stimulus_generator : process is
+
+                                                type directory_file is file of string;
+                                              file directory : directory_file open read_mode is "stimulus-directory";
+                                              variable file_name : string(1 to 50);
+                                              variable file_name_length : natural;
+                                              variable open_status : file_open_status;
+
+                                              subtype stimulus_vector is std_logic_vector(0 to 9);
+                                              type stimulus_file is file of stimulus_vector;
+                                              file stimuli : stimulus_file;
+                                              variable current_stimulus : stimulus_vector;
+                                              -- . . .
+
+                 begin
+                   file_loop : while not endfile(directory) loop
+                     read( directory, file_name, file_name_length );
+                     if file_name_length > file_name'length then
+                       report "file name too long: " & file_name & "... - file skipped"
+                         severity warning;
+                       next file_loop;
+                     end if;
+                     file_open ( open_status, stimuli,
+                                 file_name(1 to file_name_length), read_mode );
+                     if open_status /= open_ok then
+                       report file_open_status'image(open_status) & " while opening file "
+                         & file_name(1 to file_name_length) & " - file skipped"
+                         severity warning;
+                       next file_loop;
+                     end if;
+                     stimulus_loop : while not endfile(stimuli) loop
+                       read(stimuli, current_stimulus);
+                       -- . . .    -- apply the stimulus
+                     end loop stimulus_loop;
+                     file_close(stimuli);
+                   end loop file_loop;
+                   wait;
+                 end process stimulus_generator;
+
+                 -- end code from book
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_07.vhd
new file mode 100644
index 0000000..683c15a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_07.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_18_07_a is
+end entity fg_18_07_a;
+
+
+architecture writer of fg_18_07_a is
+begin
+
+  process is
+            type transform_file is file of real;
+          file initial_transforms : transform_file open write_mode is "transforms.ini";
+  begin
+    for i in 1 to 50 loop
+      write(initial_transforms, real(i));
+    end loop;
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+
+entity fg_18_07 is
+end entity fg_18_07;
+
+
+architecture test of fg_18_07 is
+begin
+
+  process is
+
+            -- code from book (in text)
+
+            type transform_array is array (1 to 3, 1 to 3) of real;
+          variable transform1, transform2 : transform_array;
+
+          type transform_file is file of real;
+          file initial_transforms : transform_file
+            open read_mode is "transforms.ini";
+
+          -- end code from book
+
+          -- code from book (Figure 18-7)
+
+          procedure read_transform ( file f : transform_file;
+                                     variable transform : out transform_array ) is
+          begin
+            for i in transform'range(1) loop
+              for j in transform'range(2) loop
+                if endfile(f) then
+                  report "unexpected end of file in read_transform - "
+                    & "some array elements not read"
+                    severity error;
+                  return;
+                end if;
+                read ( f, transform(i, j) );
+              end loop;
+            end loop;
+          end procedure read_transform;
+
+          -- end code from book
+
+  begin
+
+    -- code from book (in text)
+
+    read_transform ( initial_transforms, transform1 );
+    read_transform ( initial_transforms, transform2 );
+
+    -- end code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_08.vhd
new file mode 100644
index 0000000..104748a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_08.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package textio is
+
+  type line is access string;
+
+  type text is file of string;
+
+  type side is (right, left);
+
+  subtype width is natural;
+
+  file input : text open read_mode is "std_input";
+  file output : text open write_mode is "std_output";
+
+  procedure readline(file f: text; l: out line);
+
+  procedure read ( L : inout line;  value: out bit;  good : out boolean );
+  procedure read ( L : inout line;  value: out bit );
+
+  procedure read ( L : inout line;  value: out bit_vector;  good : out boolean );
+  procedure read ( L : inout line;  value: out bit_vector );
+
+  procedure read ( L : inout line;  value: out boolean;  good : out boolean );
+  procedure read ( L : inout line;  value: out boolean );
+
+  procedure read ( L : inout line;  value: out character;  good : out boolean );
+  procedure read ( L : inout line;  value: out character );
+
+  procedure read ( L : inout line;  value: out integer;  good : out boolean );
+  procedure read ( L : inout line;  value: out integer );
+
+  procedure read ( L : inout line;  value: out real;  good : out boolean );
+  procedure read ( L : inout line;  value: out real );
+
+  procedure read ( L : inout line;  value: out string;  good : out boolean );
+  procedure read ( L : inout line;  value: out string );
+
+  procedure read ( L : inout line;  value: out time;  good : out boolean );
+  procedure read ( L : inout line;  value: out time );
+
+  procedure writeline ( file f : text;  L : inout line );
+
+  procedure write ( L : inout line;  value : in bit;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in bit_vector;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in boolean;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in character;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in integer;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in real;
+  justified: in side := right;  field: in width := 0;
+  digits: in natural := 0 );
+
+  procedure write ( L : inout line;  value : in string;
+  justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in time;
+  justified: in side := right;  field: in width := 0;
+  unit: in time := ns );
+
+end package textio;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_09.vhd
new file mode 100644
index 0000000..c121b69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_09.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_09.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library bv_utilities;
+
+use bv_utilities.bv_arithmetic.all, std.textio.all;
+
+architecture file_loaded of memory is
+begin
+
+  mem_behavior : process is
+
+                           constant high_address : natural := mem_size - 1;
+
+                         type memory_array is
+                           array (natural range 0 to high_address / 4) of dlx_bv_word;
+
+                         variable mem : memory_array;
+
+                         -- . . .    -- other variables as in architecture preloaded
+
+                         procedure load is
+
+                           file binary_file : text open read_mode is load_file_name;
+                           variable L : line;
+                           variable ch : character;
+                           variable line_number : natural := 0;
+                           variable addr : natural;
+                           variable word : dlx_bv_word;
+
+                           procedure read_hex_natural(L : inout line; n : out natural) is
+                             variable result : natural := 0;
+                           begin
+                             for i in 1 to 8 loop
+                               read(L, ch);
+                               if '0' <= ch and ch <= '9' then
+                                 result := result*16 + character'pos(ch) - character'pos('0');
+                               elsif 'A' <= ch and ch <= 'F' then
+                                 result := result*16 + character'pos(ch) - character'pos('A') + 10;
+                               elsif 'a' <= ch and ch <= 'f' then
+                                 result := result*16 + character'pos(ch) - character'pos('a') + 10;
+                               else
+                                 report "Format error in file " & load_file_name
+                                   & " on line " & integer'image(line_number) severity error;
+                               end if;
+                             end loop;
+                             n := result;
+                           end read_hex_natural;
+
+                           procedure read_hex_word(L : inout line; word : out dlx_bv_word) is
+                             variable digit : natural;
+                             variable r : natural := 0;
+                           begin
+                             for i in 1 to 8 loop
+                               read(L, ch);
+                               if '0' <= ch and ch <= '9' then
+                                 digit := character'pos(ch) - character'pos('0');
+                               elsif 'A' <= ch and ch <= 'F' then
+                                 digit := character'pos(ch) - character'pos('A') + 10;
+                               elsif 'a' <= ch and ch <= 'f' then
+                                 digit := character'pos(ch) - character'pos('a') + 10;
+                               else
+                                 report "Format error in file " & load_file_name
+                                   & " on line " & integer'image(line_number)
+                                   severity error;
+                               end if;
+                               word(r to r+3) := natural_to_bv(digit, 4);
+                               r := r + 4;
+                             end loop;
+                           end read_hex_word;
+
+                         begin
+                           while not endfile(binary_file) loop
+                             readline(binary_file, L);
+                             line_number := line_number + 1;
+                             read_hex_natural(L, addr);
+                             read(L, ch);  -- the space between addr and data
+                             read_hex_word(L, word);
+                             mem(addr / 4) := word;
+                           end loop;
+                         end load;
+
+                         procedure do_write is -- . . . -- as in architecture preloaded
+
+                           procedure do_read is -- . . .  -- as in architecture preloaded
+
+                           begin
+                             load;  -- read binary memory image into memory array
+                             -- . . .       -- as in architecture preloaded
+                           end process mem_behavior;
+
+                         end architecture file_loaded;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_10.vhd
new file mode 100644
index 0000000..587b5ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_10.vhd
@@ -0,0 +1,150 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_18_10 is
+end entity fg_18_10;
+
+
+architecture test of fg_18_10 is
+
+  signal temperature, setting : integer;
+  signal enable, heater_fail : bit;
+
+begin
+
+-- code from book
+
+  stimulus_interpreter : process is
+
+                                   use std.textio.all;
+
+                                 file control : text open read_mode is "control";
+
+                                 variable command : line;
+                                 variable read_ok : boolean;
+                                 variable next_time : time;
+                                 variable whitespace : character;
+                                 variable signal_id : string(1 to 4);
+                                 variable temp_value, set_value : integer;
+                                 variable on_value, fail_value : bit;
+
+  begin
+
+    command_loop : while not endfile(control) loop
+
+      readline ( control, command );
+
+      -- read next stimulus time, and suspend until then
+      read ( command, next_time, read_ok );
+      if not read_ok then
+        report "error reading time from line: " & command.all
+          severity warning;
+        next command_loop;
+      end if;
+      wait for next_time - now;
+
+      -- skip whitespace
+      while command'length > 0
+        and ( command(command'left) = ' '    -- ordinary space
+              or command(command'left) = ' '  -- non-breaking space
+              or command(command'left) = HT ) loop
+        read ( command, whitespace );
+      end loop;
+
+      -- read signal identifier string
+      read ( command, signal_id, read_ok );
+      if not read_ok then
+        report "error reading signal id from line: " & command.all
+          severity warning;
+        next command_loop;
+      end if;
+      -- dispatch based on signal id
+      case signal_id is
+
+        when "temp" =>
+          read ( command, temp_value, read_ok );
+          if not read_ok then
+            report "error reading temperature value from line: "
+              & command.all
+              severity warning;
+            next command_loop;
+          end if;
+          temperature <= temp_value;
+
+        when "set " =>
+          -- . . .    -- similar to "temp"
+
+          -- not in book
+          read ( command, set_value, read_ok );
+          if not read_ok then
+            report "error reading setting value from line: "
+              & command.all
+              severity warning;
+            next command_loop;
+          end if;
+          setting <= set_value;
+          -- end not in book
+
+        when "on  " =>
+          read ( command, on_value, read_ok );
+          if not read_ok then
+            report "error reading on value from line: "
+              & command.all
+              severity warning;
+            next command_loop;
+          end if;
+          enable <= on_value;
+
+        when "fail" =>
+          -- . . .    -- similar to "on  "
+
+          -- not in book
+          read ( command, fail_value, read_ok );
+          if not read_ok then
+            report "error reading fail value from line: "
+              & command.all
+              severity warning;
+            next command_loop;
+          end if;
+          heater_fail <= fail_value;
+          -- end not in book
+
+        when others =>
+          report "invalid signal id in line: " & signal_id
+            severity warning;
+          next command_loop;
+
+      end case;
+
+    end loop command_loop;
+
+    wait;
+
+  end process stimulus_interpreter;
+
+-- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_11.vhd
new file mode 100644
index 0000000..8474b66
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_18_fg_18_11.vhd
@@ -0,0 +1,133 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_18_fg_18_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_18_11 is
+end entity fg_18_11;
+
+
+
+architecture test of fg_18_11 is
+
+  subtype byte is bit_vector(7 downto 0);
+  type byte_array is array (natural range <>) of byte;
+
+  function resolve_bytes ( drivers : in byte_array ) return byte is
+  begin
+    return drivers(drivers'left);
+  end function resolve_bytes;
+
+  function resolve_bits ( drivers : in bit_vector ) return bit is
+  begin
+    return drivers(drivers'left);
+  end function resolve_bits;
+
+  -- code from book (in text)
+
+  signal address : bit_vector(15 downto 0);
+  signal data : resolve_bytes byte;
+  signal rd, wr, io : bit;    -- read, write, io/mem select
+  signal ready : resolve_bits bit;
+
+  -- end code from book
+
+begin
+
+-- code from book
+
+  bus_monitor : process is
+
+                          constant header : string(1 to 44)
+                        := FF & "      Time   R/W I/M  Address          Data";
+
+                        use std.textio.all;
+
+                        file log : text open write_mode is "buslog";
+                        variable trace_line : line;
+                        variable line_count : natural := 0;
+
+  begin
+
+    if line_count mod 60 = 0 then
+      write ( trace_line, header );
+      writeline ( log, trace_line );
+      writeline ( log, trace_line );    -- empty line
+    end if;
+    wait until (rd = '1' or wr = '1') and ready = '1';
+    write ( trace_line, now, justified => right, field => 10, unit => us );
+    write ( trace_line, string'("    ") );
+    if rd = '1' then
+      write ( trace_line, 'R' );
+    else
+      write ( trace_line, 'W' );
+    end if;
+    write ( trace_line, string'("   ") );
+    if io = '1' then
+      write ( trace_line, 'I' );
+    else
+      write ( trace_line, 'M' );
+    end if;
+    write ( trace_line, string'("   ") );
+    write ( trace_line, address );
+    write ( trace_line, ' ');
+    write ( trace_line, data );
+    writeline ( log, trace_line );
+    line_count := line_count + 1;
+
+  end process bus_monitor;
+
+-- end code from book
+
+  stimulus : process is
+  begin
+    wait for 0.4 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0000";
+    data <= B"10011110";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 0.9 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0001";
+    data <= B"00010010";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 2.0 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0014";
+    data <= B"11100111";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 2.7 us - now;
+    wr <= '1', '0' after 10 ns;
+    io <= '1', '0' after 10 ns;
+    address <= X"0007";
+    data <= X"00";
+    ready <= '1', '0' after 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds-qn.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds-qn.vhd
new file mode 100644
index 0000000..0ed8b0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds-qn.vhd
@@ -0,0 +1,162 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_ds-qn.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+use qsim.qsim_types.all, random.random.all;
+
+architecture queue_net of disk_system is
+
+  constant disk_cache_miss_rate : real := 0.2;
+  constant num_disks : positive := 2;
+
+  constant disk_cache_fork_probabilities : probability_vector(1 to num_disks)
+    := ( others => disk_cache_miss_rate / real(num_disks) );
+
+  signal info_detail_control : info_detail_type := none;
+  signal new_job, cpu_queue_in, cpu_in, cpu_out,
+    quantum_expired, job_done, requesting_disk,
+    disk_cache_hit, request_done : arc_type;
+  signal disk_cache_miss, disk_done : arc_vector(1 to num_disks);
+  signal cpu_ready : boolean;
+
+begin
+
+  new_jobs : entity source
+    generic map ( name => "new_jobs",
+		  distribution => exponential,
+		  mean_inter_arrival_time => 2 sec,
+		  seed => sample_seeds(1),
+		  time_unit => ms,
+		  info_file_name => "new_jobs.dat" )
+    port map ( out_arc => new_job,
+	       info_detail => info_detail_control );
+
+  cpu_join : entity join
+    generic map ( name => "cpu_join",
+		  time_unit => ms,
+		  info_file_name => "cpu_join.dat" )
+    port map ( in_arc(1) => quantum_expired,
+	       in_arc(2) => new_job,
+	       in_arc(3) => request_done,
+	       out_arc => cpu_queue_in,
+	       info_detail => info_detail_control );
+
+  cpu_queue : entity queue
+    generic map ( name => "cpu_queue",
+		  time_unit => ms,
+		  info_file_name => "cpu_queue.dat" )
+    port map ( in_arc => cpu_queue_in,
+	       out_arc => cpu_in,
+	       out_ready => cpu_ready,
+	       info_detail => info_detail_control );
+
+  cpu : entity server
+    generic map ( name => "cpu",
+		  distribution => uniform,
+		  mean_service_time => 50 ms,
+		  seed => sample_seeds(2),
+		  time_unit => ms,
+		  info_file_name => "cpu.dat" )
+    port map ( in_arc => cpu_in,
+	       in_ready => cpu_ready,
+	       out_arc => cpu_out,
+	       info_detail => info_detail_control );
+
+  cpu_fork : entity fork
+    generic map ( name => "cpu_fork",
+		  probabilities => ( 1 => 0.5, 2 => 0.45 ),
+		  seed => sample_seeds(3),
+		  time_unit => ms,
+		  info_file_name => "cpu_fork.dat" )
+    port map ( in_arc => cpu_out,
+	       out_arc(1) => quantum_expired,
+	       out_arc(2) => requesting_disk,
+	       out_arc(3) => job_done,
+	       info_detail => info_detail_control );
+
+  job_sink : entity sink
+    generic map ( name => "job_sink",
+		  time_unit => ms,
+		  info_file_name => "job_sink.dat" )
+    port map ( in_arc => job_done,
+	       info_detail => info_detail_control );
+
+  disk_cache_fork : entity fork
+    generic map ( name => "disk_cache_fork",
+		  probabilities => disk_cache_fork_probabilities,
+		  seed => sample_seeds(4),
+		  time_unit => ms,
+		  info_file_name => "disk_cache_fork.dat" )
+    port map ( in_arc => requesting_disk,
+	       out_arc(1 to num_disks) => disk_cache_miss,
+	       out_arc(num_disks + 1) => disk_cache_hit,
+	       info_detail => info_detail_control );
+
+
+  disk_array : for disk_index in 1 to num_disks generate
+
+    constant disk_index_str : string := integer'image(disk_index);
+
+    signal disk_in : arc_type;
+    signal disk_ready : boolean;
+
+  begin
+
+    disk_queue : entity queue
+      generic map ( name => "disk_queue_" & disk_index_str,
+		    time_unit => ms,
+		    info_file_name => "disk_queue_" & disk_index_str & ".dat" )
+      port map ( in_arc => disk_cache_miss(disk_index),
+	         out_arc => disk_in,
+	         out_ready => disk_ready,
+	         info_detail => info_detail_control );
+
+    disk : entity server
+      generic map ( name => "disk_" & disk_index_str,
+		    distribution => exponential,
+		    mean_service_time => 15 ms,
+		    seed => sample_seeds(4 + disk_index),
+		    time_unit => ms,
+		    info_file_name => "disk_" & disk_index_str & ".dat" )
+      port map ( in_arc => disk_in,
+	         in_ready => disk_ready,
+	         out_arc => disk_done(disk_index),
+	         info_detail => info_detail_control );
+
+  end generate disk_array;
+
+
+  disk_cache_join : entity join
+    generic map ( name => "disk_cache_join",
+		  time_unit => ms,
+		  info_file_name => "disk_cache_join.dat" )
+    port map ( in_arc(1 to num_disks) => disk_done,
+	       in_arc(num_disks + 1) => disk_cache_hit,
+	       out_arc => request_done,
+	       info_detail => info_detail_control );
+
+end architecture queue_net;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds.vhd
new file mode 100644
index 0000000..862cabd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_ds.vhd
@@ -0,0 +1,30 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_ds.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity disk_system is
+
+end entity disk_system;
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork-b.vhd
new file mode 100644
index 0000000..b273c42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork-b.vhd
@@ -0,0 +1,131 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_fork-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+architecture behavior of fork is
+
+begin
+
+  forker : process
+
+    variable cumulative_probabilities : probability_vector(1 to probabilities'length);
+    variable destination : positive range out_arc'range;
+    variable probabilities_index : positive range probabilities'range;
+    variable number_of_tokens_forked : natural := 0;
+    type counter_array is array (positive range out_arc'range) of natural;
+    variable number_forked_to_destination : counter_array := (others => 0);
+
+    variable random_info : random_info_record;
+    variable random_number : real;
+
+    type transaction_vector is array (positive range <>) of boolean;
+    variable out_arc_transaction_driving_value : transaction_vector(out_arc'range)
+      := (others => false);
+
+    use std.textio.all;
+    file info_file : text;
+    variable L : line;
+
+    procedure write_summary is
+    begin
+      write(L, string'("Summary information for fork "));
+      write(L, name);
+      write(L, string'(" up to time "));
+      write(L, now, unit => time_unit);
+      writeline(info_file, L);
+      write(L, string'("  Number of tokens forked = "));
+      write(L, natural(number_of_tokens_forked));
+      writeline(info_file, L);
+      for destination in out_arc'range loop
+        write(L, string'("    Number to output("));
+        write(L, destination);
+        write(L, string'(") = "));
+        write(L, number_forked_to_destination(destination));
+        write(L, string'(" ("));
+        write(L, real(number_forked_to_destination(destination))
+              / real(number_of_tokens_forked),
+              digits => 4);
+        write(L, ')');
+        writeline(info_file, L);
+      end loop;
+      writeline(info_file, L);
+    end write_summary;
+
+    procedure write_trace is
+    begin
+      write(L, string'("Fork "));
+      write(L, name);
+      write(L, string'(": at "));
+      write(L, now, unit => time_unit);
+      write(L, string'(" forked to output "));
+      write(L, destination);
+      write(L, ' ');
+      write(L, in_arc.token, time_unit);
+      writeline(info_file, L);
+    end write_trace;
+
+  begin
+    assert probabilities'length = out_arc'length - 1
+      report "incorrent number of probabilities - should be "
+      & integer'image(out_arc'length - 1) severity failure;
+    cumulative_probabilities := probabilities;
+    for index in 2 to cumulative_probabilities'length loop
+      cumulative_probabilities(index) := cumulative_probabilities(index - 1)
+					 + cumulative_probabilities(index);
+    end loop;
+    init_uniform( random_info,
+                  lower_bound => 0.0, upper_bound => 1.0, seed => seed );
+    file_open(info_file, info_file_name, write_mode);
+
+    loop
+      wait on info_detail'transaction, in_arc;
+      if info_detail'active and info_detail = summary then
+        write_summary;
+      end if;
+      if in_arc'event then
+        generate_random(random_info, random_number);
+        destination := out_arc'left;
+        for index in 1 to cumulative_probabilities'length loop
+          exit when random_number < cumulative_probabilities(index);
+	  if out_arc'ascending then
+	    destination := destination + 1;
+	  else
+	    destination := destination - 1;
+	  end if;
+        end loop;
+        out_arc(destination) <= arc_type'( transaction => not out_arc_transaction_driving_value(destination),
+					   token => in_arc.token );
+	out_arc_transaction_driving_value(destination) := not out_arc_transaction_driving_value(destination);
+        number_of_tokens_forked := number_of_tokens_forked + 1;
+        number_forked_to_destination(destination)
+          := number_forked_to_destination(destination) + 1;
+        if info_detail = trace then
+          write_trace;
+        end if;
+      end if;
+    end loop;
+  end process forker;
+
+end behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork.vhd
new file mode 100644
index 0000000..c26a730
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_fork.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_fork.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use qsim.qsim_types.all, random.random.all;
+
+entity fork is
+
+  generic ( name : string;
+            probabilities : probability_vector;
+            -- must be one element shorter than out_arc port
+            seed : seed_type;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( in_arc : in arc_type;
+         out_arc : out arc_vector;
+         info_detail : in info_detail_type );       
+
+end fork;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join-b.vhd
new file mode 100644
index 0000000..cef314e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join-b.vhd
@@ -0,0 +1,139 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_join-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+architecture behavior of join is
+
+begin
+
+  joiner : process
+
+    use qsim.token_fifo_adt.all;
+
+    variable source : positive range in_arc'range;
+    variable token_fifo : fifo_type := new_fifo;
+    variable current_fifo_size : natural := 0;
+    variable head_token : token_type;
+    variable number_of_tokens_joined : natural := 0;
+    type counter_array is array (positive range in_arc'range) of natural;
+    variable number_joined_from_source : counter_array := (others => 0);
+
+    use std.textio.all;
+    file info_file : text;
+    variable L : line;
+
+--  Modeltech bug mt043 workaround
+    variable in_arc_last_value : arc_vector(in_arc'range) := in_arc;
+--
+
+    procedure write_summary is
+    begin
+      write(L, string'("Summary information for join "));
+      write(L, name);
+      write(L, string'(" up to time "));
+      write(L, now, unit => time_unit);
+      writeline(info_file, L);
+      write(L, string'("  Number of tokens joined = "));
+      write(L, natural(number_of_tokens_joined));
+      writeline(info_file, L);
+      for source in in_arc'range loop
+        write(L, string'("    Number from input("));
+        write(L, source);
+        write(L, string'(") = "));
+        write(L, natural(number_joined_from_source(source)));
+        write(L, string'(" ("));
+        write(L, real(number_joined_from_source(source))
+              / real(number_of_tokens_joined),
+              digits => 4);
+        write(L, ')');
+        writeline(info_file, L);
+      end loop;
+      writeline(info_file, L);
+    end write_summary;
+
+    procedure write_trace is
+    begin
+      write(L, string'("Join "));
+      write(L, name);
+      write(L, string'(": at "));
+      write(L, now, unit => time_unit);
+      write(L, string'(" joined from input "));
+      write(L, source);
+      write(L, ' ');
+      write(L, in_arc(source).token, time_unit);
+      writeline(info_file, L);
+    end write_trace;
+
+    procedure accept_new_tokens is
+    begin
+      for index in 1 to in_arc'length loop
+--  Modeltech bug mt043 workaround
+--      if in_arc(index).transaction /= in_arc'last_value(index).transaction then
+        if in_arc(index).transaction /= in_arc_last_value(index).transaction then
+--
+          source := index;
+          insert(token_fifo, in_arc(source).token);
+          current_fifo_size := current_fifo_size + 1;
+          number_of_tokens_joined := number_of_tokens_joined + 1;
+          number_joined_from_source(source) := number_joined_from_source(source) + 1;
+          if info_detail = trace then
+            write_trace;
+          end if;
+        end if;
+      end loop;
+--  Modeltech bug mt043 workaround
+      in_arc_last_value := in_arc;
+--
+    end procedure accept_new_tokens;
+
+  begin
+    file_open(info_file, info_file_name, write_mode);
+    loop
+      wait on info_detail'transaction, in_arc;
+      if info_detail'active and info_detail = summary then
+        write_summary;
+      end if;
+      if in_arc'event then
+	accept_new_tokens;
+        while current_fifo_size > 0 loop
+          remove(token_fifo, head_token);
+          current_fifo_size := current_fifo_size - 1;
+	  out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
+			        token => head_token );
+          wait for 0 fs;  -- delta delay before next output token
+          if info_detail'active and info_detail = summary then
+            write_summary;
+          end if;
+          if in_arc'event then
+	    accept_new_tokens;
+	  end if;
+        end loop;
+      end if;
+    end loop;
+  end process joiner;
+
+end behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join.vhd
new file mode 100644
index 0000000..1b27724
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_join.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_join.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+use qsim.qsim_types.all;
+
+entity join is
+
+  generic ( name : string;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( in_arc : in arc_vector;
+	 out_arc : out arc_type;
+	 info_detail : in info_detail_type );       
+
+end join;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt-b.vhd
new file mode 100644
index 0000000..199a899
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt-b.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_qsimt-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package body qsim_types is
+
+  use std.textio.all;
+
+  procedure write ( L : inout line;  t : in token_type;
+  creation_time_unit : in time := ns ) is
+  begin
+    write(L, string'("token "));
+    write(L, natural(t.id));
+    write(L, string'(" from "));
+    write(L, t.source_name(1 to t.source_name_length));
+    write(L, string'(" created at "));
+    write(L, t.creation_time, unit => creation_time_unit);
+  end write;
+
+end package body qsim_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt.vhd
new file mode 100644
index 0000000..c840b98
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qsimt.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_qsimt.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+--use std.textio.line;
+use std.textio.all;
+
+package qsim_types is
+
+  constant name_max_length : natural := 20;
+  type token_id_type is range 0 to integer'high;
+
+  type token_type is record
+                       source_name : string(1 to name_max_length);
+                       source_name_length : natural;
+                       id : token_id_type;
+                       creation_time : time;
+                     end record;
+
+  type token_vector is array (positive range <>) of token_type;
+
+  type arc_type is record
+                     transaction : boolean;  -- flips when an arc changes
+                     token : token_type;
+                   end record arc_type;
+
+  type arc_vector is array (positive range <>) of arc_type;
+
+  type info_detail_type is (none, summary, trace);
+
+  procedure write ( L : inout line;  t : in token_type;
+  creation_time_unit : in time := ns );
+
+end package qsim_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qt.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qt.vhd
new file mode 100644
index 0000000..090ac12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_qt.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_qt.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+use qsim.qsim_types.all;
+
+package queue_types is
+
+  type waiting_token_type is record
+                               token : token_type;
+                               time_when_enqueued : time;
+                             end record waiting_token_type;
+
+end package queue_types;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue-b.vhd
new file mode 100644
index 0000000..4d5e363
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue-b.vhd
@@ -0,0 +1,146 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_queue-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library math;
+
+architecture behavior of queue is
+
+begin
+
+  queue_manager : process is
+
+                            use qsim.queue_types.all, qsim.waiting_token_fifo_adt.all;
+
+                          variable waiting_token, head_token : waiting_token_type;
+                          variable waiting_token_fifo : fifo_type := new_fifo;
+                          variable out_token_in_transit : boolean := false;
+                          variable number_of_tokens_released : natural := 0;
+                          variable current_queue_size : natural := 0;
+                          variable maximum_queue_size : natural := 0;
+                          variable waiting_time : natural;  -- in time_unit
+                          variable sum_of_waiting_times : real := 0.0;  -- in time_unit
+                          variable sum_of_squares_of_waiting_times : real := 0.0;  --in time_unit**2
+
+                          use std.textio.all;
+                          file info_file : text;
+                          variable L : line;
+
+                          use math.math_real.sqrt;
+
+                          procedure write_summary is
+                            variable mean_waiting_time : real
+                              := sum_of_waiting_times / real(number_of_tokens_released);
+                            variable std_dev_of_waiting_times : real
+                              := sqrt ( ( sum_of_squares_of_waiting_times
+                                          - sum_of_waiting_times**2 / real(number_of_tokens_released) )
+                                        / real( number_of_tokens_released - 1 ) );
+                          begin
+                            write(L, string'("Summary information for queue "));
+                            write(L, name);
+                            write(L, string'(" up to time "));
+                            write(L, now, unit => time_unit);
+                            writeline(info_file, L);
+                            write(L, string'("  Number of tokens currently waiting = "));
+                            write(L, natural(current_queue_size));
+                            writeline(info_file, L);
+                            write(L, string'("  Number of tokens released = "));
+                            write(L, natural(number_of_tokens_released));
+                            writeline(info_file, L);
+                            write(L, string'("  Maximum queue size = "));
+                            write(L, natural(maximum_queue_size));
+                            writeline(info_file, L);
+                            write(L, string'("  Mean waiting time = "));
+                            write(L, mean_waiting_time * time_unit, unit => time_unit);
+                            writeline(info_file, L);
+                            write(L, string'("  Standard deviation of waiting times = "));
+                            write(L, std_dev_of_waiting_times * time_unit, unit => time_unit);
+                            writeline(info_file, L);
+                            writeline(info_file, L);
+                          end procedure write_summary;
+
+                          procedure write_trace_enqueue is
+                          begin
+                            write(L, string'("Queue "));
+                            write(L, name);
+                            write(L, string'(": at "));
+                            write(L, now, unit => time_unit);
+                            write(L, string'(" enqueued "));
+                            write(L, waiting_token.token, time_unit);
+                            writeline(info_file, L);
+                          end procedure write_trace_enqueue;
+
+                          procedure write_trace_dequeue is
+                          begin
+                            write(L, string'("Queue "));
+                            write(L, name);
+                            write(L, string'(": at "));
+                            write(L, now, unit => time_unit);
+                            write(L, string'(" dequeued "));
+                            write(L, head_token.token, time_unit);
+                            writeline(info_file, L);
+                          end procedure write_trace_dequeue;
+
+  begin
+    file_open(info_file, info_file_name, write_mode);
+    loop
+      wait on info_detail'transaction, in_arc, out_ready;
+      if info_detail'active and info_detail = summary then
+        write_summary;
+      end if;
+      if in_arc'event then
+        waiting_token := waiting_token_type'( token => in_arc.token,
+                                              time_when_enqueued => now );
+        insert(waiting_token_fifo, waiting_token);
+        current_queue_size := current_queue_size + 1;
+        if current_queue_size > maximum_queue_size then
+          maximum_queue_size := current_queue_size;
+        end if;
+        if info_detail = trace then
+          write_trace_enqueue;
+        end if;
+      end if;
+      if out_ready and current_queue_size > 0 and not out_token_in_transit then
+	remove(waiting_token_fifo, head_token);
+	current_queue_size := current_queue_size - 1;
+	out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
+			      token => head_token.token );
+	out_token_in_transit := true;
+	number_of_tokens_released := number_of_tokens_released + 1;
+	waiting_time := (now - head_token.time_when_enqueued) / time_unit;
+	sum_of_waiting_times := sum_of_waiting_times + real(waiting_time);
+        sum_of_squares_of_waiting_times := sum_of_squares_of_waiting_times
+                                           + real(waiting_time) ** 2;
+        if info_detail = trace then
+          write_trace_dequeue;
+        end if;
+      end if;
+      if out_token_in_transit and not out_ready then
+	out_token_in_transit := false;
+      end if;
+    end loop;
+  end process queue_manager;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue.vhd
new file mode 100644
index 0000000..abb1891
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_queue.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_queue.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+use qsim.qsim_types.all;
+
+entity queue is
+
+  generic ( name : string;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( in_arc : in arc_type;
+	 out_arc : out arc_type;
+	 out_ready : in boolean;
+         info_detail : in info_detail_type );
+
+end entity queue;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random-b.vhd
new file mode 100644
index 0000000..0c15b6c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random-b.vhd
@@ -0,0 +1,155 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_random-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library math;
+
+package body random is
+
+  use math.math_real;
+
+  constant sample_seeds : seed_array(0 to 50)
+    := (  0 => (1, 1),
+          1 => (1919456777, 2006618587),
+          2 => (928906921, 476680813),
+          3 => (715788085, 762347824),
+          4 => (366002668, 1804336679),
+          5 => (1866585254, 247488051),
+          6 => (1342990589, 1539624735),
+          7 => (677313287, 1675609237),
+          8 => (644816519, 2026475269),
+          9 => (1654953611, 564421524),
+          10 => (1020104619, 712556314),
+          11 => (609798541, 1592526288),
+          12 => (1106087470, 1468242308),
+          13 => (1378844312, 646793513),
+          14 => (966261604, 481733031),
+          15 => (1407842093, 1316990206),
+          16 => (1705378215, 1930221363),
+          17 => (206887499, 1810320799),
+          18 => (1681633030, 2114795480),
+          19 => (71194926, 1642522201),
+          20 => (663275331, 1947299255),
+          21 => (224432387, 944962866),
+          22 => (1156075861, 1866435087),
+          23 => (1670357576, 1247152991),
+          24 => (846934138, 1673364736),
+          25 => (1972636955, 1404522710),
+          26 => (533484185, 592078395),
+          27 => (1989468008, 1409246301),
+          28 => (697086615, 1975145057),
+          29 => (111393259, 1673620688),
+          30 => (1352201163, 872947497),
+          31 => (1342844190, 877696585),
+          32 => (938770066, 1222894811),
+          33 => (1144599578, 661919919),
+          34 => (1750521407, 269946538),
+          35 => (457892500, 1256953520),
+          36 => (1678589945, 356027520),
+          37 => (1484458924, 2103068828),
+          38 => (1296978761, 2124096638),
+          39 => (1702642440, 1161000593),
+          40 => (1244690090, 2016422304),
+          41 => (1858682943, 1053836731),
+          42 => (1496964676, 701079294),
+          43 => (432696952, 602526767),
+          44 => (2097684438, 1264032473),
+          45 => (2115456834, 298917738),
+          46 => (432301768, 232430346),
+          47 => (1929812456, 758157910),
+          48 => (1655564027, 1062345086),
+          49 => (1116121051, 538424126),
+          50 => (844396720, 821616997) );
+
+
+  procedure init_fixed ( random_info : out random_info_record;
+                         mean : in real ) is
+  begin
+    random_info.distribution := fixed;
+    random_info.mean := mean;
+  end procedure init_fixed;
+
+
+  procedure init_uniform ( random_info : out random_info_record;
+                           lower_bound, upper_bound : in real;
+                           seed : in seed_type ) is
+  begin
+    assert lower_bound <= upper_bound
+                          report "init_uniform: lower_bound > upper_bound" severity failure;
+    random_info.distribution := uniform;
+    random_info.lower_bound := lower_bound;
+    random_info.upper_bound := upper_bound;
+    random_info.seed := seed;
+  end procedure init_uniform;
+
+
+  procedure init_exponential ( random_info : out random_info_record;
+                               mean : in real;
+                               seed : in seed_type ) is
+  begin
+    assert mean > 0.0
+      report "init_exponential: mean not positive" severity failure;
+    random_info.distribution := exponential;
+    random_info.mean := mean;
+    random_info.seed := seed;
+  end procedure init_exponential;
+
+
+  procedure generate_uniform ( random_info : inout random_info_record;
+                               random_number : out real ) is
+    variable tmp : real;
+  begin
+    math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
+    random_number := random_info.lower_bound
+                     + tmp * (random_info.upper_bound - random_info.lower_bound);
+  end procedure generate_uniform;
+
+
+  procedure generate_exponential ( random_info : inout random_info_record;
+                                   random_number : out real ) is
+    variable tmp : real;
+  begin
+    loop
+      math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
+      exit when tmp /= 0.0;
+    end loop;
+    random_number := - random_info.mean * math_real.log(tmp);
+  end procedure generate_exponential;
+
+
+  procedure generate_random ( random_info : inout random_info_record;
+                              random_number : out real ) is
+  begin
+    case random_info.distribution is
+      when fixed =>
+        random_number := random_info.mean;
+      when uniform =>
+        generate_uniform(random_info, random_number);
+      when exponential =>
+        generate_exponential(random_info, random_number);
+    end case;
+  end procedure generate_random;
+
+end package body random;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random.vhd
new file mode 100644
index 0000000..445b38d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_random.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_random.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package random is
+
+  type distribution_type is (fixed, uniform, exponential);
+
+  subtype probability is real range 0.0 to 1.0;
+
+  type probability_vector is array (positive range <>) of probability;
+
+  type seed_type is record
+                      seed1, seed2 : positive;
+                    end record seed_type;
+  type seed_array is array ( natural range <> ) of seed_type;
+  constant sample_seeds : seed_array(0 to 50);
+
+  type random_info_record is record
+                               seed : seed_type;
+                               distribution : distribution_type;
+                               mean : real;
+                               lower_bound, upper_bound : real;
+                             end record random_info_record;
+
+
+  procedure init_fixed ( random_info : out random_info_record;
+                         mean : in real );
+
+  procedure init_uniform ( random_info : out random_info_record;
+                           lower_bound, upper_bound : in real;
+                           seed : in seed_type );
+
+  procedure init_exponential ( random_info : out random_info_record;
+                               mean : in real;
+                               seed : in seed_type );
+
+  procedure generate_random ( random_info : inout random_info_record;
+                              random_number : out real );
+
+end package random;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink-b.vhd
new file mode 100644
index 0000000..8efbea0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink-b.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_sink-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library math;
+
+architecture behavior of sink is
+
+begin
+
+  token_consumer : process is
+
+                             variable number_of_tokens_consumed : natural := 0;
+                           variable life_time : real;  -- in time_unit
+                           variable sum_of_life_times : real := 0.0;  -- in time_unit
+                           variable sum_of_squares_of_life_times : real := 0.0;  --in time_unit**2
+
+                           use std.textio.all;
+                           file info_file : text;
+                           variable L : line;
+
+                           use math.math_real.sqrt;
+
+                           procedure write_summary is
+                             variable mean_life_time : real
+                               := sum_of_life_times / real(number_of_tokens_consumed);
+                             variable std_dev_of_life_times : real
+                               := sqrt ( ( sum_of_squares_of_life_times
+                                           - sum_of_life_times**2 / real(number_of_tokens_consumed) )
+                                         / real( number_of_tokens_consumed - 1 ) );
+                           begin
+                             write(L, string'("Summary information for sink "));
+                             write(L, name);
+                             write(L, string'(" up to time "));
+                             write(L, now, unit => time_unit);
+                             writeline(info_file, L);
+                             write(L, string'("  Number of tokens consumed = "));
+                             write(L, natural(number_of_tokens_consumed));
+                             writeline(info_file, L);
+                             write(L, string'("  Mean life_time = "));
+                             write(L, mean_life_time * time_unit, unit => time_unit);
+                             writeline(info_file, L);
+                             write(L, string'("  Standard deviation of life_times = "));
+                             write(L, std_dev_of_life_times * time_unit, unit => time_unit);
+                             writeline(info_file, L);
+                             writeline(info_file, L);
+                           end procedure write_summary;
+
+                           procedure write_trace is
+                           begin
+                             write(L, string'("Sink "));
+                             write(L, name);
+                             write(L, string'(": at "));
+                             write(L, now, unit => time_unit);
+                             write(L, string'(" consumed "));
+                             write(L, in_arc.token, time_unit);
+                             writeline(info_file, L);
+                           end procedure write_trace;
+
+  begin
+    file_open(info_file, info_file_name, write_mode);
+    loop
+      wait on info_detail'transaction, in_arc;
+      if info_detail'active and info_detail = summary then
+        write_summary;
+      end if;
+      if in_arc'event then
+        number_of_tokens_consumed := number_of_tokens_consumed + 1;
+        life_time := real( (now - in_arc.token.creation_time) / time_unit );
+        sum_of_life_times := sum_of_life_times + life_time;
+        sum_of_squares_of_life_times := sum_of_squares_of_life_times + life_time ** 2;
+        if info_detail = trace then
+          write_trace;
+        end if;
+      end if;
+    end loop;
+  end process token_consumer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink.vhd
new file mode 100644
index 0000000..a38d21a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_sink.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_sink.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+use qsim.qsim_types.all;
+
+entity sink is
+
+  generic ( name : string;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( in_arc : in arc_type;
+	 info_detail : in info_detail_type );
+
+end sink;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source-b.vhd
new file mode 100644
index 0000000..0ae94a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source-b.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_source-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library math;
+
+architecture behavior of source is
+
+begin
+
+  token_generator : process is
+
+                              variable source_name : string(1 to name_max_length) := (others => ' ');
+                            variable source_name_length : natural;
+                            variable next_token_id : token_id_type := 0;
+                            variable next_arrival_time : time;
+                            variable number_of_tokens_generated : natural := 0;
+                            variable inter_arrival_time : natural;  -- in time_unit
+                            variable sum_of_inter_arrival_times : real := 0.0;  -- in time_unit
+                            variable sum_of_squares_of_inter_arrival_times : real := 0.0;  --in time_unit**2
+
+                            variable random_info : random_info_record;
+                            variable random_number : real;
+
+                            use std.textio.all;
+                            file info_file : text;
+                            variable L : line;
+
+                            use math.math_real.sqrt;
+
+                            procedure write_summary is
+                              variable measured_mean_inter_arrival_time : real
+                                := sum_of_inter_arrival_times / real(number_of_tokens_generated);
+                              variable measured_std_dev_of_inter_arrival_times : real
+                                := sqrt ( ( sum_of_squares_of_inter_arrival_times
+                                            - sum_of_inter_arrival_times**2 / real(number_of_tokens_generated) )
+                                          / real( number_of_tokens_generated - 1 ) );
+                            begin
+                              write(L, string'("Summary information for source "));
+                              write(L, name);
+                              write(L, string'(" up to time "));
+                              write(L, now, unit => time_unit);
+                              writeline(info_file, L);
+                              write(L, string'("  Inter arrival distribution: "));
+                              write(L, distribution_type'image(distribution));
+                              write(L, string'(" with mean inter arrival time of "));
+                              write(L, mean_inter_arrival_time, unit => time_unit);
+                              writeline(info_file, L);
+                              write(L, string'("  Number of tokens generated = "));
+                              write(L, natural(next_token_id));
+                              writeline(info_file, L);
+                              write(L, string'("  Mean inter arrival time = "));
+                              write(L, measured_mean_inter_arrival_time * time_unit, unit => time_unit);
+                              writeline(info_file, L);
+                              write(L, string'("  Standard deviation of inter arrival times = "));
+                              write(L, measured_std_dev_of_inter_arrival_times * time_unit, unit => time_unit);
+                              writeline(info_file, L);
+                              writeline(info_file, L);
+                            end procedure write_summary;
+
+                            procedure write_trace is
+                            begin
+                              write(L, string'("Source "));
+                              write(L, name);
+                              write(L, string'(": at "));
+                              write(L, now, unit => time_unit);
+                              write(L, string'(" generated token "));
+                              write(L, natural(next_token_id));
+                              writeline(info_file, L);
+                            end procedure write_trace;
+
+  begin
+    if name'length > name_max_length then
+      source_name := name(1 to name_max_length);
+      source_name_length := name_max_length;
+    else
+      source_name(1 to name'length) := name;
+      source_name_length := name'length;
+    end if;
+    file_open(info_file, info_file_name, write_mode);
+
+    case distribution is
+      when fixed =>
+        init_fixed(random_info, real(mean_inter_arrival_time / time_unit));
+      when uniform =>
+        init_uniform( random_info,
+                      lower_bound => 0.0,
+                      upper_bound => 2.0 * real(mean_inter_arrival_time / time_unit),
+                      seed => seed );
+      when exponential =>
+        init_exponential( random_info,
+                          mean => real(mean_inter_arrival_time / time_unit),
+                          seed => seed );
+    end case;
+
+    loop
+      generate_random(random_info, random_number);
+      inter_arrival_time :=  natural(random_number);
+      next_arrival_time := inter_arrival_time * time_unit + now;
+      loop
+        wait on info_detail'transaction for next_arrival_time - now;
+        if info_detail'active and info_detail = summary then
+          write_summary;
+        end if;
+        exit when next_arrival_time = now;
+      end loop;
+      out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
+		            token => token_type'( source_name => source_name,
+                                                  source_name_length => source_name_length,
+                                                  id => next_token_id,
+                                                  creation_time => now ) );
+      number_of_tokens_generated := number_of_tokens_generated + 1;
+      sum_of_inter_arrival_times := sum_of_inter_arrival_times
+                                    + real(inter_arrival_time);
+      sum_of_squares_of_inter_arrival_times := sum_of_squares_of_inter_arrival_times
+                                               + real(inter_arrival_time) ** 2;
+
+      if info_detail = trace then
+        write_trace;
+      end if;
+      next_token_id := next_token_id + 1;
+    end loop;
+  end process token_generator;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source.vhd
new file mode 100644
index 0000000..784b2e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_source.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_source.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use qsim.qsim_types.all, random.random.all;
+
+entity source is
+
+  generic ( name : string;
+            distribution : distribution_type;
+            mean_inter_arrival_time : delay_length;
+            seed : seed_type;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( out_arc : out arc_type;
+         info_detail : in info_detail_type );
+
+end entity source;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr-b.vhd
new file mode 100644
index 0000000..7cb191d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr-b.vhd
@@ -0,0 +1,159 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_srvr-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library math;
+
+architecture behavior of server is
+
+begin
+
+  service : process is
+
+                      variable served_token : token_type;
+                    variable release_time : time;
+                    variable number_of_tokens_served : natural := 0;
+                    variable service_time : natural;  -- in time_unit
+                    variable sum_of_service_times : real := 0.0;  -- in time_unit
+                    variable sum_of_squares_of_service_times : real := 0.0;  --in time_unit**2
+
+                    variable random_info : random_info_record;
+                    variable random_number : real;
+
+                    use std.textio.all;
+                    file info_file : text;
+                    variable L : line;
+
+                    use math.math_real.sqrt;
+
+                    procedure write_summary is
+                      variable measured_mean_service_time : real
+                        := sum_of_service_times / real(number_of_tokens_served);
+                      variable measured_std_dev_of_service_times : real
+                        := sqrt ( ( sum_of_squares_of_service_times
+                                    - sum_of_service_times**2 / real(number_of_tokens_served) )
+                                  / real( number_of_tokens_served - 1 ) );
+                    begin
+                      write(L, string'("Summary information for server "));
+                      write(L, name);
+                      write(L, string'(" up to time "));
+                      write(L, now, unit => time_unit);
+                      writeline(info_file, L);
+                      write(L, string'("  Service distribution: "));
+                      write(L, distribution_type'image(distribution));
+                      write(L, string'(" with mean service time of "));
+                      write(L, mean_service_time, unit => time_unit);
+                      writeline(info_file, L);
+                      write(L, string'("  Number of tokens served = "));
+                      write(L, natural(number_of_tokens_served));
+                      writeline(info_file, L);
+                      write(L, string'("  Mean service time = "));
+                      write(L, measured_mean_service_time * time_unit, unit => time_unit);
+                      writeline(info_file, L);
+                      write(L, string'("  Standard deviation of service times = "));
+                      write(L, measured_std_dev_of_service_times * time_unit, unit => time_unit);
+                      writeline(info_file, L);
+                      write(L, string'("  Utilization = "));
+                      write(L, sum_of_service_times / real(now / time_unit), digits => 4);
+                      writeline(info_file, L);
+                      writeline(info_file, L);
+                    end procedure write_summary;
+
+                    procedure write_trace_service is
+                    begin
+                      write(L, string'("Server "));
+                      write(L, name);
+                      write(L, string'(": at "));
+                      write(L, now, unit => time_unit);
+                      write(L, string'(" served "));
+                      write(L, in_arc.token, time_unit);
+                      writeline(info_file, L);
+                    end procedure write_trace_service;
+
+                    procedure write_trace_release is
+                    begin
+                      write(L, string'("Server "));
+                      write(L, name);
+                      write(L, string'(": at "));
+                      write(L, now, unit => time_unit);
+                      write(L, string'(" released "));
+                      write(L, served_token, time_unit);
+                      writeline(info_file, L);
+                    end procedure write_trace_release;
+
+  begin
+    file_open(info_file, info_file_name, write_mode);
+
+    case distribution is
+      when fixed =>
+        init_fixed(random_info, real(mean_service_time / time_unit));
+      when uniform =>
+        init_uniform( random_info,
+                      lower_bound => 0.0,
+                      upper_bound => 2.0 * real(mean_service_time / time_unit),
+                      seed => seed );
+      when exponential =>
+        init_exponential( random_info,
+                          mean => real(mean_service_time / time_unit),
+                          seed => seed );
+    end case;
+
+    in_ready <= true;
+    loop
+      wait on info_detail'transaction, in_arc;
+      if info_detail'active and info_detail = summary then
+        write_summary;
+      end if;
+      if in_arc'event then
+	in_ready <= false;
+        if info_detail = trace then
+          write_trace_service;
+        end if;
+        served_token := in_arc.token;
+        generate_random(random_info, random_number);
+        service_time :=  natural(random_number);
+        release_time := service_time * time_unit + now;
+        loop
+          wait on info_detail'transaction for release_time - now;
+          if info_detail'active and info_detail = summary then
+            write_summary;
+          end if;
+          exit when release_time = now;
+        end loop;
+	in_ready <= true;
+	out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
+			      token => served_token );
+        number_of_tokens_served := number_of_tokens_served + 1;
+        sum_of_service_times := sum_of_service_times + real(service_time);
+        sum_of_squares_of_service_times := sum_of_squares_of_service_times
+                                           + real(service_time) ** 2;
+        if info_detail = trace then
+          write_trace_release;
+        end if;
+      end if;
+    end loop;
+  end process service;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr.vhd
new file mode 100644
index 0000000..f68fbcc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_srvr.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_srvr.vhd,v 1.5 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.5 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random
+
+  use qsim.qsim_types.all, random.random.all;
+
+entity server is
+
+  generic ( name : string;
+            distribution : distribution_type;
+            mean_service_time : time;
+            seed : seed_type;
+            time_unit : delay_length := ns;
+            info_file_name : string := "info_file.dat" );
+
+  port ( in_arc : in arc_type;
+         in_ready : out boolean;
+         out_arc : out arc_type;
+         info_detail : in info_detail_type );
+
+end entity server;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-frk.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-frk.vhd
new file mode 100644
index 0000000..a96811c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-frk.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-frk.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use std.textio.all;
+
+architecture fork of test_bench is
+
+  use qsim.qsim_types.all;
+  use random.random.all;
+
+  constant num_outputs : positive := 4;
+  constant probabilities : probability_vector(1 to num_outputs - 1)
+    := ( 0.2, 0.4, 0.1 );
+
+  signal source_arc : arc_type;
+  signal fork_arc : arc_vector(1 to num_outputs);
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  source1 : entity qsim.source(behavior)
+    generic map ( name => "source1",
+                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
+                  seed => sample_seeds(1),
+                  time_unit => ns,
+                  info_file_name => "source1.dat" )
+    port map ( out_arc => source_arc,
+	       info_detail => info_detail );
+
+  fork1 : entity qsim.fork(behavior)
+    generic map ( name => "fork1",
+                  probabilities => probabilities,
+                  seed => sample_seeds(2),
+                  time_unit => ns,
+                  info_file_name => "fork1.dat" )
+    port map ( in_arc => source_arc,
+	       out_arc => fork_arc,
+               info_detail => info_detail );
+
+
+  source_monitor : process is
+                             variable L : line;
+  begin
+    wait on source_arc;
+    write(L, string'("source_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, source_arc.token, ns);
+    writeline(output, L);
+  end process source_monitor;
+
+
+  sinks : for index in 1 to num_outputs generate
+
+    constant index_string : string := integer'image(index);
+
+  begin
+
+    sink : entity qsim.sink(behavior)
+      generic map ( name => "sink" & index_string,
+                    time_unit => ns,
+                    info_file_name => "sink" & index_string & ".dat" )
+      port map ( in_arc => fork_arc(index),
+		 info_detail => info_detail );
+
+    sink_monitor : process
+      variable L : line;
+    begin
+      wait on fork_arc(index);
+      write(L, string'("sink_monitor(" & index_string & "): at "));
+      write(L, now, unit => ns);
+      write(L, string'(", "));
+      write(L, fork_arc(index).token, ns);
+      writeline(output, L);
+    end process sink_monitor;
+
+  end generate sinks;
+
+
+end architecture fork;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jn.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jn.vhd
new file mode 100644
index 0000000..45ac083
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jn.vhd
@@ -0,0 +1,128 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-jn.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use std.textio.all;
+
+architecture join of test_bench is
+
+  use qsim.qsim_types.all;
+  use random.random.all;
+
+  constant num_outputs : positive := 4;
+  constant probabilities : probability_vector(1 to num_outputs - 1)
+    := ( 0.2, 0.4, 0.1 );
+
+  signal source_arc, join_arc : arc_type;
+  signal fork_arc : arc_vector(1 to num_outputs);
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  source1 : entity qsim.source(behavior)
+    generic map ( name => "source1",
+                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
+                  seed => sample_seeds(1),
+                  time_unit => ns,
+                  info_file_name => "source1.dat" )
+    port map ( out_arc => source_arc,
+               info_detail => info_detail );
+
+  fork1 : entity qsim.fork(behavior)
+    generic map ( name => "fork1",
+                  probabilities => probabilities,
+                  seed => sample_seeds(2),
+                  time_unit => ns,
+                  info_file_name => "fork1.dat" )
+    port map ( in_arc => source_arc,
+               out_arc => fork_arc,
+               info_detail => info_detail );
+
+
+  join1 : entity qsim.join(behavior)
+    generic map ( name => "join1",
+                  time_unit => ns,
+                  info_file_name => "join1.dat" )
+    port map ( in_arc => fork_arc,
+               out_arc => join_arc,
+               info_detail => info_detail );
+
+
+  sink1 : entity qsim.sink(behavior)
+    generic map ( name => "sink1",
+                  time_unit => ns,
+                  info_file_name => "sink1.dat" )
+    port map ( in_arc => join_arc,
+               info_detail => info_detail );
+
+
+  source_monitor : process is
+                             variable L : line;
+  begin
+    wait on source_arc;
+    write(L, string'("source_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, source_arc.token, ns);
+    writeline(output, L);
+  end process source_monitor;
+
+
+  forks : for index in 1 to num_outputs generate
+
+    constant index_string : string := integer'image(index);
+
+  begin
+
+    fork_monitor : process
+      variable L : line;
+    begin
+      wait on fork_arc(index);
+      write(L, string'("fork_monitor(" & index_string & "): at "));
+      write(L, now, unit => ns);
+      write(L, string'(", "));
+      write(L, fork_arc(index).token, ns);
+      writeline(output, L);
+    end process fork_monitor;
+
+  end generate forks;
+
+
+  sink_monitor : process
+    variable L : line;
+  begin
+    wait on join_arc;
+    write(L, string'("sink_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, join_arc.token, ns);
+    writeline(output, L);
+  end process sink_monitor;
+
+
+end architecture join;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jnsth.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jnsth.vhd
new file mode 100644
index 0000000..f80fd52
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-jnsth.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-jnsth.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+use std.textio.all;
+
+architecture join_synth of test_bench is
+
+  use qsim.qsim_types.all;
+
+  constant num_outputs : positive := 4;
+
+  signal fork_arc : arc_vector(1 to num_outputs);
+  signal join_arc : arc_type;
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  generator : process is
+  begin
+    fork_arc(1) <= (true,  ("generator           ", 9,  0, now));
+    fork_arc(2) <= (true,  ("generator           ", 9,  1, now));    wait for 0 ns;
+    fork_arc(3) <= (true,  ("generator           ", 9,  2, now));
+    fork_arc(4) <= (true,  ("generator           ", 9,  3, now));    wait for 10 ns;
+
+    fork_arc(1) <= (false, ("generator           ", 9,  4, now));
+    fork_arc(2) <= (false, ("generator           ", 9,  5, now));    wait for 0 ns;
+    fork_arc(3) <= (false, ("generator           ", 9,  6, now));
+    fork_arc(4) <= (false, ("generator           ", 9,  7, now));    wait for 0 ns;
+    fork_arc(1) <= (true,  ("generator           ", 9,  8, now));
+    fork_arc(2) <= (true,  ("generator           ", 9,  9, now));    wait for 0 ns;
+    fork_arc(3) <= (true,  ("generator           ", 9, 10, now));
+    fork_arc(4) <= (true,  ("generator           ", 9, 11, now));    wait for 0 ns;
+    fork_arc(1) <= (false, ("generator           ", 9, 12, now));
+    fork_arc(2) <= (false, ("generator           ", 9, 13, now));    wait for 0 ns;
+    fork_arc(3) <= (false, ("generator           ", 9, 14, now));
+    fork_arc(4) <= (false, ("generator           ", 9, 15, now));    wait for 10 ns;
+
+    wait;
+  end process generator;
+
+  join1 : entity qsim.join(behavior)
+    generic map ( name => "join1",
+                  time_unit => ns,
+                  info_file_name => "join1.dat" )
+    port map ( in_arc => fork_arc,
+               out_arc => join_arc,
+               info_detail => info_detail );
+
+
+  sink1 : entity qsim.sink(behavior)
+    generic map ( name => "sink1",
+                  time_unit => ns,
+                  info_file_name => "sink1.dat" )
+    port map ( in_arc => join_arc,
+               info_detail => info_detail );
+
+
+  forks : for index in 1 to num_outputs generate
+
+    constant index_string : string := integer'image(index);
+
+  begin
+
+    fork_monitor : process
+      variable L : line;
+    begin
+      wait on fork_arc(index);
+      write(L, string'("fork_monitor(" & index_string & "): at "));
+      write(L, now, unit => ns);
+      write(L, string'(", "));
+      write(L, fork_arc(index).token, ns);
+      writeline(output, L);
+    end process fork_monitor;
+
+  end generate forks;
+
+
+  sink_monitor : process
+    variable L : line;
+  begin
+    wait on join_arc;
+    write(L, string'("sink_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, join_arc.token, ns);
+    writeline(output, L);
+  end process sink_monitor;
+
+
+end architecture join_synth;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-qs.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-qs.vhd
new file mode 100644
index 0000000..923f692
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-qs.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-qs.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use std.textio.all;
+
+architecture queue_server of test_bench is
+
+  use qsim.qsim_types.all;
+  use random.random.all;
+
+  signal source_arc, queue_arc, server_arc : arc_type;
+  signal server_ready : boolean;
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  source1 : entity qsim.source(behavior)
+    generic map ( name => "source1",
+                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
+                  seed => sample_seeds(1),
+                  time_unit => ns,
+                  info_file_name => "source1.dat" )
+    port map ( out_arc => source_arc,
+               info_detail => info_detail );
+
+  queue1 : entity qsim.queue(behavior)
+    generic map ( name => "queue1",
+                  time_unit => ns,
+                  info_file_name => "queue1.dat" )
+    port map ( in_arc => source_arc,
+               out_arc => queue_arc,  out_ready => server_ready,
+               info_detail => info_detail );
+
+  server1 : entity qsim.server(behavior)
+    generic map ( name => "server1",
+                  distribution => fixed,  mean_service_time => 120 ns,
+                  seed => sample_seeds(2),
+                  time_unit => ns,
+                  info_file_name => "server1.dat" )
+    port map ( in_arc => queue_arc,  in_ready => server_ready,
+               out_arc => server_arc,
+               info_detail => info_detail );
+
+  sink1 : entity qsim.sink(behavior)
+    generic map ( name => "sink1",
+                  time_unit => ns,
+                  info_file_name => "sink1.dat" )
+    port map ( in_arc => server_arc,
+               info_detail => info_detail );
+
+
+  source_monitor : process is
+                             variable L : line;
+  begin
+    wait on source_arc;
+    write(L, string'("source_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, source_arc.token, ns);
+    writeline(output, L);
+  end process source_monitor;
+
+  queue_monitor : process is
+                            variable L : line;
+  begin
+    wait on queue_arc;
+    write(L, string'("queue_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, queue_arc.token, ns);
+    writeline(output, L);
+  end process queue_monitor;
+
+  server_monitor : process is
+                             variable L : line;
+  begin
+    wait on server_arc;
+    write(L, string'("server_monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(", "));
+    write(L, server_arc.token, ns);
+    writeline(output, L);
+  end process server_monitor;
+
+
+end architecture queue_server;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-snk.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-snk.vhd
new file mode 100644
index 0000000..45e86ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-snk.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-snk.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use std.textio.all;
+
+architecture sink of test_bench is
+
+  use qsim.qsim_types.all;
+  use random.random.all;
+
+  signal a : arc_type;
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  source1 : entity qsim.source(behavior)
+    generic map ( name => "source1",
+                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
+                  seed => sample_seeds(1),
+                  time_unit => ns,
+                  info_file_name => "source1.dat" )
+    port map ( out_arc => a,
+               info_detail => info_detail );
+
+  sink1 : entity qsim.sink(behavior)
+    generic map ( name => "sink1",
+                  time_unit => ns,
+                  info_file_name => "sink1.dat" )
+    port map ( in_arc => a,
+               info_detail => info_detail );
+
+  monitor : process is
+
+                      variable L : line;
+
+  begin
+    wait on a;
+    write(L, string'("monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(" received "));
+    write(L, a.token, ns);
+    writeline(output, L);
+  end process monitor;
+
+end architecture sink;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-src.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-src.vhd
new file mode 100644
index 0000000..865ed89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb-src.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb-src.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+library random;
+
+use std.textio.all;
+use qsim.qsim_types.all;
+use random.random.all;
+
+architecture source of test_bench is
+
+  signal a : arc_type;
+  signal info_detail : info_detail_type := trace;
+
+begin
+
+  source1 : entity qsim.source(behavior)
+    generic map ( name => "source1",
+                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
+                  seed => sample_seeds(0),
+                  time_unit => ns,
+                  info_file_name => "source1.dat" )
+    port map ( out_arc => a,
+               info_detail => info_detail );
+
+  monitor : process is
+
+                      variable L : line;
+
+  begin
+    wait on a;
+    write(L, string'("monitor: at "));
+    write(L, now, unit => ns);
+    write(L, string'(" received "));
+    write(L, a.token, ns);
+    writeline(output, L);
+  end process monitor;
+
+end architecture source;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb.vhd
new file mode 100644
index 0000000..7358b25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tb.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tb.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity test_bench is
+
+end entity test_bench;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo-b.vhd
new file mode 100644
index 0000000..5c00f14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo-b.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tkfifo-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+package body token_fifo_adt is
+
+  function new_fifo return fifo_type is
+  begin
+    return new fifo_record'( null, null );
+  end function new_fifo;
+
+
+  procedure test_empty ( variable fifo : in fifo_type;
+                         variable is_empty : out boolean ) is
+  begin
+    is_empty := fifo.head_entry = null;
+  end procedure test_empty;
+
+
+  procedure insert ( fifo : inout fifo_type;
+                     element : in element_type ) is
+
+    variable new_entry : fifo_entry
+      := new fifo_entry_record'( next_entry => null,
+                                 element => element );
+  begin
+    if fifo.tail_entry /= null then
+      fifo.tail_entry.next_entry := new_entry;
+    else
+      fifo.head_entry := new_entry;
+    end if;
+    fifo.tail_entry := new_entry;
+  end procedure insert;
+
+
+  procedure remove ( fifo : inout fifo_type;
+                     element : out element_type ) is
+    variable empty_fifo : boolean;
+    variable removed_entry : fifo_entry;
+  begin
+    test_empty(fifo, empty_fifo);
+    if empty_fifo then
+      report "remove from empty fifo" severity failure;
+    else
+      removed_entry := fifo.head_entry;
+      element := removed_entry.element;
+      fifo.head_entry := removed_entry.next_entry;
+      if fifo.head_entry = null then  -- fifo now empty
+        fifo.tail_entry := null;
+      end if;
+      deallocate(removed_entry);
+    end if;
+  end procedure remove;
+
+end package body token_fifo_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo.vhd
new file mode 100644
index 0000000..06f2b00
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_tkfifo.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+package token_fifo_adt is
+
+  alias element_type is qsim.qsim_types.token_type;
+
+  type fifo_record;
+
+  type fifo_type is access fifo_record;
+
+  function new_fifo return fifo_type;
+
+  procedure test_empty ( variable fifo : in fifo_type;
+                         variable is_empty : out boolean );
+
+  procedure insert ( fifo : inout fifo_type;
+                     element : in element_type );
+
+  procedure remove ( fifo : inout fifo_type;
+                     element : out element_type );
+
+  -- private types
+
+  type fifo_entry_record;
+
+  type fifo_entry is access fifo_entry_record;
+
+  type fifo_entry_record is record
+                              next_entry : fifo_entry;
+                              element : element_type;
+                            end record;
+
+  type fifo_record is record
+                        head_entry, tail_entry : fifo_entry;
+                      end record;
+
+end package token_fifo_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo-b.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo-b.vhd
new file mode 100644
index 0000000..93618fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo-b.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_wtfifo-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+package body waiting_token_fifo_adt is
+
+  function new_fifo return fifo_type is
+  begin
+    return new fifo_record'( null, null );
+  end function new_fifo;
+
+
+  procedure test_empty ( variable fifo : in fifo_type;
+                         variable is_empty : out boolean ) is
+  begin
+    is_empty := fifo.head_entry = null;
+  end procedure test_empty;
+
+
+  procedure insert ( fifo : inout fifo_type;
+                     element : in element_type ) is
+
+    variable new_entry : fifo_entry
+      := new fifo_entry_record'( next_entry => null,
+                                 element => element );
+  begin
+    if fifo.tail_entry /= null then
+      fifo.tail_entry.next_entry := new_entry;
+    else
+      fifo.head_entry := new_entry;
+    end if;
+    fifo.tail_entry := new_entry;
+  end procedure insert;
+
+
+  procedure remove ( fifo : inout fifo_type;
+                     element : out element_type ) is
+    variable empty_fifo : boolean;
+    variable removed_entry : fifo_entry;
+  begin
+    test_empty(fifo, empty_fifo);
+    if empty_fifo then
+      report "remove from empty fifo" severity failure;
+    else
+      removed_entry := fifo.head_entry;
+      element := removed_entry.element;
+      fifo.head_entry := removed_entry.next_entry;
+      if fifo.head_entry = null then  -- fifo now empty
+        fifo.tail_entry := null;
+      end if;
+      deallocate(removed_entry);
+    end if;
+  end procedure remove;
+
+end package body waiting_token_fifo_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo.vhd
new file mode 100644
index 0000000..5da8d94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_19_wtfifo.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_19_wtfifo.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library qsim;
+
+package waiting_token_fifo_adt is
+
+  alias element_type is qsim.queue_types.waiting_token_type;
+
+  type fifo_record;
+
+  type fifo_type is access fifo_record;
+
+  function new_fifo return fifo_type;
+
+  procedure test_empty ( variable fifo : in fifo_type;
+                         variable is_empty : out boolean );
+
+  procedure insert ( fifo : inout fifo_type;
+                     element : in element_type );
+
+  procedure remove ( fifo : inout fifo_type;
+                     element : out element_type );
+
+  -- private types
+
+  type fifo_entry_record;
+
+  type fifo_entry is access fifo_entry_record;
+
+  type fifo_entry_record is record
+                              next_entry : fifo_entry;
+                              element : element_type;
+                            end record;
+
+  type fifo_record is record
+                        head_entry, tail_entry : fifo_entry;
+                      end record;
+
+end package waiting_token_fifo_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_01.vhd
new file mode 100644
index 0000000..50ae344
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_01.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package utility_definitions is
+
+  constant word_size : natural := 16;
+
+end package utility_definitions;
+
+
+----------------------------------------------------------------
+
+
+library utilities;
+
+entity ch_20_01 is
+
+end entity ch_20_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_20_01 is
+begin
+
+
+  process is
+  begin
+
+    report
+
+      -- code from book:
+
+      utilities.utility_definitions.word_size'simple_name
+
+      -- end of code from book
+
+      ;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_02.vhd
new file mode 100644
index 0000000..fddabba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_02.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library project;
+
+entity ch_20_02 is
+end entity ch_20_02;
+
+
+architecture test of ch_20_02 is
+begin
+
+  process is
+
+            --use project.mem_pkg;
+            --use project.mem_pkg.all;
+            use work.mem_pkg;
+          use work.mem_pkg.all;
+          variable words : word_array(0 to 3);
+
+  begin
+    assert
+      -- code from book (in text)
+      mem_pkg'path_name = ":project:mem_pkg:"
+      -- end code from book
+      ;
+    report mem_pkg'path_name;
+
+    assert
+      -- code from book (in text)
+      word'path_name = ":project:mem_pkg:word"
+      -- end code from book
+      ;
+    report word'path_name;
+
+    assert
+      -- code from book (in text)
+      word_array'path_name = ":project:mem_pkg:word_array"
+      -- end code from book
+      ;
+
+    report word_array'path_name;
+
+    assert
+      -- code from book (in text)
+      load_array'path_name = ":project:mem_pkg:load_array"
+      -- end code from book
+      ;
+    report load_array'path_name;
+
+    load_array(words, "/dev/null");
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_03.vhd
new file mode 100644
index 0000000..3b1a3b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_03.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_20_03_a is
+
+  -- code from book:
+
+  attribute cell_name : string;
+  attribute pin_number : positive;
+  attribute max_wire_delay : delay_length;
+  attribute encoding : bit_vector;
+
+
+  type length is range 0 to integer'high
+    units nm;
+          um = 1000 nm;
+          mm = 1000 um;
+          mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+                       x, y : length;
+                     end record coordinate;
+
+  attribute cell_position : coordinate;
+
+  -- end of code from book
+
+end package ch_20_03_a;
+
+
+
+
+entity ch_20_03 is
+
+end entity ch_20_03;
+
+
+----------------------------------------------------------------
+
+
+architecture std_cell of ch_20_03 is
+
+  use work.ch_20_03_a.all;
+
+  signal enable, clk : bit;
+
+  type state_type is (idle_state, other_state);
+
+  -- code from book:
+
+  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+  attribute pin_number of enable : signal is 14;
+  attribute max_wire_delay of clk : signal is 50 ps;
+  attribute encoding of idle_state : literal is b"0000";
+  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+
+  -- end of code from book
+
+begin
+
+  the_fpu : block is
+  begin
+  end block the_fpu;
+
+  process is
+            use std.textio.all;
+          variable L : line;
+  begin
+    write(L, std_cell'cell_name);
+    writeline(output, L);
+    write(L, enable'pin_number);
+    writeline(output, L);
+    write(L, clk'max_wire_delay);
+    writeline(output, L);
+    write(L, idle_state[return state_type]'encoding);
+    writeline(output, L);
+    write(L, length'image(the_fpu'cell_position.x));
+    write(L, ' ');
+    write(L, length'image(the_fpu'cell_position.y));
+    writeline(output, L);
+
+    wait;
+  end process;
+
+end architecture std_cell;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_04.vhd
new file mode 100644
index 0000000..b8934d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_04.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_04.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_20_04 is
+
+  attribute cell_name : string;
+
+end package ch_20_04;
+
+
+
+entity flipflop is
+
+end entity flipflop;
+
+
+
+use work.ch_20_04.all;
+
+-- code from book:
+
+architecture std_cell of flipflop is
+
+  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+
+  -- . . .       -- other declarations
+
+begin
+  -- . . .
+end architecture std_cell;
+
+-- end of code from book
+
+
+
+-- code from book:
+
+package model_utilities is
+
+  attribute optimize : string;
+  attribute optimize of model_utilities : package is "level_4";
+
+  -- . . .
+
+end package model_utilities;
+
+-- end of code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_05.vhd
new file mode 100644
index 0000000..7e46ff3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_05.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_20_05 is
+
+end entity ch_20_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_20_05 is
+
+  type stimulus_list is array (natural range <>) of integer;
+
+  -- code from book:
+
+  function "&" ( a, b : stimulus_list ) return stimulus_list;
+
+  attribute debug : string;
+  attribute debug of
+    "&" [ stimulus_list, stimulus_list return stimulus_list ] : function is
+    "source_statement_step";
+
+
+    type mvl is ('X', '0', '1', 'Z');
+    type mvl_vector is array ( integer range <>) of mvl;
+    function resolve_mvl ( drivers : mvl_vector ) return mvl;
+
+    subtype resolved_mvl is resolve_mvl mvl;
+
+
+    type builtin_types is (builtin_bit, builtin_mvl, builtin_integer);
+    attribute builtin : builtin_types;
+    
+    attribute builtin of resolved_mvl : subtype is builtin_mvl;
+
+    -- end of code from book
+
+    function "&" ( a, b : stimulus_list ) return stimulus_list is
+    begin
+      return stimulus_list'(1 to 0 => 0);
+    end function "&";
+
+    function resolve_mvl ( drivers : mvl_vector ) return mvl is
+    begin
+      return drivers(drivers'left);
+    end function resolve_mvl;
+
+  begin
+  end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_06.vhd
new file mode 100644
index 0000000..549f606
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_06.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_20_06 is
+
+end entity ch_20_06;
+
+
+----------------------------------------------------------------
+
+use std.textio.all;
+
+architecture test of ch_20_06 is
+
+  subtype encoding_type is bit_vector(1 downto 0);
+  attribute encoding : encoding_type;
+
+begin
+
+
+  process1 : process is
+
+                       -- code from book:
+
+                       type controller_state is (idle, active, fail_safe);
+                     type load_level is (idle, busy, overloaded);
+
+                     attribute encoding of idle [ return controller_state ] : literal is b"00";
+                                                                                         attribute encoding of active [ return controller_state ] : literal is b"01";
+                                                                                                                                                               attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
+
+                                                                                                                                                                                                                                        -- end of code from book
+
+                                                                                                                                                                                                                                        variable L : line;
+
+                                                                                                                                                               begin
+                                                                                                                                                                 write(L, string'("process1"));
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 write(L, idle [ return controller_state ] ' encoding);
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 write(L, active [ return controller_state ] ' encoding);
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 write(L, fail_safe [ return controller_state ] ' encoding);
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 wait;
+                                                                                                                                                               end process process1;
+
+
+                                                                                                                                                               process2 : process is
+
+                                                                                                                                                                                    type controller_state is (idle, active, fail_safe);
+                                                                                                                                                                                  type load_level is (idle, busy, overloaded);
+
+                                                                                                                                                                                  attribute encoding of idle : literal is b"11";
+
+                                                                                                                                                                                  variable L : line;
+
+                                                                                                                                                               begin
+                                                                                                                                                                 write(L, string'("process2"));
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 write(L, idle [ return controller_state ] ' encoding);
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 write(L, idle [ return load_level ] ' encoding);
+                                                                                                                                                                 writeline(output, L);
+                                                                                                                                                                 wait;
+                                                                                                                                                               end process process2;
+
+
+                                                                                         end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_07.vhd
new file mode 100644
index 0000000..9253f90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_07.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_20_07 is
+
+end entity ch_20_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_20_07 is
+
+  component multiplier is
+  end component multiplier;
+
+  type length is range 0 to integer'high
+    units nm;
+          um = 1000 nm;
+          mm = 1000 um;
+          mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+                       x, y : length;
+                     end record coordinate;
+
+  type orientation_type is (up, down, left, right);
+
+  attribute cell_allocation : string;
+  attribute cell_position : coordinate;
+  attribute cell_orientation : orientation_type;
+
+  -- code from book:
+
+  attribute cell_allocation of mult : label is "wallace_tree_multiplier";
+  attribute cell_position of mult : label is ( 1200 um, 4500 um );
+  attribute cell_orientation of mult : label is down;
+
+  -- end of code from book
+
+begin
+
+  mult : component multiplier;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_08.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_08.vhd
new file mode 100644
index 0000000..0598e3a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_08.vhd
@@ -0,0 +1,127 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_20_08 is
+
+end entity ch_20_08;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture std_cell of ch_20_08 is
+
+  attribute cell_name : string;
+  attribute pin_number : positive;
+  attribute max_wire_delay : delay_length;
+  attribute encoding : bit_vector;
+
+  type length is range 0 to integer'high
+    units nm;
+          um = 1000 nm;
+          mm = 1000 um;
+          mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+                       x, y : length;
+                     end record coordinate;
+
+  attribute cell_position : coordinate;
+
+  type built_in_type is (bv_incr, std_incr);
+  attribute built_in : built_in_type;
+
+  signal enable, clk : bit;
+
+  type state_type is (idle_state, other_state);
+
+  type speed_range is (high, other_speed);
+  type coolant_level is (high, other_level);
+
+  attribute representation : string;
+
+  function increment ( vector : in bit_vector ) return bit_vector is
+  begin
+  end;
+
+  function increment ( vector : in std_logic_vector ) return std_logic_vector is
+  begin
+  end;
+
+  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+  attribute pin_number of enable : signal is 14;
+  attribute max_wire_delay of clk : signal is 50 ps;
+  attribute encoding of idle_state : literal is b"0000";
+  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+  attribute built_in of
+    increment [ bit_vector return bit_vector ] : function is bv_incr;
+                                                             attribute built_in of
+                                                               increment [ std_logic_vector return std_logic_vector ] : function is std_incr;
+                                                                                                                                    attribute representation of high [ return speed_range ] : literal is "byte";
+                                                                                                                                                                                                         attribute representation of high [ return coolant_level ] : literal is "word";
+
+                                                                                                                                                                                                         begin
+
+                                                                                                                                                                                                           the_fpu : block is
+                                                                                                                                                                                                           begin
+                                                                                                                                                                                                           end block the_fpu;
+
+                                                                                                                                                                                                           process is
+                                                                                                                                                                                                                     variable v1 : string(1 to 11);
+                                                                                                                                                                                                                   variable v2 : positive;
+                                                                                                                                                                                                                   variable v3 : time;
+                                                                                                                                                                                                                   variable v4 : bit_vector(0 to 3);
+                                                                                                                                                                                                                   variable v5 : coordinate;
+                                                                                                                                                                                                                   variable v6, v7 : built_in_type;
+                                                                                                                                                                                                                   variable v8, v9 : string(1 to 4);
+                                                                                                                                                                                                           begin
+
+                                                                                                                                                                                                             -- code from book included...
+
+                                                                                                                                                                                                             v1 := std_cell'cell_name ;
+                                                                                                                                                                                                             v2 := enable'pin_number ;
+                                                                                                                                                                                                             v3 := clk'max_wire_delay ;
+                                                                                                                                                                                                             -- workaround MTI bugs mt037/mt038
+                                                                                                                                                                                                             -- v4 := idle_state'encoding ;
+                                                                                                                                                                                                             v4 := idle_state[return state_type]'encoding ;
+                                                                                                                                                                                                             -- end workaround
+                                                                                                                                                                                                             v5 := the_fpu'cell_position ;
+
+                                                                                                                                                                                                             v6 := increment [ bit_vector return bit_vector ] 'built_in ;
+                                                                                                                                                                                                             v7 := increment [ std_logic_vector return std_logic_vector ] 'built_in ;
+
+                                                                                                                                                                                                             v8 := high [ return speed_range ] 'representation ;
+                                                                                                                                                                                                             v9 := high [ return coolant_level ] 'representation ;
+
+                                                                                                                                                                                                             -- end code from book
+
+                                                                                                                                                                                                             wait;
+                                                                                                                                                                                                           end process;
+
+                                                                                                                                                                                                         end architecture std_cell;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_09.vhd
new file mode 100644
index 0000000..327effa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_09.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_20_09_a is
+
+  attribute attr : integer;
+
+end package ch_20_09_a;
+
+
+
+use work.ch_20_09_a.all;
+
+entity e is
+  port ( p : in bit );
+  attribute attr of p : signal is 1;
+end entity e;
+
+
+architecture arch of e is
+begin
+
+  assert false report integer'image(p'attr);
+
+end architecture arch;
+
+
+
+use work.ch_20_09_a.all;
+
+entity ch_20_09 is
+end entity ch_20_09;
+
+
+
+architecture test of ch_20_09 is
+
+  signal s : bit;
+
+  attribute attr of s : signal is 2;
+
+begin
+
+  -- code from book
+
+  c1 : entity work.e(arch)
+    port map ( p => s );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_10.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_10.vhd
new file mode 100644
index 0000000..1ed33d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_10.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package ch_20_10 is
+
+  -- code from book
+
+  attribute foreign : string;
+
+  -- end code from book
+
+end package ch_20_10;
+
+
+
+entity and2 is
+end entity and2;
+
+
+-- code from book
+
+architecture accelerated of and2 is
+  attribute foreign of accelerated : architecture is
+    "accelerate/function:and_2in/nocheck";
+begin
+end architecture accelerated;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_11.vhd
new file mode 100644
index 0000000..202ab84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_11.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_ch_20_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_20_11 is
+
+end entity ch_20_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_20_11 is
+
+  component comp is
+  end component comp;
+
+  signal clk_phase1, clk_phase2 : bit;
+
+  -- code from book:
+
+  group signal_pair is (signal, signal);
+
+  group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
+
+  attribute max_skew : time;
+
+  attribute max_skew of clock_pair : group is 200 ps;
+
+  group component_instances is ( label <> );
+
+  group U1 : component_instances ( nand1, nand2, nand3 );
+  group U2 : component_instances ( inv1, inv2 );
+
+  attribute IC_allocation : string;
+
+  attribute IC_allocation of U1 : group is "74LS00";
+  attribute IC_allocation of U2 : group is "74LS04";
+
+  -- end of code from book
+
+begin
+
+
+  nand1 : component comp;
+  nand2 : component comp;
+  nand3 : component comp;
+  inv1 : component comp;
+  inv2 : component comp;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_05.vhd
new file mode 100644
index 0000000..574c5c3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_05.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_05.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity flipflop is
+  generic ( Tsetup : delay_length );
+  port ( clk, d : in bit;  q : out bit );
+end entity flipflop;
+
+
+-- code from book
+
+architecture behavior of flipflop is
+begin
+
+  timing_check : process (clk) is
+  begin
+    if clk = '1' then
+      assert d'last_event >= Tsetup
+        report "set up violation detected in " & timing_check'path_name
+        severity error;
+    end if;
+  end process timing_check;
+
+  -- . . .    -- functionality
+
+end architecture behavior;
+
+-- end code from book
+
+
+
+entity fg_20_05 is
+end entity fg_20_05;
+
+
+architecture test of fg_20_05 is
+
+  signal clk, d, q : bit;
+
+begin
+
+  dut : entity work.flipflop(behavior)
+    generic map ( Tsetup => 3 ns )
+    port map ( clk => clk, d => d, q => q );
+
+  clk <= '1' after 10 ns, '0' after 20 ns;
+
+  d <= '1' after 8 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_06.vhd
new file mode 100644
index 0000000..027ede5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_06.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_06.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+package mem_pkg is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (natural range <>) of word;
+
+  procedure load_array ( words : out word_array;  file_name : string );
+
+end package mem_pkg;
+
+package body mem_pkg is
+
+  procedure load_array ( words : out word_array;  file_name : string ) is
+    -- words'path_name = ":project:mem_pkg:load_array:words"
+
+    use std.textio.all;
+    file load_file : text open read_mode is file_name;
+    -- load_file'path_name = ":project:mem_pkg:load_array:load_file"
+
+    procedure read_line is
+      -- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
+      variable current_line : line;
+      -- current_line'path_name =
+      --    ":project:mem_pkg:load_array:read_line:current_line"
+    begin
+      -- . . .
+      -- not in book
+      report current_line'path_name;
+      -- end not in book
+    end procedure read_line;
+
+  begin  -- load_array
+    -- . . .
+    -- not in book
+    report mem_pkg'path_name;
+    report words'path_name;
+    report load_file'path_name;
+    report read_line'path_name;
+    read_line;
+    -- end not in book
+  end procedure load_array;
+
+end package body mem_pkg;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_07.vhd
new file mode 100644
index 0000000..31d7803
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_07.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_07.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+entity top is
+end entity top;
+
+architecture top_arch of top is
+
+  signal top_sig : -- . . .;                  -- 1
+    --
+    bit;
+    --
+
+begin
+
+  stimulus : process
+    is
+      variable var : -- . . .;                  -- 2
+      --
+      bit;
+    --
+  begin
+    -- . . .
+    --
+    report "--1: " & top'path_name;
+    report "--1: " & top'instance_name;
+    report "--1: " & top_sig'path_name;
+    report "--1: " & top_sig'instance_name;
+    report "--2: " & stimulus'path_name;
+    report "--2: " & stimulus'instance_name;
+    report "--2: " & var'path_name;
+    report "--2: " & var'instance_name;
+    wait;
+    --
+  end process stimulus;
+
+  rep_gen : for index in 0 to 7 generate
+  begin
+
+    end_gen : if index = 7 generate
+      signal end_sig : -- . . .;              -- 3
+        --
+        bit;
+        --
+    begin
+      -- . . .
+      assert false report "--3: " & end_sig'path_name;
+      assert false report "--3: " & end_sig'instance_name;
+      --
+    end generate end_gen;
+
+    other_gen : if index /= 7 generate
+      signal other_sig : -- . . .;            -- 4
+        --
+        bit;
+        --
+    begin
+      other_comp : entity work.bottom(bottom_arch)
+        port map ( -- . . . );
+          --
+          port_name => open );
+      assert false report "--4: " & other_sig'path_name;
+      assert false report "--4: " & other_sig'instance_name;
+      --
+    end generate other_gen;
+
+  end generate rep_gen;
+
+end architecture top_arch;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_09.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_09.vhd
new file mode 100644
index 0000000..5ce10ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_09.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity bottom is
+  port ( -- . . . );
+    --
+    port_name : in bit := '0' );
+  --
+end entity bottom;
+
+--------------------------------------------------
+
+architecture bottom_arch of bottom is
+
+  signal bot_sig : -- . . .;          -- 5
+    --
+    bit;
+  --
+
+  procedure proc ( -- . . . ) is
+    --
+    param_name : in bit := '0' ) is
+    --
+    variable v : -- . . .;            -- 6
+      --
+      bit;
+    --
+  begin
+    -- . . .
+    --
+    report "--6: " & v'path_name;
+    report "--6: " & v'instance_name;
+    --
+  end procedure proc;
+
+begin
+
+  delays : block is
+                   constant d : integer := 1;      -- 7
+  begin
+    -- . . .
+    --
+    assert false report "--7: " & d'path_name;
+    assert false report "--7: " & d'instance_name;
+    --
+  end block delays;
+
+  func : block is
+  begin
+
+    process is
+              variable v : -- . . .;          -- 8
+            --
+            bit;
+            --
+    begin
+      -- . . .
+      --
+      report "--5: " & bot_sig'path_name;
+      report "--5: " & bot_sig'instance_name;
+      report "--8: " & v'path_name;
+      report "--8: " & v'instance_name;
+      proc(param_name => open);
+      wait;
+      --
+      --
+    end process;
+
+  end block func;
+
+end architecture bottom_arch;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_11.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_11.vhd
new file mode 100644
index 0000000..bc11774
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_11.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_20_11 is
+end entity fg_20_11;
+
+
+architecture test of fg_20_11 is
+begin
+
+-- code from book
+
+  process is
+
+            procedure add_with_overflow ( a, b : in integer;
+                                          sum : out integer;
+                                          overflow : out boolean ) is -- . . .
+
+    -- not in book
+  begin
+  end;
+  -- end not in book
+
+  procedure add_with_overflow ( a, b : in bit_vector;
+                                sum : out bit_vector;
+                                overflow : out boolean ) is -- . . .
+
+    -- not in book
+  begin
+  end;
+  -- end not in book
+
+  attribute built_in : string;
+
+  attribute built_in of
+    add_with_overflow [ integer, integer,
+                        integer, boolean ] : procedure is "int_add_overflow";
+
+  attribute built_in of
+    add_with_overflow [ bit_vector, bit_vector,
+                        bit_vector, boolean ] : procedure is "bit_vector_add_overflow";
+
+  begin
+    -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process;
+
+-- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_12.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_12.vhd
new file mode 100644
index 0000000..cc0e5c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_12.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_12.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package physical_attributes is
+
+  -- code from book (in text)
+
+  attribute layout_ignore : boolean;
+  attribute pin_number : positive;
+
+  -- end code from book
+
+end package physical_attributes;
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.physical_attributes.all;
+
+entity \74x138\ is
+  generic ( Tpd : time );
+  port ( en1, en2a_n, en2b_n : in std_logic;
+         s0, s1, s2 : in std_logic;
+         y0, y1, y2, y3, y4, y5, y6, y7 : out std_logic );
+
+  attribute layout_ignore of Tpd : constant is true;
+
+  attribute pin_number of s0 : signal is 1;
+  attribute pin_number of s1 : signal is 2;
+  attribute pin_number of s2 : signal is 3;
+  attribute pin_number of en2a_n : signal is 4;
+  -- . . .
+
+end entity \74x138\;
+
+-- code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_13.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_13.vhd
new file mode 100644
index 0000000..745f4eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_13.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_13.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_20_13 is
+end entity fg_20_13;
+
+
+architecture test of fg_20_13 is
+
+  attribute trace : string;
+
+  subtype byte is bit_vector(7 downto 0);
+  type byte_vector is array (natural range <>) of byte;
+
+  type ram_bus is record
+                    d : byte;
+                    cmd, status, clk : bit;
+                  end record ram_bus;
+
+  -- code from book
+
+  procedure mem_read ( address : in natural;
+                       result : out byte_vector;
+                       signal memory_bus : inout ram_bus ) is
+
+    attribute trace of address : constant is "integer/hex";
+    attribute trace of result : variable is "byte/multiple/hex";
+    attribute trace of memory_bus : signal is
+      "custom/command=rambus.cmd";
+    -- . . .
+
+  begin
+    -- . . .
+    -- not in book
+    report address'trace;
+    report result'trace;
+    report memory_bus'trace;
+    -- end not in book
+  end procedure mem_read;
+
+  -- end code from book
+
+  signal memory_bus : ram_bus;
+
+begin
+
+  process is
+            variable address : natural;
+          variable result : byte_vector(0 to 3);
+  begin
+    mem_read ( address, result, memory_bus );
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_14.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_14.vhd
new file mode 100644
index 0000000..62581b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_14.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_14.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package graphics_pkg is
+
+  attribute graphic_symbol : string;
+  attribute graphic_style : string;
+
+end package graphics_pkg;
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+--library graphics;
+library work;
+
+package gate_components is
+
+  --use graphics.graphics_pkg.graphic_symbol,
+  -- graphics.graphics_pkg.graphic_style;
+  use work.graphics_pkg.all;
+
+  component and2 is
+                   generic ( prop_delay : delay_length );
+                 port ( a, b : in std_logic;  y : out std_logic );
+  end component and2;
+
+  attribute graphic_symbol of and2 : component is "and2";
+  attribute graphic_style of and2 : component is "color:default, weight:bold";
+
+  -- . . .
+
+end package gate_components;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_15.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_15.vhd
new file mode 100644
index 0000000..65d281e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_15.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package cell_attributes is
+
+  type length is range 0 to integer'high
+    units nm;
+          um = 1000 nm;
+          mm = 1000 um;
+          mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+                       x, y : length;
+                     end record coordinate;
+
+  attribute cell_position : coordinate;
+
+end package cell_attributes;
+
+
+
+entity CPU is
+end entity CPU;
+
+
+-- code from book
+
+architecture cell_based of CPU is
+
+  component fpu is
+                  port ( -- . . . );
+                    -- not in book
+                    port_name : bit := '0' );
+                -- end not in book
+  end component;
+
+  use work.cell_attributes.all;
+
+  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+
+  -- . . .
+
+begin
+
+  the_fpu : component fpu
+    port map ( -- . . . );
+      -- not in book
+      port_name => open );
+  -- end not in book
+
+  -- . . .
+
+end architecture cell_based;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_16.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_16.vhd
new file mode 100644
index 0000000..c95c4e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_16.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_16.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity fg_20_16 is
+end entity fg_20_16;
+
+
+architecture test of fg_20_16 is
+
+  signal clk : bit;
+
+  attribute synthesis_hint : string;
+
+begin
+
+  -- code from book
+
+  controller : process is
+
+                         attribute synthesis_hint of control_loop : label is
+                       "implementation:FSM(clk)";
+                       -- . . .
+
+  begin
+    -- . . .    -- initialization
+    control_loop : loop
+      wait until clk = '1';
+      -- . . .
+    end loop;
+  end process controller;
+
+  -- end code fom book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_17.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_17.vhd
new file mode 100644
index 0000000..7e3ce06
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_17.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_17.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package voltage_defs is
+
+  type voltage is range -2e9 to +2e9
+    units
+      nV;
+      uV = 1000 nV;
+      mV = 1000 uV;
+      V = 1000 mV;
+    end units voltage;
+
+  attribute resolution : real;
+
+  attribute resolution of nV : units is 1.0;
+                                     attribute resolution of uV : units is 0.01;
+                                                                        attribute resolution of mV : units is 0.01;
+                                                                                                           attribute resolution of V : units is 0.001;
+
+                                                                                                                                   end package voltage_defs;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_18.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_18.vhd
new file mode 100644
index 0000000..a19dac1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_18.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_18.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package timing_attributes is
+
+  attribute max_wire_delay : delay_length;
+
+end package timing_attributes;
+
+
+entity sequencer is
+end entity sequencer;
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.timing_attributes.all;
+
+architecture structural of sequencer is
+
+  signal recovered_clk1, recovered_clk2 : std_logic;
+  signal test_enable : std_logic;
+  signal test_data : std_logic_vector(0 to 15);
+
+  attribute max_wire_delay of
+    recovered_clk1, recovered_clk2 : signal is 100 ps;
+
+  attribute max_wire_delay of others : signal is 200 ps;
+
+  -- . . .
+
+begin
+  -- . . .
+  -- not in book
+  assert false report time'image(recovered_clk1'max_wire_delay) severity note;
+  assert false report time'image(recovered_clk2'max_wire_delay) severity note;
+  assert false report time'image(test_enable'max_wire_delay) severity note;
+  assert false report time'image(test_data'max_wire_delay) severity note;
+  -- end not in book
+end architecture structural;
+
+-- code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_19.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_19.vhd
new file mode 100644
index 0000000..3636dab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_19.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_19.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package display_interface is
+
+  -- . . .
+
+  -- not in book
+  type status_type is (t1, t2, t3);
+  -- end not in book
+
+  procedure create_window ( size_x, size_y : natural;
+                            status : out status_type );
+
+  attribute foreign of create_window : procedure is
+    "language Ada;  with window_operations;" &
+    "bind to window_operations.create_window;" &
+    "parameter size_x maps to size_x : in natural;" &
+    "parameter size_y maps to size_y : in natural;" &
+    "parameter status maps to status : out window_operations.status_type;" &
+    "others map to default";
+
+  -- . . .
+
+end package display_interface;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_20.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_20.vhd
new file mode 100644
index 0000000..b3090e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_20.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_20_fg_20_20.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package constraints is
+
+  -- code from book (in text)
+
+  group port_pair is ( signal, signal );
+
+  attribute max_prop_delay : time;
+
+  -- end code from book
+
+end package constraints;
+
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.constraints.port_pair, work.constraints.max_prop_delay;
+
+entity clock_buffer is
+  port ( clock_in : in std_logic;
+         clock_out1, clock_out2, clock_out3 : out std_logic );
+
+  group clock_to_out1 : port_pair ( clock_in, clock_out1 );
+  group clock_to_out2 : port_pair ( clock_in, clock_out2 );
+  group clock_to_out3 : port_pair ( clock_in, clock_out3 );
+
+  attribute max_prop_delay of clock_to_out1 : group is 2 ns;
+  attribute max_prop_delay of clock_to_out2 : group is 2 ns;
+  attribute max_prop_delay of clock_to_out3 : group is 2 ns;
+
+end entity clock_buffer;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_01.vhd
new file mode 100644
index 0000000..d3d4efa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_01.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_ch_21_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_21_01 is
+
+end entity ch_21_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_21_01 is
+
+  type std_ulogic is (t1, t2, t3);
+  subtype std_logic is std_ulogic;
+
+  -- code from book:
+
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+
+  type std_logic_vector is array ( natural range <>) of std_logic;
+
+  -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_02.vhd
new file mode 100644
index 0000000..a34d961
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_02.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_ch_21_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_21_02 is
+
+end entity ch_21_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_21_02 is
+
+  signal s : bit;
+
+begin
+
+  -- code from book:
+
+  p : postponed process is
+                          -- . . .
+                begin
+                  -- . . .
+                  wait until s = '1';
+                  -- . . .       -- s may not be '1'!!
+                  -- not in book
+                  report bit'image(s);
+                  wait;
+                  -- end not in book
+                end postponed process p;
+
+                                      -- end of code from book
+
+                                      stimulus : process is
+                                      begin
+                                        wait for 10 ns;
+                                        s <= '1';
+                                        wait for 0 ns;
+                                        s <= '0';
+                                        wait;
+                                      end process stimulus;
+
+                              end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_03.vhd
new file mode 100644
index 0000000..adc42b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_03.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_ch_21_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity controller is
+end entity controller;
+
+
+-- code from book
+
+architecture instrumented of controller is
+
+  shared variable operation_count : natural := 0;
+  -- . . .
+
+begin
+  -- . . .
+end architecture instrumented;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_01.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_01.vhd
new file mode 100644
index 0000000..3e784fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_01.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_01.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity D_flipflop is
+  port ( clk, d : in bit;  q : buffer bit );
+end entity D_flipflop;
+
+
+architecture behavioral of D_flipflop is
+begin
+  q <= d when clk'event and clk = '1';
+end architecture behavioral;
+
+
+
+entity inverter is
+  port ( a : in bit;  y : out bit );
+end entity inverter;
+
+
+architecture behavioral of inverter is
+begin
+  y <= not a;
+end architecture behavioral;
+
+
+
+-- code from book
+
+entity count2 is
+  port ( clk : in bit;  q0, q1 : buffer bit );
+end entity count2;
+
+--------------------------------------------------
+
+architecture buffered_outputs of count2 is
+
+  component D_flipflop is
+                         port ( clk, d : in bit;  q : buffer bit );
+  end component D_flipflop;
+
+  component inverter is
+                       port ( a : in bit;  y : out bit );
+  end component inverter;
+
+  signal q0_n, q1_n : bit;
+
+begin
+
+  bit0 : component D_flipflop
+    port map ( clk => clk, d => q0_n, q => q0 );
+
+  inv0 : component inverter
+    port map ( a => q0, y => q0_n );
+
+  bit1 : component D_flipflop
+    port map ( clk => q0_n, d => q1_n, q => q1 );
+
+  inv1 : component inverter
+    port map ( a => q1, y => q1_n );
+
+end architecture buffered_outputs;
+
+-- end code from book
+
+
+
+entity fg_21_01 is
+end entity fg_21_01;
+
+
+architecture test of fg_21_01 is
+
+  signal clk, q0, q1 : bit;
+
+begin
+
+  dut : entity work.count2(buffered_outputs)
+    port map ( clk => clk, q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 10 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_02.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_02.vhd
new file mode 100644
index 0000000..cb9a1b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_02.vhd
@@ -0,0 +1,127 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_02.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               package project_util is
+
+                 -- code from book (in text)
+
+                 function "<" ( bv1, bv2 : bit_vector ) return boolean;
+
+                 subtype word is std_logic_vector(31 downto 0);
+
+                 -- end code from book
+
+               end package project_util;
+
+
+               package body project_util is
+
+                 function "<" ( bv1, bv2 : bit_vector ) return boolean is
+                   variable tmp1 : bit_vector(bv1'range) := bv1;
+                   variable tmp2 : bit_vector(bv2'range) := bv2;
+                 begin
+                   assert bv1'length = bv2'length
+                     report "vectors are of different length in ""<"" comparison"
+                     severity failure;
+                   tmp1(tmp1'left) := not tmp1(tmp1'left);
+                   tmp2(tmp2'left) := not tmp2(tmp2'left);
+                   return std.standard."<" ( tmp1, tmp2 );
+                 end function "<";
+
+               end package body project_util;
+
+
+
+-- code from book
+
+               library ieee;  use ieee.std_logic_1164.all;
+               use work.project_util.all;
+
+               entity limit_checker is
+                 port ( input, lower_bound, upper_bound : in word;
+                        out_of_bounds : out std_logic );
+               end entity limit_checker;
+
+--------------------------------------------------
+
+               architecture behavioral of limit_checker is
+
+                 subtype bv_word is bit_vector(31 downto 0);
+
+                 function word_to_bitvector ( w : in word ) return bv_word is
+                 begin
+                   return To_bitvector ( w, xmap => '0' );
+                 end function word_to_bitvector;
+
+               begin
+
+                 algorithm : process (input, lower_bound, upper_bound) is
+                 begin
+                   if "<" ( bv1 => word_to_bitvector(input),
+                            bv2 => word_to_bitvector(lower_bound) )
+                     or "<" ( bv1 => word_to_bitvector(upper_bound),
+                              bv2 => word_to_bitvector(input) ) then
+                     out_of_bounds <= '1';
+                   else
+                     out_of_bounds <= '0';
+                   end if;
+                 end process algorithm;
+
+               end architecture behavioral;
+
+-- end code from book
+
+
+               library ieee;  use ieee.std_logic_1164.all;
+               use work.project_util.all;
+
+               entity fg_21_02 is
+               end entity fg_21_02;
+
+
+               architecture test of fg_21_02 is
+
+                 signal input : word;
+                 signal out_of_bounds : std_logic;
+
+               begin
+
+                 dut : entity work.limit_checker(behavioral)
+                   port map ( input => input,
+                              lower_bound => X"FFFFFFF0", upper_bound => X"00000010",
+                              out_of_bounds => out_of_bounds );
+
+                 stimulus : input <= X"00000000",
+                                     X"00000008" after 10 ns,
+                                     X"00000010" after 20 ns,
+                                     X"00000018" after 30 ns,
+                                     X"FFFFFFF8" after 40 ns,
+                                     X"FFFFFFF0" after 50 ns,
+                                     X"FFFFFF00" after 60 ns;
+
+               end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_03.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_03.vhd
new file mode 100644
index 0000000..5f08601
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_03.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_03.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- code from book (in text)
+
+entity random_source is
+  generic ( min, max : natural;
+            seed : natural;
+            interval : delay_length );
+  port ( number : out natural );
+end entity random_source;
+
+-- end code from book
+
+
+architecture fudged of random_source is
+begin
+
+  process is
+            variable next_number : natural := seed;
+  begin
+    if next_number > max then
+      next_number := min;
+    end if;
+    number <= next_number;
+    next_number := next_number + 1;
+    wait for interval;
+  end process;
+
+end architecture fudged;
+
+
+
+entity test_bench is
+end entity test_bench;
+
+
+-- code from book
+
+architecture random_test of test_bench is
+
+  subtype bv11 is bit_vector(10 downto 0);
+
+  function natural_to_bv11 ( n : natural ) return bv11 is
+    variable result : bv11 := (others => '0');
+    variable remaining_digits : natural := n;
+  begin
+    for index in result'reverse_range loop
+      result(index) := bit'val(remaining_digits mod 2);
+      remaining_digits := remaining_digits / 2;
+      exit when remaining_digits = 0;
+    end loop;
+    return result;
+  end function natural_to_bv11;
+
+  signal stimulus_vector : bv11;
+  -- . . .
+
+begin
+
+  stimulus_generator : entity work.random_source
+    generic map ( min => 0, max => 2**10 - 1, seed => 0,
+                  interval => 100 ns )
+    port map ( natural_to_bv11(number) => stimulus_vector );
+
+  -- . . .
+
+end architecture random_test;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_04.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_04.vhd
new file mode 100644
index 0000000..2647048
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_04.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_04.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+               entity processor is
+               end entity processor;
+
+
+-- code from book
+
+               architecture rtl of processor is
+
+                 component latch is
+                                   generic ( width : positive );
+                                 port ( d : in std_ulogic_vector(0 to width - 1);
+                                        q : out std_ulogic_vector(0 to width - 1);
+                                        -- . . . );
+                                        -- not in book
+                                        other_port : in std_ulogic := '-' );
+                                 -- end not in book
+                 end component latch;
+
+                 component ROM is
+                                 port ( d_out : out std_ulogic_vector;  -- . . . );
+                                        -- not in book
+                                        other_port : in std_ulogic := '-' );
+                               -- end not in book
+                 end component ROM;
+
+                 subtype std_logic_word is std_logic_vector(0 to 31);
+
+                 signal source1, source2, destination : std_logic_word;
+                 -- . . .
+
+               begin
+
+                 temp_register : component latch
+                   generic map ( width => 32 )
+                   port map ( d => std_ulogic_vector(destination),
+                              std_logic_vector(q) => source1, -- . . . );
+                              -- not in book
+                              other_port => open );
+                 -- end not in book
+
+                 constant_ROM : component ROM
+                   port map ( std_logic_word(d_out) => source2, -- . . . );
+                              -- not in book
+                              other_port => open );
+                 -- end not in book
+
+                 -- . . .
+
+               end architecture rtl;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_05.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_05.vhd
new file mode 100644
index 0000000..12c6d98
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_05.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_05.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity SR_flipflop is
+  port ( s_n, r_n : in bit;  q, q_n : inout bit );
+
+begin
+
+  postponed process (q, q_n) is
+            begin
+              assert now = 0 fs or q = not q_n
+                report "implementation error: q /= not q_n";
+            end postponed process;
+
+                          end entity SR_flipflop;
+
+--------------------------------------------------
+
+                                 architecture dataflow of SR_flipflop is
+                                 begin
+
+                                   gate_1 : q <= s_n nand q_n;
+                                   gate_2 : q_n <= r_n nand q;
+
+                                 end architecture dataflow;
+
+
+
+-- not in book
+
+                                 entity fg_21_05 is
+                                 end entity fg_21_05;
+
+
+                                 architecture test of fg_21_05 is
+
+                                   signal s_n, r_n, q, q_n : bit;
+
+                                 begin
+
+                                   dut : entity work.SR_flipflop
+                                     port map ( s_n, r_n, q, q_n );
+
+                                   s_n <= '1',
+                                          '0' after 10 ns, '1' after 15 ns,
+                                          '0' after 30 ns, '1' after 40 ns;
+
+                                   r_n <= '0', '1' after 5 ns,
+                                          '0' after 20 ns, '1' after 25 ns,
+                                          '0' after 30 ns, '1' after 35 ns;
+
+                                 end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_06.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_06.vhd
new file mode 100644
index 0000000..8095dc5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_21_fg_21_06.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_21_fg_21_06.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity multiprocessor is
+end entity multiprocessor;
+
+
+-- code from book
+
+architecture instrumented of multiprocessor is
+
+  -- not in book
+  constant num_processors : positive := 2;
+  -- end not in book
+
+  shared variable bus_ifetch_count,
+    bus_read_count,
+    bus_write_count : natural := 0;
+
+  signal bus_request, bus_grant : bit_vector(0 to num_processors - 1);
+  -- . . .    -- other signal declarations
+
+begin
+
+  processor_array :
+  for processor_id in 0 to num_processors - 1 generate
+
+    processor : process is
+                          -- . . .
+    begin
+      -- . . .    -- initialize
+      loop
+        bus_request(processor_id) <= '1';
+        wait until bus_grant(processor_id) = '1';
+        bus_ifetch_count := bus_ifetch_count + 1;
+        -- . . .    -- fetch instruction
+        bus_request(processor_id) <= '0';
+        -- . . .    -- decode and execute instruction
+        -- not in book
+        wait until bus_grant(processor_id) = '0';
+        -- end not in book
+      end loop;
+    end process processor;
+
+  end generate processor_array;
+
+  arbiter : process is
+  begin
+    -- . . .
+    -- not in book
+    loop
+      for i in bus_request'range loop
+        if bus_request(i) = '1' then
+          bus_grant(i) <= '1' after 5 ns;
+          wait until bus_request(i) = '0';
+          bus_grant(i) <= '0' after 5 ns;
+        end if;
+      end loop;
+      wait for 5 ns;
+    end loop;
+    -- end not in book
+  end process arbiter;
+
+  -- . . .    -- other processes for memory, etc
+
+end architecture instrumented;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp b/testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp
new file mode 100644
index 0000000..ddac7ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/compliant.exp
@@ -0,0 +1,826 @@
+
+# Copyright (C) 2001 Clifton Labs, Inc
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  
+
+# Please email any bugs, comments, and/or additions to this file to:
+# vests@cliftonlabs.com
+
+# Authors: Philip A. Wilsey	philip.wilsey@ieee.org
+# 	   Dale E. Martin	dmartin@cliftonlabs.com
+
+# $Author: paw $
+# $Revision: 1.6 $
+
+# ------------------------------------------------------------------------
+#
+# $Id: compliant.exp,v 1.6 2001-11-03 23:19:37 paw Exp $
+#
+# ------------------------------------------------------------------------
+
+setup_test_group "Ashenden:Compliant Cases" "1076-1993"
+
+# create general libraries used in the testsuite
+
+create_lib stimulus
+build_compliant_test util_pk_test.vhd LIBRARY=stimulus
+
+create_lib bv_utilities
+
+build_compliant_test bv_arithmetic.vhd LIBRARY=bv_utilities
+build_compliant_test bv_arithmetic_body.vhd LIBRARY=bv_utilities
+
+build_compliant_test bv_images.vhd LIBRARY=bv_utilities
+build_compliant_test bv_images_body.vhd LIBRARY=bv_utilities
+
+# ------------------------------------------------------------------------
+# models from chapter 1....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_01_fg_01_07.vhd
+build_compliant_test ch_01_fg_01_08.vhd
+build_compliant_test ch_01_fg_01_10.vhd
+build_compliant_test ch_01_fg_01_11.vhd
+
+build_compliant_test ch_01_fg_01_13.vhd
+
+build_compliant_test ch_01_tb_01_01.vhd
+
+build_compliant_test ch_01_tb_01_02.vhd
+
+build_compliant_test ch_01_tb_01_03.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 2....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_02_tb_02_01.vhd
+build_compliant_test ch_02_fg_02_01.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 3....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_03_ch_03_01.vhd
+build_compliant_test ch_03_ch_03_02.vhd
+build_compliant_test ch_03_ch_03_03.vhd
+build_compliant_test ch_03_ch_03_04.vhd
+build_compliant_test ch_03_ch_03_05.vhd
+build_compliant_test ch_03_ch_03_06.vhd
+build_compliant_test ch_03_ch_03_07.vhd
+build_compliant_test ch_03_ch_03_08.vhd
+build_compliant_test ch_03_ch_03_10.vhd
+build_compliant_test ch_03_ch_03_11.vhd
+build_compliant_test ch_03_ch_03_12.vhd
+build_compliant_test ch_03_ch_03_13.vhd
+build_compliant_test ch_03_ch_03_14.vhd
+build_compliant_test ch_03_ch_03_16.vhd
+build_compliant_test ch_03_ch_03_17.vhd
+build_compliant_test ch_03_ch_03_18.vhd
+build_compliant_test ch_03_ch_03_19.vhd
+build_compliant_test ch_03_ch_03_20.vhd
+
+build_compliant_test ch_03_fg_03_01.vhd
+build_compliant_test ch_03_tb_03_01.vhd
+
+build_compliant_test ch_03_tb_03_02.vhd
+build_compliant_test ch_03_fg_03_02.vhd
+build_compliant_test ch_03_tb_03_03.vhd
+
+build_compliant_test ch_03_fg_03_03.vhd
+build_compliant_test ch_03_tb_03_04.vhd
+
+build_compliant_test ch_03_fg_03_04.vhd
+build_compliant_test ch_03_tb_03_05.vhd
+
+build_compliant_test ch_03_fg_03_05.vhd
+build_compliant_test ch_03_tb_03_06.vhd
+
+build_compliant_test ch_03_fg_03_05.vhd
+build_compliant_test ch_03_fg_03_06.vhd
+build_compliant_test ch_03_tb_03_07.vhd
+
+build_compliant_test ch_03_fg_03_07.vhd
+build_compliant_test ch_03_tb_03_08.vhd
+
+build_compliant_test ch_03_fg_03_08.vhd
+build_compliant_test ch_03_tb_03_09.vhd
+
+build_compliant_test ch_03_fg_03_09.vhd
+build_compliant_test ch_03_tb_03_10.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 4....
+# ------------------------------------------------------------------------
+
+create_lib ch4_pkgs
+
+build_compliant_test ch_04_pk_04_01.vhd LIBRARY=ch4_pkgs
+build_compliant_test ch_04_pk_04_02.vhd LIBRARY=ch4_pkgs
+
+build_compliant_test ch_04_ch_04_01.vhd
+build_compliant_test ch_04_ch_04_02.vhd
+build_compliant_test ch_04_ch_04_04.vhd
+build_compliant_test ch_04_ch_04_05.vhd
+build_compliant_test ch_04_ch_04_06.vhd
+build_compliant_test ch_04_ch_04_07.vhd
+build_compliant_test ch_04_ch_04_08.vhd
+build_compliant_test ch_04_ch_04_10.vhd
+
+build_compliant_test ch_04_fg_04_01.vhd
+build_compliant_test ch_04_fg_04_03.vhd
+
+build_compliant_test ch_04_tb_04_04.vhd
+build_compliant_test ch_04_fg_04_06.vhd
+
+build_compliant_test ch_04_tb_04_01.vhd
+
+build_compliant_test ch_04_fg_04_04.vhd
+build_compliant_test ch_04_tb_04_02.vhd
+
+build_compliant_test ch_04_fg_04_05.vhd
+build_compliant_test ch_04_tb_04_03.vhd
+
+delete_lib ch4_pkgs
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 5....
+# ------------------------------------------------------------------------
+
+# consider removing this test....doesn't it duplicate util_pk_test.vhd??
+build_compliant_test ch_05_pk_test.vhd
+
+build_compliant_test ch_05_ch_05_03.vhd
+build_compliant_test ch_05_fg_05_02.vhd
+build_compliant_test ch_05_tb_05_01.vhd
+build_compliant_test ch_05_tb_05_02.vhd
+
+build_compliant_test ch_05_fg_05_05.vhd
+build_compliant_test ch_05_fg_05_25.vhd
+build_compliant_test ch_05_tb_05_03.vhd
+
+build_compliant_test ch_05_fg_05_06.vhd
+build_compliant_test ch_05_tb_05_04.vhd
+
+build_compliant_test ch_05_fg_05_16.vhd
+build_compliant_test ch_05_tb_05_05.vhd
+
+# this file should be placed in a library
+build_compliant_test ch_05_fg_05_22.vhd
+build_compliant_test ch_05_tb_05_06.vhd
+build_compliant_test ch_05_fg_05_22.vhd
+build_compliant_test ch_05_tb_05_07.vhd
+
+build_compliant_test ch_05_fg_05_24.vhd
+build_compliant_test ch_05_tb_05_08.vhd
+
+build_compliant_test ch_05_fg_05_05.vhd
+
+create_lib star_lib
+
+build_compliant_test ch_05_fg_05_05.vhd
+build_compliant_test ch_05_fg_05_25.vhd
+
+build_compliant_test ch_05_tb_05_09.vhd
+build_compliant_test ch_05_tb_05_10.vhd
+build_compliant_test ch_05_fg_05_27.vhd
+build_compliant_test ch_05_tb_05_11.vhd
+
+create_lib widget_cells
+
+build_compliant_test ch_05_tb_05_12.vhd LIBRARY=widget_cells
+
+create_lib wasp_lib
+
+build_compliant_test ch_05_tb_05_13.vhd
+build_compliant_test ch_05_ch_05_01.vhd
+build_compliant_test ch_05_ch_05_02.vhd 
+build_compliant_test ch_05_ch_05_05.vhd
+build_compliant_test ch_05_tb_05_12.vhd LIBRARY=wasp_lib
+
+build_compliant_test ch_05_ch_05_04.vhd
+build_compliant_test ch_05_ch_05_06.vhd
+build_compliant_test ch_05_ch_05_07.vhd
+build_compliant_test ch_05_ch_05_08.vhd
+build_compliant_test ch_05_ch_05_09.vhd
+build_compliant_test ch_05_ch_05_10.vhd
+build_compliant_test ch_05_ch_05_11.vhd
+build_compliant_test ch_05_ch_05_12.vhd
+build_compliant_test ch_05_ch_05_13.vhd
+build_compliant_test ch_05_ch_05_14.vhd
+build_compliant_test ch_05_ch_05_15.vhd
+build_compliant_test ch_05_ch_05_16.vhd
+build_compliant_test ch_05_ch_05_17.vhd
+build_compliant_test ch_05_ch_05_18.vhd
+build_compliant_test ch_05_ch_05_19.vhd
+build_compliant_test ch_05_ch_05_20.vhd
+build_compliant_test ch_05_ch_05_21.vhd
+build_compliant_test ch_05_ch_05_22.vhd
+build_compliant_test ch_05_ch_05_23.vhd
+build_compliant_test ch_05_ch_05_24.vhd
+build_compliant_test ch_05_ch_05_25.vhd
+build_compliant_test ch_05_ch_05_26.vhd
+build_compliant_test ch_05_ch_05_27.vhd
+build_compliant_test ch_05_fg_05_01.vhd
+build_compliant_test ch_05_fg_05_03.vhd
+build_compliant_test ch_05_fg_05_04.vhd
+build_compliant_test ch_05_fg_05_07.vhd
+build_compliant_test ch_05_fg_05_08.vhd
+build_compliant_test ch_05_fg_05_09.vhd
+build_compliant_test ch_05_fg_05_12.vhd
+build_compliant_test ch_05_fg_05_17.vhd
+build_compliant_test ch_05_fg_05_18.vhd
+build_compliant_test ch_05_fg_05_19.vhd
+build_compliant_test ch_05_fg_05_20.vhd
+build_compliant_test ch_05_fg_05_21.vhd
+build_compliant_test ch_05_fg_05_23.vhd
+build_compliant_test ch_05_fg_05_25.vhd
+build_compliant_test ch_05_fg_05_28.vhd
+build_compliant_test ch_05_tb_05_12.vhd
+build_compliant_test ch_05_fg_05_30.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 6....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_06_acca.vhd
+build_compliant_test ch_06_acca-b.vhd
+build_compliant_test ch_06_accr.vhd
+build_compliant_test ch_06_accr-b.vhd
+build_compliant_test ch_06_mac.vhd
+build_compliant_test ch_06_tovec.vhd
+build_compliant_test ch_06_tovec-b.vhd
+build_compliant_test ch_06_tofp.vhd
+build_compliant_test ch_06_tofp-b.vhd
+build_compliant_test ch_06_reg.vhd
+build_compliant_test ch_06_reg-b.vhd
+build_compliant_test ch_06_mac-b.vhd
+build_compliant_test ch_06_mult.vhd
+build_compliant_test ch_06_mult-b.vhd
+build_compliant_test ch_06_pas.vhd
+build_compliant_test ch_06_pas-b.vhd
+build_compliant_test ch_06_srff.vhd
+build_compliant_test ch_06_srff-b.vhd
+build_compliant_test ch_06_ovfl.vhd
+build_compliant_test ch_06_ovfl-b.vhd
+build_compliant_test ch_06_mac-r.vhd
+
+build_compliant_test ch_06_mact.vhd
+build_compliant_test ch_06_mact-bb.vhd
+build_compliant_test ch_06_mact-br.vhd
+build_compliant_test ch_06_mact-bv.vhd
+build_compliant_test ch_06_multt.vhd
+build_compliant_test ch_06_multt-b.vhd
+build_compliant_test ch_06_tofpt.vhd
+build_compliant_test ch_06_tofpt-b.vhd
+build_compliant_test ch_06_tovect.vhd
+build_compliant_test ch_06_tovect-b.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 7....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_07_ch_07_01.vhd
+build_compliant_test ch_07_ch_07_02.vhd
+
+build_compliant_test ch_07_ch_07_03.vhd
+
+build_compliant_test ch_07_ch_07_04.vhd
+build_compliant_test ch_07_ch_07_05.vhd
+build_compliant_test ch_07_ch_07_06.vhd
+build_compliant_test ch_07_fg_07_01.vhd
+build_compliant_test ch_07_fg_07_02.vhd
+build_compliant_test ch_07_fg_07_03.vhd
+build_compliant_test ch_07_fg_07_04.vhd
+build_compliant_test ch_07_fg_07_05.vhd
+build_compliant_test ch_07_fg_07_06.vhd
+build_compliant_test ch_07_fg_07_07.vhd
+build_compliant_test ch_07_fg_07_08.vhd
+build_compliant_test ch_07_fg_07_09.vhd
+build_compliant_test ch_07_fg_07_10.vhd
+build_compliant_test ch_07_fg_07_11.vhd
+build_compliant_test ch_07_fg_07_12.vhd
+build_compliant_test ch_07_fg_07_13.vhd
+build_compliant_test ch_07_fg_07_14.vhd
+build_compliant_test ch_07_fg_07_15.vhd
+build_compliant_test ch_07_fg_07_16.vhd
+build_compliant_test ch_07_fg_07_17.vhd
+build_compliant_test ch_07_fg_07_18.vhd
+build_compliant_test ch_07_fg_07_19.vhd
+
+build_compliant_test ch_07_fg_07_20.vhd
+build_compliant_test ch_07_fg_07_22.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 8....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_08_ch_08_01.vhd
+build_compliant_test ch_08_fg_08_06.vhd
+build_compliant_test ch_08_ch_08_02.vhd
+build_compliant_test ch_08_ch_08_03.vhd
+build_compliant_test ch_08_ch_08_04.vhd
+build_compliant_test ch_08_ch_08_05.vhd
+build_compliant_test ch_08_fg_08_01.vhd
+build_compliant_test ch_08_fg_08_02.vhd
+build_compliant_test ch_08_fg_08_03.vhd
+build_compliant_test ch_08_fg_08_05.vhd
+build_compliant_test ch_08_fg_08_04.vhd
+build_compliant_test ch_08_fg_08_06.vhd
+build_compliant_test ch_08_fg_08_07.vhd
+build_compliant_test ch_08_fg_08_08.vhd LIBRARY=bv_utilities
+build_compliant_test ch_08_fg_08_09.vhd
+build_compliant_test ch_08_fg_08_10.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 9....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_09_ch_09_01.vhd
+build_compliant_test ch_09_ch_09_02.vhd
+build_compliant_test ch_09_ch_09_03.vhd
+build_compliant_test ch_09_ch_09_04.vhd
+build_compliant_test ch_09_fg_09_01.vhd
+build_compliant_test ch_09_fg_09_02.vhd
+build_compliant_test ch_09_fg_09_03.vhd
+build_compliant_test ch_09_fg_09_04.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 10....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_10_alut.vhd
+build_compliant_test ch_10_alu.vhd
+build_compliant_test ch_10_alu-b.vhd
+build_compliant_test ch_10_bvat.vhd
+build_compliant_test ch_10_bvat-b.vhd
+build_compliant_test ch_10_chkdiv.vhd
+build_compliant_test ch_10_chkmult.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 11....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_11_ch_11_01.vhd
+build_compliant_test ch_11_ch_11_02.vhd
+build_compliant_test ch_11_ch_11_03.vhd
+build_compliant_test ch_11_fg_11_01.vhd
+build_compliant_test ch_11_fg_11_02.vhd
+build_compliant_test ch_11_fg_11_03.vhd
+build_compliant_test ch_11_fg_11_04.vhd
+build_compliant_test ch_11_fg_11_05.vhd
+build_compliant_test ch_11_fg_11_06.vhd
+build_compliant_test ch_11_fg_11_07.vhd
+build_compliant_test ch_11_fg_11_08.vhd
+build_compliant_test ch_11_fg_11_09.vhd
+build_compliant_test ch_11_fg_11_10.vhd
+build_compliant_test ch_11_fg_11_12.vhd
+build_compliant_test ch_11_fg_11_13.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 12....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_12_ch_12_01.vhd
+build_compliant_test ch_12_ch_12_02.vhd
+build_compliant_test ch_12_ch_12_03.vhd
+build_compliant_test ch_12_fg_12_01.vhd
+build_compliant_test ch_12_fg_12_02.vhd
+build_compliant_test ch_12_fg_12_03.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 13....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_13_ch_13_01.vhd
+build_compliant_test ch_13_fg_13_01.vhd LIBRARY=star_lib
+build_compliant_test ch_13_fg_13_02.vhd
+build_compliant_test ch_13_fg_13_03.vhd
+build_compliant_test ch_13_fg_13_04.vhd
+build_compliant_test ch_13_fg_13_05.vhd
+build_compliant_test ch_13_fg_13_06.vhd
+build_compliant_test ch_13_fg_13_07.vhd
+build_compliant_test ch_13_fg_13_08.vhd
+build_compliant_test ch_13_fg_13_09.vhd
+build_compliant_test ch_13_fg_13_10.vhd
+build_compliant_test ch_13_fg_13_11.vhd
+build_compliant_test ch_13_fg_13_12.vhd
+build_compliant_test ch_13_fg_13_13.vhd
+build_compliant_test ch_13_fg_13_14.vhd
+build_compliant_test ch_13_fg_13_15.vhd
+build_compliant_test ch_13_fg_13_17.vhd
+
+create_lib chips
+
+build_compliant_test ch_13_fg_13_17.vhd LIBRARY=chips
+build_compliant_test ch_13_fg_13_18.vhd LIBRARY=chips
+build_compliant_test ch_13_fg_13_18.vhd
+
+create_lib gate_lib
+
+build_compliant_test ch_13_fg_13_19.vhd LIBRARY=gate_lib
+build_compliant_test ch_13_fg_13_19.vhd
+build_compliant_test ch_13_fg_13_20.vhd
+build_compliant_test ch_13_fg_13_21.vhd
+build_compliant_test ch_13_fg_13_22.vhd
+
+create_lib cell_lib
+
+build_compliant_test ch_13_fg_13_23.vhd LIBRARY=cell_lib
+build_compliant_test ch_13_fg_13_23.vhd
+build_compliant_test ch_13_fg_13_24.vhd
+
+create_lib project_lib
+
+build_compliant_test ch_05_pk_test.vhd LIBRARY=project_lib
+build_compliant_test ch_13_fg_13_25.vhd LIBRARY=project_lib
+build_compliant_test ch_13_fg_13_25.vhd
+build_compliant_test ch_13_fg_13_26.vhd
+
+build_compliant_test ch_14_ch_14_01.vhd
+build_compliant_test ch_14_fg_14_01.vhd LIBRARY=cell_lib
+build_compliant_test ch_14_fg_14_01.vhd
+build_compliant_test ch_14_fg_14_02.vhd
+build_compliant_test ch_14_fg_14_04.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 14....
+# ------------------------------------------------------------------------
+
+create_lib chip_lib
+
+build_compliant_test ch_14_fg_14_04.vhd LIBRARY=chip_lib
+build_compliant_test ch_14_fg_14_05.vhd
+build_compliant_test ch_14_fg_14_05.vhd LIBRARY=cell_lib
+build_compliant_test ch_14_fg_14_06.vhd
+build_compliant_test ch_14_fg_14_08.vhd
+build_compliant_test ch_14_fg_14_09.vhd
+build_compliant_test ch_14_fg_14_10.vhd
+build_compliant_test ch_14_fg_14_11.vhd
+build_compliant_test ch_14_fg_14_12.vhd
+build_compliant_test ch_14_fg_14_13.vhd LIBRARY=cell_lib
+build_compliant_test ch_14_fg_14_13.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 15....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_15_dlxt.vhd
+build_compliant_test ch_15_alut.vhd
+
+build_compliant_test ch_15_dlxi.vhd
+build_compliant_test ch_15_dlxi-b.vhd
+
+build_compliant_test ch_15_rft.vhd
+
+build_compliant_test ch_15_latch.vhd
+build_compliant_test ch_15_latch-b.vhd
+
+build_compliant_test ch_15_alu.vhd
+build_compliant_test ch_15_alu-b.vhd
+
+build_compliant_test ch_15_cg.vhd
+build_compliant_test ch_15_cg-b.vhd
+
+build_compliant_test ch_15_rf.vhd
+build_compliant_test ch_15_rf-b.vhd
+
+build_compliant_test ch_15_crtl.vhd
+build_compliant_test ch_15_ctrl-b.vhd
+
+build_compliant_test ch_15_regm.vhd
+build_compliant_test ch_15_regm-b.vhd
+
+build_compliant_test ch_15_regmpr.vhd
+build_compliant_test ch_15_regmpr-b.vhd
+
+build_compliant_test ch_15_dlx.vhd
+build_compliant_test ch_15_dlx-b.vhd
+build_compliant_test ch_15_dlx-r.vhd
+
+build_compliant_test ch_15_dlxr.vhd
+build_compliant_test ch_15_mem.vhd
+build_compliant_test ch_15_mem-pl.vhd
+
+build_compliant_test ch_15_ire.vhd
+build_compliant_test ch_15_ire-b.vhd
+
+build_compliant_test ch_15_mem-fl.vhd
+
+build_compliant_test ch_15_mux2.vhd
+build_compliant_test ch_15_mux2-b.vhd
+
+build_compliant_test ch_15_regmp.vhd
+build_compliant_test ch_15_regmp-b.vhd
+
+build_compliant_test ch_15_dlxtst.vhd
+build_compliant_test ch_15_dlxtst-b.vhd
+build_compliant_test ch_15_dlxtst-v.vhd
+
+build_compliant_test ch_15_dlxtstb.vhd
+
+build_compliant_test ch_15_dlxtstr.vhd
+build_compliant_test ch_15_dlxstsv.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 16....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_16_ch_16_01.vhd
+build_compliant_test ch_16_ch_16_02.vhd
+build_compliant_test ch_16_ch_16_03.vhd
+build_compliant_test ch_16_ch_16_04.vhd
+build_compliant_test ch_16_ch_16_05.vhd
+build_compliant_test ch_16_ch_16_06.vhd
+build_compliant_test ch_16_fg_16_01.vhd
+build_compliant_test ch_16_fg_16_02.vhd
+build_compliant_test ch_16_fg_16_04.vhd
+build_compliant_test ch_16_fg_16_05.vhd
+build_compliant_test ch_16_fg_16_06.vhd
+build_compliant_test ch_16_fg_16_07.vhd
+build_compliant_test ch_16_fg_16_08.vhd
+build_compliant_test ch_16_fg_16_09.vhd
+build_compliant_test ch_16_fg_16_10.vhd
+build_compliant_test ch_16_fg_16_12.vhd
+build_compliant_test ch_16_fg_16_13.vhd
+build_compliant_test ch_16_fg_16_14.vhd
+build_compliant_test ch_16_fg_16_15.vhd
+build_compliant_test ch_16_fg_16_16.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 17....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_17_ch_17_01.vhd
+build_compliant_test ch_17_ch_17_02.vhd
+build_compliant_test ch_17_ch_17_03.vhd
+build_compliant_test ch_17_ch_17_04.vhd
+build_compliant_test ch_17_ch_17_05.vhd
+build_compliant_test ch_17_ch_17_06.vhd
+build_compliant_test ch_17_ch_17_07.vhd
+build_compliant_test ch_17_ch_17_08.vhd
+build_compliant_test ch_17_ch_17_09.vhd
+build_compliant_test ch_17_fg_17_05.vhd
+build_compliant_test ch_17_fg_17_07.vhd
+build_compliant_test ch_17_fg_17_08.vhd
+build_compliant_test ch_17_fg_17_09.vhd
+build_compliant_test ch_17_fg_17_11.vhd
+build_compliant_test ch_17_fg_17_13.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 18....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_18_ch_18_01.vhd
+build_compliant_test ch_18_ch_18_02.vhd
+build_compliant_test ch_18_ch_18_03.vhd
+build_compliant_test ch_18_ch_18_04.vhd
+build_compliant_test ch_18_ch_18_05.vhd
+build_compliant_test ch_18_ch_18_06.vhd
+build_compliant_test ch_18_ch_18_07.vhd
+build_compliant_test ch_18_ch_18_08.vhd
+build_compliant_test ch_18_ch_18_09.vhd
+build_compliant_test ch_18_ch_18_10.vhd
+build_compliant_test ch_18_fg_18_01.vhd
+build_compliant_test ch_18_fg_18_02.vhd
+build_compliant_test ch_18_fg_18_03.vhd
+build_compliant_test ch_18_fg_18_04.vhd
+build_compliant_test ch_18_fg_18_05.vhd
+build_compliant_test ch_18_fg_18_06.vhd
+build_compliant_test ch_18_fg_18_07.vhd
+build_compliant_test ch_18_fg_18_08.vhd
+build_compliant_test ch_18_fg_18_09.vhd
+build_compliant_test ch_18_fg_18_10.vhd
+build_compliant_test ch_18_fg_18_11.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 19....
+# ------------------------------------------------------------------------
+
+create_lib math
+
+build_compliant_test math_real.vhd LIBRARY=math
+
+create_lib qsim
+
+build_compliant_test ch_19_qsimt.vhd LIBRARY=qsim
+build_compliant_test ch_19_qsimt-b.vhd LIBRARY=qsim
+
+build_compliant_test ch_19_qt.vhd LIBRARY=qsim
+
+build_compliant_test ch_19_wtfifo.vhd LIBRARY=qsim
+build_compliant_test ch_19_wtfifo-b.vhd LIBRARY=qsim
+
+build_compliant_test ch_19_tkfifo.vhd LIBRARY=qsim
+build_compliant_test ch_19_tkfifo-b.vhd LIBRARY=qsim
+
+create_lib random
+
+build_compliant_test ch_19_random.vhd LIBRARY=random
+build_compliant_test ch_19_random-b.vhd LIBRARY=random
+
+build_compliant_test ch_19_source.vhd
+build_compliant_test ch_19_source-b.vhd
+
+build_compliant_test ch_19_sink.vhd
+build_compliant_test ch_19_sink-b.vhd
+
+build_compliant_test ch_19_queue.vhd
+build_compliant_test ch_19_queue-b.vhd
+
+build_compliant_test ch_19_srvr.vhd
+build_compliant_test ch_19_srvr-b.vhd
+
+build_compliant_test ch_19_fork.vhd
+build_compliant_test ch_19_fork-b.vhd
+
+build_compliant_test ch_19_join.vhd
+build_compliant_test ch_19_join-b.vhd
+
+build_compliant_test ch_19_ds.vhd
+build_compliant_test ch_19_ds-qn.vhd
+
+build_compliant_test ch_19_tb.vhd
+build_compliant_test ch_19_tb-src.vhd
+
+# we may have to re-add ch_19_tb.vhd to work each time.....
+
+build_compliant_test ch_19_tb-snk.vhd
+build_compliant_test ch_19_tb-frk.vhd
+build_compliant_test ch_19_tb-jn.vhd
+build_compliant_test ch_19_tb-qs.vhd
+build_compliant_test ch_19_tb-jnsth.vhd
+
+delete_lib math
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 20....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_20_ch_20_01.vhd
+build_compliant_test ch_20_ch_20_02.vhd
+build_compliant_test ch_20_ch_20_03.vhd
+build_compliant_test ch_20_ch_20_04.vhd
+build_compliant_test ch_20_ch_20_05.vhd
+build_compliant_test ch_20_ch_20_06.vhd
+build_compliant_test ch_20_ch_20_08.vhd
+build_compliant_test ch_20_ch_20_09.vhd
+build_compliant_test ch_20_ch_20_07.vhd
+build_compliant_test ch_20_ch_20_10.vhd
+build_compliant_test ch_20_ch_20_11.vhd
+build_compliant_test ch_20_fg_20_05.vhd
+build_compliant_test ch_20_fg_20_06.vhd
+build_compliant_test ch_20_fg_20_09.vhd
+build_compliant_test ch_20_fg_20_07.vhd
+build_compliant_test ch_20_fg_20_11.vhd
+build_compliant_test ch_20_fg_20_12.vhd
+build_compliant_test ch_20_fg_20_13.vhd
+build_compliant_test ch_20_fg_20_14.vhd
+build_compliant_test ch_20_fg_20_15.vhd
+build_compliant_test ch_20_fg_20_16.vhd
+build_compliant_test ch_20_fg_20_17.vhd
+build_compliant_test ch_20_fg_20_18.vhd
+build_compliant_test ch_20_fg_20_19.vhd
+build_compliant_test ch_20_fg_20_20.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from chapter 21....
+# ------------------------------------------------------------------------
+
+build_compliant_test ch_21_ch_21_01.vhd
+build_compliant_test ch_21_ch_21_02.vhd
+build_compliant_test ch_21_ch_21_03.vhd
+build_compliant_test ch_21_fg_21_01.vhd
+build_compliant_test ch_21_fg_21_02.vhd
+build_compliant_test ch_21_fg_21_03.vhd
+build_compliant_test ch_21_fg_21_04.vhd
+build_compliant_test ch_21_fg_21_05.vhd
+build_compliant_test ch_21_fg_21_06.vhd
+
+delete_lib work
+
+# ------------------------------------------------------------------------
+# models from appendix a....
+# ------------------------------------------------------------------------
+
+build_compliant_test ap_a_ap_a_01.vhd
+build_compliant_test ap_a_ap_a_02.vhd
+build_compliant_test ap_a_ap_a_03.vhd
+build_compliant_test ap_a_ap_a_04.vhd
+build_compliant_test ap_a_ap_a_05.vhd
+build_compliant_test ap_a_ap_a_06.vhd
+build_compliant_test ap_a_ap_a_07.vhd
+build_compliant_test ap_a_ap_a_08.vhd
+build_compliant_test ap_a_ap_a_09.vhd
+build_compliant_test ap_a_ap_a_10.vhd
+build_compliant_test ap_a_fg_a_01.vhd
+build_compliant_test ap_a_fg_a_02.vhd
+build_compliant_test ap_a_fg_a_03.vhd
+build_compliant_test ap_a_fg_a_04.vhd
+build_compliant_test ap_a_fg_a_05.vhd
+build_compliant_test ap_a_fg_a_06.vhd
+build_compliant_test ap_a_fg_a_07.vhd
+build_compliant_test ap_a_fg_a_08.vhd
+build_compliant_test ap_a_fg_a_09.vhd
+build_compliant_test ap_a_fg_a_10.vhd
+build_compliant_test ap_a_fg_a_11.vhd
+
+delete_lib work
+
+delete_lib star_lib
+delete_lib widget_cells
+delete_lib wasp_lib
+delete_lib chips
+delete_lib gate_lib
+delete_lib cell_lib
+delete_lib project_lib
+delete_lib chip_lib
+delete_lib qsim
+
+delete_lib bv_utilities
+delete_lib stimulus
+
+end_test_group
+
+# $Log: compliant.exp,v $
+# Revision 1.6  2001-11-03 23:19:37  paw
+# Updating the test script so that each chapter builds into the work library
+# and work is not deleted until processing all the files for that chapter.
+# This means that none of the tests are setup for simulation (the most they
+# can test is the build), but they are now setup to satisfy the library
+# dependencies.  With these changes the analyzer passes just over 80% of the
+# tests correctly.  I will have to run through these tests chapter by chapter
+# to ensure everything is setup properly.  The original vests distributed
+# from UC was/is very inadequate.  This will take quite some time to fix.  In
+# the mean time, the files are at least useful for testing everything up to
+# TESTLEVEL=build.
+#
+# Revision 1.5  2001/10/25 01:24:24  paw
+# More changes/corrections to library creation/reference.  The parser now
+# reports over 80% on ashenden.  Many changes remain to correct errors in
+# this set of tests.
+#
+# Revision 1.3  2001/10/24 23:31:00  paw
+# More revisions/reorganization to have test harness satisfy dependencies
+# between tests.
+#
+# Revision 1.2  2001/10/24 22:18:13  paw
+# Setup a stricter library structure for the chapter 19 tests.  This is a
+# safety commit.
+#
+# Revision 1.1  2001/10/19 23:28:54  paw
+# Adding dejagnu scripts to run ashenden's test cases.
+#
+
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/math_real.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/math_real.vhd
new file mode 100644
index 0000000..8df2479
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/math_real.vhd
@@ -0,0 +1,212 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: math_real.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+--------------------------------------------------------------- 
+--
+-- This source file may be used and distributed without restriction.
+-- No declarations or definitions shall be included in this package. 
+--
+--   ****************************************************************
+--   *                                                              *
+--   *                      W A R N I N G		 	    *
+--   *								    *
+--   *   This DRAFT version IS NOT endorsed or approved by IEEE     *
+--   *								    *
+--   ****************************************************************
+--
+-- Title:    PACKAGE MATH_REAL
+--
+-- Library:  This package shall be compiled into a library 
+--           symbolically named IEEE.
+--
+-- Purpose:  VHDL declarations for mathematical package MATH_REAL
+--	     which contains common real constants, common real
+--	     functions, and real trascendental functions.
+--
+-- Author:   Based on work by IEEE VHDL Math Package Study Group 
+--
+-- Notes:
+-- 	The package body shall be considered the formal definition of 
+-- 	the semantics of this package. Tool developers may choose to implement 
+-- 	the package body in the most efficient manner available to them.
+--
+-- History:
+--	Version 0.4		JAT	4/15/93
+-------------------------------------------------------------
+Library IEEE;
+
+Package MATH_REAL is
+--synopsys synthesis_off
+
+  constant  MATH_E :         real := 2.71828_18284_59045_23536;  
+                                        -- value of e
+  constant  MATH_1_E:        real := 0.36787_94411_71442_32160;
+                                        -- value of 1/e
+  constant  MATH_PI :        real := 3.14159_26535_89793_23846;  
+                                        -- value of pi
+  constant  MATH_1_PI :      real := 0.31830_98861_83790_67154;  
+                                        -- value of 1/pi
+  constant  MATH_LOG_OF_2:   real := 0.69314_71805_59945_30942;
+                                        -- natural log of 2
+  constant  MATH_LOG_OF_10:  real := 2.30258_50929_94045_68402;
+                                        -- natural log of10
+  constant  MATH_LOG2_OF_E:  real := 1.44269_50408_88963_4074;
+                                        -- log base 2 of e
+  constant  MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
+                                        -- log base 10 of e
+  constant  MATH_SQRT2:      real := 1.41421_35623_73095_04880; 
+                                        -- sqrt of 2
+  constant  MATH_SQRT1_2:    real := 0.70710_67811_86547_52440; 
+                                        -- sqrt of 1/2
+  constant  MATH_SQRT_PI:    real := 1.77245_38509_05516_02730; 
+                                        -- sqrt of pi
+  constant  MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
+  -- conversion factor from degree to radian
+  constant  MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
+  -- conversion factor from radian to degree
+
+  --
+  -- attribute for functions whose implementation is foreign (C native)
+  --
+  -- attribute FOREIGN: string;  -- predefined attribute in VHDL-1992
+  --
+
+  function SIGN (X: real ) return real;
+  -- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
+
+  function CEIL (X : real ) return real;
+  -- returns smallest integer value (as real) not less than X
+
+  function FLOOR (X : real ) return real;
+  -- returns largest integer value (as real) not greater than X
+
+  function ROUND (X : real ) return real;
+  -- returns FLOOR(X + 0.5) if X > 0.0;
+  -- return CEIL(X - 0.5) if X < 0.0
+  
+  function FMAX (X, Y : real ) return real;
+  -- returns the algebraically larger of X and Y
+
+  function FMIN (X, Y : real ) return real;
+  -- returns the algebraically smaller of X and Y
+
+  function SRAND (seed: in integer ) return integer;
+  -- attribute FOREIGN of SRAND: function is "C_NATIVE"; 
+  -- for VHDL-1992 standard
+  --
+  -- sets value of seed for sequence of pseudo-random numbers.
+  -- returns the value of the seed.
+  -- It uses the native C function srand().
+
+  function RAND return integer;		
+  -- attribute FOREIGN of RAND: function is "C_NATIVE"; 
+  -- for VHDL-1992 standard
+  --
+  -- returns an integer pseudo-random number with uniform distribution.
+  -- It uses the native C function rand(). 
+  -- Seed for the sequence is initialized with the
+  -- SRAND() function and value of the seed is changed every
+  -- time SRAND() is called,  but it is not visible.
+  -- The range of generated values is platform dependent.
+
+  function GET_RAND_MAX return integer;		
+  -- attribute FOREIGN of GET_RAND_MAX: function is "C_NATIVE"; 
+  -- for VHDL-1992 standard
+  --
+  -- returns the upper bound of the range of the
+  -- pseudo-random numbers generated by  RAND().
+  -- The support for this function is platform dependent.
+  -- It may not be available in some platforms.
+  -- Note: the value of (RAND() / GET_RAND_MAX()) is a
+  --       pseudo-random number distributed between 0 & 1.
+
+  function SQRT (X : real ) return real;
+  -- returns square root of X;  X >= 0.0
+
+  function CBRT (X : real ) return real;
+  -- returns cube root of X
+
+  function "**" (X : integer; Y : real) return real;
+  -- returns Y power of X ==>  X**Y;
+  -- error if X = 0 and Y <= 0.0
+  -- error if X < 0 and Y does not have an integral value
+
+  function "**" (X : real; Y : real) return real;
+  -- returns Y power of X ==>  X**Y;
+  -- error if X = 0.0 and Y <= 0.0
+  -- error if X < 0.0 and Y does not have an integral value
+
+  function EXP  (X : real ) return real;
+  -- returns e**X; where e = MATH_E
+
+  function LOG (X : real ) return real;
+  -- returns natural logarithm of X; X > 0
+
+  function LOG (BASE: positive; X : real) return real;
+  -- returns logarithm base BASE of X; X > 0
+
+  function  SIN (X : real ) return real;
+  -- returns sin X; X in radians
+
+  function  COS ( X : real ) return real;
+  -- returns cos X; X in radians
+
+  function  TAN (X : real ) return real;
+  -- returns tan X; X in radians
+  -- X /= ((2k+1) * PI/2), where k is an integer
+
+  function  ASIN (X : real ) return real; 
+  -- returns  -PI/2 < asin X < PI/2; | X | <= 1.0
+
+  function  ACOS (X : real ) return real;
+  -- returns  0 < acos X < PI; | X | <= 1.0
+
+  function  ATAN (X : real) return real;
+  -- returns  -PI/2 < atan X < PI/2
+
+  function  ATAN2 (X : real; Y : real) return real;
+  -- returns  atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
+
+  function SINH (X : real) return real;
+  -- hyperbolic sine; returns (e**X - e**(-X))/2
+
+  function  COSH (X : real) return real;
+  -- hyperbolic cosine; returns (e**X + e**(-X))/2
+
+  function  TANH (X : real) return real;
+  -- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
+  
+  function ASINH (X : real) return real;
+  -- returns ln( X + sqrt( X**2 + 1))
+
+  function ACOSH (X : real) return real;
+  -- returns ln( X + sqrt( X**2 - 1));   X >= 1.0
+
+  function ATANH (X : real) return real;
+  -- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1.0
+
+--synopsys synthesis_on
+end  MATH_REAL;
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/util_pk_test.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/util_pk_test.vhd
new file mode 100644
index 0000000..5998e6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/compliant/util_pk_test.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: util_pk_test.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library ieee;  
+use ieee.std_logic_1164.all;
+
+package stimulus_generators is
+
+  procedure all_possible_values ( signal bv : out bit_vector;
+				  delay_between_values : in delay_length );
+
+  procedure all_possible_values ( signal bv : out std_ulogic_vector;
+				  delay_between_values : in delay_length );
+
+  procedure all_possible_values ( signal bv : out std_logic_vector;
+				  delay_between_values : in delay_length );
+
+end package stimulus_generators;
+
+package body stimulus_generators is
+
+  type digit_table is array ( natural range 0 to 1 ) of bit;
+  constant digit : digit_table := ( '0', '1' );
+
+  function natural_to_bv ( nat : in natural;
+      	      	      	   length : in natural ) return bit_vector is
+
+    variable temp : natural := nat;
+    variable result : bit_vector(0 to length - 1);
+
+  begin
+    for index in result'reverse_range loop
+      result(index) := digit( temp rem 2 );
+      temp := temp / 2;
+    end loop;
+    return result;
+  end function natural_to_bv;
+
+  procedure all_possible_values ( signal bv : out bit_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= natural_to_bv(0, bv'length);
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= natural_to_bv(value, bv'length);
+    end loop;
+  end procedure all_possible_values;
+
+  procedure all_possible_values ( signal bv : out std_ulogic_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= To_StdULogicVector(natural_to_bv(0, bv'length));
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= To_StdULogicVector(natural_to_bv(value, bv'length));
+    end loop;
+  end procedure all_possible_values;
+
+  procedure all_possible_values ( signal bv : out std_logic_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= To_StdLogicVector(natural_to_bv(0, bv'length));
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= To_StdLogicVector(natural_to_bv(value, bv'length));
+    end loop;
+  end procedure all_possible_values;
+
+end package body stimulus_generators;
diff --git a/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_02_ch_02_01.vhd b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_02_ch_02_01.vhd
new file mode 100644
index 0000000..0f0263c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_02_ch_02_01.vhd
@@ -0,0 +1,597 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_02_ch_02_01.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_02_01 is
+
+end entity ch_02_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_02_01 is
+begin
+
+
+  section_2_1_a : process is
+
+                            -- code from book:
+
+                            constant number_of_bytes : integer := 4;
+                          constant number_of_bits : integer := 8 * number_of_bytes;
+                          constant e : real := 2.718281828;
+                          constant prop_delay : time := 3 ns;
+                          constant size_limit, count_limit : integer := 255;
+
+                          --
+
+                          variable index : integer := 0;
+                          variable sum, average, largest : real;
+                          variable start, finish : time := 0 ns; 
+
+                          -- end of code from book
+
+  begin
+    wait;
+  end process section_2_1_a;
+
+
+  ----------------
+
+
+  section_2_1_b : process is
+
+                            -- code from book:
+
+                            variable start : time := 0 ns; 
+                          variable finish : time := 0 ns; 
+
+                          -- end of code from book
+
+                          variable program_counter : integer;
+                          variable index : integer;
+
+  begin
+
+    -- code from book:
+
+    program_counter := 0;
+    index := index + 1;
+
+    -- end of code from book
+
+    wait;
+  end process section_2_1_b;
+
+
+  ----------------
+
+
+  section_2_2_a : process is
+
+                            -- code from book:
+
+                            type apples is range 0 to 100;
+                          type oranges is range 0 to 100;
+
+                          --
+
+                          type day_of_month is range 0 to 31;
+                          type year is range 0 to 2100;
+
+                          variable today : day_of_month := 9;
+                          variable start_year : year := 1987;
+
+                          --
+
+                          constant number_of_bits : integer := 32;
+                          type bit_index is range 0 to number_of_bits - 1;
+
+                          --
+
+                          type set_index_range is range 21 downto 11;
+                          type mode_pos_range is range 5 to 7;
+                          variable set_index : set_index_range;
+                          variable mode_pos : mode_pos_range;
+
+                          --
+
+                          type input_level is range -10.0 to +10.0;
+                          type probability is range 0.0 to 1.0;
+
+                          --
+
+                          variable input_A : input_level;
+
+                          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    -- error: Incompatible types for assignment
+    -- start_year := today;
+
+    -- end of code from book
+
+    wait;
+  end process section_2_2_a;
+
+
+  ----------------
+
+
+  section_2_2_b : process is
+
+                            -- code from book:
+
+                            type resistance is range 0 to 1E9
+                          units
+                            ohm;
+                          end units resistance;
+
+                          -- end of code from book
+
+  begin
+    wait;
+  end process section_2_2_b;
+
+
+  ----------------
+
+
+  section_2_2_c : process is
+
+                            -- code from book:
+
+                            type resistance is range 0 to 1E9
+                          units
+                            ohm;
+                            kohm = 1000 ohm;
+                            Mohm = 1000 kohm;
+                          end units resistance;
+
+                          -- end of code from book
+
+  begin
+    wait;
+  end process section_2_2_c;
+
+
+  ----------------
+
+
+  section_2_2_d : process is
+
+                            -- code from book:
+
+                            type length is range 0 to 1E9
+                          units
+                            um;			-- primary unit: micron
+                            mm = 1000 um;		-- metric units
+                            m = 1000 mm;
+                            mil = 254 um;		-- imperial units
+                            inch = 1000 mil;
+                          end units length;
+
+                          -- end of code from book
+
+  begin
+    wait;
+  end process section_2_2_d;
+
+
+  ----------------
+
+
+  section_2_2_e : process is
+
+                            -- code from book:
+
+                            -- type time is range implementation_defined
+                            type time is range integer'low to integer'high
+                          units
+                            fs;
+                            ps = 1000 fs;
+                            ns = 1000 ps;
+                            us = 1000 ns;
+                            ms = 1000 us;
+                            sec = 1000 ms;
+                            min = 60 sec;
+                            hr = 60 min;
+                          end units;
+
+                          -- end of code from book
+
+  begin
+    wait;
+  end process section_2_2_e;
+
+
+  ----------------
+
+
+  section_2_2_f : process is
+
+                            -- code from book:
+
+                            type alu_function is (disable, pass, add, subtract, multiply, divide);
+
+                          --
+
+                          type octal_digit is ('0', '1', '2', '3', '4', '5', '6', '7');
+
+                          --
+
+                          variable alu_op : alu_function;
+                          variable last_digit : octal_digit := '0';
+
+                          --
+
+                          type logic_level is (unknown, low, undriven, high);
+                          variable control : logic_level;
+                          type water_level is (dangerously_low, low, ok);
+                          variable water_sensor : water_level;
+
+                          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    alu_op := subtract;
+    last_digit := '7';
+
+    --
+
+    control := low;
+    water_sensor := low;
+
+    -- end of code from book
+
+    wait;
+  end process section_2_2_f;
+
+
+  ----------------
+
+
+  section_2_2_g : process is
+
+                            -- code from book:
+
+                            type severity_level is (note, warning, error, failure);
+
+                          -- end of code from book
+
+  begin
+    wait;
+  end process section_2_2_g;
+
+
+  ----------------
+
+
+  section_2_2_h : process is
+
+                            -- code from book:
+
+                            variable cmd_char, terminator : character;
+
+                          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    cmd_char := 'P';
+    terminator := cr;
+
+    -- end of code from book
+
+    wait;
+  end process section_2_2_h;
+
+
+  ----------------
+
+
+  section_2_2_i : process is
+
+                            -- code from book:
+
+                            type boolean is (false, true);
+
+                          --
+
+                          type bit is ('0', '1');
+
+                          -- end of code from book
+
+  begin
+    wait;
+  end process section_2_2_i;
+
+
+  ----------------
+
+
+  section_2_2_j : process is
+
+                            variable write_enable_n, select_reg_n, write_reg_n : bit;
+
+  begin
+
+    -- code from book:
+
+    write_reg_n := not ( not write_enable_n and not select_reg_n );
+
+    -- end of code from book
+
+    wait;
+  end process section_2_2_j;
+
+
+  ----------------
+
+
+  section_2_2_k : process is
+
+                            -- code from book:
+
+                            type std_ulogic is ( 'U',	-- Uninitialized
+                                                 'X',	-- Forcing Unknown
+                                                 '0',	-- Forcing zero
+                                                 '1',	-- Forcing one
+                                                 'Z',	-- High Impedance
+                                                 'W',	-- Weak Unknown
+                                                 'L',	-- Weak zero
+                                                 'H',	-- Weak one
+                                                 '-' );	-- Don't care
+
+                          -- end of code from book
+
+  begin
+    wait;
+  end process section_2_2_k;
+
+
+  ----------------
+
+
+  section_2_3_a : process is
+
+                            -- code from book:
+
+                            subtype small_int is integer range -128 to 127;
+
+                          --
+
+                          variable deviation : small_int;
+                          variable adjustment : integer;
+
+                          --
+
+                          subtype bit_index is integer range 31 downto 0;
+
+                          -- end of code from book
+
+  begin
+
+    deviation := 0;
+    adjustment := 0;
+
+    -- code from book:
+
+    deviation := deviation + adjustment;
+
+    -- end of code from book
+
+    wait;
+  end process section_2_3_a;
+
+
+  ----------------
+
+
+  section_2_3_b : process is
+
+                            constant highest_integer : integer := integer'high;
+
+                          constant highest_time : time := time'high;
+
+                          -- code from book:
+
+                          subtype natural is integer range 0 to highest_integer;
+                          subtype positive is integer range 1 to highest_integer;
+
+                          --
+
+                          subtype delay_length is time range 0 fs to highest_time;
+
+                          -- end of code from book
+
+  begin
+    wait;
+  end process section_2_3_b;
+
+
+  ----------------
+
+
+  section_2_3_c : process is
+
+                            -- code from book:
+
+                            type logic_level is (unknown, low, undriven, high);
+                          type system_state is (unknown, ready, busy);
+
+                          --
+
+                          subtype valid_level is logic_level range low to high;
+
+                          -- end of code from book
+
+  begin
+    wait;
+  end process section_2_3_c;
+
+
+  ----------------
+
+
+  section_2_4_a : process is
+
+                            -- code from book:
+
+                            type resistance is range 0 to 1E9
+                          units
+                            ohm;
+                            kohm = 1000 ohm;
+                            Mohm = 1000 kohm;
+                          end units resistance;
+
+                          type set_index_range is range 21 downto 11;
+
+                          type logic_level is (unknown, low, undriven, high);
+
+                          -- end of code from book
+
+  begin
+
+    -- output from vsim: "2000"
+    report resistance'image(2 kohm);
+
+    -- code from book:
+
+    assert resistance'left = 0 ohm;
+    assert resistance'right = 1E9 ohm;
+    assert resistance'low = 0 ohm;
+    assert resistance'high = 1E9 ohm;
+    assert resistance'ascending = true;
+    assert resistance'image(2 kohm) = "2000 ohm";
+    assert resistance'value("5 Mohm") = 5_000_000 ohm;
+
+    assert set_index_range'left = 21;
+    assert set_index_range'right = 11;
+    assert set_index_range'low = 11;
+    assert set_index_range'high = 21;
+    assert set_index_range'ascending = false;
+    assert set_index_range'image(14) = "14";
+    assert set_index_range'value("20") = 20;
+
+    assert logic_level'left = unknown;
+    assert logic_level'right = high;
+    assert logic_level'low = unknown;
+    assert logic_level'high = high;
+    assert logic_level'ascending = true;
+    assert logic_level'image(undriven) = "undriven";
+    assert logic_level'value("Low") = low;
+
+    --
+
+    assert logic_level'pos(unknown) = 0;
+    assert logic_level'val(3) = high;
+    assert logic_level'succ(unknown) = low;
+    assert logic_level'pred(undriven) = low;
+
+    --
+
+    assert time'pos(4 ns) = 4_000_000;
+
+    -- end of code from book
+
+    wait;
+  end process section_2_4_a;
+
+
+  ----------------
+
+
+  section_2_4_b : process is
+
+                            -- code from book:
+
+                            type length is range integer'low to integer'high
+                          units
+                            mm;
+                          end units length;
+
+                          type area is range integer'low to integer'high
+                            units
+                              square_mm;
+                            end units area;
+
+                          --
+
+                          variable L1, L2 : length;
+                          variable A : area;
+
+                          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    -- error: No feasible entries for infix op: "*"
+    -- A := L1 * L2;      -- this is incorrect
+
+    --
+
+    A := area'val( length'pos(L1) * length'pos(L2) );
+
+    -- end of code from book
+
+    wait;
+  end process section_2_4_b;
+
+
+  ----------------
+
+
+  section_2_4_c : process is
+
+                            -- code from book:
+
+                            type opcode is (nop, load, store, add, subtract, negate, branch, halt);
+                          subtype arith_op is opcode range add to negate;
+
+                          -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    assert arith_op'base'left = nop;
+    assert arith_op'base'succ(negate) = branch;
+
+    -- end of code from book
+
+    wait;
+  end process section_2_4_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_03_ch_03_09.vhd b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_03_ch_03_09.vhd
new file mode 100644
index 0000000..1307b47
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_03_ch_03_09.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_09.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_09 is
+
+end entity ch_03_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_03_09 is
+begin
+
+
+  process_3_2_d : process is
+
+                            -- code from book:
+
+                            variable N : integer := 1;
+
+                          --
+
+                          constant C : integer := 1;
+
+                          -- end of code from book
+
+                          constant expression : integer := 7;
+
+  begin
+
+    -- code from book:
+
+    -- error: Case choice must be a locally static expression
+
+    -- case expression is         -- example of an illegal case statement
+    --   when N | N+1 => -- . . .
+    --   when N+2 to N+5 => -- . . .
+    --   when others => -- . . .
+    -- end case;
+
+    --
+
+    case expression is
+      when C | C+1 => -- . . .
+      when C+2 to C+5 => -- . . .
+      when others => -- . . .
+    end case;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_2_d;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_03_ch_03_15.vhd b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_03_ch_03_15.vhd
new file mode 100644
index 0000000..6b5b3e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_03_ch_03_15.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_03_ch_03_15.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_03_15 is
+
+end entity ch_03_15;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_03_15 is
+begin
+
+  -- code from book:
+
+  erroneous : process is
+                        variable i, j : integer;
+  begin
+    i := loop_param;          -- error!
+    for loop_param in 1 to 10 loop
+      loop_param := 5;        -- error!
+    end loop;
+    j := loop_param;          -- error!
+  end process erroneous;
+
+  -- end of code from book
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_03.vhd b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_03.vhd
new file mode 100644
index 0000000..7cbf47b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_03.vhd
@@ -0,0 +1,131 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_03.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_03 is
+
+end entity ch_04_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_03 is
+
+  subtype coeff_ram_address is integer range 0 to 63;
+
+  -- code from book:
+
+  type coeff_array is array (coeff_ram_address) of real;
+
+  -- end of code from book
+
+begin
+
+
+  process_04_1_c : process is
+
+                             -- code from book:
+
+                             type point is array (1 to 3) of real;
+                           constant origin : point := (0.0, 0.0, 0.0);
+                           variable view_point : point := (10.0, 20.0, 0.0);
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_04_1_c;
+
+
+  process_04_1_d : process is
+
+                             type point is array (1 to 3) of real;
+
+                           -- code from book:
+
+                           variable view_point : point := (1 => 10.0, 2 => 20.0, 3 => 0.0);
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_04_1_d;
+
+
+  process_04_1_e : process is
+
+                             -- code from book:
+
+                             variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, 3 to 63 => 0.0);
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_04_1_e;
+
+
+  process_04_1_f : process is
+
+                             -- code from book:
+
+                             variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, others => 0.0);
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_04_1_f;
+
+
+  process_04_1_g : process is
+
+                             -- code from book:
+
+                             variable coeff : coeff_array := (0 | 2 => 1.6, 1 => 2.3, others => 0.0);
+
+                           -- end of code from book
+
+  begin
+    wait;
+  end process process_04_1_g;
+
+
+  process_04_1_h : process is
+
+                             -- code from book:
+
+                             -- error: Associations in array aggregate must be all named or all positional
+                             -- variable coeff : coeff_array := (1.6, 2.3, 2 => 1.6, others => 0.0);  -- illegal
+
+                             -- end of code from book
+
+  begin
+    wait;
+  end process process_04_1_h;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_09.vhd b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_09.vhd
new file mode 100644
index 0000000..661407f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_04_ch_04_09.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_04_ch_04_09.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ch_04_09 is
+
+end entity ch_04_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of ch_04_09 is
+begin
+
+
+  process_04_3_c : process is
+
+                             -- code from book:
+
+                             subtype name is string(1 to 20);
+                           type display_string is array (integer range 0 to 19) of character;
+
+                           variable item_name : name;
+                           variable display : display_string;
+
+                           --
+
+                           subtype big_endian_upper_halfword is bit_vector(0 to 15);
+                           subtype little_endian_upper_halfword is bit_vector(31 downto 16);
+
+                           variable big : big_endian_upper_halfword;
+                           variable little : little_endian_upper_halfword;
+
+                           -- end of code from book
+
+  begin
+
+    -- error: Incompatible types for assignment
+    -- display := item_name;  -- ilegal
+
+    item_name := (others => 'A');
+
+    little := x"AAAA";
+
+    -- code from book:
+
+    display := display_string(item_name);
+
+    --
+
+    big := little;
+    little := big;
+
+    -- end of code from book
+
+    wait;
+  end process process_04_3_c;
+
+
+  ----------------
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_12.vhd b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_12.vhd
new file mode 100644
index 0000000..f57c9ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_12.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_12.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package «element_type_simple_name»_ordered_collection_adt is
+
+  -- template: fill in the placeholders to specialize for a particular type
+
+  alias element_type is «element_type»;
+  alias key_type is «key_type»;
+  alias key_of is «key_function» [ element_type return key_type ];
+  alias "<" is «less_than_function» [ key_type, key_type return boolean ];
+
+  -- types provided by the package
+
+  type ordered_collection_object;    -- private
+  type position_object;              -- private
+
+  type ordered_collection is access ordered_collection_object;
+  type position is access position_object;
+
+  -- operations on ordered collections
+
+  function new_ordered_collection return ordered_collection;
+  -- returns an empty ordered collection of element_type values
+
+  procedure insert ( c : inout ordered_collection;  e : in element_type );
+  -- inserts e into c in position determined by key_of(e)
+
+  procedure get_element ( variable p : in position;  e : out element_type );
+  -- returns the element value at position p in its collection
+
+  procedure test_null_position ( variable p : in position;  is_null : out boolean );
+  -- test whether p refers to no position in its collection
+
+  procedure search ( variable c : in ordered_collection;  k : in key_type;
+  p : out position );
+  -- searches for an element with key k in c, and returns the position of
+  -- that element, or, if not found, a position for which test_null_position
+  -- returns true
+
+  procedure find_first ( variable c : in ordered_collection;  p : out position );
+  -- returns the position of the first element of c
+
+  procedure advance ( p : inout position );
+  -- advances p to the next element in its collection,
+  -- or if there are no more, sets p so that test_null_position returns true
+
+  procedure delete ( p : inout position );
+  -- deletes the element at position p from its collection, and advances p
+
+  -- private types: pretend these are not visible
+
+  type ordered_collection_object is
+    record
+      element : element_type;
+      next_element, prev_element : ordered_collection;
+    end record ordered_collection_object;
+
+  type position_object is
+    record
+      the_collection : ordered_collection;
+      current_element : ordered_collection;
+    end record position_object;
+
+end package «element_type_simple_name»_ordered_collection_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_14.vhd b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_14.vhd
new file mode 100644
index 0000000..ad47459
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_14.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_14.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- not in book
+
+entity test_bench is
+end entity test_bench;
+
+-- end not in book
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture initial_test of test_bench is
+
+  use work.stimulus_types.all;
+
+  -- . . .    -- component and signal declarations
+
+  -- not in book
+  signal dut_signals : std_logic_vector(0 to stimulus_vector_length - 1);
+  -- end not in book
+
+begin
+
+  -- . . .    -- instantiate design under test
+
+  stimulus_generation : process is
+
+                                  use work.stimulus_element_ordered_collection_adt.all;
+
+                                variable stimulus_list : ordered_collection := new_ordered_collection;
+                                variable next_stimulus_position : position;
+                                variable next_stimulus : stimulus_element;
+                                variable position_is_null : boolean;
+
+  begin
+    insert(stimulus_list, stimulus_element'(0 ns, "0XXXXXXXXX"));
+    insert(stimulus_list, stimulus_element'(200 ns, "0000110110"));
+    insert(stimulus_list, stimulus_element'(300 ns, "10001ZZZZZ"));
+    insert(stimulus_list, stimulus_element'(50 ns, "1XXXXXXXXX"));
+    insert(stimulus_list, stimulus_element'(60 ns, "1ZZZZZZZZZ"));
+    -- . . .
+    -- not in book
+    insert(stimulus_list, stimulus_element'(100 ns, "----------"));
+    search(stimulus_list, 100 ns, next_stimulus_position);
+    delete(next_stimulus_position);
+    get_element(next_stimulus_position, next_stimulus);
+    -- end not in book
+    find_first(stimulus_list, next_stimulus_position);
+    loop
+      test_null_position(next_stimulus_position, position_is_null);
+      exit when position_is_null;
+      get_element(next_stimulus_position, next_stimulus);
+      wait for next_stimulus.application_time - now;
+      dut_signals <= next_stimulus.pattern;
+      advance(next_stimulus_position);
+    end loop;
+    wait;
+  end process stimulus_generation;
+
+end architecture initial_test;
diff --git a/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_16.vhd b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_16.vhd
new file mode 100644
index 0000000..0f4e934
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/non_compliant/ch_17_fg_17_16.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ch_17_fg_17_16.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package body «element_type_simple_name»_ordered_collection_adt is
+
+  function new_ordered_collection return ordered_collection is
+    variable result : ordered_collection := new ordered_collection_object;
+  begin
+    result.next_element := result;
+    result.prev_element := result;
+    return result;
+  end function new_ordered_collection;
+
+  procedure insert ( c : inout ordered_collection;  e : in element_type ) is
+    variable current_element : ordered_collection := c.next_element;
+    variable new_element : ordered_collection;
+  begin
+    while current_element /= c
+      and key_of(current_element.element) < key_of(e) loop
+      current_element := current_element.next_element;
+    end loop;
+    -- insert new element before current_element
+    new_element := new ordered_collection_object'(
+      element => e,
+      next_element => current_element,
+      prev_element => current_element.prev_element );
+    new_element.next_element.prev_element := new_element;
+    new_element.prev_element.next_element := new_element;
+  end procedure insert;
+
+  procedure get_element ( variable p : in position;  e : out element_type ) is
+  begin
+    e := p.current_element.element;
+  end procedure get_element;
+
+  procedure test_null_position ( variable p : in position;  is_null : out boolean ) is
+  begin
+    is_null := p.current_element = p.the_collection;
+  end procedure test_null_position;
+
+  procedure search ( variable c : in ordered_collection;  k : in key_type;
+  p : out position ) is
+    variable current_element : ordered_collection := c.next_element;
+  begin
+    while current_element /= c
+      and key_of(current_element.element) < k loop
+      current_element := current_element.next_element;
+    end loop;
+    if current_element = c or k < key_of(current_element.element) then
+      p := new position_object'(c, c);  -- null position
+    else
+      p := new position_object'(c, current_element);
+    end if;
+  end procedure search;
+
+  procedure find_first ( variable c : in ordered_collection;  p : out position ) is
+  begin
+    p := new position_object'(c, c.next_element);
+  end procedure find_first;
+
+  procedure advance ( p : inout position ) is
+    variable is_null : boolean;
+  begin
+    test_null_position(p, is_null);
+    if not is_null then
+      p.current_element := p.current_element.next_element;
+    end if;
+  end procedure advance;
+
+  procedure delete ( p : inout position ) is
+    variable is_null : boolean;
+  begin
+    test_null_position(p, is_null);
+    if not is_null then
+      p.current_element.next_element.prev_element
+        := p.current_element.prev_element;
+      p.current_element.prev_element.next_element
+        := p.current_element.next_element;
+      p.current_element := p.current_element.next_element;
+    end if;
+  end procedure delete;
+
+end package body «element_type_simple_name»_ordered_collection_adt;
diff --git a/testsuite/vests/vhdl-93/ashenden/non_compliant/non_compliant.exp b/testsuite/vests/vhdl-93/ashenden/non_compliant/non_compliant.exp
new file mode 100644
index 0000000..28d1643
--- /dev/null
+++ b/testsuite/vests/vhdl-93/ashenden/non_compliant/non_compliant.exp
@@ -0,0 +1,50 @@
+
+# Copyright (C) 2001 Clifton Labs, Inc
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  
+
+# Please email any bugs, comments, and/or additions to this file to:
+# vests@cliftonlabs.com
+
+# Authors: Philip A. Wilsey	philip.wilsey@ieee.org
+# 	   Dale E. Martin	dmartin@cliftonlabs.com
+
+# $Author: paw $
+# $Revision: 1.1 $
+
+# ------------------------------------------------------------------------
+#
+# $Id: non_compliant.exp,v 1.1 2001-10-19 23:28:54 paw Exp $
+#
+# ------------------------------------------------------------------------
+
+setup_test_group "Ashenden:Non-compliant Cases" "1076-1993"
+
+run_non_compliant_test ch_02_ch_02_01.vhd
+run_non_compliant_test ch_03_ch_03_09.vhd
+run_non_compliant_test ch_03_ch_03_15.vhd
+run_non_compliant_test ch_04_ch_04_03.vhd
+run_non_compliant_test ch_04_ch_04_09.vhd
+run_non_compliant_test ch_17_fg_17_12.vhd
+run_non_compliant_test ch_17_fg_17_14.vhd
+run_non_compliant_test ch_17_fg_17_16.vhd
+
+end_test_group
+
+# $Log: non_compliant.exp,v $
+# Revision 1.1  2001-10-19 23:28:54  paw
+# Adding dejagnu scripts to run ashenden's test cases.
+#
+
diff --git a/testsuite/vests/vhdl-93/billowitch/README b/testsuite/vests/vhdl-93/billowitch/README
new file mode 100644
index 0000000..80149ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/README
@@ -0,0 +1,26 @@
+
+This directory contains copies of the VHDL files that were originally
+developed by Bill Billowitch to form a VHDL 1076-1987 test suite.  The
+development of the test suite was done with partial support of the
+United States Air Force.  Both Bill Billowitch and the Air Force have
+granted the University of Cincinnati permission to release these files
+under the GNU Public License.
+
+Since the original test suite was developed for the 1076-1987 standard,
+some changes were required to make them compliant with the 1076-1993
+standard; they are now not necessarily compilant with the earlier
+(1076-1987) standard.  The VHDL files are organized into three
+subdirectories, fail_tests, pass_tests or disputed_tests, corresponding
+to their being non-compliant, compliant, or in question to the 1076-1993
+standard (files in this subdirectory were originally located in the
+compliant subdirectory of the 1076-1987 test suite).
+
+If you find errors or corrections to these files, please submit them to
+us at vests@cliftonlabs.com.  Thank you.
+
+------------------------------------------------------------------------
+Philip A. Wilsey 
+The University of Cincinnati
+vests@cliftonlabs.com
+------------------------------------------------------------------------
+Last Revised: March 27, 2002
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/README b/testsuite/vests/vhdl-93/billowitch/compliant/README
new file mode 100644
index 0000000..d216c07
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/README
@@ -0,0 +1,8 @@
+The following files have been modified to be VHDL 93 compliant.  (In 
+VHDL 87, string literals like B"0010" had to be of type bit vector.  Now,
+they can be of any character type.)
+
+tc2759.vhd
+tc2761.vhd
+tc2767.vhd 
+tc2768.vhd
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/compliant.exp b/testsuite/vests/vhdl-93/billowitch/compliant/compliant.exp
new file mode 100644
index 0000000..28a9624
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/compliant.exp
@@ -0,0 +1,1693 @@
+
+# Copyright (C) Clifton Labs, Inc
+# All rights reserved.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  
+
+# This script should runs the tests in this subdirectory.  It should
+# only use functions that are defined (or redefined by the tool under
+# test) in vests.drivers.exp and the reporting functions in
+# vests-support.exp.  That way the integration of vests with another
+# VHDL system requires only the redefinition of the functions in
+# vests-drivers.exp. 
+
+setup_test_group "Billowitch:Compliant Cases" "1076-1993"
+
+run_compliant_test tc1.vhd
+
+run_compliant_test tc10.vhd
+run_compliant_test tc14.vhd
+run_compliant_test tc15.vhd
+run_compliant_test tc17.vhd
+run_compliant_test tc18.vhd
+run_compliant_test tc23.vhd
+run_compliant_test tc24.vhd
+run_compliant_test tc25.vhd
+run_compliant_test tc26.vhd
+run_compliant_test tc27.vhd
+run_compliant_test tc29.vhd
+run_compliant_test tc30.vhd
+run_compliant_test tc31.vhd
+run_compliant_test tc32.vhd
+run_compliant_test tc33.vhd
+run_compliant_test tc35.vhd
+run_compliant_test tc36.vhd
+run_compliant_test tc37.vhd
+run_compliant_test tc38.vhd
+run_compliant_test tc39.vhd
+run_compliant_test tc40.vhd
+run_compliant_test tc41.vhd
+run_compliant_test tc43.vhd
+run_compliant_test tc45.vhd
+run_compliant_test tc52.vhd
+run_compliant_test tc53.vhd
+run_compliant_test tc54.vhd
+run_compliant_test tc56.vhd
+run_compliant_test tc63.vhd
+run_compliant_test tc64.vhd
+run_compliant_test tc66.vhd
+run_compliant_test tc68.vhd
+run_compliant_test tc69.vhd
+run_compliant_test tc70.vhd
+run_compliant_test tc76.vhd
+run_compliant_test tc80.vhd
+run_compliant_test tc81.vhd
+run_compliant_test tc82.vhd
+run_compliant_test tc83.vhd
+run_compliant_test tc84.vhd
+run_compliant_test tc86.vhd
+run_compliant_test tc87.vhd
+run_compliant_test tc88.vhd
+run_compliant_test tc90.vhd
+run_compliant_test tc91.vhd
+run_compliant_test tc98.vhd
+run_compliant_test tc99.vhd
+
+run_compliant_test tc100.vhd
+run_compliant_test tc110.vhd
+run_compliant_test tc111.vhd
+run_compliant_test tc113.vhd
+run_compliant_test tc114.vhd
+run_compliant_test tc115.vhd
+run_compliant_test tc116.vhd
+run_compliant_test tc117.vhd
+run_compliant_test tc118.vhd
+run_compliant_test tc119.vhd
+run_compliant_test tc131.vhd
+run_compliant_test tc133.vhd
+run_compliant_test tc134.vhd
+run_compliant_test tc135.vhd
+run_compliant_test tc136.vhd
+run_compliant_test tc137.vhd
+run_compliant_test tc138.vhd
+run_compliant_test tc141.vhd
+run_compliant_test tc143.vhd
+run_compliant_test tc146.vhd
+run_compliant_test tc147.vhd
+run_compliant_test tc148.vhd
+run_compliant_test tc149.vhd
+run_compliant_test tc150.vhd
+run_compliant_test tc154.vhd
+run_compliant_test tc157.vhd
+run_compliant_test tc158.vhd
+run_compliant_test tc162.vhd
+run_compliant_test tc163.vhd
+run_compliant_test tc164.vhd
+run_compliant_test tc166.vhd
+run_compliant_test tc167.vhd
+run_compliant_test tc168.vhd
+run_compliant_test tc169.vhd
+run_compliant_test tc171.vhd
+run_compliant_test tc172.vhd
+run_compliant_test tc173.vhd
+run_compliant_test tc176.vhd
+run_compliant_test tc179.vhd
+run_compliant_test tc180.vhd
+run_compliant_test tc182.vhd
+run_compliant_test tc183.vhd
+run_compliant_test tc187.vhd
+run_compliant_test tc188.vhd
+run_compliant_test tc194.vhd
+run_compliant_test tc198.vhd
+run_compliant_test tc201.vhd
+run_compliant_test tc203.vhd
+run_compliant_test tc204.vhd
+run_compliant_test tc205.vhd
+run_compliant_test tc206.vhd
+run_compliant_test tc208.vhd
+run_compliant_test tc209.vhd
+run_compliant_test tc211.vhd
+run_compliant_test tc213.vhd
+run_compliant_test tc217.vhd
+run_compliant_test tc218.vhd
+run_compliant_test tc219.vhd
+run_compliant_test tc220.vhd
+run_compliant_test tc228.vhd
+run_compliant_test tc229.vhd
+run_compliant_test tc230.vhd
+run_compliant_test tc234.vhd
+run_compliant_test tc239.vhd
+run_compliant_test tc241.vhd
+run_compliant_test tc251.vhd
+run_compliant_test tc254.vhd
+run_compliant_test tc265.vhd
+run_compliant_test tc272.vhd
+run_compliant_test tc276.vhd
+run_compliant_test tc277.vhd
+run_compliant_test tc278.vhd
+run_compliant_test tc279.vhd
+run_compliant_test tc281.vhd
+run_compliant_test tc284.vhd
+run_compliant_test tc285.vhd
+run_compliant_test tc286.vhd
+run_compliant_test tc287.vhd
+run_compliant_test tc288.vhd
+run_compliant_test tc290.vhd
+run_compliant_test tc291.vhd
+run_compliant_test tc292.vhd
+run_compliant_test tc293.vhd
+run_compliant_test tc294.vhd
+run_compliant_test tc295.vhd
+run_compliant_test tc297.vhd
+run_compliant_test tc298.vhd
+run_compliant_test tc299.vhd
+run_compliant_test tc301.vhd
+run_compliant_test tc308.vhd
+run_compliant_test tc309.vhd
+run_compliant_test tc311.vhd
+run_compliant_test tc312.vhd
+run_compliant_test tc313.vhd
+run_compliant_test tc314.vhd
+run_compliant_test tc317.vhd
+run_compliant_test tc318.vhd
+run_compliant_test tc319.vhd
+run_compliant_test tc320.vhd
+run_compliant_test tc322.vhd
+run_compliant_test tc323.vhd
+run_compliant_test tc326.vhd
+run_compliant_test tc333.vhd
+run_compliant_test tc334.vhd
+run_compliant_test tc335.vhd
+run_compliant_test tc337.vhd
+run_compliant_test tc339.vhd
+run_compliant_test tc341.vhd
+run_compliant_test tc343.vhd
+run_compliant_test tc344.vhd
+run_compliant_test tc346.vhd
+run_compliant_test tc347.vhd
+run_compliant_test tc349.vhd
+run_compliant_test tc350.vhd
+run_compliant_test tc351.vhd
+run_compliant_test tc355.vhd
+run_compliant_test tc359.vhd
+run_compliant_test tc361.vhd
+run_compliant_test tc364.vhd
+run_compliant_test tc365.vhd
+run_compliant_test tc366.vhd
+run_compliant_test tc376.vhd
+run_compliant_test tc377.vhd
+run_compliant_test tc378.vhd
+run_compliant_test tc381.vhd
+run_compliant_test tc382.vhd
+run_compliant_test tc385.vhd
+run_compliant_test tc386.vhd
+run_compliant_test tc387.vhd
+run_compliant_test tc388.vhd
+run_compliant_test tc392.vhd
+run_compliant_test tc393.vhd
+run_compliant_test tc395.vhd
+run_compliant_test tc397.vhd
+run_compliant_test tc398.vhd
+run_compliant_test tc399.vhd
+run_compliant_test tc400.vhd
+run_compliant_test tc401.vhd
+run_compliant_test tc402.vhd
+run_compliant_test tc403.vhd
+run_compliant_test tc404.vhd
+run_compliant_test tc406.vhd
+run_compliant_test tc407.vhd
+run_compliant_test tc408.vhd
+run_compliant_test tc409.vhd
+run_compliant_test tc410.vhd
+run_compliant_test tc411.vhd
+run_compliant_test tc412.vhd
+run_compliant_test tc413.vhd
+run_compliant_test tc414.vhd
+run_compliant_test tc415.vhd
+run_compliant_test tc416.vhd
+run_compliant_test tc417.vhd
+run_compliant_test tc418.vhd
+run_compliant_test tc419.vhd
+run_compliant_test tc420.vhd
+run_compliant_test tc421.vhd
+run_compliant_test tc422.vhd
+run_compliant_test tc423.vhd
+run_compliant_test tc424.vhd
+run_compliant_test tc425.vhd
+run_compliant_test tc426.vhd
+run_compliant_test tc427.vhd
+run_compliant_test tc428.vhd
+run_compliant_test tc429.vhd
+run_compliant_test tc430.vhd
+run_compliant_test tc431.vhd
+run_compliant_test tc432.vhd
+run_compliant_test tc433.vhd
+run_compliant_test tc434.vhd
+run_compliant_test tc435.vhd
+run_compliant_test tc436.vhd
+run_compliant_test tc437.vhd
+run_compliant_test tc438.vhd
+run_compliant_test tc439.vhd
+run_compliant_test tc440.vhd
+run_compliant_test tc441.vhd
+run_compliant_test tc442.vhd
+run_compliant_test tc443.vhd
+run_compliant_test tc444.vhd
+run_compliant_test tc445.vhd
+run_compliant_test tc446.vhd
+run_compliant_test tc447.vhd
+run_compliant_test tc448.vhd
+run_compliant_test tc449.vhd
+run_compliant_test tc450.vhd
+run_compliant_test tc451.vhd
+run_compliant_test tc452.vhd
+run_compliant_test tc453.vhd
+run_compliant_test tc454.vhd
+run_compliant_test tc455.vhd
+run_compliant_test tc456.vhd
+run_compliant_test tc457.vhd
+run_compliant_test tc458.vhd
+run_compliant_test tc459.vhd
+run_compliant_test tc460.vhd
+run_compliant_test tc461.vhd
+run_compliant_test tc462.vhd
+run_compliant_test tc463.vhd
+run_compliant_test tc464.vhd
+run_compliant_test tc465.vhd
+run_compliant_test tc466.vhd
+run_compliant_test tc467.vhd
+run_compliant_test tc468.vhd
+run_compliant_test tc469.vhd
+run_compliant_test tc470.vhd
+run_compliant_test tc471.vhd
+run_compliant_test tc472.vhd
+run_compliant_test tc473.vhd
+run_compliant_test tc474.vhd
+run_compliant_test tc475.vhd
+run_compliant_test tc476.vhd
+run_compliant_test tc477.vhd
+run_compliant_test tc478.vhd
+run_compliant_test tc479.vhd
+run_compliant_test tc480.vhd
+run_compliant_test tc481.vhd
+run_compliant_test tc482.vhd
+run_compliant_test tc483.vhd
+run_compliant_test tc484.vhd
+run_compliant_test tc485.vhd
+run_compliant_test tc486.vhd
+run_compliant_test tc487.vhd
+run_compliant_test tc488.vhd
+run_compliant_test tc489.vhd
+run_compliant_test tc490.vhd
+run_compliant_test tc491.vhd
+run_compliant_test tc492.vhd
+run_compliant_test tc493.vhd
+run_compliant_test tc494.vhd
+run_compliant_test tc495.vhd
+run_compliant_test tc496.vhd
+run_compliant_test tc497.vhd
+run_compliant_test tc498.vhd
+run_compliant_test tc499.vhd
+run_compliant_test tc500.vhd
+run_compliant_test tc501.vhd
+run_compliant_test tc503.vhd
+run_compliant_test tc505.vhd
+run_compliant_test tc512.vhd
+run_compliant_test tc513.vhd
+run_compliant_test tc515.vhd
+run_compliant_test tc516.vhd
+run_compliant_test tc517.vhd
+run_compliant_test tc519.vhd
+run_compliant_test tc520.vhd
+run_compliant_test tc521.vhd
+run_compliant_test tc522.vhd
+run_compliant_test tc523.vhd
+run_compliant_test tc524.vhd
+run_compliant_test tc525.vhd
+run_compliant_test tc526.vhd
+run_compliant_test tc527.vhd
+run_compliant_test tc528.vhd
+run_compliant_test tc529.vhd
+run_compliant_test tc530.vhd
+run_compliant_test tc531.vhd
+run_compliant_test tc534.vhd
+run_compliant_test tc535.vhd
+run_compliant_test tc537.vhd
+run_compliant_test tc538.vhd
+run_compliant_test tc539.vhd
+run_compliant_test tc541.vhd
+run_compliant_test tc542.vhd
+run_compliant_test tc544.vhd
+run_compliant_test tc545.vhd
+run_compliant_test tc546.vhd
+run_compliant_test tc554.vhd INPUT=iofile.10:iofiles/iofile.10
+run_compliant_test tc555.vhd OUTPUT=iofile.10:iofiles/iofile.10
+run_compliant_test tc556.vhd OUTPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc557.vhd OUTPUT=iofile.08:iofiles/iofile.08
+run_compliant_test tc558.vhd INPUT=iofile.08:iofiles/iofile.08
+run_compliant_test tc559.vhd INPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc560.vhd OUTPUT=iofile.16:iofiles/iofile.16
+run_compliant_test tc561.vhd INPUT=iofile.16:iofiles/iofile.16
+run_compliant_test tc562.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc563.vhd OUTPUT=iofile.17:iofiles/iofile.17
+run_compliant_test tc564.vhd INPUT=iofile.17:iofiles/iofile.17
+run_compliant_test tc565.vhd OUTPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc566.vhd OUTPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc567.vhd INPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc568.vhd INPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc569.vhd OUTPUT=iofile.19:iofiles/iofile.19
+run_compliant_test tc570.vhd INPUT=iofile.19:iofiles/iofile.19
+run_compliant_test tc571.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc572.vhd OUTPUT=iofile.20:iofiles/iofile.20
+run_compliant_test tc573.vhd INPUT=iofile.20:iofiles/iofile.20
+run_compliant_test tc574.vhd OUTPUT=iofile.28:iofiles/iofile.28
+run_compliant_test tc575.vhd OUTPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc576.vhd INPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc577.vhd INPUT=iofile.28:iofiles/iofile.28
+run_compliant_test tc578.vhd OUTPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc579.vhd INPUT=iofile.18:iofiles/iofile.18
+run_compliant_test tc580.vhd OUTPUT=iofile.28:iofiles/iofile.28
+run_compliant_test tc581.vhd OUTPUT=iofile.21:iofiles/iofile.21
+run_compliant_test tc582.vhd INPUT=iofile.21:iofiles/iofile.21
+run_compliant_test tc583.vhd OUTPUT=iofile.29:iofiles/iofile.29
+run_compliant_test tc584.vhd OUTPUT=iofile.22:iofiles/iofile.22
+run_compliant_test tc585.vhd INPUT=iofile.22:iofiles/iofile.22
+run_compliant_test tc586.vhd OUTPUT=iofile.31:iofiles/iofile.31
+run_compliant_test tc587.vhd OUTPUT=iofile.23:iofiles/iofile.23
+run_compliant_test tc588.vhd INPUT=iofile.23:iofiles/iofile.23
+run_compliant_test tc589.vhd INPUT=iofile.31:iofiles/iofile.31
+run_compliant_test tc590.vhd OUTPUT=iofile.24:iofiles/iofile.24
+run_compliant_test tc591.vhd INPUT=iofile.24:iofiles/iofile.24
+run_compliant_test tc592.vhd INPUT=iofile.29:iofiles/iofile.29
+run_compliant_test tc593.vhd OUTPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc594.vhd INPUT=iofile.25:iofiles/iofile.25
+run_compliant_test tc595.vhd INPUT=iofile.28:iofiles/iofile.28
+run_compliant_test tc596.vhd OUTPUT=iofile.26:iofiles/iofile.26
+run_compliant_test tc597.vhd INPUT=iofile.26:iofiles/iofile.26
+run_compliant_test tc598.vhd OUTPUT=iofile.32:iofiles/iofile.32
+run_compliant_test tc599.vhd OUTPUT=iofile.27:iofiles/iofile.27
+run_compliant_test tc600.vhd INPUT=iofile.27:iofiles/iofile.27
+run_compliant_test tc601.vhd INPUT=iofile.32:iofiles/iofile.32
+run_compliant_test tc602.vhd OUTPUT=iofile.32:iofiles/iofile.32
+run_compliant_test tc603.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc604.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc605.vhd OUTPUT=iofile.29:iofiles/iofile.29
+run_compliant_test tc606.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc607.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc608.vhd INPUT=iofile.29:iofiles/iofile.29
+run_compliant_test tc609.vhd OUTPUT=iofile.33:iofiles/iofile.33
+run_compliant_test tc610.vhd INPUT=iofile.33:iofiles/iofile.33
+run_compliant_test tc611.vhd INPUT=iofile.32:iofiles/iofile.32
+run_compliant_test tc612.vhd OUTPUT=iofile.34:iofiles/iofile.34
+run_compliant_test tc613.vhd INPUT=iofile.34:iofiles/iofile.34
+run_compliant_test tc614.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc615.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc616.vhd OUTPUT=iofile.34:iofiles/iofile.34
+run_compliant_test tc617.vhd OUTPUT=iofile.31:iofiles/iofile.31
+run_compliant_test tc618.vhd INPUT=iofile.31:iofiles/iofile.31
+run_compliant_test tc619.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc620.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc621.vhd INPUT=iofile.34:iofiles/iofile.34
+run_compliant_test tc622.vhd OUTPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc623.vhd INPUT=iofile.30:iofiles/iofile.30
+run_compliant_test tc624.vhd OUTPUT=iofile.36:iofiles/iofile.36
+run_compliant_test tc625.vhd OUTPUT=iofile.35:iofiles/iofile.35
+run_compliant_test tc626.vhd INPUT=iofile.35:iofiles/iofile.35
+run_compliant_test tc627.vhd INPUT=iofile.36:iofiles/iofile.36
+run_compliant_test tc628.vhd OUTPUT=iofile.40:iofiles/iofile.40
+run_compliant_test tc629.vhd OUTPUT=iofile.37:iofiles/iofile.37
+run_compliant_test tc630.vhd INPUT=iofile.37:iofiles/iofile.37
+run_compliant_test tc631.vhd INPUT=iofile.40:iofiles/iofile.40
+run_compliant_test tc632.vhd OUTPUT=iofile.38:iofiles/iofile.38
+run_compliant_test tc633.vhd INPUT=iofile.38:iofiles/iofile.38
+run_compliant_test tc634.vhd OUTPUT=iofile.43:iofiles/iofile.43
+run_compliant_test tc635.vhd OUTPUT=iofile.39:iofiles/iofile.39
+run_compliant_test tc636.vhd INPUT=iofile.39:iofiles/iofile.39
+run_compliant_test tc637.vhd OUTPUT=iofile.41:iofiles/iofile.41
+run_compliant_test tc638.vhd INPUT=iofile.41:iofiles/iofile.41
+run_compliant_test tc639.vhd INPUT=iofile.43:iofiles/iofile.43
+run_compliant_test tc640.vhd OUTPUT=iofile.42:iofiles/iofile.42
+run_compliant_test tc641.vhd INPUT=iofile.42:iofiles/iofile.42
+run_compliant_test tc642.vhd OUTPUT=iofile.44:iofiles/iofile.44
+run_compliant_test tc643.vhd OUTPUT=iofile.46:iofiles/iofile.46
+run_compliant_test tc644.vhd INPUT=iofile.44:iofiles/iofile.44
+run_compliant_test tc645.vhd INPUT=iofile.46:iofiles/iofile.46
+run_compliant_test tc646.vhd OUTPUT=iofile.62:iofiles/iofile.62
+run_compliant_test tc647.vhd INPUT=iofile.62:iofiles/iofile.62
+run_compliant_test tc648.vhd OUTPUT=iofile.01:iofiles/iofile.01
+run_compliant_test tc649.vhd OUTPUT=iofile.63:iofiles/iofile.63
+run_compliant_test tc650.vhd INPUT=iofile.63:iofiles/iofile.63
+run_compliant_test tc651.vhd INPUT=iofile.01:iofiles/iofile.01
+run_compliant_test tc652.vhd OUTPUT=iofile.45:iofiles/iofile.45
+run_compliant_test tc653.vhd INPUT=iofile.45:iofiles/iofile.45
+run_compliant_test tc654.vhd OUTPUT=iofile.03:iofiles/iofile.03
+run_compliant_test tc655.vhd INPUT=iofile.03:iofiles/iofile.03
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+run_compliant_test tc2738.vhd
+run_compliant_test tc2739.vhd
+run_compliant_test tc2740.vhd
+run_compliant_test tc2742.vhd
+run_compliant_test tc2743.vhd
+run_compliant_test tc2744.vhd
+run_compliant_test tc2745.vhd
+run_compliant_test tc2747.vhd
+run_compliant_test tc2758.vhd
+run_compliant_test tc2759.vhd
+run_compliant_test tc2760.vhd
+run_compliant_test tc2761.vhd
+run_compliant_test tc2765.vhd
+run_compliant_test tc2767.vhd
+run_compliant_test tc2768.vhd
+run_compliant_test tc2769.vhd
+run_compliant_test tc2771.vhd
+run_compliant_test tc2853.vhd
+run_compliant_test tc2854.vhd
+run_compliant_test tc2860.vhd
+run_compliant_test tc2861.vhd
+run_compliant_test tc2862.vhd
+run_compliant_test tc2863.vhd
+run_compliant_test tc2864.vhd
+run_compliant_test tc2865.vhd
+run_compliant_test tc2866.vhd
+run_compliant_test tc2868.vhd
+run_compliant_test tc2870.vhd
+run_compliant_test tc2874.vhd
+run_compliant_test tc2876.vhd
+run_compliant_test tc2879.vhd
+run_compliant_test tc2880.vhd
+run_compliant_test tc2881.vhd
+run_compliant_test tc2882.vhd
+run_compliant_test tc2883.vhd
+run_compliant_test tc2900.vhd
+run_compliant_test tc2901.vhd
+run_compliant_test tc2902.vhd
+run_compliant_test tc2903.vhd
+run_compliant_test tc2904.vhd
+run_compliant_test tc2917.vhd
+run_compliant_test tc2918.vhd
+run_compliant_test tc2932.vhd
+run_compliant_test tc2945.vhd
+run_compliant_test tc2948.vhd
+run_compliant_test tc2949.vhd
+run_compliant_test tc2950.vhd
+run_compliant_test tc2951.vhd
+run_compliant_test tc2952.vhd
+run_compliant_test tc2955.vhd
+run_compliant_test tc2959.vhd
+run_compliant_test tc2960.vhd
+run_compliant_test tc2961.vhd
+run_compliant_test tc2962.vhd
+run_compliant_test tc2964.vhd
+run_compliant_test tc2966.vhd
+run_compliant_test tc2967.vhd
+run_compliant_test tc2968.vhd
+run_compliant_test tc2969.vhd
+run_compliant_test tc2972.vhd
+run_compliant_test tc2973.vhd
+run_compliant_test tc2974.vhd
+run_compliant_test tc2975.vhd
+run_compliant_test tc2976.vhd
+run_compliant_test tc2977.vhd
+run_compliant_test tc2978.vhd
+run_compliant_test tc2979.vhd
+run_compliant_test tc2980.vhd
+run_compliant_test tc2981.vhd
+run_compliant_test tc2982.vhd
+run_compliant_test tc2987.vhd
+run_compliant_test tc2988.vhd
+run_compliant_test tc2989.vhd
+run_compliant_test tc2990.vhd
+run_compliant_test tc3001.vhd
+run_compliant_test tc3005.vhd
+run_compliant_test tc3010.vhd
+run_compliant_test tc3016.vhd
+run_compliant_test tc3022.vhd
+run_compliant_test tc3023.vhd
+run_compliant_test tc3024.vhd
+run_compliant_test tc3029.vhd
+run_compliant_test tc3032.vhd
+run_compliant_test tc3033.vhd
+run_compliant_test tc3034.vhd
+run_compliant_test tc3035.vhd
+run_compliant_test tc3036.vhd
+run_compliant_test tc3037.vhd
+run_compliant_test tc3038.vhd
+run_compliant_test tc3039.vhd
+run_compliant_test tc3040.vhd
+run_compliant_test tc3041.vhd
+run_compliant_test tc3042.vhd
+run_compliant_test tc3043.vhd
+run_compliant_test tc3044.vhd
+run_compliant_test tc3045.vhd
+run_compliant_test tc3046.vhd
+run_compliant_test tc3047.vhd
+run_compliant_test tc3048.vhd
+run_compliant_test tc3049.vhd
+run_compliant_test tc3050.vhd
+run_compliant_test tc3051.vhd
+run_compliant_test tc3052.vhd
+run_compliant_test tc3053.vhd
+run_compliant_test tc3054.vhd
+run_compliant_test tc3055.vhd
+run_compliant_test tc3057.vhd
+run_compliant_test tc3059.vhd
+run_compliant_test tc3060.vhd
+run_compliant_test tc3061.vhd
+run_compliant_test tc3062.vhd
+run_compliant_test tc3063.vhd
+run_compliant_test tc3066.vhd
+run_compliant_test tc3067.vhd
+run_compliant_test tc3068.vhd
+run_compliant_test tc3069.vhd
+run_compliant_test tc3070.vhd
+run_compliant_test tc3071.vhd
+run_compliant_test tc3072.vhd
+run_compliant_test tc3073.vhd
+run_compliant_test tc3074.vhd
+run_compliant_test tc3075.vhd
+run_compliant_test tc3076.vhd
+run_compliant_test tc3077.vhd
+run_compliant_test tc3078.vhd
+run_compliant_test tc3079.vhd
+run_compliant_test tc3080.vhd
+run_compliant_test tc3081.vhd
+run_compliant_test tc3082.vhd
+run_compliant_test tc3083.vhd
+run_compliant_test tc3084.vhd
+run_compliant_test tc3085.vhd
+run_compliant_test tc3086.vhd
+run_compliant_test tc3099.vhd
+run_compliant_test tc3100.vhd
+run_compliant_test tc3101.vhd
+run_compliant_test tc3102.vhd
+run_compliant_test tc3109.vhd
+run_compliant_test tc3110.vhd
+run_compliant_test tc3111.vhd
+run_compliant_test tc3112.vhd
+run_compliant_test tc3113.vhd
+run_compliant_test tc3114.vhd
+run_compliant_test tc3115.vhd
+run_compliant_test tc3116.vhd
+run_compliant_test tc3117.vhd
+run_compliant_test tc3118.vhd
+run_compliant_test tc3119.vhd
+run_compliant_test tc3120.vhd
+run_compliant_test tc3121.vhd
+run_compliant_test tc3122.vhd
+run_compliant_test tc3123.vhd
+run_compliant_test tc3125.vhd
+run_compliant_test tc3126.vhd
+run_compliant_test tc3127.vhd
+run_compliant_test tc3128.vhd
+run_compliant_test tc3137.vhd
+run_compliant_test tc3138.vhd
+run_compliant_test tc3139.vhd
+run_compliant_test tc3140.vhd
+run_compliant_test tc3141.vhd
+run_compliant_test tc3142.vhd
+run_compliant_test tc3143.vhd
+run_compliant_test tc3144.vhd
+run_compliant_test tc3145.vhd
+run_compliant_test tc3146.vhd
+run_compliant_test tc3147.vhd
+run_compliant_test tc3148.vhd
+run_compliant_test tc3149.vhd
+run_compliant_test tc3150.vhd
+run_compliant_test tc3151.vhd
+run_compliant_test tc3152.vhd
+run_compliant_test tc3153.vhd
+run_compliant_test tc3154.vhd
+run_compliant_test tc3155.vhd
+run_compliant_test tc3156.vhd
+run_compliant_test tc3157.vhd
+run_compliant_test tc3158.vhd
+run_compliant_test tc3159.vhd
+run_compliant_test tc3160.vhd
+run_compliant_test tc3162.vhd
+run_compliant_test tc3163.vhd
+run_compliant_test tc3164.vhd
+run_compliant_test tc3165.vhd
+run_compliant_test tc3166.vhd
+run_compliant_test tc3167.vhd
+run_compliant_test tc3168.vhd
+run_compliant_test tc3169.vhd
+run_compliant_test tc3170.vhd
+run_compliant_test tc3171.vhd
+run_compliant_test tc3172.vhd
+run_compliant_test tc3173.vhd
+run_compliant_test tc3174.vhd
+run_compliant_test tc3175.vhd
+run_compliant_test tc3176.vhd
+run_compliant_test tc3177.vhd
+run_compliant_test tc3178.vhd
+run_compliant_test tc3179.vhd
+run_compliant_test tc3180.vhd
+run_compliant_test tc3181.vhd
+run_compliant_test tc3182.vhd
+run_compliant_test tc3183.vhd
+run_compliant_test tc3184.vhd
+run_compliant_test tc3185.vhd OUTPUT=iofile.02:iofiles/iofile.02
+run_compliant_test tc3186.vhd OUTPUT=iofile.01:iofiles/iofile.01
+run_compliant_test tc3187.vhd OUTPUT=iofile.04:iofiles/iofile.04
+run_compliant_test tc3188.vhd INPUT=iofile.06:iofiles/iofile.06
+run_compliant_test tc3189.vhd INPUT=iofile.02:iofiles/iofile.02
+run_compliant_test tc3190.vhd OUTPUT=iofile.08:iofiles/iofile.08
+run_compliant_test tc3191.vhd INPUT=iofile.04:iofiles/iofile.04
+run_compliant_test tc3192.vhd OUTPUT=iofile.06:iofiles/iofile.06
+run_compliant_test tc3193.vhd INPUT=iofile.08:iofiles/iofile.08
+run_compliant_test tc3194.vhd OUTPUT=iofile.09:iofiles/iofile.09
+run_compliant_test tc3195.vhd INPUT=iofile.09:iofiles/iofile.09
+run_compliant_test tc3196.vhd OUTPUT=iofile.10:iofiles/iofile.10
+run_compliant_test tc3197.vhd INPUT=iofile.10:iofiles/iofile.10
+run_compliant_test tc3198.vhd OUTPUT=iofile.12:iofiles/iofile.12
+run_compliant_test tc3199.vhd INPUT=iofile.12:iofiles/iofile.12
+run_compliant_test tc3200.vhd OUTPUT=iofile.14:iofiles/iofile.14
+run_compliant_test tc3201.vhd INPUT=iofile.14:iofiles/iofile.14
+run_compliant_test tc3202.vhd INPUT=iofile.61:iofiles/iofile.61
+run_compliant_test tc3203.vhd OUTPUT=iofile.61:iofiles/iofile.61
+run_compliant_test tc3204.vhd OUTPUT=iofile.47:iofiles/iofile.47
+run_compliant_test tc3205.vhd OUTPUT=iofile.64:iofiles/iofile.64
+run_compliant_test tc3206.vhd INPUT=iofile.64:iofiles/iofile.64
+
+end_test_group
+
+# $Log: compliant.exp,v $
+# Revision 1.6  2009-09-05 21:58:50  paw
+# Removing 4 empty shells of test cases from the list of test models to evaluate.
+#
+# Revision 1.5  2008-04-06 17:01:06  paw
+# Updated these vhdl files with filename strings that is consistent with the
+# rest of the regression setup.  Updated the runtest script (compliant.exp)
+# with these filenames.  This should change all these from failed to passed.
+#
+# Revision 1.4  2001-10-29 02:12:44  paw
+# Modifications for file IO.  I have replaced all the file names with
+# iofile.X and have placed all the files for savant in the subdirectory
+# iofiles.  Technically these files should be described using XML and we
+# should build translators to/from the files.  I'll leave that exercise for
+# another time.  In addition, I could build files only for those vhdl files
+# that we can build and simulate in savant; consequently there are still
+# about 5-6 tests with the old file names.  As the system matures so that
+# these tests execute, I will incorporate their iofiles (or point them at the
+# correct existing file should it already exist).
+#
+# Revision 1.3  2001/10/19 23:29:32  paw
+# Adding comments for cvs tracking information.
+#
+# Revision 1.2  2001/10/15 16:00:50  paw
+# Updating the compliant.exp script to properly use the functions in the new
+# savant test harness.
+#
+# Adding the scripts for non_compliant testing in the billowitch suite.
+#
+# When properly placed in the testsuite subdirectory of savant, a make check
+# will work.  Documentation will be added to the testsuite to describe how.
+#
+# Revision 1.1  2001/09/14 14:31:25  paw
+# This script sets up the group (Billowitch:Pass Cases) run and invokes
+# the run_compliant_test procedure for each file.  For those cases
+# requiring file input/output, additional modifications will be needed.
+#
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.01 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.01
new file mode 100644
index 0000000..9e58d8b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.01
@@ -0,0 +1,5 @@
+This is string 1
+__Hello  World__
+This is string 3
+_Bird is a word_
+_Goodbye (ciao)_
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.02 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.02
new file mode 100644
index 0000000..11b2fd7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.02
@@ -0,0 +1,100 @@
+1994
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.03 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.03
new file mode 100644
index 0000000..257145b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.03
@@ -0,0 +1,100 @@
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
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+3 3 3 3 3 3 3 3
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+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
+3 3 3 3 3 3 3 3
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.04 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.04
new file mode 100644
index 0000000..8bc3f65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.04
@@ -0,0 +1,100 @@
+1.994500e+03
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.05 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.05
new file mode 100644
index 0000000..8278c45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.05
@@ -0,0 +1,100 @@
+3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00
+3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00
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new file mode 100644
index 0000000..805caa4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.06
@@ -0,0 +1,100 @@
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.07 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.07
new file mode 100644
index 0000000..e88cfec
--- /dev/null
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.08 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.08
new file mode 100644
index 0000000..0e51709
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.08
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.11 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.11
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.12 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.12
new file mode 100644
index 0000000..5bb9123
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.12
@@ -0,0 +1,100 @@
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.13 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.13
new file mode 100644
index 0000000..4aa1d6b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.13
@@ -0,0 +1,100 @@
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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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+FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 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FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.14 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.14
new file mode 100644
index 0000000..46c0944
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.14
@@ -0,0 +1,100 @@
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.15 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.15
new file mode 100644
index 0000000..aa79d35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.15
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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 -1.000000e+38 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 NS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FALSE 0   NOTE -2147483648 -1.000000e+38 0 NS 0 1 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 -2147483648 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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.16 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.16
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index 0000000..26fb2a8
--- /dev/null
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.17 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.17
new file mode 100644
index 0000000..b7ea775
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.18 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.18
new file mode 100644
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.19 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.19
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new file mode 100644
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.25 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.25
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.28 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.28
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.29 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.29
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.30 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.30
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.31 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.31
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index 0000000..1b22109
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.33 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.33
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index 0000000..839aa9d
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.34 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.34
new file mode 100644
index 0000000..43230e5
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+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.35 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.35
new file mode 100644
index 0000000..c446c27
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.35
@@ -0,0 +1,100 @@
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+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
+TRUE 1 s NOTE 3 3.000000e+00 3 NS 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3.000000e+00 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 NS 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.51 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.51
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.52 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.52
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+WARNING
+WARNING
+WARNING
+WARNING
+WARNING
+WARNING
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.56 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.56
new file mode 100644
index 0000000..7c8423a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.56
@@ -0,0 +1,100 @@
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
+hello, world
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.57 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.57
new file mode 100644
index 0000000..d09402f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.57
@@ -0,0 +1,100 @@
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
+1 0 1 0 1
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.58 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.58
new file mode 100644
index 0000000..b43955f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.58
@@ -0,0 +1,100 @@
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
+1 10 NS
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.59 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.59
new file mode 100644
index 0000000..b8e7816
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.59
@@ -0,0 +1,5 @@
+1 This is string 1
+2 __Hello  World__
+3 This is string 3
+4 _Bird is a word_
+5 _Goodbye (ciao)_
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.60 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.60
new file mode 100644
index 0000000..885bec6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.60
@@ -0,0 +1,2 @@
+0 1 2 3 4 2 4 6 8 10 -2 -1 0 1 2 13 2 -45 6 1
+1 4 16 64 256 1 4 9 16 25 1 2 4 8 16 5 4 3 2 1
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.61 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.61
new file mode 100644
index 0000000..c7c491a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.61
@@ -0,0 +1,40 @@
+hello world
+
+0*          *          1**
+0 *         *          1**
+0  *        *          1**
+0   *       *          1**
+0    *      *          1**
+0     *     *          1**
+0      *    *          1**
+0       *   *          1**
+0        *  *          1**
+0         * *          1**
+
+1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1
+1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0
+1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0
+0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0
+0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0
+0                              1                              0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0                              0                              1
+0                              0                              1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0                              0                              0
+1                              0                              0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0                              1                              0
+0                              0                              0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1                              0                              0
+0                              1                              0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1                              0                              1
+0                              0                              0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0                              0                              1
+0                              0                              0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1                              0                              0
+0                              0                              0                              0                              0                              1                             *  *                               1                              1                              1                              1                              1                              1
+0                              0                              0                              1                             *  *                               1                              1                              1                              1
+0                              1                             *  *                               1                              1
+
+FALSE     * * TRUE
+FALSE    *  *  TRUE
+FALSE   *   *   TRUE
+FALSE  *    *    TRUE
+FALSE *     *     TRUE 
+FALSE*      *      TRUE  
+FALSE*       *       TRUE   
+FALSE*        *        TRUE    
+FALSE*         *         TRUE     
+FALSE*          *          TRUE      
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.62 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.62
new file mode 100644
index 0000000..5571755
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.62
@@ -0,0 +1,100 @@
+1000000000 na
+1000000000 na
+1000000000 na
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.63 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.63
new file mode 100644
index 0000000..7851b75
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.63
@@ -0,0 +1,100 @@
+1000000 uohm
+1000000 uohm
+1000000 uohm
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diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.64 b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.64
new file mode 100644
index 0000000..6c45c8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/iofiles/iofile.64
@@ -0,0 +1,24 @@
+3600000000000000000 fs
+3600000000000000000 fs
+3600000000000000000 fs
+3600000000000000000 fs
+3600000000000000000 fs
+
+-1 fs
+-1 fs
+-1 fs
+-1 fs
+-1 fs
+
+37582000000 fs
+37582000000 fs
+37582000000 fs
+37582000000 fs
+37582000000 fs
+
+1000001001000 fs
+1000001001000 fs
+1000001001000 fs
+1000001001000 fs
+1000001001000 fs
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1.vhd
new file mode 100644
index 0000000..0ab0d78
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s01b00x00p03n01i00001ent IS
+END c04s01b00x00p03n01i00001ent;
+
+ARCHITECTURE c04s01b00x00p03n01i00001arch OF c04s01b00x00p03n01i00001ent IS
+  type t1 is range 0.012345 to 300.012345;  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+    variable k : t1 := 10.0;
+  BEGIN
+    k := 123.0;
+    assert NOT( k=123.0 )
+      report "***PASSED TEST: c04s01b00x00p03n01i00001"
+      severity NOTE;
+    assert ( k=123.0 )
+      report "***FAILED TEST: c04s01b00x00p03n01i00001 - Type declaration has the format: the reserved word type followed by an identifier and the reserved word is."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s01b00x00p03n01i00001arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc10.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc10.vhd
new file mode 100644
index 0000000..17985ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc10.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc10.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p02n01i00010ent IS
+END c04s02b00x00p02n01i00010ent;
+
+ARCHITECTURE c04s02b00x00p02n01i00010arch OF c04s02b00x00p02n01i00010ent IS
+  subtype eight_bit       is integer range -32768 to 32767;       -- No_failure_here
+  subtype positive_8_bit    is eight_bit range 1 to 32767;     -- No_failure_here
+
+  -- an unconstrained array declaration
+  type  memory is array  (integer range <>) of bit;
+  subtype foo1 is memory (1 to 10);                      -- No_failure_here
+  subtype foo3 is memory (integer range 25 downto 2);    -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+    variable k1 : eight_bit    := 0;
+    variable k2 : positive_8_bit    := 10;
+    variable k3 : foo1       := ("1111111111");
+    variable k5 : foo3       := ("111111111111111111111111");
+  BEGIN
+    assert NOT(    k1 = 0         and
+                   k2 = 10         and
+                   k3 = "1111111111"   and
+                   k5 = "111111111111111111111111")
+      report "***PASSED TEST: c04s02b00x00p02n01i00010"
+      severity NOTE;
+    assert (    k1 = 0         and
+                k2 = 10         and
+                k3 = "1111111111"   and
+                k5 = "111111111111111111111111")
+      report "***FAILED TEST: c04s02b00x00p02n01i00010 - Subtype declaration syntactic format test fail."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p02n01i00010arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc100.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc100.vhd
new file mode 100644
index 0000000..8c62564
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc100.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc100.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x00p29n06i00100pkg is
+  type int_1 is range 1 to 32;
+  attribute pin_number : int_1;
+end c04s03b02x00p29n06i00100pkg;
+
+use work.c04s03b02x00p29n06i00100pkg.all;
+ENTITY c04s03b02x00p29n06i00100ent IS
+  port ( P2 : out bit) ;
+  attribute pin_number of P2 : signal is 1;
+END c04s03b02x00p29n06i00100ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00100arch OF c04s03b02x00p29n06i00100ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable pn : int_1;
+  BEGIN
+    pn := 1;
+    assert NOT( P2'pin_number = pn )
+      report "***PASSED TEST: c04s03b02x00p29n06i00100"      severity NOTE;
+    assert ( P2'pin_number = pn )
+      report "***FAILED TEST: c04s03b02x00p29n06i00100 - Reading user defined attributes of interface elements of mode 'out' should be permitted."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00100arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1009.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1009.vhd
new file mode 100644
index 0000000..9f9cfa9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1009.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1009.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01009pkg is
+  type T1 is record
+               S1 : Bit ;
+               S2 : Integer;
+             end record;
+  type T2 is record
+               S11 : BIT ;
+               S12 : T1 ;
+             end record;
+end c06s03b00x00p09n01i01009pkg;
+
+use work.c06s03b00x00p09n01i01009pkg.all;
+ENTITY c06s03b00x00p09n01i01009ent IS
+END c06s03b00x00p09n01i01009ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01009arch OF c06s03b00x00p09n01i01009ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : work.c06s03b00x00p09n01i01009pkg.T2 ;    -- No_failure_here
+  BEGIN
+    V1.S11    := '1';
+    V1.S12.S1 := '1';
+    V1.S12.S2 :=  1 ;
+    assert NOT(V1.S11    = '1' and 
+               V1.S12.S1 = '1' and 
+               V1.S12.S2 =  1 )
+      report "***PASSED TEST: c06s03b00x00p09n01i01009" 
+      severity NOTE;
+    assert    (V1.S11    = '1' and 
+               V1.S12.S1 = '1' and 
+               V1.S12.S2 =  1 )
+      report "***FAILED TEST: c06s03b00x00p09n01i01009 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01009arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1010.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1010.vhd
new file mode 100644
index 0000000..8d4b1fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1010.vhd
@@ -0,0 +1,252 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1010.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c06s03b00x00p10n01i01010pkg IS
+--
+--  This packages contains declarations of User attributes
+--
+-- ----------------------------------------------------------------------
+--
+  TYPE RESISTANCE IS RANGE 0 TO 1E9
+    UNITS
+      pf;
+      nf = 1000 pf;
+      mf = 1000 nf;
+    END UNITS;
+
+  TYPE t_logic IS (
+    U,  D,
+    Z0, Z1, ZDX, DZX, ZX,
+    W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
+    R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
+    F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
+    );
+--
+--          Scalar types Declarations
+--
+  SUBTYPE st_scl1 IS BOOLEAN;
+  SUBTYPE st_scl2 IS BIT;
+  SUBTYPE st_scl3 IS CHARACTER;
+  SUBTYPE st_scl4 IS INTEGER;
+  SUBTYPE st_scl5 IS REAL;
+  SUBTYPE st_scl6 IS TIME;
+  SUBTYPE st_scl7 IS RESISTANCE;
+  SUBTYPE st_scl8 IS t_logic;
+--
+--          character string types
+--
+  SUBTYPE st_str1 IS STRING;
+  SUBTYPE st_str2 IS STRING (1 TO 4);
+--
+--          Scalar types with a range constraint
+--
+  SUBTYPE cst_scl1 IS BOOLEAN    RANGE  TRUE   TO      TRUE;
+  SUBTYPE cst_scl2 IS BIT        RANGE   '0'   TO       '0';
+  SUBTYPE cst_scl3 IS CHARACTER  RANGE   'a'   TO       'z';
+  SUBTYPE cst_scl4 IS INTEGER    RANGE    10 DOWNTO       0;
+  SUBTYPE cst_scl5 IS REAL       RANGE   0.0   TO      10.0;
+  SUBTYPE cst_scl6 IS TIME       RANGE  0 fs   TO     10 ns;
+  SUBTYPE cst_scl7 IS RESISTANCE RANGE  0 pf   TO  10000 pf;
+  SUBTYPE cst_scl8 IS t_logic    RANGE    F0   TO        FX;
+  
+-- -----------------------------------------------------------------------------------------
+--      Attribute Declarations
+-- -----------------------------------------------------------------------------------------
+--
+  ATTRIBUTE atr_scl1 : st_scl1;
+  ATTRIBUTE atr_scl2 : st_scl2;
+  ATTRIBUTE atr_scl3 : st_scl3;
+  ATTRIBUTE atr_scl4 : st_scl4;
+  ATTRIBUTE atr_scl5 : st_scl5;
+  ATTRIBUTE atr_scl6 : st_scl6;
+  ATTRIBUTE atr_scl7 : st_scl7;
+  ATTRIBUTE atr_scl8 : st_scl8;
+  
+  ATTRIBUTE atr_str1 : st_str1;
+  ATTRIBUTE atr_str2 : st_str2;
+  
+  ATTRIBUTE cat_scl1 : cst_scl1;
+  ATTRIBUTE cat_scl2 : cst_scl2;
+  ATTRIBUTE cat_scl3 : cst_scl3;
+  ATTRIBUTE cat_scl4 : cst_scl4;
+  ATTRIBUTE cat_scl5 : cst_scl5;
+  ATTRIBUTE cat_scl6 : cst_scl6;
+  ATTRIBUTE cat_scl7 : cst_scl7;
+  ATTRIBUTE cat_scl8 : cst_scl8; 
+  
+END;
+
+
+
+USE WORK.c06s03b00x00p10n01i01010pkg.all;
+ENTITY c06s03b00x00p10n01i01010ent IS
+END c06s03b00x00p10n01i01010ent;
+
+USE WORK.c06s03b00x00p10n01i01010pkg.all;
+ENTITY c06s03b00x00p10n01i01010ent_a IS
+  GENERIC (  gene_1 : cst_scl7;
+             gene_2 : st_str2   );
+  PORT (  port_1 : cst_scl7;
+          port_2 : st_str2   );
+--
+  ATTRIBUTE atr_scl1 OF port_1: SIGNAL IS      TRUE;
+  ATTRIBUTE atr_scl2 OF port_1: SIGNAL IS       '0';
+  ATTRIBUTE atr_scl3 OF port_1: SIGNAL IS       'z';
+  ATTRIBUTE atr_scl4 OF port_1: SIGNAL IS         0;
+  ATTRIBUTE atr_scl5 OF port_1: SIGNAL IS      10.0;
+  ATTRIBUTE atr_scl6 OF port_1: SIGNAL IS     10 ns;
+  ATTRIBUTE atr_scl7 OF port_1: SIGNAL IS  10000 pf;
+  ATTRIBUTE atr_scl8 OF port_1: SIGNAL IS        FX;
+
+  ATTRIBUTE atr_str1 OF port_1: SIGNAL IS  "signal";
+  ATTRIBUTE atr_str2 OF port_1: SIGNAL IS    "XXXX";
+--
+  ATTRIBUTE cat_scl1 OF port_1: SIGNAL IS      TRUE;
+--
+  ATTRIBUTE atr_scl1 OF port_2: SIGNAL IS      TRUE;
+  ATTRIBUTE atr_str1 OF port_2: SIGNAL IS  "signal";
+  ATTRIBUTE atr_str2 OF port_2: SIGNAL IS    "XXXX";
+  ATTRIBUTE cat_scl1 OF port_2: SIGNAL IS      TRUE;
+--
+  ATTRIBUTE atr_scl1 OF gene_1: CONSTANT IS      TRUE;
+  ATTRIBUTE atr_str1 OF gene_1: CONSTANT IS  "signal";
+  ATTRIBUTE atr_str2 OF gene_1: CONSTANT IS    "XXXX";
+  ATTRIBUTE cat_scl1 OF gene_1: CONSTANT IS      TRUE;
+--
+  ATTRIBUTE atr_scl1 OF gene_2: CONSTANT IS      TRUE;
+  ATTRIBUTE atr_str1 OF gene_2: CONSTANT IS  "signal";
+  ATTRIBUTE atr_str2 OF gene_2: CONSTANT IS    "XXXX";
+  ATTRIBUTE cat_scl1 OF gene_2: CONSTANT IS      TRUE;
+  
+END c06s03b00x00p10n01i01010ent_a;
+
+-----------------------------------------------------------------------
+-- ARCHITECTURAL DECLARATION
+-----------------------------------------------------------------------
+
+ARCHITECTURE c06s03b00x00p10n01i01010arch_a OF c06s03b00x00p10n01i01010ent_a IS
+  SIGNAL sign_1 : cst_scl7;
+  SIGNAL sign_2 : st_str2;
+--
+  ATTRIBUTE atr_scl1 OF sign_1: SIGNAL IS      TRUE;
+  ATTRIBUTE atr_scl2 OF sign_1: SIGNAL IS       '0';
+  ATTRIBUTE atr_scl3 OF sign_1: SIGNAL IS       'z';
+  ATTRIBUTE atr_scl4 OF sign_1: SIGNAL IS         0;
+  ATTRIBUTE atr_scl5 OF sign_1: SIGNAL IS      10.0;
+  ATTRIBUTE atr_scl6 OF sign_1: SIGNAL IS     10 ns;
+  ATTRIBUTE atr_scl7 OF sign_1: SIGNAL IS  10000 pf;
+  ATTRIBUTE atr_scl8 OF sign_1: SIGNAL IS        FX;
+  
+  ATTRIBUTE atr_str1 OF sign_1: SIGNAL IS  "signal";
+  ATTRIBUTE atr_str2 OF sign_1: SIGNAL IS    "XXXX";
+--
+  ATTRIBUTE cat_scl1 OF sign_1: SIGNAL IS      TRUE;
+--
+  ATTRIBUTE atr_scl1 OF sign_2: SIGNAL IS      TRUE;
+  ATTRIBUTE atr_str1 OF sign_2: SIGNAL IS  "signal";
+  ATTRIBUTE atr_str2 OF sign_2: SIGNAL IS    "XXXX";
+  ATTRIBUTE cat_scl1 OF sign_2: SIGNAL IS      TRUE;
+--
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    port_1'atr_scl1 =      TRUE    and 
+                   port_1'atr_scl2 =       '0'    and 
+                   port_1'atr_scl3 =       'z'    and 
+                   port_1'atr_scl4 =         0    and 
+                   port_1'atr_scl5 =      10.0    and 
+                   port_1'atr_scl6 =     10 ns    and 
+                   port_1'atr_scl7 =  10000 pf    and 
+                   port_1'atr_scl8 =        FX    and 
+                   port_1'atr_str1 =  "signal"    and 
+                   port_1'atr_str2 =    "XXXX"    and 
+                   port_1'cat_scl1 =      TRUE    and 
+                   port_2'atr_scl1 =      TRUE    and 
+                   port_2'atr_str1 =  "signal"    and 
+                   port_2'atr_str2 =    "XXXX"    and 
+                   port_2'cat_scl1 =      TRUE    and 
+                   gene_1'atr_scl1 =      TRUE    and 
+                   gene_1'atr_str1 =  "signal"    and 
+                   gene_1'atr_str2 =    "XXXX"    and 
+                   gene_1'cat_scl1 =      TRUE    and 
+                   gene_2'atr_scl1 =      TRUE    and 
+                   gene_2'atr_str1 =  "signal"    and 
+                   gene_2'atr_str2 =    "XXXX"    and 
+                   gene_2'cat_scl1 =      TRUE )   
+      report "***PASSED TEST: c06s03b00x00p10n01i01010"
+      severity NOTE;
+    assert (    port_1'atr_scl1 =      TRUE    and 
+                port_1'atr_scl2 =       '0'    and 
+                port_1'atr_scl3 =       'z'    and 
+                port_1'atr_scl4 =         0    and 
+                port_1'atr_scl5 =      10.0    and 
+                port_1'atr_scl6 =     10 ns    and 
+                port_1'atr_scl7 =  10000 pf    and 
+                port_1'atr_scl8 =        FX    and 
+                port_1'atr_str1 =  "signal"    and 
+                port_1'atr_str2 =    "XXXX"    and 
+                port_1'cat_scl1 =      TRUE    and 
+                port_2'atr_scl1 =      TRUE    and 
+                port_2'atr_str1 =  "signal"    and 
+                port_2'atr_str2 =    "XXXX"    and 
+                port_2'cat_scl1 =      TRUE    and 
+                gene_1'atr_scl1 =      TRUE    and 
+                gene_1'atr_str1 =  "signal"    and 
+                gene_1'atr_str2 =    "XXXX"    and 
+                gene_1'cat_scl1 =      TRUE    and 
+                gene_2'atr_scl1 =      TRUE    and 
+                gene_2'atr_str1 =  "signal"    and 
+                gene_2'atr_str2 =    "XXXX"    and 
+                gene_2'cat_scl1 =      TRUE )   
+      report "***FAILED TEST: c06s03b00x00p10n01i01010 - An expanded name denotes an entity, the prefix denotes a construct that is ports, signals and generics." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01010arch_a;
+
+
+ARCHITECTURE c06s03b00x00p10n01i01010arch OF c06s03b00x00p10n01i01010ent IS
+  COMPONENT c06s03b00x00p10n01i01010ent_a
+    GENERIC (  gene_1 : cst_scl7;
+               gene_2 : st_str2   );
+    PORT (  port_1 : cst_scl7;
+            port_2 : st_str2   );
+  END COMPONENT;
+  FOR  SUB : c06s03b00x00p10n01i01010ent_a USE ENTITY work.c06s03b00x00p10n01i01010ent_a(c06s03b00x00p10n01i01010arch_a);
+
+  SIGNAL s1 : cst_scl7;
+  SIGNAL s2 : st_str2;
+
+BEGIN
+  SUB : c06s03b00x00p10n01i01010ent_a GENERIC MAP ( 10 pf, "ABCD" )
+    PORT MAP (    s1,    s2 ); 
+  
+END c06s03b00x00p10n01i01010arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1011.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1011.vhd
new file mode 100644
index 0000000..8aec15c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1011.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1011.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01011ent IS
+END c06s03b00x00p10n01i01011ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01011arch OF c06s03b00x00p10n01i01011ent IS
+  procedure check (x: in integer; y: in boolean; signal z :out integer) is
+  begin
+    z <= 5;
+  end;
+  signal p: integer ;
+  signal q: boolean ;
+  signal k: integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    check(c06s03b00x00p10n01i01011arch.p, c06s03b00x00p10n01i01011arch.q, k);
+    wait for 10 ns;
+    assert NOT(k=5)
+      report "***PASSED TEST: c06s03b00x00p10n01i01011"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s03b00x00p10n01i01011 - An expanded name with the prefix of an architecture name and the suffix of signal names declared in the architecture can be used in a statement (in this test, procedure call statement) within the architecture body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01011arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1012.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1012.vhd
new file mode 100644
index 0000000..7a864be
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1012.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1012.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01012ent IS
+  port (p,q: in bit);
+END c06s03b00x00p10n01i01012ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01012arch OF c06s03b00x00p10n01i01012ent IS
+
+BEGIN
+  TESTING: PROCESS(c06s03b00x00p10n01i01012ent.p, c06s03b00x00p10n01i01012ent.q)
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c06s03b00x00p10n01i01012"
+      severity NOTE;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01012arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1013.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1013.vhd
new file mode 100644
index 0000000..85f98a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1013.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1013.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01013ent IS
+END c06s03b00x00p10n01i01013ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01013arch OF c06s03b00x00p10n01i01013ent IS
+  signal q : bit;
+BEGIN
+  TESTING: PROCESS(c06s03b00x00p10n01i01013arch.q)
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c06s03b00x00p10n01i01013"
+      severity NOTE;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01013arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1019.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1019.vhd
new file mode 100644
index 0000000..e5290e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1019.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1019.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01019ent IS
+  port (p : in bit);
+END c06s03b00x00p10n01i01019ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01019arch OF c06s03b00x00p10n01i01019ent IS
+
+BEGIN
+  B1:Block
+    type chars is ('a', 'b', 'c', 'd', 'e');
+  begin
+    TESTING: PROCESS
+      variable c           : chars;
+      variable All_done    : boolean;
+    BEGIN
+      L1 : for LL1 in TRUE downto FALSE  loop
+        NULL; 
+        if L1.LL1 then       -- Selected prefix is loop,
+                                       -- suffix is identifier that
+                                                 -- refers to loop iteration id.
+          All_done := True;
+        end if;
+      end loop L1;
+      assert NOT(All_done=TRUE) 
+        report "***PASSED TEST: c06s03b00x00p10n01i01019"
+        severity NOTE;
+      assert (All_done=TRUE) 
+        report "***FAILED TEST: c06s03b00x00p10n01i01019 - Entity declaration does not occur in construct specifed by the prefix." 
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block B1;
+
+END c06s03b00x00p10n01i01019arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1020.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1020.vhd
new file mode 100644
index 0000000..7c0ea9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1020.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1020.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01020ent IS
+  port (p : in bit);
+END c06s03b00x00p10n01i01020ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01020arch OF c06s03b00x00p10n01i01020ent IS
+
+BEGIN
+  B1:Block
+    type chars is ('a', 'b', 'c', 'd', 'e');
+  begin
+    TESTING: PROCESS
+      variable c           : chars;
+      variable All_done    : boolean;
+    BEGIN
+      L1 : for LL1 in 0 to 5 loop
+        TESTING.c := 'a';
+      end loop L1;
+      assert NOT(TESTING.c='a')
+        report "***PASSED TEST: c06s03b00x00p10n01i01020" 
+        severity NOTE;
+      assert (TESTING.c='a')
+        report "***FAILED TEST: c06s03b00x00p10n01i01020 - Entity declaration does not occur in construct specifed by the prefix." 
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block B1;
+
+END c06s03b00x00p10n01i01020arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1024.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1024.vhd
new file mode 100644
index 0000000..d081d0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1024.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1024.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n02i01024ent IS
+END c06s03b00x00p10n02i01024ent;
+
+ARCHITECTURE c06s03b00x00p10n02i01024arch OF c06s03b00x00p10n02i01024ent IS
+  signal pop  : bit;
+  signal done : bit;
+BEGIN
+  TESTING: PROCESS
+    variable done : bit := '1';
+    variable pop  : bit;
+  BEGIN
+    pop            :=    done;
+    c06s03b00x00p10n02i01024arch.pop   <=   TESTING.done;
+    c06s03b00x00p10n02i01024arch.done   <=   TESTING.pop;
+    wait for 1 ns;
+    assert NOT(c06s03b00x00p10n02i01024arch.pop='1' and c06s03b00x00p10n02i01024arch.done='1') 
+      report "***PASSED TEST: c06s03b00x00p10n02i01024" 
+      severity NOTE;
+    assert (c06s03b00x00p10n02i01024arch.pop='1' and c06s03b00x00p10n02i01024arch.done='1') 
+      report "***FAILED TEST: c06s03b00x00p10n02i01024 - An expanded name denoting an entity declared within a named construct is allowed only within the construct." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n02i01024arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1026.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1026.vhd
new file mode 100644
index 0000000..fde63bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1026.vhd
@@ -0,0 +1,125 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1026.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p01n01i01026ent IS
+END c06s04b00x00p01n01i01026ent;
+
+ARCHITECTURE c06s04b00x00p01n01i01026arch OF c06s04b00x00p01n01i01026ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable E    : bit_vector (0 to 47);
+    variable F    : bit_vector (47 downto 0);
+    alias FF    : bit_vector (47 downto 0) is F;
+    variable G    : bit_vector (3 downto 0);
+    variable H    : bit_vector (0 to 3);
+  BEGIN
+
+    F    := x"555555555555";
+    E    := x"555555555555";
+    G    := b"1111";
+    G(1)    := '0';
+    H    := b"1111";
+    H(1)    := '0';
+
+    assert NOT(   ( F(47) = '0')   and
+                  ( F(42) = '1')   and
+                  ( F(37) = '0')   and
+                  ( F(32) = '1')   and
+                  ( F(27) = '0')   and
+                  ( F(22) = '1')   and
+                  ( F(17) = '0')   and
+                  ( F(12) = '1')   and
+                  ( F(7) = '0')   and
+                  ( F(2) = '1')   and
+                  ( FF(47) = '0')   and
+                  ( FF(42) = '1')   and
+                  ( FF(37) = '0')   and
+                  ( FF(32) = '1')   and
+                  ( FF(27) = '0')   and
+                  ( FF(22) = '1')   and
+                  ( FF(17) = '0')   and
+                  ( FF(12) = '1')   and
+                  ( FF(7) = '0')   and
+                  ( FF(2) = '1')   and
+                  ( E(47) = '1')   and
+                  ( E(42) = '0')   and
+                  ( E(37) = '1')   and
+                  ( E(32) = '0')   and
+                  ( E(27) = '1')   and
+                  ( E(22) = '0')   and
+                  ( E(17) = '1')   and
+                  ( E(12) = '0')   and
+                  ( E(7) = '1')   and
+                  ( E(2) = '0')   and
+                  ( E = F)   and 
+                  ( G = b"1101")   and
+                  ( H = b"1011")   )
+      report "***PASSED TEST: c06s04b00x00p01n01i01026"
+      severity NOTE;
+    assert (   ( F(47) = '0')   and
+               ( F(42) = '1')   and
+               ( F(37) = '0')   and
+               ( F(32) = '1')   and
+               ( F(27) = '0')   and
+               ( F(22) = '1')   and
+               ( F(17) = '0')   and
+               ( F(12) = '1')   and
+               ( F(7) = '0')   and
+               ( F(2) = '1')   and
+               ( FF(47) = '0')   and
+               ( FF(42) = '1')   and
+               ( FF(37) = '0')   and
+               ( FF(32) = '1')   and
+               ( FF(27) = '0')   and
+               ( FF(22) = '1')   and
+               ( FF(17) = '0')   and
+               ( FF(12) = '1')   and
+               ( FF(7) = '0')   and
+               ( FF(2) = '1')   and
+               ( E(47) = '1')   and
+               ( E(42) = '0')   and
+               ( E(37) = '1')   and
+               ( E(32) = '0')   and
+               ( E(27) = '1')   and
+               ( E(22) = '0')   and
+               ( E(17) = '1')   and
+               ( E(12) = '0')   and
+               ( E(7) = '1')   and
+               ( E(2) = '0')   and
+               ( E = F)   and 
+               ( G = b"1101")   and
+               ( H = b"1011")   )
+      report "***FAILED TEST: c06s04b00x00p01n01i01026 - Indexed reference test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p01n01i01026arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1027.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1027.vhd
new file mode 100644
index 0000000..e6c773d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1027.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1027.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p01n01i01027ent IS
+END c06s04b00x00p01n01i01027ent;
+
+ARCHITECTURE c06s04b00x00p01n01i01027arch OF c06s04b00x00p01n01i01027ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    V1    : BIT_VECTOR(1 to 2);
+    variable    V2    : BIT_VECTOR(3 to 4);
+    variable   pass   : integer := 0;
+  BEGIN
+    v1(1) := '1';
+    v1(2) := '0';
+    v2(3) := '0';
+    v2(4) := '1';
+
+    assert v1(1) = '1' report "v1(1) initial value is wrong.";
+    assert v1(2) = '0' report "v1(2) initial value is wrong.";
+    assert v2(3) = '0' report "v2(3) initial value is wrong.";
+    assert v2(4) = '1' report "v2(4) initial value is wrong.";
+    if (   V1(1) /= '1' or V1(2) /= '0' or
+           V2(3) /= '0' or V2(4) /= '1'   ) then   
+      pass := 1;
+    end if;
+    v1 := v2;         -- composite variable assignment
+    assert v1(1) = '0' report "v1(1) final value is wrong.";
+    assert v1(2) = '1' report "v1(2) final value is wrong.";
+    assert v2(3) = '0' report "v2(3) final value is wrong.";
+    assert v2(4) = '1' report "v2(4) final value is wrong.";
+    if (   V1(1) /= '0' or V1(2) /= '1' or
+           V2(3) /= '0' or V2(4) /= '1'   ) then   
+      pass := 1;
+    end if;
+    v1 := ('1', '1');      -- composite variable assignment
+    -- aggregate value
+    assert v1(1) = '1' report "v1(1) final value is wrong.";
+    assert v1(2) = '1' report "v1(2) final value is wrong.";
+    assert v2(3) = '0' report "v2(3) final value is wrong.";
+    assert v2(4) = '1' report "v2(4) final value is wrong.";
+    if (   V1(1) /= '1' or V1(2) /= '1' or
+           V2(3) /= '0' or V2(4) /= '1'   ) then   
+      pass := 1;
+    end if;
+    wait for 5 ns;
+    assert NOT(   pass = 0   )
+      report "***PASSED TEST: c06s04b00x00p01n01i01027"
+      severity NOTE;
+    assert (   pass = 0   )
+      report "***FAILED TEST: c06s04b00x00p01n01i01027 - Indexed reference test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p01n01i01027arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1028.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1028.vhd
new file mode 100644
index 0000000..46e6495
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1028.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1028.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01028ent IS
+  type THREE is range 1 to 3;
+  type A1 is array (THREE) of BOOLEAN;
+  type A2 is array (THREE, THREE) of BOOLEAN;
+  type A3 is array (THREE) of A1;
+  
+  type R1 is record
+               RE1: A1;
+             end record;
+  
+  type R2 is record
+               RE2: A2;
+             end record;
+  
+  type R3 is record
+               RE3: A3;
+             end record;
+END c06s04b00x00p02n01i01028ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01028arch OF c06s04b00x00p02n01i01028ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+    variable V1: R1 ; -- := (RE1=>(others=>TRUE));
+    variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));  
+    variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
+  BEGIN
+    V := V1.RE1(1);
+    assert NOT( V=false )
+      report "***PASSED TEST: c06s04b00x00p02n01i01028"
+      severity NOTE;
+    assert ( V=false )
+      report "***FAILED TEST: c06s04b00x00p02n01i01028 - The prefix of an indexed name can be a selected name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01028arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1029.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1029.vhd
new file mode 100644
index 0000000..ad3d710
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1029.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1029.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01029ent IS
+  type THREE is range 1 to 3;
+  type A1 is array (THREE) of BOOLEAN;
+  type A2 is array (THREE, THREE) of BOOLEAN;
+  type A3 is array (THREE) of A1;
+  
+  type R1 is record
+               RE1: A1;
+             end record;
+  
+  type R2 is record
+               RE2: A2;
+             end record;
+  
+  type R3 is record
+               RE3: A3;
+             end record;
+END c06s04b00x00p02n01i01029ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01029arch OF c06s04b00x00p02n01i01029ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+    variable V1: R1 ; -- := (RE1=>(others=>TRUE));
+    variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));  
+    variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
+  BEGIN
+    V := V2.RE2(2, 3);
+    assert NOT( V=false )
+      report "***PASSED TEST: c06s04b00x00p02n01i01029"
+      severity NOTE;
+    assert ( V=false )
+      report "***FAILED TEST: c06s04b00x00p02n01i01029 - The prefix of an indexed name can be a selected name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01029arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1030.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1030.vhd
new file mode 100644
index 0000000..d92909e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1030.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1030.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01030ent IS
+  type THREE is range 1 to 3;
+  type A1 is array (THREE) of BOOLEAN;
+  type A2 is array (THREE, THREE) of BOOLEAN;
+  type A3 is array (THREE) of A1;
+  
+  type R1 is record
+               RE1: A1;
+             end record;
+  
+  type R2 is record
+               RE2: A2;
+             end record;
+  
+  type R3 is record
+               RE3: A3;
+             end record;
+END c06s04b00x00p02n01i01030ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01030arch OF c06s04b00x00p02n01i01030ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+    variable V1: R1 ; -- := (RE1=>(others=>TRUE));
+    variable V2: R2 ; -- := (RE2=>(others=>(others=>TRUE)));  
+    variable V3: R3 ; -- := (RE3=>(others=>(others=>TRUE)));
+  BEGIN
+    V := V3.RE3(1)(3);
+    assert NOT( V=false )
+      report "***PASSED TEST: c06s04b00x00p02n01i01030"
+      severity NOTE;
+    assert ( V=false )
+      report "***FAILED TEST: c06s04b00x00p02n01i01030 - The prefix of an indexed name can be a selected name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01030arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1031.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1031.vhd
new file mode 100644
index 0000000..419aac9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1031.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1031.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01031ent IS
+END c06s04b00x00p02n01i01031ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01031arch OF c06s04b00x00p02n01i01031ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    TEN    is range 1 to 10;
+    type    ABASE1    is array (TEN range <>) of BOOLEAN;
+    subtype    A1    is ABASE1(TEN);
+    type    ABASE2    is array (TEN range <>) of A1;
+    subtype    A2    is ABASE2(TEN);
+    variable Sl_of_sl    : A2 ;
+    variable V2      : A2 ; -- := (others=>(others=>TRUE));
+  BEGIN
+    Sl_of_sl(1 to 8)(7)  := V2(2 to 9)(2);
+    assert NOT( Sl_of_sl(1 to 8)(7)=(false,false,false,false,false,false,false,false,false,false))
+      report "***PASSED TEST: c06s04b00x00p02n01i01031"
+      severity NOTE;
+    assert ( Sl_of_sl(1 to 8)(7)=(false,false,false,false,false,false,false,false,false,false))
+      report "***FAILED TEST: c06s04b00x00p02n01i01031 - The prefix of an indexed name can be a slice name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01031arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1032.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1032.vhd
new file mode 100644
index 0000000..b8f40e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1032.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1032.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01032ent IS
+END c06s04b00x00p02n01i01032ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01032arch OF c06s04b00x00p02n01i01032ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type TWO is range 1 to 2;
+    
+    type A0 is array (TWO) of BOOLEAN;
+    type A1 is array (TWO) of A0;
+    type A2 is array (TWO) of A1;
+    type A3 is array (TWO) of A2;
+    type A4 is array (TWO) of A3;
+    type A5 is array (TWO) of A4;
+    type A6 is array (TWO) of A5;
+    type A7 is array (TWO) of A6;
+    type A8 is array (TWO) of A7;
+    type A9 is array (TWO) of A8;
+    
+    variable V1: A9;
+  BEGIN
+    V1(1)(2)(1)(2)(1)(2)(1)(2)(1)(2) := TRUE; 
+    assert NOT(V1(1)(2)(1)(2)(1)(2)(1)(2)(1)(2) = TRUE) 
+      report "***PASSED TEST: c06s04b00x00p02n01i01032"
+      severity NOTE;
+    assert (V1(1)(2)(1)(2)(1)(2)(1)(2)(1)(2) = TRUE) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01032 - The prefix of an indexed name can be a indexed name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01032arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1033.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1033.vhd
new file mode 100644
index 0000000..d743054
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1033.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1033.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01033ent IS
+END c06s04b00x00p02n01i01033ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01033arch OF c06s04b00x00p02n01i01033ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    
+    type A1 is array (THREE) of BOOLEAN;
+    
+    function F1(i : integer) return A1 is
+      variable AR : A1;
+    begin
+      return AR;
+    end F1;
+    
+    variable A : integer;
+    variable V: BOOLEAN;
+    
+    variable BOOL    : boolean;
+  BEGIN
+    V  := F1(A)(1);     -- Indexed Name
+    assert NOT(V=false)
+      report "***PASSED TEST: c06s04b00x00p02n01i01033"
+      severity NOTE;
+    assert (V= false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01033 - The prefix of an indexed name can be a indexed name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01033arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1034.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1034.vhd
new file mode 100644
index 0000000..927ef8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1034.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1034.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01034ent IS
+END c06s04b00x00p02n01i01034ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01034arch OF c06s04b00x00p02n01i01034ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    
+    type A1 is array (THREE) of BOOLEAN;
+    type A2 is array (THREE, THREE) of BOOLEAN;
+    
+    function F2(i : integer) return A2 is
+      variable AR2 : A2;
+    begin
+      return AR2;
+    end F2;
+    
+    variable A : integer;
+    variable V: BOOLEAN;
+    
+  BEGIN
+    V  := F2(A)(2, 3);  -- Indexed Name
+    assert NOT(V=false)
+      report "***PASSED TEST: c06s04b00x00p02n01i01034"
+      severity NOTE;
+    assert (V= false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01034 - The prefix of an indexed name can be a indexed name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01034arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1035.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1035.vhd
new file mode 100644
index 0000000..b59f476
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1035.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1035.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01035ent IS
+END c06s04b00x00p02n01i01035ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01035arch OF c06s04b00x00p02n01i01035ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    
+    type A1 is array (THREE) of BOOLEAN;
+    type A2 is array (THREE, THREE) of BOOLEAN;
+    type A3 is array (THREE) of A1;
+    
+    function F3(i : integer) return A3 is
+      variable AR3 : A3;
+    begin
+      return AR3;
+    end F3;
+    variable A  : integer;
+    variable V  : BOOLEAN;
+    
+  BEGIN
+    V := F3(A)(1)(3);   -- Indexed Name
+    assert NOT(V=false)
+      report "***PASSED TEST: c06s04b00x00p02n01i01035"
+      severity NOTE;
+    assert (V= false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01035 - The prefix of an indexed name can be a indexed name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01035arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1037.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1037.vhd
new file mode 100644
index 0000000..22021af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1037.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1037.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s04b00x00p02n01i01037pkg is
+  type    THREE    is range 1 to 3;
+  type    A1    is array (THREE) of BOOLEAN;
+  function    Af1    (g : integer) return A1;
+end c06s04b00x00p02n01i01037pkg;
+
+package body c06s04b00x00p02n01i01037pkg is
+  function Af1 (g : integer) return A1 is
+    variable vaf1 : A1;
+  begin
+    return Vaf1;
+  end Af1;
+end c06s04b00x00p02n01i01037pkg;
+
+use work.c06s04b00x00p02n01i01037pkg.all;
+ENTITY c06s04b00x00p02n01i01037ent IS
+  generic (g : integer := 2);
+  port (PT: BOOLEAN) ;
+  attribute AT1 : A1;
+  attribute AT1 of PT : signal is Af1(g) ;
+END c06s04b00x00p02n01i01037ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01037arch OF c06s04b00x00p02n01i01037ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+  BEGIN
+    V := PT'AT1(1);
+    assert NOT(V=false) 
+      report "***PASSED TEST: c06s04b00x00p02n01i01037"
+      severity NOTE;
+    assert (V=false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01037 - Indexed name be an attribute name test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01037arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1038.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1038.vhd
new file mode 100644
index 0000000..1dda60f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1038.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1038.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s04b00x00p02n01i01038pkg is
+  type    THREE    is range 1 to 3;
+  type    A2    is array (THREE, THREE) of BOOLEAN;
+  function    Af2    (g : integer) return A2;
+end c06s04b00x00p02n01i01038pkg;
+
+package body c06s04b00x00p02n01i01038pkg is
+  function Af2 (g : integer) return A2 is
+    variable vaf1 : A2;
+  begin
+    return Vaf1;
+  end Af2;
+end c06s04b00x00p02n01i01038pkg;
+
+use work.c06s04b00x00p02n01i01038pkg.all;
+ENTITY c06s04b00x00p02n01i01038ent IS
+  generic (g : integer := 2);
+  port (PT: BOOLEAN) ;
+  attribute AT2 : A2;
+  attribute AT2 of PT : signal is Af2(g) ;
+END c06s04b00x00p02n01i01038ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01038arch OF c06s04b00x00p02n01i01038ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+  BEGIN
+    V := PT'AT2(2, 3);
+    assert NOT(V=false) 
+      report "***PASSED TEST: c06s04b00x00p02n01i01038" 
+      severity NOTE;
+    assert (V=false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01038 - Indexed name be an attribute name test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01038arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1039.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1039.vhd
new file mode 100644
index 0000000..3a73163
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1039.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1039.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s04b00x00p02n01i01039pkg is
+  type THREE is range 1 to 3;
+  type A1 is array (THREE) of BOOLEAN;
+  type A3 is array (THREE) of A1;
+  function Af3(g : integer) return A3;
+end c06s04b00x00p02n01i01039pkg;
+
+package body c06s04b00x00p02n01i01039pkg is
+  function Af3(g : integer) return A3 is
+    variable vaf1 : A3;
+  begin
+    return Vaf1;
+  end Af3;
+end c06s04b00x00p02n01i01039pkg;
+
+use work.c06s04b00x00p02n01i01039pkg.all;
+ENTITY c06s04b00x00p02n01i01039ent IS
+  generic (g : integer := 2);
+  port (PT: BOOLEAN) ;
+  attribute AT3 : A3;
+  attribute AT3 of PT : signal is Af3(g) ;
+END c06s04b00x00p02n01i01039ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01039arch OF c06s04b00x00p02n01i01039ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V: BOOLEAN;
+  BEGIN
+    V := PT'AT3(1)(3);
+    assert NOT(V=false) 
+      report "***PASSED TEST: c06s04b00x00p02n01i01039" 
+      severity NOTE;
+    assert (V=false) 
+      report "***FAILED TEST: c06s04b00x00p02n01i01039 - Indexed name be an attribute test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p02n01i01039arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1040.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1040.vhd
new file mode 100644
index 0000000..9d22685
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1040.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1040.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01040ent IS
+END c06s04b00x00p03n01i01040ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01040arch OF c06s04b00x00p03n01i01040ent IS
+  type A is array (1 to 10) of integer;
+  function foo (f:integer :=  3) return A is
+    variable v: A := (1,2,3,4,5,6,7,8,9,10);
+  begin
+    return v;
+  end foo;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := foo(3)(3);
+    assert NOT( k=3 )
+      report "***PASSED TEST: c06s04b00x00p03n01i01040"
+      severity NOTE;
+    assert ( k=3 )
+      report "***FAILED TEST: c06s04b00x00p03n01i01040 - The prefix of an indexed name must be appropriate for an array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01040arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1050.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1050.vhd
new file mode 100644
index 0000000..fe4b014
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1050.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1050.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01050ent IS
+END c06s04b00x00p03n02i01050ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01050arch OF c06s04b00x00p03n02i01050ent IS
+  type arrtype is array (positive range 1 to 10, bit range '0' to '1') of real;
+BEGIN
+  TESTING: PROCESS
+    variable k : arrtype ;
+  BEGIN
+    k(1,'0') := 1.2;
+    assert NOT(k(1,'0')=1.2)
+      report "***PASSED TEST: c06s04b00x00p03n02i01050"
+      severity NOTE;
+    assert (k(1,'0')=1.2)
+      report "***FAILED TEST: c06s04b00x00p03n02i01050 - The expressions specify the index values for the element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01050arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1067.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1067.vhd
new file mode 100644
index 0000000..616346f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1067.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1067.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n04i01067ent IS
+END c06s04b00x00p03n04i01067ent;
+
+ARCHITECTURE c06s04b00x00p03n04i01067arch OF c06s04b00x00p03n04i01067ent IS
+  type arrtype is array (positive range 1 to 10) of real;
+BEGIN
+  TESTING: PROCESS
+    variable k : arrtype;
+  BEGIN
+    k(1+2) := 1.2;
+    assert NOT( K(3)=1.2 )
+      report "***PASSED TEST: c06s04b00x00p03n04i01067"
+      severity NOTE;
+    assert ( K(3)=1.2 )
+      report "***FAILED TEST: c06s04b00x00p03n04i01067 - The index value belongs to the range of the corresponding index range of the array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n04i01067arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1069.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1069.vhd
new file mode 100644
index 0000000..d18a68a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1069.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1069.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01069ent IS
+  PORT ( ii: INOUT integer);
+  TYPE    A    IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE A6    IS A (1 TO 6);
+  SUBTYPE A8    IS A (1 TO 8);
+
+  FUNCTION func1 RETURN A6 IS
+  BEGIN
+    RETURN (1,2,3,4,5,6);
+  END;
+END c06s04b00x00p03n01i01069ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01069arch OF c06s04b00x00p03n01i01069ent IS
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+  BEGIN
+    q(1) := func1(1);
+    q(2) := func1(2);
+    q(3) := func1(3);
+    q(4) := func1(4);
+    q(5) := func1(5);
+    q(6) := func1(6);
+    q(7) := func1(3);
+    q(8) := func1(1);
+    WAIT FOR 1 ns;
+    assert NOT(q(1 TO 8) = (1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>3,8=>1)) 
+      report "***PASSED TEST: c06s04b00x00p03n01i01069" 
+      severity NOTE;
+    assert (q(1 TO 8) = (1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>3,8=>1)) 
+      report "***FAILED TEST: c06s04b00x00p03n01i01069 - Index on functin call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01069arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1070.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1070.vhd
new file mode 100644
index 0000000..09277be
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1070.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1070.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01070ent IS
+  PORT ( ii: INOUT integer);
+
+  TYPE    A  IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE    A6 IS A (1 TO 6);
+  SUBTYPE    A8 IS A (1 TO 8);
+
+  FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
+  BEGIN
+    IF (a=3) AND (b=3) THEN
+      RETURN (1,2,3,4,5,6);
+    ELSE
+      IF (a=3) THEN
+        RETURN (11,22,33,44,55,66);
+      ELSE
+        RETURN (111,222,333,444,555,666);
+      END IF;
+    END IF;
+  END;
+END c06s04b00x00p03n01i01070ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01070arch OF c06s04b00x00p03n01i01070ent IS
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+  BEGIN
+    q(1) := func1(3,3)(1);
+    q(2) := func1(0,3)(2);
+    q(3) := func1(3,0)(3);
+    q(4) := func1(0,3)(4);
+    q(5) := func1(3,3)(5);
+    q(6) := func1(3,0)(6);
+    q(7) := func1(3,3)(3);
+    q(8) := func1(0,3)(1);
+    WAIT FOR 1 ns;
+    assert NOT(q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
+      report "***PASSED TEST: c06s04b00x00p03n01i01070" 
+      severity NOTE;
+    assert (q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
+      report "***FAILED TEST: c06s04b00x00p03n01i01070 - Index on functin call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01070arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1071.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1071.vhd
new file mode 100644
index 0000000..9ffe396
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1071.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1071.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01071ent IS
+  PORT ( ii: INOUT integer);
+
+  TYPE    A  IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE    A6 IS A (1 TO 6);
+  SUBTYPE    A8 IS A (1 TO 8);
+
+  FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
+  BEGIN
+    IF (a=3) AND (b=3) THEN
+      RETURN (1,2,3,4,5,6);
+    ELSE
+      IF (a=3) THEN
+        RETURN (11,22,33,44,55,66);
+      ELSE
+        RETURN (111,222,333,444,555,666);
+      END IF;
+    END IF;
+  END;
+END c06s04b00x00p03n01i01071ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01071arch OF c06s04b00x00p03n01i01071ent IS
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+  BEGIN
+    q(1) := func1(1);
+    q(2) := func1(2);
+    q(3) := func1(3);
+    q(4) := func1(4);
+    q(5) := func1(5);
+    q(6) := func1(6);
+    q(7) := func1(3);
+    q(8) := func1(1);
+    WAIT FOR 1 ns;
+    assert NOT(q(1 TO 8) = (1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>3,8=>1))
+      report "***PASSED TEST: c06s04b00x00p03n01i01071"
+      severity NOTE;
+    assert (q(1 TO 8) = (1=>1,2=>2,3=>3,4=>4,5=>5,6=>6,7=>3,8=>1))
+      report "***FAILED TEST: c06s04b00x00p03n01i01071 - Index on functin call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01071arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1072.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1072.vhd
new file mode 100644
index 0000000..0dcffe6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1072.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1072.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01072ent IS
+  PORT ( ii: INOUT integer);
+
+  TYPE    A  IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE    A6 IS A (1 TO 6);
+  SUBTYPE    A8 IS A (1 TO 8);
+
+  FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
+  BEGIN
+    IF (a=3) AND (b=3) THEN
+      RETURN (1,2,3,4,5,6);
+    ELSE
+      IF (a=3) THEN
+        RETURN (11,22,33,44,55,66);
+      ELSE
+        RETURN (111,222,333,444,555,666);
+      END IF;
+    END IF;
+  END;
+END c06s04b00x00p03n01i01072ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01072arch OF c06s04b00x00p03n01i01072ent IS
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+  BEGIN
+    q(1) := func1(3)(1);
+    q(2) := func1(0)(2);
+    q(3) := func1(3)(3);
+    q(4) := func1(0)(4);
+    q(5) := func1(3)(5);
+    q(6) := func1(0)(6);
+    q(7) := func1(3)(3);
+    q(8) := func1(0)(1);
+    WAIT FOR 1 ns;
+    assert NOT(q(1 TO 8) = (1=>1,2=>222,3=>3,4=>444,5=>5,6=>666,7=>3,8=>111))
+      report "***PASSED TEST: c06s04b00x00p03n01i01072" 
+      severity NOTE;
+    assert (q(1 TO 8) = (1=>1,2=>222,3=>3,4=>444,5=>5,6=>666,7=>3,8=>111))
+      report "***FAILED TEST: c06s04b00x00p03n01i01072 - Index on functin call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01072arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1073.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1073.vhd
new file mode 100644
index 0000000..a8d4f9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1073.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1073.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01073ent IS
+  PORT ( ii: INOUT integer);
+  TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  TYPE Z IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>,NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE A8 IS A (1 TO 8);
+  SUBTYPE Z3 IS Z (1 TO 3,1 TO 3,1 TO 3);
+  SUBTYPE Z6 IS Z (1 TO 6,1 TO 6,1 TO 6);
+
+  FUNCTION func1 (a,b : INTEGER := 3) RETURN Z6 IS
+  BEGIN
+    IF (a=3) AND (b=3) THEN
+      RETURN (OTHERS=>(OTHERS=>(1,2,3,4,5,6)));
+    ELSE
+      IF (a=3) THEN
+        RETURN (OTHERS=>(OTHERS=>(11,22,33,44,55,66)));
+      ELSE
+        RETURN (OTHERS=>(OTHERS=>(111,222,333,444,555,666)));
+      END IF;
+    END IF;
+  END;
+END c06s04b00x00p03n01i01073ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01073arch OF c06s04b00x00p03n01i01073ent IS
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+  BEGIN
+    q(1) := func1(3,0)(1,1,1);
+    q(2) := func1(0,3)(2,2,2);
+    q(3) := func1(0,0)(3,3,3);
+    q(4) := func1(4,4,4); -- Indexed name - function params defaulted
+    q(5) := func1(5,5,5);
+    q(6) := func1(6,6,6);
+    q(7) := func1(3,3,3);
+    q(8) := func1(1,1,1);
+    WAIT FOR 1 ns;
+    assert NOT(q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
+      report "***PASSED TEST: c06s04b00x00p03n01i01073" 
+      severity NOTE;
+    assert (q(1 TO 8) = (1=>11,2=>222,3=>333,4=>4,5=>5,6=>6,7=>3,8=>1))
+      report "***FAILED TEST:c06s04b00x00p03n01i01073 - Index on functin call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01073arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1075.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1075.vhd
new file mode 100644
index 0000000..0dcdb5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1075.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1075.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01075ent IS
+END c06s04b00x00p03n02i01075ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01075arch OF c06s04b00x00p03n02i01075ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CSTRING is array (CHARACTER range <>) of CHARACTER;
+
+    constant C1 : CSTRING('A' to 'H') := "BCDEFGHA";
+    constant C2 : CSTRING('A' to 'H') := "CDEFGHAB";
+    constant C3 : CSTRING('A' to 'H') := "DEFGHABC";
+
+    variable V1 : CHARACTER;
+    variable V2 : CHARACTER;
+    variable V3 : CHARACTER;
+  BEGIN
+    V1 := C1('A');          --      A -> B
+    assert V1 = 'B';
+    V2 := C2(C1('A'));      --      A -> B -> D
+    assert V2 = 'D';
+    V3 := C3(C2(C1('A')));  --      A -> B -> H
+    assert V3 = 'G';
+    wait for 5 ns;
+    assert NOT( V1 = 'B' and V2 = 'D' and V3 = 'G' ) 
+      report "***PASSED TEST: c06s04b00x00p03n02i01075" 
+      severity NOTE;
+    assert ( V1 = 'B' and V2 = 'D' and V3 = 'G' ) 
+      report "***FAILED TEST: c06s04b00x00p03n02i01075 - The expresion for index name check test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01075arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1076.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1076.vhd
new file mode 100644
index 0000000..23acba6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1076.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1076.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n01i01076ent IS
+  subtype    line      is integer range 0 to 15;
+  subtype    cmd      is integer range 0 to 3;
+  type    d_lines   is array (line range <>) of bit;
+  subtype    data_line is d_lines(line);
+  subtype    cmd_line  is d_lines(cmd);
+END c06s05b00x00p01n01i01076ent;
+
+ARCHITECTURE c06s05b00x00p01n01i01076arch OF c06s05b00x00p01n01i01076ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable d1    : data_line := (0 to 3 => '1', others => '0');
+    variable instr    : cmd_line;
+  BEGIN
+    --
+    -- Test assigning a slice to a full array
+    --
+    instr := d1(0 to 3);
+    for i in 0 to 3 loop
+      assert instr(i) = '1'
+        report "Slice to full array assignment failed."
+        severity note ;
+    end loop;
+
+    --
+    -- Now try a full array to a slice
+    --
+    d1(8 to 11) := instr;
+    for i in 8 to 11 loop
+      assert d1(i) = '1'
+        report "Full array to slice assignment failed."
+        severity note ;
+    end loop;
+
+    --
+    -- Now try assigning a slice to a slice
+    --
+    d1(8 to 11) := d1(4 to 7);
+    for i in 4 to 15 loop
+      assert d1(i) = '0'
+        report "Slice to slice assignment failed."
+        severity note ;
+    end loop;
+
+    assert NOT( instr = "1111" and d1 = "1111000000000000" )
+      report "***PASSED TEST: c06s05b00x00p01n01i01076"
+      severity NOTE;
+    assert ( instr = "1111" and d1 = "1111000000000000" )
+      report "***FAILED TEST: c06s05b00x00p01n01i01076 - A slice name denotes a one-dimensional array composed of a sequence of consecutive elements of another one-dimensional array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n01i01076arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1077.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1077.vhd
new file mode 100644
index 0000000..a541143
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1077.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1077.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n01i01077ent IS
+END c06s05b00x00p01n01i01077ent;
+
+ARCHITECTURE c06s05b00x00p01n01i01077arch OF c06s05b00x00p01n01i01077ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A    : bit_vector (1 to 32);
+    constant AA    : bit_vector (1 to 32) := x"0000ffff";
+    variable B    : bit_vector (32 downto 1);
+    variable C    : bit_vector (15 downto 0);
+    variable D, DD    : bit_vector (0 to 15);
+    variable E    : bit_vector (0 to 47);
+    variable F    : bit_vector (47 downto 0);
+    alias FF    : bit_vector (47 downto 0) is F;
+    alias FH    : bit_vector (0 to 31) is F (47 downto 16);
+  BEGIN
+    A := x"0000ffff";
+    B := x"00ff00ff";
+    C := x"00ff";
+    D := x"0f0f";
+    E := x"000000ffffff";
+    FF := x"000fff000fff";
+    assert NOT(   ( A(1 to 32) = x"0000ffff")   and
+                  ( A(1 to 20) = x"0000f")   and
+                  ( A(9 to 32) = x"00ffff")   and
+                  ( A(9 to 28) = x"00fff")   and
+                  ( C(15 downto 0) = x"00ff")   and
+                  ( C(11 downto 0) = x"0ff")   and
+                  ( C(15 downto 4) = x"00f")   and
+                  ( C(11 downto 4) = x"0f")   and
+                  ( F(47 downto 0) = x"000fff000fff")   and
+                  ( F(39 downto 0) = x"0fff000fff")   and
+                  ( F(47 downto 8) = x"000fff000f")   and
+                  ( F(39 downto 8) = x"0fff000f")   and
+                  ( F(47 downto 36) = x"000")   and
+                  ( F(11 downto 0) = x"fff")   and
+                  ( F(35 downto 20) = x"fff0")   and
+                  ( FF(47 downto 0) = x"000fff000fff")   and
+                  ( FF(39 downto 0) = x"0fff000fff")   and
+                  ( FF(47 downto 8) = x"000fff000f")   and
+                  ( FF(39 downto 8) = x"0fff000f")   and
+                  ( FF(47 downto 36) = x"000")   and
+                  ( FF(11 downto 0) = x"fff")   and
+                  ( FF(35 downto 20) = x"fff0")   and
+                  ( FH(0 to 31) = x"000fff00")   and
+                  ( FH(8 to 31) = x"0fff00")   and
+                  ( FH(0 to 11) = x"000")      and
+                  ( FH(12 to 27) = x"fff0")   ) 
+      report "***PASSED TEST: c06s05b00x00p01n01i01077"
+      severity NOTE;
+    assert (   ( A(1 to 32) = x"0000ffff")   and
+               ( A(1 to 20) = x"0000f")   and
+               ( A(9 to 32) = x"00ffff")   and
+               ( A(9 to 28) = x"00fff")   and
+               ( C(15 downto 0) = x"00ff")   and
+               ( C(11 downto 0) = x"0ff")   and
+               ( C(15 downto 4) = x"00f")   and
+               ( C(11 downto 4) = x"0f")   and
+               ( F(47 downto 0) = x"000fff000fff")   and
+               ( F(39 downto 0) = x"0fff000fff")   and
+               ( F(47 downto 8) = x"000fff000f")   and
+               ( F(39 downto 8) = x"0fff000f")   and
+               ( F(47 downto 36) = x"000")   and
+               ( F(11 downto 0) = x"fff")   and
+               ( F(35 downto 20) = x"fff0")   and
+               ( FF(47 downto 0) = x"000fff000fff")   and
+               ( FF(39 downto 0) = x"0fff000fff")   and
+               ( FF(47 downto 8) = x"000fff000f")   and
+               ( FF(39 downto 8) = x"0fff000f")   and
+               ( FF(47 downto 36) = x"000")   and
+               ( FF(11 downto 0) = x"fff")   and
+               ( FF(35 downto 20) = x"fff0")   and
+               ( FH(0 to 31) = x"000fff00")   and
+               ( FH(8 to 31) = x"0fff00")   and
+               ( FH(0 to 11) = x"000")      and
+               ( FH(12 to 27) = x"fff0")   ) 
+      report "***FAILED TEST: c06s05b00x00p01n01i01077 - A slice name denotes a one-dimensional array composed of a sequence of consecutive elements of another one-dimensional array test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n01i01077arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1078.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1078.vhd
new file mode 100644
index 0000000..37b345a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1078.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1078.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n02i01078ent IS
+END c06s05b00x00p01n02i01078ent;
+
+ARCHITECTURE c06s05b00x00p01n02i01078arch OF c06s05b00x00p01n02i01078ent IS
+  SUBTYPE    bit_vector_4 is bit_vector ( 0 to 3 );
+  SUBTYPE    bit_vector_8 is bit_vector ( 0 to 7 );
+
+  SIGNAL    resultt : boolean;
+
+  procedure subprogram ( VARIABLE v : IN bit_vector_4; signal result : out boolean ) is
+  begin
+    if ( v = B"1010" ) then
+      result <= true;
+    else
+      result <= false;
+    end if;
+  end ;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE  v_slice : bit_vector_8 := B"1010_1100";
+  BEGIN
+    subprogram ( v_slice ( 0 to 3 ), resultt );
+    wait for 1 ns;
+    assert NOT( resultt = true )
+      report "***PASSED TEST: c06s05b00x00p01n02i01078"
+      severity NOTE;
+    assert ( resultt = true )
+      report "***FAILED TEST: c06s05b00x00p01n02i01078 - A slice of a variable should still be a variable."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n02i01078arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1079.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1079.vhd
new file mode 100644
index 0000000..626adde
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1079.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1079.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n02i01079ent IS
+END c06s05b00x00p01n02i01079ent;
+
+ARCHITECTURE c06s05b00x00p01n02i01079arch OF c06s05b00x00p01n02i01079ent IS
+  SUBTYPE    bit_vector_4 is bit_vector ( 0 to 3 );
+  SUBTYPE    bit_vector_8 is bit_vector ( 0 to 7 );
+
+  SIGNAL    v_slice : bit_vector_8 := B"1010_1100";   
+
+  procedure subprogram ( signal v : out bit_vector_4 ) is
+  begin
+    v <= B"0101" after 10 ns;
+  end ;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    subprogram ( v_slice ( 0 to 3 ) );
+    wait for 11 ns;
+    assert NOT(v_slice = B"0101_1100") 
+      report "***PASSED TEST: c06s05b00x00p01n02i01079"
+      severity NOTE;
+    assert (v_slice = B"0101_1100") 
+      report "***FAILED TEST: c06s05b00x00p01n02i01079 - A slice of a signal should still be a signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n02i01079arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1080.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1080.vhd
new file mode 100644
index 0000000..d69ddda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1080.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1080.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n02i01080ent IS
+END c06s05b00x00p01n02i01080ent;
+
+ARCHITECTURE c06s05b00x00p01n02i01080arch OF c06s05b00x00p01n02i01080ent IS
+  SUBTYPE    bit_vector_4 is bit_vector ( 0 to 3 );
+  SUBTYPE    bit_vector_8 is bit_vector ( 0 to 7 );
+  SIGNAL   result  : boolean;
+
+  CONSTANT    v_slice : bit_vector_8 := B"1010_1100";   
+
+  procedure subprogram ( constant v : in bit_vector_4; signal resultt : out boolean ) is
+  begin
+    if (v = "1010") then
+      resultt <= true;
+    else
+      resultt <= false;
+    end if;
+  end ;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    subprogram ( v_slice ( 0 to 3 ), result );
+    wait for 11 ns;
+    assert NOT(result = true)
+      report "***PASSED TEST: c06s05b00x00p01n02i01080"
+      severity NOTE;
+    assert (result = true)
+      report "***FAILED TEST: c06s05b00x00p01n02i01080 - A slice of a constant should still be a constant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n02i01080arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1081.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1081.vhd
new file mode 100644
index 0000000..569b7e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1081.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1081.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p01n02i01081ent IS
+END c06s05b00x00p01n02i01081ent;
+
+ARCHITECTURE c06s05b00x00p01n02i01081arch OF c06s05b00x00p01n02i01081ent IS
+  SUBTYPE    bit_vector_4 is bit_vector ( 0 to 3 );
+  SUBTYPE    bit_vector_8 is bit_vector ( 0 to 7 );
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE var : bit_vector_8 := B"1110_0010";
+    VARIABLE v1  : bit_vector_4 := B"0011";
+    VARIABLE v2  : bit_vector_4 := B"1111";
+  BEGIN
+    var (0 to 3) := v1;
+    var (4 to 7) := v2;
+    assert NOT( var = B"0011_1111" )
+      report "***PASSED TEST: c06s05b00x00p01n02i01081"
+      severity NOTE;
+    assert ( var = B"0011_1111" )
+      report "***FAILED TEST: c06s05b00x00p01n02i01081 - Slices of a variable may be the target of a variable assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p01n02i01081arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1086.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1086.vhd
new file mode 100644
index 0000000..3dff0d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1086.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1086.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01086ent IS
+END c06s05b00x00p02n01i01086ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01086arch OF c06s05b00x00p02n01i01086ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable str : string (1 to 25) := "This is array slice check";
+    variable k   : integer;
+  BEGIN
+    if str(1 to 3) = "Thi" then -- Success_here
+      k := 5;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c06s05b00x00p02n01i01086" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c06s05b00x00p02n01i01086 - Slice name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01086arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1087.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1087.vhd
new file mode 100644
index 0000000..d3bbfb9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1087.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1087.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01087ent IS
+END c06s05b00x00p02n01i01087ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01087arch OF c06s05b00x00p02n01i01087ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    FIVE    is range 1 to 5;
+    type    ABASE1    is array (FIVE range <>) of BOOLEAN;
+    subtype    A1    is ABASE1(FIVE);
+    type    ABASE2    is array (FIVE range <>) of A1;
+    subtype    A2    is ABASE2(FIVE);
+    variable    V1   : A1;
+    variable    V2   : A2 ; -- := (others=>(others=>TRUE));
+  BEGIN
+    V1(2 to 4) := V2(3)(2 to 4);
+    assert NOT(V1(2 to 4) = (false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p02n01i01087" 
+      severity NOTE;
+    assert (V1(2 to 4) = (false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p02n01i01087 - Indexed name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01087arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1088.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1088.vhd
new file mode 100644
index 0000000..e8ed114
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1088.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1088.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01088ent IS
+END c06s05b00x00p02n01i01088ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01088arch OF c06s05b00x00p02n01i01088ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE is range 1 to 5;
+    type ABASE is array (FIVE range <>) of BOOLEAN;
+    subtype A1 is ABASE(FIVE);
+    type R1 is record
+                 RE1: A1;
+               end record;
+    variable V1: A1;
+    variable V2: R1 ; -- := (RE1=>(others=>TRUE));
+  BEGIN
+    V1(2 to 4) := V2.RE1(2 to 4);
+    assert NOT(V1(2 to 4) = (false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p02n01i01088" 
+      severity NOTE;
+    assert (V1(2 to 4) = (false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p02n01i01088 - Selected name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01088arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1089.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1089.vhd
new file mode 100644
index 0000000..72808a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1089.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1089.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01089ent IS
+END c06s05b00x00p02n01i01089ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01089arch OF c06s05b00x00p02n01i01089ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE is range 1 to 5;
+    type ABASE is array (FIVE range <>) of BOOLEAN;
+    subtype A1 is ABASE(FIVE);
+    type R1 is record
+                 RE1: A1;
+               end record;
+    type R2 is record
+                 RE2: R1;
+               end record;
+    variable V1: A1;
+    variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE)));
+  BEGIN
+    V1(2 to 4) := V3.RE2.RE1(2 to 4);
+    assert NOT(V1(2 to 4) = (false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p02n01i01089" 
+      severity NOTE;
+    assert (V1(2 to 4) = (false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p02n01i01089 - Selected name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01089arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1090.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1090.vhd
new file mode 100644
index 0000000..b06ad7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1090.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1090.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01090ent IS
+END c06s05b00x00p02n01i01090ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01090arch OF c06s05b00x00p02n01i01090ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    I1    is range 0 to 11;
+    type    ABASE is array (I1 range <>) of BOOLEAN;
+    subtype    A1    is ABASE(I1);
+    variable    V1    : A1 ; -- := A1'(others=>TRUE);
+  BEGIN
+    V1(5 to 6) :=  V1(1 to 10)(2 to 9)(3 to 8)(4 to 7)(5 to 6);
+    assert NOT(V1(5 to 6)=(false,false))
+      report "***PASSED TEST: c06s05b00x00p02n01i01090" 
+      severity NOTE;
+    assert (V1(5 to 6)=(false,false))
+      report "***FAILED TEST: c06s05b00x00p02n01i01090 - Slice name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01090arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1091.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1091.vhd
new file mode 100644
index 0000000..c660335
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1091.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1091.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s05b00x00p02n01i01091pkg is
+  type FIVE    is range 1 to 5;
+  type ABASE    is array (FIVE range <>) of BOOLEAN;
+  subtype A1    is ABASE(FIVE);
+  attribute    AT1 : A1;
+  function    fat1(i:integer) return a1;
+end c06s05b00x00p02n01i01091pkg;
+
+package body c06s05b00x00p02n01i01091pkg is
+  function fat1(i:integer) return a1 is
+    variable va1 : a1;
+  begin
+    return Va1;
+  end fat1;
+end c06s05b00x00p02n01i01091pkg;
+
+use work.c06s05b00x00p02n01i01091pkg.all;
+ENTITY c06s05b00x00p02n01i01091ent IS
+  port (PT: BOOLEAN) ;
+
+  attribute AT1 of PT : signal is fat1(8);
+END c06s05b00x00p02n01i01091ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01091arch OF c06s05b00x00p02n01i01091ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : A1;
+  BEGIN
+    V1(2 to 4) := PT'AT1(2 to 4);
+    assert NOT(V1(2 to 4)=(false,false,false))
+      report "***PASSED TEST: c06s05b00x00p02n01i01091"
+      severity NOTE;
+    assert (V1(2 to 4)=(false,false,false))
+      report "***FAILED TEST: c06s05b00x00p02n01i01091 - Slice name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01091arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1092.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1092.vhd
new file mode 100644
index 0000000..e5d9a7b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1092.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1092.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01092ent IS
+END c06s05b00x00p03n01i01092ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01092arch OF c06s05b00x00p03n01i01092ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable str : string(1 to 25) := "This is array slice check";
+    variable k   : integer;
+  BEGIN
+    if str(1 to 3) = "Thi" then
+      k := 5;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c06s05b00x00p03n01i01092"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s05b00x00p03n01i01092 - The prefix of a slice must be appropriate for a one-dimensional array object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01092arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc110.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc110.vhd
new file mode 100644
index 0000000..01a900b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc110.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc110.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00110ent IS
+  port (S1 : out BIT_VECTOR(0 to 3) := "1011");
+END c04s03b02x00p29n06i00110ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00110arch OF c04s03b02x00p29n06i00110ent IS
+  signal S2,S3 : BIT;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if (S1'LOW = 0) then
+      S2 <= '1' after 10 ns;
+    end if;
+
+    if (S1'HIGH = 3) then
+      S3 <= '1' after 10 ns;
+    end if;
+    wait for 20 ns;
+    
+    assert NOT(S2='1' and S3='1') 
+      report "***PASSED TEST: c04s03b02x00p29n06i00110" 
+      severity NOTE;
+    assert (S2='1' and S3='1') 
+      report "***FAILED TEST: c04s03b02x00p29n06i00110 - Reading of the attributes LOW and HIGH of the interface element of mode out is allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00110arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1103.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1103.vhd
new file mode 100644
index 0000000..332f1c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1103.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1103.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01103ent IS
+END c06s05b00x00p03n01i01103ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01103arch OF c06s05b00x00p03n01i01103ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE    is range 1 to 5;
+    type ABASE    is array (FIVE range <>) of BOOLEAN;
+    subtype A1    is ABASE(FIVE);
+    type R1 is record
+                 RE1: A1;
+               end record;
+    type R2 is record
+                 RE2: R1;
+               end record;
+    variable V1: A1;
+    variable V2: R1 ; -- := (RE1=>(others=>TRUE));
+    variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE)));
+  BEGIN
+    V1(2 to 4) := V2.RE1(2 to 4);  -- No_failure_here
+    assert NOT(V1(2 to 4)=(false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p03n01i01103" 
+      severity NOTE;
+    assert (V1(2 to 4)=(false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p03n01i01103 - Prefix of a slice can be a selected name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01103arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1104.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1104.vhd
new file mode 100644
index 0000000..59d5cbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1104.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1104.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01104ent IS
+END c06s05b00x00p03n01i01104ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01104arch OF c06s05b00x00p03n01i01104ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE    is range 1 to 5;
+    type ABASE    is array (FIVE range <>) of BOOLEAN;
+    subtype A1    is ABASE(FIVE);
+    type R1 is record
+                 RE1: A1;
+               end record;
+    type R2 is record
+                 RE2: R1;
+               end record;
+    variable V1: A1;
+    variable V2: R1 ; -- := (RE1=>(others=>TRUE));
+    variable V3: R2 ; -- := (RE2=>(RE1=>(others=>TRUE)));
+  BEGIN
+    V1(2 to 4) := V3.RE2.RE1(2 to 4);  -- No_failure_here
+    assert NOT(V1(2 to 4)=(false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p03n01i01104" 
+      severity NOTE;
+    assert (V1(2 to 4)=(false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p03n01i01104 - Prefix of a slice can be a selected name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01104arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc111.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc111.vhd
new file mode 100644
index 0000000..9f4c28f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc111.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc111.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00111ent IS
+END c04s03b02x00p29n06i00111ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00111arch OF c04s03b02x00p29n06i00111ent IS
+  PROCEDURE p1 ( prm_out : OUT INTEGER ) IS
+    ATTRIBUTE attr1 : INTEGER;
+    ATTRIBUTE attr1 OF prm_out : VARIABLE IS 300;
+  BEGIN
+    ASSERT prm_out'attr1 = 300 REPORT "ERROR: Bad value for prm_out'attr1" SEVERITY FAILURE;
+    assert NOT(prm_out'attr1 = 300)
+      report "***PASSED TEST: c04s03b02x00p29n06i00111"
+      severity NOTE;
+    assert (prm_out'attr1 = 300)
+      report "***FAILED TEST: c04s03b02x00p29n06i00111 - Reading of the attributes of the interface element of mode out in a subprogram testing failed." 
+      severity ERROR;
+  END;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE tmp : INTEGER;
+  BEGIN
+--
+    p1 ( tmp );
+--   
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00111arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1117.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1117.vhd
new file mode 100644
index 0000000..e9963b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1117.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1117.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01117ent IS
+END c06s05b00x00p03n01i01117ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01117arch OF c06s05b00x00p03n01i01117ent IS
+
+  subtype FIVE    is INTEGER range 1 to 5;
+  type    ABASE    is array (FIVE range <>) of BOOLEAN;
+  subtype A1    is ABASE (FIVE);
+  function F (i: integer) return A1 is
+    variable ARR : A1;
+  begin
+    return ARR;
+  end F;
+
+BEGIN
+  TESTING: PROCESS
+    variable V1    : A1;
+  BEGIN
+    V1(2 to 4) := F(5)(2 to 4);
+    assert NOT(V1(2 to 4) = (false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p03n01i01117"
+      severity NOTE;
+    assert (V1(2 to 4) = (false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p03n01i01117 - Prefix of a slice number must be a one-dimensional array type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01117arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1119.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1119.vhd
new file mode 100644
index 0000000..f263a26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1119.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1119.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01119ent IS
+  subtype    idx     is integer range 1 to 10;
+  type    aray1    is array (idx) of bit;
+  type    aray2    is array (idx range <>) of aray1;
+END c06s05b00x00p03n01i01119ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01119arch OF c06s05b00x00p03n01i01119ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable v1   : aray1;
+    variable v2   : aray1;
+    variable v5    : aray1;
+    variable v3     : aray2(1 to 2);
+    variable v4     : aray2(1 to 3);
+  BEGIN
+    --
+    -- Try slices consisting of indexed names
+    --
+    v1 := "1111111111";
+    v1 := v3(1)(idx);                -- slice is a whole array
+    assert not (v2 = v1)
+      report "Slice of an indexed name as a value passed."
+      severity note;
+    
+    v5 := "1111111111";
+    v4(2)(idx) := v5;                -- slice is a whole array
+    assert not(v4(2) = v5)
+      report "Slice of an indexed name as a target passed."
+      severity note;
+    
+    v2(1) := v3(1)(1 to 1)(1);               -- a one element slice
+    assert not (v3(1)(1) = v2(1))
+      report "One element slice of an indexed name as a value passed." 
+      severity note;
+    
+    v3(1)(1 to 1)(1) := v1(1);               -- a one element slice
+    assert not (v3(1)(1) = v1(1))
+      report "One element slice of an indexed name as a target passed."
+      severity note;
+
+    assert NOT(   v1       = "0000000000"   and
+                  v4(2)       = "1111111111"   and
+                  v2(1)      = '0'      and
+                  v3(1)(1)   = '0') 
+      report "***PASSED TEST: c06s05b00x00p03n01i01119" 
+      severity NOTE;
+    assert (   v1       = "0000000000"   and
+               v4(2)       = "1111111111"   and
+               v2(1)      = '0'      and
+               v3(1)(1)   = '0') 
+      report "***FAILED TEST: c06s05b00x00p03n01i01119 - The prefix of a slice may be an indexed name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01119arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1121.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1121.vhd
new file mode 100644
index 0000000..16ee4cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1121.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1121.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n02i01121ent IS
+END c06s05b00x00p03n02i01121ent;
+
+ARCHITECTURE c06s05b00x00p03n02i01121arch OF c06s05b00x00p03n02i01121ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     ENUM1  is (M1, M2, M3, M4, M5, M6);
+    type     A1     is array (ENUM1 range <>) of BOOLEAN;
+    subtype  A11    is A1 (M1 to M3);
+    subtype  A12    is A1 (M4 to M6);
+    variable V1     : A1 (M1 to M6) ;
+    variable V11    : A11;
+    variable V12    : A12;
+    variable k      : integer;
+  BEGIN
+    if (
+      (V11 = V12)
+      and (V11(M2 to M3) = V12(M4 to M5))
+      and (V1 (M1 to M3) = V11(M1 to M3))
+      and (V1 (M2 to M3) = V12(M4 to M5))
+      ) then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s05b00x00p03n02i01121"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s05b00x00p03n02i01121 - The type of the slice is the same as the base type of the one-dimensional array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n02i01121arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1122.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1122.vhd
new file mode 100644
index 0000000..e901ab6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1122.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1122.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n02i01122ent IS
+END c06s05b00x00p03n02i01122ent;
+
+ARCHITECTURE c06s05b00x00p03n02i01122arch OF c06s05b00x00p03n02i01122ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5, M6);
+    type A1    is array (ENUM1 range <>) of BOOLEAN;
+    subtype A11 is A1 (M1 to M3);
+    subtype A12 is A1 (M4 to M6);
+    variable V1 : A1  (M1 to M6) ;
+    variable V11: A11;
+    variable V12: A12;
+    variable k : integer := 0;
+  BEGIN
+    if (
+      (V11 = V12)
+      and (V11(M2 to M3) = V12(M4 to M5))
+      and (V1 (M1 to M3) = V11(M1 to M3))
+      and (V1 (M2 to M3) = V12(M4 to M5))
+      ) then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s05b00x00p03n02i01122"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s05b00x00p03n02i01122 - The type of the slice is the same as the base type of the one-dimensional array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n02i01122arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1123.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1123.vhd
new file mode 100644
index 0000000..6a5171f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1123.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1123.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n02i01123ent IS
+END c06s05b00x00p03n02i01123ent;
+
+ARCHITECTURE c06s05b00x00p03n02i01123arch OF c06s05b00x00p03n02i01123ent IS
+  TYPE       colors       is ( red, green, blue, yellow, orange, black );
+  TYPE       ncolor_array    is array ( NATURAL range <> ) of colors;
+  SUBTYPE       ncolor_4    is ncolor_array ( 0 to 3 );
+  TYPE       pcolor_array    is array ( POSITIVE range <> ) of colors;
+  SUBTYPE       pcolor_4    is ncolor_array ( 1 to 4 );
+BEGIN
+  TESTING: PROCESS
+    variable vn : ncolor_4 := ( red, red, green, black );
+    variable vp : pcolor_4 := ( blue, yellow, yellow, orange );
+  BEGIN
+    vn(1 to 3) := vp(2 to 4);
+    assert NOT( vn = ( red, yellow, yellow, orange ) ) 
+      report "***PASSED TEST: c06s05b00x00p03n02i01123"
+      severity NOTE;
+    assert ( vn = ( red, yellow, yellow, orange ) ) 
+      report "***FAILED TEST: c06s05b00x00p03n02i01123 - The base type of the array type is the type of the slice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n02i01123arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1126.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1126.vhd
new file mode 100644
index 0000000..cac6262
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1126.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1126.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01126ent IS
+END c06s05b00x00p04n01i01126ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01126arch OF c06s05b00x00p04n01i01126ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    FIVE1 is range 1 to 5;
+    type    FIVE2 is range 1 to 5;
+    type    A3B   is array (FIVE1 range <>) of BOOLEAN;
+    subtype    A3    is A3B   (FIVE1);
+    type    A4B   is array (FIVE2 range <>) of A3;
+    subtype    A4    is A4B   (FIVE2);
+
+    variable    V4: A4 ;
+  BEGIN
+    V4(3)(1 to 5) := V4(4)(FIVE1);   -- legal assignments.
+    assert NOT(V4(3)(1 to 5) = (false,false,false,false,false)) 
+      report "***PASSED TEST: c06s05b00x00p04n01i01126" 
+      severity NOTE;
+    assert (V4(3)(1 to 5) = (false,false,false,false,false)) 
+      report "***FAILED TEST: c06s05b00x00p04n01i01126 - Bounds of the discrete range must be the type of the index of the array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01126arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc113.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc113.vhd
new file mode 100644
index 0000000..58688f7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc113.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc113.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c04s03b02x00p29n10i00113pkg is
+  type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER;
+  type V_REGISTER    is array (INTEGER range 0 to 7) of BIT;
+end c04s03b02x00p29n10i00113pkg;
+
+use work.c04s03b02x00p29n10i00113pkg.all;
+ENTITY c04s03b02x00p29n10i00113ent IS
+  port (
+    p23 : inout Boolean        := FALSE;
+    p24 : inout Bit            := '0'  ;
+    p25 : inout Character      := NUL  ;
+    p26 : inout SEVERITY_LEVEL := NOTE ;
+    p27 : inout Integer        := -1   ;
+    p28 : inout Real           := -1.0 ;
+    p29 : inout TIME           := 1 fs ;
+    p30 : inout Natural        := 0    ;
+    p31 : inout Positive       := 1    ;
+    p32 : inout Apollo_string  := "abcdefgh";
+    p33 : inout V_register     := B"10010110"
+    );
+END c04s03b02x00p29n10i00113ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00113arch OF c04s03b02x00p29n10i00113ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    p23 = FALSE   and
+                   p24 = '0'     and 
+                   p25 = NUL     and 
+                   p26 = NOTE    and 
+                   p27 = -1      and 
+                   p28 = -1.0    and 
+                   p29 = 1 fs    and 
+                   p30 = 0       and 
+                   p31 = 1       and 
+                   p32 = "abcdefgh"and
+                   p33 = B"10010110"   )
+      report "***PASSED TEST: c04s03b02x00p29n10i00113"
+      severity NOTE;
+    assert (    p23 = FALSE   and
+                p24 = '0'     and 
+                p25 = NUL     and 
+                p26 = NOTE    and 
+                p27 = -1      and 
+                p28 = -1.0    and 
+                p29 = 1 fs    and 
+                p30 = 0       and 
+                p31 = 1       and 
+                p32 = "abcdefgh"and
+                p33 = B"10010110"   )
+      report "***FAILED TEST:c04s03b02x00p29n10i00113 - Values of INOUT port reading failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00113arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1137.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1137.vhd
new file mode 100644
index 0000000..f3b9543
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1137.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1137.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n02i01137ent IS
+  type aray1 is array (integer range <>) of bit;
+END c06s05b00x00p04n02i01137ent;
+
+ARCHITECTURE c06s05b00x00p04n02i01137arch OF c06s05b00x00p04n02i01137ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable nul : aray1(2 to 1); -- null array 
+    variable nu2 : aray1(9 to 1); -- null array
+  BEGIN
+    --
+    -- Test the range direction
+    --
+    assert NOT(nul = nu2) 
+      report "***PASSED TEST: c06s05b00x00p04n02i01137" 
+      severity NOTE;
+    assert (nul = nu2) 
+      report "***FAILED TEST: c06s05b00x00p04n02i01137- The slice is a null slice if the discrete range is a null range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n02i01137arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1138.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1138.vhd
new file mode 100644
index 0000000..2c25fda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1138.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1138.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01138ent IS
+END c06s05b00x00p05n02i01138ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01138arch OF c06s05b00x00p05n02i01138ent IS
+  signal T1 : boolean;
+BEGIN
+  TESTING: PROCESS
+    variable B : Bit_vector (1 to 10) := B"01010_10101";
+  BEGIN
+    if B(1 to 2) = B"01"  then
+      T1 <= TRUE;
+    else
+      T1 <= FALSE;
+    end if;
+    wait for 1 ns;
+    assert NOT(T1=TRUE)
+      report "***PASSED TEST: c06s05b00x00p05n02i01138"
+      severity NOTE;
+    assert (T1=TRUE)
+      report "***FAILED TEST: c06s05b00x00p05n02i01138 - The prefix and the discrete range of the slice is not correctly evaluated."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01138arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1139.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1139.vhd
new file mode 100644
index 0000000..9d450fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1139.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1139.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01139ent IS
+END c06s05b00x00p05n02i01139ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01139arch OF c06s05b00x00p05n02i01139ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ABASE is array (ENUM1 range <>) of BOOLEAN;
+    subtype A1 is ABASE(ENUM1 range M1 to M5);
+    function F(i : integer) return ENUM1 is
+    begin
+      return M2;
+    end F;
+
+    function G(j : integer) return ENUM1 is
+    begin
+      return M4;
+    end G;
+    variable ii : integer;
+    variable jj : integer;
+    variable V1 : A1 ; -- := (others=>TRUE);
+    variable V4 : A1 ; -- := (others=>TRUE);
+    variable V2, V3: ENUM1;
+  BEGIN
+    V1(M1 to M3) := V1(F(ii) to G(jj));
+    assert NOT(V1(M1 to M3)=(false,false,false))
+      report "***PASSED TEST: c06s05b00x00p05n02i01139"
+      severity NOTE;
+    assert (V1(M1 to M3)=(false,false,false))
+      report "***FAILED TEST: c06s05b00x00p05n02i01139 - Dynamic expressions are permitted in lower and upper bounds in range specifications in array slices." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01139arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc114.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc114.vhd
new file mode 100644
index 0000000..616be3a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc114.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc114.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c04s03b02x00p29n10i00114pkg is
+  type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER;
+  type V_REGISTER    is array (INTEGER range 0 to 7) of BIT;
+end c04s03b02x00p29n10i00114pkg;
+
+use work.c04s03b02x00p29n10i00114pkg.all;
+ENTITY c04s03b02x00p29n10i00114ent IS
+  port (
+    p23 : inout Boolean        := FALSE;
+    p24 : inout Bit            := '0'  ;
+    p25 : inout Character      := NUL  ;
+    p26 : inout SEVERITY_LEVEL := NOTE ;
+    p27 : inout Integer        := -1   ;
+    p28 : inout Real           := -1.0 ;
+    p29 : inout TIME           := 1 fs ;
+    p30 : inout Natural        := 0    ;
+    p31 : inout Positive       := 1    ;
+    p32 : inout Apollo_string  := "abcdefgh";
+    p33 : inout V_register     := B"10010110"
+    );
+END c04s03b02x00p29n10i00114ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00114arch OF c04s03b02x00p29n10i00114ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    p23   <= not p23;
+    p24   <= not p24;
+    p25   <= character'succ(p25);
+    p26   <= severity_level'succ(p26);
+    p27   <= p27 + p27;
+    p28   <= p28 + p28;
+    p29   <= p29 + p29;
+    p30   <= p30 + p30;
+    p31   <= p31 + p31;
+    p32(2)   <= character'succ(p32(2));
+    p33(1)   <= not p33(1);
+    
+    wait on p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33;
+
+    assert NOT(    p23 = TRUE   and
+                   p24 = '1'     and 
+                   p25 = SOH     and 
+                   p26 = WARNING    and 
+                   p27 = -2      and 
+                   p28 = -2.0    and 
+                   p29 = 2 fs    and 
+                   p30 = 0       and 
+                   p31 = 2       and 
+                   p32 = "accdefgh"and
+                   p33 = B"11010110"   )
+      report "***PASSED TEST: c04s03b02x00p29n10i00114"
+      severity NOTE;
+    assert (    p23 = TRUE   and
+                p24 = '1'     and 
+                p25 = SOH     and 
+                p26 = WARNING    and 
+                p27 = -2      and 
+                p28 = -2.0    and 
+                p29 = 2 fs    and 
+                p30 = 0       and 
+                p31 = 2       and 
+                p32 = "accdefgh"and
+                p33 = B"11010110"   )
+      report "***FAILED TEST: c04s03b02x00p29n10i00114 - Interface object update test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00114arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1140.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1140.vhd
new file mode 100644
index 0000000..e725695
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1140.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1140.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01140ent IS
+END c06s05b00x00p05n02i01140ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01140arch OF c06s05b00x00p05n02i01140ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ABASE is array (ENUM1 range <>) of BOOLEAN;
+    subtype A1 is ABASE(ENUM1 range M1 to M5);
+    variable V1 : A1 ; -- := (others=>TRUE);
+    variable V4 : A1 ; -- := (others=>TRUE);
+    variable V2, V3: ENUM1;
+  BEGIN
+    V1(V2 to V3) := V4(V2 to V3);
+    assert NOT(V1(M1 to M3)=(false,false,false))
+      report "***PASSED TEST: c06s05b00x00p05n02i01140"
+      severity NOTE;
+    assert (V1(M1 to M3)=(false,false,false))
+      report "***FAILED TEST: c06s05b00x00p05n02i01140 - Dynamic expressions are permitted in lower and upper bounds in range specifications in array slices." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01140arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1145.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1145.vhd
new file mode 100644
index 0000000..4a81abd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1145.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1145.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01145ent IS
+END c06s05b00x00p05n02i01145ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01145arch OF c06s05b00x00p05n02i01145ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ABASE is array (ENUM1 range <>) of BOOLEAN;
+    subtype A1 is ABASE(ENUM1 range M1 to M5);
+    variable V1 : A1 ; -- := (others=>TRUE);
+    variable V4 : A1 ; -- := (others=>TRUE);
+    variable V2, V3: ENUM1;
+  BEGIN
+    V1(V2 to V3) := V4(V2 to V3);
+    assert NOT(V1=(false,false,false,false,false))
+      report "***PASSED TEST: c06s05b00x00p05n02i01145"
+      severity NOTE;
+    assert (V1=(false,false,false,false,false))
+      report "***FAILED TEST: c06s05b00x00p05n02i01145 - Dynamic expressions are permitted in lower and upper bounds in range specifications in array slices." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01145arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1147.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1147.vhd
new file mode 100644
index 0000000..4d515a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1147.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1147.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n03i01147ent IS
+END c06s05b00x00p05n03i01147ent;
+
+ARCHITECTURE c06s05b00x00p05n03i01147arch OF c06s05b00x00p05n03i01147ent IS
+  SUBTYPE thirteen is INTEGER range 0 to 12;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE null_array    : bit_vector ( 1 to 0 ); -- OK, a nice clean null array
+    VARIABLE slice       : bit_vector ( thirteen );
+  BEGIN
+
+    assert NOT(    null_array = slice (11 to 10)   and
+                   null_array = slice (-1 to -5)   and
+                   null_array = slice (15 to 14)  )
+      report "***PASSED TEST: c06s05b00x00p05n03i01147"
+      severity NOTE;
+    assert ( null_array = slice (11 to 10)   and
+             null_array = slice (-1 to -5)   and
+             null_array = slice (15 to 14)  )
+      report "***FAILED TEST: c06s05b00x00p05n03i01147 - The bounds of a null slice need not belong to the subtype of the index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n03i01147arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1149.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1149.vhd
new file mode 100644
index 0000000..1792cb9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1149.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1149.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p07n02i01149ent IS
+END c06s05b00x00p07n02i01149ent;
+
+ARCHITECTURE c06s05b00x00p07n02i01149arch OF c06s05b00x00p07n02i01149ent IS
+  type    A is array (10 downto 1) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable var : A := (66,66,others=>6);
+  BEGIN
+    wait for 5 ns;
+    assert NOT( var(1) = 6 )
+      report "***PASSED TEST: c06s05b00x00p07n02i01149"
+      severity NOTE;
+    assert ( var(1) = 6 )
+      report "***FAILED TEST: c06s05b00x00p07n02i01149 - A(N) is an element of the array A(decline) and has the corresponding element type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p07n02i01149arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc115.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc115.vhd
new file mode 100644
index 0000000..3063a4c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc115.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc115.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n10i00115ent IS
+  PORT ( prt_inout : INOUT INTEGER );
+  
+  ATTRIBUTE attr1 : INTEGER;
+  ATTRIBUTE attr1 OF prt_inout : SIGNAL   IS 200;
+END c04s03b02x00p29n10i00115ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00115arch OF c04s03b02x00p29n10i00115ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    ASSERT prt_inout'attr1 = 200 REPORT "ERROR: Bad value for prt_inout'attr1" SEVERITY FAILURE;
+
+    assert NOT( prt_inout'attr1 = 200 )   
+      report "***PASSED TEST: c04s03b02x00p29n10i00115"
+      severity NOTE;
+    assert ( prt_inout'attr1 = 200 )   
+      report "***FAILED TEST: c04s03b02x00p29n10i00115 - Interface object attribute reading test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00115arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1151.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1151.vhd
new file mode 100644
index 0000000..010c7db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1151.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1151.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p07n02i01151ent IS
+END c06s05b00x00p07n02i01151ent;
+
+ARCHITECTURE c06s05b00x00p07n02i01151arch OF c06s05b00x00p07n02i01151ent IS
+  type    A is array (1 to 10) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable var : A := (6,6,others=>88);
+  BEGIN
+    wait for 5 ns;
+    assert NOT( var(1) = 6 )
+      report "***PASSED TEST: c06s05b00x00p07n02i01151"
+      severity NOTE;
+    assert ( var(1) = 6 )
+      report "***FAILED TEST: c06s05b00x00p07n02i01151 - A(N) is an element of the array A(ascending) and has the corresponding element type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p07n02i01151arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1152.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1152.vhd
new file mode 100644
index 0000000..e9bc582
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1152.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1152.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01152ent IS
+END c06s06b00x00p02n01i01152ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01152arch OF c06s06b00x00p02n01i01152ent IS
+  type iarray is array (1 to 10) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for foo in iarray'range(1) loop  -- Success_here
+      k := k + 1;
+    end loop;
+    assert NOT( k=10 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01152"
+      severity NOTE;
+    assert ( k=10 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01152 - The attribute name consists of a prefix, an apostrophe('), an attribute designator, and (optionally) a static expression enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01152arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1153.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1153.vhd
new file mode 100644
index 0000000..d028f30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1153.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1153.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01153ent IS
+END c06s06b00x00p02n01i01153ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01153arch OF c06s06b00x00p02n01i01153ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    A1 is array (1 to 2) of BOOLEAN;
+    type    A2 is array (1 to 2) of A1;
+    variable    V  : A2;
+    variable    k  : integer;
+  BEGIN
+    if V(1)'LOW = 1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01153"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01153 - The attribute name consists of a prefix, an apostrophe('), an attribute designator, and (optionally) a static expression enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01153arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1154.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1154.vhd
new file mode 100644
index 0000000..6ab209b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1154.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1154.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s06b00x00p02n01i01154pkg is
+  type A1 is array (1 to 2) of BOOLEAN;
+  type A2 is array (1 to 2) of A1;
+end c06s06b00x00p02n01i01154pkg;
+
+use work.c06s06b00x00p02n01i01154pkg.all;
+ENTITY c06s06b00x00p02n01i01154ent IS
+  port (PT: A2) ;
+  attribute AT1 : BOOLEAN;
+  attribute AT1 of PT : signal is TRUE;
+END c06s06b00x00p02n01i01154ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01154arch OF c06s06b00x00p02n01i01154ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 5;
+  BEGIN
+    if PT'AT1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01154"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01154 - The attribute name consists of a prefix, an apostrophe('), an attribute designator, and (optionally) a static expression enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01154arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1155.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1155.vhd
new file mode 100644
index 0000000..2f1f2c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1155.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1155.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01155ent IS
+END c06s06b00x00p02n01i01155ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01155arch OF c06s06b00x00p02n01i01155ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    ABASE is array (INTEGER range <>) of BOOLEAN;            
+    subtype A1    is ABASE(1 to 5);
+    variable V : A1;
+    variable k : integer := 0;
+  BEGIN
+    if V(2 to 4)'LOW = 2 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01155"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01155 - The prefix of an attribute name may be a slice name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01155arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1156.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1156.vhd
new file mode 100644
index 0000000..78444a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1156.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1156.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s06b00x00p02n01i01156pkg is
+  type A1 is array (1 to 5) of BOOLEAN;
+end c06s06b00x00p02n01i01156pkg;
+
+use work.c06s06b00x00p02n01i01156pkg.all;
+ENTITY c06s06b00x00p02n01i01156ent IS
+  port      (PT: A1) ;
+  attribute AT1 : BOOLEAN;
+  attribute AT1 of PT : signal is TRUE;
+END c06s06b00x00p02n01i01156ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01156arch OF c06s06b00x00p02n01i01156ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if PT'AT1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01156"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01156 - The prefix of an attribute name may be a slice name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01156arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1157.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1157.vhd
new file mode 100644
index 0000000..54852cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1157.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1157.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01157ent IS
+END c06s06b00x00p02n01i01157ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01157arch OF c06s06b00x00p02n01i01157ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 5) of BOOLEAN;
+    type R1 is record
+                 RE1: REAL;
+                 RE2: A1;
+               end record;
+    variable V: R1;
+    variable k : integer := 0;
+  BEGIN
+    if V.RE2'LOW = 1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01157"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01157 - The prefix of an attribute name may be a selected name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01157arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1159.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1159.vhd
new file mode 100644
index 0000000..a2ba4a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1159.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1159.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01159ent IS
+END c06s06b00x00p02n01i01159ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01159arch OF c06s06b00x00p02n01i01159ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type arr is array(0 to 50) of boolean;
+
+    function ret_arr(I : integer) return arr is
+      variable RA : arr ;
+    begin
+      return  RA;
+    end ret_arr;
+    variable k : integer := 0;
+  BEGIN
+    k := arr'low;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01159"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01159 - The prefix of an attribute name may be a selected name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01159arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc116.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc116.vhd
new file mode 100644
index 0000000..f89f798
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc116.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc116.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n10i00116ent IS
+END c04s03b02x00p29n10i00116ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00116arch OF c04s03b02x00p29n10i00116ent IS
+
+  PROCEDURE p1 ( prm_inout : INOUT INTEGER ) IS
+    ATTRIBUTE attr1 : INTEGER;
+    ATTRIBUTE attr1 OF prm_inout : VARIABLE IS 300;
+  BEGIN
+    ASSERT prm_inout'attr1 = 300 REPORT "ERROR: Bad value for prm_inout'attr1" SEVERITY FAILURE;
+    assert NOT(   prm_inout'attr1 = 300 ) 
+      report "***PASSED TEST: c04s03b02x00p29n10i00116"
+      severity NOTE;
+    assert (   prm_inout'attr1 = 300 ) 
+      report "***FAILED TEST: c04s03b02x00p29n10i00116 - Interface object attribute reading in a subprogram test failed."
+      severity ERROR;
+  END;
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE tmp : INTEGER;
+  BEGIN
+--
+    p1 ( tmp );
+--
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00116arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1164.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1164.vhd
new file mode 100644
index 0000000..74f6d22
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1164.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1164.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s06b00x00p02n01i01164pkg is
+  type A1 is array (1 to 2) of BOOLEAN;
+  type A2 is array (1 to 2) of A1;
+end c06s06b00x00p02n01i01164pkg;
+
+use work.c06s06b00x00p02n01i01164pkg.all;
+
+ENTITY c06s06b00x00p02n01i01164ent IS
+  port      (PT: A2);
+  attribute AT1 : BOOLEAN;
+  attribute AT1 of PT : signal is TRUE;
+END c06s06b00x00p02n01i01164ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01164arch OF c06s06b00x00p02n01i01164ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if PT'AT1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01164"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01164 - The prefix of an attribute name may be an indexed name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01164arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1165.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1165.vhd
new file mode 100644
index 0000000..585888d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1165.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1165.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01165ent IS
+END c06s06b00x00p02n01i01165ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01165arch OF c06s06b00x00p02n01i01165ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 2) of BOOLEAN;
+    type A2 is array (1 to 2) of A1;
+    variable V : A2;
+    variable k : integer := 0;
+  BEGIN
+    if V(1)'LOW = 1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01165"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01165 - The prefix of an attribute name may be an indexed name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01165arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1166.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1166.vhd
new file mode 100644
index 0000000..6ae1ccc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1166.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1166.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01166ent IS
+END c06s06b00x00p02n01i01166ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01166arch OF c06s06b00x00p02n01i01166ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 2) of BOOLEAN;
+    type A2 is array (1 to 2) of A1;
+    variable V : A2;
+    variable k : integer := 0;
+  BEGIN
+    if V(1)'HIGH = 2 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01166"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01166 - The prefix of an attribute name may be an indexed name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01166arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1167.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1167.vhd
new file mode 100644
index 0000000..fbb1bc8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1167.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1167.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p04n02i01167ent IS
+END c06s06b00x00p04n02i01167ent;
+
+ARCHITECTURE c06s06b00x00p04n02i01167arch OF c06s06b00x00p04n02i01167ent IS
+  attribute p: POSITIVE;
+  signal    s: integer;
+  attribute p of s: signal is 10;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if s'p = 10 then  -- Success_here
+      s <=  12;
+    else
+      s <= 0;
+    end if;
+    wait for 10 ns;
+    assert NOT( s=12 )
+      report "***PASSED TEST: c06s06b00x00p04n02i01167"
+      severity NOTE;
+    assert ( s=12 )
+      report "***FAILED TEST: c06s06b00x00p04n02i01167 - The meaning of the prefix of an attribute must be determinable independently of the attribute designator and independently of the fact that it is the prefix of an attribute."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p04n02i01167arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc117.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc117.vhd
new file mode 100644
index 0000000..d9c943c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc117.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc117.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c04s03b02x00p29n10i00117pkg is
+  type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER;
+  type V_REGISTER    is array (INTEGER range 0 to 7) of BIT;
+end c04s03b02x00p29n10i00117pkg;
+
+use work.c04s03b02x00p29n10i00117pkg.all;
+ENTITY c04s03b02x00p29n10i00117ent IS
+  port (
+    p23 : buffer Boolean        := FALSE;
+    p24 : buffer Bit            := '0'  ;
+    p25 : buffer Character      := NUL  ;
+    p26 : buffer SEVERITY_LEVEL := NOTE ;
+    p27 : buffer Integer        := -1   ;
+    p28 : buffer Real           := -1.0 ;
+    p29 : buffer TIME           := 1 fs ;
+    p30 : buffer Natural        := 0    ;
+    p31 : buffer Positive       := 1    ;
+    p32 : buffer Apollo_string  :=  "abcdefgh";
+    p33 : buffer V_register     := B"10010110"
+    );
+END c04s03b02x00p29n10i00117ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00117arch OF c04s03b02x00p29n10i00117ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    p23 = FALSE   and
+                   p24 = '0'     and 
+                   p25 = NUL     and 
+                   p26 = NOTE    and 
+                   p27 = -1      and 
+                   p28 = -1.0    and 
+                   p29 = 1 fs    and 
+                   p30 = 0       and 
+                   p31 = 1       and 
+                   p32 = "abcdefgh"and
+                   p33 = B"10010110"   )
+      report "***PASSED TEST: c04s03b02x00p29n10i00117"
+      severity NOTE;
+    assert (    p23 = FALSE   and
+                p24 = '0'     and 
+                p25 = NUL     and 
+                p26 = NOTE    and 
+                p27 = -1      and 
+                p28 = -1.0    and 
+                p29 = 1 fs    and 
+                p30 = 0       and 
+                p31 = 1       and 
+                p32 = "abcdefgh"and
+                p33 = B"10010110"   )
+      report "***FAILED TEST: c04s03b02x00p29n10i00117 - The buffer ports on entities should be able to read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00117arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1174.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1174.vhd
new file mode 100644
index 0000000..0ae0eaf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1174.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1174.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p06n01i01174ent IS
+END c06s06b00x00p06n01i01174ent;
+
+ARCHITECTURE c06s06b00x00p06n01i01174arch OF c06s06b00x00p06n01i01174ent IS
+  signal    POS : Integer;
+  attribute PIO : positive;
+  attribute PIO of POS : signal is 10; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT(POS'PIO = 10) 
+      report "***PASSED TEST: c06s06b00x00p06n01i01174" 
+      severity NOTE;
+    assert (POS'PIO = 10) 
+      report "***FAILED TEST: c06s06b00x00p06n01i01174 - If the attribute designator does not denote a predefined attribute, the static expression in the attribute name must not be present."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p06n01i01174arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1175.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1175.vhd
new file mode 100644
index 0000000..b502e4d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1175.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1175.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p01n02i01175ent IS
+END c08s00b00x00p01n02i01175ent;
+
+ARCHITECTURE c08s00b00x00p01n02i01175arch OF c08s00b00x00p01n02i01175ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : integer := 0;
+    variable b : integer := 1;
+  BEGIN
+    LP1 : for i in 1 to 10 loop
+      a := a + 1; 
+    end loop;
+
+    if a = 10 then
+      b := 10;
+    elsif a = 0 then
+      b := 0;
+    else
+      b := 5;
+    end if;
+
+    assert NOT( (a=10) and (b=10) )
+      report "***PASSED TEST: c08s00b00x00p01n02i01175"
+      severity NOTE;
+    assert ( (a=10) and (b=10) )
+      report "***FAILED TEST: c08s00b00x00p01n02i01175 - Sequential statements are permitted in a sequence of statements."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p01n02i01175arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1176.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1176.vhd
new file mode 100644
index 0000000..c483172
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1176.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1176.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p01n02i01176ent IS
+END c08s00b00x00p01n02i01176ent;
+
+ARCHITECTURE c08s00b00x00p01n02i01176arch OF c08s00b00x00p01n02i01176ent IS
+  signal k : integer := 0;
+BEGIN
+  L1 : process
+  begin
+    k <= 5;
+    wait for 1 ns;
+  end process L1;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(k = 5) 
+      report "***PASSED TEST: c08s00b00x00p01n02i01176"
+      severity NOTE;
+    assert (k = 5) 
+      report "***FAILED TEST: c08s00b00x00p01n02i01176 - Sequential statement are executed in the order in which they appear."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p01n02i01176arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1177.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1177.vhd
new file mode 100644
index 0000000..c1ac855
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1177.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1177.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p01n02i01177ent IS
+END c08s00b00x00p01n02i01177ent;
+
+ARCHITECTURE c08s00b00x00p01n02i01177arch OF c08s00b00x00p01n02i01177ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if FALSE = FALSE then
+    end if;
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c08s00b00x00p01n02i01177"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c08s00b00x00p01n02i01177 - Empty sequence of statement is permitted in 'if statement'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p01n02i01177arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1178.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1178.vhd
new file mode 100644
index 0000000..d8c269f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1178.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1178.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p01n02i01178ent IS
+END c08s00b00x00p01n02i01178ent;
+
+ARCHITECTURE c08s00b00x00p01n02i01178arch OF c08s00b00x00p01n02i01178ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    case TRUE is
+      when TRUE   =>
+      when FALSE   =>
+    end case;
+    assert FALSE 
+      report "***PASSED TEST: c08s00b00x00p01n02i01178"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p01n02i01178arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1179.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1179.vhd
new file mode 100644
index 0000000..98b9b21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1179.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1179.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p01n02i01179ent IS
+END c08s00b00x00p01n02i01179ent;
+
+ARCHITECTURE c08s00b00x00p01n02i01179arch OF c08s00b00x00p01n02i01179ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for i in FALSE to TRUE loop
+    end loop;
+    assert FALSE 
+      report "***PASSED TEST: c08s00b00x00p01n02i01179"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p01n02i01179arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc118.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc118.vhd
new file mode 100644
index 0000000..4984bac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc118.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc118.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c04s03b02x00p29n10i00118pkg is
+  type Apollo_string is array (INTEGER range 1 to 8) of CHARACTER;
+  type V_REGISTER    is array (INTEGER range 0 to 7) of BIT;
+end c04s03b02x00p29n10i00118pkg;
+
+use work.c04s03b02x00p29n10i00118pkg.all;
+ENTITY c04s03b02x00p29n10i00118ent IS
+  port (
+    p23 : buffer Boolean        := FALSE;
+    p24 : buffer Bit            := '0'  ;
+    p25 : buffer Character      := NUL  ;
+    p26 : buffer SEVERITY_LEVEL := NOTE ;
+    p27 : buffer Integer        := -1   ;
+    p28 : buffer Real           := -1.0 ;
+    p29 : buffer TIME           := 1 ns ;
+    p30 : buffer Natural        := 0    ;
+    p31 : buffer Positive       := 1    ;
+    p32 : buffer Apollo_string  :=  "abcdefgh";
+    p33 : buffer V_register     := B"10010110"
+    );
+END c04s03b02x00p29n10i00118ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00118arch OF c04s03b02x00p29n10i00118ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    p23  <= not p23 AFTER 10 ns;
+    p24  <= not p24 AFTER 10 ns;
+
+    if (p25 /= character'high) then
+      p25  <= character'succ (p25) AFTER 10 ns;
+    else
+      p25  <= character'low  AFTER 10 ns;
+    end if;
+    
+    if (p26 /= severity_level'high) then
+      p26  <= severity_level'succ(p26) AFTER 10 ns;
+    else
+      p26  <= severity_level'low  AFTER 10 ns;
+    end if;
+    
+    p27  <= integer'succ(p27) AFTER 10 ns; -- unlikely to overflow....
+    p28  <= p28 + 1.0 AFTER 10 ns;
+    p29  <= p29 * 2 AFTER 10 ns;
+    p30  <= p30 + 1 AFTER 10 ns;
+    p31  <= p31 * 2 AFTER 10 ns;
+    p32(2) <= character'succ (p32(2)) AFTER 10 ns;
+    p33(1) <= not p33(1) AFTER 10 ns;
+
+    WAIT ON p23,p24,p25,p26,p27,p28,p29,p30,p31,p32,p33;
+
+    assert NOT(    p23 = TRUE   and
+                   p24 = '1'     and 
+                   p25 = SOH     and 
+                   p26 = WARNING    and 
+                   p27 = 0      and 
+                   p28 = 0.0    and 
+                   p29 = 2 ns    and 
+                   p30 = 1       and 
+                   p31 = 2       and 
+                   p32 = "accdefgh"and
+                   p33 = B"11010110"   )
+      report "***PASSED TEST: c04s03b02x00p29n10i00118"      severity NOTE;
+    assert (    p23 = TRUE   and
+                p24 = '1'     and 
+                p25 = SOH     and 
+                p26 = WARNING    and 
+                p27 = 0      and 
+                p28 = 0.0    and 
+                p29 = 2 ns    and 
+                p30 = 1       and 
+                p31 = 2       and 
+                p32 = "accdefgh"and
+                p33 = B"11010110"   )
+      report "***FAILED TEST: c04s03b02x00p29n10i00118 - The buffer ports on entities should be able to read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00118arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1180.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1180.vhd
new file mode 100644
index 0000000..b8ddcac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1180.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1180.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p02n01i01180ent IS
+END c08s00b00x00p02n01i01180ent;
+
+ARCHITECTURE c08s00b00x00p02n01i01180arch OF c08s00b00x00p02n01i01180ent IS
+BEGIN
+  TESTING: PROCESS
+    procedure check (x : out boolean) is
+    begin
+      x := false;   
+    end;
+    variable k : boolean;
+  BEGIN
+    check (k);
+    assert NOT( k=false )
+      report "***PASSED TEST: c08s00b00x00p02n01i01180"
+      severity NOTE;
+    assert ( k=false )
+      report "***FAILED TEST: c08s00b00x00p02n01i01180 - Procedure call is a sequential statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s00b00x00p02n01i01180arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1182.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1182.vhd
new file mode 100644
index 0000000..89dab97
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1182.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1182.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p01n01i01182ent IS
+END c08s01b00x00p01n01i01182ent;
+
+ARCHITECTURE c08s01b00x00p01n01i01182arch OF c08s01b00x00p01n01i01182ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : time := 0 ns;
+  BEGIN
+    k := now;
+    wait for 5 ns;
+    k := now - k;
+    assert NOT( k=5 ns )
+      report "***PASSED TEST: c08s01b00x00p01n01i01182"
+      severity NOTE;
+    assert ( k=5  ns)
+      report "***FAILED TEST: c08s01b00x00p01n01i01182 - A wait statement cause the suspension of the process statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p01n01i01182arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1183.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1183.vhd
new file mode 100644
index 0000000..99b90e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1183.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1183.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p02n01i01183ent IS
+END c08s01b00x00p02n01i01183ent;
+
+ARCHITECTURE c08s01b00x00p02n01i01183arch OF c08s01b00x00p02n01i01183ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c08s01b00x00p02n01i01183"
+      severity NOTE;
+    wait;
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p02n01i01183 - A wait statement with no argument"
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c08s01b00x00p02n01i01183arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1187.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1187.vhd
new file mode 100644
index 0000000..46263fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1187.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1187.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p03n01i01187ent IS
+END c08s01b00x00p03n01i01187ent;
+
+ARCHITECTURE c08s01b00x00p03n01i01187arch OF c08s01b00x00p03n01i01187ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;   
+    wait on k;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s01b00x00p03n01i01187"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c08s01b00x00p03n01i01187 - In wait statement, the reserved word 'on' followed by one or more signal names separated with commas(,)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p03n01i01187arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc119.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc119.vhd
new file mode 100644
index 0000000..c09d028
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc119.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc119.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n10i00119ent IS
+  port ( prt_buffer : BUFFER INTEGER );
+
+  ATTRIBUTE attr1 : INTEGER;
+  ATTRIBUTE attr1 OF prt_buffer : SIGNAL   IS 200;
+END c04s03b02x00p29n10i00119ent;
+
+ARCHITECTURE c04s03b02x00p29n10i00119arch OF c04s03b02x00p29n10i00119ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT prt_buffer'attr1 = 200 REPORT "ERROR: Bad value for prt_buffer'attr1" SEVERITY FAILURE;
+    assert NOT(   prt_buffer'attr1 = 200 ) 
+      report "***PASSED TEST: c04s03b02x00p29n10i00119"
+      severity NOTE;
+    assert (   prt_buffer'attr1 = 200 ) 
+      report "***FAILED TEST: c04s03b02x00p29n10i00119 - Reading the attributes of the interface object of buffer test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n10i00119arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1192.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1192.vhd
new file mode 100644
index 0000000..76ff5c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1192.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1192.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p03n01i01192ent IS
+END c08s01b00x00p03n01i01192ent;
+
+ARCHITECTURE c08s01b00x00p03n01i01192arch OF c08s01b00x00p03n01i01192ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;   
+    wait on k, k, k;
+    assert NOT(k=5)
+      report "***PASSED TEST: c08s01b00x00p03n01i01192" 
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c08s01b00x00p03n01i01192 - Same signal multiple times. This is not made clearly in LRM" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p03n01i01192arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1197.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1197.vhd
new file mode 100644
index 0000000..926ba21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1197.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1197.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p05n01i01197ent IS
+END c08s01b00x00p05n01i01197ent;
+
+ARCHITECTURE c08s01b00x00p05n01i01197arch OF c08s01b00x00p05n01i01197ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;
+    wait on k until (k=5); 
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s01b00x00p05n01i01197"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s01b00x00p05n01i01197 - In the wait statement, the reserved word 'until' is followed by a boolean statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p05n01i01197arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1199.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1199.vhd
new file mode 100644
index 0000000..72f1d42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1199.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1199.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p07n01i01199ent IS
+END c08s01b00x00p07n01i01199ent;
+
+ARCHITECTURE c08s01b00x00p07n01i01199arch OF c08s01b00x00p07n01i01199ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;
+    wait for 70 ns;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s01b00x00p07n01i01199"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s01b00x00p07n01i01199 - In timeout clause, the reserved word 'for' is followed by a time expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p07n01i01199arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1205.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1205.vhd
new file mode 100644
index 0000000..ed14023
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1205.vhd
@@ -0,0 +1,192 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1205.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s01b00x00p08n03i01205pkg is
+  
+  -- Type declarations.
+  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
+  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
+
+  -- Define the bus resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
+  
+  -- Further type declarations.
+  subtype SWITCH_T       is switchF SWITCH_LEVEL;
+  type    WORD           is array(0 to 31) of SWITCH_T;
+
+end c08s01b00x00p08n03i01205pkg;
+
+package body c08s01b00x00p08n03i01205pkg is
+
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
+    
+  begin
+    return( S(1) );
+  end switchf;
+  
+end c08s01b00x00p08n03i01205pkg;
+
+
+
+use work.c08s01b00x00p08n03i01205pkg.all;
+entity c08s01b00x00p08n03i01205ent_a is
+  
+  generic ( GenOne : in INTEGER ; GenTwo :INTEGER);
+  
+end c08s01b00x00p08n03i01205ent_a;
+
+-------------------------------------------------------------------------
+
+architecture c08s01b00x00p08n03i01205arch_a of c08s01b00x00p08n03i01205ent_a is
+  -- Type definitions.
+  type WORD2 is array( 0 to 31 ) of SWITCH_LEVEL;
+  
+  -- Local signals.
+  signal A, B    : WORD;
+  signal UnResolved    : WORD2;
+  
+  
+begin
+  
+  TEST_PROCESS:  process
+    -- Constant declarations.
+    constant One : INTEGER := 1;
+    constant Two : INTEGER := 2;
+    
+    -- Local variables.
+    variable ShouldBeTime : TIME;
+    variable I            : INTEGER;
+
+    variable k    : integer := 0;
+    
+  begin
+    -- Test locally static signals.
+    A( 1 ) <= 'X' after 10 ns;
+    A( 2 ) <= 'X' after 5 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on A(1);
+    
+    -- Should wake up when the A(1) assignment takes place.
+    assert (A(1) = 'X');
+    assert (ShouldBeTime = NOW);
+    
+    if (A(1) /= 'X' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    
+    -- Perform same test, but with a constant.
+    A( One ) <= '1' after 10 ns;
+    A( Two ) <= '1' after 5 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on A(One);
+    
+    -- Should wake up when the A(1) assignment takes place.
+    assert (A(One) = '1');
+    assert (ShouldBeTime = NOW);
+
+    if (A(One) /= '1' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    
+    -- Perform same test, but with a generic.   (globally static)
+    A( GenOne ) <= 'X' after 10 ns;
+    A( GenTwo ) <= 'X' after 5 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on A(GenOne);
+    
+    -- Should wake up when the A(1) assignment takes place.
+    assert (A(GenOne) = 'X');
+    assert (ShouldBeTime = NOW);
+    
+    if (A(GenOne) /= 'X' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    
+    -- Perform same test, but assigning to the whole thing.
+    A <= ('1','1','1','1','1','1','1','1','1','1',
+          '1','1','1','1','1','1','1','1','1','1',
+          '1','1','1','1','1','1','1','1','1','1',
+          '1','1') after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on A(GenOne);
+    
+    -- Should wake up when the all assignments take place.
+    assert (A(GenOne) = '1');
+    assert (ShouldBeTime = NOW);
+
+    if (A(GenOne) /= '1' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    
+    -- Now, perform same test but assigning to a composite
+    -- signal which is NOT resolved at the scalar subelement
+    -- level.
+    UnResolved <= ('1','1','1','1','1','1','1','1','1','1',
+                   '1','1','1','1','1','1','1','1','1','1',
+                   '1','1','1','1','1','1','1','1','1','1',
+                   '1','1') after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on UnResolved(GenOne);
+    
+    -- Should wake up when the all assignments take place.
+    assert (UnResolved(GenOne) = '1');
+    assert (ShouldBeTime = NOW);
+    
+    if (UnResolved(GenOne) /= '1' and ShouldBeTime /= Now) then
+      k := 1;   
+    end if;
+    
+    assert NOT(k = 0) 
+      report "***PASSED TEST: c08s01b00x00p08n03i01205" 
+      severity NOTE;
+    assert (k = 0) 
+      report "***FAILED TEST: c08s01b00x00p08n03i01205 - All statically indexed signal names (both locally and globally static) may be used in the sensitivity clause of a wait statement." 
+      severity ERROR;
+    wait;
+  end process TEST_PROCESS;
+  
+end c08s01b00x00p08n03i01205arch_a;
+
+use work.c08s01b00x00p08n03i01205pkg.all;
+ENTITY c08s01b00x00p08n03i01205ent IS
+END c08s01b00x00p08n03i01205ent;
+
+ARCHITECTURE c08s01b00x00p08n03i01205arch OF c08s01b00x00p08n03i01205ent IS
+  
+  component c08s01b00x00p08n03i01205ent_a
+    generic( GenOne : in INTEGER;  GenTwo : INTEGER );
+  end component;
+  for T1 : c08s01b00x00p08n03i01205ent_a use entity work.c08s01b00x00p08n03i01205ent_a(c08s01b00x00p08n03i01205arch_a); 
+
+BEGIN
+
+  T1 : c08s01b00x00p08n03i01205ent_a generic map ( 1, 2 );
+
+END c08s01b00x00p08n03i01205arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1206.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1206.vhd
new file mode 100644
index 0000000..d9d1f10
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1206.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1206.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p08n04i01206ent IS
+END c08s01b00x00p08n04i01206ent;
+
+ARCHITECTURE c08s01b00x00p08n04i01206arch OF c08s01b00x00p08n04i01206ent IS
+  signal cll : integer := 0;
+  signal del : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    cll   <= 5 after 55 ns;
+    del   <= 5 after 55 ns;   
+    wait until (cll = 5 or  del = 5);
+    assert NOT( cll=5 )
+      report "***PASSED TEST: c08s01b00x00p08n04i01206"
+      severity NOTE;
+    assert ( cll=5 )
+      report "***FAILED TEST: c08s01b00x00p08n04i01206 - if no sensitivity clause appears, the sensitivity set will contain the signals denoted by the longest static prefix of each signal name that appears as a primary in the condition of the condirion clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p08n04i01206arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1207.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1207.vhd
new file mode 100644
index 0000000..b639ef3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1207.vhd
@@ -0,0 +1,140 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1207.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s01b00x00p08n04i01207pkg is
+
+  -- Type declarations.
+  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
+  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
+
+  -- Define the bus resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
+
+  -- Further type declarations.
+  subtype SWITCH_T       is switchF SWITCH_LEVEL;
+  type    WORD           is array(0 to 31) of SWITCH_T;
+
+end c08s01b00x00p08n04i01207pkg;
+
+package body c08s01b00x00p08n04i01207pkg is
+
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
+  begin
+    return( S(1) );
+  end switchf;
+
+end c08s01b00x00p08n04i01207pkg;
+
+use work.c08s01b00x00p08n04i01207pkg.all;
+ENTITY c08s01b00x00p08n04i01207ent IS
+END c08s01b00x00p08n04i01207ent;
+
+ARCHITECTURE c08s01b00x00p08n04i01207arch OF c08s01b00x00p08n04i01207ent IS
+
+  -- Local types.
+  type WORD2 is array(0 to 31) of SWITCH_LEVEL;
+  
+  -- Local signals.
+  signal A, B    : WORD;
+  signal UnResolved    : WORD2;
+
+BEGIN
+  TESTING: PROCESS
+    -- Constant declarations.
+    constant One : INTEGER := 1;
+    constant Two : INTEGER := 2;
+    
+    -- Local variables.
+    variable ShouldBeTime : TIME;
+    variable I            : INTEGER;
+    variable k        : integer := 0;
+  BEGIN
+    -- 1. Test waiting on static signals.
+    for I in 0 to 31 loop
+      A( I ) <= 'X' after (I * 1 ns);
+    end loop;
+    ShouldBeTime := NOW + 31 ns;
+    wait until (A(31) = 'X');
+    
+    -- Should wake up when the A(31) assignment takes place.
+    if (A(31) /= 'X' and ShouldBeTime /= NOW) then
+      k := 1;
+    end if;
+    assert (A(31) = 'X');
+    assert (ShouldBeTime = NOW);
+    
+    -- 2. Test waiting on non-static signals.  (should still have same behavior, but just be slower)
+    for I in 0 to 31 loop
+      A( I ) <= '1' after (I * 1 ns);
+    end loop;
+    ShouldBeTime := NOW + 31 ns;
+    I := 31;
+    wait until (A(I) = '1');
+    
+    -- Should wake up when the A(31) assignment takes place.
+    if (A(I) /= '1' and ShouldBeTime /= NOW) then
+      k := 1;
+    end if;
+    assert (A(I) = '1');
+    assert (ShouldBeTime = NOW);
+    
+    -- 3. Test that waiting on a variable expression merely times-out. 
+    ShouldBeTime := NOW + 35 ns;
+    wait until (I = 47) for 35 ns;
+    if (ShouldBeTime /= NOW) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 4. Perform same test as '1' on a signal not resolved at the scalar subelement level.
+    UnResolved <= ( 'X','X','X','X','X','X','X','X','X','X',
+                    'X','X','X','X','X','X','X','X','X','X',
+                    'X','X','X','X','X','X','X','X','X','X',
+                    'X','X' ) after 31 ns;
+    ShouldBeTime := NOW + 31 ns;
+    wait until (UnResolved(31) = 'X');
+    
+    -- Should wake up when the UnResolved(31) assignment takes place.
+    if (UnResolved(31) /= 'X' and ShouldBeTime /= NOW) then
+      k := 1;
+    end if;
+    assert (UnResolved(31) = 'X');
+    assert (ShouldBeTime = NOW);
+
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s01b00x00p08n04i01207"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s01b00x00p08n04i01207 - The sensitivity set of a wait statement will contain the signal denoted by the longest static prefix of each signal name if no sensitivity clause." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p08n04i01207arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1208.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1208.vhd
new file mode 100644
index 0000000..691c892
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1208.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1208.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p24n01i01208ent IS
+END c08s01b00x00p24n01i01208ent;
+
+ARCHITECTURE c08s01b00x00p24n01i01208arch OF c08s01b00x00p24n01i01208ent IS
+  type    WOR is array (0 to 3) of BIT;
+  signal   TS   : WOR := "0000";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    TS <= "0101" after 20 ns;
+    wait on TS until (TS(1) = '1');
+    assert NOT( TS(1) = '1' )
+      report "***PASSED TEST: c08s01b00x00p24n01i01208"
+      severity NOTE;
+    assert ( TS(1) = '1' )
+      report "***FAILED TEST: c08s01b00x00p24n01i01208 - Composite signal in teh sensitivity list of the wait statement is equivalent to having each subelement of that composite signal in the list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p24n01i01208arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1209.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1209.vhd
new file mode 100644
index 0000000..6ddbec4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1209.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1209.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s01b00x00p24n01i01209pkg is
+
+  -- Type declarations.
+  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
+  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
+
+  -- Define the bus resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
+
+  -- Further type declarations.
+  subtype SWITCH_T       is switchF SWITCH_LEVEL;
+  type    WORD           is array(0 to 31) of SWITCH_T;
+
+end c08s01b00x00p24n01i01209pkg;
+
+package body c08s01b00x00p24n01i01209pkg is
+
+-- A dumb resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
+  begin
+    return( S(1) );
+  end switchf;
+
+end c08s01b00x00p24n01i01209pkg;
+
+
+use work.c08s01b00x00p24n01i01209pkg.all;
+ENTITY c08s01b00x00p24n01i01209ent IS
+END c08s01b00x00p24n01i01209ent;
+
+ARCHITECTURE c08s01b00x00p24n01i01209arch OF c08s01b00x00p24n01i01209ent IS
+
+  -- Local types
+  type WORD2 is array(0 to 31) of SWITCH_LEVEL;
+  type REC   is RECORD
+                  R1    : SWITCH_T;
+                  R2    : SWITCH_T;
+                end RECORD;
+  
+  -- Local signals.
+  signal A : WORD;
+  signal UnResolved : WORD2;
+  signal RecSig     : REC;
+  
+BEGIN
+  TESTING: PROCESS
+    -- Constant declarations.
+    constant One : INTEGER := 1;
+    constant Two : INTEGER := 2;
+    
+    -- Local variables.
+    variable ShouldBeTime : TIME;
+    variable I            : INTEGER;
+    variable   k    : integer := 0;
+
+
+  BEGIN
+    --1. Test waiting on an array of scalar resolved elements.
+    for I in 0 to 31 loop
+      ShouldBeTime := NOW + 1 ns;
+      A( I ) <= 'X' after 1 ns;
+      wait on A;
+      if (A(I) /= 'X' and ShouldBeTime /= Now) then
+        k := 1;
+      end if; 
+      -- Verify that we waited the right amount of time.
+      assert (ShouldBeTime = NOW);
+      assert (A( I ) = 'X');
+    end loop;
+    
+    -- 2. Test waiting on an array of scalar unresolved elements.
+    ShouldBeTime := NOW + 1 ns;
+    UnResolved <= ( '1','1','1','1','1','1','1','1','1','1',
+                    '1','1','1','1','1','1','1','1','1','1',
+                    '1','1','1','1','1','1','1','1','1','1',
+                    '1','1' ) after 1 ns;
+    wait on UnResolved;
+    if (UnResolved /= ( '1','1','1','1','1','1','1','1','1','1',
+                        '1','1','1','1','1','1','1','1','1','1',
+                        '1','1','1','1','1','1','1','1','1','1',
+                        '1','1' )  and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    -- Verify that we waited allright.
+    assert (ShouldBeTime = NOW);
+    for I in 0 to 31 loop
+      assert ( UnResolved( I ) = '1');
+    end loop;
+    
+    -- 3. Test waiting on a record.
+    RECSIG.R1 <= 'X' after 1 ns;
+    RECSIG.R2 <= 'X' after 2 ns;
+    ShouldBeTime := NOW + 1 ns;
+    wait on RECSIG;
+    if (RECSIG.R1 /= 'X' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (RECSIG.R1 = 'X');
+    ShouldBeTime := NOW + 1 ns;
+    wait on RECSIG;
+    if (RECSIG.R2 /= 'X' and ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (RECSIG.R2 = 'X');
+
+    assert NOT( k=0 ) 
+      report "***PASSED TEST: c08s01b00x00p24n01i01209"
+      severity NOTE;
+    assert ( k=0 ) 
+      report "***FAILED TEST: c08s01b00x00p24n01i01209 - The effect of a signal name denotes a signal of a composite type is as if name of each scalar subelement of that signal appears in the list." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p24n01i01209arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1210.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1210.vhd
new file mode 100644
index 0000000..4d7ed36
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1210.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1210.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p25n01i01210ent IS
+END c08s01b00x00p25n01i01210ent;
+
+ARCHITECTURE c08s01b00x00p25n01i01210arch OF c08s01b00x00p25n01i01210ent IS
+  signal T1 : BIT := '0';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    T1 <= '1' after 15 ns;
+    wait on T1 until (T1 = '1');
+    assert NOT( T1 = '1' )
+      report "***PASSED TEST: c08s01b00x00p25n01i01210"
+      severity NOTE;
+    assert ( T1 = '1' )
+      report "***FAILED TEST: c08s01b00x00p25n01i01210 - Process resumes execution when the condition clause in a wait statement is met"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p25n01i01210arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1211.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1211.vhd
new file mode 100644
index 0000000..d8e2a73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1211.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1211.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p25n01i01211ent IS
+END c08s01b00x00p25n01i01211ent;
+
+ARCHITECTURE c08s01b00x00p25n01i01211arch OF c08s01b00x00p25n01i01211ent IS
+  -- Local signals.
+  signal A : BIT;
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable ShouldBeTime : TIME;
+  BEGIN
+    -- Check a condition clause that is NEVER true.
+    -- Should suspend until the timeout_clause is reached.
+    A <= '1' after 1 ns;
+    ShouldBeTime := NOW + 20 ns;
+    wait on A until (FALSE) for 20 ns;
+    assert NOT(ShouldBeTime = NOW)
+      report "***PASSED TEST: c08s01b00x00p25n01i01211"
+      severity NOTE;
+    assert (ShouldBeTime = NOW)
+      report "***FAILED TEST: c08s01b00x00p25n01i01211 - If the condition specified by the condition clause is FALSE, the wait statement will suspend itself again." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p25n01i01211arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1212.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1212.vhd
new file mode 100644
index 0000000..833a3ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1212.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1212.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p25n02i01212ent IS
+END c08s01b00x00p25n02i01212ent;
+
+ARCHITECTURE c08s01b00x00p25n02i01212arch OF c08s01b00x00p25n02i01212ent IS
+  signal I : bit := '0';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    I <= '1' after 10 ns;
+    wait on I;
+    assert NOT( I = '1' )
+      report "***PASSED TEST: c08s01b00x00p25n02i01212"
+      severity NOTE;
+    assert ( I = '1' )
+      report "***FAILED TEST: c08s01b00x00p25n02i01212 - The condition clause assumes the default value TRUE when no condition clause is present."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p25n02i01212arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1213.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1213.vhd
new file mode 100644
index 0000000..8c590fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1213.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1213.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p25n02i01213ent IS
+END c08s01b00x00p25n02i01213ent;
+
+ARCHITECTURE c08s01b00x00p25n02i01213arch OF c08s01b00x00p25n02i01213ent IS
+  signal   A : BIT;
+BEGIN
+  TESTING: PROCESS
+    variable   ShouldBeTime : TIME;
+  BEGIN
+    A <= '1' after 1 ns;
+    ShouldBeTime := NOW + 1 ns;
+    wait on A for 20 ns;
+    assert NOT(ShouldBeTime = NOW) 
+      report "***PASSED TEST: c08s01b00x00p25n02i01213"
+      severity NOTE;
+    assert (ShouldBeTime = NOW) 
+      report "***FAILED TEST: c08s01b00x00p25n02i01213 - When NO condition_clause is present, the condition clause 'until TRUE' is assumed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p25n02i01213arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1214.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1214.vhd
new file mode 100644
index 0000000..a01e7c3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1214.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1214.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p26n01i01214ent IS
+END c08s01b00x00p26n01i01214ent;
+
+ARCHITECTURE c08s01b00x00p26n01i01214arch OF c08s01b00x00p26n01i01214ent IS
+  signal sig1 : integer;
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 0;
+    variable y : time    := 0 ns;
+  BEGIN
+    y := now;
+    wait on sig1 until x >= 12 for 20 ns;
+    y := now - y;
+    assert NOT( y = 20 ns )
+      report "***PASSED TEST: c08s01b00x00p26n01i01214"
+      severity NOTE;
+    assert ( y = 20 ns )
+      report "***FAILED TEST: c08s01b00x00p26n01i01214 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p26n01i01214arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1215.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1215.vhd
new file mode 100644
index 0000000..fe98b3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1215.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1215.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p26n01i01215ent IS
+END c08s01b00x00p26n01i01215ent;
+
+ARCHITECTURE c08s01b00x00p26n01i01215arch OF c08s01b00x00p26n01i01215ent IS
+  -- Local signals.
+  signal A : BIT;
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable ShouldBeTime    : TIME;
+    variable I               : INTEGER;
+    variable k      : integer := 0;
+  BEGIN
+    -- Given that a particular condition will never be TRUE,
+    -- verify that we always wait for the desired amount of time.
+    for I in 0 to 100 loop
+      -- Perform the assignment.
+      if  ((I mod 2) = 0) then
+        A <= '1' after 1 ns;
+      else
+        A <= '0' after 1 ns;
+      end if;
+
+      -- Compute the time we should end the wait statement.
+      ShouldBeTime := NOW + 2 ns;
+
+      -- Wait the desired amount of time.  Note that the condition
+      -- will never be TRUE.
+      if  ((I mod 2) = 0) then
+        wait until (A = '0') for 2 ns;
+      else
+        wait until (A = '1') for 2 ns;
+      end if;
+      
+      -- Assert that we ended on time.
+      assert (ShouldBeTime = NOW);
+      if (ShouldBeTime /= NOW) then
+        k := 1;
+      end if;
+    end loop;
+    assert NOT(k=0)
+      report "***PASSED TEST: c08s01b00x00p26n01i01215"
+      severity NOTE;
+    assert (k=0)
+      report "***FAILED TEST: c08s01b00x00p26n01i01215 - The timeout clause specifies the maximum amount of time the process will remain suspended at this wait statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p26n01i01215arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1216.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1216.vhd
new file mode 100644
index 0000000..a9d5242
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1216.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1216.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p26n02i01216ent IS
+END c08s01b00x00p26n02i01216ent;
+
+ARCHITECTURE c08s01b00x00p26n02i01216arch OF c08s01b00x00p26n02i01216ent IS
+  signal   A : BIT;
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable ShouldBeTime : TIME;
+    variable I            : INTEGER;
+  BEGIN
+    -- First, wait for 1fs;
+    wait for 1 fs;
+
+    assert FALSE
+      report "***PASSED TEST: c08s01b00x00p26n02i01216 - This test needs manual check. Assertion Failure Note should not appear."
+      severity NOTE;
+    -- Then, wait until the end of time.
+    wait;
+    assert (FALSE)
+      report "Should never have executed this statement."  
+      severity FAILURE;
+  END PROCESS TESTING;
+
+END c08s01b00x00p26n02i01216arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1218.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1218.vhd
new file mode 100644
index 0000000..280e593
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1218.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1218.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p26n03i01218ent IS
+END c08s01b00x00p26n03i01218ent;
+
+ARCHITECTURE c08s01b00x00p26n03i01218arch OF c08s01b00x00p26n03i01218ent IS
+  signal I : bit := '0';
+BEGIN
+  TESTING: PROCESS
+    constant t1 : time := 100 ns;
+    constant t2 : time := 10 ns;
+  BEGIN
+    I <= '1' after 200 ns;
+    wait on I for (t1 - t2);
+    assert NOT( I = '0' ) 
+      report "***PASSED TEST: c08s01b00x00p26n03i01218" 
+      severity NOTE;
+    assert ( I = '0' ) 
+      report "***FAILED TEST: c08s01b00x00p26n03i01218 - The FOR clause in a WAIT statement must evaluate to a positive value."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p26n03i01218arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1220.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1220.vhd
new file mode 100644
index 0000000..5158f61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1220.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1220.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p27n01i01220ent IS
+END c08s01b00x00p27n01i01220ent;
+
+ARCHITECTURE c08s01b00x00p27n01i01220arch OF c08s01b00x00p27n01i01220ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable y : time := 0 ns;
+  BEGIN
+    y := now;
+    wait for 20 ns;
+    y := now - y;
+    assert NOT( y = 20 ns )
+      report "***PASSED TEST: c08s01b00x00p27n01i01220"
+      severity NOTE;
+    assert ( y = 20 ns )
+      report "***FAILED TEST: c08s01b00x00p27n01i01220 - The suspended process does not resume immediately after the timeout interval has expired."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p27n01i01220arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1221.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1221.vhd
new file mode 100644
index 0000000..da664a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1221.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1221.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p27n01i01221ent IS
+END c08s01b00x00p27n01i01221ent;
+
+ARCHITECTURE c08s01b00x00p27n01i01221arch OF c08s01b00x00p27n01i01221ent IS
+  signal  k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    variable y : time := 0 ns;
+  BEGIN
+    y := now;
+    k <= transport 5 after 20 ns;
+    wait until k = 5; 
+    y := now - y;
+    assert NOT( y = 20 ns )
+      report "***PASSED TEST: c08s01b00x00p27n01i01221"
+      severity NOTE;
+    assert ( y = 20 ns )
+      report "***FAILED TEST: c08s01b00x00p27n01i01221 - The suspended process does not resume immediately after the timeout interval has expired."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p27n01i01221arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1222.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1222.vhd
new file mode 100644
index 0000000..c02f59d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1222.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1222.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p27n01i01222ent IS
+END c08s01b00x00p27n01i01222ent;
+
+ARCHITECTURE c08s01b00x00p27n01i01222arch OF c08s01b00x00p27n01i01222ent IS
+  -- Local signals.
+  signal A : BIT;
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable ShouldBeTime    : TIME;
+    variable I               : INTEGER;
+    variable k       : integer := 0;
+  BEGIN
+    -- Assign same value to a signal.  Verify that the wait statement waits for the timeout interval.
+    ShouldBeTime := NOW + 3 ns;
+    A <= A after 2 ns;
+    wait until (A = '1') for 3 ns;
+    if (ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+
+    -- Assign same value to a signal.  Verify that the wait statement waits for the timeout interval.
+    ShouldBeTime := NOW + 3 ns;
+    A <= A after 2 ns;
+    wait on A for 3 ns;
+    if (ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s01b00x00p27n01i01222"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s01b00x00p27n01i01222 - The suspended process should resume immediately after the timeout interval has expired."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p27n01i01222arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1223.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1223.vhd
new file mode 100644
index 0000000..fc8d0f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1223.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1223.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p27n01i01223ent IS
+END c08s01b00x00p27n01i01223ent;
+
+ARCHITECTURE c08s01b00x00p27n01i01223arch OF c08s01b00x00p27n01i01223ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    ShouldBeTime : time := 0 fs;
+  BEGIN
+    ShouldBeTime := NOW + 1 fs;
+    wait for 1 fs;
+    assert NOT(ShouldBeTime = NOW)
+      report "***PASSED TEST: c08s01b00x00p27n01i01223"
+      severity NOTE;
+    assert (ShouldBeTime = NOW)
+      report "***FAILED TEST: c08s01b00x00p27n01i01223 - The minimum waiting time test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p27n01i01223arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1224.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1224.vhd
new file mode 100644
index 0000000..fd52d9e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1224.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1224.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p28n01i01224ent IS
+END c08s01b00x00p28n01i01224ent;
+
+ARCHITECTURE c08s01b00x00p28n01i01224arch OF c08s01b00x00p28n01i01224ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 20 ns;
+    wait until (k = 5);
+    assert NOT( k=5 )
+      report "***PASSED TEST:c08s01b00x00p28n01i01224"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s01b00x00p28n01i01224 - The process will resume if the result of an event occuring on sentivity set is TRUE."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p28n01i01224arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1225.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1225.vhd
new file mode 100644
index 0000000..c1a0f6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1225.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1225.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p28n01i01225ent IS
+END c08s01b00x00p28n01i01225ent;
+
+ARCHITECTURE c08s01b00x00p28n01i01225arch OF c08s01b00x00p28n01i01225ent IS
+  -- Local signals.
+  signal A : BIT;
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable ShouldBeTime    : TIME;
+    variable I               : INTEGER;
+    variable k       : integer := 0;
+  BEGIN
+    -- Make sure it takes an EVENT to trigger the WAIT statement.
+    A <= A after 2 ns,           -- NOT an event.
+         (not A) after 4 ns;      -- an event.
+    ShouldBeTime := NOW + 4 ns;   -- Should wait for event.   
+    wait on A;
+    if (ShouldBeTime /= Now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW)
+      report "Did not wait for 4ns";
+
+    -- If the value of the condition is FALSE, resuspend.
+    -- If the value is TRUE, the process will resume.
+    A <= '1' after 2 ns,
+         '0' after 4 ns;
+
+    -- Make sure that we wait until the second one for
+    -- the following wait statement to resume.
+    ShouldBeTime := NOW + 4 ns;
+    wait until (A = '0');
+    if (ShouldBeTime /= Now and A /= '0') then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW)
+      report "Did not wait for 4ns";
+    assert (A = '0')
+      report "Did not assign the correct value.";
+    
+    -- Such resuspension does not involve the recalculation of the timeout interval.
+    -- If the value of the condition is FALSE, resuspend.
+    -- IF the value is TRUE, the process will resume.
+    A <= '1' after 2 ns,
+         '0' after 4 ns;
+    
+    -- Make sure that we wait until the second one for
+    -- the following wait statement to resume.
+    ShouldBeTime := NOW + 3 ns;
+    wait until (A = '0') for 3 ns;
+    if (ShouldBeTime /= Now and A /= '1') then
+      k := 1;   
+    end if;
+    assert (ShouldBeTime = NOW)
+      report "Did not wait for 3ns";
+    assert (A = '1')
+      report "Did not assign the correct value to A.";
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s01b00x00p28n01i01225"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s01b00x00p28n01i01225 - The process will resume if the result of an event occuring on sentivity set is TRUE."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p28n01i01225arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1230.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1230.vhd
new file mode 100644
index 0000000..5fc1d79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1230.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1230.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01230ent IS
+END c08s02b00x00p03n01i01230ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01230arch OF c08s02b00x00p03n01i01230ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert true;
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p03n01i01230"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01230arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1232.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1232.vhd
new file mode 100644
index 0000000..baa98a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1232.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1232.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01232ent IS
+END c08s02b00x00p03n01i01232ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01232arch OF c08s02b00x00p03n01i01232ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : boolean := TRUE;
+  BEGIN
+    k := FALSE;
+    assert k 
+      report "***PASSED TEST: c08s02b00x00p03n01i01232"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01232arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1233.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1233.vhd
new file mode 100644
index 0000000..8d1f760
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1233.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1233.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01233ent IS
+END c08s02b00x00p03n01i01233ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01233arch OF c08s02b00x00p03n01i01233ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p03n01i01233"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01233arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1234.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1234.vhd
new file mode 100644
index 0000000..7abfc5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1234.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1234.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01234ent IS
+END c08s02b00x00p03n01i01234ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01234arch OF c08s02b00x00p03n01i01234ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 5;
+  BEGIN
+    assert ((k+1) < (k-3)) 
+      report "***PASSED TEST: c08s02b00x00p03n01i01234" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01234arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1256.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1256.vhd
new file mode 100644
index 0000000..51feb14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1256.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1256.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01256ent IS
+END c08s02b00x00p04n02i01256ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01256arch OF c08s02b00x00p04n02i01256ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "Report this Note"
+      severity NOTE;   
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p04n02i01256"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01256arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1257.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1257.vhd
new file mode 100644
index 0000000..c268592
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1257.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1257.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01257ent IS
+END c08s02b00x00p04n02i01257ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01257arch OF c08s02b00x00p04n02i01257ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "Report this Warning"
+      severity WARNING;   
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p04n02i01257 - This test needed manual check to see WARNING assertion note appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01257arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1258.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1258.vhd
new file mode 100644
index 0000000..bfef1c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1258.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1258.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01258ent IS
+END c08s02b00x00p04n02i01258ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01258arch OF c08s02b00x00p04n02i01258ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "Report this Error"
+      severity ERROR;   
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p04n02i01258 - This test needed manual check to see ERROR assertion note appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01258arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1259.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1259.vhd
new file mode 100644
index 0000000..f9b4a87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1259.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1259.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01259ent IS
+END c08s02b00x00p04n02i01259ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01259arch OF c08s02b00x00p04n02i01259ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "Report this Failure"
+      severity FAILURE;   
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p04n02i01259 - This test needed manual check to see FAILURE assertion note appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01259arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1260.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1260.vhd
new file mode 100644
index 0000000..890f409
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1260.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1260.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p05n01i01260ent IS
+END c08s02b00x00p05n01i01260ent;
+
+ARCHITECTURE c08s02b00x00p05n01i01260arch OF c08s02b00x00p05n01i01260ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE
+      severity NOTE;
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p05n01i01260 - This test needs manual check to make sure that default value for the message ""Assertion violation"" appears."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p05n01i01260arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1261.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1261.vhd
new file mode 100644
index 0000000..fbd0f45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1261.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1261.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p05n01i01261ent IS
+END c08s02b00x00p05n01i01261ent;
+
+ARCHITECTURE c08s02b00x00p05n01i01261arch OF c08s02b00x00p05n01i01261ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    -- Print out the NOTE message:
+    assert (FALSE)
+      report "Verify that the following says 'Assertion violation'."
+      severity NOTE;
+
+    -- Print out the default message.
+    assert (FALSE)
+      severity WARNING;
+
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p05n01i01261 - This test needs manual check. Messages as NOTE: Verify that the following says 'Asserion violation' and WARNING: Assertion violation should appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p05n01i01261arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1262.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1262.vhd
new file mode 100644
index 0000000..ee7f720
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1262.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1262.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p05n03i01262ent IS
+END c08s02b00x00p05n03i01262ent;
+
+ARCHITECTURE c08s02b00x00p05n03i01262arch OF c08s02b00x00p05n03i01262ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+
+    assert FALSE
+      report "Report this string";
+
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p05n03i01262 - This test needs manual check to see that default value of the severity level is ERROR."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p05n03i01262arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1263.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1263.vhd
new file mode 100644
index 0000000..cb53f88
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1263.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1263.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p05n03i01263ent IS
+END c08s02b00x00p05n03i01263ent;
+
+ARCHITECTURE c08s02b00x00p05n03i01263arch OF c08s02b00x00p05n03i01263ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Print out the NOTE message:
+    assert (FALSE)
+      report "Verify that the following assertion violation is an error'."
+      severity NOTE;
+
+    -- Print out the default message and severity level.
+    assert (FALSE);
+
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p05n03i01263 - This test needs manual check. Messages NOTE: Verify that the following assertion violation is an error and ERROR: Assertion violation should appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p05n03i01263arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1265.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1265.vhd
new file mode 100644
index 0000000..ecf9e6e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1265.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1265.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p06n01i01265ent IS
+END c08s02b00x00p06n01i01265ent;
+
+ARCHITECTURE c08s02b00x00p06n01i01265arch OF c08s02b00x00p06n01i01265ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable I : integer := 1;
+  BEGIN
+
+    assert (I=1);
+    assert TRUE
+      report "Report on the message"; 
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p06n01i01265 - This test needs manual check. No other assertion messages should occur except this."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p06n01i01265arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1266.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1266.vhd
new file mode 100644
index 0000000..317f6ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1266.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1266.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p06n03i01266ent IS
+END c08s02b00x00p06n03i01266ent;
+
+ARCHITECTURE c08s02b00x00p06n03i01266arch OF c08s02b00x00p06n03i01266ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : boolean;
+    variable y : severity_level; 
+  BEGIN
+
+    assert k = true
+      report "Assertion violation"
+      severity y;
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p06n03i01266"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p06n03i01266arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1267.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1267.vhd
new file mode 100644
index 0000000..3bfb3db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1267.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1267.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p07n01i01267ent IS
+END c08s02b00x00p07n01i01267ent;
+
+ARCHITECTURE c08s02b00x00p07n01i01267arch OF c08s02b00x00p07n01i01267ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE;
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p07n01i01267 - This test needs manual check. The assertion message consists at least that 1.An indication that this message is from an assertion. 2.Severity level. 3.Value of the message string. 4.The name of the design unit."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p07n01i01267arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1268.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1268.vhd
new file mode 100644
index 0000000..21c9675
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1268.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1268.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p07n01i01268ent IS
+END c08s02b00x00p07n01i01268ent;
+
+ARCHITECTURE c08s02b00x00p07n01i01268arch OF c08s02b00x00p07n01i01268ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***PASSED TEST: c08s02b00x00p07n01i01268 - This test needs manual check."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p07n01i01268arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1269.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1269.vhd
new file mode 100644
index 0000000..ce0ba6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1269.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1269.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p02n01i01269ent IS
+END c08s04b00x00p02n01i01269ent;
+
+ARCHITECTURE c08s04b00x00p02n01i01269arch OF c08s04b00x00p02n01i01269ent IS
+  signal X1    : integer := 1;
+  signal X2    : integer := 2;
+  signal T1    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    T1   <= X1 + X2;
+    wait for 1 ns;
+    assert NOT(T1 = 3) 
+      report "***PASSED TEST: c08s04b00x00p02n01i01269"
+      severity NOTE;
+    assert (T1 = 3) 
+      report "***FAILED TEST: c08s04b00x00p02n01i01269 - Signal assignment statement consists of a target, a signal assignment operator"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p02n01i01269arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1292.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1292.vhd
new file mode 100644
index 0000000..f830c57
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1292.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1292.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p05n01i01292ent IS
+END c08s04b00x00p05n01i01292ent;
+
+ARCHITECTURE c08s04b00x00p05n01i01292arch OF c08s04b00x00p05n01i01292ent IS
+  signal done : integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    done <= 1 after 10 ns,
+            0 after 20 ns,
+            5 after 35 ns;
+    wait for 70 ns;
+    assert NOT( done=5 )
+      report "***PASSED TEST: c08s04b00x00p05n01i01292"
+      severity NOTE;
+    assert (done=5)
+      report "***FAILED TEST: c08s04b00x00p05n01i01292 - The waveform consists of one or more waveform elements separated with commas(,)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p05n01i01292arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1294.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1294.vhd
new file mode 100644
index 0000000..21b5324
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1294.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1294.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01294ent IS
+END c08s04b00x00p06n01i01294ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01294arch OF c08s04b00x00p06n01i01294ent IS
+  type   BIT_VECTOR is array (integer range <>) of BIT;
+  signal DID : BIT_VECTOR(0 to 7);
+BEGIN
+  TESTING: PROCESS
+    variable NUM1 : BIT_VECTOR(0 to 7) := B"01010101";
+  BEGIN
+    DID <= NUM1;
+    wait on  DID;
+    assert NOT( DID = B"01010101" )
+      report "***PASSED TEST: c08s04b00x00p06n01i01294"
+      severity NOTE;
+    assert ( DID = B"01010101" )
+      report "***FAILED TEST: c08s04b00x00p06n01i01294 - Type of the right hand and left hand side of the signal assignment statement must be the same"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01294arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1299.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1299.vhd
new file mode 100644
index 0000000..d54df2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1299.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1299.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01299ent IS
+END c08s04b00x00p06n01i01299ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01299arch OF c08s04b00x00p06n01i01299ent IS
+  signal   X : integer := 5;
+  signal  Y : integer := 3;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Y <= X;
+    wait for 1 ns;
+    assert NOT( Y=5 )  
+      report "***PASSED TEST: c08s04b00x00p06n01i01299"
+      severity NOTE;
+    assert ( Y=5 )  
+      report "***FAILED TEST: c08s04b00x00p06n01i01299 - Signal assignment in a process block." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01299arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1306.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1306.vhd
new file mode 100644
index 0000000..6130a0a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1306.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1306.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01306ent IS
+END c08s04b00x00p06n01i01306ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01306arch OF c08s04b00x00p06n01i01306ent IS
+  signal   S1 : BIT := '1';
+  type REC_1 is record
+                  RE_1:BIT;
+                  RE_2:INTEGER;
+                end record;
+  signal  S3 : REC_1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S3.RE_1 <= S1;
+    wait for 1 ns;
+    assert NOT(S3.RE_1 = '1') 
+      report "***PASSED TEST: c08s04b00x00p06n01i01306" 
+      severity NOTE;
+    assert (S3.RE_1 = '1') 
+      report "***FAILED TEST: c08s04b00x00p06n01i01306 - A indexed name can be used on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01306arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1307.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1307.vhd
new file mode 100644
index 0000000..ad21b83
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1307.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1307.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01307ent IS
+END c08s04b00x00p06n01i01307ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01307arch OF c08s04b00x00p06n01i01307ent IS
+  type UA is array (NATURAL range <>) of BIT;
+  subtype ARAY_1 is UA (0 to 500);
+  signal  S2 : ARAY_1;
+  signal   S1 : BIT := '1';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2(200) <= S1;
+    wait for 1 ns;
+    assert NOT(S2(200) = '1') 
+      report "***PASSED TEST: c08s04b00x00p06n01i01307" 
+      severity NOTE;
+    assert (S2(200) = '1') 
+      report "***FAILED TEST: c08s04b00x00p06n01i01307 - A indexed name can be used on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01307arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1309.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1309.vhd
new file mode 100644
index 0000000..1bf2b64
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1309.vhd
@@ -0,0 +1,152 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1309.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s04b00x00p07n01i01309pkg is
+
+  -- Type declarations.
+  subtype     BV2  is BIT_VECTOR( 0 to 1 );
+  subtype     CH2  is STRING( 1 to 2 );
+
+  -- Constant declarations.
+  constant BVC  : BV2 := B"00";
+  constant CHC  : CH2 := "bb";
+
+  -- Function returns BV2.
+  function  returnBV2 return BV2;
+
+  -- Function returns CH2.
+  function  returnCH2 return CH2;
+
+end c08s04b00x00p07n01i01309pkg;
+
+package body c08s04b00x00p07n01i01309pkg is
+  
+  -- Function returns BV2.
+  function  returnBV2 return BV2 is
+  begin
+    return ( BVC );
+  end returnBV2;
+  
+  -- Function returns CH2.
+  function  returnCH2 return CH2 is
+  begin
+    return( CHC );
+  end returnCH2;
+  
+end c08s04b00x00p07n01i01309pkg;
+
+use work.c08s04b00x00p07n01i01309pkg.all;
+ENTITY c08s04b00x00p07n01i01309ent IS
+END c08s04b00x00p07n01i01309ent;
+
+ARCHITECTURE c08s04b00x00p07n01i01309arch OF c08s04b00x00p07n01i01309ent IS
+  -- Local signals.
+  signal S       : BIT;
+  signal T       : BIT;
+  
+  signal C1, C2  : CHARACTER;
+BEGIN
+  TESTING: PROCESS
+    
+    -- local variables
+    variable BITV     : BV2 := B"11";
+    variable STRV     : CH2 := "ab";
+    variable ShouldBeTime : TIME;
+    
+    variable k : integer := 0;
+    
+  BEGIN
+    -- Assign with a variable as the expression.
+    ( S, T )  <= BITV after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on S,T;
+    if (ShouldBeTime /= Now or S /= BITV(0) or T /= BITV(1)) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((S = BITV( 0 )) and (T = BITV( 1 )));
+    
+    ( C1,C2 ) <= STRV after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on C1,C2;
+    if (ShouldBeTime /= Now or C1 /= STRV(1) or C2 /= STRV(2)) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((C1 = STRV( 1 )) and (C2 = STRV( 2 )));
+    
+    -- Assign with a function return value.
+    ( S, T )  <= returnBV2 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on S,T;
+    if (ShouldBeTime /= Now or S /= BVC(0) or T /= BVC(1)) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((S = BVC( 0 )) and (T = BVC( 1 )));
+    
+    ( C1,C2 ) <= returnCH2 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on C1,C2;
+    if (ShouldBeTime /= Now or C1 /= CHC(1) or C2 /= CHC(2)) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((C1 = CHC( 1 )) and (C2 = CHC( 2 )));
+    
+    -- Assign with a qualified expression.
+    ( S, T )  <= BV2'( '0', '1' ) after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on S,T;
+    if (ShouldBeTime /= Now or S /= '0' or T /= '1') then
+      k := 1;   
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((S = '0') and (T = '1'));
+    
+    ( C1,C2 ) <= CH2'( 'c', 'c' ) after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on C1,C2;
+    if (ShouldBeTime /= Now or C1 /= 'c' or C2 /= 'c') then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert ((C1 = 'c') and (C2 = 'c'));
+    
+    assert NOT( k = 0 ) 
+      report "***PASSED TEST: c08s04b00x00p07n01i01309"
+      severity NOTE;
+    assert ( k = 0 ) 
+      report "***FAILED TEST: c08s04b00x00p07n01i01309 - If the target of the signal assignment statement is in the form of an aggregate, then the type of the aggregate must be determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n01i01309arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc131.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc131.vhd
new file mode 100644
index 0000000..d6080cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc131.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc131.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x01p04n01i00131ent IS
+  generic ( constant c1 : integer := 9090 );
+END c04s03b02x01p04n01i00131ent;
+
+ARCHITECTURE c04s03b02x01p04n01i00131arch OF c04s03b02x01p04n01i00131ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c1 = 9090 ) 
+      report "***PASSED TEST: c04s03b02x01p04n01i00131" 
+      severity NOTE;
+    assert ( c1 = 9090 ) 
+      report "***FAILED TEST: c04s03b02x01p04n01i00131 - Constant declarations in generic interface list in generic interface list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x01p04n01i00131arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1310.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1310.vhd
new file mode 100644
index 0000000..debcc8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1310.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1310.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n02i01310ent IS
+END c08s04b00x00p07n02i01310ent;
+
+ARCHITECTURE c08s04b00x00p07n02i01310arch OF c08s04b00x00p07n02i01310ent IS
+  type sigrec is
+    record
+      A1 : bit;
+      A2 : integer;
+      A3 : character;
+      A4 : boolean;
+    end record;
+  signal   S1 : bit;
+  signal   S2 : integer;
+  signal   S3 : character;
+  signal   S4 : boolean;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (S1, S2, S3, S4) <= sigrec'('1', 1, '1', true);
+    wait for 1 ns;
+    assert NOT( (S1='1')and(S2=1)and(S3='1')and(S4=true) )
+      report "***PASSED TEST: c08s04b00x00p07n02i01310"
+      severity NOTE;
+    assert ( (S1='1')and(S2=1)and(S3='1')and(S4=true) )
+      report "***FAILED TEST: c08s04b00x00p07n02i01310 - A waveform element on the rigth-hand side must be the same as the base type of the aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n02i01310arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1316.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1316.vhd
new file mode 100644
index 0000000..f00af5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1316.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1316.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n04i01316ent IS
+END c08s04b00x00p07n04i01316ent;
+
+ARCHITECTURE c08s04b00x00p07n04i01316arch OF c08s04b00x00p07n04i01316ent IS
+  type sigrec is
+    record
+      B1 : bit;
+      B2 : integer;
+      B3 : boolean;
+    end record;
+  signal S1 : bit;
+  signal S2 : integer;
+  signal S3 : boolean;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (S1, S2, S3) <= sigrec'('0',2,false);
+    wait for 10 ns;
+    assert NOT( (S1 = '0') and (S2 = 2) and (S3 = false) )
+      report "***PASSED TEST: c08s04b00x00p07n04i01316"
+      severity NOTE;
+    assert ( (S1 = '0') and (S2 = 2) and (S3 = false) )
+      report "***FAILED TEST: c08s04b00x00p07n04i01316 - Right hand side values are assigned to the drivers associated with the signal named as the corresponding subelement of the aggreate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n04i01316arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1317.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1317.vhd
new file mode 100644
index 0000000..41bd148
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1317.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1317.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n01i01317ent IS
+END c08s04b00x00p07n01i01317ent;
+
+ARCHITECTURE c08s04b00x00p07n01i01317arch OF c08s04b00x00p07n01i01317ent IS
+  signal s1, s2 : CHARACTER := NUL;
+BEGIN
+  TESTING: PROCESS
+    type RT is
+      record
+        a : CHARACTER;
+        b : CHARACTER;
+      end record;
+
+    variable rv : RT := ('1', '2'); 
+  BEGIN
+    assert s1 = NUL;
+    assert s2 = NUL;
+    (s1, s2) <= rv;
+    wait on s1;
+    assert s1 = '1';
+    assert s2 = '2'; 
+    assert NOT( s1 = '1' and s2 = '2' )
+      report "***PASSED TEST:c08s04b00x00p07n01i01317"
+      severity NOTE;
+    assert ( s1 = '1' and s2 = '2' )
+      report "***FAILED TEST: c08s04b00x00p07n01i01317 - Aggregate (record type) signal assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n01i01317arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1318.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1318.vhd
new file mode 100644
index 0000000..6aaa5e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1318.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1318.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n01i01318ent IS
+END c08s04b00x00p07n01i01318ent;
+
+ARCHITECTURE c08s04b00x00p07n01i01318arch OF c08s04b00x00p07n01i01318ent IS
+  signal s1, s2 : CHARACTER := NUL;
+BEGIN
+  TESTING: PROCESS
+    type       AT is array (INTEGER range <>) of CHARACTER;
+    variable    av : AT(0 to 1) := ('1', '2');
+  BEGIN
+    assert s1 = NUL;
+    assert s2 = NUL;
+    (s1, s2) <= av;
+    wait on s1;
+    assert s1 = '1';
+    assert s2 = '2'; 
+    assert NOT( s1 = '1' and s2 = '2' )
+      report "***PASSED TEST: c08s04b00x00p07n01i01318" 
+      severity NOTE;
+    assert ( s1 = '1' and s2 = '2' )
+      report "***FAILED TEST: c08s04b00x00p07n01i01318 - Aggregate (array type) signal assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n01i01318arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1321.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1321.vhd
new file mode 100644
index 0000000..7f2c4ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1321.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1321.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p09n03i01321ent IS
+END c08s04b00x00p09n03i01321ent;
+
+ARCHITECTURE c08s04b00x00p09n03i01321arch OF c08s04b00x00p09n03i01321ent IS
+  signal S1 : BIT := '1';
+  signal S2 : BIT := '1';
+  signal S  : BIT := '1';
+BEGIN
+  S1 <= transport '0' after 5  ns,
+        '1' after 10 ns;
+  S2 <= transport S1  after 15 ns;
+  TEST : PROCESS(S2)
+    variable k : integer := 0;
+  BEGIN
+    if ((S2 = '0') and (NOW = 20 ns)) then   
+      k := 1;
+    end if;
+    if ((S2 = '1') and (NOW = 25 ns) and (k = 1)) then   
+      S <= '0' after 10 ns;
+    end if;
+  END PROCESS TEST;
+
+  TESTING: PROCESS(S)
+  BEGIN
+    if (NOW > 1 ns) then
+      assert NOT(S = '0') 
+        report "***PASSED TEST: c08s04b00x00p09n03i01321"
+        severity NOTE;
+      assert (S = '0')
+        report "***FAILED TEST: c08s04b00x00p09n03i01321 - Any pulse is transmitted, not matter how short its durtion"
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c08s04b00x00p09n03i01321arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1322.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1322.vhd
new file mode 100644
index 0000000..0877699
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1322.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1322.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p09n04i01322ent IS
+END c08s04b00x00p09n04i01322ent;
+
+ARCHITECTURE c08s04b00x00p09n04i01322arch OF c08s04b00x00p09n04i01322ent IS
+  signal S1 : BIT := '1';
+  signal S2 : BIT := '1';
+BEGIN
+  S1 <= transport '0' after 5 ns,
+        '1' after 10 ns;
+  S2 <= S1 after 15 ns;
+  TESTING: PROCESS(S2)
+  BEGIN
+    assert NOT( S2 = '1' )
+      report "***PASSED TEST: c08s04b00x00p09n04i01322"
+      severity NOTE;
+    assert ( S2 = '1' )
+      report "***FAILED TEST: c08s04b00x00p09n04i01322 - A pulse whose duration is shorter than the switching time of the circuit is not transmitted."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c08s04b00x00p09n04i01322arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1323.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1323.vhd
new file mode 100644
index 0000000..c4b8645
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1323.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1323.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p02n01i01323ent IS
+END c08s04b01x00p02n01i01323ent;
+
+ARCHITECTURE c08s04b01x00p02n01i01323arch OF c08s04b01x00p02n01i01323ent IS
+  signal   k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= transport 5;
+    wait for 1 ns;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s04b01x00p02n01i01323"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s04b01x00p02n01i01323 - waveform element in a signal assignment statement may either consist of a value expression and an after clause (optional)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p02n01i01323arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1327.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1327.vhd
new file mode 100644
index 0000000..8f78287
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1327.vhd
@@ -0,0 +1,228 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1327.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p03n02i01327ent IS
+END c08s04b01x00p03n02i01327ent;
+
+ARCHITECTURE c08s04b01x00p03n02i01327arch OF c08s04b01x00p03n02i01327ent IS
+  -- enumerated types.
+  type    SWITCH_LEVEL is ('0', '1', 'X');
+  subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+
+  -- integer types.
+  type POSITIVE        is range 0 to INTEGER'HIGH;
+
+  -- user defined physical types.
+  type DISTANCE is range 0 to 1E9
+    units
+      -- Base units.
+      A;                    -- angstrom
+
+      -- Metric lengths.
+      nm       = 10 A;      -- nanometer
+      um       = 1000 nm;   -- micrometer (or micron)
+      mm       = 1000 um;   -- millimeter
+      cm       = 10 mm;     -- centimeter
+
+      -- English lengths.
+      mil      = 254000 A;  -- mil
+      inch     = 1000 mil;  -- inch
+    end units;
+
+  -- floating point types.
+  type POSITIVE_R    is range 0.0 to REAL'HIGH;
+
+  -- array types.
+  type MEMORY is array(INTEGER range <>) of BIT;
+  type WORD   is array(0 to 31) of BIT;
+  type BYTE   is array(7 downto 0) of BIT;
+  
+  -- record types.
+  type DATE is
+    record
+      DAY           : INTEGER range 1 to 31;
+      MONTH         : INTEGER range 1 to 12;
+      YEAR          : INTEGER range -10000 to 1988;
+    end record;
+  
+  -- Signals with no resolution function.
+  signal SWITCHSIG : SWITCH_LEVEL;
+  signal LOGICSIG  : LOGIC_SWITCH;
+  signal CHARSIG   : CHARACTER;
+  signal BOOLSIG   : BOOLEAN;
+  signal SEVERSIG  : SEVERITY_LEVEL;
+  signal INTSIG    : INTEGER;
+  signal POSSIG    : POSITIVE;
+  signal DISTSIG   : DISTANCE;
+  signal TIMESIG   : TIME;
+  signal REALSIG   : REAL;
+  signal POSRSIG   : POSITIVE_R;
+  signal BYTESIG   : BYTE;
+  signal RECSIG    : DATE;
+
+  -- Composite signals with resolution functions on the scalar subelements.
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables
+    variable ShouldBeTime : TIME := 0 ns;
+
+    variable k : integer := 0;
+  BEGIN
+    -- Test each signal assignment.
+    SWITCHSIG <= '1' after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on SWITCHSIG;
+    if (ShouldBeTime /= now or switchsig /= '1') then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (SWITCHSIG = '1');
+    
+    LOGICSIG <= '1' after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on LOGICSIG;
+    if (ShouldBeTime /= now or logicsig /= '1') then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (LOGICSIG = '1');
+    
+    CHARSIG <= '1' after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on CHARSIG;
+    if (ShouldBeTime /= now or charsig /= '1') then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (CHARSIG = '1');
+    
+    BOOLSIG <= TRUE after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on BOOLSIG;
+    if (ShouldBeTime /= now or boolsig /= true) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (BOOLSIG = TRUE);
+    
+    SEVERSIG <= ERROR after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on SEVERSIG;
+    if (ShouldBeTime /= now or seversig /= error) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (SEVERSIG = ERROR);
+    
+    INTSIG <= 47 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on INTSIG;
+    if (ShouldBeTime /= now or intsig /= 47) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (INTSIG = 47);
+    
+    POSSIG <= 47 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on POSSIG;
+    if (ShouldBeTime /= now or possig /= 47) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (POSSIG = 47);
+    
+    DISTSIG <= 1 A after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on DISTSIG;
+    if (ShouldBeTime /= now or distsig /= 1 A) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (DISTSIG = 1 A);
+    
+    TIMESIG <= 10 ns after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on TIMESIG;
+    if (ShouldBeTime /= now or timesig /= 10 ns) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (TIMESIG = 10 ns);
+    
+    REALSIG <= 47.0 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on REALSIG;
+    if (ShouldBeTime /= now or realsig /= 47.0) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (REALSIG = 47.0);
+    
+    POSRSIG <= 47.0 after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on POSRSIG;
+    if (ShouldBeTime /= now or posrsig /= 47.0) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (POSRSIG = 47.0);
+    
+    BYTESIG <= B"10101010" after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on BYTESIG;
+    if (ShouldBeTime /= now or bytesig /= B"10101010") then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (BYTESIG = B"10101010");
+    
+    RECSIG <= ( DAY => 14, MONTH => 2, YEAR => 1988 ) after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on RECSIG;
+    if (ShouldBeTime /= now or recsig.day /= 14 or recsig.month /= 2 or recsig.year /= 1988) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (RECSIG.DAY = 14);
+    assert (RECSIG.MONTH = 2);
+    assert (RECSIG.YEAR = 1988);
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s04b01x00p03n02i01327"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s04b01x00p03n02i01327 - Evaluation of waveform elements is used to specify that driver is to assign a particular value to a target at the specified time."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p03n02i01327arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1328.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1328.vhd
new file mode 100644
index 0000000..92c7a5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1328.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1328.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s04b01x00p03n03i01328pkg is
+  
+  type MVL    is ('0', '1', 'Z');
+  type TVECT    is array (INTEGER RANGE <>) of MVL;
+  
+  function BUSFUNC(INPUT: TVECT) return MVL;
+
+  subtype TS1    is BUSFUNC MVL;
+  type    TSV    is array (INTEGER RANGE <>) of TS1;
+  subtype WORD    is TSV(1 downto 0);
+end c08s04b01x00p03n03i01328pkg;
+
+package body c08s04b01x00p03n03i01328pkg is
+  
+  function BUSFUNC(INPUT: TVECT) return MVL is
+    variable RESOLVED_VALUE: MVL := 'Z';
+  begin
+    for I in INPUT'RANGE loop
+      if INPUT(I) /= 'Z' then
+        RESOLVED_VALUE := INPUT(I);
+        exit;
+      end if;
+    end loop;
+    return RESOLVED_VALUE;
+  end BUSFUNC;
+
+end c08s04b01x00p03n03i01328pkg;
+
+use WORK.c08s04b01x00p03n03i01328pkg.all;
+ENTITY c08s04b01x00p03n03i01328ent IS
+END c08s04b01x00p03n03i01328ent;
+
+ARCHITECTURE c08s04b01x00p03n03i01328arch OF c08s04b01x00p03n03i01328ent IS
+  signal S1 : BIT :='1';
+  signal X  : BUSFUNC MVL BUS; 
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+
+    S1 <= transport '0' after 15 ns;
+
+    wait on S1;
+
+    if (S1 = '1') then
+      X <= '1';
+    else
+      X <= null after 5 ns;
+    end if;
+
+    wait for 6 ns;
+    assert NOT( X='Z' )
+      report "***PASSED TEST: c08s04b01x00p03n03i01328"
+      severity NOTE;
+    assert ( X='Z' )
+      report "***FAILED TEST: c08s04b01x00p03n03i01328 - The driver of the signal of the signal is turned off when the waveform element consists of the reserved word 'null' and an optional after clasuse."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p03n03i01328arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc133.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc133.vhd
new file mode 100644
index 0000000..6a67b8b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc133.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc133.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p08n01i00133ent IS
+END c04s03b02x02p08n01i00133ent;
+
+ARCHITECTURE c04s03b02x02p08n01i00133arch OF c04s03b02x02p08n01i00133ent IS
+  type RT1 is record
+                a : INTEGER;
+                b : INTEGER;
+              end record;
+BEGIN
+  TESTING: PROCESS
+
+    procedure Proc1(P : inout RT1; ref : in RT1; set : in RT1) is
+    begin
+      if (P = ref) then
+        P := set;
+      end if;
+    end;
+    
+    variable V : RT1 := (1, 2);
+
+  BEGIN
+    V := (1, 2);
+    Proc1(P.a => V.b, P.b => V.a, ref => (2, 1), set => (2, 3));
+                                        -- test here
+    assert V = (3, 2) report "FAIL: P didn't get set right";
+    assert NOT( V = (3,2) )
+      report "***PASSED TEST: c04s03b02x02p08n01i00133"
+      severity NOTE;
+    assert ( V = (3,2) )
+      report "***FAILED TEST: c04s03b02x02p08n01i00133 - Association element in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p08n01i00133arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1331.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1331.vhd
new file mode 100644
index 0000000..ec591a1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1331.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1331.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01331ent IS
+END c08s04b01x00p04n01i01331ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01331arch OF c08s04b01x00p04n01i01331ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 5 after 0 ns;
+    wait for 1 ns;
+    assert NOT( X=5 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01331" 
+      severity NOTE;
+    assert ( X=5 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01331 - Time expression may have a static value of zero and it is of the type TIME." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01331arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1332.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1332.vhd
new file mode 100644
index 0000000..5bd3512
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1332.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1332.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n02i01332ent IS
+END c08s04b01x00p04n02i01332ent;
+
+ARCHITECTURE c08s04b01x00p04n02i01332arch OF c08s04b01x00p04n02i01332ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    variable bef, aft, diff : TIME;
+  BEGIN
+    bef := NOW;   
+    k <= 5;
+    aft := NOW;
+    diff := aft - bef;
+    assert NOT( diff = 0 ns )
+      report "***PASSED TEST: c08s04b01x00p04n02i01332"
+      severity NOTE;
+    assert ( diff = 0 ns )
+      report "***FAILED TEST: c08s04b01x00p04n02i01332 - 0 ns is the default after clause"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n02i01332arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1335.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1335.vhd
new file mode 100644
index 0000000..c555f34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1335.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1335.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01335ent IS
+END c08s04b01x00p04n01i01335ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01335arch OF c08s04b01x00p04n01i01335ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 fs;
+    wait for 10 fs;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01335" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01335 - Predefined TIME unit fs as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01335arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1337.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1337.vhd
new file mode 100644
index 0000000..73c3865
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1337.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1337.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01337ent IS
+END c08s04b01x00p04n01i01337ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01337arch OF c08s04b01x00p04n01i01337ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 ps;
+    wait for 10 ps;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01337" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01337 - Predefined TIME unit ps as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01337arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1338.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1338.vhd
new file mode 100644
index 0000000..55b1dd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1338.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1338.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01338ent IS
+END c08s04b01x00p04n01i01338ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01338arch OF c08s04b01x00p04n01i01338ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 ns;
+    wait for 10 ns;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01338"
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01338 - Predefined TIME unit ns as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01338arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1339.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1339.vhd
new file mode 100644
index 0000000..3da648d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1339.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1339.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01339ent IS
+END c08s04b01x00p04n01i01339ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01339arch OF c08s04b01x00p04n01i01339ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 us;
+    wait for 10 us;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01339" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01339 - Predefined TIME unit us as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01339arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc134.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc134.vhd
new file mode 100644
index 0000000..395710d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc134.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc134.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p08n01i00134ent IS
+END c04s03b02x02p08n01i00134ent;
+
+ARCHITECTURE c04s03b02x02p08n01i00134arch OF c04s03b02x02p08n01i00134ent IS
+  type    AT1 is array (INTEGER range <>) of INTEGER;
+  subtype ST1 is AT1(1 to 2);
+BEGIN
+  TESTING: PROCESS
+
+    procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
+    begin
+      if ( P = ref ) then
+        P := set;
+      end if;
+    end;
+    
+    variable V1, V2 : INTEGER;
+
+  BEGIN
+    V1 := 1;
+    V2 := 2;
+    Proc1(P(1) => V2, P(2) => V1, ref => (2, 1), set => (2, 3));
+                                        -- test here
+    assert V1 = 3 report "FAIL: actual V1 didn't get set right";
+    assert V2 = 2 report "FAIL: actual V2 didn't get set right";
+
+    assert NOT( V1 = 3 and V2 = 2 )
+      report "***PASSED TEST: c04s03b02x02p08n01i00134"
+      severity NOTE;
+    assert ( V1 = 3 and V2 = 2 )
+      report "***FAILED TEST: c04s03b02x02p08n01i00134 - Association element in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p08n01i00134arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1340.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1340.vhd
new file mode 100644
index 0000000..a2bc7e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1340.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1340.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01340ent IS
+END c08s04b01x00p04n01i01340ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01340arch OF c08s04b01x00p04n01i01340ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 ms;
+    wait for 10 ms;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01340" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01340 - Predefined TIME unit ms as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01340arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1341.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1341.vhd
new file mode 100644
index 0000000..57f5be6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1341.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1341.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01341ent IS
+END c08s04b01x00p04n01i01341ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01341arch OF c08s04b01x00p04n01i01341ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 sec;
+    wait for 10 sec;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01341"
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01341 - Predefined TIME unit sec as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01341arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1342.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1342.vhd
new file mode 100644
index 0000000..79ed15f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1342.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1342.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01342ent IS
+END c08s04b01x00p04n01i01342ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01342arch OF c08s04b01x00p04n01i01342ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 10 min;
+    wait for 10 min;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01342" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01342 - Predefined TIME unit min as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01342arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1343.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1343.vhd
new file mode 100644
index 0000000..5404b96
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1343.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1343.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01343ent IS
+END c08s04b01x00p04n01i01343ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01343arch OF c08s04b01x00p04n01i01343ent IS
+  signal X : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= 15 after 1 hr;
+    wait for 1 hr;
+    assert NOT( X=15 ) 
+      report "***PASSED TEST: c08s04b01x00p04n01i01343" 
+      severity NOTE;
+    assert ( X=15 ) 
+      report "***FAILED TEST: c08s04b01x00p04n01i01343 - Predefined TIME unit hr as the base type of the time expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01343arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1344.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1344.vhd
new file mode 100644
index 0000000..73a4434
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1344.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1344.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p06n05i01344ent IS
+END c08s04b01x00p06n05i01344ent;
+
+ARCHITECTURE c08s04b01x00p06n05i01344arch OF c08s04b01x00p06n05i01344ent IS
+  signal k : integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <=   1 after 10 ns,
+           2 after 20 ns,
+           3 after 30 ns,
+           4 after 40 ns,
+           5 after 50 ns;
+    wait for 60 ns;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s04b01x00p06n05i01344"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s04b01x00p06n05i01344 - The sequence of new transactions must be in ascending order with respect to time."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p06n05i01344arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1347.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1347.vhd
new file mode 100644
index 0000000..6c512fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1347.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1347.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p07n01i01347ent IS
+END c08s04b01x00p07n01i01347ent;
+
+ARCHITECTURE c08s04b01x00p07n01i01347arch OF c08s04b01x00p07n01i01347ent IS
+  signal Add_bus : integer := 67;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Add_bus <= 1 after 5 ns, 6 after 10 ns, 12 after 19 ns;
+    Add_bus <= 6 after 12 ns, 20 after 19 ns, 6 after 21 ns;
+    wait;
+  END PROCESS TESTING;
+
+  TEST : PROCESS(Add_bus)
+    variable ok : integer := 1;
+  BEGIN
+    if (now = 5 ns) then
+      if (Add_bus /= 67) then
+        ok := 0;
+      end if;
+    elsif (now = 10 ns) then
+      if (Add_bus /= 6) then
+        ok := 0;
+      end if;
+    elsif (now = 12 ns) then
+      if (Add_bus /= 6) then
+        ok := 0;
+      end if;
+    elsif (now = 19 ns) then
+      if (Add_bus /= 20) then
+        ok := 0;
+      end if;
+    end if;
+    if (now = 21 ns) then
+      assert NOT( Add_bus = 6 and ok = 1)
+        report "***PASSED TEST: c08s04b01x00p07n01i01347"
+        severity NOTE;
+      assert ( Add_bus = 6 and ok = 1)
+        report "***FAILED TEST: c08s04b01x00p07n01i01347 - The sequence of transactions is used to update the projected output waveform representing the current and future values of the driver associated with the signal assignment statement. And this test failed."
+        severity ERROR;
+    end if;
+  END PROCESS TEST;
+
+END c08s04b01x00p07n01i01347arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1348.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1348.vhd
new file mode 100644
index 0000000..2227f81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1348.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1348.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p07n01i01348ent IS
+END c08s04b01x00p07n01i01348ent;
+
+ARCHITECTURE c08s04b01x00p07n01i01348arch OF c08s04b01x00p07n01i01348ent IS
+
+  -- Local signals.
+  signal S : BIT := '0';
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables.
+    variable S_INITIAL : BIT;
+    variable ShouldBeTime : TIME;
+
+    variable k : integer := 0;
+
+  BEGIN
+    -- 0. Keep around the initial value of S.
+    S_INITIAL := S;
+    
+    -- 1. When no preemption necessary, verify the results.
+    S <= transport (not S) after 10 ns, (S) after 20 ns;
+    -- a. Wait for first transaction.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now or S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+
+    -- b. Wait for second transaction.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+
+    -- 2. Preempt a transaction which is to occur at the same time as second one.
+    S_INITIAL := S;
+    S <= transport (S) after 10 ns;
+    S <= transport (not S) after 10 ns;     -- Should preempt first transaction.
+    -- a. Verify that the second transaction comes as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now or S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    
+    -- b. Verify that the first transaction has been preempted.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S for 10 ns;
+    if (ShouldBeTime /= now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 3. Preempt a transaction which is to occur at a later time than second one.
+    S_INITIAL := S;
+    S <= transport (S) after 15 ns;
+    S <= transport (not S) after 10 ns;     -- Should preempt first transaction.
+    -- a. Verify that the second transaction comes as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;  
+    if (ShouldBeTime /= now or S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    
+    -- b. Verify that the first transaction has been preempted.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S for 10 ns;
+    if (ShouldBeTime /= now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 4. Preempt multiple transactions.
+    S_INITIAL := S;
+    S <= transport (S) after 15 ns, (not S) after 30 ns;
+    S <= transport (not S) after 10 ns, (S) after 20 ns;
+    -- a. Verify that the second transactions come as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now or S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now or S /= S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+    
+    -- b. Verify that the first transactions have been preempted.
+    ShouldBeTime := NOW + 40 ns;
+    wait on S for 40 ns;
+    if (ShouldBeTime /= now) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s04b01x00p07n01i01348"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s04b01x00p07n01i01348 - The sequence of transactions is used to update the projected output waveform representing the current and future values of the driver associated with the signal assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p07n01i01348arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1349.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1349.vhd
new file mode 100644
index 0000000..e507c8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1349.vhd
@@ -0,0 +1,207 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1349.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p10n01i01349ent IS
+END c08s04b01x00p10n01i01349ent;
+
+ARCHITECTURE c08s04b01x00p10n01i01349arch OF c08s04b01x00p10n01i01349ent IS
+  -- Local signals.
+  signal S : BIT := '0';
+BEGIN
+  TESTING: PROCESS
+
+    -- local variables.
+    variable S_INITIAL : BIT;
+    variable ShouldBeTime : TIME;
+
+    variable k : integer := 0;
+
+  BEGIN
+    -- 0. Keep around the initial value of S.
+    S_INITIAL := S;
+
+    -- 1. When no preemption necessary, verify the results.  INERTIAL SAME AS TRANSPORT.
+    S <= (not S) after 10 ns, (S) after 20 ns;
+    -- a. Wait for first transaction.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+
+    -- b. Wait for second transaction.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+
+    -- 2. Preempt a transaction which is to occur at the same time as second one.
+    --    INERTIAL SAME AS TRANSPORT.
+    S_INITIAL := S;
+    S <= (S) after 10 ns;
+    S <= (not S) after 10 ns;     -- Should preempt first transaction.
+    -- a. Verify that the second transaction comes as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    
+    -- b. Verify that the first transaction has been preempted.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S for 10 ns;
+    if (ShouldBeTime /= now ) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 3. Preempt a transaction which is to occur at a later time than second one.
+    --   INERTIAL SAME AS TRANSPORT.
+    S_INITIAL := S;
+    S <= (S) after 15 ns;
+    S <= (not S) after 10 ns;     -- Should preempt first transaction.
+    -- a. Verify that the second transaction comes as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    
+    -- b. Verify that the first transaction has been preempted.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S for 10 ns;
+    if (ShouldBeTime /= now ) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 4. Preempt multiple transactions.  INERTIAL SAME AS TRANSPORT.
+    S_INITIAL := S;
+    S <= (S) after 15 ns, (not S) after 30 ns;
+    S <= (not S) after 10 ns, (S) after 20 ns;
+    -- a. Verify that the second transactions come as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+    
+    -- b. Verify that the first transactions have been preempted.
+    ShouldBeTime := NOW + 40 ns;
+    wait on S for 40 ns;
+    if (ShouldBeTime /= now ) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    
+    -- 5. Preempt transactions which occur before the second inertial assignment.
+    S_INITIAL := S;
+    S <= (S) after 5 ns;
+    S <= (not S) after 10 ns, (S) after 20 ns;
+    -- a. Verify that the second transactions come as expected.
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    ShouldBeTime := NOW + 10 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+    
+    -- b. Verify that the first transactions have been preempted.
+    ShouldBeTime := NOW + 40 ns;
+    wait on S for 40 ns;
+    if (ShouldBeTime /= now ) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+
+    -- 6. Don't preempt transactions which occur before the second inertial assignment.
+    S_INITIAL := S;
+    S <= (not S) after 5 ns;
+    S <= (not S) after 10 ns, (S) after 20 ns;
+    -- a. Verify that the first transaction was NOT preempted.
+    ShouldBeTime := NOW + 5 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= not S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = (not S_INITIAL));
+    ShouldBeTime := NOW + 15 ns;
+    wait on S;
+    if (ShouldBeTime /= now and S /= S_INITIAL) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+    assert (S = S_INITIAL);
+    
+    -- b. Verify that there are no more transactions.
+    ShouldBeTime := NOW + 40 ns;
+    wait on S for 40 ns;
+    if (ShouldBeTime /= now ) then
+      k := 1;
+    end if;
+    assert (ShouldBeTime = NOW);
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s04b01x00p10n01i01349"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s04b01x00p10n01i01349 - Interial signal assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p10n01i01349arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc135.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc135.vhd
new file mode 100644
index 0000000..ae8a585
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc135.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc135.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p08n01i00135ent IS
+END c04s03b02x02p08n01i00135ent;
+
+ARCHITECTURE c04s03b02x02p08n01i00135arch OF c04s03b02x02p08n01i00135ent IS
+  type    AT1 is array (INTEGER range <>, INTEGER range <>) of INTEGER;
+  subtype ST1 is AT1(1 to 2, 1 to 2);
+BEGIN
+  TESTING: PROCESS
+
+    procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
+    begin
+      if (P=ref) then
+        P := set;
+      end if;
+    end;
+    
+    variable V : ST1 := ((1, 2), (3, 4));
+
+  BEGIN
+    V := ((1, 2), (3, 4));
+    Proc1(  P(1,1) => V(2,2), P(1,2) => V(2,1),
+            P(2,1) => V(1,2), P(2,2) => V(1,1),
+            ref => ((4, 3), (2, 1)), set => ((9, 8), (7, 6)));  -- test here
+    assert V = ((6, 7), (8, 9)) report "FAIL: actual V didn't get set right";
+
+    assert NOT( V = ((6,7),(8,9)) )
+      report "***PASSED TEST: c04s03b02x02p08n01i00135"
+      severity NOTE;
+    assert ( V = ((6,7),(8,9)) )
+      report "***FAILED TEST: c04s03b02x02p08n01i00135 - Association element in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p08n01i00135arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1350.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1350.vhd
new file mode 100644
index 0000000..13d60f7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1350.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1350.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p10n01i01350ent IS
+END c08s04b01x00p10n01i01350ent;
+
+ARCHITECTURE c08s04b01x00p10n01i01350arch OF c08s04b01x00p10n01i01350ent IS
+  signal Add_bus : integer := 67;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Add_bus <= 1 after 5 ns, 6 after 10 ns, 12 after 19 ns;
+    Add_bus <= 6 after 12 ns, 20 after 19 ns, 6 after 21 ns;
+    wait;
+  END PROCESS TESTING;
+  
+  TEST : PROCESS(Add_bus)
+    variable ok : integer := 1;
+  BEGIN
+    if (now = 5 ns) then
+      if (Add_bus /= 67) then
+        ok := 0;
+      end if;
+    elsif (now = 10 ns) then
+      if (Add_bus /= 6) then
+        ok := 0;
+      end if;
+    elsif (now = 12 ns) then
+      if (Add_bus /= 6) then
+        ok := 0;
+      end if;
+    elsif (now = 19 ns) then
+      if (Add_bus /= 20) then
+        ok := 0;
+      end if;
+    end if;
+    if (now = 21 ns) then
+      assert NOT( Add_bus = 6 and ok = 1)
+        report "***PASSED TEST: c08s04b01x00p10n01i01350"
+        severity NOTE;
+      assert ( Add_bus = 6 and ok = 1)
+        report "***FAILED TEST: c08s04b01x00p10n01i01350 - Projected output waveform with initial delay test failed."
+        severity ERROR;
+    end if;
+  END PROCESS TEST;
+
+END c08s04b01x00p10n01i01350arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1354.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1354.vhd
new file mode 100644
index 0000000..2665c21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1354.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1354.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p02n01i01354ent IS
+END c08s05b00x00p02n01i01354ent;
+
+ARCHITECTURE c08s05b00x00p02n01i01354arch OF c08s05b00x00p02n01i01354ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : integer := 1;
+  BEGIN
+    a := 10; 
+    assert NOT(a = 10)
+      report "***PASSED TEST: c08s05b00x00p02n01i01354" 
+      severity NOTE;
+    assert (a = 10)
+      report "***FAILED TEST: c08s05b00x00p02n01i01354 - Target of a variable assignment can only be a name or an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p02n01i01354arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1356.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1356.vhd
new file mode 100644
index 0000000..1bccb66
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1356.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1356.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01356ent IS
+END c08s05b00x00p03n01i01356ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01356arch OF c08s05b00x00p03n01i01356ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type t1 is record
+                 ele1 : integer;
+                 ele2 : real;
+               end record;
+    variable f1: t1;
+    variable i : integer := 0;
+    variable r : real    := 0.0;
+  BEGIN
+    f1.ele1 := 1;
+    f1.ele2 := 2.3;
+    i := f1.ele1;
+    r := f1.ele2;
+    assert NOT((i=1) and (r=2.3)) 
+      report "***PASSED TEST: c08s05b00x00p03n01i01356" 
+      severity NOTE;
+    assert ((i=1) and (r=2.3)) 
+      report "***FAILED TEST: c08s05b00x00p03n01i01356 - Target and the expression on the right-hand side should have the same type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01356arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1359.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1359.vhd
new file mode 100644
index 0000000..b73b2f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1359.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1359.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01359ent IS
+END c08s05b00x00p03n01i01359ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01359arch OF c08s05b00x00p03n01i01359ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
+--
+  BEGIN
+    v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2) 
+      report "***PASSED TEST: c08s05b00x00p03n01i01359" 
+      severity NOTE;
+    assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2) 
+      report "***FAILED TEST: c08s05b00x00p03n01i01359 - Target of a variable assignment is not a variable." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01359arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc136.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc136.vhd
new file mode 100644
index 0000000..ce868ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc136.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc136.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p08n01i00136ent IS
+END c04s03b02x02p08n01i00136ent;
+
+ARCHITECTURE c04s03b02x02p08n01i00136arch OF c04s03b02x02p08n01i00136ent IS
+  type    AT0 is array (INTEGER range <>) of INTEGER;
+  subtype ST0 is AT0(1 to 2);
+  type    AT1 is array (INTEGER range <>) of ST0;
+  subtype ST1 is AT1(1 to 2);
+BEGIN
+  TESTING: PROCESS
+
+    procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
+    begin
+      if (P = ref) then
+        P := set;
+      end if;
+    end;
+    
+    variable V : ST1 := ((1, 2), (3, 4));
+    variable V11, V12, V21, V22 : INTEGER; 
+
+  BEGIN
+    V11 := 1;
+    V12 := 2;
+    V21 := 3;
+    V22 := 4;
+    Proc1(  P(1)(1) => V22, P(1)(2) => V21, P(2)(1) => V12, P(2)(2) => V11,
+            ref => ((4, 3), (2, 1)), set => ((9, 8), (7, 6))); -- test here
+    assert V11 = 6 report "FAIL: actual V11 didn't get set right";
+    assert V12 = 7 report "FAIL: actual V12 didn't get set right";
+    assert V21 = 8 report "FAIL: actual V21 didn't get set right";
+    assert V22 = 9 report "FAIL: actual V22 didn't get set right";   
+    assert NOT( V11=6 and V12=7 and V21=8 and V22=9 )
+      report "***PASSED TEST: c04s03b02x02p08n01i00136"
+      severity NOTE;
+    assert ( V11=6 and V12=7 and V21=8 and V22=9 )
+      report "***FAILED TEST: c04s03b02x02p08n01i00136 - Association element in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p08n01i00136arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1360.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1360.vhd
new file mode 100644
index 0000000..31173ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1360.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1360.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01360ent IS
+END c08s05b00x00p03n01i01360ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01360arch OF c08s05b00x00p03n01i01360ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr1 : st_arr1 :=c_st_arr1_1 ;
+--
+  BEGIN
+    v_st_arr1(st_arr1'Left) :=
+      c_st_arr1_2(st_arr1'Right) ;
+    assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01360" 
+      severity NOTE;
+    assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01360 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01360arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1361.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1361.vhd
new file mode 100644
index 0000000..63bed44
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1361.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1361.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01361ent IS
+END c08s05b00x00p03n01i01361ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01361arch OF c08s05b00x00p03n01i01361ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
+--
+  BEGIN
+    v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01361"
+      severity NOTE;
+    assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01361 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01361arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1362.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1362.vhd
new file mode 100644
index 0000000..d8547fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1362.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1362.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01362ent IS
+END c08s05b00x00p03n01i01362ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01362arch OF c08s05b00x00p03n01i01362ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
+--
+  BEGIN
+    v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
+      c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
+    assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01362" 
+      severity NOTE;
+    assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01362 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01362arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1363.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1363.vhd
new file mode 100644
index 0000000..837ec49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1363.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1363.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01363ent IS
+END c08s05b00x00p03n01i01363ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01363arch OF c08s05b00x00p03n01i01363ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
+--
+  BEGIN
+    v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2));
+    assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01363" 
+      severity NOTE;
+    assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01363 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01363arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1364.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1364.vhd
new file mode 100644
index 0000000..39683ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1364.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1364.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01364ent IS
+END c08s05b00x00p03n01i01364ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01364arch OF c08s05b00x00p03n01i01364ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
+--
+  BEGIN
+    v_st_arr1(st_arr1'Left) :=
+      c_st_arr1_2(st_arr1'Right) ;
+    assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01364" 
+      severity NOTE;
+    assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01364 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01364arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1365.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1365.vhd
new file mode 100644
index 0000000..b54e7b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1365.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1365.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01365ent IS
+END c08s05b00x00p03n01i01365ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01365arch OF c08s05b00x00p03n01i01365ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
+--
+  BEGIN
+    v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01365" 
+      severity NOTE;
+    assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01365 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01365arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1366.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1366.vhd
new file mode 100644
index 0000000..cad1786
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1366.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1366.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01366ent IS
+END c08s05b00x00p03n01i01366ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01366arch OF c08s05b00x00p03n01i01366ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
+--
+  BEGIN
+    v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
+      c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
+    assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01366" 
+      severity NOTE;
+    assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01366 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01366arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1367.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1367.vhd
new file mode 100644
index 0000000..015838f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1367.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1367.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01367ent IS
+END c08s05b00x00p03n01i01367ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01367arch OF c08s05b00x00p03n01i01367ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_rec3 : st_rec3 := c_st_rec3_1 ;
+--
+  BEGIN
+    v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01367" 
+      severity NOTE;
+    assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01367 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01367arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1368.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1368.vhd
new file mode 100644
index 0000000..21b561a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1368.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1368.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01368ent IS
+END c08s05b00x00p03n01i01368ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01368arch OF c08s05b00x00p03n01i01368ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
+--
+  BEGIN
+    v_st_arr1(st_arr1'Left) :=
+      c_st_arr1_2(st_arr1'Right) ;
+    assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01368"
+      severity NOTE;
+    assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01368 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01368arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1369.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1369.vhd
new file mode 100644
index 0000000..e1adcb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1369.vhd
@@ -0,0 +1,176 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1369.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01369ent IS
+END c08s05b00x00p03n01i01369ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01369arch OF c08s05b00x00p03n01i01369ent IS
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
+--
+  BEGIN
+    v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01369" 
+      severity NOTE;
+    assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) = c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01369 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01369arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc137.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc137.vhd
new file mode 100644
index 0000000..7f63631
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc137.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc137.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p08n01i00137ent IS
+END c04s03b02x02p08n01i00137ent;
+
+ARCHITECTURE c04s03b02x02p08n01i00137arch OF c04s03b02x02p08n01i00137ent IS
+  type    AT0 is array (INTEGER range <>) of INTEGER;
+  subtype ST0 is AT0(1 to 2);
+  type    AT1 is array (INTEGER range <>) of ST0;
+  subtype ST1 is AT1(1 to 2);
+BEGIN
+  TESTING: PROCESS
+
+    procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is      
+    begin
+      if (P = ref) then
+        P := set;
+      end if;
+    end;
+    
+    variable V    : ST1 := ((1, 2), (3, 4));
+    variable V1    : ST0;
+    variable V2    : ST0;
+
+  BEGIN
+    V1 := (1, 2);
+    V2 := (3, 4);
+    Proc1(  P(1) => V2, P(2) => V1,
+            ref => ((3, 4), (1, 2)), set => ((9, 8), (7, 6))); -- test here
+    assert V1 = (7, 6) report "FAIL: actual V1 didn't get set right";
+    assert V2 = (9, 8) report "FAIL: actual V2 didn't get set right";
+    assert NOT( V1=(7,6) and V2=(9,8) )
+      report "***PASSED TEST: c04s03b02x02p08n01i00137"
+      severity NOTE;
+    assert ( V1=(7,6) and V2=(9,8) )
+      report "***FAILED TEST: c04s03b02x02p08n01i00137 - Association element in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p08n01i00137arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1370.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1370.vhd
new file mode 100644
index 0000000..8f98d28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1370.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1370.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01370ent IS
+END c08s05b00x00p03n01i01370ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01370arch OF c08s05b00x00p03n01i01370ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr3 : st_arr3 := c_st_arr3_1 ;
+--
+  BEGIN
+    v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
+      c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
+    assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01370"
+      severity NOTE;
+    assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01370 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01370arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1371.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1371.vhd
new file mode 100644
index 0000000..f8a4f9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1371.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1371.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01371ent IS
+END c08s05b00x00p03n01i01371ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01371arch OF c08s05b00x00p03n01i01371ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_rec3 : st_rec3 :=c_st_rec3_1 ;
+--
+  BEGIN
+    v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_rec3_2.f3(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01371" 
+      severity NOTE;
+    assert (v_st_rec3.f3(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01371 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01371arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1372.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1372.vhd
new file mode 100644
index 0000000..c9f6073
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1372.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1372.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01372ent IS
+END c08s05b00x00p03n01i01372ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01372arch OF c08s05b00x00p03n01i01372ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
+--
+  BEGIN
+    v_st_arr1(st_arr1'Left) :=
+      c_st_arr1_2(st_arr1'Right) ;
+    assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01372" 
+      severity NOTE;
+    assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
+      report "***FAILED TEST:c08s05b00x00p03n01i01372 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01372arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1373.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1373.vhd
new file mode 100644
index 0000000..2819a3b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1373.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1373.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01373ent IS
+END c08s05b00x00p03n01i01373ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01373arch OF c08s05b00x00p03n01i01373ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr2 : st_arr2 := c_st_arr2_1 ;
+--
+  BEGIN
+    v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) :=
+      c_st_arr2_2(st_arr2'Right(1),st_arr2'Right(2)) ;
+    assert NOT(v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01373"
+      severity NOTE;
+    assert (v_st_arr2(st_arr2'Left(1),st_arr2'Left(2)) =c_st_arr1_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01373 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01373arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1374.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1374.vhd
new file mode 100644
index 0000000..2bccfd0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1374.vhd
@@ -0,0 +1,177 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1374.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01374ent IS
+END c08s05b00x00p03n01i01374ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01374arch OF c08s05b00x00p03n01i01374ent IS
+
+BEGIN
+  TESTING: PROCESS
+--
+-- Define constants for package
+--
+    constant lowb : integer := 1 ;
+    constant highb : integer := 5 ;
+    constant lowb_i2 : integer := 0 ;
+    constant highb_i2 : integer := 1000 ;
+    constant lowb_p : integer := -100 ;
+    constant highb_p : integer := 1000 ;
+    constant lowb_r : real := 0.0 ;
+    constant highb_r : real := 1000.0 ;
+    constant lowb_r2 : real := 8.0 ;
+    constant highb_r2 : real := 80.0 ;
+    
+    constant c_boolean_1 : boolean := false ;
+    constant c_boolean_2 : boolean := true ;
+--
+-- bit
+    constant c_bit_1 : bit := '0' ;
+    constant c_bit_2 : bit := '1' ;
+    
+-- severity_level
+    constant c_severity_level_1 : severity_level := NOTE ;
+    constant c_severity_level_2 : severity_level := WARNING ;
+--
+-- character
+    constant c_character_1 : character := 'A' ;
+    constant c_character_2 : character := 'a' ;
+    
+-- integer types
+-- predefined
+    constant c_integer_1 : integer := lowb ;
+    constant c_integer_2 : integer := highb ;
+--
+-- user defined integer type
+    type     t_int1 is range 0 to 100 ;
+    constant c_t_int1_1 : t_int1 := 0 ;
+    constant c_t_int1_2 : t_int1 := 10 ;
+    subtype  st_int1 is t_int1 range 8 to 60 ;
+    constant c_st_int1_1 : st_int1 := 8 ;
+    constant c_st_int1_2 : st_int1 := 9 ;
+--
+-- physical types
+-- predefined
+    constant c_time_1 : time := 1 ns ;
+    constant c_time_2 : time := 2 ns ;
+--
+--
+-- floating point types
+-- predefined
+    constant c_real_1 : real := 0.0 ;
+    constant c_real_2 : real := 1.0 ;
+--
+-- simple record
+    type     t_rec1 is record
+                         f1 : integer range lowb_i2 to highb_i2 ;
+                         f2 : time ;
+                         f3 : boolean ;
+                         f4 : real ;
+                       end record ;
+    constant c_t_rec1_1 : t_rec1 :=
+      (c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
+    constant c_t_rec1_2 : t_rec1 :=
+      (c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
+    subtype  st_rec1 is t_rec1 ;
+    constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
+    constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
+--
+-- more complex record
+    type     t_rec2 is record
+                         f1 : boolean ;
+                         f2 : st_rec1 ;
+                         f3 : time ;
+                       end record ;
+    constant c_t_rec2_1 : t_rec2 :=
+      (c_boolean_1, c_st_rec1_1, c_time_1) ;
+    constant c_t_rec2_2 : t_rec2 :=
+      (c_boolean_2, c_st_rec1_2, c_time_2) ;
+    subtype  st_rec2 is t_rec2 ;
+    constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
+    constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
+--
+-- simple array
+    type     t_arr1 is array (integer range <>) of st_int1 ;
+    subtype  t_arr1_range1 is integer range lowb to highb ;
+    subtype  st_arr1 is t_arr1 (t_arr1_range1) ;
+    constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
+    constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
+    constant c_t_arr1_1  : st_arr1 := c_st_arr1_1 ;
+    constant c_t_arr1_2  : st_arr1 := c_st_arr1_2 ;
+--
+-- more complex array
+    type     t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
+    subtype  t_arr2_range1 is integer range lowb to highb ;
+    subtype  t_arr2_range2 is boolean range false to true ;
+    subtype  st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
+    constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
+    constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
+    constant c_t_arr2_1  : st_arr2 := c_st_arr2_1 ;
+    constant c_t_arr2_2  : st_arr2 := c_st_arr2_2 ;
+--
+-- most complex record
+    type     t_rec3 is record
+                         f1 : boolean ;
+                         f2 : st_rec2 ;
+                         f3 : st_arr2 ;
+                       end record ;
+    constant c_t_rec3_1 : t_rec3 :=
+      (c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
+    constant c_t_rec3_2 : t_rec3 :=
+      (c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
+    subtype  st_rec3 is t_rec3 ;
+    constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
+    constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
+--
+-- most complex array
+    type     t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
+    subtype  t_arr3_range1 is integer range lowb to highb ;
+    subtype  t_arr3_range2 is boolean range true downto false ;
+    subtype  st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
+    constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
+    constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
+    constant c_t_arr3_1  : st_arr3 := c_st_arr3_1 ;
+    constant c_t_arr3_2  : st_arr3 := c_st_arr3_2 ;
+--
+    variable v_st_arr3 : st_arr3 :=c_st_arr3_1 ;
+--
+  BEGIN
+    v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) :=
+      c_st_arr3_2(st_arr3'Right(1),st_arr3'Right(2)) ;
+    assert NOT(v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***PASSED TEST: c08s05b00x00p03n01i01374" 
+      severity NOTE;
+    assert (v_st_arr3(st_arr3'Left(1),st_arr3'Left(2)) = c_st_rec3_2)
+      report "***FAILED TEST: c08s05b00x00p03n01i01374 - The types of the variable and the assigned variable must match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01374arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1375.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1375.vhd
new file mode 100644
index 0000000..d56afd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1375.vhd
@@ -0,0 +1,120 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1375.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s05b00x00p03n01i01375pkg is
+
+  -- Type declarations.
+  subtype     BV2  is BIT_VECTOR( 0 to 1 );
+  subtype     CH2  is STRING( 1 to 2 );
+
+  -- Constant declarations.
+  constant BVC  : BV2 := B"00";
+  constant CHC  : CH2 := "bb";
+
+  -- Function returns BV2.
+  function  returnBV2 return BV2;
+
+  -- Function returns CH2.
+  function  returnCH2 return CH2;
+  
+end c08s05b00x00p03n01i01375pkg;
+
+package body c08s05b00x00p03n01i01375pkg is
+  
+  -- Function returns BV2.
+  function  returnBV2 return BV2 is
+  begin
+    return ( BVC );
+  end returnBV2;
+  
+  -- Function returns CH2.
+  function  returnCH2 return CH2 is
+  begin
+    return( CHC );
+  end returnCH2;
+  
+end c08s05b00x00p03n01i01375pkg;
+
+use work.c08s05b00x00p03n01i01375pkg.all;
+ENTITY c08s05b00x00p03n01i01375ent IS
+END c08s05b00x00p03n01i01375ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01375arch OF c08s05b00x00p03n01i01375ent IS
+
+BEGIN
+  TESTING: PROCESS
+    
+    -- local variables
+    variable BITV     : BV2 := B"11";
+    variable STRV     : CH2 := "ab";
+    
+    variable S, T        : BIT;
+    variable S1, T1        : BIT;
+    variable S11, T11        : BIT;
+    variable C1, C2      : CHARACTER;
+    variable C11, C22      : CHARACTER;
+    variable C111, C222      : CHARACTER;
+    
+  BEGIN
+    -- Assign with a variable as the expression.
+    ( S, T )  := BITV;
+    
+    ( C1,C2 ) := STRV;
+    
+    -- Assign with a function return value.
+    ( S1, T1 )  := returnBV2;
+    
+    ( C11,C22 ) := returnCH2;
+    
+    -- Assign with a qualified expression.
+    ( S11, T11 )  := BV2'( '0', '1' );
+    
+    ( C111,C222 ) := CH2'( 'c', 'c' );
+
+    assert NOT(((S = BITV( 0 )) and (T = BITV( 1 )))
+               and ((C1 = STRV( 1 )) and (C2 = STRV( 2 )))
+               and ((S1 = BVC( 0 )) and (T1 = BVC( 1 )))
+               and ((C11 = CHC( 1 )) and (C22 = CHC( 2 )))
+               and ((S11 = '0') and (T11 = '1'))
+               and ((C111 = 'c') and (C222 = 'c')))
+      report "***PASSED TEST: c08s05b00x00p03n01i01375" 
+      severity NOTE;
+    assert (((S = BITV( 0 )) and (T = BITV( 1 )))
+            and ((C1 = STRV( 1 )) and (C2 = STRV( 2 )))
+            and ((S1 = BVC( 0 )) and (T1 = BVC( 1 )))
+            and ((C11 = CHC( 1 )) and (C22 = CHC( 2 )))
+            and ((S11 = '0') and (T11 = '1'))
+            and ((C111 = 'c') and (C222 = 'c')))
+      report "***FAILED TEST: c08s05b00x00p03n01i01375 - Legal aggregate variable assignment fail." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01375arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc138.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc138.vhd
new file mode 100644
index 0000000..d1294d8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc138.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc138.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p09n01i00138ent IS
+  CONSTANT a,b    : INTEGER := 2;
+  CONSTANT c       : INTEGER := 3; 
+
+  PROCEDURE addup (i1,i2,i3:IN INTEGER:=a**b+c-a;SIGNAL i4:OUT INTEGER) IS
+  BEGIN
+    i4 <= (i1+i2+i3);
+  END;
+END c04s03b02x02p09n01i00138ent;
+
+ARCHITECTURE c04s03b02x02p09n01i00138arch OF c04s03b02x02p09n01i00138ent IS
+  SIGNAL a1 : INTEGER := 57;
+  SIGNAL a2 : INTEGER := 68;
+  SIGNAL a3 : INTEGER := 77;
+  SIGNAL a11: INTEGER := 77;
+  SIGNAL a12: INTEGER := 77;
+  SIGNAL a13: INTEGER := 77;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    addup(i2=>a1,i1=>a1,i4=>a1);
+    WAIT FOR 1 ns;
+    IF (a1 = 119) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual twice plus default" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(i3=>a2,i1=>a2,i2=>a3,i4=>a11);
+    WAIT FOR 1 ns;
+    IF (a11 = 213) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual twice" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(i3=>a3,i2=>a3,i1=>a3,i4=>a12);
+    WAIT FOR 1 ns;
+    IF (a12 = 231) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual thrice" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(i4=>a13);
+    WAIT FOR 1 ns;
+    IF (a13 = 15) THEN
+      ASSERT false REPORT "PASS: All parameters defaulted to same value" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    wait for 5 ns;
+    assert NOT(   a1 = 119   and
+                  a11= 213   and
+                  a12= 231   and
+                  a13= 15      )   
+      report "***PASSED TEST: c04s03b02x02p09n01i00138"
+      severity NOTE;
+    assert (   a1 = 119   and
+               a11= 213   and
+               a12= 231   and
+               a13= 15      )   
+      report "***FAILED TEST: c04s03b02x02p09n01i00138 - Named association where 2 or more named formal signals are associated with the same actual signal test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p09n01i00138arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1386.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1386.vhd
new file mode 100644
index 0000000..3aabe19
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1386.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1386.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n02i01386ent IS
+END c08s05b00x00p03n02i01386ent;
+
+ARCHITECTURE c08s05b00x00p03n02i01386arch OF c08s05b00x00p03n02i01386ent IS
+
+BEGIN
+  TESTING : PROCESS   
+
+    variable radix : natural := 10;
+    variable v1 : natural;
+
+    type r_array_index_type is range 1 to 3;
+    type r_array_type is array (r_array_index_type) of natural;
+    variable r_array : r_array_type;
+
+    procedure set_radix ( constant radix : natural
+                          ) is
+    begin
+      TESTING.radix := radix;             -- test selected name as target
+    end set_radix;
+
+  BEGIN
+    v1 := 8;   --test simple name as target
+    assert v1 = 8
+      report "Simple name as target failed."
+      severity note ;
+
+    set_radix (v1);
+    assert radix = v1
+      report "Selected name as target failed."
+      severity note ;
+
+    r_array ( 3 to 3 ) := (3 => 10);          -- test slice name as target
+    assert r_array ( 3 ) = 10
+      report "Slice name as target failed."
+      severity note ;
+
+    r_array ( 2 ) := 8;               -- test indexed name as target
+    assert r_array ( 2 ) = 8
+      report "Indexed name as target failed."
+      severity note ;
+
+    assert NOT(v1=8 and r_array(3)=10 and r_array(2)=8) 
+      report "***PASSED TEST: c08s05b00x00p03n02i01386" 
+      severity NOTE;
+    assert (v1=8 and r_array(3)=10 and r_array(2)=8) 
+      report "***FAILED TEST: c08s05b00x00p03n02i01386 - The name of thetarget of the variable assignment statement must denote a variable"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n02i01386arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1387.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1387.vhd
new file mode 100644
index 0000000..a38c9d6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1387.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1387.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n01i01387ent IS
+END c08s05b00x00p04n01i01387ent;
+
+ARCHITECTURE c08s05b00x00p04n01i01387arch OF c08s05b00x00p04n01i01387ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable NUM1 : BIT_VECTOR(0 to 3) := ('0','0','0','0');
+  BEGIN
+    NUM1 := ('0', '0', '1', '1');   
+    assert NOT( NUM1(0) = '0' and NUM1(1) = '0' and NUM1(2) = '1' and NUM1(3) = '1' ) 
+      report "***PASSED TEST: c08s05b00x00p04n01i01387"
+      severity NOTE;
+    assert ( NUM1(0) = '0' and NUM1(1) = '0' and NUM1(2) = '1' and NUM1(3) = '1' ) 
+      report "***FAILED TEST: c08s05b00x00p04n01i01387 - Assigning to an aggregate variable"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n01i01387arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1389.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1389.vhd
new file mode 100644
index 0000000..d2044c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1389.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1389.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n02i01389ent IS
+END c08s05b00x00p04n02i01389ent;
+
+ARCHITECTURE c08s05b00x00p04n02i01389arch OF c08s05b00x00p04n02i01389ent IS
+  subtype C2 is BIT_VECTOR(1 to 2);
+BEGIN
+  TESTING: PROCESS
+    variable S1 : BIT;
+    variable T1 : BIT;
+    variable BIT2 : C2 := B"11";
+  BEGIN
+    (S1, T1) := BIT2;
+    assert NOT((S1 = '1') and (T1 = '1')) 
+      report "***PASSED TEST: c08s05b00x00p04n02i01389" 
+      severity NOTE;
+    assert ((S1 = '1') and (T1 = '1')) 
+      report "***FAILED TEST: c08s05b00x00p04n02i01389 - Base types of the expression on the right hand side is the same as the base type of the aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n02i01389arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1390.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1390.vhd
new file mode 100644
index 0000000..900de44
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1390.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1390.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n03i01390ent IS
+END c08s05b00x00p04n03i01390ent;
+
+ARCHITECTURE c08s05b00x00p04n03i01390arch OF c08s05b00x00p04n03i01390ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A : integer := 0;
+    variable B : integer := 0;
+    variable C : integer := 1;
+    variable D : integer := 2;
+    type array_of_ints is array (Positive range <>) of integer;
+  BEGIN
+    (A,B) := array_of_ints'(C,D);
+    assert NOT( (A=1) and (B=2) )
+      report "***PASSED TEST: c08s05b00x00p04n03i01390"
+      severity NOTE;
+    assert ( (A=1) and (B=2) )
+      report "***FAILED TEST: c08s05b00x00p04n03i01390 - Each element association of the aggregate must be a locally static name that denotes a variable"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n03i01390arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1392.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1392.vhd
new file mode 100644
index 0000000..74f1c6e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1392.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1392.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n04i01392ent IS
+END c08s05b00x00p04n04i01392ent;
+
+ARCHITECTURE c08s05b00x00p04n04i01392arch OF c08s05b00x00p04n04i01392ent IS
+--
+  TYPE rec_list IS RECORD
+                     a,b,c,d : INTEGER;
+                   END RECORD;
+
+BEGIN
+  TESTING: PROCESS
+--
+    VARIABLE rec1 : rec_list := (1,2,3,4);
+    VARIABLE rec2 : rec_list := (1,2,3,4);
+    VARIABLE rec3 : rec_list := (1,2,3,4);
+    VARIABLE rec4 : rec_list := (1,2,3,4);
+    VARIABLE rec5 : rec_list := (1,2,3,4);
+    VARIABLE rec6 : rec_list := (1,2,3,4);
+
+--
+  BEGIN
+--
+    rec1 := ( rec1.d, rec1.c, rec1.b, rec1.a);
+--
+    ( rec2.d, rec2.c, rec2.b, rec2.a) := rec2;
+--
+    (rec3.d, rec3.c, rec3.b, rec3.a)
+      :=  rec_list' (rec3.c, rec3.d, rec3.a, rec3.b);
+--
+    (rec4.a, rec4.b, rec4.c, rec4.d)
+      :=  rec_list' ( d=>rec4.a, c=>rec4.b, b=>rec4.c, a=>rec4.d);
+--
+    ( d=>rec5.a, c=>rec5.b, b=>rec5.c, a=>rec5.d) := rec5;
+--
+    (rec6.d, rec6.c, rec6.b, rec6.a)
+      :=  rec_list' ( d=>rec6.a, c=>rec6.b, b=>rec6.c, a=>rec6.d);
+    
+--
+    ASSERT NOT(   rec1 = (4,3,2,1)   and  
+                  rec2 = (4,3,2,1)    and 
+                  rec3 = (2,1,4,3)    and 
+                  rec4 = (4,3,2,1)    and 
+                  rec5 = (4,3,2,1)    and 
+                  rec6 = (1,2,3,4)) 
+      report "***PASSED TEST: c08s05b00x00p04n04i01392"
+      severity NOTE;
+    ASSERT (   rec1 = (4,3,2,1)   and  
+               rec2 = (4,3,2,1)    and 
+               rec3 = (2,1,4,3)    and 
+               rec4 = (4,3,2,1)    and 
+               rec5 = (4,3,2,1)    and 
+               rec6 = (1,2,3,4)) 
+      report "***FAILED TEST: c08s05b00x00p04n04i01392 - Record aggregates type variable assignment fail."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n04i01392arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1393.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1393.vhd
new file mode 100644
index 0000000..854a578
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1393.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1393.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n01i01393ent IS
+END c08s05b00x00p04n01i01393ent;
+
+ARCHITECTURE c08s05b00x00p04n01i01393arch OF c08s05b00x00p04n01i01393ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type RT is
+      record
+        a : CHARACTER;
+        b : CHARACTER;
+      end record;
+    variable v1, v2    : CHARACTER := NUL;
+    variable rv       : RT := ('1', '2');
+  BEGIN
+    assert v1 = NUL;
+    assert v2 = NUL;
+    (v1, v2) := rv;
+    assert v1 = '1';
+    assert v2 = '2';
+    wait for 1 ns;
+    assert NOT( v1 = '1' and v2 = '2' )
+      report "***PASSED TEST: c08s05b00x00p04n01i01393"
+      severity NOTE;
+    assert ( v1 = '1' and v2 = '2' )
+      report "***FAILED TEST: c08s05b00x00p04n01i01393 - Aggregate (record type) assignment for variable test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n01i01393arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1394.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1394.vhd
new file mode 100644
index 0000000..515babb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1394.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1394.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n01i01394ent IS
+END c08s05b00x00p04n01i01394ent;
+
+ARCHITECTURE c08s05b00x00p04n01i01394arch OF c08s05b00x00p04n01i01394ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type AT2 is array (0 to 1, 0 to 1) of CHARACTER;
+    type AT1 is array (0 to 1) of CHARACTER;
+    variable v1, v2    : AT1;
+    variable av       : AT2 := (('a', 'b'), ('c', 'd'));
+  BEGIN
+    assert v1 = (NUL, NUL);
+    assert v2 = (NUL, NUL);
+    v1(0) := av(0,0);
+    v1(1) := av(0,1);
+    v2(0) := av(1,0);
+    v2(1) := av(1,1);
+    assert v1 = ('a', 'b');
+    assert v2 = ('c', 'd');
+    wait for 1 ns;
+    assert NOT( v1 = ('a','b') and v2 = ('c', 'd') )
+      report "***PASSED TEST: c08s05b00x00p04n01i01394"
+      severity NOTE;
+    assert ( v1 = ('a','b') and v2 = ('c', 'd') )
+      report "***FAILED TEST: c08s05b00x00p04n01i01394 - Aggregate (2-d array type) assignment for variable test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n01i01394arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc14.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc14.vhd
new file mode 100644
index 0000000..b1d2968
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc14.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc14.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p03n01i00014ent IS
+END c04s02b00x00p03n01i00014ent;
+
+ARCHITECTURE c04s02b00x00p03n01i00014arch OF c04s02b00x00p03n01i00014ent IS
+  subtype sub1 is integer;
+  subtype sub2 is sub1;    -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+    variable k : sub2 := 0;
+  BEGIN
+    assert NOT( k=0 )
+      report "***PASSED TEST: c04s02b00x00p03n01i00014"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c04s02b00x00p03n01i00014 - Subtype indication syntactic test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p03n01i00014arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1403.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1403.vhd
new file mode 100644
index 0000000..2bd767b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1403.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1403.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p06n01i01403ent IS
+END c08s05b00x00p06n01i01403ent;
+
+ARCHITECTURE c08s05b00x00p06n01i01403arch OF c08s05b00x00p06n01i01403ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    T    : INTEGER := 1;
+    subtype    ST    is BIT_VECTOR(T to 10);
+    variable    OK    : BIT_VECTOR(T+1 to 11);
+    variable    ILL    : BIT_VECTOR(T to 11);
+
+    variable    V    : ST;
+  BEGIN
+    V := OK;
+    assert NOT(V = "0000000000") 
+      report "***PASSED TEST: c08s05b00x00p06n01i01403" 
+      severity NOTE;
+    assert (V = "0000000000") 
+      report "***FAILED TEST: c08s05b00x00p06n01i01403 - Variable assignment scalar subtype check test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p06n01i01403arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1405.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1405.vhd
new file mode 100644
index 0000000..31e3d69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1405.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1405.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p07n01i01405ent IS
+END c08s05b00x00p07n01i01405ent;
+
+ARCHITECTURE c08s05b00x00p07n01i01405arch OF c08s05b00x00p07n01i01405ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable S1 : BIT;
+    variable T1 : BIT;
+    variable T2 : BIT;
+    variable B2 : BIT_VECTOR(0 to 2) := B"111";
+  BEGIN
+    (S1, T1, T2) := B2;
+    assert NOT( (S1='1') and (T1='1') and (T2='1') )
+      report "***PASSED TEST: c08s05b00x00p07n01i01405"
+      severity NOTE;
+    assert ( (S1='1') and (T1='1') and (T2='1') )
+      report "***FAILED TEST: c08s05b00x00p07n01i01405 - Subtypes of the subelements of the right-hand side and that of the names in the aggregate should match"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p07n01i01405arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1409.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1409.vhd
new file mode 100644
index 0000000..d980782
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1409.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1409.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01409ent IS
+END c08s05b01x00p01n01i01409ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01409arch OF c08s05b01x00p01n01i01409ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type      A1 is array (positive range <>) of integer;
+    type      A2 is array (0 to 10) of A1 (4 downto 1);
+    variable   XC : A2; 
+  BEGIN
+    XC (4) (1) := 1;
+    assert NOT(XC(4)(1) = 1) 
+      report "***PASSED TEST: c08s05b01x00p01n01i01409" 
+      severity NOTE;
+    assert (XC(4)(1) = 1) 
+      report "***FAILED TEST: c08s05b01x00p01n01i01409 - The types of the right hand side and left hand side are the same and for each element of the array variable there is a matching element on the right hand side." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01409arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc141.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc141.vhd
new file mode 100644
index 0000000..e42d57f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc141.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc141.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p09n01i00141ent IS
+  FUNCTION addup (i1,i2,i3:INTEGER:=5) RETURN INTEGER IS
+  BEGIN
+    RETURN (i1+i2+i3);
+  END;
+END c04s03b02x02p09n01i00141ent;
+
+ARCHITECTURE c04s03b02x02p09n01i00141arch OF c04s03b02x02p09n01i00141ent IS
+  SIGNAL a1 : INTEGER := 57;
+  SIGNAL a2 : INTEGER := 68;
+  SIGNAL a3 : INTEGER := 77;
+  SIGNAL i1 : INTEGER := 0;
+  SIGNAL i2 : INTEGER := 0;
+  SIGNAL i3 : INTEGER := 0;
+  SIGNAL i4 : INTEGER := 0;
+  SIGNAL i5 : INTEGER := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    i1 <= addup(i2=>a1,i1=>a1);
+    WAIT FOR 1 ns;
+    IF (i1 = 119) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual twice plus default" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    i2 <= addup(i3=>a2,i1=>a2,i2=>a1);
+    WAIT FOR 1 ns;
+    IF (i2 = 193) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual twice" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    i3 <= addup(i3=>a3,i2=>a3,i1=>a3);
+    WAIT FOR 1 ns;
+    IF (i3 = 231) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual thrice" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    i4 <= addup;
+    WAIT FOR 1 ns;
+    IF (i4 = 15) THEN
+      ASSERT false REPORT "PASS: All parameters defaulted to same value" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    i5 <= addup(addup(addup,addup,addup),addup(addup,addup,addup),addup(addup,addup,addup));
+    WAIT FOR 1 ns;
+    IF (i5 = 135) THEN
+      ASSERT false REPORT "PASS: All parameters defaulted to same value recursively" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY error;
+    END IF;
+    wait for 5 ns;
+    assert NOT(   i1 = 119   and
+                  i2 = 193   and
+                  i3 = 231   and
+                  i4 = 15      and
+                  i5 = 135   ) 
+      report "***PASSED TEST: c04s03b02x02p09n01i00141"
+      severity NOTE;
+    assert (   i1 = 119   and
+               i2 = 193   and
+               i3 = 231   and
+               i4 = 15      and
+               i5 = 135   ) 
+      report "***FAILED TEST: c04s03b02x02p09n01i00141 - Named association on function call test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p09n01i00141arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1410.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1410.vhd
new file mode 100644
index 0000000..9a07c6b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1410.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1410.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01410ent IS
+END c08s05b01x00p01n01i01410ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01410arch OF c08s05b01x00p01n01i01410ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type      BIT_VECTOR is array (natural range <>) of BIT;
+    variable   NUM1 : BIT_VECTOR(0 to 1); 
+    variable   NUM2 : BIT_VECTOR(0 to 1) := ('1','1'); 
+  BEGIN
+    NUM1 := NUM2;
+    assert NOT((NUM1(0)='1') and(NUM1(1)='1')) 
+      report "***PASSED TEST: c08s05b01x00p01n01i01410" 
+      severity NOTE;
+    assert ((NUM1(0)='1') and(NUM1(1)='1')) 
+      report "***FAILED TEST: c08s05b01x00p01n01i01410 - The types of the igth hand side and left hand side are the same and for each element of the array variable there is a matching element on the right hand side." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01410arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1412.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1412.vhd
new file mode 100644
index 0000000..434cacb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1412.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1412.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01412ent IS
+END c08s05b01x00p01n01i01412ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01412arch OF c08s05b01x00p01n01i01412ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        x : integer;
+        y : real;
+        z : boolean;
+        b : bit;
+      end record;
+    type array_type is array (1 to 10) of rec_type;
+    variable   v1 : array_type;   
+  BEGIN
+    v1 (1).x := 12;
+    v1 (1).y := 1.2;
+    v1 (1).z := true;
+    v1 (1).b := bit'('0');
+    assert NOT( v1(1).x = 12 and v1(1).y = 1.2 and v1(1).z = true and v1(1).b = '0') 
+      report "***PASSED TEST: c08s05b01x00p01n01i01412" 
+      severity NOTE;
+    assert ( v1(1).x = 12 and v1(1).y = 1.2 and v1(1).z = true and v1(1).b = '0') 
+      report "***FAILED TEST: c08s05b01x00p01n01i01412 - Each element of the array variable there is a matching element on the right hand side." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01412arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1413.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1413.vhd
new file mode 100644
index 0000000..e23a5c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1413.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1413.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01413ent IS
+END c08s05b01x00p01n01i01413ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01413arch OF c08s05b01x00p01n01i01413ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (i : integer) return real is
+    begin
+      return (1.0);
+    end;
+    type rec_type is
+      record
+        x : integer;
+        y : real;
+        z : boolean;
+        b : bit;
+      end record;
+    type array_type is array (1 to 10) of rec_type;
+    variable   v1 : array_type;   
+    constant    i  : integer := 20;
+  BEGIN
+    v1 (1).x := i;
+    v1 (1).y := check(i);
+    v1 (1).z := true;
+    v1 (1).b := bit'('0');
+    assert NOT(v1(1).x=20 and v1(1).y=1.0 and v1(1).z=true and v1(1).b='0') 
+      report "***PASSED TEST: c08s05b01x00p01n01i01413" 
+      severity NOTE;
+    assert (v1(1).x=20 and v1(1).y=1.0 and v1(1).z=true and v1(1).b='0') 
+      report "***FAILED TEST: c08s05b01x00p01n01i01413 Each element of the array variable there is a matching element on the right hand side." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01413arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1414.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1414.vhd
new file mode 100644
index 0000000..0a76d48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1414.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1414.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01414ent IS
+END c08s05b01x00p01n01i01414ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01414arch OF c08s05b01x00p01n01i01414ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_type is array (1 to 10) of integer;
+    variable   v1 : array_type;   
+  BEGIN
+    v1 (1) := integer'(12);
+    assert NOT(v1(1)=12) 
+      report "***PASSED TEST: c08s05b01x00p01n01i01414" 
+      severity NOTE;
+    assert (v1(1)=12) 
+      report "***FAILED TEST: c08s05b01x00p01n01i01414 - Each element of the array variable there is a matching element on the right hand side." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01414arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1421.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1421.vhd
new file mode 100644
index 0000000..618cb3a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1421.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1421.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p02n01i01421ent IS
+END c08s06b00x00p02n01i01421ent;
+
+ARCHITECTURE c08s06b00x00p02n01i01421arch OF c08s06b00x00p02n01i01421ent IS
+
+  procedure assert_msg  is
+  begin
+    assert FALSE
+      report "***PASSED TEST: c08s06b00x00p02n01i01421" 
+      severity NOTE;
+  end assert_msg;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert_msg;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p02n01i01421arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1422.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1422.vhd
new file mode 100644
index 0000000..c3b3408
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1422.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1422.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p04n01i01422ent IS
+END c08s06b00x00p04n01i01422ent;
+
+ARCHITECTURE c08s06b00x00p04n01i01422arch OF c08s06b00x00p04n01i01422ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    procedure proc1(
+      constant p : in    STRING;
+      variable l : out    INTEGER
+      ) is
+    begin
+      l := P'LENGTH;
+    end;
+
+    constant C : STRING := "Testing";
+    variable l : INTEGER := c'LENGTH - 1;
+
+  BEGIN
+    assert l /= c'LENGTH;
+    proc1(c, l);
+    assert NOT(l = c'LENGTH)
+      report "***PASSED TEST: c08s06b00x00p04n01i01422" 
+      severity NOTE;
+    assert (l = c'LENGTH)
+      report "***FAILED TEST: c08s06b00x00p04n01i01422 - Sequential procedure call test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p04n01i01422arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1423.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1423.vhd
new file mode 100644
index 0000000..b48aac1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1423.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1423.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p05n01i01423ent IS
+END c08s06b00x00p05n01i01423ent;
+
+ARCHITECTURE c08s06b00x00p05n01i01423arch OF c08s06b00x00p05n01i01423ent IS
+  procedure check (signal x   : in  integer;
+                   signal kkk : out integer ) is
+  begin
+    if (x = 0) then
+      kkk <= 5;
+      wait for 1 ns;
+    end if;
+  end check;
+  signal k  : integer := 0;
+  signal kk  : integer := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    check (k,kk);
+    assert NOT(kk = 5)
+      report "***PASSED TEST: c08s06b00x00p05n01i01423"
+      severity NOTE;
+    assert (kk = 5)
+      report "***FAILED TEST: c08s06b00x00p05n01i01423 - No actual parmeter is required for a formal parmeter with a default expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p05n01i01423arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1424.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1424.vhd
new file mode 100644
index 0000000..4ce750d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1424.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1424.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p05n01i01424ent IS
+END c08s06b00x00p05n01i01424ent;
+
+ARCHITECTURE c08s06b00x00p05n01i01424arch OF c08s06b00x00p05n01i01424ent IS
+
+  procedure copy_into ( variable dest : out integer;
+                        variable src  : in  integer := 0   ) is
+    --
+    -- This procedure copies the value of the second argument
+    -- into the first argument.
+    --
+  begin
+    dest := src;
+  end copy_into;
+
+BEGIN
+  TESTING : PROCESS
+    variable   v1 : integer := 0;
+  BEGIN
+
+    --
+    -- Try it with only one parameter
+    --
+    copy_into(v1);            -- v1 <- (0)
+    assert NOT(v1 = 0)
+      report "***PASSED TEST: c08s06b00x00p05n01i01424"
+      severity NOTE;
+    assert (v1 = 0)
+      report "***FAILED TEST: c08s06b00x00p05n01i01424 - Procedure call without an actual parameter part is permitted." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p05n01i01424arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1425.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1425.vhd
new file mode 100644
index 0000000..19cfc38
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1425.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1425.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p05n01i01425ent IS
+END c08s06b00x00p05n01i01425ent;
+
+ARCHITECTURE c08s06b00x00p05n01i01425arch OF c08s06b00x00p05n01i01425ent IS
+
+  procedure assert_same_int ( variable v1, v2 : in integer := 0 ) is
+    --
+    -- This procedure compares the value of the first argument
+    -- into the second argument and prints an assertion message
+    -- if they are the same.
+    --
+  begin
+    assert NOT(v1 = v2)
+      report "***PASSED TEST: c08s06b00x00p05n01i01425"
+      severity NOTE;
+    assert (v1 = v2)
+      report "***FAILED TEST: c08s06b00x00p05n01i01425 - Procedure call without an actual parameter part is permitted." 
+      severity ERROR;
+  end assert_same_int;
+
+BEGIN
+  TESTING : PROCESS
+    variable   v1 : integer := 1;
+  BEGIN
+
+    --
+    -- Try without any parameters; the procedure should
+    -- use the default values for the arguments.
+    --
+    v1 := 5;
+    assert_same_int;   
+
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p05n01i01425arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc143.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc143.vhd
new file mode 100644
index 0000000..3c27e48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc143.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc143.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p12n01i00143pkg is
+  type fourstate is ('0','1','x','z');
+  function fourstate_to_bit(x : fourstate) return bit;
+  procedure simple ( crude : in bit;
+                     signal refined : out bit);
+end c04s03b02x02p12n01i00143pkg;
+
+package body c04s03b02x02p12n01i00143pkg is
+  procedure simple ( crude : in bit;
+                     signal refined : out bit) is
+  begin
+    refined <= crude after 5 ns;
+  end simple;
+  
+  function fourstate_to_bit(x : fourstate) return bit is
+    variable newval: bit := '0';
+  begin
+    case x is
+      when '0' => newval := '0';
+      when '1' => newval := '1';
+      when 'z' => newval := '0';
+      when 'x' => newval := '0';
+    end case;
+    return newval;
+  end fourstate_to_bit;
+end c04s03b02x02p12n01i00143pkg;
+
+use work.c04s03b02x02p12n01i00143pkg.all;
+ENTITY c04s03b02x02p12n01i00143ent IS
+  port( x, y: in fourstate);
+END c04s03b02x02p12n01i00143ent;
+
+ARCHITECTURE c04s03b02x02p12n01i00143arch OF c04s03b02x02p12n01i00143ent IS
+  signal yint : bit;
+BEGIN
+
+  simple ( fourstate_to_bit(y) , yint);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT( yint = '0' )
+      report "***PASSED TEST: c04s03b02x02p12n01i00143"
+      severity NOTE;
+    assert ( yint = '0' )
+      report "***FAILED TEST: c04s03b02x02p12n01i00143 - Type conversion test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p12n01i00143arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1442.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1442.vhd
new file mode 100644
index 0000000..530af35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1442.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1442.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01442ent IS
+END c08s07b00x00p02n01i01442ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01442arch OF c08s07b00x00p02n01i01442ent IS
+
+begin
+  TESTING: process
+    variable k : integer := 0;
+    variable m : integer := 6;
+    variable j : boolean := TRUE;
+  begin
+    if m > 5 then
+      case j is
+        when TRUE   => k := 1;
+        when FALSE   => NULL;
+      end case;
+    end if;
+    assert NOT(k = 1)
+      report "***PASSED TEST: c08s07b00x00p02n01i01442"
+      severity NOTE;
+    assert (k = 1)
+      report "***FAILED TEST: c08s07b00x00p02n01i01442 - CASE statement to be sequence statements of IF statement" 
+      severity ERROR;
+    wait;
+  end process TESTING;
+
+END c08s07b00x00p02n01i01442arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1443.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1443.vhd
new file mode 100644
index 0000000..101ac09
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1443.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1443.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01443ent IS
+END c08s07b00x00p02n01i01443ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01443arch OF c08s07b00x00p02n01i01443ent IS
+
+begin
+  transmit: process
+    variable k : integer := 10;
+    variable m : integer := 6;
+  begin
+    if m > 5 then
+      while (k > 5) loop
+        k := k - 1;
+      end loop;
+    end if;
+    assert (k = 5)
+      report "***FAILED TEST: c08s07b00x00p02n01i01443 - WHILE statement to be sequence statements of IF statement" 
+      severity ERROR;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s07b00x00p02n01i01443"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01443arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1444.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1444.vhd
new file mode 100644
index 0000000..c8db78d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1444.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1444.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01444ent IS
+END c08s07b00x00p02n01i01444ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01444arch OF c08s07b00x00p02n01i01444ent IS
+
+begin
+  transmit: process
+    variable k : integer := 10;
+    variable m : integer := 6;
+    variable n : integer ;
+  begin
+    if m > 5 then
+      for n in 1 to 5 loop
+        k := k - 1;
+      end loop;
+    end if;
+    assert (k = 5)
+      report "***FAILED TEST: c08s07b00x00p02n01i01444 - FOR LOOP statement to be sequence statements of IF statement" 
+      severity ERROR;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s07b00x00p02n01i01444"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01444arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1445.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1445.vhd
new file mode 100644
index 0000000..636479b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1445.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1445.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01445ent IS
+END c08s07b00x00p02n01i01445ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01445arch OF c08s07b00x00p02n01i01445ent IS
+
+begin
+  transmit: process
+    variable k : integer := 10;
+    variable m : integer := 6;
+    variable n : time    := 0 ns;
+  begin
+    if m > 5 then
+      n := now;
+      wait for 5 ns;
+      n := now - n;
+    end if;
+    assert NOT(n = 5 ns)
+      report "***PASSED TEST: c08s07b00x00p02n01i01445"
+      severity NOTE;
+    assert (n = 5 ns)
+      report "***FAILED TEST: c08s07b00x00p02n01i01445 - WAIT FOR statement to be sequence statements of IF statement" 
+      severity ERROR;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01445arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1446.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1446.vhd
new file mode 100644
index 0000000..45929ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1446.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1446.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01446ent IS
+END c08s07b00x00p02n01i01446ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01446arch OF c08s07b00x00p02n01i01446ent IS
+
+  signal     k : integer := 0;
+begin
+  transmit: process
+    variable m : integer := 6;
+  begin
+    if m > 5 then
+      k <= 5;
+    end if;
+    wait for 1 ns;
+    assert (k = 5)
+      report "***FAILED TEST: c08s07b00x00p02n01i01446 - Signal Assignment statement to be sequence statements of IF statement" 
+      severity ERROR;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s07b00x00p02n01i01446"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01446arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1447.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1447.vhd
new file mode 100644
index 0000000..1ba77d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1447.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1447.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01447ent IS
+END c08s07b00x00p02n01i01447ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01447arch OF c08s07b00x00p02n01i01447ent IS
+
+begin
+  transmit: process
+    procedure ARITH(z  : out integer) is
+    begin
+      z := 5;
+    end ARITH;
+    variable k : integer ;
+    variable m : integer := 6;
+  begin
+    if m > 5 then
+      ARITH(k);
+    end if;
+    assert (k = 5)
+      report "***FAILED TEST: c08s07b00x00p02n01i01447 - Procedure Call statement to be sequence statements of IF statement" 
+      severity ERROR;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s07b00x00p02n01i01447"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01447arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1448.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1448.vhd
new file mode 100644
index 0000000..9af36a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1448.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1448.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01448ent IS
+END c08s07b00x00p02n01i01448ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01448arch OF c08s07b00x00p02n01i01448ent IS
+
+begin
+  transmit: process
+    procedure ARITH(op : in  integer;
+                    z  : out integer) is
+    begin
+      if (op > 5) then
+        z := 5;
+        return;
+      end if;
+    end ARITH;
+    variable k : integer ;
+    variable m : integer := 6;
+  begin
+    ARITH(m,k);
+    assert (k = 5)
+      report "***FAILED TEST: c08s07b00x00p02n01i01448 - RETURN statement to be sequence statements of IF statement" 
+      severity ERROR;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s07b00x00p02n01i01448"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01448arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1450.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1450.vhd
new file mode 100644
index 0000000..962b1e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1450.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1450.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p01n01i01450ent IS
+END c08s07b00x00p01n01i01450ent;
+
+ARCHITECTURE c08s07b00x00p01n01i01450arch OF c08s07b00x00p01n01i01450ent IS
+
+begin
+  p: process
+    variable j : integer := 1;
+    variable i : integer := 0;   
+    variable k : integer := 0;
+    variable m : integer := 0;
+  begin
+    if    j = 1  then
+      i := 1;
+    elsif j = 2  then
+      k := 1;
+    else
+      m := 1;
+    end if;
+    assert (i = 0) and (k = 1) and (m = 1)
+      report "***PASSED TEST: c08s07b00x00p01n01i01450"
+      severity NOTE;
+    assert NOT((i = 0) and (k = 1) and (m = 1))
+      report "***FAILED TEST: c08s07b00x00p01n01i01450 - An expression specifying a condition must be of type BOOLEAN"
+      severity ERROR;
+    wait;
+  end process;
+
+END c08s07b00x00p01n01i01450arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1451.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1451.vhd
new file mode 100644
index 0000000..9e87805
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1451.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1451.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p01n01i01451ent IS
+END c08s07b00x00p01n01i01451ent;
+
+ARCHITECTURE c08s07b00x00p01n01i01451arch OF c08s07b00x00p01n01i01451ent IS
+
+begin
+  t: process
+    type some2 is (alpha,beta);   
+    variable j : some2 := alpha;
+    variable k : integer := 0;
+  begin
+    if  j = alpha  then
+      k := 1;
+    end if;
+    assert (k = 0)
+      report "***PASSED TEST: c08s07b00x00p01n01i01451"
+      severity NOTE;
+    assert NOT(k = 0)
+      report "***FAILED TEST: c08s07b00x00p01n01i01451 - BOOLEAN expression of IF statement using enumerated types"
+      severity ERROR;
+    wait;
+  end process;
+
+END c08s07b00x00p01n01i01451arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1452.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1452.vhd
new file mode 100644
index 0000000..bf9bfd5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1452.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1452.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p01n01i01452ent IS
+END c08s07b00x00p01n01i01452ent;
+
+ARCHITECTURE c08s07b00x00p01n01i01452arch OF c08s07b00x00p01n01i01452ent IS
+
+begin
+  expr_check: process
+    variable x : integer := 3;
+    variable y : integer := 5;
+    variable z : integer := 9;
+    variable k : integer := 0;
+  begin
+    if -x + z < y + x and x * z > y -x then        -- no_failure_here
+      k := 1;
+    end if;
+    assert (k = 1)
+      report "***FAILED TEST: c08s07b00x00p01n01i01452 - expression type of IF statement wrong"
+      severity ERROR;
+    assert NOT(k = 1)
+      report "***PASSED TEST: c08s07b00x00p01n01i01452"
+      severity NOTE;
+    wait;
+  end process;
+
+END c08s07b00x00p01n01i01452arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1456.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1456.vhd
new file mode 100644
index 0000000..0b1502c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1456.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1456.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01456ent IS
+END c08s07b00x00p04n01i01456ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01456arch OF c08s07b00x00p04n01i01456ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable k     : integer := 0;
+    variable m     : integer := 0;
+    variable n     : integer := 0;
+  begin
+    if    delay = 1 then
+      k := 1;
+    elsif delay = 0 then
+      m := 1;
+    else
+      n := 1;
+    end if;
+    assert NOT((k = 1) and (m = 0) and (n = 0))
+      report "***PASSED TEST: c08s07b00x00p04n01i01456"
+      severity NOTE;
+    assert (k = 1) and (m = 0) and (n = 0)
+      report "***FAILED TEST: c08s07b00x00p04n01i01456 - only the condition after the IF statement is TRUE, all others are evaluated to be FALSE"
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01456arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1457.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1457.vhd
new file mode 100644
index 0000000..2526d40
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1457.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1457.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01457ent IS
+END c08s07b00x00p04n01i01457ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01457arch OF c08s07b00x00p04n01i01457ent IS
+
+BEGIN
+  TESTING : PROCESS
+    variable a    : integer := 1;
+    variable k        : integer := 0;
+    variable m        : integer := 0;
+  BEGIN
+    if    a = 0 then
+      m := 1;
+    elsif a = 1 then
+      k := 1;
+    end if;
+    wait for 5 ns;
+    assert NOT((m = 0) and (k = 1))
+      report "***PASSED TEST: c08s07b00x00p04n01i01457"
+      severity NOTE;
+    assert (m = 0) and (k = 1)
+      report "***FAILED TEST: c08s07b00x00p04n01i01457 - only the condition after the ELSIF statement is TRUE, all others should be FALSE"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s07b00x00p04n01i01457arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1458.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1458.vhd
new file mode 100644
index 0000000..ac8634a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1458.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1458.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01458ent IS
+END c08s07b00x00p04n01i01458ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01458arch OF c08s07b00x00p04n01i01458ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable k     : integer := 0;
+    variable m     : integer := 0;
+    variable n     : integer := 0;
+  begin
+    if    delay = 0 then
+      m := 1;
+    elsif delay = 4 then
+      n := 1;
+    else
+      k := 1;
+    end if;
+    assert NOT((m = 0) and (n = 0) and (k = 1))
+      report "***PASSED TEST: c08s07b00x00p04n01i01458"
+      severity NOTE;
+    assert (m = 0) and (n = 0) and (k = 1)
+      report "***FAILED TEST: c08s07b00x00p04n01i01458 - conditions after the if and elsif are evaluated to be FALSE, so should treat a final else as elsif TRUE then" 
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01458arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1459.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1459.vhd
new file mode 100644
index 0000000..3709c5c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1459.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1459.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01459ent IS
+END c08s07b00x00p04n01i01459ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01459arch OF c08s07b00x00p04n01i01459ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable m     : integer := 0;
+    variable n     : integer := 0;
+  begin
+    if    delay = 0 then
+      m := 1;
+    elsif delay = 4 then
+      n := 1;
+    end if;
+    assert NOT((m = 0) and (n = 0))
+      report "***PASSED TEST: c08s07b00x00p04n01i01459"
+      severity NOTE;
+    assert (m = 0) and (n = 0)
+      report "***FAILED TEST: c08s07b00x00p04n01i01459 - all conditions should be evaluated and yield FALSE" 
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01459arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc146.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc146.vhd
new file mode 100644
index 0000000..c765a65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc146.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc146.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p12n01i00146pkg is
+  procedure P1 (a : in integer; b: out integer);
+  function  F1 (I : in integer) return real;
+end c04s03b02x02p12n01i00146pkg;
+
+package body c04s03b02x02p12n01i00146pkg is
+  procedure P1 (a: in integer; b: out integer) is
+  begin
+    b := a;
+  end;
+  
+  function  F1 (I: in integer) return real is
+    variable y : real := 1.0;
+  begin
+    return (y * 10.0);
+  end;
+end c04s03b02x02p12n01i00146pkg;
+
+use work.c04s03b02x02p12n01i00146pkg.all;
+ENTITY c04s03b02x02p12n01i00146ent IS
+END c04s03b02x02p12n01i00146ent;
+
+ARCHITECTURE c04s03b02x02p12n01i00146arch OF c04s03b02x02p12n01i00146ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    variable x : real := 1.0;
+    variable y : real ;
+  BEGIN
+    P1 (10, F1(b) => x );   -- no_failure_here                
+    -- b and x have the same type.
+    y := x;
+    assert NOT(y=10.0)
+      report "***PASSED TEST: c04s03b02x02p12n01i00146"
+      severity NOTE;
+    assert (y=10.0)
+      report "***FAILED TEST: c04s03b02x02p12n01i00146 - Element of an association list has a function act on it within the association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p12n01i00146arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1460.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1460.vhd
new file mode 100644
index 0000000..3e54918
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1460.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1460.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01460ent IS
+END c08s07b00x00p04n01i01460ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01460arch OF c08s07b00x00p04n01i01460ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable k     : integer := 0;
+    variable m     : integer := 0;
+  begin
+    if    delay = 0 then
+      m := 1;
+    else
+      k := 1;
+    end if;
+    assert NOT((m = 0) and (k = 1))
+      report "***PASSED TEST: c08s07b00x00p04n01i01460"
+      severity NOTE;
+    assert (m = 0) and (k = 1)
+      report "***FAILED TEST: c08s07b00x00p04n01i01460 - conditions after the if is evalusted to be FALSE, so should treat a final else as elsif TRUE then" 
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01460arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1461.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1461.vhd
new file mode 100644
index 0000000..58fa236
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1461.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1461.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01461ent IS
+END c08s07b00x00p04n01i01461ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01461arch OF c08s07b00x00p04n01i01461ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable k     : integer := 0;
+    variable m     : integer := 0;
+    variable n     : integer := 0;
+  begin
+    if    delay = 1 then
+      k := 1;
+    end if;
+    assert NOT(k = 1) 
+      report "***PASSED TEST: c08s07b00x00p04n01i01461"
+      severity NOTE;
+    assert (k = 1) 
+      report "***FAILED TEST: c08s07b00x00p04n01i01461 - the condition after the IF statement is TRUE in 'if-end if' format"
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01461arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1462.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1462.vhd
new file mode 100644
index 0000000..93122e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1462.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1462.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p04n01i01462ent IS
+END c08s07b00x00p04n01i01462ent;
+
+ARCHITECTURE c08s07b00x00p04n01i01462arch OF c08s07b00x00p04n01i01462ent IS
+
+begin
+  transmit: process
+    variable delay : integer := 1;
+    variable k     : integer := 0;
+    variable m     : integer := 0;
+    variable n     : integer := 0;
+    variable p     : integer := 0;
+  begin
+    if    delay = 0 then
+      m := 1;
+    elsif delay = 2 then
+      p := 1;
+    elsif delay = 1 then
+      k := 1;
+    else
+      n := 1;
+    end if;
+    assert NOT((m = 0) and (p = 0) and (k = 1) and (n = 0))
+      report "***PASSED TEST: c08s07b00x00p04n01i01462"
+      severity NOTE;
+    assert (m = 0) and (p = 0) and (k = 1) and (n = 0)
+      report "***FAILED TEST: c08s07b00x00p04n01i01462 - only the condition after the second ELSIF statement is TRUE, all others should be FALSE"
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p04n01i01462arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1463.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1463.vhd
new file mode 100644
index 0000000..2b0a800
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1463.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1463.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p02n01i01463ent IS
+END c08s08b00x00p02n01i01463ent;
+
+ARCHITECTURE c08s08b00x00p02n01i01463arch OF c08s08b00x00p02n01i01463ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+    variable k : integer := 0;
+  BEGIN
+    case x is
+      when 1 => k := 5;
+      when 2 => NULL;
+      when 3 => NULL;
+      when others => NULL;
+    end case;
+    assert NOT( k=5 ) 
+      report "***PASSED TEST: c08s08b00x00p02n01i01463" 
+      severity NOTE;
+    assert ( k=5 ) 
+      report "***FAILED TEST: c08s08b00x00p02n01i01463 - missing reserved word 'when'"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p02n01i01463arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc147.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc147.vhd
new file mode 100644
index 0000000..45f04e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc147.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc147.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p14n01i00147ent IS
+  PORT ( ii: INOUT integer);
+  FUNCTION addup (i1,i2,i3:INTEGER:=5) RETURN INTEGER IS
+  BEGIN
+    IF (i1 = 0) THEN
+      RETURN (i2+i3);
+    ELSE
+      RETURN addup(i2=>i1*3,i1=>0,i3=>0)+i2+i3;
+    END IF;
+  END;
+END c04s03b02x02p14n01i00147ent;
+
+ARCHITECTURE c04s03b02x02p14n01i00147arch OF c04s03b02x02p14n01i00147ent IS
+  SIGNAL a1 : INTEGER := 57;
+  SIGNAL a2 : INTEGER := 68;
+  SIGNAL a3 : INTEGER := 77;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    ii <= addup(
+      i3=>addup(i3=>-8,i1=>addup(4,2,2),i2=>addup(i1=>0,i2=>0,i3=>0)),
+      i1=>addup(
+        i2=>addup(
+          i2=>addup(i2=>6,i3=>7),
+          i1=>addup(i3=>3,i1=>1,i2=>2),
+          i3=>addup(i2=>8,i3=>9,i1=>7)
+          ),
+        i1=>addup(i2=>2,i1=>1,i3=>3),
+        i3=>addup(i2=>a2,i3=>a3,i1=>a1)
+        ),
+      i2=>addup(i3=>-8,i2=>0,i1=>8)
+      );
+    WAIT FOR 1 ns;
+    assert NOT(ii=1346) 
+      report "***PASSED TEST: c04s03b02x02p14n01i00147"
+      severity NOTE;
+    assert (ii=1346) 
+      report "***FAILED TEST: c04s03b02x02p14n01i00147 - Function call does not use function call in parameter list." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p14n01i00147arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1473.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1473.vhd
new file mode 100644
index 0000000..b2feed6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1473.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1473.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01473ent IS
+END c08s08b00x00p04n01i01473ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01473arch OF c08s08b00x00p04n01i01473ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : character := 'C';
+  BEGIN
+    case i is
+      when 'C' => k := 5;
+      when 'L' => NULL;
+      when 'S' => NULL;
+      when 'I' => NULL;
+      when others => NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n01i01473"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n01i01473 - expression of one dimension character array  type"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01473arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1474.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1474.vhd
new file mode 100644
index 0000000..5f120cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1474.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1474.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01474ent IS
+END c08s08b00x00p04n01i01474ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01474arch OF c08s08b00x00p04n01i01474ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : BIT     := '0';
+  BEGIN
+    case i is
+      when '0' => k := 5;
+      when '1' => NULL;
+      when others => NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n01i01474"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n01i01474 - expression of enumeration type"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01474arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1475.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1475.vhd
new file mode 100644
index 0000000..dc84b9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1475.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1475.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01475ent IS
+END c08s08b00x00p04n01i01475ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01475arch OF c08s08b00x00p04n01i01475ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : BIT     := '0';
+  BEGIN
+    case i is
+      when '0' => k := 5;
+      when '1' => NULL;
+      when others => NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n01i01475"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n01i01475 - expression of integer type"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01475arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc148.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc148.vhd
new file mode 100644
index 0000000..55abf23
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc148.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc148.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p14n01i00148ent IS
+END c04s03b02x02p14n01i00148ent;
+
+ARCHITECTURE c04s03b02x02p14n01i00148arch OF c04s03b02x02p14n01i00148ent IS
+
+  FUNCTION FLOAT ( ival : in integer) return real is
+    VARIABLE v1 : real := 543.0;
+  begin
+    RETURN v1;
+  end FLOAT;
+
+  FUNCTION ROUND ( rval : in real) return integer is
+    VARIABLE v1 : integer := 543;
+  begin
+    RETURN v1;
+  end ROUND;
+  
+  PROCEDURE test_bed
+    ( in1  : in  integer;
+      out1 : out real ) is
+  begin
+    out1 := FLOAT (in1);
+  end test_bed;
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE var1 : real;
+    VARIABLE var2 : real := 543.2;
+  BEGIN
+    test_bed ( in1  => ROUND (var2),
+               out1 => var1   );
+    assert NOT( var1 = 543.0 )
+      report "***PASSED TEST: c04s03b02x02p14n01i00148"
+      severity NOTE;
+    assert ( var1 = 543.0 )
+      report "***FAILED TEST: c04s03b02x02p14n01i00148 - The actual part of a named element association may be in the form of a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p14n01i00148arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1483.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1483.vhd
new file mode 100644
index 0000000..2075f49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1483.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1483.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01483ent IS
+END c08s08b00x00p04n03i01483ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01483arch OF c08s08b00x00p04n03i01483ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : integer := 2;
+  BEGIN
+    case i is
+      when 1 | 2   =>   k := 5;
+      when others   =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01483"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01483 - one alternative can consist of serveral choices"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01483arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1485.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1485.vhd
new file mode 100644
index 0000000..71b3149
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1485.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1485.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01485ent IS
+END c08s08b00x00p04n03i01485ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01485arch OF c08s08b00x00p04n03i01485ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable m : severity_level := NOTE;
+    variable k : integer := 0;
+  BEGIN
+    case m is
+      when severity_level'low | severity_level'high   =>   k := 5;
+      when others               =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01485"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01485 - Each choice in a case statement alternative must be of the same type as the expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01485arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1486.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1486.vhd
new file mode 100644
index 0000000..40dca66
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1486.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1486.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01486ent IS
+END c08s08b00x00p04n03i01486ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01486arch OF c08s08b00x00p04n03i01486ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable m : character := 'j';
+    variable k : integer := 0;
+  BEGIN
+    case m is
+      when 'a'|'b'|'c'|'d'|'j' =>   k := 5;
+      when 'e'|'f'|'g'|'h'|'i' =>   k := 4;
+      when others       =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01486"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01486 - Each choice in a case statement alternative must be of the same type as the expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01486arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1487.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1487.vhd
new file mode 100644
index 0000000..e78ab79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1487.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1487.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01487ent IS
+END c08s08b00x00p04n03i01487ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01487arch OF c08s08b00x00p04n03i01487ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     t_enum1 is (en1, en2, en3, en4);
+    variable m : t_enum1 := en1;
+    variable k : integer := 0;
+  BEGIN
+    case m is
+      when en1 | en2 =>   k := 5;
+      when en3 | en4 =>   k := 4;
+      when others    =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01487"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01487 - Each choice in a case statement alternative must be of the same type as the expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01487arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1488.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1488.vhd
new file mode 100644
index 0000000..f81c251
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1488.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1488.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01488ent IS
+END c08s08b00x00p04n03i01488ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01488arch OF c08s08b00x00p04n03i01488ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable m : integer := 7;
+    variable k : integer := 0;
+  BEGIN
+    case m is
+      when integer'Low to -11 | 6 to 100 =>   k := 5;
+      when others    =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01488"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01488 - Each choice in a case statement alternative must be of the same type as the expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01488arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc149.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc149.vhd
new file mode 100644
index 0000000..869e7c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc149.vhd
@@ -0,0 +1,125 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc149.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p14n01i00149ent IS
+  PORT ( ii: INOUT integer);
+  PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
+  BEGIN
+    IF add THEN
+      i4 := (i1+i2+i3);
+    ELSE
+      i4 := (i1-i2)-i3;
+    END IF;
+  END;
+END c04s03b02x02p14n01i00149ent;
+
+ARCHITECTURE c04s03b02x02p14n01i00149arch OF c04s03b02x02p14n01i00149ent IS
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE a1 : INTEGER := 57;
+    VARIABLE a11: INTEGER := 57;
+    VARIABLE a12: INTEGER := 57;
+    VARIABLE a13: INTEGER := 57;
+    VARIABLE a2 : INTEGER := 68;
+    VARIABLE a3 : INTEGER := 77;
+    VARIABLE b1 : BIT := '1';
+    VARIABLE b2 : BIT := '0';
+    FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
+    BEGIN
+      IF (inp > 0) THEN
+        RETURN (TRUE);
+      ELSE
+        RETURN (FALSE);
+      END IF;
+    END;
+    FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
+    BEGIN
+      IF (inp = '1') THEN
+        RETURN (22);
+      ELSE
+        RETURN (23);
+      END IF;
+    END;
+
+  BEGIN
+    WAIT FOR 1 ns;
+    addup(i2=>conv1(b1),add=>convb(INTEGER'HIGH),i1=>conv1(b2),i3=>a1,i4=>a1);
+    WAIT FOR 1 ns;
+    IF (a1 = 102) THEN
+      ASSERT false REPORT "PASS: Function call uses function to convert type of actual" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(add=>convb(-33),i3=>2,i1=>a3,i2=>a2,i4=>a11);
+    WAIT FOR 1 ns;
+    IF (a11 = 7) THEN
+      ASSERT false REPORT "PASS: Function call uses function to convert actual to false" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(add=>TRUE,i3=>conv1('1'),i2=>conv1('1'),i1=>conv1('0'),i4=>a12);
+    WAIT FOR 1 ns;
+    IF (a12 = 67) THEN
+      ASSERT false REPORT "PASS: Function call uses same actual twice" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
+    END IF;
+    
+    WAIT FOR 1 ns;
+    addup(15,5,5,convb(-1),a13);
+    WAIT FOR 1 ns;
+    IF (a13 = 5) THEN
+      ASSERT false REPORT "PASS: No named association used" SEVERITY note;
+    ELSE
+      ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
+    END IF;
+    WAIT FOR 1 ns;
+
+    assert NOT(   a1 = 102   and
+                  a11= 7      and
+                  a12= 67      and
+                  a13= 5      )
+      report "***PASSED TEST: c04s03b02x02p14n01i00149"
+      severity NOTE;
+    assert (   a1 = 102   and
+               a11= 7      and
+               a12= 67      and
+               a13= 5      )
+      report "***FAILED TEST: c04s03b02x02p14n01i00149 - Function call uses function to convert type of actual."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p14n01i00149arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1491.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1491.vhd
new file mode 100644
index 0000000..d06c340
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1491.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1491.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p05n01i01491ent IS
+END c08s08b00x00p05n01i01491ent;
+
+ARCHITECTURE c08s08b00x00p05n01i01491arch OF c08s08b00x00p05n01i01491ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type x is (Jan,Feb,Mar);
+    variable y:x := Jan;
+    variable k   : integer := 5;
+
+  BEGIN
+    case y is
+      when Jan   => k := 5;
+      when Feb   => NULL;
+      when Mar   => NULL;
+    end case;
+
+    assert NOT( k = 5 ) 
+      report "***PASSED TEST: c08s08b00x00p05n01i01491"
+      severity NOTE;
+    assert ( k = 5 ) 
+      report "***FAILED TEST: c08s08b00x00p05n01i01491 - each value of the subtype of the object of scalar type is represented only once in the set of choices of the case statement" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p05n01i01491arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1493.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1493.vhd
new file mode 100644
index 0000000..d9c8b9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1493.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1493.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p07n01i01493ent IS
+END c08s08b00x00p07n01i01493ent;
+
+ARCHITECTURE c08s08b00x00p07n01i01493arch OF c08s08b00x00p07n01i01493ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Scal is array (0 to 1) of CHARACTER;
+    variable kk : Scal    := "TH"; 
+    variable k  : integer := 0;
+  BEGIN
+    case kk is
+      when "TH"   =>   k := 5;
+      when "AB"   =>    NULL;
+      when others   =>   NULL;
+    end case; 
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s08b00x00p07n01i01493"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s08b00x00p07n01i01493 - case expression is the name of an object whose subtype is locally static, when it is a one-dimensional character array type"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p07n01i01493arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1495.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1495.vhd
new file mode 100644
index 0000000..67af127
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1495.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1495.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p09n01i01495ent IS
+END c08s08b00x00p09n01i01495ent;
+
+ARCHITECTURE c08s08b00x00p09n01i01495arch OF c08s08b00x00p09n01i01495ent IS
+  SUBTYPE string_30 is STRING(1 to 30);
+  SUBTYPE string_4  is STRING(1 to 4);
+BEGIN
+  TESTING: PROCESS
+    VARIABLE str : string_30 := "1234567890abcdefghijlkmnopqrst";
+    variable k   : integer   := 0;
+  BEGIN
+    case string_4'(str(1 to 4)) is
+      when "1234" =>   k := 5; 
+      when OTHERS =>   k := 6; 
+    end case;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c08s08b00x00p09n01i01495" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c08s08b00x00p09n01i01495 - Expression being a qualified expression failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p09n01i01495arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1496.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1496.vhd
new file mode 100644
index 0000000..7caf885
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1496.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1496.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n01i01496ent IS
+END c08s08b00x00p14n01i01496ent;
+
+ARCHITECTURE c08s08b00x00p14n01i01496arch OF c08s08b00x00p14n01i01496ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable p : integer := 0;
+  BEGIN
+    case p is
+      when 0      =>   k := 5;
+      when 1      =>    NULL;
+      when others   =>   NULL;
+    end case;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s08b00x00p14n01i01496"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s08b00x00p14n01i01496 - Simple expression and discrete range given as choice in a case statement must be locally static"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n01i01496arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1497.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1497.vhd
new file mode 100644
index 0000000..ed07f0f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1497.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1497.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n01i01497ent IS
+END c08s08b00x00p14n01i01497ent;
+
+ARCHITECTURE c08s08b00x00p14n01i01497arch OF c08s08b00x00p14n01i01497ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable p : integer := 20;
+  BEGIN
+    case p>=20 and p<30 is
+      when TRUE   =>   k := 5;
+      when FALSE   =>    NULL;
+      when others   =>   NULL;
+    end case;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s08b00x00p14n01i01497"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s08b00x00p14n01i01497 - Case expression may be a complex static expression" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n01i01497arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1499.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1499.vhd
new file mode 100644
index 0000000..8bc5cf8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1499.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1499.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n01i01499ent IS
+END c08s08b00x00p14n01i01499ent;
+
+ARCHITECTURE c08s08b00x00p14n01i01499arch OF c08s08b00x00p14n01i01499ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype sub_int is integer range 1 to 2;
+    variable V1 : integer;
+    variable k1 : integer := 0;
+    variable k2 : integer := 0;
+    variable k3 : integer := 0;
+    variable k4 : integer := 0;
+  BEGIN
+    V1 := 0;
+    case V1 is
+      when sub_int'low
+        to sub_int'high => assert (false)
+                             report "V1 in specified range"
+                             severity failure;
+      when others       => k1 := 1;
+    end case;
+    V1 := 1;
+    case V1 is
+      when sub_int'low
+        to sub_int'high => k2 := 1;
+      when others       => assert (false)
+                             report "V1 NOT in specified range"
+                             severity failure;
+    end case;
+    V1 := 2;
+    case V1 is
+      when sub_int'low
+        to sub_int'high => k3 := 1;
+      when others       => assert (false)
+                             report "V1 NOT in specified range"
+                             severity failure;
+    end case;
+    V1 := 3;
+    case V1 is
+      when sub_int'low
+        to sub_int'high => assert (false)
+                             report "V1 in specified range"
+                             severity failure;
+      when others       => k4 := 1;
+    end case;
+    assert NOT(k1=1 and k2=1 and k3=1 and k4=1) 
+      report "***PASSED TEST: c08s08b00x00p14n01i01499" 
+      severity NOTE;
+    assert (k1=1 and k2=1 and k3=1 and k4=1) 
+      report "***FAILED TEST: c08s08b00x00p14n01i01499 - A choice can be a discrete range using attributes." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n01i01499arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc15.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc15.vhd
new file mode 100644
index 0000000..17f35f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc15.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc15.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p06n01i00015ent IS
+END c04s02b00x00p06n01i00015ent;
+
+ARCHITECTURE c04s02b00x00p06n01i00015arch OF c04s02b00x00p06n01i00015ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    subtype   tboolean    is boolean       range FALSE to TRUE;
+    subtype tbit      is bit         range '0'   to '1';   
+    subtype tcharacter   is character      range 'A'   to 'Z';
+    subtype tseverity_level   is severity_level   range NOTE  to ERROR;
+    subtype tinteger   is integer      range 1111  to 2222;
+    subtype treal      is real         range 1.11  to 2.22;
+    subtype ttime      is time         range 1 ns  to 1 hr;
+    subtype tnatural   is natural      range 100   to 200;
+    subtype tpositive   is positive      range 1000  to 2000;
+
+    variable k1  : tboolean;
+    variable k2  : tbit;
+    variable k3  : tcharacter;
+    variable k4  : tseverity_level;
+    variable k5  : tinteger;
+    variable k6  : treal;
+    variable k7  : ttime;
+    variable k8  : tnatural;
+    variable k9  : tpositive;
+
+  BEGIN
+    assert NOT(   k1   = tboolean'left      and
+                  k2   = tbit'left       and
+                  k3   = tcharacter'left   and
+                  k4   = tseverity_level'left   and
+                  k5   = tinteger'left      and
+                  k6   = treal'left      and
+                  k7   = ttime'left      and
+                  k8   = tnatural'left      and
+                  k9   = tpositive'left   )
+      report "***PASSED TEST: c04s02b00x00p06n01i00015"
+      severity NOTE;
+    assert (   k1   = tboolean'left      and
+               k2   = tbit'left       and
+               k3   = tcharacter'left   and
+               k4   = tseverity_level'left   and
+               k5   = tinteger'left      and
+               k6   = treal'left      and
+               k7   = ttime'left      and
+               k8   = tnatural'left      and
+               k9   = tpositive'left   )
+      report "***FAILED TEST: c04s02b00x00p06n01i00015 - A type mark denotes a type or a subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p06n01i00015arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc150.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc150.vhd
new file mode 100644
index 0000000..94b0905
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc150.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc150.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p14n01i00150ent IS
+END c04s03b02x02p14n01i00150ent;
+
+ARCHITECTURE c04s03b02x02p14n01i00150arch OF c04s03b02x02p14n01i00150ent IS
+
+  FUNCTION FLOAT ( ival : in integer) return real is
+    VARIABLE v1 : real := 543.0;
+  begin
+    RETURN v1;
+  end FLOAT;
+
+  FUNCTION ROUND ( rval : in real) return integer is
+    VARIABLE v1 : integer := 543;
+  begin
+    RETURN v1;
+  end ROUND;
+  
+  PROCEDURE test_bed
+    ( in1  : in  integer;
+      out1 : out real )
+  is
+  begin
+    out1 := FLOAT (in1);
+  end test_bed;
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE var1 : real;
+    VARIABLE var2 : real := 543.2;
+  BEGIN
+    test_bed ( ROUND (var2), var1 );
+    assert NOT( var1 = 543.0 )
+      report "***PASSED TEST:c04s03b02x02p14n01i00150"
+      severity NOTE;
+    assert ( var1 = 543.0 )
+      report "***FAILED TEST:c04s03b02x02p14n01i00150 - The actual part of a named element association may be in the form of a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p14n01i00150arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1500.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1500.vhd
new file mode 100644
index 0000000..50a4e74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1500.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1500.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n02i01500ent IS
+END c08s08b00x00p14n02i01500ent;
+
+ARCHITECTURE c08s08b00x00p14n02i01500arch OF c08s08b00x00p14n02i01500ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : integer := 5;
+  BEGIN
+    case i is
+      when 1  to 19   => k := 5;
+      when 20 to 29   => NULL;
+      when 30 to 39   => NULL;
+      when others   => NULL;
+    end case;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s08b00x00p14n02i01500"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s08b00x00p14n02i01500 - A choice defined by a discrete range stands for all values in the corresponding range"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n02i01500arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1505.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1505.vhd
new file mode 100644
index 0000000..bf5a3d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1505.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1505.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n03i01505ent IS
+END c08s08b00x00p14n03i01505ent;
+
+ARCHITECTURE c08s08b00x00p14n03i01505arch OF c08s08b00x00p14n03i01505ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 19;
+    variable k : integer := 0;
+  BEGIN
+    case x is
+      when others    =>   k:=5;
+    end case;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s08b00x00p14n03i01505"
+      severity NOTE;
+    assert ( k=5 ) 
+      report "***FAILED TEST: c08s08b00x00p14n03i01505 - OTHERS choice may stand foe the full set of values of the expression in a case statement" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n03i01505arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1507.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1507.vhd
new file mode 100644
index 0000000..e6adcb2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1507.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1507.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p16n01i01507ent IS
+END c08s08b00x00p16n01i01507ent;
+
+ARCHITECTURE c08s08b00x00p16n01i01507arch OF c08s08b00x00p16n01i01507ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable s1, s2, s3, s4, s5, s6 : INTEGER := 0;
+  BEGIN
+
+    for i in 1 to 1000 loop
+      case i is
+        when 1 =>                           s1 := s1 + 1;
+        when 2 | 3 =>                       s2 := s2 + 1;
+        when 4 to 100 =>                    s3 := s3 + 1;
+        when 200 to 201 | 300 to 350 =>     s4 := s4 + 1;
+        when 400 to 450 =>                  s5 := s5 + 1;
+        when others =>                      s6 := s6 + 1;
+      end case;
+    end loop;
+    wait for 5 ns;
+    assert NOT(    s1 = 1   and
+                   s2 = 2   and
+                   s3 = 97   and
+                   s4 = 2 + 51   and
+                   s5 = 51   and
+                   s6 = 1000 - (s1+s2+s3+s4+s5)   )
+      report "***PASSED TEST: c08s08b00x00p16n01i01507"
+      severity NOTE;
+    assert (    s1 = 1   and
+                s2 = 2   and
+                s3 = 97   and
+                s4 = 2 + 51   and
+                s5 = 51   and
+                s6 = 1000 - (s1+s2+s3+s4+s5)   )
+      report "***FAILED TEST: c08s08b00x00p16n01i01507 - Case statement execution test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p16n01i01507arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1508.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1508.vhd
new file mode 100644
index 0000000..ce5840e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1508.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1508.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01508ent IS
+END c08s09b00x00p02n01i01508ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01508arch OF c08s09b00x00p02n01i01508ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    loop
+      k := k + 1;
+      if k > 500 then
+        exit;
+      end if;
+    end loop;
+
+    assert FALSE 
+      report "***PASSED TEST: c08s09b00x00p02n01i01508"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01508arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1509.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1509.vhd
new file mode 100644
index 0000000..166adb5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1509.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1509.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01509ent IS
+END c08s09b00x00p02n01i01509ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01509arch OF c08s09b00x00p02n01i01509ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    L1 :
+    while counter < 10 loop
+      counter := counter + 1;
+    end loop L1;
+
+    assert NOT( counter = 10 ) 
+      report "***PASSED TEST: c08s09b00x00p02n01i01509"
+      severity NOTE;
+    assert ( counter = 10 ) 
+      report "***FAILED TEST: c08s09b00x00p02n01i01509 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01509arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1510.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1510.vhd
new file mode 100644
index 0000000..6046b3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1510.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1510.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01510ent IS
+END c08s09b00x00p02n01i01510ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01510arch OF c08s09b00x00p02n01i01510ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    while counter < 10 loop
+      counter := counter + 1;
+    end loop;
+
+    assert NOT( counter = 10 ) 
+      report "***PASSED TEST: c08s09b00x00p02n01i01510"
+      severity NOTE;
+    assert ( counter = 10 ) 
+      report "***FAILED TEST: c08s09b00x00p02n01i01510 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01510arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1511.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1511.vhd
new file mode 100644
index 0000000..bc852e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1511.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1511.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01511ent IS
+END c08s09b00x00p02n01i01511ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01511arch OF c08s09b00x00p02n01i01511ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    L2 :
+    for i in 1 to 10 loop
+      counter := counter + 1;
+    end loop L2;
+
+    assert NOT( counter = 10 ) 
+      report "***PASSED TEST: c08s09b00x00p02n01i01511"
+      severity NOTE;
+    assert ( counter = 10 ) 
+      report "***FAILED TEST: c08s09b00x00p02n01i01511 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01511arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1512.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1512.vhd
new file mode 100644
index 0000000..851b4fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1512.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1512.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01512ent IS
+END c08s09b00x00p02n01i01512ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01512arch OF c08s09b00x00p02n01i01512ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      counter := counter + 1;
+    end loop;
+
+    assert NOT( counter = 10 ) 
+      report "***PASSED TEST: c08s09b00x00p02n01i01512"
+      severity NOTE;
+    assert ( counter = 10 ) 
+      report "***FAILED TEST: c08s09b00x00p02n01i01512 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01512arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1514.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1514.vhd
new file mode 100644
index 0000000..ba9d1a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1514.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1514.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01514ent IS
+END c08s09b00x00p02n01i01514ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01514arch OF c08s09b00x00p02n01i01514ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 5 loop
+      k := k + 1;
+    end loop;
+
+    assert NOT( k = 5 ) 
+      report "***PASSED TEST: c08s09b00x00p02n01i01514" 
+      severity NOTE;
+    assert ( k = 5 ) 
+      report "***FAILED TEST: c08s09b00x00p02n01i01514 - Missing reserved word 'end loop' in a loop statement" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01514arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1516.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1516.vhd
new file mode 100644
index 0000000..d954196
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1516.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1516.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p03n01i01516ent IS
+END c08s09b00x00p03n01i01516ent;
+
+ARCHITECTURE c08s09b00x00p03n01i01516arch OF c08s09b00x00p03n01i01516ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MY_WORD is array (0 to 31) of BIT;
+    variable k : integer := 0;
+  BEGIN
+
+    for foo in integer range MY_WORD'range loop
+      k := k + 1;
+    end loop;
+    assert NOT(k = 32) 
+      report "***PASSED TEST: /c08s09b00x00p03n01i01516"
+      severity NOTE;
+    assert (k = 32) 
+      report "***FAILED TEST: c08s09b00x00p03n01i01516 - FOR loop with a discrete range specification"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p03n01i01516arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1521.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1521.vhd
new file mode 100644
index 0000000..7d3a2c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1521.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1521.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p05n01i01521ent IS
+END c08s09b00x00p05n01i01521ent;
+
+ARCHITECTURE c08s09b00x00p05n01i01521arch OF c08s09b00x00p05n01i01521ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    T:
+    while k < 5 loop
+      k := k + 1;
+    end loop T;
+    assert NOT(k = 5)
+      report "***PASSED TEST: c08s09b00x00p05n01i01521"
+      severity NOTE; 
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s09b00x00p05n01i01521 - Syntax of a labeled while loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p05n01i01521arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1522.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1522.vhd
new file mode 100644
index 0000000..492b76d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1522.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1522.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p07n01i01522ent IS
+END c08s09b00x00p07n01i01522ent;
+
+ARCHITECTURE c08s09b00x00p07n01i01522arch OF c08s09b00x00p07n01i01522ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L1 : Loop
+      k := k + 1;
+      if (k = 20) then
+        assert FALSE
+          report "PASSED TEST: c08s09b00x00p07n01i01522 - test executing indefinetely"
+          severity NOTE;
+      end if;
+      if (k > 50) then
+        exit;
+      end if;
+    end loop L1;
+    assert ( k<50 )
+      report "***PASSED TEST: c08s09b00x00p07n01i01522 - Loop statement without an iteration scheme specifies repeated execution of the statement"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p07n01i01522arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1523.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1523.vhd
new file mode 100644
index 0000000..b44e6e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1523.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1523.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s09b00x00p07n01i01523pkg is
+
+  -- Global procedure.
+  procedure proc1;
+
+  -- Global function.
+  function  func1 return INTEGER;
+
+end c08s09b00x00p07n01i01523pkg;
+
+package body c08s09b00x00p07n01i01523pkg is
+
+  procedure proc1 is
+    -- Local variables
+    variable  INTV  : INTEGER := 0;
+
+  begin
+    -- Check initialization.
+    assert (INTV = 0);
+
+    -- Loop until the indicated condition has been met.
+    loop
+      -- Execute some meaningful function.
+      null;
+
+      -- Increment the counter.
+      INTV := INTV + 1;
+
+      -- If the condition has been met, terminate the loop.
+      if  (INTV = 10) then
+        return;
+      end if;
+
+      -- Verify that we have not exceeded the limits of the loop.
+      assert (INTV < 10);
+    end loop;
+    
+    -- Should NEVER get to this step.
+    assert (FALSE)
+      report "Return has not exited the procedure.";
+  end proc1;
+  
+  function func1 return INTEGER is
+    -- Local variables
+    variable  INTV  : INTEGER := 0;
+    
+  begin
+    -- Check initialization.
+    assert (INTV = 0);
+    
+    -- Loop until the indicated condition has been met.
+    loop
+      -- Execute some meaningful function.
+      null;
+      -- Increment the counter.
+      INTV := INTV + 1;
+      
+      -- If the condition has been met, terminate the loop.
+      if  (INTV = 10) then
+        return( INTV );
+      end if;
+      
+      -- Verify that we have not exceeded the limits of the loop.
+      assert (INTV < 10);
+    end loop;
+    
+    -- Should NEVER get to this step.
+    assert (FALSE)
+      report "Return has not exited the procedure.";
+  end func1;
+  
+end c08s09b00x00p07n01i01523pkg;
+
+use work.c08s09b00x00p07n01i01523pkg.all;
+ENTITY c08s09b00x00p07n01i01523ent IS
+END c08s09b00x00p07n01i01523ent;
+
+ARCHITECTURE c08s09b00x00p07n01i01523arch OF c08s09b00x00p07n01i01523ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    -- Call procedure to loop/return.
+    proc1;
+    
+    assert NOT(func1=10)
+      report "***PASSED TEST: c08s09b00x00p07n01i01523" 
+      severity NOTE;
+    assert (func1=10)
+      report "***PASSED TEST: c08s09b00x00p07n01i01523 - Function did not return proper value." 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p07n01i01523arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1524.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1524.vhd
new file mode 100644
index 0000000..7619eb1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1524.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1524.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p08n01i01524ent IS
+END c08s09b00x00p08n01i01524ent;
+
+ARCHITECTURE c08s09b00x00p08n01i01524arch OF c08s09b00x00p08n01i01524ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    while k > 3 loop
+      k := k + 1;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p08n01i01524"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p08n01i01524 - For a loop statement with a while iteration scheme, if the condition is evaluated to be FALSE, the execution of the loop statement is complete"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p08n01i01524arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1529.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1529.vhd
new file mode 100644
index 0000000..64e010a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1529.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1529.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p08n01i01529ent IS
+END c08s09b00x00p08n01i01529ent;
+
+ARCHITECTURE c08s09b00x00p08n01i01529arch OF c08s09b00x00p08n01i01529ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable INTV   : INTEGER := 0;
+    variable COUNTV : INTEGER := 0;
+    variable I      : INTEGER := 0;
+    variable   k      : integer := 0;
+  BEGIN
+
+    -- While condition is FALSE, so no stmts are executed.
+    while (FALSE) loop
+      assert (FALSE)
+        report "First loop was executed when it should not have been.";
+      k := 1;
+    end loop;
+
+    -- While condition is FALSE, so no stmts are executed.
+    while (I /= 0) loop
+      assert (FALSE)
+        report "Second loop was executed when it should not have been.";
+      k := 1;
+    end loop;
+
+    -- Verify that loop is executed right number of times.
+    COUNTV := 0;
+    while (I /= 10) loop
+      I := I + 1;
+      COUNTV := COUNTV + 1;
+    end loop;
+    if (I /= 10 and COUNTV /= 10) then
+      k := 1;
+    end if;
+    assert (I = 10);
+    assert (COUNTV = 10);
+
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s09b00x00p08n01i01529"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s09b00x00p08n01i01529 - while condition is not boolean expression" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p08n01i01529arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1530.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1530.vhd
new file mode 100644
index 0000000..8fa6eb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1530.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1530.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n01i01530ent IS
+END c08s09b00x00p09n01i01530ent;
+
+ARCHITECTURE c08s09b00x00p09n01i01530arch OF c08s09b00x00p09n01i01530ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable VAR    : REAL := 0.0;
+    variable k : integer := 0;
+  BEGIN
+    -- Outer scope's declaration of VAR is of type REAL.
+    assert (VAR = 0.0);
+    if (VAR /= 0.0) then
+      k := 1;
+    end if;
+
+    -- Loop using VAR as an integer.
+    for VAR in 0 to 10 loop
+      -- Verify that inner declaration is of type INTEGER.
+      assert (VAR <= 10);
+      if (VAR > 10) then
+        k := 1;
+      end if;
+    end loop;
+
+    -- Outer scope's declaration of VAR is of type REAL.
+    assert (VAR = 0.0);
+    if (VAR /= 0.0) then
+      k := 1;
+    end if;
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p09n01i01530"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p09n01i01530 - The loop parameter specification is the declaration of the loop parameter with a given identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n01i01530arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1531.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1531.vhd
new file mode 100644
index 0000000..6968c26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1531.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1531.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n02i01531ent IS
+END c08s09b00x00p09n02i01531ent;
+
+ARCHITECTURE c08s09b00x00p09n02i01531arch OF c08s09b00x00p09n02i01531ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    COLORS is (RED, GREEN, BLUE);
+    type    MYFAVS is (RED, YELLOW, GREEN);
+
+    -- variable declarations.
+    variable COLSLOW      : COLORS := RED;
+    variable COLSHIGH     : COLORS := GREEN;
+    variable FAVSLOW      : MYFAVS := RED;
+    variable FAVSHIGH     : MYFAVS := GREEN;
+
+    variable k : integer := 0;
+  BEGIN
+    -- This loop should be fine.
+    for I in COLSLOW to COLSHIGH loop
+      if not((I >= COLSLOW) and (I <= COLSHIGH)) then
+        k := 1;
+      end if;
+    end loop;
+
+    -- This loop should be fine.
+    for I in FAVSLOW to FAVSHIGH loop
+      if not((I >= FAVSLOW) and (I <= FAVSHIGH)) then
+        k := 1;
+      end if;
+    end loop;
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p09n02i01531"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p09n02i01531 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n02i01531arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1536.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1536.vhd
new file mode 100644
index 0000000..fbf25ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1536.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1536.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n03i01536ent IS
+END c08s09b00x00p09n03i01536ent;
+
+ARCHITECTURE c08s09b00x00p09n03i01536arch OF c08s09b00x00p09n03i01536ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : integer := 10;
+  BEGIN
+    for i in 1 to 5 loop
+      k := i;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s09b00x00p09n03i01536"
+      severity NOTE;
+    assert ( k=5 ) 
+      report "***FAILED TEST: c08s09b00x00p09n03i01536 -  The loop parameter can be the source of an assignment statement (but not the target)" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n03i01536arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1539.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1539.vhd
new file mode 100644
index 0000000..435e069
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1539.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1539.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01539ent IS
+END c08s09b00x00p10n01i01539ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01539arch OF c08s09b00x00p10n01i01539ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 5 loop
+      k := k + 1;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s09b00x00p10n01i01539"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s09b00x00p10n01i01539 - The sequence of statements is executed once for each value of the discrete range"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01539arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc154.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc154.vhd
new file mode 100644
index 0000000..764c204
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc154.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc154.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p16n01i00154pkg is
+  procedure P1 (a  : in integer; b: inout integer);
+  function  F1 (I1 : in integer) return real;
+  function  F2 (I2 : in real) return integer;
+end c04s03b02x02p16n01i00154pkg;
+
+package body c04s03b02x02p16n01i00154pkg is
+  procedure P1 (a  : in integer; b: inout integer) is
+  begin
+    b := a;
+  end P1;
+
+  function  F1 (I1 : in integer) return real is
+  begin
+    return 10.0;
+  end F1;
+
+  function  F2 (I2 : in real) return integer is
+  begin
+    return 10;
+  end F2;
+end c04s03b02x02p16n01i00154pkg;
+
+
+use work.c04s03b02x02p16n01i00154pkg.all;
+ENTITY c04s03b02x02p16n01i00154ent IS
+END c04s03b02x02p16n01i00154ent;
+
+ARCHITECTURE c04s03b02x02p16n01i00154arch OF c04s03b02x02p16n01i00154ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    variable x : real := 1.0;
+  BEGIN
+    P1 (10, F1(b) => F2(x));  -- No_failure_here
+    assert NOT(F2(x) = 10)
+      report "***PASSED TEST: c04s03b02x02p16n01i00154"
+      severity NOTE;
+    assert (F2(x) = 10)
+      report "***FAILED TEST: c04s03b02x02p16n01i00154 - Types of the actuals match those of the formals test failed.."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p16n01i00154arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1540.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1540.vhd
new file mode 100644
index 0000000..168deff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1540.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1540.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01540ent IS
+END c08s09b00x00p10n01i01540ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01540arch OF c08s09b00x00p10n01i01540ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for j in 1 to 100 loop
+      for i in 1 to 5 loop
+        k := k + 1;
+      end loop;
+    end loop;
+    assert NOT( k=500 )
+      report "***PASSED TEST: c08s09b00x00p10n01i01540"
+      severity NOTE;
+    assert ( k=500 )
+      report "***FAILED TEST: c08s09b00x00p10n01i01540 - The sequence of statements is executed once for each value of the discrete range"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01540arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1543.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1543.vhd
new file mode 100644
index 0000000..33618c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1543.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1543.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01543ent IS
+END c08s09b00x00p10n01i01543ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01543arch OF c08s09b00x00p10n01i01543ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    for i in boolean loop
+      counter := counter + 1;
+    end loop;
+    assert NOT(counter=boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1) 
+      report "***PASSED TEST: c08s09b00x00p10n01i01543" 
+      severity NOTE;
+    assert (counter=boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1) 
+      report "***FAILED TEST: c08s09b00x00p10n01i01543 - The loop is executed once for each of the values in the range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01543arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1544.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1544.vhd
new file mode 100644
index 0000000..a4a2f02
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1544.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1544.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01544ent IS
+END c08s09b00x00p10n01i01544ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01544arch OF c08s09b00x00p10n01i01544ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    for i in bit loop
+      counter := counter + 1;
+    end loop;
+    assert NOT(counter=bit'Pos(bit'High)-bit'Pos(bit'Low)+1) 
+      report "***PASSED TEST: c08s09b00x00p10n01i01544" 
+      severity NOTE;
+    assert (counter=bit'Pos(bit'High)-bit'Pos(bit'Low)+1) 
+      report "***FAILED TEST: c08s09b00x00p10n01i01544 - The loop is executed once for each of the values in the range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01544arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1545.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1545.vhd
new file mode 100644
index 0000000..bfe2343
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1545.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1545.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01545ent IS
+END c08s09b00x00p10n01i01545ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01545arch OF c08s09b00x00p10n01i01545ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    for i in severity_level loop
+      counter := counter + 1;
+    end loop;
+    assert NOT(counter=severity_level'Pos(severity_level'High)-severity_level'Pos(severity_level'Low)+1) 
+      report "***PASSED TEST: c08s09b00x00p10n01i01545"
+      severity NOTE;
+    assert (counter=severity_level'Pos(severity_level'High)-severity_level'Pos(severity_level'Low)+1) 
+      report "***FAILED TEST: c08s09b00x00p10n01i01545 - The loop is executed once for each of the values in the range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01545arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1546.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1546.vhd
new file mode 100644
index 0000000..904fb79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1546.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1546.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01546ent IS
+END c08s09b00x00p10n01i01546ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01546arch OF c08s09b00x00p10n01i01546ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable counter : integer := 0;
+  BEGIN
+    for i in character loop
+      counter := counter + 1;
+    end loop;
+    assert NOT(counter=character'Pos(character'High)-character'Pos(character'Low)+1) 
+      report "***PASSED TEST: c08s09b00x00p10n01i01546" 
+      severity NOTE;
+    assert (counter=character'Pos(character'High)-character'Pos(character'Low)+1) 
+      report "***FAILED TEST: c08s09b00x00p10n01i01546 - The loop is executed once for each of the values in the range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01546arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1547.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1547.vhd
new file mode 100644
index 0000000..1fbdfe7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1547.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1547.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01547ent IS
+END c08s09b00x00p10n01i01547ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01547arch OF c08s09b00x00p10n01i01547ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     t_enum1 is (en1, en2, en3, en4) ;
+    subtype  st_enum1 is t_enum1 range en4 downto en1 ;
+    variable counter : integer := 0;
+  BEGIN
+    for i in st_enum1 loop
+      counter := counter + 1;
+    end loop;
+    assert NOT(counter=st_enum1'Pos(st_enum1'High)-st_enum1'Pos(st_enum1'Low)+1) 
+      report "***PASSED TEST: c08s09b00x00p10n01i01547" 
+      severity NOTE;
+    assert (counter=st_enum1'Pos(st_enum1'High)-st_enum1'Pos(st_enum1'Low)+1) 
+      report "***FAILED TEST: c08s09b00x00p10n01i01547 - The loop is executed once for each of the values in the range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01547arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1548.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1548.vhd
new file mode 100644
index 0000000..20b58fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1548.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1548.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01548ent IS
+END c08s09b00x00p10n01i01548ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01548arch OF c08s09b00x00p10n01i01548ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    COLORS is (RED, GREEN, BLUE);
+    variable k : integer := 0;
+  BEGIN
+
+    -- None of these loops should EVER execute any of their statements.
+    for I in INTEGER'HIGH to 0 loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+
+    for I in INTEGER'HIGH to INTEGER'HIGH-1 loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+
+    for I in INTEGER'LOW downto 0 loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+    
+    for I in INTEGER'LOW downto INTEGER'LOW + 1 loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+    
+    for I in COLORS'HIGH to COLORS'LOW loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+    
+    for I in COLORS'HIGH to COLORS'PRED( COLORS'HIGH ) loop    
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+    
+    for I in COLORS'LOW downto COLORS'HIGH loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+    
+    for I in COLORS'LOW downto COLORS'SUCC( COLORS'LOW ) loop
+      assert (FALSE)
+        report "For-loop executed once when it should never have been executed.";
+      k := 1;
+    end loop;
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p10n01i01548"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p10n01i01548 - The sequence of statements is executed once for each value of the discrete range"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01548arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1549.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1549.vhd
new file mode 100644
index 0000000..a38fa83
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1549.vhd
@@ -0,0 +1,178 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1549.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01549ent IS
+END c08s09b00x00p10n01i01549ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01549arch OF c08s09b00x00p10n01i01549ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    COLORS is (RED, GREEN, BLUE);
+    -- local variables
+    variable EXECUTED_ONCE : BOOLEAN;
+    variable COUNT         : INTEGER;
+    variable k : integer := 0;
+  BEGIN
+    -- 1. These for-loops should only execute one time.
+    EXECUTED_ONCE := FALSE;
+    for I in INTEGER'HIGH to INTEGER'HIGH loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in first loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+
+    EXECUTED_ONCE := FALSE;
+    for I in INTEGER'LOW to INTEGER'LOW loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in second loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+
+    EXECUTED_ONCE := FALSE;
+    for I in INTEGER'HIGH downto INTEGER'HIGH loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in third loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+    
+    EXECUTED_ONCE := FALSE;
+    for I in INTEGER'LOW downto INTEGER'LOW loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in fourth loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+    
+    EXECUTED_ONCE := FALSE;
+    for I in COLORS'HIGH to COLORS'HIGH loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in fifth loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+
+    EXECUTED_ONCE := FALSE;
+    for I in COLORS'LOW to COLORS'LOW loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in sixth loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+
+    EXECUTED_ONCE := FALSE;
+    for I in COLORS'HIGH downto COLORS'HIGH loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in seventh loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+    
+    EXECUTED_ONCE := FALSE;
+    for I in COLORS'LOW downto COLORS'LOW loop
+      if (EXECUTED_ONCE) then
+        k := 1;
+      end if;
+      assert (not( EXECUTED_ONCE ))
+        report "Failing in eighth loop.";
+      EXECUTED_ONCE := TRUE;
+    end loop;
+
+    -- 2. These for-loops should be executed COUNT number of times.
+    COUNT := 0;
+    for I in 3 to 13 loop
+      COUNT := COUNT + 1;
+    end loop;
+    if (count /= 11) then
+      k := 1;
+    end if;
+    assert (COUNT = 11)
+      report "Failing in 9th loop.";
+    
+    COUNT := 0;
+    for I in 13 downto 3 loop
+      COUNT := COUNT + 1;
+    end loop;
+    if (count /= 11) then
+      k := 1;
+    end if;
+    assert (COUNT = 11)
+      report "Failing in 10th loop.";
+    
+    COUNT := 0;
+    for I in COLORS'LOW to COLORS'HIGH loop
+      COUNT := COUNT + 1;
+    end loop;
+    if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
+      k := 1;
+    end if;
+    assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
+      report "Failing in 11th loop.";
+    
+    COUNT := 0;
+    for I in COLORS'HIGH downto COLORS'LOW loop
+      COUNT := COUNT + 1;
+    end loop;
+    if (count /= (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1)) then
+      k := 1;
+    end if;
+    assert (COUNT = (COLORS'POS( COLORS'HIGH ) - COLORS'POS( COLORS'LOW ) + 1))
+      report "Failing in 12th loop.";
+
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p10n01i01549"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p10n01i01549 - The sequence of statements is executed once for each value of the discrete range"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01549arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1550.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1550.vhd
new file mode 100644
index 0000000..5719e98
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1550.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1550.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01550ent IS
+END c08s09b00x00p10n01i01550ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01550arch OF c08s09b00x00p10n01i01550ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type colors is (red, yellow, blue);
+    variable k : integer := 0;
+  BEGIN
+    --
+    -- Test for loop; loop should initialize
+    -- the loop variable and sequence through
+    -- all three colors if implemented correctly
+    --
+    -- 'c' is declared in the loop parameter spec.
+    --
+    L1: for c in red to blue loop
+      case c is
+        when red =>
+          k := k + 1;
+        when yellow =>
+          k := k + 10;
+        when blue =>
+          k := k + 100;
+        when others =>
+          k := 0;
+      end case;
+    end loop L1;
+
+    assert NOT( k=111 )
+      report "***PASSED TEST: c08s09b00x00p10n01i01550"
+      severity NOTE;
+    assert ( k=111 )
+      report "***FAILED TEST: c08s09b00x00p10n01i01550 - The loop parameter is declared by its appearance in the loop parameter specification and its scope is limited to the loop statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01550arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1551.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1551.vhd
new file mode 100644
index 0000000..c30c0bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1551.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1551.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n03i01551ent IS
+END c08s09b00x00p10n03i01551ent;
+
+ARCHITECTURE c08s09b00x00p10n03i01551arch OF c08s09b00x00p10n03i01551ent IS
+
+  type t1 is (a,b);
+  type t2 is (b,c);
+  type t3 is (c,d);
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in c downto b loop
+      k := 5;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s09b00x00p10n03i01551"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s09b00x00p10n03i01551 - Each iteration of a loop statement with a for iteration scheme, the corresponding value of the discrete range is assigned to the loop parameter, these values are assigned in left to rigth order"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n03i01551arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1552.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1552.vhd
new file mode 100644
index 0000000..d2b54ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1552.vhd
@@ -0,0 +1,150 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1552.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n03i01552ent IS
+END c08s09b00x00p10n03i01552ent;
+
+ARCHITECTURE c08s09b00x00p10n03i01552arch OF c08s09b00x00p10n03i01552ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- enumerated type.
+    type    COLORS is (RED, GREEN, BLUE, ORANGE, PINK, GRAY, YELLOW);
+
+    -- local variables
+    variable EXECUTED_ONCE : BOOLEAN;
+    variable LAST_INT      : INTEGER;
+    variable LAST_COLOR    : COLORS;
+
+    variable k : integer := 0;
+  BEGIN
+    -- 1. Test ascending and descending integer discrete ranges.
+    EXECUTED_ONCE := FALSE;
+    LAST_INT := INTEGER'LOW + 1;
+    for I in (INTEGER'LOW+1) to (INTEGER'LOW + 10) loop
+      -- Verify that the first value is correct.
+      if  (not(EXECUTED_ONCE)) then
+        if (I /= (integer'low + 1)) then
+          k := 1;
+        end if;
+        assert (I = (INTEGER'LOW+1))
+          report "First value is bad.";
+        EXECUTED_ONCE := TRUE;
+        
+        -- Otherwise, test that this value is to the right of the previous one.
+      else
+        if (integer'succ(last_int) /= I) then
+          k := 1;
+        end if;
+        assert (INTEGER'SUCC( LAST_INT ) = I)
+          report "Subsequent values are bad.";
+        LAST_INT := I;
+      end if;
+    end loop;
+    
+    EXECUTED_ONCE := FALSE;
+    LAST_INT := INTEGER'HIGH - 1;
+    for I in (INTEGER'HIGH-1) downto (INTEGER'HIGH - 10) loop
+      -- Verify that the first value is correct.
+      if  (not(EXECUTED_ONCE)) then
+        if (I /= integer'high-1) then
+          k := 1;
+        end if;
+        assert (I = (INTEGER'HIGH-1))
+          report "First value, second loop, is bad.";
+        EXECUTED_ONCE := TRUE;
+        
+        -- Otherwise, test that this value is to the right of the previous one.
+      else
+        if (integer'pred(last_int) /= I) then
+          k := 1;
+        end if;
+        assert (INTEGER'PRED( LAST_INT ) = I)
+          report "Subsequent values, second loop, are bad.";
+        LAST_INT := I;
+      end if;
+    end loop;
+    
+    -- 2. Test ascending and descending enumerated type ranges.
+    EXECUTED_ONCE := FALSE;
+    LAST_COLOR := COLORS'SUCC( COLORS'LOW );
+    for I in (COLORS'SUCC( COLORS'LOW )) to (COLORS'HIGH) loop
+      -- Verify that the first value is correct.
+      if  (not(EXECUTED_ONCE)) then
+        if (I /= colors'succ(colors'low)) then
+          k := 1;
+        end if;
+        assert (I = (COLORS'SUCC( COLORS'LOW )))
+          report "First value, third loop, is bad.";
+        EXECUTED_ONCE := TRUE;
+        -- Otherwise, test that this value is to the right of the previous one.
+      else
+        if (colors'succ(last_color) /= I) then
+          k := 1;
+        end if;
+        assert (COLORS'SUCC( LAST_COLOR ) = I)
+          report "Subsequent values, third loop, are bad.";
+        LAST_COLOR := I;
+      end if;
+    end loop;
+    
+    EXECUTED_ONCE := FALSE;
+    LAST_COLOR := COLORS'PRED( COLORS'HIGH );
+    for I in (COLORS'PRED( COLORS'HIGH )) downto (COLORS'LOW) loop
+      -- Verify that the first value is correct.
+      if  (not(EXECUTED_ONCE)) then
+        if (I /= colors'pred(colors'high)) then
+          k := 1;
+        end if;
+        assert (I = (COLORS'PRED( COLORS'HIGH )))
+          report "First value, fourth loop, is bad.";
+        EXECUTED_ONCE := TRUE;
+        
+        -- Otherwise, test that this value is to the right of the previous one.
+      else
+        if (colors'pred(last_color) /= I) then
+          k := 1;
+        end if;
+        assert (COLORS'PRED( LAST_COLOR ) = I)
+          report "Subsequent values, fourth loop, are bad.";
+        LAST_COLOR := I;
+      end if;
+    end loop;
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s09b00x00p10n03i01552"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s09b00x00p10n03i01552 - Each iteration of a loop statement with a for iteration scheme, the corresponding value of the discrete range is assigned to the loop parameter, these values are assigned in left to rigth order"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n03i01552arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1553.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1553.vhd
new file mode 100644
index 0000000..6ea4d5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1553.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1553.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01553ent IS
+END c08s09b00x00p10n01i01553ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01553arch OF c08s09b00x00p10n01i01553ent IS
+  signal VS : STRING(1 to 14) := "This is a test";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for i in VS'range loop
+      VS <= VS(VS'LEFT + 1 to VS'RIGHT) & '_' after 1 ns;
+      wait for 2 ns;
+    end loop;
+    wait for 5 ns;
+    assert NOT( VS = "______________" )
+      report "***PASSED TEST: c08s09b00x00p10n01i01553"
+      severity NOTE;
+    assert ( VS = "______________" )
+      report "***FAILED TEST: c08s09b00x00p10n01i01553 - The loop parameter is declared by its appearance in the loop parameter specification and its scope is limited to the loop statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01553arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1554.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1554.vhd
new file mode 100644
index 0000000..554ff86
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1554.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1554.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p02n01i01554ent IS
+END c08s10b00x00p02n01i01554ent;
+
+ARCHITECTURE c08s10b00x00p02n01i01554arch OF c08s10b00x00p02n01i01554ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      next;
+      k := 5;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s10b00x00p02n01i01554"
+      severity NOTE;
+    assert (k=0)
+      report "***FAILED TEST: c08s10b00x00p02n01i01554 - A next statement is allowed in a loop without a label"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p02n01i01554arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1555.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1555.vhd
new file mode 100644
index 0000000..60ca71e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1555.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1555.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p02n01i01555ent IS
+END c08s10b00x00p02n01i01555ent;
+
+ARCHITECTURE c08s10b00x00p02n01i01555arch OF c08s10b00x00p02n01i01555ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L1 : for i in 1 to 10 loop
+      next L1;
+      k := 5;
+    end loop L1;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s10b00x00p02n01i01555"
+      severity NOTE;
+    assert (k=0)
+      report "***FAILED TEST: c08s10b00x00p02n01i01555 - The when clause is optional" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p02n01i01555arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1558.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1558.vhd
new file mode 100644
index 0000000..2143938
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1558.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1558.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01558ent IS
+END c08s10b00x00p03n01i01558ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01558arch OF c08s10b00x00p03n01i01558ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      next L;
+      k := 5;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s10b00x00p03n01i01558"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s10b00x00p03n01i01558 - a next statement with a loop label is allowed inside a labeled loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01558arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1560.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1560.vhd
new file mode 100644
index 0000000..9f611d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1560.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1560.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01560ent IS
+END c08s10b00x00p03n01i01560ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01560arch OF c08s10b00x00p03n01i01560ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable s : integer := 0;
+  BEGIN
+    K : for j in 1 to 10 loop
+      L : for i in 1 to 10 loop
+        next K when ( (j = 3) and (i = 1) );
+        s := s + 1;
+      end loop L;
+    end loop K;
+    assert NOT(s = 90) 
+      report "***PASSED TEST: c08s10b00x00p03n01i01560"
+      severity NOTE;
+    assert (s = 90) 
+      report "***FAILED TEST: c08s10b00x00p03n01i01560 - A next statement with a loop label inside a labeled loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01560arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1565.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1565.vhd
new file mode 100644
index 0000000..ac40569
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1565.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1565.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01565ent IS
+END c08s10b00x00p03n01i01565ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01565arch OF c08s10b00x00p03n01i01565ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      next when i = 3;
+      k := k + 1;
+    end loop;
+    assert NOT( k=9 ) 
+      report "***PASSED TEST: c08s10b00x00p03n01i01565"
+      severity NOTE;
+    assert ( k=9 ) 
+      report "***FAILED TEST: c08s10b00x00p03n01i01565 - A NEXT statement must be inside a loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01565arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1566.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1566.vhd
new file mode 100644
index 0000000..c7cd1e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1566.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1566.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01566ent IS
+END c08s10b00x00p03n01i01566ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01566arch OF c08s10b00x00p03n01i01566ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    P : for j in 1 to 10 loop
+      L : for i in 1 to 10 loop
+        next when j = 3;
+        k := k + 1;
+      end loop L;
+    end loop;
+    assert NOT( k=90 ) 
+      report "***PASSED TEST: c08s10b00x00p03n01i01566"
+      severity NOTE;
+    assert ( k=90 ) 
+      report "***FAILED TEST: c08s10b00x00p03n01i01566 - A NEXT statement inside nested FOR loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01566arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1567.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1567.vhd
new file mode 100644
index 0000000..84597ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1567.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1567.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01567ent IS
+END c08s10b00x00p03n01i01567ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01567arch OF c08s10b00x00p03n01i01567ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 0;
+  BEGIN
+    L1: for i in boolean loop
+      k := 5;
+      L2: for j in 1 to 3 loop
+        next L2;
+        k := 3;
+      end loop L2;
+      m := m + 1;
+    end loop L1;
+    assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***PASSED TEST: c08s10b00x00p03n01i01567"
+      severity NOTE;
+    assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***FAILED TEST: c08s10b00x00p03n01i01567 - A next statement with a loop label is only allowed within the labeled loop, and applies to that loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01567arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1568.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1568.vhd
new file mode 100644
index 0000000..6278635
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1568.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1568.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01568ent IS
+END c08s10b00x00p03n01i01568ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01568arch OF c08s10b00x00p03n01i01568ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant c_boolean_2 : boolean := true;
+    variable v_boolean   : boolean := false;
+    variable counter     : integer := 0;
+  BEGIN
+    L1 :
+    while v_boolean /= c_boolean_2 loop
+      v_boolean := c_boolean_2 ;
+      for j in 1 to 3 loop
+        next L1 when j = j ;
+      end loop ;
+      counter := counter + 1 ;
+    end loop L1;
+    assert NOT( counter = 0 )
+      report "***PASSED TEST: c08s10b00x00p03n01i01568"
+      severity NOTE;
+    assert ( counter = 0 )
+      report "***FAILED TEST: c08s10b00x00p03n01i01568 - A next statement with a loop label is only allowed within the labeled loop, and applies to that loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01568arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1569.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1569.vhd
new file mode 100644
index 0000000..11f6552
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1569.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1569.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01569ent IS
+END c08s10b00x00p03n01i01569ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01569arch OF c08s10b00x00p03n01i01569ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 0;
+  BEGIN
+    L1: for i in boolean loop
+      k := 5;
+      L2: for j in 1 to 3 loop
+        next;
+        k := 3;
+      end loop L2;
+      m := m + 1;
+    end loop L1;
+    assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***PASSED TEST: c08s10b00x00p03n01i01569"
+      severity NOTE;
+    assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***FAILED TEST: c08s10b00x00p03n01i01569 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01569arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc157.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc157.vhd
new file mode 100644
index 0000000..b2dac23
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc157.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc157.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p18n01i00157ent IS
+END c04s03b02x02p18n01i00157ent;
+
+ARCHITECTURE c04s03b02x02p18n01i00157arch OF c04s03b02x02p18n01i00157ent IS
+  TYPE TwoBy3By4Type IS ARRAY (1 TO 2,1 TO 3,1 TO 4) OF integer RANGE 111 TO 234;
+
+  FUNCTION func1(fp1:TwoBy3By4Type:=
+                 (
+                   (  (111,112,113,114),
+                      (121,122,123,124),
+                      (131,132,133,134) ),
+
+                   (  (211,212,213,214),
+                      (221,222,223,224),
+                      (231,232,233,234) )
+                   )) RETURN BOOLEAN;
+
+  FUNCTION func1(fp1:TwoBy3By4Type:=
+                 (
+                   (  (111,112,113,114),
+                      (121,122,123,124),
+                      (131,132,133,134) ),
+
+                   (  (211,212,213,214),
+                      (221,222,223,224),
+                      (231,232,233,234) )
+                   )) RETURN BOOLEAN IS
+    VARIABLE fv1 : TwoBy3By4Type :=
+      (
+        (  (111,112,113,114),
+           (121,122,123,124),
+           (131,132,133,134) ),
+
+        (  (211,212,213,214),
+           (221,222,223,224),
+           (231,232,233,234) )
+        );
+  BEGIN
+    RETURN ((fv1 = fp1) AND (fp1(2,2,3) = 223));
+  END;
+
+BEGIN
+  TESTING: PROCESS
+    
+    VARIABLE v1,v2 : TwoBy3By4Type :=
+      (
+        (  (111,112,113,114),
+           (121,122,123,124),
+           (131,132,133,134) ),
+        
+        (  (211,212,213,214),
+           (221,222,223,224),
+           (231,232,233,234) )
+        );
+    
+  BEGIN
+    wait for 5 ns;
+    assert NOT( func1(v1))
+      report "***PASSED TEST: c04s03b02x02p18n01i00157"
+      severity NOTE;
+    assert ( func1(v1))
+      report "***FAILED TEST: c04s03b02x02p18n01i00157 - Multi-dimensional array test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p18n01i00157arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1570.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1570.vhd
new file mode 100644
index 0000000..28202ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1570.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1570.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01570ent IS
+END c08s10b00x00p03n01i01570ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01570arch OF c08s10b00x00p03n01i01570ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer    := 0;
+    variable m : integer    := 0;
+    variable done : boolean := false;
+  BEGIN
+    L1: for i in boolean loop
+      k := 5;
+      while not done loop
+        done := true ;
+        next ;
+        k := 3;
+      end loop ;
+      m := m + 1;
+    end loop L1;
+    assert NOT(( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***PASSED TEST: c08s10b00x00p03n01i01570"
+      severity NOTE;
+    assert (( k=5 ) and (m= boolean'Pos(boolean'High) - boolean'Pos(boolean'Low) + 1))
+      report "***FAILED TEST: c08s10b00x00p03n01i01570 - A next statement is used without a loop label, it occurs only within a loop and it refers to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01570arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1571.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1571.vhd
new file mode 100644
index 0000000..767953c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1571.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1571.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01571ent IS
+END c08s10b00x00p03n01i01571ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01571arch OF c08s10b00x00p03n01i01571ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant c_boolean_2 : boolean := true;
+    variable v_boolean   : boolean := false;
+    variable counter     : integer := 0;
+  BEGIN
+    L1 :
+    while v_boolean /= c_boolean_2 loop
+      v_boolean := c_boolean_2 ;
+      for j in 1 to 3 loop
+        next when j = j ;
+      end loop ;
+      counter := counter + 1 ;
+    end loop L1;
+    assert NOT( counter = 1 )
+      report "***PASSED TEST: c08s10b00x00p03n01i01571"
+      severity NOTE;
+    assert ( counter = 1 )
+      report "***FAILED TEST: c08s10b00x00p03n01i01571 - A next statement with a loop label is only allowed within the labeled loop, and applies to that loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01571arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1572.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1572.vhd
new file mode 100644
index 0000000..aab8f82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1572.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1572.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01572ent IS
+END c08s10b00x00p03n01i01572ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01572arch OF c08s10b00x00p03n01i01572ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local variables
+    variable DIDIT    : BOOLEAN;
+    variable CONSTONE : INTEGER := 1;
+    variable k    : integer := 0;
+  BEGIN
+    -- TEST1:  Should always go to outer loop.
+    OUTERLOOP:
+    for I in 1 to 10 loop
+
+      INNERLOOP:
+      for J in 1 to 10 loop
+        -- Skip to next iteration of outerloop.
+        next OUTERLOOP;
+
+        k := 1;
+        -- This should never be executed.
+        assert (FALSE)
+          report "Statement should never be executed.";
+      end loop INNERLOOP;
+
+      k := 1;
+      -- This should never be executed.
+      assert (FALSE)
+        report "Statement should never be executed.";
+    end loop OUTERLOOP;
+    
+    -- TEST2:  Should always go to inner loop.
+    -- Set the flag initially.
+    DIDIT := TRUE;
+    
+    -- Execute the loops.
+    OUTERLOOP2:
+    for I in 1 to 10 loop
+      
+      INNERLOOP2:
+      for J in 1 to 10 loop
+        -- Check that last statement of OUTERLOOP2 got done.
+        if  (J = 1) then
+          assert (DIDIT)
+            report "Last statement of OUTERLOOP2 was not executed.";
+          if (DIDIT /= true) then   
+            k := 1;
+          end if;
+          DIDIT := FALSE;
+        end if;
+        
+        -- Skip to next iteration of outerloop.
+        next INNERLOOP2;
+        k := 1; 
+        -- This should never be executed.
+        assert (FALSE)
+          report "Statement should never be executed.";
+      end loop INNERLOOP2;
+      
+      -- This should ALWAYS be executed.
+      DIDIT := TRUE;
+    end loop OUTERLOOP2;
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s10b00x00p03n01i01572"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s10b00x00p03n01i01572 - The NEXT statement did not properly associated with the loop whose label it matchs." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01572arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1573.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1573.vhd
new file mode 100644
index 0000000..a7536bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1573.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1573.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01573ent IS
+END c08s10b00x00p04n01i01573ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01573arch OF c08s10b00x00p04n01i01573ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      next when i > 5;
+      k := k + 1;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s10b00x00p04n01i01573"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s10b00x00p04n01i01573 - The current iteration of the loop is terminated if the value of the condition is TRUE"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01573arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1574.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1574.vhd
new file mode 100644
index 0000000..2bd2bd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1574.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1574.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01574ent IS
+END c08s10b00x00p04n01i01574ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01574arch OF c08s10b00x00p04n01i01574ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      next L when i > 5;
+      k := k + 1;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s10b00x00p04n01i01574"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s10b00x00p04n01i01574 - The current iteration of the loop is terminated if the value of the condition is TRUE"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01574arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1576.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1576.vhd
new file mode 100644
index 0000000..87f7d54
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1576.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1576.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01576ent IS
+END c08s10b00x00p04n01i01576ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01576arch OF c08s10b00x00p04n01i01576ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local variables
+    variable DIDIT    : BOOLEAN;
+    variable CONSTONE : INTEGER := 1;
+    variable   k     : integer := 0;
+  BEGIN
+    -- The following loop should never fail its assertion.
+    DIDIT := FALSE;
+    for I in 0 to 10 loop
+      -- Make sure that the last statement of loop is executed.
+      if  (I /= 0) then
+        if (DIDIT /= true) then
+          k := 1;
+        end if;
+        assert (DIDIT)
+          report "Did not execute statement after 'next when FALSE'";
+        DIDIT := FALSE;
+      end if;
+      
+      -- This condition is NEVER true.
+      next when FALSE;
+      
+      -- This statement should always be executed.
+      DIDIT := TRUE;
+    end loop;
+    
+    -- The following loop should never fail its assertion.
+    DIDIT := FALSE;
+    for I in 0 to 10 loop
+      -- Make sure that the last statement of loop is executed.
+      if  (I /= 0) then
+        if (DIDIT /= true) then
+          k := 1;
+        end if;
+        assert (DIDIT)
+          report "Did not execute statement after 'next when FALSE'";
+        DIDIT := FALSE;
+      end if;
+      
+      -- This condition is NEVER true.
+      next when (CONSTONE /= 1);
+      
+      -- This statement should always be executed.
+      DIDIT := TRUE;
+    end loop;
+
+    assert NOT( k=0 ) 
+      report "***PASSED TEST: c08s10b00x00p04n01i01576" 
+      severity NOTE;
+    assert ( k=0 ) 
+      report "***FAILED TEST: c08s10b00x00p04n01i01576 - If the condition in the next statement is FALSE, it should execute the sequence of statements enclosed within the loop condition with the next statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01576arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc158.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc158.vhd
new file mode 100644
index 0000000..9b1ce80
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc158.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc158.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p19n01i00158pkg is
+  type rec_type is
+    record
+      a, b, c : integer;
+    end record;
+  procedure P1 (p : in rec_type; q: in integer; r: out integer);
+end c04s03b02x02p19n01i00158pkg;
+
+package body c04s03b02x02p19n01i00158pkg is
+  procedure P1 (p : in rec_type; q: in integer; r: out integer) is
+  begin
+  end P1;
+end c04s03b02x02p19n01i00158pkg;
+
+use work.c04s03b02x02p19n01i00158pkg.all;
+ENTITY c04s03b02x02p19n01i00158ent IS
+END c04s03b02x02p19n01i00158ent;
+
+ARCHITECTURE c04s03b02x02p19n01i00158arch OF c04s03b02x02p19n01i00158ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+  BEGIN
+    P1 ((a => 1, b => 2, c => 3),      q => 10, r => x);  -- No_failure_here
+    P1 (p => (a => 1, b => 2, c => 3), q => 10, r => x);  -- No_failure_here
+    P1 (p.a => 1, p.b => 2, p.c => 3,  q => 10, r => x);  -- No_failure_here
+    P1 (p => (1, 2, 3),                q => 10, r => x);  -- No_failure_here
+    assert FALSE
+      report "***PASSED TEST: c04s03b02x02p19n01i00158"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p19n01i00158arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1581.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1581.vhd
new file mode 100644
index 0000000..0db6f82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1581.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1581.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p02n01i01581ent IS
+END c08s11b00x00p02n01i01581ent;
+
+ARCHITECTURE c08s11b00x00p02n01i01581arch OF c08s11b00x00p02n01i01581ent IS
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      exit when i = 6;
+      k := i;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s11b00x00p02n01i01581"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s11b00x00p02n01i01581 - Exit statement consists of the reserved word 'exit' and optionally the reserved word 'when' followed by a condition "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p02n01i01581arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1582.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1582.vhd
new file mode 100644
index 0000000..ff436c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1582.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1582.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p02n01i01582ent IS
+END c08s11b00x00p02n01i01582ent;
+
+ARCHITECTURE c08s11b00x00p02n01i01582arch OF c08s11b00x00p02n01i01582ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 0;
+  BEGIN
+    while i < 10 loop
+      exit when i = 5;
+      i := i + 1;
+    end loop;
+    assert NOT( i=5 )
+      report "***PASSED TEST: c08s11b00x00p02n01i01582"
+      severity NOTE;
+    assert ( i=5 )
+      report "***FAILED TEST: c08s11b00x00p02n01i01582 - Exit statement consists of the reserved word 'exit' and optionally the reserved word 'when' followed by a condition "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p02n01i01582arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1583.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1583.vhd
new file mode 100644
index 0000000..2334510
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1583.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1583.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p02n01i01583ent IS
+END c08s11b00x00p02n01i01583ent;
+
+ARCHITECTURE c08s11b00x00p02n01i01583arch OF c08s11b00x00p02n01i01583ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    while k < 10 loop
+      exit ;
+      k := 5;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c08s11b00x00p02n01i01583"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c08s11b00x00p02n01i01583 - The when clause in the exit statement is optional" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p02n01i01583arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1585.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1585.vhd
new file mode 100644
index 0000000..295cfbd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1585.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1585.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p02n01i01585ent IS
+END c08s11b00x00p02n01i01585ent;
+
+ARCHITECTURE c08s11b00x00p02n01i01585arch OF c08s11b00x00p02n01i01585ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    while k < 10 loop
+      exit when k = 5;
+      k := k + 1;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s11b00x00p02n01i01585"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s11b00x00p02n01i01585 - The loop label in the exit statement is optional" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p02n01i01585arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1587.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1587.vhd
new file mode 100644
index 0000000..e3b5a7e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1587.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1587.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01587ent IS
+END c08s11b00x00p03n01i01587ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01587arch OF c08s11b00x00p03n01i01587ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      k := i;
+      exit L;
+    end loop;
+    assert NOT(k = 1) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01587"
+      severity NOTE;
+    assert (k = 1) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01587 - A loop label is allowed within a labeled loop."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01587arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1589.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1589.vhd
new file mode 100644
index 0000000..15b1f13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1589.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1589.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01589ent IS
+END c08s11b00x00p03n01i01589ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01589arch OF c08s11b00x00p03n01i01589ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p : integer := 0;
+  BEGIN
+    K : for j in 1 to 10 loop
+      L : for i in 1 to 10 loop
+        exit K when j = 3;
+        p := p + 1;
+      end loop L;
+    end loop;
+    assert NOT( p = 20 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01589"
+      severity NOTE;
+    assert ( p = 20 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01589 - An exit statement with a loop label within a labeled loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01589arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1594.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1594.vhd
new file mode 100644
index 0000000..66a0ab7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1594.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1594.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01594ent IS
+END c08s11b00x00p03n01i01594ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01594arch OF c08s11b00x00p03n01i01594ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      k := i;
+      exit;
+    end loop;
+    assert NOT(k = 1) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01594" 
+      severity NOTE;
+    assert (k = 1) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01594 - A exit statement inside a FOR loop without a loop label" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01594arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1596.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1596.vhd
new file mode 100644
index 0000000..1cec019
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1596.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1596.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01596ent IS
+END c08s11b00x00p03n01i01596ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01596arch OF c08s11b00x00p03n01i01596ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p : integer := 0;
+  BEGIN
+    L : for j in 1 to 10 loop
+      K : for i in 1 to 20 loop
+        exit when j = 5;
+        p := p + 1;
+      end loop K;
+    end loop;
+    assert NOT( p=180 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01596"
+      severity NOTE;
+    assert ( p=180 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01596 - Exit applies only to inner loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01596arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1597.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1597.vhd
new file mode 100644
index 0000000..8ad4755
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1597.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1597.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01597ent IS
+END c08s11b00x00p03n01i01597ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01597arch OF c08s11b00x00p03n01i01597ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p : integer := 0;
+  BEGIN
+    L1 :
+    for i in boolean loop
+      p := 5 + p;
+      L2 :
+      for j in 1 to 3 loop
+        exit ;
+        p := 0;
+      end loop L2 ;
+    end loop L1;
+    assert NOT( p=10 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01597" 
+      severity NOTE;
+    assert ( p=10 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01597 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01597arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1598.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1598.vhd
new file mode 100644
index 0000000..90aebb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1598.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1598.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01598ent IS
+END c08s11b00x00p03n01i01598ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01598arch OF c08s11b00x00p03n01i01598ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p    : integer := 0;
+    variable done    : boolean := false;
+  BEGIN
+    L1 : for i in boolean loop
+      while not done loop
+        done := true ;
+        exit ;
+        p := 0;
+      end loop ;
+      p := p + 1;
+    end loop L1;
+    assert NOT( p=2 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01598" 
+      severity NOTE;
+    assert ( p=2 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01598 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01598arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1599.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1599.vhd
new file mode 100644
index 0000000..6743b3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1599.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1599.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01599ent IS
+END c08s11b00x00p03n01i01599ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01599arch OF c08s11b00x00p03n01i01599ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p       : integer := 0;
+    variable done       : boolean := false;
+    variable v_boolean : boolean := false;
+  BEGIN
+    L1 : while v_boolean /= boolean'High loop
+      while not done loop
+        done := true ;
+        exit ;
+        p := 0;
+      end loop ;
+      p := p + 1;
+      v_boolean := boolean'Succ(v_boolean);
+    end loop L1;
+    assert NOT( p=1 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01599"
+      severity NOTE;
+    assert ( p=1 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01599 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01599arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc16.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc16.vhd
new file mode 100644
index 0000000..7c7a958
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc16.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc16.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p06n03i00016ent IS
+END c04s02b00x00p06n03i00016ent;
+
+ARCHITECTURE c04s02b00x00p06n03i00016arch OF c04s02b00x00p06n03i00016ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define a subtype of a subtype.
+    subtype ZERO is NATURAL;
+
+    -- Define variables of these subtypes.
+    variable ZEROV     : ZERO := 0;
+    variable NATURALV  : NATURAL := 0;
+  BEGIN
+    -- Verify that these two variables have the same base type.
+    assert NOT( Naturalv = zerov and zerov = zero'low )
+      report "***PASSED TEST: c04s02b00x00p06n03i00016"
+      severity NOTE;
+    assert ( Naturalv = zerov and zerov = zero'low )
+      report "***FAILED TEST: c04s02b00x00p06n03i00016 - The base type of a subtype is the base type of the type mark."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p06n03i00016arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1600.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1600.vhd
new file mode 100644
index 0000000..c1b3691
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1600.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1600.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01600ent IS
+END c08s11b00x00p03n01i01600ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01600arch OF c08s11b00x00p03n01i01600ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p       : integer := 0;
+    variable done       : boolean := false;
+    variable v_boolean : boolean := false;
+  BEGIN
+    L1 : while v_boolean /= boolean'High loop
+      for j in 1 to 3 loop
+        exit;
+        p := 0;
+      end loop;
+      p := p + 1;
+      v_boolean := boolean'Succ(v_boolean);
+    end loop L1;
+    assert NOT( p=1 ) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01600" 
+      severity NOTE;
+    assert ( p=1 ) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01600 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01600arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1601.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1601.vhd
new file mode 100644
index 0000000..1ea6957
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1601.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1601.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01601ent IS
+END c08s11b00x00p03n01i01601ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01601arch OF c08s11b00x00p03n01i01601ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable p       : integer := 0;
+    variable counter   : integer := 0;
+  BEGIN
+    L1 :
+    for i in boolean loop
+      L2 :
+      for j in 1 to 3 loop
+        exit L2 ;
+        p := 5 ;
+      end loop L2 ;
+      counter := counter + 1 ;
+    end loop L1 ;
+    assert NOT((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1))) 
+      report "***PASSED TEST: c08s11b00x00p03n01i01601" 
+      severity NOTE;
+    assert ((p=0)and(counter=(boolean'Pos(boolean'High)-boolean'Pos(boolean'Low)+1))) 
+      report "***FAILED TEST: c08s11b00x00p03n01i01601 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01601arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1603.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1603.vhd
new file mode 100644
index 0000000..e650aa7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1603.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1603.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01603ent IS
+END c08s11b00x00p04n01i01603ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01603arch OF c08s11b00x00p04n01i01603ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      exit L when i = 6;
+      k := i;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c08s11b00x00p04n01i01603"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c08s11b00x00p04n01i01603 - Exit from the labeled loop when the condition of the WHEN clause evaluates to be true"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01603arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1606.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1606.vhd
new file mode 100644
index 0000000..14f1da0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1606.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1606.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01606ent IS
+END c08s11b00x00p04n01i01606ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01606arch OF c08s11b00x00p04n01i01606ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables
+    variable GONE_THROUGH_ONCE : BOOLEAN := FALSE;
+    variable k : integer := 0;
+  BEGIN
+    for I in 0 to 10 loop
+      -- Check to see if we have gone through this more than once.
+      if  (not(GONE_THROUGH_ONCE)) then
+        GONE_THROUGH_ONCE := TRUE;
+      else
+        assert (FALSE)
+          report "Going through loop more than once.";
+      end if;
+
+      -- Exit the loop.
+      exit when TRUE;
+      k := 1;
+      -- The following should never be executed.
+      assert (FALSE)
+        report "This statement should NEVER be executed.";
+    end loop;
+
+    -- Verify that we went through at least once.
+    assert( GONE_THROUGH_ONCE )
+      report "Did not go through the loop at all.";
+
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s11b00x00p04n01i01606"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s11b00x00p04n01i01606 - The loop should terminate when the condition is TRUE." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01606arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1607.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1607.vhd
new file mode 100644
index 0000000..ca50fb5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1607.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1607.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01607ent IS
+END c08s11b00x00p04n01i01607ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01607arch OF c08s11b00x00p04n01i01607ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables
+    variable GONE_THROUGH_ONCE : BOOLEAN := FALSE;
+    variable k : integer := 0;
+  BEGIN
+    for I in 0 to 10 loop
+      -- Check to see if we have gone through this more than once.
+      if  (not(GONE_THROUGH_ONCE)) then
+        GONE_THROUGH_ONCE := TRUE;
+      else
+        assert (FALSE)
+          report "Going through loop more than once.";
+      end if;
+
+      -- Exit the loop.
+      exit;
+      k := 1;
+      -- The following should never be executed.
+      assert (FALSE)
+        report "This statement should NEVER be executed.";
+    end loop;
+
+    -- Verify that we went through at least once.
+    assert( GONE_THROUGH_ONCE )
+      report "Did not go through the loop at all.";
+
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s11b00x00p04n01i01607"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s11b00x00p04n01i01607 - The loop should terminate when the condition is TRUE." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01607arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1608.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1608.vhd
new file mode 100644
index 0000000..4d743cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1608.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1608.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01608ent IS
+END c08s11b00x00p04n01i01608ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01608arch OF c08s11b00x00p04n01i01608ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local variables
+    variable DIDIT    : BOOLEAN;
+    variable CONSTONE : INTEGER := 1;
+    variable k : integer := 0;
+  BEGIN
+    -- The following loop should never fail its assertion.
+    DIDIT := FALSE;
+    for I in 0 to 10 loop
+      -- Make sure that the last statement of loop is executed.
+      if  (I /= 0) then
+        if (DIDIT /= true) then
+          k := 1;
+        end if;
+        assert (DIDIT)
+          report "Did not execute statement after 'next when FALSE'";
+        DIDIT := FALSE;
+      end if;
+
+      -- This condition is NEVER true.
+      exit when FALSE;
+
+      -- This statement should always be executed.
+      DIDIT := TRUE;
+    end loop;
+    
+    -- The following loop should never fail its assertion.
+    DIDIT := FALSE;
+    for I in 0 to 10 loop
+      -- Make sure that the last statement of loop is executed.
+      if  (I /= 0) then
+        if (DIDIT /= true) then
+          k := 1;
+        end if;
+        assert (DIDIT)
+          report "Did not execute statement after 'next when FALSE'";
+        DIDIT := FALSE;
+      end if;
+      
+      -- This condition is NEVER true.
+      exit when (CONSTONE /= 1);
+      
+      -- This statement should always be executed.
+      DIDIT := TRUE;
+    end loop;
+
+    assert NOT(k=0) 
+      report "***PASSED TEST: c08s11b00x00p04n01i01608"
+      severity NOTE;
+    assert (k=0) 
+      report "***FAILED TEST: c08s11b00x00p04n01i01608 - If the condition evaluate to FALSE, the execution of the sequence of the statements enclosed within the loop condition with the next statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01608arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1613.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1613.vhd
new file mode 100644
index 0000000..f18176a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1613.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1613.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p01n01i01613ent IS
+END c08s12b00x00p01n01i01613ent;
+
+ARCHITECTURE c08s12b00x00p01n01i01613arch OF c08s12b00x00p01n01i01613ent IS
+
+  --
+  -- Nested functions to test return statement.
+  --
+  function two  return integer is
+    function one  return integer is
+    begin
+      return 1;
+    end one;
+  begin
+    return one + one;
+  end two;
+
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    assert NOT( two=2 )
+      report "***PASSED TEST: c08s12b00x00p01n01i01613"
+      severity NOTE;
+    assert ( two=2 )
+      report "***FAILED TEST: c08s12b00x00p01n01i01613 - Return statement applies to the innermost enclosing function."
+      severity ERROR;
+    wait;
+  END PROCESS;
+
+END c08s12b00x00p01n01i01613arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1614.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1614.vhd
new file mode 100644
index 0000000..80ca038
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1614.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1614.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p01n01i01614ent IS
+END c08s12b00x00p01n01i01614ent;
+
+ARCHITECTURE c08s12b00x00p01n01i01614arch OF c08s12b00x00p01n01i01614ent IS
+
+  --
+  -- Nested procedures to test return statement.
+  --
+  procedure two ( variable val : inout integer ) is
+    procedure one ( variable val : out integer ) is
+    begin
+      val := 1;
+      return;
+      val := 2;                     -- should never get here
+    end one;
+  begin
+    one(val);
+    val := val * 2;
+    return;
+    val := val * 2;                   -- should never get here
+  end two;
+
+BEGIN
+  TESTING : PROCESS
+    variable v1 : integer;
+  BEGIN
+    two (v1);
+    assert NOT( v1=2 )
+      report "***PASSED TEST: c08s12b00x00p01n01i01614"
+      severity NOTE;
+    assert ( v1=2 )
+      report "***FAILED TEST: c08s12b00x00p01n01i01614 - Return statement applies to the innermost enclosing function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p01n01i01614arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1617.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1617.vhd
new file mode 100644
index 0000000..95bf769
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1617.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1617.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01617ent IS
+END c08s12b00x00p03n01i01617ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01617arch OF c08s12b00x00p03n01i01617ent IS
+  function f1 (in1:real) return integer is
+  begin
+    return(12);
+  end f1;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := f1(2.3);   
+    assert NOT(k = 12) 
+      report "***PASSED TEST: c08s12b00x00p03n01i01617" 
+      severity NOTE;
+    assert (k = 12) 
+      report "***FAILED TEST: c08s12b00x00p03n01i01617 - A return statement is only allowed within the body of a function" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01617arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1619.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1619.vhd
new file mode 100644
index 0000000..df89239
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1619.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1619.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01619ent IS
+END c08s12b00x00p03n01i01619ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01619arch OF c08s12b00x00p03n01i01619ent IS
+  function F (p : integer) return BIT is
+  begin
+    if p = 5 then
+      return '0';
+    else
+      return '1';
+    end if; 
+  end F;
+BEGIN
+  TESTING: PROCESS
+    variable k : BIT ;
+  BEGIN
+    k := F(5);
+    assert NOT(k = '0') 
+      report "***PASSED TEST: c08s12b00x00p03n01i01619" 
+      severity NOTE;
+    assert (k = '0') 
+      report "***FAILED TEST: c08s12b00x00p03n01i01619 - Multiple return statements in a function body." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01619arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc162.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc162.vhd
new file mode 100644
index 0000000..ccacfec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc162.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc162.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p20n02i00162pkg is
+  subtype string_v is string(1 to 32);
+  CONSTANT null_string_v : string_v := (
+    'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
+    'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', 'a', 'b', 'c', 'd', 'e', 'f');
+end c04s03b02x02p20n02i00162pkg;
+
+ENTITY c04s03b02x02p20n02i00162ent IS
+END c04s03b02x02p20n02i00162ent;
+
+use work.c04s03b02x02p20n02i00162pkg.all;
+ARCHITECTURE c04s03b02x02p20n02i00162arch OF c04s03b02x02p20n02i00162ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable buf : string_v := null_string_v; 
+
+    PROCEDURE sprintf
+      (
+        buff   : out string_v;
+        str1   : in  string := null_string_v;
+        str2   : in  string := null_string_v;
+        str3   : in  string := null_string_v
+        )
+    is
+      VARIABLE index : integer := 1;
+    begin
+
+      buff := null_string_v;
+
+      for i in str1'range LOOP
+        exit when str1(i) = ' ';
+        buff (index) := str1 (i);
+        index := index + 1;
+      end LOOP;
+      for i in str2'range LOOP
+        exit when str2(i) = ' ';
+        buff (index) := str2 (i);
+        index := index + 1;
+      end LOOP;
+      for i in str3'range LOOP
+        exit when str3(i) = ' ';
+        buff (index) := str3 (i);
+        index := index + 1;
+      end LOOP;
+    end sprintf;
+
+  BEGIN
+    sprintf ( buf,
+              "VHDL ",
+              "TECHNOLOGY ",
+              "GROUP " );
+    wait for 10 ns;
+
+    assert NOT( buf(1  to 19) = "VHDLTECHNOLOGYGROUP"   and
+                buf(20 to 32) = "TUVWXYZabcdef")
+      report "***PASSED TEST: c04s03b02x02p20n02i00162"
+      severity NOTE;
+    assert ( buf(1  to 19) = "VHDLTECHNOLOGYGROUP"   and
+             buf(20 to 32) = "TUVWXYZabcdef")
+      report "***FAILED TEST: c04s03b02x02p20n02i00162- The value of the default expression is used as the actual expression in an implicit association element fot that interface element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p20n02i00162arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc163.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc163.vhd
new file mode 100644
index 0000000..b57d89c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc163.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc163.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p20n01i00163pkg is
+  procedure P1 (p : in integer := 0; r: inout integer);
+end c04s03b02x02p20n01i00163pkg;
+
+package body c04s03b02x02p20n01i00163pkg is
+  procedure P1 (p : in integer := 0; r: inout integer) is
+  begin
+    r := p / 3 ;
+  end;
+end c04s03b02x02p20n01i00163pkg;
+
+
+use work.c04s03b02x02p20n01i00163pkg.all;
+ENTITY c04s03b02x02p20n01i00163ent IS
+END c04s03b02x02p20n01i00163ent;
+
+ARCHITECTURE c04s03b02x02p20n01i00163arch OF c04s03b02x02p20n01i00163ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+  BEGIN
+    P1 (r => x);  -- No_failure_here
+    -- no association for p
+    assert NOT( x=0 )
+      report "***PASSED TEST: c04s03b02x02p20n01i00163"
+      severity NOTE;
+    assert ( x=0 )
+      report "***FAILED TEST: c04s03b02x02p20n01i00163 - Defualt value in an association list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p20n01i00163arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1630.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1630.vhd
new file mode 100644
index 0000000..3d89b5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1630.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1630.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p04n01i01630ent IS
+END c08s12b00x00p04n01i01630ent;
+
+ARCHITECTURE c08s12b00x00p04n01i01630arch OF c08s12b00x00p04n01i01630ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 0;
+    procedure return_exp_check is
+    begin
+      i := 10;
+    end;
+  BEGIN
+    return_exp_check;
+    assert NOT(i = 10) 
+      report "***PASSED TEST: c08s12b00x00p04n01i01630" 
+      severity NOTE;
+    assert (i = 10) 
+      report "***FAILED TEST: c08s12b00x00p04n01i01630 - A return statement is not required in a procedure body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p04n01i01630arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1633.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1633.vhd
new file mode 100644
index 0000000..20a31d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1633.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1633.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p05n01i01633ent IS
+END c08s12b00x00p05n01i01633ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01633arch OF c08s12b00x00p05n01i01633ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type AR2 is array (0 to 2) of BIT;
+    function K return AR2 is
+    begin
+      return (1 => '1', others => '0');
+    end K;
+    variable kk : AR2;
+  BEGIN
+    kk := K;
+    assert (kk = "010") 
+      report "***FAILED TEST: c08s12b00x00p05n01i01633 - The return type must be the same base tyep declared in the specification of the function."
+      severity ERROR;
+    assert NOT(kk = "010") 
+      report "***PASSED TEST: c08s12b00x00p05n01i01633"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01633arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1634.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1634.vhd
new file mode 100644
index 0000000..a2b5390
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1634.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1634.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p05n01i01634ent IS
+END c08s12b00x00p05n01i01634ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01634arch OF c08s12b00x00p05n01i01634ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type E is (A,B,C,D);
+    subtype E1 is E range C to D;
+    function F return E is
+      variable V : E1 := C;
+    begin
+      return V;
+    end F;
+    variable k : E := A; 
+  BEGIN
+    k := F;
+    assert NOT(k = C)
+      report "***PASSED TEST: c08s12b00x00p05n01i01634" 
+      severity NOTE;
+    assert (k = C) 
+      report "***FAILED TEST: c08s12b00x00p05n01i01634 - The return type must be the same base tyep declared in the specification of the function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01634arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1635.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1635.vhd
new file mode 100644
index 0000000..d838d6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1635.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1635.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p05n01i01635ent IS
+END c08s12b00x00p05n01i01635ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01635arch OF c08s12b00x00p05n01i01635ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PH is range 1 to 24
+      units
+        U;
+        X=3 U;
+        Y=2 X;
+      end units;
+    subtype PH1 is PH range X to Y;
+    function J return PH1 is
+    begin
+      return X;
+    end J;
+    variable k : PH1 := 2 X; 
+  BEGIN
+    k := J;
+    assert NOT(k = X)
+      report "***PASSED TEST: c08s12b00x00p05n01i01635" 
+      severity NOTE;
+    assert (k = X) 
+      report "***FAILED TEST: c08s12b00x00p05n01i01635 - The return type must be the same base tyep declared in the specification of the function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01635arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1636.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1636.vhd
new file mode 100644
index 0000000..0bcd8b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1636.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1636.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p05n01i01636ent IS
+END c08s12b00x00p05n01i01636ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01636arch OF c08s12b00x00p05n01i01636ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PH is range 1 to 24
+      units
+        U;
+        X=3 U;
+        Y=2 X;
+      end units;
+    type AR1 is array (POSITIVE range <>) of PH;   
+    function K return AR1 is
+      variable V : AR1(49 to 50) ;
+    begin
+      V := (5 U,X) ;
+      return V;
+    end K;
+    variable kk : AR1(49 to 50); 
+  BEGIN
+    kk := K;
+    assert NOT(kk = (5 U,X))
+      report "***PASSED TEST: c08s12b00x00p05n01i01636" 
+      severity NOTE;
+    assert (kk = (5 U,X))
+      report "***FAILED TEST: c08s12b00x00p05n01i01636 - The return type must be the same base tyep declared in the specification of the function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01636arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1637.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1637.vhd
new file mode 100644
index 0000000..0db0ff8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1637.vhd
@@ -0,0 +1,238 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1637.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s12b00x00p05n01i01637pkg is
+
+  -- type declarations
+  type ENUM is ( E1, E2, E3 );
+  type DISTANCE is range 0 to 1E9
+    units
+      -- Base units.
+      A;                    -- angstrom
+
+      -- Metric lengths.
+      nm       = 10 A;      -- nanometer
+      um       = 1000 nm;   -- micrometer (or micron)
+      mm       = 1000 um;   -- millimeter
+      cm       = 10 mm;     -- centimeter
+
+      -- English lengths.
+      mil      = 254000 A;  -- mil
+      inch     = 1000 mil;  -- inch
+    end units;
+  type ANARRAY is ARRAY( 0 to 1 ) of REAL;
+  type ARECORD is
+    RECORD
+      Field1      : INTEGER;
+      Field2      : BOOLEAN;
+    end record;
+
+  -- constant declarations
+  CONSTANT CONSTI     : INTEGER  := 47;
+  CONSTANT CONSTR     : REAL     := 47.0;
+  CONSTANT CONSTE     : ENUM     := E1;
+  CONSTANT CONSTD     : DISTANCE := 1 A;
+  CONSTANT CONSTT     : TIME     := 1 hr;
+  CONSTANT CONSTB     : BIT      := '1';
+  CONSTANT CONSTS     : SEVERITY_LEVEL := WARNING;
+  CONSTANT CONSTBO    : BOOLEAN  := FALSE;
+  CONSTANT CONSTA     : ANARRAY  := ( 3.1415926, 4.0 );
+  CONSTANT CONSTRE    : ARECORD  := ( Field1 => 2, Field2 => TRUE );
+  
+  -- function declarations.
+  function funcI return INTEGER;
+  function funcR return REAL;
+  function funcE return ENUM;
+  function funcD return DISTANCE;
+  function funcT return TIME;
+  function funcB return BIT;
+  function funcS return SEVERITY_LEVEL;
+  function funcBO return BOOLEAN;
+  function funcA return ANARRAY;
+  function funcRE return ARECORD;
+  
+end c08s12b00x00p05n01i01637pkg;
+
+package body c08s12b00x00p05n01i01637pkg is
+  
+  function funcI return INTEGER is
+  begin
+    return( CONSTI );
+  end;
+  
+  function funcR return REAL is
+  begin
+    return( CONSTR );
+  end;
+  
+  function funcE return ENUM is
+  begin
+    return( CONSTE );
+  end;
+  
+  function funcD return DISTANCE is
+  begin
+    return( CONSTD );
+  end;
+  
+  function funcT return TIME is
+  begin
+    return( CONSTT );
+  end;
+  
+  function funcB return BIT is
+  begin
+    return( CONSTB );
+  end;
+  
+  function funcS return SEVERITY_LEVEL is
+  begin
+    return( CONSTS );
+  end;
+  
+  function funcBO return BOOLEAN is
+  begin
+    return( CONSTBO );
+  end;
+  
+  function funcA return ANARRAY is
+  begin
+    return( CONSTA );
+  end;
+  
+  function funcRE return ARECORD is
+  begin
+    return( CONSTRE );
+  end;
+  
+end c08s12b00x00p05n01i01637pkg;
+
+use work.c08s12b00x00p05n01i01637pkg.all;
+ENTITY c08s12b00x00p05n01i01637ent IS
+END c08s12b00x00p05n01i01637ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01637arch OF c08s12b00x00p05n01i01637ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- variable declarations.
+    VARIABLE VARI     : INTEGER;
+    VARIABLE VARR     : REAL;
+    VARIABLE VARE     : ENUM;
+    VARIABLE VARD     : DISTANCE;
+    VARIABLE VART     : TIME;
+    VARIABLE VARB     : BIT;
+    VARIABLE VARS     : SEVERITY_LEVEL;
+    VARIABLE VARBO    : BOOLEAN;
+    VARIABLE VARA     : ANARRAY;
+    VARIABLE VARRE    : ARECORD;
+  BEGIN
+    -- Call each function, verify that it returns the proper value.
+    assert (funcI = CONSTI);
+    assert (funcR = CONSTR);
+    assert (funcE = CONSTE);
+    assert (funcD = CONSTD);
+    assert (funcT = CONSTT);
+    assert (funcB = CONSTB);
+    assert (funcS = CONSTS);
+    assert (funcBO = CONSTBO);
+    assert (funcA = CONSTA);
+    assert (funcRE = CONSTRE);
+    
+    -- Assign function values to variables, make sure they're OK.
+    VARI  := funcI;
+    VARR  := funcR;
+    VARE  := funcE;
+    VARD  := funcD;
+    VART  := funcT;
+    VARB  := funcB;
+    VARS  := funcS;
+    VARBO := funcBO;
+    VARA  := funcA;
+    VARRE := funcRE;
+    assert (VARI = CONSTI);
+    assert (VARR = CONSTR);
+    assert (VARE = CONSTE);
+    assert (VARD = CONSTD);
+    assert (VART = CONSTT);
+    assert (VARB = CONSTB);
+    assert (VARS = CONSTS);
+    assert (VARBO = CONSTBO);
+    assert (VARA = CONSTA);
+    assert (VARRE = CONSTRE);
+
+    assert NOT((funcI = CONSTI)   and
+               (funcR = CONSTR)   and
+               (funcE = CONSTE)   and
+               (funcD = CONSTD)   and
+               (funcT = CONSTT)   and
+               (funcB = CONSTB)   and
+               (funcS = CONSTS)   and
+               (funcBO = CONSTBO)   and
+               (funcA = CONSTA)   and
+               (funcRE = CONSTRE)   and
+               (VARI = CONSTI)   and
+               (VARR = CONSTR)   and
+               (VARE = CONSTE)   and
+               (VARD = CONSTD)   and
+               (VART = CONSTT)   and
+               (VARB = CONSTB)   and
+               (VARS = CONSTS)   and
+               (VARBO = CONSTBO)   and
+               (VARA = CONSTA)   and
+               (VARRE = CONSTRE))   
+      report "***PASSED TEST: c08s12b00x00p05n01i01637"
+      severity NOTE;
+    assert   ((funcI = CONSTI)   and
+              (funcR = CONSTR)   and
+              (funcE = CONSTE)   and
+              (funcD = CONSTD)   and
+              (funcT = CONSTT)   and
+              (funcB = CONSTB)   and
+              (funcS = CONSTS)   and
+              (funcBO = CONSTBO)   and
+              (funcA = CONSTA)   and
+              (funcRE = CONSTRE)   and
+              (VARI = CONSTI)   and
+              (VARR = CONSTR)   and
+              (VARE = CONSTE)   and
+              (VARD = CONSTD)   and
+              (VART = CONSTT)   and
+              (VARB = CONSTB)   and
+              (VARS = CONSTS)   and
+              (VARBO = CONSTBO)   and
+              (VARA = CONSTA)   and
+              (VARRE = CONSTRE))   
+      report "***FAILED TEST: c08s12b00x00p05n01i01637 - The value of the expression defines the result returned by the function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01637arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1639.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1639.vhd
new file mode 100644
index 0000000..b3f2e64
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1639.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1639.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p06n01i01639ent IS
+END c08s12b00x00p06n01i01639ent;
+
+ARCHITECTURE c08s12b00x00p06n01i01639arch OF c08s12b00x00p06n01i01639ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable correct : boolean := true;
+    procedure Proc1(constant p_boolean :boolean ) is
+    begin
+      if p_boolean = p_boolean then
+        return;
+      else
+        return;   
+      end if;
+      correct := false;
+    end Proc1;
+  BEGIN
+    Proc1(false);
+    assert NOT( correct = true )
+      report "***PASSED TEST: c08s12b00x00p06n01i01639"
+      severity NOTE;
+    assert ( correct = true )
+      report "***FAILED TEST: c08s12b00x00p06n01i01639 - A return statement stops execution of a procedure."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p06n01i01639arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc164.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc164.vhd
new file mode 100644
index 0000000..440307c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc164.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc164.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p23n01i00164ent IS
+END c04s03b02x02p23n01i00164ent;
+
+ARCHITECTURE c04s03b02x02p23n01i00164arch OF c04s03b02x02p23n01i00164ent IS
+  signal p1 : bit;   --added to make it compile
+BEGIN
+  TESTING: PROCESS(p1)
+    VARIABLE v1,v2,v3,v4 : integer;
+
+    PROCEDURE default_test
+      (
+        param_1 : in integer;
+        default : in integer := 22;
+        param_3 : out integer;
+        param_4 : out integer
+        )
+    is
+    begin
+      param_3 := param_1;
+      param_4 := default;
+    end default_test;
+
+  BEGIN
+    v1 := 1919;
+    default_test (v1,
+                  -- missing association
+                  param_3 => v3,
+                  param_4 => v4
+                  );
+    assert NOT( v3=1919 and v4=22 )
+      report "***PASSED TEST: c04s03b02x02p23n01i00164"
+      severity NOTE;
+    assert ( v3=1919 and v4=22 )
+      report "***FAILED TEST: c04s03b02x02p23n01i00164 - If an association element is omitted from an association list in order to make use of the default expression on the corresponding interface element, all subsequent association elements in that association list must be named associations."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c04s03b02x02p23n01i00164arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1641.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1641.vhd
new file mode 100644
index 0000000..d25733b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1641.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1641.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p06n01i01641ent IS
+END c08s12b00x00p06n01i01641ent;
+
+ARCHITECTURE c08s12b00x00p06n01i01641arch OF c08s12b00x00p06n01i01641ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function ts (x1:bit) return integer is
+    begin
+      return (5);
+    end ts;
+    variable k : integer := 0;
+  BEGIN
+    k := ts('1');   
+    assert NOT(k=5) 
+      report "***PASSED TEST: c08s12b00x00p06n01i01641"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c08s12b00x00p06n01i01641 - Value of the expression is of different subtype." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p06n01i01641arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1642.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1642.vhd
new file mode 100644
index 0000000..a38810c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1642.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1642.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s12b00x00p06n01i01642pkg is
+
+  procedure procI;
+  function  funcI return INTEGER;
+
+end c08s12b00x00p06n01i01642pkg;
+
+package body c08s12b00x00p06n01i01642pkg is
+
+  procedure procI is
+  begin
+    -- Return.
+    return;
+
+    -- Statement should NEVER be executed.
+    assert (FALSE)
+      report "Statement in procedure was executed in error.";
+  end procI;
+
+  function funcI return INTEGER is
+  begin
+    -- Return from the function.
+    return( 4 );
+
+    -- Statement should NEVER be executed.
+    assert (FALSE)
+      report "Statement in function was executed in error.";
+  end funcI;
+
+end c08s12b00x00p06n01i01642pkg;
+
+use work.c08s12b00x00p06n01i01642pkg.all;
+ENTITY c08s12b00x00p06n01i01642ent IS
+END c08s12b00x00p06n01i01642ent;
+
+ARCHITECTURE c08s12b00x00p06n01i01642arch OF c08s12b00x00p06n01i01642ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Execute the procedure.
+    procI;
+    
+    -- Execute the function.
+    assert NOT(funcI = 4)
+      report "***PASSED TEST: c08s12b00x00p06n01i01642" 
+      severity NOTE;
+    assert (funcI = 4)
+      report "***FAILED TEST: c08s12b00x00p06n01i01642 - The execution of the return statement completes if the type of the expression is of teh result subtype." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p06n01i01642arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1643.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1643.vhd
new file mode 100644
index 0000000..91a6a25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1643.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1643.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s12b00x00p08n01i01643pkg is
+
+
+  -- function declarations.
+  function funcI  return INTEGER;
+  function funcI2 return INTEGER;
+
+end c08s12b00x00p08n01i01643pkg;
+
+package body c08s12b00x00p08n01i01643pkg is
+
+  function funcI return INTEGER is
+  begin
+    return ( 3 );
+  end;
+
+  function funcI2 return INTEGER is
+  begin
+    return ( 3  );
+  end;
+
+end c08s12b00x00p08n01i01643pkg;
+
+use work.c08s12b00x00p08n01i01643pkg.all;
+ENTITY c08s12b00x00p08n01i01643ent IS
+END c08s12b00x00p08n01i01643ent;
+
+ARCHITECTURE c08s12b00x00p08n01i01643arch OF c08s12b00x00p08n01i01643ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( funcI = 3 and funcI2 = 3)         
+      report "***PASSED TEST: c08s12b00x00p08n01i01643"
+      severity NOTE;
+    assert ( funcI = 3 and funcI2 = 3)         
+      report "***FAILED TEST: c08s12b00x00p08n01i01643 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p08n01i01643arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1644.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1644.vhd
new file mode 100644
index 0000000..33fb02c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1644.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1644.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p02n01i01644ent IS
+END c08s13b00x00p02n01i01644ent;
+
+ARCHITECTURE c08s13b00x00p02n01i01644arch OF c08s13b00x00p02n01i01644ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if TRUE then
+      NULL;
+    end if;
+    assert FALSE
+      report "***PASSED TEST: c08s13b00x00p02n01i01644"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p02n01i01644arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1646.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1646.vhd
new file mode 100644
index 0000000..8c52a5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1646.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1646.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01646ent IS
+END c08s13b00x00p03n01i01646ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01646arch OF c08s13b00x00p03n01i01646ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if TRUE then
+      k := 5;
+      NULL;
+    elsif FALSE then
+      k := 5;
+      NULL;
+    end if;
+    assert NOT(k = 5) 
+      report "***PASSED TEST: c08s13b00x00p03n01i01646"
+      severity NOTE;
+    assert (k = 5) 
+      report "***FAILED TEST: c08s13b00x00p03n01i01646 - NULL statement has no effect other than to pass on to the next statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01646arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1647.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1647.vhd
new file mode 100644
index 0000000..79a482f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1647.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1647.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01647ent IS
+END c08s13b00x00p03n01i01647ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01647arch OF c08s13b00x00p03n01i01647ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : boolean := true;
+    variable kk: integer := 0;
+  BEGIN
+    case k is
+      when false    => NULL;
+      when true   => NULL;
+                     kk := 5;
+    end case;
+    assert NOT(kk=5) 
+      report "***PASSED TEST: c08s13b00x00p03n01i01647"
+      severity NOTE;
+    assert (kk=5) 
+      report "***FAILED TEST: c08s13b00x00p03n01i01647 - The execution of the null statement has no effect other than to pass on to the next statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01647arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1648.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1648.vhd
new file mode 100644
index 0000000..7a7f0d7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1648.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1648.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01648ent IS
+END c08s13b00x00p03n01i01648ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01648arch OF c08s13b00x00p03n01i01648ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for i in 1 to 10 loop
+      k := k + 1;
+      null;
+    end loop;
+    assert NOT(k = 10) 
+      report "***PASSED TEST: c08s13b00x00p03n01i01648"
+      severity NOTE;
+    assert (k = 10) 
+      report "***FAILED TEST: c08s13b00x00p03n01i01648 - The execution of the null statement has no effect other than to pass on to the next statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01648arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1649.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1649.vhd
new file mode 100644
index 0000000..c68064b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1649.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1649.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01649ent IS
+END c08s13b00x00p03n01i01649ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01649arch OF c08s13b00x00p03n01i01649ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables
+    variable FIRST_DONE  : BOOLEAN := FALSE;
+    variable SECOND_DONE : BOOLEAN := FALSE;
+  BEGIN
+    FIRST_DONE := TRUE;
+    null;
+    SECOND_DONE := TRUE;
+
+    -- Make sure that both statements surrounding the null
+    -- statement got executed.
+    assert NOT(FIRST_DONE and SECOND_DONE)
+      report "***PASSED TEST: c08s13b00x00p03n01i01649"
+      severity NOTE;
+    assert (FIRST_DONE and SECOND_DONE)
+      report "***FAILED TEST: c08s13b00x00p03n01i01649 - The execution of the null statement has no effect other than to pass on to the next statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01649arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1650.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1650.vhd
new file mode 100644
index 0000000..83b90dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1650.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1650.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01650ent IS
+END c08s13b00x00p03n01i01650ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01650arch OF c08s13b00x00p03n01i01650ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- local variables
+    variable LOCALI      : INTEGER := 47;
+    variable LOCALR      : REAL    := 47.0;
+    variable LOCALB      : BOOLEAN := TRUE;
+  BEGIN
+    -- Check for proper initialization.
+    assert (LOCALI = 47);
+    assert (LOCALR = 47.0);
+    assert (LOCALB = TRUE);
+
+    -- Execute the NULL statement.
+    null;
+
+    -- Verify that nothing has changed as a result.
+    assert NOT((LOCALI = 47)   and
+               (LOCALR = 47.0)   and
+               (LOCALB = TRUE))
+      report "***PASSED TEST: c08s13b00x00p03n01i01650"
+      severity NOTE;
+    assert ((LOCALI = 47)      and
+            (LOCALR = 47.0)      and
+            (LOCALB = TRUE))
+      report "***FAILED TEST: c08s13b00x00p03n01i01650 - The execution of the null statement has no effect on any of the local variable within the process." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01650arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1651.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1651.vhd
new file mode 100644
index 0000000..087ad2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1651.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1651.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p03n01i01651ent IS
+  procedure passive is
+  begin
+    null;                             -- or is that "dull"?
+  end passive;
+begin
+  passive;
+END c08s13b00x00p03n01i01651ent;
+
+ARCHITECTURE c08s13b00x00p03n01i01651arch OF c08s13b00x00p03n01i01651ent IS
+  function troo return boolean is
+  begin
+    null;
+    return true;
+  end troo;
+BEGIN
+  TESTING: PROCESS
+    variable v1 : integer := 1;
+    variable v2 : integer := 0;
+  BEGIN
+    if v1 > v2 then
+      null;
+    elsif v1 < v2 then
+      null;
+    else
+      null;
+    end if;
+
+    case troo is
+      when false => null;
+      when true => null;
+    end case;
+
+    loop
+      null;
+      exit;                         -- jump out of the infinite loop
+    end loop;
+
+    null;
+    assert FALSE 
+      report "***PASSED TEST: c08s13b00x00p03n01i01651"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p03n01i01651arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1653.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1653.vhd
new file mode 100644
index 0000000..2b83fb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1653.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1653.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c09s00b00x00p02n01i01653ent_a is
+  port (signal ss : in integer);
+end c09s00b00x00p02n01i01653ent_a;
+
+architecture c09s00b00x00p02n01i01653arch_a of c09s00b00x00p02n01i01653ent_a is
+begin
+  process
+  begin
+    wait;
+  end process;
+end c09s00b00x00p02n01i01653arch_a;
+
+ENTITY c09s00b00x00p02n01i01653ent IS
+  port ( Pt    : in BOOLEAN;
+         PTO    : out BIT) ;
+END c09s00b00x00p02n01i01653ent;
+
+ARCHITECTURE c09s00b00x00p02n01i01653arch OF c09s00b00x00p02n01i01653ent IS
+
+  component FO 
+    port (signal ss : in INTEGER);
+  end component ;
+  for Ls : FO use entity work.c09s00b00x00p02n01i01653ent_a(c09s00b00x00p02n01i01653arch_a);
+
+  signal S1, S2    : Integer;
+  signal S       : INTEGER;
+
+BEGIN
+  -- concurrent signal statement
+  S <= transport 5;
+  
+  -- concurrent assertion statement
+  assert ( not PT)
+    report " dead wire "
+    severity WARNING;
+  
+  -- generate
+  L_G_1:  for I in 1 to 1 generate
+    L_X_2:    block
+      signal S3 : Bit;
+    begin
+      S2 <= transport 1;
+    end block;
+  end generate;
+  
+  -- component instatiation
+  Ls : FO port map (S1);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s00b00x00p02n01i01653" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s00b00x00p02n01i01653arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1654.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1654.vhd
new file mode 100644
index 0000000..db00e36
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1654.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1654.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s00b00x00p04n01i01654ent IS
+END c09s00b00x00p04n01i01654ent;
+
+ARCHITECTURE c09s00b00x00p04n01i01654arch OF c09s00b00x00p04n01i01654ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE                            -- force assertion violation
+      report "PASS: process TESTING executes."
+      severity NOTE;
+
+    assert FALSE
+      report "***PASSED TEST: c09s00b00x00p04n01i01654 - it is really uncertain that which assertion note appear first for different simulator."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+  TEST: PROCESS
+  begin
+    assert FALSE
+      report "PASS: process TEST executes."
+      severity NOTE;
+    
+    -- Note: It does not matter which process executes first. (The order
+    --      of process execution is not defined by the LRM, and dependence
+    --      on the execution order is not allowed.)
+    
+    wait;                                   -- wait forever
+  END PROCESS TEST;
+
+END c09s00b00x00p04n01i01654arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1655.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1655.vhd
new file mode 100644
index 0000000..90eb032
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1655.vhd
@@ -0,0 +1,142 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1655.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c09s00b00x00p05n01i01655pkg is
+  procedure cpc (constant loc : string);
+end c09s00b00x00p05n01i01655pkg;
+
+package body c09s00b00x00p05n01i01655pkg is
+  procedure cpc (constant loc : string) is      -- concurrent procedure
+  begin
+    assert false
+      report "Concurrent procedure called from " & loc            
+      severity note ;
+  end cpc;
+end c09s00b00x00p05n01i01655pkg;
+
+use work.c09s00b00x00p05n01i01655pkg.all;
+
+entity c09s00b00x00p05n01i01655ent_a is
+  port (signal pi : in  bit;
+        signal po : out bit
+        );
+begin
+  cas : assert false
+    report "Labeled concurrent assert called from component."
+    severity note ;
+
+  cpcc : cpc("component entity");
+
+  ppsc :                                -- passive process stmt
+  process (pi)
+  begin
+    assert false
+      report "Passive process can be labeled in component."
+      severity note ;
+  end process;
+end c09s00b00x00p05n01i01655ent_a;
+
+architecture c09s00b00x00p05n01i01655arch_a of c09s00b00x00p05n01i01655ent_a is
+begin
+  cpc("component architecture");
+end;
+
+use work.c09s00b00x00p05n01i01655pkg.all, work.c09s00b00x00p05n01i01655ent_a;
+
+ENTITY c09s00b00x00p05n01i01655ent IS
+  port (signal pi : in  bit;
+        signal po : out bit
+        );
+begin
+  cas : assert false
+    report "Labeled concurrent assert called from entity."
+    severity note ;
+  
+  cpce : cpc("entity.");
+  
+  ppse :                                -- passive process stmt
+  process (pi)
+  begin
+    assert false
+      report "Passive process can be labeled in entity."
+      severity note ;
+  end process;
+END c09s00b00x00p05n01i01655ent;
+
+ARCHITECTURE c09s00b00x00p05n01i01655arch OF c09s00b00x00p05n01i01655ent IS
+  signal lab_sig : boolean := true;
+  
+  component comp
+    port (signal pi : in bit;
+          signal po : out bit
+          );
+  end component; -- comp
+  for lcia : comp use entity work.c09s00b00x00p05n01i01655ent_a(c09s00b00x00p05n01i01655arch_a)
+    port map (pi, po);
+BEGIN
+  casa : assert false
+    report "Labeled concurrent assert called from architecture."
+    severity note ;
+  
+  cpca : cpc("architecture.");
+  
+  ppsa : process (pi)
+  begin
+    assert false
+      report "Passive process can be labeled in architecture."
+      severity note ;
+  end process;
+  
+  lba: block
+  begin
+    cpcb : cpc("block.");
+    
+    casb : assert false
+      report "Labeled concurrent assert called from labeled block."
+      severity note ;
+  end block lba;
+  
+  csa : lab_sig <= false;
+  assert lab_sig
+    report "Labeled concurrent signal assignment executed in architecture."
+    severity note ;
+  
+  lcia : comp
+    port map (pi => pi, po => po);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s00b00x00p05n01i01655 - This test need manual check to the ASSERTION statement."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s00b00x00p05n01i01655arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1658.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1658.vhd
new file mode 100644
index 0000000..8d34ca4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1658.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1658.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity E  is
+  port ( S_in : in bit; S_out : out bit) ;
+end E;
+
+entity C1  is
+  port ( A : bit; B :out bit) ;
+end C1;
+
+use work.c1;
+
+ENTITY c09s01b00x00p02n01i01658ent IS
+  port ( B : bit ) ;
+END c09s01b00x00p02n01i01658ent;
+
+ARCHITECTURE c09s01b00x00p02n01i01658arch OF c09s01b00x00p02n01i01658ent IS
+
+BEGIN
+
+  lab : block 
+    component C1
+      port ( A : bit; B : out bit );
+    end component ; -- C1
+    
+    for all : C1 use entity work.E
+      port map ( S_in => A, S_out => B ) ;
+    
+    type    T1 is ('0', '1');
+    subtype T2 is integer range 0 to 7;
+    
+    signal S1    : real;
+    alias  S1_too    : real is S1;
+    
+    attribute ATTR : T1;
+    attribute ATTR of ALL : signal is '1';
+
+  begin
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE 
+        report "***PASSED TEST: c09s01b00x00p02n01i01658" 
+        severity NOTE;
+      wait;
+    END PROCESS TESTING;
+  end block lab;
+
+
+END c09s01b00x00p02n01i01658arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1659.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1659.vhd
new file mode 100644
index 0000000..61c30e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1659.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1659.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p02n01i01659ent IS
+END c09s01b00x00p02n01i01659ent;
+
+ARCHITECTURE c09s01b00x00p02n01i01659arch OF c09s01b00x00p02n01i01659ent IS
+
+BEGIN
+
+  B1:block --<< no guard condition here
+  begin
+    process
+    begin
+      null ;
+      wait;
+    end process ;
+  end block ;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s01b00x00p02n01i01659" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p02n01i01659arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc166.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc166.vhd
new file mode 100644
index 0000000..1b54754
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc166.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc166.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x00p01n01i00166ent IS
+END c04s03b03x00p01n01i00166ent;
+
+ARCHITECTURE c04s03b03x00p01n01i00166arch OF c04s03b03x00p01n01i00166ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    V1    : INTEGER := 1;
+    alias       V1_A1    : INTEGER is V1;
+    variable   pass   : integer := 0;
+  BEGIN
+    assert V1    = 1;
+    assert V1_A1    = 1;
+    if (V1 /= 1 or V1_A1 /= 1) then
+      pass := 1;
+    end if;
+
+
+    V1 := 2;      -- change value...
+    assert V1    = 2;
+    assert V1_A1    = 2;   -- ... check read
+    if (V1 /= 2 or V1_A1 /= 2) then
+      pass := 1;
+    end if;
+
+    V1_A1 := 3;      -- change value using alias
+    assert V1    = 3;   -- ... check that value changed
+    assert V1_A1    = 3;
+    if (V1 /= 3 or V1_A1 /= 3) then
+      pass := 1;
+    end if;
+
+    wait for 5 ns;
+    assert NOT(   pass = 0   ) 
+      report "***PASSED TEST: c04s03b03x00p01n01i00166"
+      severity NOTE;
+    assert (   pass = 0   ) 
+      report "***FAILED TEST: c04s03b03x00p01n01i00166 - Alias for variable object test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x00p01n01i00166arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1662.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1662.vhd
new file mode 100644
index 0000000..bf54c72
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1662.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1662.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p03n01i01662ent IS
+  port (A, B: inout bit);
+END c09s01b00x00p03n01i01662ent;
+
+ARCHITECTURE c09s01b00x00p03n01i01662arch OF c09s01b00x00p03n01i01662ent IS
+  signal       S1, S2, S3   : bit       := '0';
+  constant    gm      : natural    := 0;
+BEGIN
+
+  BL: block                          -- no_failure_here
+    generic    (n: natural:= 2);
+    generic map    (gm);
+    port       (A, B: inout bit);
+    port map    (S1, S2);
+  begin
+  end block BL;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s01b00x00p03n01i01662"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p03n01i01662arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1665.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1665.vhd
new file mode 100644
index 0000000..3da3c45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1665.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1665.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p05n01i01665ent IS
+  port (A,B : inout bit);
+END c09s01b00x00p05n01i01665ent;
+
+ARCHITECTURE c09s01b00x00p05n01i01665arch OF c09s01b00x00p05n01i01665ent IS
+
+BEGIN
+  BL: block
+  begin
+  end block BL; -- No_failure_here
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s01b00x00p05n01i01665" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p05n01i01665arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc167.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc167.vhd
new file mode 100644
index 0000000..427f106
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc167.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc167.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x00p01n01i00167ent IS
+END c04s03b03x00p01n01i00167ent;
+
+ARCHITECTURE c04s03b03x00p01n01i00167arch OF c04s03b03x00p01n01i00167ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant    C1 : INTEGER := 1;
+    alias       a1 : INTEGER is C1;
+
+    constant    C2 : STRING := "Hello";
+    alias       a2 : STRING(4 downto 1) is C2(1 to 4);
+    alias       a3 : STRING(1 to 5)    is C2;
+
+    alias       a4 : CHARACTER is C2(2);
+  BEGIN
+    assert C1 = 1;
+    assert A1 = 1;
+    assert C2 = "Hello";
+    assert A2 = "Hell";
+    assert A3 = "Hello";
+    assert A4 = 'e';
+    assert NOT(    C1 = 1   and
+                   A1 = 1   and
+                   C2 = "Hello"   and
+                   A2 = "Hell"   and
+                   A3 = "Hello"   and
+                   A4 = 'e'   )
+      report "***PASSED TEST: c04s03b03x00p01n01i00167"
+      severity NOTE;
+    assert (    C1 = 1   and
+                A1 = 1   and
+                C2 = "Hello"   and
+                A2 = "Hell"   and
+                A3 = "Hello"   and
+                A4 = 'e'   )
+      report "***FAILED TEST: c04s03b03x00p01n01i00167 - Alias for constant object test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x00p01n01i00167arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1677.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1677.vhd
new file mode 100644
index 0000000..3d2b300
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1677.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1677.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p08n01i01677ent IS
+END c09s01b00x00p08n01i01677ent;
+
+ARCHITECTURE c09s01b00x00p08n01i01677arch OF c09s01b00x00p08n01i01677ent IS
+
+  SUBTYPE    bit_vector_4 is bit_vector ( 0 to 3 );
+  SUBTYPE    bit_vector_8 is bit_vector ( 0 to 7 );
+  SIGNAL     v_slice : bit_vector_8 := B"1010_1100";
+
+BEGIN
+
+  labeled : block
+    port ( v : OUT bit_vector_4 := "1010");
+    port map ( v_slice ( 0 to 3 ));
+  begin
+    v <= B"0101" after 10 ns; -- only driver created ..
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert (v_slice = B"1010_1100")
+      report "Condition error: value of signal V_SLICE incorrect"
+      severity failure;
+
+    wait for 10 ns;
+
+    assert NOT(v_slice = B"0101_1100")
+      report "***PASSED TEST: c09s01b00x00p08n01i01677"
+      severity NOTE;
+    assert (v_slice = B"0101_1100")
+      report "***FAILED TEST: c09s01b00x00p08n01i01677 - The value of signal V_SLICE was not properly updated."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p08n01i01677arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1678.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1678.vhd
new file mode 100644
index 0000000..2074ee3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1678.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1678.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p08n01i01678ent IS
+END c09s01b00x00p08n01i01678ent;
+
+ARCHITECTURE c09s01b00x00p08n01i01678arch OF c09s01b00x00p08n01i01678ent IS
+  signal   S2 : integer := 2;
+BEGIN
+  B: block
+    generic (    G1 : INTEGER;
+                 G2 : STRING);
+    generic map (    G1 => 10, 
+                     G2 => "Hi");
+    port (      P1 : INTEGER);
+    port map (   P1 => S2);
+  begin
+    assert NOT( G1 = 10 and G2 = "Hi" and P1 = 2 )
+      report "***PASSED TEST: c09s01b00x00p08n01i01678"
+      severity NOTE;
+    assert ( G1 = 10 and G2 = "Hi" and P1 = 2 )
+      report "***FAILED TEST: c09s01b00x00p08n01i01678 - Certain values do not be imported from the enclosing enviornment into the block."
+      severity ERROR;
+  end block;
+
+END c09s01b00x00p08n01i01678arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1679.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1679.vhd
new file mode 100644
index 0000000..c50c895
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1679.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1679.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p08n01i01679ent IS
+END c09s01b00x00p08n01i01679ent;
+
+ARCHITECTURE c09s01b00x00p08n01i01679arch OF c09s01b00x00p08n01i01679ent IS
+  constant    size    : INTEGER := 3;
+  signal    S    : STRING(1 to size) := "Hi!";
+BEGIN
+  B: block
+    generic    (size : INTEGER);
+    generic map    (size => size);
+    port       (P : in STRING(1 to size));
+    port map    (P => S);
+  begin
+    assert NOT(P="Hi!") 
+      report "***PASSED TEST: c09s01b00x00p08n01i01679"
+      severity NOTE;
+    assert (P="Hi!") 
+      report "***FAILED TEST: c09s01b00x00p08n01i01679 - Block statement test failed."
+      severity ERROR;
+  end block;
+
+END c09s01b00x00p08n01i01679arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc168.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc168.vhd
new file mode 100644
index 0000000..88d9b4c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc168.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc168.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x00p01n01i00168ent IS
+END c04s03b03x00p01n01i00168ent;
+
+ARCHITECTURE c04s03b03x00p01n01i00168arch OF c04s03b03x00p01n01i00168ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    V1    : INTEGER := 1;
+    alias       V1_A1    : INTEGER is V1;
+    -- scalar alias of scalar
+    -- alias of variable
+    alias       V1_A2    : INTEGER is V1_A1;
+    -- alias of alias
+    
+    variable   pass   : integer := 0;
+  BEGIN
+    assert V1    = 1;
+    assert V1_A1    = 1;
+    assert V1_A2    = 1;
+    if (V1 /= 1 or V1_A1 /= 1 or V1_A2 /= 1) then   
+      pass := 1;
+    end if;
+    
+    V1 := 2;         -- change value...
+    assert V1    = 2;
+    assert V1_A1    = 2;      -- ... check read
+    assert V1_A2    = 2;      -- ... check read
+    if (V1 /= 2 or V1_A1 /= 2 or V1_A2 /= 2) then   
+      pass := 1;
+    end if;
+    
+    V1_A1 := 3;         -- change value using alias
+    assert V1    = 3;      -- ... check that value changed
+    assert V1_A1    = 3;
+    assert V1_A2    = 3;
+    if (V1 /= 3 or V1_A1 /= 3 or V1_A2 /= 3) then   
+      pass := 1;
+    end if;
+
+    V1_A2 := 4;         -- change value using alias
+    assert V1    = 4;      -- ... check that value changed
+    assert V1_A1    = 4;
+    assert V1_A2    = 4;
+    if (V1 /= 4 or V1_A1 /= 4 or V1_A2 /= 4) then   
+      pass := 1;
+    end if;
+
+    wait for 5 ns;
+    assert NOT(   pass = 0   ) 
+      report "***PASSED TEST: c04s03b03x00p01n01i00168"
+      severity NOTE;
+    assert (   pass = 0   ) 
+      report "***FAILED TEST: c04s03b03x00p01n01i00168 - Alias of alias variable test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x00p01n01i00168arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1681.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1681.vhd
new file mode 100644
index 0000000..2a7c1ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1681.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1681.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p09n01i01681ent IS
+END c09s01b00x00p09n01i01681ent;
+
+ARCHITECTURE c09s01b00x00p09n01i01681arch OF c09s01b00x00p09n01i01681ent IS
+
+BEGIN
+
+  lab : block
+  begin
+  end block lab;                       -- labels match
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s01b00x00p09n01i01681" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p09n01i01681arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1684.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1684.vhd
new file mode 100644
index 0000000..2c6e00e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1684.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1684.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p02n01i01684ent IS
+END c09s02b00x00p02n01i01684ent;
+
+ARCHITECTURE c09s02b00x00p02n01i01684arch OF c09s02b00x00p02n01i01684ent IS
+  signal done : bit;
+  signal bomb : bit;
+BEGIN
+  process (done, bomb)
+  begin
+  end process;
+  
+  TESTING : PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s02b00x00p02n01i01684" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p02n01i01684arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc169.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc169.vhd
new file mode 100644
index 0000000..ac04354
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc169.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc169.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x00p01n01i00169ent IS
+END c04s03b03x00p01n01i00169ent;
+
+ARCHITECTURE c04s03b03x00p01n01i00169arch OF c04s03b03x00p01n01i00169ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    V2 : STRING(1 to 5) := "Hello";
+    alias       a3 : STRING(1 to 5) is V2;   -- composite alias of composite
+    alias       a2 : STRING(4 downto 1) is V2(1 to 4);
+    
+    alias       a4 : CHARACTER is V2(4);   -- scalar alias of composite
+  BEGIN
+    assert V2    = "Hello";
+    assert A2    = "Hell";
+    assert V2(1)    = 'H';
+    assert A2(4)    = 'H';
+    assert V2(2)    = 'e';
+    assert A2(3)    = 'e';
+    assert A3    = "Hello";
+    assert A4    = 'l';
+
+    wait for 5 ns;
+    assert NOT(   V2       = "Hello"   and 
+                  A2       = "Hell"   and 
+                  V2(1)    = 'H'      and 
+                  A2(4)    = 'H'      and 
+                  V2(2)    = 'e'      and 
+                  A2(3)    = 'e'      and 
+                  A3       = "Hello"   and 
+                  A4       = 'l'      )
+      report "***PASSED TEST: c04s03b03x00p01n01i00169"
+      severity NOTE;
+    assert (   V2       = "Hello"   and 
+               A2       = "Hell"   and 
+               V2(1)    = 'H'      and 
+               A2(4)    = 'H'      and 
+               V2(2)    = 'e'      and 
+               A2(3)    = 'e'      and 
+               A3       = "Hello"   and 
+               A4       = 'l'      )
+      report "***FAILED TEST: c04s03b03x00p01n01i00169 - Alias of alias composite type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x00p01n01i00169arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1690.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1690.vhd
new file mode 100644
index 0000000..798b154
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1690.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1690.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01690ent IS
+END c09s02b00x00p03n01i01690ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01690arch OF c09s02b00x00p03n01i01690ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    bus_idx is         range 0 to 63;
+    subtype cmd_idx is bus_idx range 0 to 7;
+    variable         v : cmd_idx := 5;
+    variable    untrue : boolean := false;
+  BEGIN
+    assert NOT(v=5 and untrue = false) 
+      report "***PASSED TEST: c09s02b00x00p03n01i01690" 
+      severity NOTE;
+    assert (v=5 and untrue = false) 
+      report "***FAILED TEST: c09s02b00x00p03n01i01690 - Configuration  declarations are not permitted in process statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p03n01i01690arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1691.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1691.vhd
new file mode 100644
index 0000000..e755c9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1691.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1691.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01691ent IS
+  port (P: in Bit);
+END c09s02b00x00p03n01i01691ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01691arch OF c09s02b00x00p03n01i01691ent IS
+
+BEGIN
+  process (P)
+  begin
+  end process;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s02b00x00p03n01i01691" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p03n01i01691arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1698.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1698.vhd
new file mode 100644
index 0000000..e6e2186
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1698.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1698.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p05n01i01698ent IS
+END c09s02b00x00p05n01i01698ent;
+
+ARCHITECTURE c09s02b00x00p05n01i01698arch OF c09s02b00x00p05n01i01698ent IS
+  signal s : integer;
+BEGIN
+  TEST : PROCESS(s)
+  BEGIN
+  END PROCESS TEST;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s02b00x00p05n01i01698"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p05n01i01698arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc17.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc17.vhd
new file mode 100644
index 0000000..2845166
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc17.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc17.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p08n01i00017ent IS
+END c04s02b00x00p08n01i00017ent;
+
+ARCHITECTURE c04s02b00x00p08n01i00017arch OF c04s02b00x00p08n01i00017ent IS
+
+  -- Forward declaration of the function.
+  function WIRED_OR( S : BIT_VECTOR ) return BIT;
+
+  -- Declare the subtype.
+  subtype RBIT is WIRED_OR BIT;
+
+  -- Declare the actual function.
+  function WIRED_OR( S : BIT_VECTOR ) return BIT is
+  begin
+    assert FALSE 
+      report "***PASSED TEST: c04s02b00x00p08n01i00017" 
+      severity NOTE;
+    if  ( (S(0) = '1') OR (S(1) = '1')) then
+      return '1';
+    end if;
+    return '0';
+  end WIRED_OR;
+
+  -- Declare a signal of that type.  A resolved signal.
+  signal S : RBIT;
+
+BEGIN
+
+  -- A concurrent signal assignment.  Driver # 1.
+  S <= '1';
+
+  TESTING: PROCESS
+  BEGIN
+    -- Verify that resolution function getting called.
+    S <= '1' after 10 ns;
+    wait on S;
+    assert NOT( S = '1' ) 
+      report "***PASSED TEST: c04s02b00x00p08n01i00017"
+      severity NOTE;
+    assert ( S = '1' )
+      report "***FAILED TEST: c04s02b00x00p08n01i00017 - If a resolution function name appears in a subtype, all signals declared to be of that subtype are resolved by that function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p08n01i00017arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1703.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1703.vhd
new file mode 100644
index 0000000..2c8d26f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1703.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1703.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p05n01i01703ent IS
+END c09s02b00x00p05n01i01703ent;
+
+ARCHITECTURE c09s02b00x00p05n01i01703arch OF c09s02b00x00p05n01i01703ent IS
+  signal s : boolean := false;
+BEGIN
+
+  TESTING: PROCESS
+    type result_type is (fail, pass);
+    variable result : result_type := fail;
+    variable i, j   : integer;
+    variable k   : integer := 0;
+  BEGIN
+    --
+    -- Test all sequential statements in this process
+    --
+    s <= true;                        -- signal assignment        
+    j := 1;                           -- variable assignment
+    i := 0;
+    
+    L1: while  ( i < 10 )  loop       -- conditional loop
+      if i > 2 then
+        exit;
+      end if;
+      case i is
+        when 0 =>
+          L2: for j in 1 to 3 loop
+            case j is
+              when 3 =>       -- should never execute because of
+                i := i + 1; -- alternative 2
+                k := 1;
+                exit;
+                assert false
+                  report "exit in loop 2 case failed."
+                  severity note;
+              when 2 =>
+                i := i + 1;
+                next L1;
+                k := 1;
+                assert false     -- should never execute
+                  report "next in loop 2 case failed."
+                  severity note;
+              when 1 =>
+                assert false
+                  report "first iteration of loop 2."
+                  severity note ;
+                next;     -- applies to loop L2
+              when others =>
+                --
+                -- This should never be executed but is
+                -- required by the 1076-1987 spec. which
+                -- says the subtype of 'j' is the same as
+                -- the base type (integer) and not constrained
+                -- to the range "1 to 3".
+                --
+                k := 1;
+                assert false
+                  report "Should never get here."
+                  severity note ;
+            end case;
+            k := 1;
+            assert false      -- should never execute
+              report "next in loop 2 failed."
+              severity note;
+          end loop L2;
+        when 2 =>
+          s <= false after 5 ns;
+          wait for 6 ns;
+          assert not s
+            report "wait statement in loop L1 failed."
+            severity note ;
+          
+          i := i +1;
+        when 1 =>
+          null;
+          assert false
+            report "null statement and next statement worked."
+            severity note ;
+          i := i +1;
+        when others =>
+          k := 1;
+          assert false
+            report "exit in if statement in loop L1 failed."
+            severity note ;
+          exit;
+      end case;
+    end loop L1;
+
+    wait for 50 ns;
+
+    assert NOT(s=false and k = 0 and j=1) 
+      report "***PASSED TEST: c09s02b00x00p05n01i01703" 
+      severity NOTE;
+    assert (s=false and k = 0 and j=1) 
+      report "***FAILED TEST: c09s02b00x00p05n01i01703 - Process statement execution failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p05n01i01703arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1704.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1704.vhd
new file mode 100644
index 0000000..329120b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1704.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1704.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p07n01i01704ent IS
+END c09s02b00x00p07n01i01704ent;
+
+ARCHITECTURE c09s02b00x00p07n01i01704arch OF c09s02b00x00p07n01i01704ent IS
+  signal   S :    Bit;
+BEGIN
+  TESTING: PROCESS( S )
+    -- local variables.
+    variable INITED : BOOLEAN := FALSE;
+    variable CNT    : INTEGER := 0;
+    variable NEWTIME: TIME;
+    variable k      : integer := 1;
+  BEGIN
+    -- Take care of the first run.
+    if  (not( INITED )) then
+      INITED  := TRUE;
+      CNT     := 0;
+      S       <= (not S) after 1 ns;
+      NEWTIME := NOW + 1 ns;
+
+      -- Otherwise, take care of all subsequent runs.
+      -- NOTE:  Take care of the last time we will get awakened.
+    elsif (NOW /= TIME'HIGH) then
+      
+      -- Verify that we woke up when S was updated.
+      if NOT(( S'EVENT ) and ( NEWTIME = NOW )) then
+        k := 0;
+      end if;
+      
+      -- See if we should continue.  If so, do it.
+      CNT    := CNT + 1;
+      if  (CNT <= 50) then
+        S       <= (not S) after 1 ns;
+        NEWTIME := NOW + 1 ns;
+      end if;
+    end if;
+    if (CNT = 50) then
+      assert NOT( k=1 )
+        report "***PASSED TEST: c09s02b00x00p07n01i01704"
+        severity NOTE;
+      assert ( k=1 )
+        report "***FAILED TEST: c09s02b00x00p07n01i01704 - The process statement is assumed to contain an implicit wait statement if a sensitivity list appears following the reserved word process."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s02b00x00p07n01i01704arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1705.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1705.vhd
new file mode 100644
index 0000000..992a567
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1705.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1705.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p07n01i01705ent IS
+END c09s02b00x00p07n01i01705ent;
+
+ARCHITECTURE c09s02b00x00p07n01i01705arch OF c09s02b00x00p07n01i01705ent IS
+  signal   S1 :    Bit;
+  signal   S2 :    Bit;
+BEGIN
+  TESTING: PROCESS( S1 )
+  BEGIN
+    S1   <=   '1' after 10 ns;
+  END PROCESS TESTING;
+
+  TESTING1: PROCESS
+  BEGIN
+    S2   <=   '1' after 10 ns;
+    wait on S2;
+    assert NOT(S1=S2) 
+      report "***PASSED TEST: c09s02b00x00p07n01i01705"
+      severity NOTE;
+    assert (S1=S2) 
+      report "***FAILED TEST: c09s02b00x00p07n01i01705 - The process statement is assumed to contain an implicit wait statement if a sensitivity list appears following the reserved word process."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING1;
+
+END c09s02b00x00p07n01i01705arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1709.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1709.vhd
new file mode 100644
index 0000000..879ad90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1709.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1709.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c09s02b00x00p10n01i01709pkg is
+
+  -- Type declarations.
+  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
+  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
+
+  -- Define the bus resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
+
+  -- Further type declarations.
+  subtype SWITCH_T       is switchF SWITCH_LEVEL;
+  type    WORD           is array(0 to 31) of SWITCH_T;
+
+end c09s02b00x00p10n01i01709pkg;
+
+package body c09s02b00x00p10n01i01709pkg is
+
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
+  begin
+    return( S(1) );
+  end switchf;
+
+end c09s02b00x00p10n01i01709pkg;
+
+
+ENTITY c09s02b00x00p10n01i01709ent IS
+END c09s02b00x00p10n01i01709ent;
+
+use work.c09s02b00x00p10n01i01709pkg.all;
+ARCHITECTURE c09s02b00x00p10n01i01709arch OF c09s02b00x00p10n01i01709ent IS
+  signal A       : WORD;
+BEGIN
+  -- Test signal arrays indexed using literal constants.  (locally static)
+  TESTING: PROCESS(A(1))
+    variable INITED : BOOLEAN := FALSE;
+    variable NewTime: TIME;
+  BEGIN
+    -- Perform the first piece of assignments.
+    if  (not(INITED)) then
+      INITED := TRUE;
+      A( 1 ) <= 'X' after 10 ns;
+      NewTime := NOW + 10 ns;
+    end if;
+    if (now = NewTime) then
+      assert NOT( A(1) = 'X' )
+        report "***PASSED TEST: c09s02b00x00p10n01i01709"
+        severity NOTE;
+      assert ( A(1) = 'X' )
+        report "***FAILED TEST: c09s02b00x00p10n01i01709 - Signal arrays indexed using literal constants may be used in the sentitivity list of a porcess statement."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s02b00x00p10n01i01709arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc171.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc171.vhd
new file mode 100644
index 0000000..4679ace
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc171.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc171.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n01i00171ent IS
+  port (ABus    : in      bit;
+        DBus    : out     bit;
+        MemReq  : in      bit;
+        BusReq  : inout   bit;
+        BusAck  : buffer  bit;
+        DataRdy : linkage bit);
+  constant Board : integer := 7 ;
+END c04s03b03x01p03n01i00171ent;
+
+ARCHITECTURE c04s03b03x01p03n01i00171arch OF c04s03b03x01p03n01i00171ent IS
+  alias SIGN1 : bit is BusReq;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c04s03b03x01p03n01i00171" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n01i00171arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1710.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1710.vhd
new file mode 100644
index 0000000..345de2e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1710.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1710.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p10n01i01710ent IS
+END c09s02b00x00p10n01i01710ent;
+
+ARCHITECTURE c09s02b00x00p10n01i01710arch OF c09s02b00x00p10n01i01710ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c09s02b00x00p10n01i01710"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c09s02b00x00p10n01i01710"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c09s02b00x00p10n01i01710arch;
+
+-- CONFIGURATION c09s02b00x00p10n01i01710cfg OF c09s02b00x00p10n01i01710ent IS
+--     FOR c09s02b00x00p10n01i01710arch
+--     END FOR;
+-- END c09s02b00x00p10n01i01710cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1711.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1711.vhd
new file mode 100644
index 0000000..b799872
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1711.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1711.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c09s02b00x00p10n01i01711pkg is
+
+  -- Type declarations.
+  type    SWITCH_LEVEL   is ( '0', '1', 'X' );
+  type    S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
+
+  -- Define the bus resolution function.
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
+
+  -- Further type declarations.
+  subtype SWITCH_T       is switchF SWITCH_LEVEL;
+--   type    WORD           is array(0 to 31) of SWITCH_T;
+  type    WORD           is array(1 to 32) of SWITCH_T;
+
+end c09s02b00x00p10n01i01711pkg;
+
+package body  c09s02b00x00p10n01i01711pkg is
+
+  function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
+  begin
+    return( S(1) );
+  end switchf;
+
+end c09s02b00x00p10n01i01711pkg;
+
+
+ENTITY c09s02b00x00p10n01i01711ent IS
+  generic ( GenFive : in INTEGER := 12 );
+END c09s02b00x00p10n01i01711ent;
+use work.c09s02b00x00p10n01i01711pkg.all;
+ARCHITECTURE c09s02b00x00p10n01i01711arch OF c09s02b00x00p10n01i01711ent IS
+  -- Local constants.
+  constant  Three : integer := 3; 
+
+  -- Local signals.
+  signal A       : WORD;
+
+BEGIN
+  -- Test signal arrays indexed using a generic constants.  (locally static)
+  TESTING: PROCESS(A(GenFive))
+    -- Local variables.
+    variable INITED : BOOLEAN := FALSE;
+    variable NewTime: TIME;
+  BEGIN
+    -- Perform the first piece of assignments.
+    if  (not(INITED)) then
+      INITED       := TRUE;
+      A( GenFive ) <= 'X' after 10 ns;
+      NewTime    := NOW + 10 ns;
+    end if;
+    if (now = NewTime) then
+      assert NOT( A(GenFive) = 'X' )
+        report "***PASSED TEST: c09s02b00x00p10n01i01711"
+        severity NOTE;
+      assert ( A(GenFive) = 'X' )
+        report "***FAILED TEST: c09s02b00x00p10n01i01711 - Signal arrays indexed using a generic constants may be used in the sentitivity list of a porcess statement."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s02b00x00p10n01i01711arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1717.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1717.vhd
new file mode 100644
index 0000000..f2f3173
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1717.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1717.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p13n01i01717ent IS
+END c09s02b00x00p13n01i01717ent;
+
+ARCHITECTURE c09s02b00x00p13n01i01717arch OF c09s02b00x00p13n01i01717ent IS
+  -- Local signals.
+  signal A, B : BIT := '0';
+BEGIN
+  TESTING: PROCESS
+    -- Local variables.
+    variable STARTED: BOOLEAN    := FALSE;
+    variable OldTime: TIME    := 250 ns;
+    variable OldInt : INTEGER    := 13;
+    variable OldA,
+      OldB   : BIT;
+    variable I      : INTEGER;
+  BEGIN
+    -- Initialize variables for this first pass.
+    if  (NOT(STARTED)) then
+      OldTime := NOW;
+      OldInt  := 47;
+      OldA    := A;
+      OldB    := B;
+      I       := 0;
+      STARTED := TRUE;
+    elsif (I > 15) then
+      assert NOT(I = 16) 
+        report "***PASSED TEST: c09s02b00x00p13n01i01717"
+        severity NOTE;
+      assert (I = 16) 
+        report "***FAILED TEST: c09s02b00x00p13n01i01717 - The execution of a process statement consists of the repetitive execution of its sequence of statements."
+        severity ERROR;
+      wait;
+    end if;
+    -- Verify that no variables, time or signals have changed.
+    assert( OldInt = 47 )   severity ERROR;
+    assert( OldTime = NOW ) severity ERROR;
+    assert( OldA = A )      severity ERROR;
+    assert( OldB = B )      severity ERROR;
+    I := I + 1;
+  END PROCESS TESTING;
+
+  -- This process merely makes assignments to the signals A and B.
+  ASSIGN_PROCESS:   process
+  begin
+    A <= '1' ;
+    B <= '1';
+    wait;
+  end process;
+
+END c09s02b00x00p13n01i01717arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1718.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1718.vhd
new file mode 100644
index 0000000..1b27aa7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1718.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1718.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p14n01i01718ent IS
+
+  -- Local procedure.
+  procedure proccall;
+  procedure proccall is
+  begin
+    assert( TRUE ) severity NOTE;
+  end;
+
+begin
+
+  -- Try a concurrent assertion statement.
+  assert( TRUE ) severity NOTE;
+
+  -- Try a passive concurrent procedure call.
+  proccall;
+
+  -- Try a passive process statement.
+  process
+  begin
+    assert( TRUE ) severity NOTE;
+    wait;
+  end process;
+
+END c09s02b00x00p14n01i01718ent;
+
+ARCHITECTURE c09s02b00x00p14n01i01718arch OF c09s02b00x00p14n01i01718ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s02b00x00p14n01i01718"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p14n01i01718arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1719.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1719.vhd
new file mode 100644
index 0000000..cb4ea2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1719.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1719.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p16n02i01719ent IS
+END c09s02b00x00p16n02i01719ent;
+
+ARCHITECTURE c09s02b00x00p16n02i01719arch OF c09s02b00x00p16n02i01719ent IS
+  SUBTYPE bit_4 is bit_vector ( 0 to 3);
+  SUBTYPE bit_8 is bit_vector ( 0 to 7);
+
+  SIGNAL  s  : bit_8 := B"0000_0000";
+  SIGNAL  s4 : bit_4;
+  SIGNAL  s5 : bit_4;
+BEGIN
+
+  -- trigger only one element.
+  s (6) <= '1' after 10 ns;
+
+  TESTING: PROCESS(s(0 to 3))
+  BEGIN
+    assert (NOW <= 0 fs ) 
+      report "***FAILED TEST: c09s02b00x00p16n02i01719 - This process should be inactive."
+      severity ERROR;
+  END PROCESS TESTING;
+
+  p2 : PROCESS (s(3 to 6))
+  begin
+    assert NOT((s(3 to 6) = B"0001") and (NOW = 10 ns))
+      report "***PASSED TEST: c09s02b00x00p16n02i01719 - This test is passed only is the FAILED assertion did not appear."
+      severity NOTE;
+  end process p2;
+
+
+END c09s02b00x00p16n02i01719arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc172.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc172.vhd
new file mode 100644
index 0000000..9b4ef8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc172.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc172.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n02i00172ent IS
+END c04s03b03x01p03n02i00172ent;
+
+ARCHITECTURE c04s03b03x01p03n02i00172arch OF c04s03b03x01p03n02i00172ent IS
+  signal    Data    : integer;
+  alias    SIGN2    : integer is Data;  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Data   <= 100 after 50 ns;
+    wait for 50 ns;
+    assert NOT( SIGN2 = 100 )
+      report "***PASSED TEST: c04s03b03x01p03n02i00172"      severity NOTE;
+    assert ( SIGN2 = 100 )
+      report "***FAILED TEST: c04s03b03x01p03n02i00172 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n02i00172arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1720.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1720.vhd
new file mode 100644
index 0000000..237ecee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1720.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1720.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p01n02i01720ent IS
+END c12s06b01x00p01n02i01720ent;
+
+ARCHITECTURE c12s06b01x00p01n02i01720arch OF c12s06b01x00p01n02i01720ent IS
+
+  -- Global type declaration.
+  type NIBBLE is array( 0 to 3 ) of BIT;
+
+  -- Global signals.
+  SIGNAL B   : BIT := '1';
+  SIGNAL N   : NIBBLE := B"1111";
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- If one driver created, it will take on the indicated value.
+    B <= '0' after 10 ns;
+    N <= B"0000" after 10 ns;
+    wait on N,B;
+    assert NOT( B='0' and N=B"0000" )
+      report "***PASSED TEST: c12s06b01x00p01n02i01720"
+      severity NOTE;
+    assert ( B='0' and N=B"0000" )
+      report "***FAILED TEST: c12s06b01x00p01n02i01720 - At least one driver gets created for eah signal which is assigned to either directly or indirectly inside of a process."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p01n02i01720arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1721.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1721.vhd
new file mode 100644
index 0000000..9e4a264
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1721.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1721.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p01n02i01721ent IS
+END c12s06b01x00p01n02i01721ent;
+
+ARCHITECTURE c12s06b01x00p01n02i01721arch OF c12s06b01x00p01n02i01721ent IS
+
+  -- Global signals.
+  SIGNAL B   : BIT := '1';
+
+BEGIN
+  -- If one driver created, it will take on the indicated value.
+  TESTING: PROCESS
+  BEGIN
+    B <= '0' after 10 ns;
+    B <= '1' after 10 ns;
+    B <= '0' after 10 ns;
+    wait on B;
+    assert NOT( B='0' ) 
+      report "***PASSED TEST: c12s06b01x00p01n02i01721"
+      severity NOTE;
+    assert ( B='0' ) 
+      report "***FAILED TEST: c12s06b01x00p01n02i01721 - At least one driver gets created for eah signal which is assigned to either directly or indirectly inside of a process."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p01n02i01721arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1723.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1723.vhd
new file mode 100644
index 0000000..fa05621
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1723.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1723.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p03n01i01723ent IS
+END c12s06b01x00p03n01i01723ent;
+
+ARCHITECTURE c12s06b01x00p03n01i01723arch OF c12s06b01x00p03n01i01723ent IS
+  signal k : bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= '1';
+    wait for 1 ns;
+    assert NOT(k = '1') 
+      report "***PASSED TEST: c12s06b01x00p03n01i01723" 
+      severity NOTE;
+    assert (k = '1') 
+      report "***FAILED TEST: c12s06b01x00p03n01i01723 - A driver contains at least one transaction. This should be OK."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p03n01i01723arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1724.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1724.vhd
new file mode 100644
index 0000000..626bbac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1724.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1724.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p03n02i01724ent IS
+END c12s06b01x00p03n02i01724ent;
+
+ARCHITECTURE c12s06b01x00p03n02i01724arch OF c12s06b01x00p03n02i01724ent IS
+  type    SWITCH_LEVEL is ( 'X', '0', '1' );
+  subtype    LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+
+  -- Global signals.
+  SIGNAL B   : LOGIC_SWITCH := '1';
+  SIGNAL B2  : LOGIC_SWITCH;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( (B='1') and (B2='0') )
+      report "***PASSED TEST: c12s06b01x00p03n02i01724"
+      severity NOTE;
+    assert ( (B='1') and (B2='0') )
+      report "***FAILED TEST: c12s06b01x00p03n02i01724 - The initial contents of a driver associated with a given signal is defined by the default value associated with the signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p03n02i01724arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1727.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1727.vhd
new file mode 100644
index 0000000..0945620
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1727.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1727.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p04n03i01727ent IS
+END c12s06b01x00p04n03i01727ent;
+
+ARCHITECTURE c12s06b01x00p04n03i01727arch OF c12s06b01x00p04n03i01727ent IS
+  signal   B : BIT := '1';
+BEGIN
+  TESTING: PROCESS
+    variable ShouldBeTime : TIME; 
+  BEGIN
+    B <= '1','0' after 10 ns;
+    ShouldBeTime := NOW + 10 ns;
+    wait on B;
+    assert NOT(( NOW = ShouldBeTime ) and ( B = '0' ))
+      report "***PASSED TEST: c12s06b01x00p04n03i01727"
+      severity NOTE;
+    assert (( NOW = ShouldBeTime ) and ( B = '0' ))
+      report "***FAILED TEST: c12s06b01x00p04n03i01727 - As time passes, the current transaction is deleted from the projected output waveform of that driver and the new tra nsaction takes its place."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p04n03i01727arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1728.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1728.vhd
new file mode 100644
index 0000000..0d3e39c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1728.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1728.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s03b00x00p02n01i01728ent IS
+END c09s03b00x00p02n01i01728ent;
+
+ARCHITECTURE c09s03b00x00p02n01i01728arch OF c09s03b00x00p02n01i01728ent IS
+
+  procedure check (x: in integer; y: in boolean) is
+  begin
+    assert NOT( x=3 and y=true )
+      report "***PASSED TEST: c09s03b00x00p02n01i01728"
+      severity NOTE;
+    assert ( x=3 and y=true )
+      report "***FAILED TEST: c09s03b00x00p02n01i01728 - Procedure call statement syntax diagram did not pass."
+      severity ERROR;
+  end;
+
+  signal p: integer := 3;
+  signal q: boolean := true;
+
+BEGIN
+
+  check (p,q);    -- No_failure_here
+
+END c09s03b00x00p02n01i01728arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1729.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1729.vhd
new file mode 100644
index 0000000..f37a21f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1729.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1729.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s03b00x00p02n01i01729ent IS
+END c09s03b00x00p02n01i01729ent;
+
+ARCHITECTURE c09s03b00x00p02n01i01729arch OF c09s03b00x00p02n01i01729ent IS
+
+  procedure check (x: in integer; y: in boolean) is
+  begin
+    assert NOT( x=3 and y=true )
+      report "***PASSED TEST: c09s03b00x00p02n01i01729"
+      severity NOTE;
+    assert ( x=3 and y=true )
+      report "***FAILED TEST: c09s03b00x00p02n01i01729 - A label can be used before a procedure call statement."
+      severity ERROR;
+  end;
+
+  signal p: integer := 3;
+  signal q: boolean := true;
+
+BEGIN
+
+  L1 :   check (p,q);    -- No_failure_here
+
+END c09s03b00x00p02n01i01729arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc173.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc173.vhd
new file mode 100644
index 0000000..9bf2221
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc173.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc173.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n02i00173ent IS
+END c04s03b03x01p03n02i00173ent;
+
+ARCHITECTURE c04s03b03x01p03n02i00173arch OF c04s03b03x01p03n02i00173ent IS
+  signal    Addr : bit;
+  alias    SIGN : bit is Addr;  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Addr <= '1' after 10 ns;
+    wait for 10 ns;
+    assert NOT( SIGN = '1' )
+      report "***PASSED TEST: c04s03b03x01p03n02i00173"
+      severity NOTE;
+    assert ( SIGN = '1' )
+      report "***FAILED TEST: c04s03b03x01p03n02i00173 - The base type of the name being defined by the declaration is the same as the base type of the subtype indication test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n02i00173arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1732.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1732.vhd
new file mode 100644
index 0000000..4ee5378
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1732.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1732.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s03b00x00p14n01i01732ent IS
+END c09s03b00x00p14n01i01732ent;
+
+ARCHITECTURE c09s03b00x00p14n01i01732arch OF c09s03b00x00p14n01i01732ent IS
+  signal    s1 : bit;
+  signal    s2 : integer;
+  signal    s3 : integer;
+
+  procedure unguarded_proc (where : in integer; signal here : out integer) is
+  begin
+    if where = 1 then
+      here <= 5;
+    else
+      here <= 6;
+    end if;
+  end;
+
+BEGIN
+  s3   <= 1 after 20 ns;
+
+  block_label1 : BLOCK ( s1 = '1' )
+  begin
+    unguarded_proc (s3,s2);
+  end block block_label1;
+
+  TESTING: PROCESS(s2)
+  BEGIN
+    if (now > 1 ns) then
+      assert NOT( s2=5 )
+        report "***PASSED TEST: c09s03b00x00p14n01i01732"
+        severity NOTE;
+      assert ( s2=5 )
+        report "***FAILED TEST: c09s03b00x00p14n01i01732 - The value of an implicitly declared signal GUARD has no effect on evaluation of a concurrent procedure call."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s03b00x00p14n01i01732arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1733.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1733.vhd
new file mode 100644
index 0000000..c45979a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1733.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1733.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s03b00x00p14n01i01733ent IS
+END c09s03b00x00p14n01i01733ent;
+
+ARCHITECTURE c09s03b00x00p14n01i01733arch OF c09s03b00x00p14n01i01733ent IS
+  signal    s1 : bit;
+  signal    s2 : integer;
+
+  procedure guarded_proc (signal guard_signal : in boolean; where : in integer; signal here : out integer) is
+  begin
+    if (where = 1) and (guard_signal = true) then
+      here <= 5;
+    else
+      here <= 6;
+    end if;
+  end;
+
+BEGIN
+  s1   <= '1' after 45 ns;
+
+  block_label1 : BLOCK ( s1 = '1' )
+  begin
+    guarded_proc (GUARD,1,s2);
+  end block block_label1;
+
+  TESTING: PROCESS(s2)
+  BEGIN
+    if (now > 1 ns) then
+      assert NOT(s2 = 5)
+        report "***PASSED TEST: c09s03b00x00p14n01i01733"
+        severity NOTE;
+      assert (s2 = 5)
+        report "***FAILED TEST: c09s03b00x00p14n01i01733 - If the value of an implicitly declared signal GUARD is explicitly referenced in the actual parameter part of the concurrent proccedure call, then it has effect on evaluation of a concurrent procedure call."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s03b00x00p14n01i01733arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1734.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1734.vhd
new file mode 100644
index 0000000..2579ad5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1734.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1734.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s04b00x00p02n01i01734ent IS
+begin
+  l1: assert false
+    report "Labeled concurrent assert OK in entity."
+    severity note ;
+  assert false
+    report "Unlabeled concurrent assert OK in entity."
+    severity note ;
+END c09s04b00x00p02n01i01734ent;
+
+ARCHITECTURE c09s04b00x00p02n01i01734arch OF c09s04b00x00p02n01i01734ent IS
+
+BEGIN
+  l2: assert false
+    report "Labeled concurrent assert OK in architecture."
+    severity note ;
+  assert false
+    report "Unlabeled concurrent assert OK in architecture."
+    severity note ;
+
+  B : block
+  BEGIN
+    l1: assert false
+      report "Labeled concurrent assert OK in block."
+      severity note ;
+    assert false
+      report "Unlabeled concurrent assert OK in block."
+      severity note ;
+
+    assert FALSE 
+      report "***PASSED TEST: c09s04b00x00p02n01i01734 - This test is passed if and only if we get other six assertion sentence."
+      severity NOTE;
+  end block B;
+
+END c09s04b00x00p02n01i01734arch;
+
+
+
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1735.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1735.vhd
new file mode 100644
index 0000000..24214d8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1735.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1735.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s04b00x00p06n01i01735ent IS
+END c09s04b00x00p06n01i01735ent;
+
+ARCHITECTURE c09s04b00x00p06n01i01735arch OF c09s04b00x00p06n01i01735ent IS
+  signal arch_s1 : bit;
+  signal arch_s2 : boolean;
+  signal arch_s3 : character;
+  signal arch_s4 : severity_level;
+  signal arch_s5 : integer;
+  signal arch_s6 : real;
+  signal arch_s7 : time;
+  signal arch_s8 : positive;
+  signal arch_s9 : natural;
+BEGIN
+  ASSERT arch_s1 /= bit'left 
+    REPORT "bit concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s2 /= boolean'left 
+    REPORT "boolean concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s3 /= character'left 
+    REPORT "character concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s4 /= severity_level'left 
+    REPORT "severity_level concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s5 /= integer'left 
+    REPORT "integer concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s6 /= real'left 
+    REPORT "real concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s7 /= time'left 
+    REPORT "time concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s8 /= positive'left 
+    REPORT "positive concurrent assertion" 
+    severity NOTE;
+  ASSERT arch_s9 /= natural'left 
+    REPORT "natural concurrent assertion" 
+    severity NOTE;
+  TESTING: PROCESS
+  BEGIN
+    ASSERT arch_s1 /= bit'left 
+      REPORT "bit concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s2 /= boolean'left 
+      REPORT "boolean concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s3 /= character'left 
+      REPORT "character concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s4 /= severity_level'left 
+      REPORT "severity_level concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s5 /= integer'left 
+      REPORT "integer concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s6 /= real'left 
+      REPORT "real concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s7 /= time'left 
+      REPORT "time concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s8 /= positive'left 
+      REPORT "positive concurrent assertion" 
+      severity NOTE;
+    ASSERT arch_s9 /= natural'left 
+      REPORT "natural concurrent assertion" 
+      severity NOTE;
+    assert FALSE 
+      report "***PASSED TEST: c09s04b00x00p06n01i01735 - This need manual check - The concurrent assertion statement and the sequential assertion should print out the same ASSERTION NOTES."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s04b00x00p06n01i01735arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1736.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1736.vhd
new file mode 100644
index 0000000..b759bd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1736.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1736.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s04b00x00p08n01i01736ent IS
+END c09s04b00x00p08n01i01736ent;
+
+ARCHITECTURE c09s04b00x00p08n01i01736arch OF c09s04b00x00p08n01i01736ent IS
+
+BEGIN
+  assert FALSE 
+    report "***PASSED TEST: c09s04b00x00p08n01i01736 - This test need manual check. No other assertion note should appear."
+    severity NOTE;
+  assert TRUE 
+    report "***FAILED TEST: c09s04b00x00p08n01i01736 - Only when the assertion is false, then the specified message will be sent to the simulation report."
+    severity ERROR;
+
+END c09s04b00x00p08n01i01736arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1739.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1739.vhd
new file mode 100644
index 0000000..2da9b79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1739.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1739.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s04b00x00p10n01i01739ent IS
+begin
+  assert false 
+    report "Success:entity assertion with static expression" 
+    severity NOTE;
+END c09s04b00x00p10n01i01739ent;
+
+ARCHITECTURE c09s04b00x00p10n01i01739arch OF c09s04b00x00p10n01i01739ent IS
+
+BEGIN
+  assert false 
+    report "Success:architecture assertion with static expression" 
+    severity NOTE;
+
+  b: block
+  begin
+    assert false 
+      report "Success:architecture in block: assertion with static expression" 
+      severity NOTE;
+  end block b;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s04b00x00p10n01i01739 - This test need manual check, three assertion notes of Success should appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s04b00x00p10n01i01739arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1744.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1744.vhd
new file mode 100644
index 0000000..7d26a88
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1744.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1744.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p03n01i01744ent IS
+  port   (parallel_in    : bit_vector (7 downto 0);
+          clock      : bit;
+          serial_out   : out bit);
+END c09s05b00x00p03n01i01744ent;
+
+ARCHITECTURE c09s05b00x00p03n01i01744arch OF c09s05b00x00p03n01i01744ent IS
+  constant    bit_time    : time    := 1 ns;
+  signal       GUARD      : boolean:= TRUE;
+BEGIN
+  serial_out <= guarded transport    -- No_failure_here
+                parallel_in(7) after 1*bit_time,
+                parallel_in(6) after 2*bit_time,
+                parallel_in(5) after 3*bit_time,
+                parallel_in(4) after 4*bit_time,
+                parallel_in(3) after 5*bit_time,
+                parallel_in(2) after 6*bit_time,
+                parallel_in(1) after 7*bit_time,
+                parallel_in(0) after 8*bit_time,
+                '0' after 9*bit_time;
+  PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s05b00x00p03n01i01744" 
+      severity NOTE;
+    wait;
+  END PROCESS;
+
+END c09s05b00x00p03n01i01744arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1745.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1745.vhd
new file mode 100644
index 0000000..9768509
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1745.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1745.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p05n03i01745ent IS
+END c09s05b00x00p05n03i01745ent;
+
+ARCHITECTURE c09s05b00x00p05n03i01745arch OF c09s05b00x00p05n03i01745ent IS
+  signal   A    : bit    := '0';
+BEGIN
+  A   <= transport '1' after 10 ns;
+  TESTING: PROCESS(A)
+    variable NEWTIME : TIME;
+  BEGIN
+    NEWTIME := now;
+    if ( now > 1 ns ) then
+      assert NOT( A= '1' and NEWTIME = 10 ns )
+        report "***PASSED TEST: c09s05b00x00p05n03i01745"
+        severity NOTE;
+      assert ( A= '1' and NEWTIME = 10 ns )
+        report "***FAILED TEST: c09s05b00x00p05n03i01745 - Transport specifies the transport delay."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s05b00x00p05n03i01745arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1747.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1747.vhd
new file mode 100644
index 0000000..91a4913
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1747.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1747.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p12n02i01747ent IS
+  function resolve_bit ( inputs : bit_vector) return bit is
+    VARIABLE val : bit := '0';
+  begin
+    if inputs'length = 0 then
+      return val;
+    else
+      for i in inputs'range LOOP
+        if inputs(i) = '1' then return '1'; end if;
+      END LOOP;
+      return '0';
+    end if;
+  end resolve_bit;
+END c09s05b00x00p12n02i01747ent;
+
+ARCHITECTURE c09s05b00x00p12n02i01747arch OF c09s05b00x00p12n02i01747ent IS
+  signal      a      : resolve_bit bit BUS;
+  signal    b      : resolve_bit bit BUS;
+  signal    grd    : boolean;
+
+BEGIN
+  grd <=    TRUE    after 10 ns,
+            FALSE   after 20 ns; 
+
+  block_label : BLOCK (grd)
+  begin
+    b <= guarded '1' after 1 ns;
+  end block block_label;
+
+  block_label_1 : BLOCK (grd)
+  begin
+    TESTING: PROCESS
+    BEGIN
+      if GUARD then
+        a <= '1' after 1 ns;
+      else
+        a <= NULL;
+      end if;
+      wait on GUARD, a;
+    END PROCESS TESTING;
+  end block block_label_1;
+  
+  process(a,b)
+    variable f1, f2 : integer := 0;
+  begin
+    if    (now = 11 ns) and (a=b) then
+      f1 := 1;
+    end if;
+    if    (now = 20 ns) and (a=b) then
+      f2 := 1;
+    end if;
+    if (now = 20 ns) then   
+      assert NOT((f1=1) and (f2=1)) 
+        report "***PASSED TEST: c09s05b00x00p12n02i01747"
+        severity NOTE;
+      assert ((f1=1) and (f2=1)) 
+        report "***FAILED TEST: c09s05b00x00p12n02i01747 - The concurrent guarded signal assignment statement has an equivalent process statement."
+        severity ERROR;
+    end if;
+  end process;
+
+END c09s05b00x00p12n02i01747arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1748.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1748.vhd
new file mode 100644
index 0000000..bc9624f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1748.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1748.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p16n01i01748ent IS
+END c09s05b00x00p16n01i01748ent;
+
+ARCHITECTURE c09s05b00x00p16n01i01748arch OF c09s05b00x00p16n01i01748ent IS
+  signal gate_1    : BIT;
+  signal gate_2    : BIT;
+  signal data_in    : BIT;
+  signal data_pass    : BIT;
+  signal data_latch    : BIT;
+BEGIN
+
+  gate_1    <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
+  gate_2    <= gate_1 after 1 ns;
+  data_in    <=    '1' after  5 ns, '0' after 25 ns,
+                   '1' after 35 ns, '0' after 36 ns,
+                   '1' after 37 ns, '0' after 38 ns,
+                   '1' after 39 ns, '0' after 40 ns,
+                   '1' after 41 ns, '0' after 42 ns;
+
+  B: block ((gate_1 and gate_2) = '1')
+  begin
+    data_pass    <=       data_in;
+    data_latch    <= guarded    data_in;
+  end block;
+
+  TESTING: PROCESS(data_pass,data_latch)
+    variable ok : integer := 1;
+  BEGIN
+    if (now = 5 ns) then
+      if not(data_pass'event and data_pass = '1' and data_latch'quiet and data_latch = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 11 ns) then
+      if not(data_latch'event and data_latch = '1' and data_pass'quiet and data_pass = '1') then
+        ok := 0;
+      end if;
+    elsif (now = 25 ns) then
+      if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 31 ns) then
+      if not(data_latch'event and data_latch = '0' and data_pass'quiet and data_pass = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 35 ns) then
+      if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then
+        ok := 0;
+      end if;
+    elsif (now = 36 ns) then
+      if not(data_latch'event and data_latch = '0' and data_pass'event and data_pass = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 37 ns) then
+      if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then
+        ok := 0;
+      end if;
+    elsif (now = 38 ns) then
+      if not(data_latch'event and data_latch = '0' and data_pass'event and data_pass = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 39 ns) then
+      if not(data_latch'event and data_latch = '1' and data_pass'event and data_pass = '1') then
+        ok := 0;
+      end if;
+    elsif (now = 40 ns) then
+      if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '0') then
+        ok := 0;
+      end if;
+    elsif (now = 41 ns) then
+      if not(data_latch'quiet and data_latch = '1' and data_pass'event and data_pass = '1') then
+        ok := 0;
+      end if;
+    end if;
+
+    if (now > 41 ns) then   
+      assert NOT( ok=1 )
+        report "***PASSED TEST: c09s05b00x00p16n01i01748"
+        severity NOTE;
+      assert ( ok=1 )
+        report "***FAILED TEST: c09s05b00x00p16n01i01748 - Concurrent signal assignment test failed."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s05b00x00p16n01i01748arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1753.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1753.vhd
new file mode 100644
index 0000000..da754bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1753.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1753.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p25n01i01753ent IS
+END c09s05b00x00p25n01i01753ent;
+
+ARCHITECTURE c09s05b00x00p25n01i01753arch OF c09s05b00x00p25n01i01753ent IS
+  type byte is array (positive range <>) of bit;
+
+  function F (constant S: byte) return bit is
+  begin
+    return '0';
+  end;
+
+  constant    N    : integer := 4;
+  signal       UG,I   : bit_vector(1 to 4);
+  signal       GS, UGS   : bit;
+  signal       UGT   : F bit register;
+BEGIN
+  A: (I(1), I(2), I(3), I(N)) <= transport UG(1 to N) after 20 ns;  -- No_failure_here
+  
+  GS   <=   '1' after 10 ns; 
+  B:block (GS = '1')
+  begin
+    C: UGT <= guarded UGS after 10 ns;  -- No_failure_here
+  end block;
+  TESTING: PROCESS(I,UGT)
+  BEGIN
+    assert NOT(I="0000" and UGT='0')  
+      report "***PASSED TEST: c09s05b00x00p25n01i01753" 
+      severity NOTE;
+    assert (I="0000" and UGT='0')  
+      report "***FAILED TEST: c09s05b00x00p25n01i01753 - An aggregate target in a concurrent signal assignment statement contains only locally static names, and no two signal names identify the same object, or subelement thereof." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s05b00x00p25n01i01753arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1756.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1756.vhd
new file mode 100644
index 0000000..2a60eda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1756.vhd
@@ -0,0 +1,128 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1756.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b01x00p01n01i01756ent IS
+END c09s05b01x00p01n01i01756ent;
+
+ARCHITECTURE c09s05b01x00p01n01i01756arch OF c09s05b01x00p01n01i01756ent IS
+  type   t_wlogic  is (U, D, Z0, Z1, ZDX, DZX, ZX);
+  signal count : integer ;
+  signal ECLK  : t_wlogic;
+  signal ECLK2 : t_wlogic;
+  signal ECL   : integer := 1;
+BEGIN
+  count <=    0 after  0 ns,
+              1 after 10 ns,
+              2 after 20 ns,
+              3 after 30 ns,
+              4 after 40 ns,
+              5 after 50 ns,
+              6 after 60 ns;
+  ----------------------------------------------------------------------
+  ECLK <=  U   after 1 ns WHEN count=0 ELSE
+           D   after 1 ns WHEN count=1 ELSE
+           Z0  after 1 ns WHEN count=2 ELSE
+           Z1  after 1 ns WHEN count=3 ELSE
+           ZDX after 1 ns WHEN count=4 ELSE
+           DZX after 1 ns WHEN count=5 ELSE
+           ZX  after 1 ns ;
+  TESTING: PROCESS(count)
+  BEGIN
+    if   count = 0 then
+      ECLK2 <= U   after 1 ns;
+    elsif   count = 1 then
+      ECLK2 <= D   after 1 ns;
+    elsif   count = 2 then
+      ECLK2 <= Z0  after 1 ns;
+    elsif   count = 3 then
+      ECLK2 <= Z1  after 1 ns;
+    elsif   count = 4 then
+      ECLK2 <= ZDX after 1 ns;
+    elsif   count = 5 then
+      ECLK2 <= DZX after 1 ns;
+    else
+      ECLK2 <= ZX  after 1 ns;
+    end if;   
+  END PROCESS TESTING;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if       now =  0 ns then
+      NULL;
+    elsif   (now =  1 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 11 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 21 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 31 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 41 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 51 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 61 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    end if;
+  END PROCESS;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if      (now > 60 ns) and (ECL = 1) then
+      assert FALSE
+        report "***PASSED TEST: c09s05b01x00p01n01i01756"
+        severity NOTE;
+    elsif   (now > 60 ns) and (ECL = 0) then
+      assert FALSE
+        report "***FAILED TEST: c09s05b01x00p01n01i01756 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
+        severity ERROR;
+    end if;
+  END PROCESS;
+
+END c09s05b01x00p01n01i01756arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1757.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1757.vhd
new file mode 100644
index 0000000..18b7cf7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1757.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1757.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b01x00p01n01i01757ent IS
+END c09s05b01x00p01n01i01757ent;
+
+ARCHITECTURE c09s05b01x00p01n01i01757arch OF c09s05b01x00p01n01i01757ent IS
+  type   t_wlogic  is (U, D, Z0, Z1, ZDX, DZX, ZX);
+  signal count : integer ;
+  signal ECLK  : t_wlogic;
+  signal ECLK2 : t_wlogic;
+  signal ECL   : integer := 1;
+BEGIN
+  count <=    0 after  0 ns,
+              1 after 10 ns,
+              2 after 20 ns,
+              3 after 30 ns,
+              4 after 40 ns,
+              5 after 50 ns,
+              6 after 60 ns;
+  ----------------------------------------------------------------------
+  ECLK <= transport 
+          U   after 1 ns WHEN count=0 ELSE
+          D   after 1 ns WHEN count=1 ELSE
+          Z0  after 1 ns WHEN count=2 ELSE
+          Z1  after 1 ns WHEN count=3 ELSE
+          ZDX after 1 ns WHEN count=4 ELSE
+          DZX after 1 ns WHEN count=5 ELSE
+          ZX  after 1 ns ;
+  TESTING: PROCESS(count)
+  BEGIN
+    if   count = 0 then
+      ECLK2 <= transport U   after 1 ns;
+    elsif   count = 1 then
+      ECLK2 <= transport D   after 1 ns;
+    elsif   count = 2 then
+      ECLK2 <= transport Z0  after 1 ns;
+    elsif   count = 3 then
+      ECLK2 <= transport Z1  after 1 ns;
+    elsif   count = 4 then
+      ECLK2 <= transport ZDX after 1 ns;
+    elsif   count = 5 then
+      ECLK2 <= transport DZX after 1 ns;
+    else
+      ECLK2 <= transport ZX  after 1 ns;
+    end if;   
+  END PROCESS TESTING;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if       now =  0 ns then
+      NULL;
+    elsif   (now =  1 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 11 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 21 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 31 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 41 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 51 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 61 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST"
+        severity ERROR;
+      ECL <= 0;
+    end if;
+  END PROCESS;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if      (now > 60 ns) and (ECL = 1) then
+      assert FALSE
+        report "***PASSED TEST: c09s05b01x00p01n01i01757"
+        severity NOTE;
+    elsif   (now > 60 ns) and (ECL = 0) then
+      assert FALSE
+        report "***FAILED TEST: c09s05b01x00p01n01i01757 - The conditional signal assignment represents a process statement in which the signal transform is an if statement."
+        severity ERROR;
+    end if;
+  END PROCESS;
+
+END c09s05b01x00p01n01i01757arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc176.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc176.vhd
new file mode 100644
index 0000000..f7f746b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc176.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc176.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n02i00176ent IS
+END c04s03b03x01p03n02i00176ent;
+
+ARCHITECTURE c04s03b03x01p03n02i00176arch OF c04s03b03x01p03n02i00176ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable REAL_NUMBER: BIT_VECTOR(0 to 31);
+    alias    SIGN:        bit          is REAL_NUMBER(0);
+    alias    MANTISSA:    BIT_VECTOR(23 downto 0)    is REAL_NUMBER(8 to 31);
+    alias    EXPONENT:    BIT_VECTOR(1 to 7)    is REAL_NUMBER(1 to 7);
+  BEGIN
+    REAL_NUMBER := "00011011000110111110010011100100";
+    wait for 10 ns;
+    assert NOT(   SIGN   = '0'         and
+                  MANTISSA= "000110111110010011100100"and
+                  EXPONENT= "0011011"   )
+      report "***PASSED TEST:c04s03b03x01p03n02i00176" 
+      severity NOTE;
+    assert (   SIGN   = '0'         and
+               MANTISSA= "000110111110010011100100"and
+               EXPONENT= "0011011"   )
+      report "***FAILED TEST: c04s03b03x01p03n02i00176 - A single dimensional array test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n02i00176arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1761.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1761.vhd
new file mode 100644
index 0000000..7d679bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1761.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1761.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b01x00p21n01i01761ent IS
+END c09s05b01x00p21n01i01761ent;
+
+ARCHITECTURE c09s05b01x00p21n01i01761arch OF c09s05b01x00p21n01i01761ent IS
+  signal TS1,TS2   : integer;
+  signal B,C   : integer;
+  signal D,E,F   : bit;
+BEGIN
+  TS1 <= transport 1 after 10 ns when B = C else
+         2 after 10 ns when B > C else
+         3 after 10 ns;
+
+  TS2 <= transport 4-1 after 10 ns when D = '1' else
+         5+1 after 10 ns when E = '1' else
+         6*2 after 10 ns when F = '1' else
+         8/2 after 10 ns;
+
+  TESTING: PROCESS(TS1,TS2)
+  BEGIN
+    if ( now > 1 ns) then
+      assert NOT(TS1=1 and TS2=4) 
+        report "***PASSED TEST: c09s05b01x00p21n01i01761" 
+        severity NOTE;
+      assert (TS1=1 and TS2=4) 
+        report "***FAILED TEST: c09s05b01x00p21n01i01761 - Conditions in the conditional signal assignment statement should be valid." 
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s05b01x00p21n01i01761arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1762.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1762.vhd
new file mode 100644
index 0000000..f9c2248
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1762.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1762.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p01n01i01762ent IS
+END c09s05b02x00p01n01i01762ent;
+
+ARCHITECTURE c09s05b02x00p01n01i01762arch OF c09s05b02x00p01n01i01762ent IS
+  type   t_wlogic  is (U, D, Z0, Z1, ZDX, DZX, ZX);
+  signal count : integer ;
+  signal ECLK  : t_wlogic;
+  signal ECLK2 : t_wlogic;
+  signal ECL   : integer := 1;
+BEGIN
+  count <=    0 after  0 ns,
+              1 after 10 ns,
+              2 after 20 ns,
+              3 after 30 ns,
+              4 after 40 ns,
+              5 after 50 ns,
+              6 after 60 ns;
+  ----------------------------------------------------------------------
+  WITH count SELECT
+    ECLK <=  U   after 1 ns WHEN 0,
+    D   after 1 ns WHEN 1,
+    Z0  after 1 ns WHEN 2,
+    Z1  after 1 ns WHEN 3,
+    ZDX after 1 ns WHEN 4,
+    DZX after 1 ns WHEN 5,
+    ZX  after 1 ns WHEN OTHERS;
+  TESTING: PROCESS(count)
+  BEGIN
+    case count is
+      WHEN 0      => ECLK2 <= U   after 1 ns;
+      WHEN 1      => ECLK2 <= D   after 1 ns;
+      WHEN 2      => ECLK2 <= Z0  after 1 ns;
+      WHEN 3      => ECLK2 <= Z1  after 1 ns;
+      WHEN 4      => ECLK2 <= ZDX after 1 ns;
+      WHEN 5      => ECLK2 <= DZX after 1 ns;
+      WHEN OTHERS   => ECLK2 <= ZX  after 1 ns;
+    end case;
+  END PROCESS TESTING;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if    now =  0 ns then
+      NULL;
+    elsif   (now =  1 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 11 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif    (now = 21 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 31 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 41 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 51 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 61 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    end if;
+  END PROCESS;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if    (now > 60 ns) and (ECL = 1) then
+      assert FALSE 
+        report "***PASSED TEST: c09s05b02x00p01n01i01762"
+        severity NOTE;
+    elsif   (now > 60 ns) and (ECL = 0) then
+      assert FALSE 
+        report "***FAILED TEST: c09s05b02x00p01n01i01762 - The selected signal assignment represents a process statement in which the signal transform is a case statement."
+        severity ERROR;
+    end if;
+  END PROCESS;
+
+END c09s05b02x00p01n01i01762arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1763.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1763.vhd
new file mode 100644
index 0000000..bebd842
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1763.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1763.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p01n01i01763ent IS
+END c09s05b02x00p01n01i01763ent;
+
+ARCHITECTURE c09s05b02x00p01n01i01763arch OF c09s05b02x00p01n01i01763ent IS
+  type   t_wlogic  is (U, D, Z0, Z1, ZDX, DZX, ZX);
+  signal count : integer ;
+  signal ECLK  : t_wlogic;
+  signal ECLK2 : t_wlogic;
+  signal ECL   : integer := 1;
+BEGIN
+  count <=    0 after  0 ns,   
+              1 after 10 ns,
+              2 after 20 ns,
+              3 after 30 ns,
+              4 after 40 ns,
+              5 after 50 ns,
+              6 after 60 ns;
+  ----------------------------------------------------------------------
+  WITH count SELECT
+    ECLK <=    transport 
+    U   after 1 ns WHEN 0,
+    D   after 1 ns WHEN 1,
+    Z0  after 1 ns WHEN 2,
+    Z1  after 1 ns WHEN 3,
+    ZDX after 1 ns WHEN 4,
+    DZX after 1 ns WHEN 5,
+    ZX  after 1 ns WHEN OTHERS;
+  TESTING: PROCESS(count)
+  BEGIN
+    case count is
+      WHEN 0      => ECLK2 <= transport U   after 1 ns;
+      WHEN 1      => ECLK2 <= transport D   after 1 ns;
+      WHEN 2      => ECLK2 <= transport Z0  after 1 ns;
+      WHEN 3      => ECLK2 <= transport Z1  after 1 ns;
+      WHEN 4      => ECLK2 <= transport ZDX after 1 ns;
+      WHEN 5      => ECLK2 <= transport DZX after 1 ns;
+      WHEN OTHERS   => ECLK2 <= transport ZX  after 1 ns;
+    end case;
+  END PROCESS TESTING;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if    now =  0 ns then
+      NULL;
+    elsif   (now =  1 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 11 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif    (now = 21 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 31 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 41 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 51 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    elsif   (now = 61 ns) and (ECLK /= ECLK2) then
+      assert FALSE
+        report "FAILED TEST" 
+        severity ERROR;
+      ECL <= 0;
+    end if;
+  END PROCESS;
+  PROCESS(ECLK,ECLK2)
+  BEGIN
+    if    (now > 60 ns) and (ECL = 1) then
+      assert FALSE 
+        report "***PASSED TEST: c09s05b02x00p01n01i01763"
+        severity NOTE;
+    elsif   (now > 60 ns) and (ECL = 0) then
+      assert FALSE 
+        report "***FAILED TEST: c09s05b02x00p01n01i01763 - The transport selected signal assignment represents a process statement in which the signal transform is a case statement."
+        severity ERROR;
+    end if;
+  END PROCESS;
+
+END c09s05b02x00p01n01i01763arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1766.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1766.vhd
new file mode 100644
index 0000000..af96b37
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1766.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1766.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p02n01i01766ent IS
+END c09s05b02x00p02n01i01766ent;
+
+ARCHITECTURE c09s05b02x00p02n01i01766arch OF c09s05b02x00p02n01i01766ent IS
+  signal   i,j   : integer := 1;
+BEGIN
+
+  with i select                        -- No_failure_here
+            j <= transport 1 when 1,
+                 2 when 2,
+                 3 when others;
+  TESTING: PROCESS(j)
+  BEGIN
+    assert NOT(j = 1) 
+      report "***PASSED TEST: c09s05b02x00p02n01i01766"
+      severity NOTE;
+    assert (j = 1) 
+      report "***FAILED TEST: c09s05b02x00p02n01i01766 - In the selected signal assignment, the reserved word with must be followed by an expression and the reserved word select." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s05b02x00p02n01i01766arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1775.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1775.vhd
new file mode 100644
index 0000000..280e424
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1775.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1775.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01775ent IS
+END c09s05b02x00p11n01i01775ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01775arch OF c09s05b02x00p11n01i01775ent IS
+  signal i : integer := 21;
+  signal j : boolean ;
+BEGIN
+
+  with i select
+    j <= transport
+    TRUE  when 1  to 19,  -- No_failure_here
+                              -- Valid expression for a choice
+    FALSE when 20 to 29,
+    TRUE  when 30 to 49,
+    FALSE when others;
+
+  TESTING: PROCESS(j)
+  BEGIN
+    assert NOT(j = FALSE) 
+      report "***PASSED TEST: c09s05b02x00p11n01i01775" 
+      severity NOTE;
+    assert (j = FALSE) 
+      report "***FAILED TEST: c09s05b02x00p11n01i01775 - Each value of the type of the select expression should be represented once and exactly once." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01775arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1776.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1776.vhd
new file mode 100644
index 0000000..d031c04
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1776.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1776.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01776ent IS
+END c09s05b02x00p11n01i01776ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01776arch OF c09s05b02x00p11n01i01776ent IS
+  SUBTYPE string_30 is STRING(1 to 30);
+  SUBTYPE string_4  is STRING(1 to 4);
+  CONSTANT    str    : string_30 := "1234567890abcdefghijlkmnopqrst";
+  SIGNAL    s    : bit;
+BEGIN
+
+  -- test point
+  with string_4'(str(1 to 4)) select
+    s <=    '1' after 10 ns when "1234",
+    '0' after 10 ns when OTHERS;
+
+  TESTING : PROCESS(s)
+  BEGIN
+    if (now = 10 ns) then
+      assert NOT(s='1') 
+        report "***PASSED TEST: c09s05b02x00p11n01i01776" 
+        severity NOTE;
+      assert (s='1')
+        report "***FAILED TEST: c09s05b02x00p11n01i01776 - Qualified expression used as the expression in a selected signal assignment fialed." 
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01776arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1781.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1781.vhd
new file mode 100644
index 0000000..9f37834
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1781.vhd
@@ -0,0 +1,140 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1781.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c09s06b00x00p04n05i01781pkg is
+  type info is record
+                 field_1 : integer;
+                 field_2 : real;
+               end record;
+  type stuff is array (Integer range 1 to 2) of info;
+end c09s06b00x00p04n05i01781pkg;
+
+use work.c09s06b00x00p04n05i01781pkg.all;
+entity c09s06b00x00p04n05i01781ent_a is
+  generic (
+    g0  :   Boolean        ;
+    g1  :   Bit            ;
+    g2  :   Character      ;
+    g3  :   SEVERITY_LEVEL ;
+    g4  :   Integer        ;
+    g5  :   Real           ;
+    g6  :   TIME           ;
+    g7  :   Natural        ;
+    g8  :   Positive       ;
+    g9  :   String         ;
+    gA  :   Bit_vector     ;
+    gB  :   stuff
+    );
+end c09s06b00x00p04n05i01781ent_a;
+
+use work.c09s06b00x00p04n05i01781pkg.all;
+architecture c09s06b00x00p04n05i01781arch_a of c09s06b00x00p04n05i01781ent_a is
+  -- Check that the data was passed...
+begin
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   g0 = True                   and 
+                  g1 = '0'                      and  
+                  g2 = '@'                      and 
+                  g3 = NOTE                     and 
+                  g4 = 123456789                and 
+                  g5 = 987654321.5              and 
+                  g6 = 110  ns                   and 
+                  g7 = 12312                    and 
+                  g8 = 3423                     and 
+                  g9 = "16 characters OK"       and 
+                  gA = B"01010010100101010010101001010100"and 
+                  gB = ((123, 456.7 ), (890, 135.7))) 
+      report "***PASSED TEST: c09s06b00x00p04n05i01781"
+      severity NOTE;
+    assert (   g0 = True                   and 
+               g1 = '0'                      and  
+               g2 = '@'                      and 
+               g3 = NOTE                     and 
+               g4 = 123456789                and 
+               g5 = 987654321.5              and 
+               g6 = 110  ns                   and 
+               g7 = 12312                    and 
+               g8 = 3423                     and 
+               g9 = "16 characters OK"       and 
+               gA = B"01010010100101010010101001010100"and 
+               gB = ((123, 456.7 ), (890, 135.7))) 
+      report "***FAILED TEST: c09s06b00x00p04n05i01781 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c09s06b00x00p04n05i01781arch_a;
+
+-------------------------------------------------------------------------
+
+ENTITY c09s06b00x00p04n05i01781ent IS
+END c09s06b00x00p04n05i01781ent;
+
+use work.c09s06b00x00p04n05i01781pkg.all;
+ARCHITECTURE c09s06b00x00p04n05i01781arch OF c09s06b00x00p04n05i01781ent IS
+  subtype reg32    is Bit_vector ( 31 downto 0 );
+  subtype string16    is String ( 1 to 16 );
+  component MultiType
+    generic (
+      g0  :   Boolean        ;
+      g1  :   Bit            ;
+      g2  :   Character      ;
+      g3  :   SEVERITY_LEVEL ;
+      g4  :   Integer        ;
+      g5  :   Real           ;
+      g6  :   TIME           ;
+      g7  :   Natural        ;
+      g8  :   Positive       ;
+      g9  :   String         ;
+      gA  :   Bit_vector     ;
+      gB  :   stuff
+      );
+  end component;
+  for u1 : MultiType use entity work.c09s06b00x00p04n05i01781ent_a(c09s06b00x00p04n05i01781arch_a);
+
+BEGIN
+  u1 : MultiType
+    generic map (
+      True,
+      '0',
+      '@',
+      NOTE,
+      123456789,
+      987654321.5,
+      110 ns,
+      12312,
+      3423,
+      "16 characters OK",
+      B"0101_0010_1001_0101_0010_1010_0101_0100",
+      gB(2) => ( 890, 135.7 ),
+      gB(1) => ( 123, 456.7 )
+      );
+
+END c09s06b00x00p04n05i01781arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1782.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1782.vhd
new file mode 100644
index 0000000..567dca0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1782.vhd
@@ -0,0 +1,136 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1782.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c09s06b00x00p04n05i01782pkg is
+  type info is record
+                 field_1 : integer;
+                 field_2 : real;
+               end record;
+  type stuff is array (Integer range 1 to 2) of info;
+end c09s06b00x00p04n05i01782pkg;
+
+use work.c09s06b00x00p04n05i01782pkg.all;
+entity c09s06b00x00p04n05i01782ent_a is
+  generic (
+    g0  :   Boolean        ;
+    g1  :   Bit            ;
+    g2  :   Character      ;
+    g3  :   SEVERITY_LEVEL ;
+    g4  :   Integer        ;
+    g5  :   Real           ;
+    g6  :   TIME           ;
+    g7  :   Natural        ;
+    g8  :   Positive       ;
+    g9  :   String         ;
+    gA  :   Bit_vector     ;
+    gB  :   stuff      := ((234,567.7),(429,35.7))
+    );
+end c09s06b00x00p04n05i01782ent_a;
+
+use work.c09s06b00x00p04n05i01782pkg.all;
+architecture c09s06b00x00p04n05i01782arch_a of c09s06b00x00p04n05i01782ent_a is
+  -- Check that the data was passed...
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert NOT(   g0 = True                   and 
+                  g1 = '0'                      and  
+                  g2 = '@'                      and 
+                  g3 = NOTE                     and 
+                  g4 = 123456789                and 
+                  g5 = 987654321.5              and 
+                  g6 = 110  ns                   and 
+                  g7 = 12312                    and 
+                  g8 = 3423                     and 
+                  g9 = "16 characters OK"       and 
+                  gA = B"01010010100101010010101001010100"and 
+                  gB = ((123, 456.7 ), (890, 135.7))) 
+      report "***PASSED TEST: c09s06b00x00p04n05i01782"
+      severity NOTE;
+    assert (   g0 = True                   and 
+               g1 = '0'                      and  
+               g2 = '@'                      and 
+               g3 = NOTE                     and 
+               g4 = 123456789                and 
+               g5 = 987654321.5              and 
+               g6 = 110  ns                   and 
+               g7 = 12312                    and 
+               g8 = 3423                     and 
+               g9 = "16 characters OK"       and 
+               gA = B"01010010100101010010101001010100"and 
+               gB = ((123, 456.7 ), (890, 135.7))) 
+      report "***FAILED TEST: c09s06b00x00p04n05i01782 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c09s06b00x00p04n05i01782arch_a;
+
+-------------------------------------------------------------------------
+
+ENTITY c09s06b00x00p04n05i01782ent IS
+END c09s06b00x00p04n05i01782ent;
+
+
+use work.c09s06b00x00p04n05i01782pkg.all;
+ARCHITECTURE c09s06b00x00p04n05i01782arch OF c09s06b00x00p04n05i01782ent IS
+  subtype reg32    is Bit_vector ( 31 downto 0 );
+  subtype string16    is String ( 1 to 16 );
+  component MultiType
+    generic (
+      g0  :   Boolean        ;
+      g1  :   Bit            ;
+      g2  :   Character      ;
+      g3  :   SEVERITY_LEVEL ;
+      g4  :   Integer        ;
+      g5  :   Real           ;
+      g6  :   TIME           ;
+      g7  :   Natural        ;
+      g8  :   Positive       ;
+      g9  :   String         ;
+      gA  :   Bit_vector     ;
+      gB  :   stuff      :=((123,456.7),(890,135.7))); 
+  end component; 
+  for u1 : MultiType use entity work.c09s06b00x00p04n05i01782ent_a(c09s06b00x00p04n05i01782arch_a); 
+BEGIN 
+  u1 : MultiType generic map ( 
+    True, 
+    '0', 
+    '@', 
+    NOTE, 
+    123456789,
+    987654321.5,
+    110 ns,
+    12312,
+    3423,
+    "16 characters OK",
+    B"0101_0010_1001_0101_0010_1010_0101_0100"
+    );
+
+END c09s06b00x00p04n05i01782arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1785.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1785.vhd
new file mode 100644
index 0000000..b76d370
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1785.vhd
@@ -0,0 +1,154 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1785.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c09s06b00x00p04n07i01785pkg is
+  type info is record
+                 field_1 : integer;
+                 field_2 : real;
+               end record;
+  type stuff is array (Integer range 1 to 2) of info;
+end c09s06b00x00p04n07i01785pkg;
+
+use work.c09s06b00x00p04n07i01785pkg.all;
+entity c09s06b00x00p04n07i01785ent_a is
+  port    (
+    port_0  : in Boolean        ;
+    port_1  : in Bit            ;
+    port_2  : in Character      ;
+    port_3  : in SEVERITY_LEVEL ;
+    port_4  : in Integer        ;
+    port_5  : in Real           ;
+    port_6  : in TIME           ;
+    port_7  : in Natural        ;
+    port_8  : in Positive       ;
+    port_9  : in String         ; 
+    port_A  : in Bit_vector     ;
+    port_B  : in stuff
+    );
+end c09s06b00x00p04n07i01785ent_a;
+
+
+use work.c09s06b00x00p04n07i01785pkg.all;
+architecture c09s06b00x00p04n07i01785arch_a of c09s06b00x00p04n07i01785ent_a is
+  -- Check that the data was passed...
+begin
+  TESTING: PROCESS(port_0,port_1,port_2,port_3,port_4,port_5,port_6,port_7,port_8)
+  BEGIN
+    assert NOT(   port_0 = True                and 
+                  port_1 = '0'                and 
+                  port_2 = '@'                  and 
+                  port_3 = NOTE                and 
+                  port_4 = 123456789                 and
+                  port_5 = 987654321.5              and
+                  port_6 = 110 ns                  and
+                  port_7 = 12312                  and 
+                  port_8 = 3423                  and 
+                  port_9 = "16 characters OK"          and 
+                  port_A = B"01010010100101010010101001010100"    and 
+                  port_B = ((123, 456.7), (890, 135.7))) 
+      report "***PASSED TEST: c09s06b00x00p04n07i01785"
+      severity NOTE;
+    assert (   port_0 = True                and 
+               port_1 = '0'                and 
+               port_2 = '@'                  and 
+               port_3 = NOTE                and 
+               port_4 = 123456789                 and
+               port_5 = 987654321.5              and
+               port_6 = 110 ns                  and
+               port_7 = 12312                  and 
+               port_8 = 3423                  and 
+               port_9 = "16 characters OK"          and 
+               port_A = B"01010010100101010010101001010100"    and 
+               port_B = ((123, 456.7), (890, 135.7))) 
+      report "***FAILED TEST: c09s06b00x00p04n07i01785 - Port map aspect associates a single actual with each local port in the corresponding component declaration test failed."
+      severity ERROR;
+  END PROCESS TESTING;
+end c09s06b00x00p04n07i01785arch_a;
+
+-----------------------------------------------------------------------
+
+ENTITY c09s06b00x00p04n07i01785ent IS
+END c09s06b00x00p04n07i01785ent;
+
+
+use work.c09s06b00x00p04n07i01785pkg.all;
+ARCHITECTURE c09s06b00x00p04n07i01785arch OF c09s06b00x00p04n07i01785ent IS
+  subtype reg32    is Bit_vector ( 31 downto 0 );
+  subtype string16    is String ( 1 to 16 );
+  
+  signal sig_0  :   Boolean        := TRUE;
+  signal sig_1  :   Bit            := '0';
+  signal sig_2  :   Character      := '@';
+  signal sig_3  :   SEVERITY_LEVEL := NOTE;
+  signal sig_4  :   Integer        := 123456789;
+  signal sig_5  :   Real           := 987654321.5;
+  signal sig_6  :   TIME           := 110 NS;
+  signal sig_7  :   Natural        := 12312;
+  signal sig_8  :   Positive       := 3423;
+  signal sig_9  :   String16       := "16 characters OK";
+  signal sig_A  :   REG32          := B"0101_0010_1001_0101_0010_1010_0101_0100";
+  signal sig_B  :   stuff          := (( 123, 456.7 ), ( 890, 135.7 ));
+
+  component MultiType
+    port    (
+      port_0  : in Boolean        ;
+      port_1  : in Bit            ;
+      port_2  : in Character      ;
+      port_3  : in SEVERITY_LEVEL ;
+      port_4  : in Integer        ;
+      port_5  : in Real           ;
+      port_6  : in TIME           ;
+      port_7  : in Natural        ;
+      port_8  : in Positive       ;
+      port_9  : in String         ;
+      port_A  : in Bit_vector     ;
+      port_B  : in stuff
+      );
+  end component;
+  for u1 : MultiType use entity work.c09s06b00x00p04n07i01785ent_a (c09s06b00x00p04n07i01785arch_a);
+
+BEGIN
+  u1 : MultiType
+    port map (
+      port_0 => sig_0,
+      port_1 => sig_1,
+      port_2 => sig_2,
+      port_3 => sig_3,
+      port_4 => sig_4,
+      port_5 => sig_5,
+      port_6 => sig_6,
+      port_7 => sig_7,
+      port_8 => sig_8,
+      port_9 => sig_9,
+      port_A => sig_A,
+      port_B => sig_B
+      );
+
+END c09s06b00x00p04n07i01785arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1787.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1787.vhd
new file mode 100644
index 0000000..9088d0f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1787.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1787.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c09s06b00x00p04n05i01787ent_a is
+  generic (
+    g0  :   Boolean        ;
+    g1  :   Bit            ;
+    g2  :   Character      ;
+    g3  :   SEVERITY_LEVEL ;
+    g4  :   Integer        ;
+    g5  :   Real           ;
+    g6  :   TIME           ;
+    g7  :   Natural        ;
+    g8  :   Positive       ;
+    g9  :   String         ;
+    gA  :   Bit_vector
+    );
+  port    (
+    port0  : out  Boolean        ;
+    port1  : out  Bit            ;
+    port2  : out  Character      ;
+    port3  : out  SEVERITY_LEVEL ;
+    port4  : out  Integer        ;
+    port5  : out  Real           ;
+    port6  : out  TIME           ;
+    port7  : out  Natural        ;
+    port8  : out  Positive       ;
+    port9  : out  String         ;
+    portA  : out  Bit_vector
+    );
+end c09s06b00x00p04n05i01787ent_a;
+
+architecture c09s06b00x00p04n05i01787arch_a of c09s06b00x00p04n05i01787ent_a is
+begin
+  port0 <= g0 after 11 ns;
+  port1 <= g1 after 11 ns;
+  port2 <= g2 after 11 ns;
+  port3 <= g3 after 11 ns;
+  port4 <= g4 after 11 ns;
+  port5 <= g5 after 11 ns;
+  port6 <= g6 after 11 ns;
+  port7 <= g7 after 11 ns;
+  port8 <= g8 after 11 ns;
+  port9 <= g9 after 11 ns;
+  portA <= gA after 11 ns;
+end c09s06b00x00p04n05i01787arch_a;
+
+ENTITY c09s06b00x00p04n05i01787ent IS
+END c09s06b00x00p04n05i01787ent;
+
+ARCHITECTURE c09s06b00x00p04n05i01787arch OF c09s06b00x00p04n05i01787ent IS
+  component MultiType
+    generic (
+      g0  :   Boolean        ;
+      g1  :   Bit            ;
+      g2  :   Character      ;
+      g3  :   SEVERITY_LEVEL ;
+      g4  :   Integer        ;
+      g5  :   Real           ;
+      g6  :   TIME           ;
+      g7  :   Natural        ;
+      g8  :   Positive       ;
+      g9  :   String         ;
+      gA  :   Bit_vector
+      );
+    port    (
+      port0  : out  Boolean        ;
+      port1  : out  Bit            ;
+      port2  : out  Character      ;
+      port3  : out  SEVERITY_LEVEL ;
+      port4  : out  Integer        ;
+      port5  : out  Real           ;
+      port6  : out  TIME           ;
+      port7  : out  Natural        ;
+      port8  : out  Positive       ;
+      port9  : out  String         ;
+      portA  : out  Bit_vector
+      );
+  end component;
+  for u1 : MultiType use entity work.c09s06b00x00p04n05i01787ent_a(c09s06b00x00p04n05i01787arch_a);
+
+  subtype reg32    is Bit_vector ( 31 downto 0 );
+  subtype string16    is String ( 1 to 16 );
+  
+  signal signal0  :   Boolean        ;
+  signal signal1  :   Bit            ;
+  signal signal2  :   Character      ;
+  signal signal3  :   SEVERITY_LEVEL ;
+  signal signal4  :   Integer        ;
+  signal signal5  :   Real           ;
+  signal signal6  :   TIME           ;
+  signal signal7  :   Natural        ;
+  signal signal8  :   Positive       ;
+  signal signal9  :   String16       ;
+  signal signalA  :   Reg32          ;
+  
+
+BEGIN
+  u1 : MultiType
+    generic map (
+      True,
+      '0',
+      '@',
+      NOTE,
+      123456789,
+      987654321.5,
+      110 ns,
+      12312,
+      3423,
+      "16 characters OK",
+      B"0101_0010_1001_0101_0010_1010_0101_0100"
+      )
+    port map (
+      signal0  ,
+      signal1  ,
+      signal2  ,
+      signal3  ,
+      signal4  ,
+      signal5  ,
+      signal6  ,
+      signal7  ,
+      signal8  ,
+      signal9  ,
+      signalA
+      );
+
+  TESTING: PROCESS
+  BEGIN
+    wait on signal0,signal1,signal2,signal3,signal4,signal5,signal6,signal7,signal8;
+    assert NOT(   signal0 = True                  and 
+                  signal1 = '0'                   and    
+                  signal2 = '@'                  and 
+                  signal3 = NOTE                and 
+                  signal4 = 123456789          and 
+                  signal5 = 987654321.5          and 
+                  signal6 = 110 ns              and 
+                  signal7 = 12312              and 
+                  signal8 = 3423              and 
+                  signal9 = "16 characters OK"    and 
+                  signalA = B"01010010100101010010101001010100")
+      report "***PASSED TEST: c09s06b00x00p04n05i01787"
+      severity NOTE;
+    assert (   signal0 = True                  and 
+               signal1 = '0'                   and    
+               signal2 = '@'                  and 
+               signal3 = NOTE                and 
+               signal4 = 123456789          and 
+               signal5 = 987654321.5          and 
+               signal6 = 110 ns              and 
+               signal7 = 12312              and 
+               signal8 = 3423              and 
+               signal9 = "16 characters OK"    and 
+               signalA = B"01010010100101010010101001010100")
+      report "***FAILED TEST: c09s06b00x00p04n05i01787 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s06b00x00p04n05i01787arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc179.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc179.vhd
new file mode 100644
index 0000000..cf6d060
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc179.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc179.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p02n01i00179ent IS
+  attribute attr : INTEGER;
+END c04s04b00x00p02n01i00179ent;
+
+ARCHITECTURE c04s04b00x00p02n01i00179arch OF c04s04b00x00p02n01i00179ent IS
+  constant    C : INTEGER    := 1;
+  attribute    attr of C : CONSTANT       is 40;
+  constant    D : INTEGER    := C'attr;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( C = 1 and D = 40 )
+      report "***PASSED TEST: c04s04b00x00p02n01i00179"
+      severity NOTE;
+    assert ( C = 1 and D = 40 )
+      report "***FAILED TEST: c04s04b00x00p02n01i00179 - User-defined attribute test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p02n01i00179arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1792.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1792.vhd
new file mode 100644
index 0000000..b397f30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1792.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1792.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s07b00x00p05n01i01792ent IS
+END c09s07b00x00p05n01i01792ent;
+
+ARCHITECTURE c09s07b00x00p05n01i01792arch OF c09s07b00x00p05n01i01792ent IS
+
+BEGIN
+  L1: for I in 1 to 3 generate
+  end generate L1;
+
+  L2: if true generate
+  end generate L2;            -- No_failure_here
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s07b00x00p05n01i01792" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s07b00x00p05n01i01792arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1793.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1793.vhd
new file mode 100644
index 0000000..c50f943
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1793.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1793.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s07b00x00p06n02i01793ent IS
+END c09s07b00x00p06n02i01793ent;
+
+ARCHITECTURE c09s07b00x00p06n02i01793arch OF c09s07b00x00p06n02i01793ent IS
+  type   Day is (Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday);
+
+  procedure i_proof_1 (x : integer) is
+  begin
+  end i_proof_1;
+
+  procedure i_proof_2 (x : character) is
+  begin
+  end i_proof_2;
+
+  procedure i_proof_3 (x : Day) is
+  begin
+  end i_proof_3;
+
+BEGIN
+
+  glabel1 : FOR i in 0 to 8 generate
+    i_proof_1(i);
+  end generate glabel1;
+
+  glabel2 : FOR i in 'A' to 'Z' generate
+    i_proof_2(i);
+  end generate glabel2;
+
+  glabel3 : FOR i in Monday to Sunday generate
+    i_proof_3(i);
+  end generate glabel3;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s07b00x00p06n02i01793"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s07b00x00p06n02i01793arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1798.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1798.vhd
new file mode 100644
index 0000000..919825e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1798.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1798.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p02n01i01798ent IS
+END c07s01b00x00p02n01i01798ent;
+
+ARCHITECTURE c07s01b00x00p02n01i01798arch OF c07s01b00x00p02n01i01798ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 3;
+    variable y : integer := 5;
+    variable z : integer := 9;
+  BEGIN
+    if -x + z <  y + x and x * z > y - x then  -- No_failure_here
+      x := x - z;
+    end if;
+    assert NOT(x=-6) 
+      report "***PASSED TEST: c07s01b00x00p02n01i01798"
+      severity NOTE;
+    assert (x=-6) 
+      report "***FAILED TEST: c07s01b00x00p02n01i01798 - The expression is a valid expression according to the rules of the syntactic diagram." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p02n01i01798arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc18.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc18.vhd
new file mode 100644
index 0000000..4d3f6b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc18.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc18.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p09n01i00018ent IS
+END c04s02b00x00p09n01i00018ent;
+
+ARCHITECTURE c04s02b00x00p09n01i00018arch OF c04s02b00x00p09n01i00018ent IS
+BEGIN
+  TESTING: PROCESS
+    -- Define a subtype.
+    subtype DEC is INTEGER range 1 to 10;
+
+    -- Define a subtype based on DEC.
+    subtype DEC2 is DEC;
+
+    -- Define two variable counters.
+    variable CNT1, CNT2 : INTEGER := 0;
+  BEGIN
+    -- Verify that the range of DEC is the same as DEC2.
+    for I in DEC loop
+      CNT1 := CNT1 + 1;
+    end loop;
+    for I in DEC2 loop
+      CNT2 := CNT2 + 1;
+    end loop;
+    assert NOT( CNT1 = CNT2 )
+      report "***PASSED TEST: c04s02b00x00p09n01i00018"
+      severity NOTE;
+    assert ( CNT1 = CNT2 )
+      report "***FAILED TEST: c04s02b00x00p09n01i00018 - If the subtype indication does not indicate a type constraint, the subtype is the same as that denoted by the type mark."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p09n01i00018arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc180.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc180.vhd
new file mode 100644
index 0000000..889f01f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc180.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc180.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p03n01i00180ent IS
+END c04s04b00x00p03n01i00180ent;
+
+ARCHITECTURE c04s04b00x00p03n01i00180arch OF c04s04b00x00p03n01i00180ent IS
+  attribute p: POSITIVE;
+  signal s: integer;
+  attribute p of s: signal is 10;  -- Success_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT( s'p=10 )
+      report "***PASSED TEST: c04s04b00x00p03n01i00180"
+      severity NOTE;
+    assert ( s'p=10 )
+      report "***FAILED TEST: c04s04b00x00p03n01i00180 - In attribute declaration, the reserved word attribute must be followed by an identifier, a colon, a type mark and a semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p03n01i00180arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1801.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1801.vhd
new file mode 100644
index 0000000..4850bdd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1801.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1801.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p03n01i01801ent IS
+END c07s01b00x00p03n01i01801ent;
+
+ARCHITECTURE c07s01b00x00p03n01i01801arch OF c07s01b00x00p03n01i01801ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c07s01b00x00p03n01i01801"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c07s01b00x00p03n01i01801"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c07s01b00x00p03n01i01801arch;
+
+-- CONFIGURATION c07s01b00x00p03n01i01801cfg OF c07s01b00x00p03n01i01801ent IS
+--     FOR c07s01b00x00p03n01i01801arch
+--     END FOR;
+-- END c07s01b00x00p03n01i01801cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1803.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1803.vhd
new file mode 100644
index 0000000..ae2157c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1803.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1803.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p05n01i01803ent IS
+END c07s01b00x00p05n01i01803ent;
+
+ARCHITECTURE c07s01b00x00p05n01i01803arch OF c07s01b00x00p05n01i01803ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 3;
+    variable y : integer := 5;
+    variable z : integer := 9;
+  BEGIN
+    if ((-x + z) < (y + x)) then     -- NO_Failure_here
+      -- sign can appear before the first term.
+      x := y * z;
+    end if;
+    assert NOT(x = 45) 
+      report "***PASSED TEST: c07s01b00x00p05n01i01803"
+      severity NOTE;
+    assert (x = 45) 
+      report "***FAILED TEST: c07s01b00x00p05n01i01803 - Sign appear before the first term in a simple expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p05n01i01803arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1804.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1804.vhd
new file mode 100644
index 0000000..853be07
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1804.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1804.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p06n01i01804ent IS
+END c07s01b00x00p06n01i01804ent;
+
+ARCHITECTURE c07s01b00x00p06n01i01804arch OF c07s01b00x00p06n01i01804ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 0;
+    variable y : integer := 2;
+    variable z : integer := 5;
+  BEGIN
+    x := y * 10 * z;  -- No_failure_here
+    assert NOT( x=100 )
+      report "***PASSED TEST: c07s01b00x00p06n01i01804"
+      severity NOTE;
+    assert ( x=100 )
+      report "***FAILED TEST: c07s01b00x00p06n01i01804 - The term must be factor or a sequence of factors combined with multiplying operators."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p06n01i01804arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1807.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1807.vhd
new file mode 100644
index 0000000..0385ce0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1807.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1807.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i01807ent IS
+END c07s01b00x00p07n01i01807ent;
+
+ARCHITECTURE c07s01b00x00p07n01i01807arch OF c07s01b00x00p07n01i01807ent IS
+  signal POS : integer;
+  signal P1  : integer := 2;
+  signal P2  : integer := 2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    POS <= P1 ** P2 after 20 ns;   
+    wait for 35 ns;
+    assert NOT(POS = 4) 
+      report "***PASSED TEST: c07s01b00x00p07n01i01807"
+      severity NOTE;
+    assert (POS = 4) 
+      report "***FAILED TEST: c07s01b00x00p07n01i01807 - Primary**primary test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i01807arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1808.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1808.vhd
new file mode 100644
index 0000000..ab589dd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1808.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1808.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i01808ent IS
+END c07s01b00x00p07n01i01808ent;
+
+ARCHITECTURE c07s01b00x00p07n01i01808arch OF c07s01b00x00p07n01i01808ent IS
+  signal POS : integer;
+  signal P1  : integer := -2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    POS <=  abs P1 after 20 ns;   
+    wait for 35 ns;
+    assert NOT(POS = 2) 
+      report "***PASSED TEST: c07s01b00x00p07n01i01808" 
+      severity NOTE;
+    assert (POS = 2) 
+      report "***FAILED TEST: c07s01b00x00p07n01i01808 - abs Primary test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i01808arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1809.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1809.vhd
new file mode 100644
index 0000000..4f077bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1809.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1809.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i01809ent IS
+END c07s01b00x00p07n01i01809ent;
+
+ARCHITECTURE c07s01b00x00p07n01i01809arch OF c07s01b00x00p07n01i01809ent IS
+  signal POS : boolean;
+  signal P1  : boolean := false;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    POS <=  not P1 after 20 ns;   
+    wait for 35 ns;
+    assert NOT(POS = true) 
+      report "***PASSED TEST: c07s01b00x00p07n01i01809" 
+      severity NOTE;
+    assert (POS = true) 
+      report "***FAILED TEST: c07s01b00x00p07n01i01809 - not Primary test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i01809arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1810.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1810.vhd
new file mode 100644
index 0000000..e577081
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1810.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1810.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01810ent IS
+END c07s01b00x00p08n01i01810ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01810arch OF c07s01b00x00p08n01i01810ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a1 : boolean := true;
+    variable b1 : boolean;
+    variable x1 : integer := 12;
+    variable y1 : real := 12.3;
+    variable p1 : real := 12.5;
+    variable z1 : integer := 10;
+  BEGIN
+    b1 := (x1 < z1) or (y1 > p1) or (x1 = z1) or a1; -- No_failure_here
+    assert NOT(b1 = true)
+      report "***PASSED TEST: c07s01b00x00p08n01i01810"
+      severity NOTE;
+    assert ( b1 = true )
+      report "***FAILED TEST: c07s01b00x00p08n01i01810 - The primary must be a name, a literal, an aggregate, a function call, a qualified expression, a type conversion, an allocator, or an expression enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01810arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1813.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1813.vhd
new file mode 100644
index 0000000..3fd1be3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1813.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1813.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01813ent IS
+END c07s01b00x00p08n01i01813ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01813arch OF c07s01b00x00p08n01i01813ent IS
+  type A1  is array (1 to 5) of integer;
+  type Acc is access A1;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Acc := new A1'(1,2,3,4,5);
+    variable V2 : integer;
+    variable V3 : integer;
+    variable V4 : integer;
+    variable V5 : integer;
+    variable V6 : integer;
+  BEGIN
+    V2 := V1(1); -- No_failure_here
+    V3 := V1(2); -- No_failure_here
+    V4 := V1(3); -- No_failure_here
+    V5 := V1(4); -- No_failure_here
+    V6 := V1(5); -- No_failure_here
+    assert NOT(V2=1 and V3=2 and V4=3 and V5=4 and V6=5)
+      report "***PASSED TEST: c07s01b00x00p08n01i01813"
+      severity NOTE;
+    assert (V2=1 and V3=2 and V4=3 and V5=4 and V6=5)
+      report "***FAILED TEST: c07s01b00x00p08n01i01813 - The primary must be a name, a literal, an aggregate, a function call, a qualified expression, a type conversion, an allocator, or an expression enclosed within parentheses."  
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01813arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc182.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc182.vhd
new file mode 100644
index 0000000..842d3d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc182.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc182.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p04n02i00182ent IS
+END c04s04b00x00p04n02i00182ent;
+
+ARCHITECTURE c04s04b00x00p04n02i00182arch OF c04s04b00x00p04n02i00182ent IS
+  type COORDINATE is
+    record
+      X, Y: INTEGER;
+    end record;
+  attribute    LOCATION         : COORDINATE;
+  signal       loc1, loc2    : COORDINATE;
+  attribute LOCATION    of loc1   : signal is (10, 15);
+  attribute LOCATION    of others : signal is (25, 77);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    loc1'LOCATION = (10, 15)   and
+                   loc2'LOCATION = (25, 77)   )
+      report "***PASSED TEST: c04s04b00x00p04n02i00182"
+      severity NOTE;
+    assert (    loc1'LOCATION = (10, 15)   and
+                loc2'LOCATION = (25, 77)   )
+      report "***FAILED TEST: c04s04b00x00p04n02i00182 - Attribute associated with a signal test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p04n02i00182arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc183.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc183.vhd
new file mode 100644
index 0000000..ddbf5b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc183.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc183.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s04b00x00p04n02i00183pkg is
+  attribute    a1    : integer;
+  attribute    a2    : integer;
+  attribute    a1    of c04s04b00x00p04n02i00183pkg : package is 3;
+  constant     c1    : integer  := c04s04b00x00p04n02i00183pkg'a1;
+  attribute    a2    of c04s04b00x00p04n02i00183pkg : package is c1 * 2;
+  function    fn1    return integer;
+  function    fn2    return integer;
+end c04s04b00x00p04n02i00183pkg;
+
+package body c04s04b00x00p04n02i00183pkg is
+  constant t1 : integer := 3; --testgen'a1;
+  constant t2 : integer := 6; --testgen'a2;
+  function fn1 return integer is
+  begin
+    return t1;
+  end;
+  function fn2 return integer is
+  begin
+    return t2;
+  end;
+end c04s04b00x00p04n02i00183pkg;
+
+
+use work.c04s04b00x00p04n02i00183pkg.all;
+ENTITY c04s04b00x00p04n02i00183ent IS
+END c04s04b00x00p04n02i00183ent;
+
+ARCHITECTURE c04s04b00x00p04n02i00183arch OF c04s04b00x00p04n02i00183ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( c1 = 3 and fn1 = c1 and fn2 = c1+c1 )   
+      report "***PASSED TEST: c04s04b00x00p04n02i00183"
+      severity NOTE;
+    assert ( c1 = 3 and fn1 = c1 and fn2 = c1+c1 )   
+      report "***FAILED TEST: c04s04b00x00p04n02i00183 - Package attribute test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p04n02i00183arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc187.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc187.vhd
new file mode 100644
index 0000000..2f21fa3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc187.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc187.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p12n01i00187ent IS
+  attribute ATE             : INTEGER;
+  attribute ATE of  c04s04b00x00p12n01i00187ent   : entity is 2;
+  --Correct placement in interface declaration
+END c04s04b00x00p12n01i00187ent;
+
+ARCHITECTURE c04s04b00x00p12n01i00187arch OF c04s04b00x00p12n01i00187ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable S : integer;
+  BEGIN
+    S := c04s04b00x00p12n01i00187ent'ATE;
+    assert NOT( S = 2 )
+      report "***PASSED TEST: c04s04b00x00p12n01i00187"
+      severity NOTE;
+    assert ( S = 2 )
+      report "***FAILED TEST: c04s04b00x00p12n01i00187 - Attribute specification of the entity test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p12n01i00187arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc188.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc188.vhd
new file mode 100644
index 0000000..5d8f147
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc188.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc188.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p13n01i00188ent IS
+  port ( S2 : in    integer;
+         V2 : inout Real    ) ;
+  
+  attribute    V1 : REAL;
+  attribute    V1 of V2 : signal is 1.0;
+  alias    A2 : real is V2;
+  
+  attribute    S1 : INTEGER;
+  attribute    S1 of S2 : signal is 1;
+  alias    A1 : integer is S2;
+END c04s04b00x00p13n01i00188ent;
+
+ARCHITECTURE c04s04b00x00p13n01i00188arch OF c04s04b00x00p13n01i00188ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype    BTRUE    is BOOLEAN range TRUE to TRUE;
+    variable    B1    : BTRUE;
+  BEGIN
+    assert NOT( (A1'S1 = S2'S1) and (A2'V1 = V2'V1) )
+      report "***PASSED TEST: c04s04b00x00p13n01i00188"
+      severity NOTE;
+    assert ( (A1'S1 = S2'S1) and (A2'V1 = V2'V1) )
+      report "***FAILED TEST: c04s04b00x00p13n01i00188 - Attribute of an object applies to any alias of the object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p13n01i00188arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1906.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1906.vhd
new file mode 100644
index 0000000..53f1f34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1906.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1906.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p10n01i01906ent IS
+END c07s01b00x00p10n01i01906ent;
+
+ARCHITECTURE c07s01b00x00p10n01i01906arch OF c07s01b00x00p10n01i01906ent IS
+  type    MVL    is ('0','1','X','Z') ;
+  signal    Q    : MVL;
+  signal    PP,P2    : BIT := '1' ;
+  signal    R1    : BIT;
+BEGIN
+  TESTING: PROCESS
+    function "and" (L,R : MVL) return MVL is
+      variable V1 : MVL;
+    begin
+      if (L = '1') then
+        V1 := '1' ;
+      end if;
+      return V1;
+    end;
+  BEGIN
+    Q    <= "and"('1','Z');  -- No_failure_here
+    R1    <= PP and P2;
+    wait for 1 ns;
+    assert NOT((Q='1') and (R1='1'))
+      report "***PASSED TEST: c07s01b00x00p10n01i01906"
+      severity NOTE;
+    assert (( Q='1' ) and (R1='1'))
+      report "***FAILED TEST: c07s01b00x00p10n01i01906 - The identification of an overloaded operator depends on the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p10n01i01906arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1907.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1907.vhd
new file mode 100644
index 0000000..67ad1b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1907.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1907.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p11n01i01907ent IS
+END c07s01b00x00p11n01i01907ent;
+
+ARCHITECTURE c07s01b00x00p11n01i01907arch OF c07s01b00x00p11n01i01907ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable b1a, b2a, b3a, b4a : BOOLEAN;
+    variable b1o, b2o, b3o, b4o : BOOLEAN;
+    variable b1x, b2x, b3x, b4x : BOOLEAN;
+  BEGIN
+    -- Test that the following operators can be used associatively.
+    -- 1. AND.
+    b1a := TRUE;
+    b2a := TRUE;
+    b3a := FALSE;
+    assert (NOT (b1a AND b2a AND b3a))
+      report "AND operator cannot be used associatively.";
+    b4a := TRUE;
+    assert (b1a AND b2a AND b4a)
+      report "AND operator cannot be used associatively.";
+
+    -- 2. OR.
+    b1o := FALSE;
+    b2o := FALSE;
+    b3o := TRUE;
+    assert (b1o OR b2o OR b3o)
+      report "OR operator cannot be used associatively.";
+    b4o := FALSE;
+    assert (NOT (b1o OR b2o OR b4o))
+      report "OR operator cannot be used associatively.";
+    
+    -- 3. XOR.
+    b1x := TRUE;
+    b2x := TRUE;
+    b3x := FALSE;
+    assert (NOT (b1x XOR b2x XOR b3x))
+      report "XOR operator cannot be used associatively.";
+    b4x := TRUE;
+    assert (b1x XOR b2x XOR b4x)
+      report "XOR operator cannot be used associatively.";
+
+    wait for 5 ns;
+
+    assert NOT(    (NOT (b1a AND b2a AND b3a))    and
+                   (b1a AND b2a AND b4a)      and
+                   (b1o OR b2o OR b3o)      and
+                   (NOT (b1o OR b2o OR b4o))   and
+                   (NOT (b1x XOR b2x XOR b3x))   and
+                   (b1x XOR b2x XOR b4x)      )
+      report "***PASSED TEST: /src/ch07/sc01/p012/s010101.vhd"
+      severity NOTE;
+    assert (    (NOT (b1a AND b2a AND b3a))    and
+                (b1a AND b2a AND b4a)      and
+                (b1o OR b2o OR b3o)      and
+                (NOT (b1o OR b2o OR b4o))   and
+                (NOT (b1x XOR b2x XOR b3x))   and
+                (b1x XOR b2x XOR b4x)      )
+      report "***FAILED TEST: c07s01b00x00p11n01i01907 - Associative test for and or and xor failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p11n01i01907arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1908.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1908.vhd
new file mode 100644
index 0000000..18e837c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1908.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1908.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p09n01i01908ent IS
+END c07s02b00x00p09n01i01908ent;
+
+ARCHITECTURE c07s02b00x00p09n01i01908arch OF c07s02b00x00p09n01i01908ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( 1 + 2 * 3 = 10 / 2 + abs(-2) )
+      report "***PASSED TEST: c07s02b00x00p09n01i01908"
+      severity NOTE;
+    assert ( 1 + 2 * 3 = 10 / 2 + abs(-2) )
+      report "***FAILED TEST: c07s02b00x00p09n01i01908 - Operators of higher precedence are associated with their operands before operators of lower precedence."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p09n01i01908arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1909.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1909.vhd
new file mode 100644
index 0000000..6705646
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1909.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1909.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p09n03i01909ent IS
+END c07s02b00x00p09n03i01909ent;
+
+ARCHITECTURE c07s02b00x00p09n03i01909arch OF c07s02b00x00p09n03i01909ent IS
+  signal Q     : BIT := '1';
+  signal R     : BIT := '0';
+  signal S     : BIT := '1';
+  signal PP,P2 : BIT := '1' ;
+  signal R1    : BIT;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    R1 <= ((Q and S) or R) and (P2 and PP) ;
+    wait for 5 ns;
+    assert NOT( R1 = '1' )
+      report "***PASSED TEST: c07s02b00x00p09n03i01909"
+      severity NOTE;
+    assert ( R1 = '1' )
+      report "***FAILED TEST: c07s02b00x00p09n03i01909 - The parentheses can be used to control the association of operators and operands."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p09n03i01909arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1910.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1910.vhd
new file mode 100644
index 0000000..4228e66
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1910.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1910.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p09n01i01910ent IS
+END c07s02b00x00p09n01i01910ent;
+
+ARCHITECTURE c07s02b00x00p09n01i01910arch OF c07s02b00x00p09n01i01910ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable ValueB1 : BOOLEAN;
+    variable ValueB2 : BOOLEAN;
+    variable ValueB3 : BOOLEAN;
+    variable ValueB4 : BOOLEAN;
+    variable ValueI1, SameValueI1, DifferentValueI1 : INTEGER;
+    variable ValueI2, SameValueI2, DifferentValueI2 : INTEGER;
+    variable ValueI3, SameValueI3, DifferentValueI3 : INTEGER;
+    variable ValueI4, SameValueI4, DifferentValueI4 : INTEGER;
+    variable ValueI5, SameValueI5, DifferentValueI5 : INTEGER;
+    variable ValueI6, SameValueI6, DifferentValueI6 : INTEGER;
+    variable ValueI7, SameValueI7, DifferentValueI7 : INTEGER;
+  BEGIN
+    -- "+" (addition) operator, and the "-" operator.
+    --     - NOTE:  The following expression would not be able to parse
+    --              if the precedence used was such that the "=" operator
+    --              had a higher precedence than the "+" operator.  Thus,
+    --              if this parses you are guaranteed that the precedence
+    --              relative to these two levels is correctly defined.Same
+    --              goes for the "-" operator.
+    ValueB1         := 1 + 3 = 3 + 1;
+    assert (ValueB1)
+      report "The expression has not been processed correctly.(5)";
+    ValueB2         := 3 - 1 = 5 - 3;
+    assert (ValueB2)
+      report "The expression has not been processed correctly.(6)";
+    
+    -- "+" (sign) operator, and the "-" (sign) operator.
+    --     - NOTE:  The following expression would not be able to parse
+    --              if the precedence used was such that the "=" operator
+    --              had a higher precedence than the "+" operator.  Thus,
+    --              if this parses you are guaranteed that the precedence
+    --              relative to these two levels is correctly defined.Same
+    --              goes for the "-" operator.
+    ValueB3         := + 1 = + 1;
+    assert (ValueB3)
+      report "The expression has not been processed correctly.(7)";
+    ValueB4         := - 3 = - 3;
+    assert (ValueB4)
+      report "The expression has not been processed correctly.(8)";
+
+    ValueI1         := -3 + 4;
+    SameValueI1     := (-3) + 4;
+    DifferentValueI1:= -(3 + 4);
+    assert (ValueI1 = SameValueI1)
+      report "Values of lower precedence associated before those of higher precedence.(9)";
+    assert (ValueI1 /= DifferentValueI1)
+      report "Values of lower precedence associated before those of higher precedence.(10)";
+    
+    -- "*" operator.
+    ValueI2         := 3 + 4 * 5;
+    SameValueI2     := 3 + (4 * 5);
+    DifferentValueI2:= (3 + 4) * 5;
+    assert (ValueI2 = SameValueI2)
+      report "Values of lower precedence associated before those of higher precedence.(13)";
+    assert (ValueI2 /= DifferentValueI2)
+      report "Values of lower precedence associated before those of higher precedence.(14)";
+    
+    -- "/" operator.
+    ValueI3         := 5 + 10 / 5;
+    SameValueI3     := 5 + (10 / 5);
+    DifferentValueI3:= (5 + 10) / 5;
+    assert (ValueI3 = SameValueI3)
+      report "Values of lower precedence associated before those of higher precedence.(15)";
+    assert (ValueI3 /= DifferentValueI3)
+      report "Values of lower precedence associated before those of higher precedence.(16)";
+    
+    -- "mod" operator.
+    ValueI4         := 4 + 11 mod 3;
+    SameValueI4     := 4 + (11 mod 3);
+    DifferentValueI4:= (4 + 11) mod 3;
+    assert (ValueI4 = SameValueI4)
+      report "Values of lower precedence associated before those of higher precedence.(17)";
+    assert (ValueI4 /= DifferentValueI4)
+      report "Values of lower precedence associated before those of higher precedence.(18)";
+    
+    -- "rem" operator.
+    ValueI5         := 4 + 11 rem 3;
+    SameValueI5     := 4 + (11 rem 3);
+    DifferentValueI5:= (4 + 11) rem 3;
+    assert (ValueI5 = SameValueI5)
+      report "Values of lower precedence associated before those of higher precedence.(19)";
+    assert (ValueI5 /= DifferentValueI5)
+      report "Values of lower precedence associated before those of higher precedence.(20)";
+
+    -- "**" operator.
+    ValueI6         := 3 * 4 ** 2;
+    SameValueI6     := 3 * (4 ** 2);
+    DifferentValueI6:= (3 * 4) ** 2;
+    assert (ValueI6 = SameValueI6)
+      report "Values of lower precedence associated before those of higher precedence.(21)";
+    assert (ValueI6 /= DifferentValueI6)
+      report "Values of lower precedence associated before those of higher precedence.(22)";
+    
+    -- "abs" operator.
+    ValueI7         := abs (-5) * (-7);
+    SameValueI7     := (abs (-5)) * (-7);
+    DifferentValueI7:= abs((-5) * (-7));
+    assert (ValueI7 = SameValueI7)
+      report "Values of lower precedence associated before those of higher precedence.(23)";
+    assert (ValueI7 /= DifferentValueI7)
+      report "Values of lower precedence associated before those of higher precedence.(24)";
+
+    wait for 5 ns;
+
+    assert NOT(   (ValueB1)   and
+                  (ValueB2)   and 
+                  (ValueB3)   and 
+                  (ValueB4)   and 
+                  (ValueI1 = SameValueI1)      and
+                  (ValueI1 /= DifferentValueI1)   and
+                  (ValueI2 = SameValueI2)      and
+                  (ValueI2 /= DifferentValueI2)   and
+                  (ValueI3 = SameValueI3)      and
+                  (ValueI3 /= DifferentValueI3)   and
+                  (ValueI4 = SameValueI4)      and
+                  (ValueI4 /= DifferentValueI4)   and
+                  (ValueI5 = SameValueI5)      and
+                  (ValueI5 /= DifferentValueI5)   and
+                  (ValueI6 = SameValueI6)      and
+                  (ValueI6 /= DifferentValueI6)   and
+                  (ValueI7 = SameValueI7)      and
+                  (ValueI7 /= DifferentValueI7)   )
+      report "***PASSED TEST: c07s02b00x00p09n01i01910"
+      severity NOTE;
+    assert (   (ValueB1)   and
+               (ValueB2)   and 
+               (ValueB3)   and 
+               (ValueB4)   and 
+               (ValueI1 = SameValueI1)      and
+               (ValueI1 /= DifferentValueI1)   and
+               (ValueI2 = SameValueI2)      and
+               (ValueI2 /= DifferentValueI2)   and
+               (ValueI3 = SameValueI3)      and
+               (ValueI3 /= DifferentValueI3)   and
+               (ValueI4 = SameValueI4)      and
+               (ValueI4 /= DifferentValueI4)   and
+               (ValueI5 = SameValueI5)      and
+               (ValueI5 /= DifferentValueI5)   and
+               (ValueI6 = SameValueI6)      and
+               (ValueI6 /= DifferentValueI6)   and
+               (ValueI7 = SameValueI7)      and
+               (ValueI7 /= DifferentValueI7)   )
+      report "***FAILED TEST: c07s02b00x00p09n01i01910 - Operators of higher precedence are associated with their operands before operators of lower precedence."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p09n01i01910arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1911.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1911.vhd
new file mode 100644
index 0000000..ba8d49a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1911.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1911.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p09n02i01911ent IS
+END c07s02b00x00p09n02i01911ent;
+
+ARCHITECTURE c07s02b00x00p09n02i01911arch OF c07s02b00x00p09n02i01911ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable ValueI1, SameValueI1, DifferentValueI1 : INTEGER;
+    variable ValueI2, SameValueI2, DifferentValueI2 : INTEGER;
+    variable ValueI3, SameValueI3, DifferentValueI3 : INTEGER;
+    variable ValueI4, SameValueI4, DifferentValueI4 : INTEGER;
+  BEGIN
+    -- adding operators.  
+    --   Cannot compare the "&" operator against either the "+" or 
+    --   "-" operators.  The only two we can compare are the "+"
+    --         and the "-" operators.
+    -- "+", "-"
+    ValueI1         := 14 + 1 - 9 - 7;
+    SameValueI1     := ((14 + 1) - 9) - 7;
+    DifferentValueI1:= 14 + (1 - (9 - 7));
+    assert (ValueI1 = SameValueI1)
+      report "Values of same precedence are not evaluated left to right.";
+    assert (ValueI1 /= DifferentValueI1)
+      report "Values of same precedence are not evaluated left to right.";
+    
+    -- multiplying operators.
+    -- "*", "/"
+    ValueI2          := 14 / 7 * 3;
+    SameValueI2      := (14 / 7) * 3;   -- 6
+    DifferentValueI2 := 14 / (7 * 3);   -- 0
+    assert (ValueI2 = SameValueI2)
+      report "Values of same precedence are not evaluated left to right.";
+    assert (ValueI2 /= DifferentValueI2)
+      report "Values of same precedence are not evaluated left to right.";
+    
+    -- "*", "mod"
+    ValueI3          := 14 mod 7 * 3;
+    SameValueI3      := (14 mod 7) * 3;   -- 0
+    DifferentValueI3 := 14 mod (7 * 3);   -- 14
+    assert (ValueI3 = SameValueI3)
+      report "Values of same precedence are not evaluated left to right.";
+    assert (ValueI3 /= DifferentValueI3)
+      report "Values of same precedence are not evaluated left to right.";
+
+    -- "*", "rem"
+    ValueI4          := 14 rem 7 * 3;
+    SameValueI4      := (14 rem 7) * 3;   -- 0
+    DifferentValueI4 := 14 rem (7 * 3);   -- 14
+    assert (ValueI4 = SameValueI4)
+      report "Values of same precedence are not evaluated left to right.";
+    assert (ValueI4 /= DifferentValueI4)
+      report "Values of same precedence are not evaluated left to right.";
+    
+    wait for 5 ns;
+    assert NOT(    (ValueI1 = SameValueI1)   and
+                   (ValueI1 /= DifferentValueI1)   and
+                   (ValueI2 = SameValueI2)   and
+                   (ValueI2 /= DifferentValueI2)   and
+                   (ValueI3 = SameValueI3)   and
+                   (ValueI3 /= DifferentValueI3)   and
+                   (ValueI4 = SameValueI4)   and
+                   (ValueI4 /= DifferentValueI4)   )
+      report "***PASSED TEST: c07s02b00x00p09n02i01911"
+      severity NOTE;
+    assert (    (ValueI1 = SameValueI1)   and
+                (ValueI1 /= DifferentValueI1)   and
+                (ValueI2 = SameValueI2)   and
+                (ValueI2 /= DifferentValueI2)   and
+                (ValueI3 = SameValueI3)   and
+                (ValueI3 /= DifferentValueI3)   and
+                (ValueI4 = SameValueI4)   and
+                (ValueI4 /= DifferentValueI4)   )
+      report "***FAILED TEST: c07s02b00x00p09n02i01911 - Operators are not associated with their operands in textual order."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p09n02i01911arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1912.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1912.vhd
new file mode 100644
index 0000000..41819b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1912.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1912.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p09n03i01912ent IS
+END c07s02b00x00p09n03i01912ent;
+
+ARCHITECTURE c07s02b00x00p09n03i01912arch OF c07s02b00x00p09n03i01912ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1a,b2a,b3a   : BOOLEAN;
+    variable   b1b,b2b,b3b   : BOOLEAN;
+    variable   b1c,b2c,b3c   : BOOLEAN;
+    variable   i1a,i2a,i3a   : INTEGER;
+    variable   i1b,i2b,i3b   : INTEGER;
+  BEGIN
+    -- I. logical operator and relational operator.
+    b1a              := FALSE;
+    b2a              := FALSE;
+    b3a              := TRUE;
+    assert ((b1a and b2a) /= b3a)
+      report "1:Parentheses do NOT change the precedence of operation.";
+    
+    -- V. logical operator and miscellaneous operator.
+    b1b              := FALSE;
+    b2b              := TRUE;
+    assert (not (b1b and b2b))
+      report "2:Parentheses do NOT change the precedence of operation.";
+    
+    -- VI. relational operators cannot be thus compared to ANY other operators
+    --     but the NOT operator, because they return boolean values and no other
+    --     higher precedence operators work on this type.
+    b1c              := FALSE;
+    b2c              := TRUE;
+    assert (not (b1c >= b2c))
+      report "3:Parentheses do NOT change the precedence of operation.";
+
+    -- VIII. adding operator and multiplying operator.
+    i1a              := 3;
+    i2a              := 4;
+    i3a              := 5;
+    assert (((i1a + i2a) * i3a) = 35)
+      report "4:Parentheses do NOT change the precedence of operation.";
+    
+    -- XII. multiplying operator and miscellaneous operator.
+    i1b              := 2;
+    i2b              := 3;
+    i3b              := 2;
+    assert (((i1b + i2b) ** i3b) = 25)
+      report "5:Parentheses do NOT change the precedence of operation.";
+
+    wait for 5 ns;
+    assert NOT(   ((b1a and b2a) /= b3a)      and
+                  (not (b1b and b2b))      and
+                  (not (b1c >= b2c))      and
+                  (((i1a + i2a) * i3a) = 35)   and
+                  (((i1b + i2b) ** i3b) = 25)   )
+      report "***PASSED TEST: c07s02b00x00p09n03i01912"
+      severity NOTE;
+    assert (   ((b1a and b2a) /= b3a)      and
+               (not (b1b and b2b))      and
+               (not (b1c >= b2c))      and
+               (((i1a + i2a) * i3a) = 35)   and
+               (((i1b + i2b) ** i3b) = 25)   )
+      report "***FAILED TEST: c07s02b00x00p09n03i01912 - The parentheses should be able to control the association of operators and operands."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p09n03i01912arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1914.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1914.vhd
new file mode 100644
index 0000000..813da17
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1914.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1914.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01914ent IS
+END c07s02b01x00p01n01i01914ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01914arch OF c07s02b01x00p01n01i01914ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := not b1;
+    assert NOT(b1 = '1') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01914" 
+      severity NOTE;
+    assert (b1 = '1') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01914 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01914arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1915.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1915.vhd
new file mode 100644
index 0000000..572302c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1915.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1915.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01915ent IS
+END c07s02b01x00p01n01i01915ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01915arch OF c07s02b01x00p01n01i01915ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := b1 and b1;
+    assert NOT(b1 = '0') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01915"
+      severity NOTE;
+    assert (b1 = '0') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01915 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01915arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1916.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1916.vhd
new file mode 100644
index 0000000..9be00fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1916.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1916.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01916ent IS
+END c07s02b01x00p01n01i01916ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01916arch OF c07s02b01x00p01n01i01916ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := b1 or b1;
+    assert NOT(b1 = '0') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01916" 
+      severity NOTE;
+    assert (b1 = '0') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01916 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01916arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1917.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1917.vhd
new file mode 100644
index 0000000..dedff4b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1917.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1917.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01917ent IS
+END c07s02b01x00p01n01i01917ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01917arch OF c07s02b01x00p01n01i01917ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := b1 nand b1;
+    assert NOT(b1 = '1') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01917" 
+      severity NOTE;
+    assert (b1 = '1') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01917 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01917arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1918.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1918.vhd
new file mode 100644
index 0000000..7c6e53e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1918.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1918.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01918ent IS
+END c07s02b01x00p01n01i01918ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01918arch OF c07s02b01x00p01n01i01918ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := b1 xor b1;
+    assert NOT(b1 = '0') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01918" 
+      severity NOTE;
+    assert (b1 = '0') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01918 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01918arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1919.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1919.vhd
new file mode 100644
index 0000000..7d6340a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1919.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1919.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01919ent IS
+END c07s02b01x00p01n01i01919ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01919arch OF c07s02b01x00p01n01i01919ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : bit := '0';
+  BEGIN
+    b1 := b1 nor b1;
+    assert NOT(b1 = '1') 
+      report "***PASSED TEST: c07s02b01x00p01n01i01919" 
+      severity NOTE;
+    assert (b1 = '1') 
+      report "***FAILED TEST: c07s02b01x00p01n01i01919 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01919arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1920.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1920.vhd
new file mode 100644
index 0000000..2167a6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1920.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1920.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01920ent IS
+END c07s02b01x00p01n01i01920ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01920arch OF c07s02b01x00p01n01i01920ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := not b1;
+    assert NOT(b1 = FALSE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01920" 
+      severity NOTE;
+    assert (b1 = FALSE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01920 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01920arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1921.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1921.vhd
new file mode 100644
index 0000000..a4a2a5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1921.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1921.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01921ent IS
+END c07s02b01x00p01n01i01921ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01921arch OF c07s02b01x00p01n01i01921ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := b1 and b1;
+    assert NOT(b1 = TRUE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01921"
+      severity NOTE;
+    assert (b1 = TRUE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01921 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01921arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1922.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1922.vhd
new file mode 100644
index 0000000..30b0aed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1922.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1922.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01922ent IS
+END c07s02b01x00p01n01i01922ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01922arch OF c07s02b01x00p01n01i01922ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := b1 or b1;
+    assert NOT(b1 = TRUE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01922"
+      severity NOTE;
+    assert (b1 = TRUE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01922 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01922arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1923.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1923.vhd
new file mode 100644
index 0000000..baffde1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1923.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1923.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01923ent IS
+END c07s02b01x00p01n01i01923ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01923arch OF c07s02b01x00p01n01i01923ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := b1 nand b1;
+    assert NOT(b1 = FALSE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01923" 
+      severity NOTE;
+    assert (b1 = FALSE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01923 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01923arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1924.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1924.vhd
new file mode 100644
index 0000000..a6ed08a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1924.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1924.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01924ent IS
+END c07s02b01x00p01n01i01924ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01924arch OF c07s02b01x00p01n01i01924ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := b1 xor b1;
+    assert NOT(b1 = FALSE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01924"
+      severity NOTE;
+    assert (b1 = FALSE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01924 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01924arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1925.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1925.vhd
new file mode 100644
index 0000000..2185442
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1925.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1925.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01925ent IS
+END c07s02b01x00p01n01i01925ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01925arch OF c07s02b01x00p01n01i01925ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   b1 : Boolean := TRUE;
+  BEGIN
+    b1 := b1 nor b1;
+    assert NOT(b1 = FALSE) 
+      report "***PASSED TEST: c07s02b01x00p01n01i01925" 
+      severity NOTE;
+    assert (b1 = FALSE) 
+      report "***FAILED TEST: c07s02b01x00p01n01i01925 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01925arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1931.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1931.vhd
new file mode 100644
index 0000000..1f27f2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1931.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1931.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01931ent IS
+END c07s02b01x00p01n02i01931ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01931arch OF c07s02b01x00p01n02i01931ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+--
+--          Test operators on one-dimesioned arrays of BIT
+--
+    ASSERT ( B"1100" AND  B"1010" ) = B"1000" 
+      REPORT "ERROR: composite AND operator failed : BIT"
+      SEVERITY FAILURE;
+    ASSERT ( B"1100"  OR  B"1010" ) = B"1110" 
+      REPORT "ERROR: composite  OR operator failed : BIT"
+      SEVERITY FAILURE;
+    ASSERT ( B"1100" NAND B"1010" ) = B"0111" 
+      REPORT "ERROR: composite NAND operator failed : BIT"
+      SEVERITY FAILURE;
+    ASSERT ( B"1100" NOR  B"1010" ) = B"0001" 
+      REPORT "ERROR: composite NOR operator failed : BIT"
+      SEVERITY FAILURE;
+    ASSERT ( B"1100" XOR  B"1010" ) = B"0110" 
+      REPORT "ERROR: composite XOR operator failed : BIT"
+      SEVERITY FAILURE;
+    ASSERT (         NOT  B"1100" ) = B"0011" 
+      REPORT "ERROR: composite NOT operator failed : BIT"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   (( B"1100" AND  B"1010" ) = B"1000")   and
+                  (( B"1100"  OR  B"1010" ) = B"1110")   and
+                  (( B"1100" NAND B"1010" ) = B"0111")   and
+                  (( B"1100" NOR  B"1010" ) = B"0001")   and
+                  (( B"1100" XOR  B"1010" ) = B"0110")   and
+                  ((         NOT  B"1100" ) = B"0011")   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01931"
+      severity NOTE;
+    assert (   (( B"1100" AND  B"1010" ) = B"1000")   and
+               (( B"1100"  OR  B"1010" ) = B"1110")   and
+               (( B"1100" NAND B"1010" ) = B"0111")   and
+               (( B"1100" NOR  B"1010" ) = B"0001")   and
+               (( B"1100" XOR  B"1010" ) = B"0110")   and
+               ((         NOT  B"1100" ) = B"0011")   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01931 - Logical operators should be valid for any one-dimensional array type whose element type is BIT."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01931arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1932.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1932.vhd
new file mode 100644
index 0000000..5aa6a7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1932.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1932.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01932ent IS
+END c07s02b01x00p01n02i01932ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01932arch OF c07s02b01x00p01n02i01932ent IS
+  SUBTYPE bit_8 is bit_vector(0 to 7);
+  SUBTYPE bit_4 is bit_vector(0 to 3);
+BEGIN
+  TESTING: PROCESS
+    CONSTANT slice_8a : bit_8 := B"1010_0011";
+    VARIABLE slice_8b : bit_8 := B"1110_1001";
+    VARIABLE target_1 : bit_4;
+    VARIABLE target_2 : bit_4;
+    VARIABLE target_3 : bit_4;
+    VARIABLE target_4 : bit_4;
+    VARIABLE target_5 : bit_4;
+    VARIABLE target_6 : bit_4;
+  BEGIN
+    target_1 := slice_8a (3 to 6) AND slice_8b (4 to 7);
+
+    target_2 := slice_8a (3 to 6) OR slice_8b (4 to 7);
+
+    target_3 := slice_8a (3 to 6) NOR slice_8b (4 to 7);
+
+    target_4 := slice_8a (3 to 6) NAND slice_8b (4 to 7);
+
+    target_5 := slice_8a (3 to 6) XOR slice_8b (4 to 7);
+    
+    target_6 := NOT slice_8b (0 to 3);
+
+    assert NOT(
+      target_1 = B"0001"   and
+      target_2 = B"1001"   and
+      target_3 = B"0110"   and
+      target_4 = B"1110"   and
+      target_5 = B"1000"   and
+      target_6 = B"0001"   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01932" 
+      severity NOTE;
+    assert (
+      target_1 = B"0001"   and
+      target_2 = B"1001"   and
+      target_3 = B"0110"   and
+      target_4 = B"1110"   and
+      target_5 = B"1000"   and
+      target_6 = B"0001"   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01932 - Logical operators are valid for bit slice operations."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01932arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc194.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc194.vhd
new file mode 100644
index 0000000..36b1d25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc194.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc194.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s00b00x00p11n01i00194ent IS
+END c03s00b00x00p11n01i00194ent;
+
+ARCHITECTURE c03s00b00x00p11n01i00194arch OF c03s00b00x00p11n01i00194ent IS
+  type       T1 is array (0 to 31) of BIT;
+  subtype    T2 is integer range 2 to 20;
+  signal    S1 : T2 ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= 15 after 10 ns; -- no_failure_here
+    wait for 20 ns;
+    assert NOT(S1 = 15)
+      report "***PASSED TEST: c03s00b00x00p11n01i00194"
+      severity NOTE;
+    assert ( S1 = 15 )
+      report "***FAILED TEST: c03s00b00x00p11n01i00194 - The assignment operation to an object having a given subtype only assigns values that belong to the subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s00b00x00p11n01i00194arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1942.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1942.vhd
new file mode 100644
index 0000000..669b3eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1942.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1942.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01942ent IS
+END c07s02b01x00p01n02i01942ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01942arch OF c07s02b01x00p01n02i01942ent IS
+  TYPE b4 IS ARRAY (1 TO 4) OF BOOLEAN;
+
+  CONSTANT T : BOOLEAN := TRUE;
+  CONSTANT F : BOOLEAN :=FALSE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+--
+--          Test operators on one-dimesioned arrays of BOOLEAN
+--
+    ASSERT ( b4'( T,T,F,F ) AND  b4'( T,F,T,F ) ) = b4'( T,F,F,F ) 
+      REPORT "ERROR: composite AND operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    ASSERT ( b4'( T,T,F,F )  OR  b4'( T,F,T,F ) ) = b4'( T,T,T,F ) 
+      REPORT "ERROR: composite  OR operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    ASSERT ( b4'( T,T,F,F ) NAND b4'( T,F,T,F ) ) = b4'( F,T,T,T ) 
+      REPORT "ERROR: composite NAND operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    ASSERT ( b4'( T,T,F,F ) NOR  b4'( T,F,T,F ) ) = b4'( F,F,F,T ) 
+      REPORT "ERROR: composite NOR operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    ASSERT ( b4'( T,T,F,F ) XOR  b4'( T,F,T,F ) ) = b4'( F,T,T,F ) 
+      REPORT "ERROR: composite XOR operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    ASSERT (                NOT  b4'( T,T,F,F ) ) = b4'( F,F,T,T ) 
+      REPORT "ERROR: composite NOT operator failed : BOOLEAN"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   (( b4'( T,T,F,F ) AND  b4'( T,F,T,F ) ) = b4'( T,F,F,F ))   and
+                  (( b4'( T,T,F,F )  OR  b4'( T,F,T,F ) ) = b4'( T,T,T,F ))   and
+                  (( b4'( T,T,F,F ) NAND b4'( T,F,T,F ) ) = b4'( F,T,T,T ))   and
+                  (( b4'( T,T,F,F ) NOR  b4'( T,F,T,F ) ) = b4'( F,F,F,T ))   and
+                  (( b4'( T,T,F,F ) XOR  b4'( T,F,T,F ) ) = b4'( F,T,T,F ))   and
+                  ((                NOT  b4'( T,T,F,F ) ) = b4'( F,F,T,T ))   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01942" 
+      severity NOTE;
+    assert (   (( b4'( T,T,F,F ) AND  b4'( T,F,T,F ) ) = b4'( T,F,F,F ))   and
+               (( b4'( T,T,F,F )  OR  b4'( T,F,T,F ) ) = b4'( T,T,T,F ))   and
+               (( b4'( T,T,F,F ) NAND b4'( T,F,T,F ) ) = b4'( F,T,T,T ))   and
+               (( b4'( T,T,F,F ) NOR  b4'( T,F,T,F ) ) = b4'( F,F,F,T ))   and
+               (( b4'( T,T,F,F ) XOR  b4'( T,F,T,F ) ) = b4'( F,T,T,F ))   and
+               ((                NOT  b4'( T,T,F,F ) ) = b4'( F,F,T,T ))   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01942 - Logical operators should be valid for any one-dimensional array type whose element type is BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01942arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1943.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1943.vhd
new file mode 100644
index 0000000..f2bf0bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1943.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1943.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n05i01943ent IS
+END c07s02b01x00p01n05i01943ent;
+
+ARCHITECTURE c07s02b01x00p01n05i01943arch OF c07s02b01x00p01n05i01943ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c07s02b01x00p01n05i01943"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c07s02b01x00p01n05i01943"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c07s02b01x00p01n05i01943arch;
+
+-- CONFIGURATION c07s02b01x00p01n05i01943cfg OF c07s02b01x00p01n05i01943ent IS
+--     FOR c07s02b01x00p01n05i01943arch
+--     END FOR;
+-- END c07s02b01x00p01n05i01943cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1944.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1944.vhd
new file mode 100644
index 0000000..9515a28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1944.vhd
@@ -0,0 +1,122 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1944.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01944ent IS
+END c07s02b01x00p01n04i01944ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01944arch OF c07s02b01x00p01n04i01944ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A : bit_vector (1 to 32);
+    variable B : bit_vector (32 downto 1);
+    constant AA : bit_vector (1 to 32) := x"0000ffff";
+    variable C : bit_vector (15 downto 0);
+    variable D, DD : bit_vector (0 to 15);
+    variable E : bit_vector (0 to 47);
+    variable F : bit_vector (47 downto 0);
+    alias FF : bit_vector (47 downto 0) is F;
+  BEGIN
+    
+    A := x"0000ffff";
+    B := x"00ff00ff";
+
+    C := x"00ff";
+    D := x"0f0f";
+
+    E := x"000000ffffff";
+    F := x"000fff000fff";
+
+    assert NOT(    (A and B ) = x"000000ff"   and
+                   (A or  B ) = x"00ffffff"   and
+                   (A xor B ) = x"00ffff00"   and
+                   (A nand B) = x"ffffff00"   and
+                   (A nor B ) = x"ff000000"   and
+                   (not A   ) = x"ffff0000"   and
+                   (AA and B ) = x"000000ff"   and
+                   (AA or  B ) = x"00ffffff"   and
+                   (AA xor B ) = x"00ffff00"   and
+                   (AA nand B) = x"ffffff00"   and
+                   (AA nor B ) = x"ff000000"   and
+                   (not AA   ) = x"ffff0000"   and
+                   (C and D ) = x"000f"   and
+                   (C or  D ) = x"0fff"   and
+                   (C xor D ) = x"0ff0"   and
+                   (C nand D) = x"fff0"   and
+                   (C nor D ) = x"f000"   and
+                   (not C   ) = x"ff00"   and
+                   (E and F ) = x"000000000fff"   and
+                   (E or  F ) = x"000fffffffff"   and
+                   (E xor F ) = x"000ffffff000"   and
+                   (E nand F) = x"fffffffff000"   and
+                   (E nor F ) = x"fff000000000"   and
+                   (E and FF ) = x"000000000fff"   and
+                   (E or  FF ) = x"000fffffffff"   and
+                   (E xor FF ) = x"000ffffff000"   and
+                   (E nand FF) = x"fffffffff000"   and
+                   (E nor FF ) = x"fff000000000"   and
+                   (not E   ) = x"ffffff000000")
+      report "***PASSED TEST: c07s02b01x00p01n04i01944" 
+      severity NOTE;
+    assert (    (A and B ) = x"000000ff"   and
+                (A or  B ) = x"00ffffff"   and
+                (A xor B ) = x"00ffff00"   and
+                (A nand B) = x"ffffff00"   and
+                (A nor B ) = x"ff000000"   and
+                (not A   ) = x"ffff0000"   and
+                (AA and B ) = x"000000ff"   and
+                (AA or  B ) = x"00ffffff"   and
+                (AA xor B ) = x"00ffff00"   and
+                (AA nand B) = x"ffffff00"   and
+                (AA nor B ) = x"ff000000"   and
+                (not AA   ) = x"ffff0000"   and
+                (C and D ) = x"000f"   and
+                (C or  D ) = x"0fff"   and
+                (C xor D ) = x"0ff0"   and
+                (C nand D) = x"fff0"   and
+                (C nor D ) = x"f000"   and
+                (not C   ) = x"ff00"   and
+                (E and F ) = x"000000000fff"   and
+                (E or  F ) = x"000fffffffff"   and
+                (E xor F ) = x"000ffffff000"   and
+                (E nand F) = x"fffffffff000"   and
+                (E nor F ) = x"fff000000000"   and
+                (E and FF ) = x"000000000fff"   and
+                (E or  FF ) = x"000fffffffff"   and
+                (E xor FF ) = x"000ffffff000"   and
+                (E nand FF) = x"fffffffff000"   and
+                (E nor FF ) = x"fff000000000"   and
+                (not E   ) = x"ffffff000000")
+      report "***FAILED TEST: c07s02b01x00p01n04i01944 - One dimensional array type logical operation failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01944arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1945.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1945.vhd
new file mode 100644
index 0000000..206571b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1945.vhd
@@ -0,0 +1,308 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1945.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01945pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- ----------------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01945pkg.all;
+ENTITY c07s02b01x00p01n02i01945ent IS
+END c07s02b01x00p01n02i01945ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01945arch OF c07s02b01x00p01n02i01945ent IS
+--
+--          CONSTANT Declarations
+--
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  CONSTANT  AND_C_csa1_1 : t_csa1_1          := ( '1', '0', '0', '0' );
+  CONSTANT  AND_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
+  
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  AND_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE, FALSE, FALSE );
+  CONSTANT  AND_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE, FALSE, FALSE );
+  
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  CONSTANT  AND_C_csa1_3 : t_csa1_3          := ( '1', '0', '0', '0' );
+  CONSTANT  AND_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  AND_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE, FALSE, FALSE );
+  CONSTANT  AND_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE, FALSE, FALSE );
+--
+--          SIGNAL Declarations
+--
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  SIGNAL  AND_S_csa1_1 : t_csa1_1          := ( '1', '0', '0', '0' );
+  SIGNAL  AND_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  AND_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE, FALSE, FALSE );
+  SIGNAL  AND_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE, FALSE, FALSE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  SIGNAL  AND_S_csa1_3 : t_csa1_3          := ( '1', '0', '0', '0' );
+  SIGNAL  AND_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  AND_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE, FALSE, FALSE );
+  SIGNAL  AND_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE, FALSE, FALSE );
+
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+    VARIABLE  AND_V_csa1_1 : t_csa1_1          := ( '1', '0', '0', '0' );
+    VARIABLE  AND_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '0', '0' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  AND_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE, FALSE, FALSE );
+    VARIABLE  AND_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE, FALSE, FALSE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+    VARIABLE  AND_V_csa1_3 : t_csa1_3          := ( '1', '0', '0', '0' );
+    VARIABLE  AND_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '0', '0' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  AND_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE, FALSE, FALSE );
+    VARIABLE  AND_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE, FALSE, FALSE );
+  BEGIN
+--
+--          Test AND operator on: CONSTANTs
+--
+    ASSERT ( ARGA_C_csa1_1 AND  ARGB_C_csa1_1 ) =  AND_C_csa1_1
+      REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_2 AND  ARGB_C_csa1_2 ) =  AND_C_csa1_2
+      REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_3 AND  ARGB_C_csa1_3 ) =  AND_C_csa1_3
+      REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_4 AND  ARGB_C_csa1_4 ) =  AND_C_csa1_4
+      REPORT "ERROR: composite AND operator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_1 AND  ARGB_C_usa1_1 ) =  AND_C_usa1_1
+      REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_2 AND  ARGB_C_usa1_2 ) =  AND_C_usa1_2
+      REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_3 AND  ARGB_C_usa1_3 ) =  AND_C_usa1_3
+      REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_4 AND  ARGB_C_usa1_4 ) =  AND_C_usa1_4
+      REPORT "ERROR: composite AND operator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test AND operator on: SIGNALs
+--
+    ASSERT ( ARGA_S_csa1_1 AND  ARGB_S_csa1_1 ) =  AND_S_csa1_1
+      REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_2 AND  ARGB_S_csa1_2 ) =  AND_S_csa1_2
+      REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_3 AND  ARGB_S_csa1_3 ) =  AND_S_csa1_3
+      REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_4 AND  ARGB_S_csa1_4 ) =  AND_S_csa1_4
+      REPORT "ERROR: composite AND operator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_1 AND  ARGB_S_usa1_1 ) =  AND_S_usa1_1
+      REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_2 AND  ARGB_S_usa1_2 ) =  AND_S_usa1_2
+      REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_3 AND  ARGB_S_usa1_3 ) =  AND_S_usa1_3
+      REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_4 AND  ARGB_S_usa1_4 ) =  AND_S_usa1_4
+      REPORT "ERROR: composite AND operator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test AND operator on: VARIABLEs
+--
+    ASSERT ( ARGA_V_csa1_1 AND  ARGB_V_csa1_1 ) =  AND_V_csa1_1
+      REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_2 AND  ARGB_V_csa1_2 ) =  AND_V_csa1_2
+      REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_3 AND  ARGB_V_csa1_3 ) =  AND_V_csa1_3
+      REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_4 AND  ARGB_V_csa1_4 ) =  AND_V_csa1_4
+      REPORT "ERROR: composite AND operator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_1 AND  ARGB_V_usa1_1 ) =  AND_V_usa1_1
+      REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_2 AND  ARGB_V_usa1_2 ) =  AND_V_usa1_2
+      REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_3 AND  ARGB_V_usa1_3 ) =  AND_V_usa1_3
+      REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_4 AND  ARGB_V_usa1_4 ) =  AND_V_usa1_4
+      REPORT "ERROR: composite AND operator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( ARGA_C_csa1_1 AND  ARGB_C_csa1_1 ) =  AND_C_csa1_1   and
+                  ( ARGA_C_csa1_2 AND  ARGB_C_csa1_2 ) =  AND_C_csa1_2   and
+                  ( ARGA_C_csa1_3 AND  ARGB_C_csa1_3 ) =  AND_C_csa1_3   and
+                  ( ARGA_C_csa1_4 AND  ARGB_C_csa1_4 ) =  AND_C_csa1_4   and
+                  ( ARGA_C_usa1_1 AND  ARGB_C_usa1_1 ) =  AND_C_usa1_1   and
+                  ( ARGA_C_usa1_2 AND  ARGB_C_usa1_2 ) =  AND_C_usa1_2   and
+                  ( ARGA_C_usa1_3 AND  ARGB_C_usa1_3 ) =  AND_C_usa1_3   and
+                  ( ARGA_C_usa1_4 AND  ARGB_C_usa1_4 ) =  AND_C_usa1_4   and
+                  ( ARGA_S_csa1_1 AND  ARGB_S_csa1_1 ) =  AND_S_csa1_1   and
+                  ( ARGA_S_csa1_2 AND  ARGB_S_csa1_2 ) =  AND_S_csa1_2   and
+                  ( ARGA_S_csa1_3 AND  ARGB_S_csa1_3 ) =  AND_S_csa1_3   and
+                  ( ARGA_S_csa1_4 AND  ARGB_S_csa1_4 ) =  AND_S_csa1_4   and
+                  ( ARGA_S_usa1_1 AND  ARGB_S_usa1_1 ) =  AND_S_usa1_1   and
+                  ( ARGA_S_usa1_2 AND  ARGB_S_usa1_2 ) =  AND_S_usa1_2   and
+                  ( ARGA_S_usa1_3 AND  ARGB_S_usa1_3 ) =  AND_S_usa1_3   and
+                  ( ARGA_S_usa1_4 AND  ARGB_S_usa1_4 ) =  AND_S_usa1_4   and
+                  ( ARGA_V_csa1_1 AND  ARGB_V_csa1_1 ) =  AND_V_csa1_1   and
+                  ( ARGA_V_csa1_2 AND  ARGB_V_csa1_2 ) =  AND_V_csa1_2   and
+                  ( ARGA_V_csa1_3 AND  ARGB_V_csa1_3 ) =  AND_V_csa1_3   and
+                  ( ARGA_V_csa1_4 AND  ARGB_V_csa1_4 ) =  AND_V_csa1_4   and
+                  ( ARGA_V_usa1_1 AND  ARGB_V_usa1_1 ) =  AND_V_usa1_1   and
+                  ( ARGA_V_usa1_2 AND  ARGB_V_usa1_2 ) =  AND_V_usa1_2   and
+                  ( ARGA_V_usa1_3 AND  ARGB_V_usa1_3 ) =  AND_V_usa1_3   and
+                  ( ARGA_V_usa1_4 AND  ARGB_V_usa1_4 ) =  AND_V_usa1_4   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01945" 
+      severity NOTE;
+    assert (   ( ARGA_C_csa1_1 AND  ARGB_C_csa1_1 ) =  AND_C_csa1_1   and
+               ( ARGA_C_csa1_2 AND  ARGB_C_csa1_2 ) =  AND_C_csa1_2   and
+               ( ARGA_C_csa1_3 AND  ARGB_C_csa1_3 ) =  AND_C_csa1_3   and
+               ( ARGA_C_csa1_4 AND  ARGB_C_csa1_4 ) =  AND_C_csa1_4   and
+               ( ARGA_C_usa1_1 AND  ARGB_C_usa1_1 ) =  AND_C_usa1_1   and
+               ( ARGA_C_usa1_2 AND  ARGB_C_usa1_2 ) =  AND_C_usa1_2   and
+               ( ARGA_C_usa1_3 AND  ARGB_C_usa1_3 ) =  AND_C_usa1_3   and
+               ( ARGA_C_usa1_4 AND  ARGB_C_usa1_4 ) =  AND_C_usa1_4   and
+               ( ARGA_S_csa1_1 AND  ARGB_S_csa1_1 ) =  AND_S_csa1_1   and
+               ( ARGA_S_csa1_2 AND  ARGB_S_csa1_2 ) =  AND_S_csa1_2   and
+               ( ARGA_S_csa1_3 AND  ARGB_S_csa1_3 ) =  AND_S_csa1_3   and
+               ( ARGA_S_csa1_4 AND  ARGB_S_csa1_4 ) =  AND_S_csa1_4   and
+               ( ARGA_S_usa1_1 AND  ARGB_S_usa1_1 ) =  AND_S_usa1_1   and
+               ( ARGA_S_usa1_2 AND  ARGB_S_usa1_2 ) =  AND_S_usa1_2   and
+               ( ARGA_S_usa1_3 AND  ARGB_S_usa1_3 ) =  AND_S_usa1_3   and
+               ( ARGA_S_usa1_4 AND  ARGB_S_usa1_4 ) =  AND_S_usa1_4   and
+               ( ARGA_V_csa1_1 AND  ARGB_V_csa1_1 ) =  AND_V_csa1_1   and
+               ( ARGA_V_csa1_2 AND  ARGB_V_csa1_2 ) =  AND_V_csa1_2   and
+               ( ARGA_V_csa1_3 AND  ARGB_V_csa1_3 ) =  AND_V_csa1_3   and
+               ( ARGA_V_csa1_4 AND  ARGB_V_csa1_4 ) =  AND_V_csa1_4   and
+               ( ARGA_V_usa1_1 AND  ARGB_V_usa1_1 ) =  AND_V_usa1_1   and
+               ( ARGA_V_usa1_2 AND  ARGB_V_usa1_2 ) =  AND_V_usa1_2   and
+               ( ARGA_V_usa1_3 AND  ARGB_V_usa1_3 ) =  AND_V_usa1_3   and
+               ( ARGA_V_usa1_4 AND  ARGB_V_usa1_4 ) =  AND_V_usa1_4   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01945 - Logical operator AND for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01945arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1946.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1946.vhd
new file mode 100644
index 0000000..ef01428
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1946.vhd
@@ -0,0 +1,309 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1946.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01946pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- -----------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01946pkg.all;
+ENTITY c07s02b01x00p01n02i01946ent IS
+END c07s02b01x00p01n02i01946ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01946arch OF c07s02b01x00p01n02i01946ent IS
+--
+--          CONSTANT Declarations
+--
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  CONSTANT   OR_C_csa1_1 : t_csa1_1          := ( '1', '1', '1', '0' );
+  CONSTANT   OR_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '1', '0' );
+  
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT   OR_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE,  TRUE, FALSE );
+  CONSTANT   OR_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE,  TRUE, FALSE );
+  
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  CONSTANT   OR_C_csa1_3 : t_csa1_3          := ( '1', '1', '1', '0' );
+  CONSTANT   OR_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '1', '0' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT   OR_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE,  TRUE, FALSE );
+  CONSTANT   OR_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE,  TRUE, FALSE );
+
+--
+--          SIGNAL Declarations
+--
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  SIGNAL   OR_S_csa1_1 : t_csa1_1          := ( '1', '1', '1', '0' );
+  SIGNAL   OR_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '1', '0' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL   OR_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE,  TRUE, FALSE );
+  SIGNAL   OR_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE,  TRUE, FALSE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  SIGNAL   OR_S_csa1_3 : t_csa1_3          := ( '1', '1', '1', '0' );
+  SIGNAL   OR_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '1', '0' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL   OR_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE,  TRUE, FALSE );
+  SIGNAL   OR_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE,  TRUE, FALSE );
+
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+    VARIABLE   OR_V_csa1_1 : t_csa1_1          := ( '1', '1', '1', '0' );
+    VARIABLE   OR_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '1', '0' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE   OR_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE,  TRUE, FALSE );
+    VARIABLE   OR_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE,  TRUE, FALSE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+    VARIABLE   OR_V_csa1_3 : t_csa1_3          := ( '1', '1', '1', '0' );
+    VARIABLE   OR_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '1', '0' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE   OR_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE,  TRUE, FALSE );
+    VARIABLE   OR_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE,  TRUE, FALSE );
+  BEGIN
+--
+--          Test OR operator on: CONSTANTs
+--
+    ASSERT ( ARGA_C_csa1_1 OR  ARGB_C_csa1_1 ) =  OR_C_csa1_1
+      REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_2 OR  ARGB_C_csa1_2 ) =  OR_C_csa1_2
+      REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_3 OR  ARGB_C_csa1_3 ) =  OR_C_csa1_3
+      REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_4 OR  ARGB_C_csa1_4 ) =  OR_C_csa1_4
+      REPORT "ERROR: composite OR operator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_1 OR  ARGB_C_usa1_1 ) =  OR_C_usa1_1
+      REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_2 OR  ARGB_C_usa1_2 ) =  OR_C_usa1_2
+      REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_3 OR  ARGB_C_usa1_3 ) =  OR_C_usa1_3
+      REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_4 OR  ARGB_C_usa1_4 ) =  OR_C_usa1_4
+      REPORT "ERROR: composite OR operator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test OR operator on: SIGNALs
+--
+    ASSERT ( ARGA_S_csa1_1 OR  ARGB_S_csa1_1 ) =  OR_S_csa1_1
+      REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_2 OR  ARGB_S_csa1_2 ) =  OR_S_csa1_2
+      REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_3 OR  ARGB_S_csa1_3 ) =  OR_S_csa1_3
+      REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_4 OR  ARGB_S_csa1_4 ) =  OR_S_csa1_4
+      REPORT "ERROR: composite OR operator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_1 OR  ARGB_S_usa1_1 ) =  OR_S_usa1_1
+      REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_2 OR  ARGB_S_usa1_2 ) =  OR_S_usa1_2
+      REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_3 OR  ARGB_S_usa1_3 ) =  OR_S_usa1_3
+      REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_4 OR  ARGB_S_usa1_4 ) =  OR_S_usa1_4
+      REPORT "ERROR: composite OR operator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test OR operator on: VARIABLEs
+--
+    ASSERT ( ARGA_V_csa1_1 OR  ARGB_V_csa1_1 ) =  OR_V_csa1_1
+      REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_2 OR  ARGB_V_csa1_2 ) =  OR_V_csa1_2
+      REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_3 OR  ARGB_V_csa1_3 ) =  OR_V_csa1_3
+      REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_4 OR  ARGB_V_csa1_4 ) =  OR_V_csa1_4
+      REPORT "ERROR: composite OR operator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_1 OR  ARGB_V_usa1_1 ) =  OR_V_usa1_1
+      REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_2 OR  ARGB_V_usa1_2 ) =  OR_V_usa1_2
+      REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_3 OR  ARGB_V_usa1_3 ) =  OR_V_usa1_3
+      REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_4 OR  ARGB_V_usa1_4 ) =  OR_V_usa1_4
+      REPORT "ERROR: composite OR operator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( ARGA_C_csa1_1 OR  ARGB_C_csa1_1 ) =  OR_C_csa1_1   and
+                  ( ARGA_C_csa1_2 OR  ARGB_C_csa1_2 ) =  OR_C_csa1_2   and
+                  ( ARGA_C_csa1_3 OR  ARGB_C_csa1_3 ) =  OR_C_csa1_3   and
+                  ( ARGA_C_csa1_4 OR  ARGB_C_csa1_4 ) =  OR_C_csa1_4   and
+                  ( ARGA_C_usa1_1 OR  ARGB_C_usa1_1 ) =  OR_C_usa1_1   and
+                  ( ARGA_C_usa1_2 OR  ARGB_C_usa1_2 ) =  OR_C_usa1_2   and
+                  ( ARGA_C_usa1_3 OR  ARGB_C_usa1_3 ) =  OR_C_usa1_3   and
+                  ( ARGA_C_usa1_4 OR  ARGB_C_usa1_4 ) =  OR_C_usa1_4   and   
+                  ( ARGA_S_csa1_1 OR  ARGB_S_csa1_1 ) =  OR_S_csa1_1   and
+                  ( ARGA_S_csa1_2 OR  ARGB_S_csa1_2 ) =  OR_S_csa1_2   and
+                  ( ARGA_S_csa1_3 OR  ARGB_S_csa1_3 ) =  OR_S_csa1_3   and
+                  ( ARGA_S_csa1_4 OR  ARGB_S_csa1_4 ) =  OR_S_csa1_4   and
+                  ( ARGA_S_usa1_1 OR  ARGB_S_usa1_1 ) =  OR_S_usa1_1   and
+                  ( ARGA_S_usa1_2 OR  ARGB_S_usa1_2 ) =  OR_S_usa1_2   and
+                  ( ARGA_S_usa1_3 OR  ARGB_S_usa1_3 ) =  OR_S_usa1_3   and
+                  ( ARGA_S_usa1_4 OR  ARGB_S_usa1_4 ) =  OR_S_usa1_4   and
+                  ( ARGA_V_csa1_1 OR  ARGB_V_csa1_1 ) =  OR_V_csa1_1   and
+                  ( ARGA_V_csa1_2 OR  ARGB_V_csa1_2 ) =  OR_V_csa1_2   and
+                  ( ARGA_V_csa1_3 OR  ARGB_V_csa1_3 ) =  OR_V_csa1_3   and
+                  ( ARGA_V_csa1_4 OR  ARGB_V_csa1_4 ) =  OR_V_csa1_4   and
+                  ( ARGA_V_usa1_1 OR  ARGB_V_usa1_1 ) =  OR_V_usa1_1   and
+                  ( ARGA_V_usa1_2 OR  ARGB_V_usa1_2 ) =  OR_V_usa1_2   and
+                  ( ARGA_V_usa1_3 OR  ARGB_V_usa1_3 ) =  OR_V_usa1_3   and
+                  ( ARGA_V_usa1_4 OR  ARGB_V_usa1_4 ) =  OR_V_usa1_4   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01946" 
+      severity NOTE;
+    assert (   ( ARGA_C_csa1_1 OR  ARGB_C_csa1_1 ) =  OR_C_csa1_1   and
+               ( ARGA_C_csa1_2 OR  ARGB_C_csa1_2 ) =  OR_C_csa1_2   and
+               ( ARGA_C_csa1_3 OR  ARGB_C_csa1_3 ) =  OR_C_csa1_3   and
+               ( ARGA_C_csa1_4 OR  ARGB_C_csa1_4 ) =  OR_C_csa1_4   and
+               ( ARGA_C_usa1_1 OR  ARGB_C_usa1_1 ) =  OR_C_usa1_1   and
+               ( ARGA_C_usa1_2 OR  ARGB_C_usa1_2 ) =  OR_C_usa1_2   and
+               ( ARGA_C_usa1_3 OR  ARGB_C_usa1_3 ) =  OR_C_usa1_3   and
+               ( ARGA_C_usa1_4 OR  ARGB_C_usa1_4 ) =  OR_C_usa1_4   and   
+               ( ARGA_S_csa1_1 OR  ARGB_S_csa1_1 ) =  OR_S_csa1_1   and
+               ( ARGA_S_csa1_2 OR  ARGB_S_csa1_2 ) =  OR_S_csa1_2   and
+               ( ARGA_S_csa1_3 OR  ARGB_S_csa1_3 ) =  OR_S_csa1_3   and
+               ( ARGA_S_csa1_4 OR  ARGB_S_csa1_4 ) =  OR_S_csa1_4   and
+               ( ARGA_S_usa1_1 OR  ARGB_S_usa1_1 ) =  OR_S_usa1_1   and
+               ( ARGA_S_usa1_2 OR  ARGB_S_usa1_2 ) =  OR_S_usa1_2   and
+               ( ARGA_S_usa1_3 OR  ARGB_S_usa1_3 ) =  OR_S_usa1_3   and
+               ( ARGA_S_usa1_4 OR  ARGB_S_usa1_4 ) =  OR_S_usa1_4   and
+               ( ARGA_V_csa1_1 OR  ARGB_V_csa1_1 ) =  OR_V_csa1_1   and
+               ( ARGA_V_csa1_2 OR  ARGB_V_csa1_2 ) =  OR_V_csa1_2   and
+               ( ARGA_V_csa1_3 OR  ARGB_V_csa1_3 ) =  OR_V_csa1_3   and
+               ( ARGA_V_csa1_4 OR  ARGB_V_csa1_4 ) =  OR_V_csa1_4   and
+               ( ARGA_V_usa1_1 OR  ARGB_V_usa1_1 ) =  OR_V_usa1_1   and
+               ( ARGA_V_usa1_2 OR  ARGB_V_usa1_2 ) =  OR_V_usa1_2   and
+               ( ARGA_V_usa1_3 OR  ARGB_V_usa1_3 ) =  OR_V_usa1_3   and
+               ( ARGA_V_usa1_4 OR  ARGB_V_usa1_4 ) =  OR_V_usa1_4   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01946 - Logical operator OR for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01946arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1947.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1947.vhd
new file mode 100644
index 0000000..f1923bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1947.vhd
@@ -0,0 +1,309 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1947.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01947pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- -----------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01947pkg.all;
+ENTITY c07s02b01x00p01n02i01947ent IS
+END c07s02b01x00p01n02i01947ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01947arch OF c07s02b01x00p01n02i01947ent IS
+--
+--          CONSTANT Declarations
+--
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  CONSTANT NAND_C_csa1_1 : t_csa1_1          := ( '0', '1', '1', '1' );
+  CONSTANT NAND_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
+  
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT NAND_C_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE,  TRUE );
+  CONSTANT NAND_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE,  TRUE );
+  
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  CONSTANT NAND_C_csa1_3 : t_csa1_3          := ( '0', '1', '1', '1' );
+  CONSTANT NAND_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT NAND_C_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE,  TRUE );
+  CONSTANT NAND_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE,  TRUE );
+--
+--          SIGNAL Declarations
+--
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  SIGNAL NAND_S_csa1_1 : t_csa1_1          := ( '0', '1', '1', '1' );
+  SIGNAL NAND_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL NAND_S_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE,  TRUE );
+  SIGNAL NAND_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE,  TRUE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  SIGNAL NAND_S_csa1_3 : t_csa1_3          := ( '0', '1', '1', '1' );
+  SIGNAL NAND_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL NAND_S_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE,  TRUE );
+  SIGNAL NAND_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE,  TRUE );
+
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+    VARIABLE NAND_V_csa1_1 : t_csa1_1          := ( '0', '1', '1', '1' );
+    VARIABLE NAND_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '1' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE NAND_V_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE,  TRUE );
+    VARIABLE NAND_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE,  TRUE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+    VARIABLE NAND_V_csa1_3 : t_csa1_3          := ( '0', '1', '1', '1' );
+    VARIABLE NAND_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '1' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE NAND_V_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE,  TRUE );
+    VARIABLE NAND_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE,  TRUE );
+
+  BEGIN
+--
+--          Test NANDoperator on: CONSTANTs
+--
+    ASSERT ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4
+      REPORT "ERROR: composite NANDoperator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NANDoperator on: SIGNALs
+--
+    ASSERT ( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4
+      REPORT "ERROR: composite NANDoperator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NANDoperator on: VARIABLEs
+--
+    ASSERT ( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4
+      REPORT "ERROR: composite NANDoperator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1   and
+                  ( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2   and
+                  ( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3   and
+                  ( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4   and
+                  ( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1   and
+                  ( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2   and
+                  ( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3   and
+                  ( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4   and
+                  ( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1   and
+                  ( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2   and
+                  ( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3   and
+                  ( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4   and
+                  ( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1   and
+                  ( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2   and
+                  ( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3   and
+                  ( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4   and
+                  ( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1   and
+                  ( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2   and
+                  ( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3   and
+                  ( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4   and
+                  ( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1   and
+                  ( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2   and
+                  ( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3   and
+                  ( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01947" 
+      severity NOTE;
+    assert (   ( ARGA_C_csa1_1 NAND ARGB_C_csa1_1 ) = NAND_C_csa1_1   and
+               ( ARGA_C_csa1_2 NAND ARGB_C_csa1_2 ) = NAND_C_csa1_2   and
+               ( ARGA_C_csa1_3 NAND ARGB_C_csa1_3 ) = NAND_C_csa1_3   and
+               ( ARGA_C_csa1_4 NAND ARGB_C_csa1_4 ) = NAND_C_csa1_4   and
+               ( ARGA_C_usa1_1 NAND ARGB_C_usa1_1 ) = NAND_C_usa1_1   and
+               ( ARGA_C_usa1_2 NAND ARGB_C_usa1_2 ) = NAND_C_usa1_2   and
+               ( ARGA_C_usa1_3 NAND ARGB_C_usa1_3 ) = NAND_C_usa1_3   and
+               ( ARGA_C_usa1_4 NAND ARGB_C_usa1_4 ) = NAND_C_usa1_4   and
+               ( ARGA_S_csa1_1 NAND ARGB_S_csa1_1 ) = NAND_S_csa1_1   and
+               ( ARGA_S_csa1_2 NAND ARGB_S_csa1_2 ) = NAND_S_csa1_2   and
+               ( ARGA_S_csa1_3 NAND ARGB_S_csa1_3 ) = NAND_S_csa1_3   and
+               ( ARGA_S_csa1_4 NAND ARGB_S_csa1_4 ) = NAND_S_csa1_4   and
+               ( ARGA_S_usa1_1 NAND ARGB_S_usa1_1 ) = NAND_S_usa1_1   and
+               ( ARGA_S_usa1_2 NAND ARGB_S_usa1_2 ) = NAND_S_usa1_2   and
+               ( ARGA_S_usa1_3 NAND ARGB_S_usa1_3 ) = NAND_S_usa1_3   and
+               ( ARGA_S_usa1_4 NAND ARGB_S_usa1_4 ) = NAND_S_usa1_4   and
+               ( ARGA_V_csa1_1 NAND ARGB_V_csa1_1 ) = NAND_V_csa1_1   and
+               ( ARGA_V_csa1_2 NAND ARGB_V_csa1_2 ) = NAND_V_csa1_2   and
+               ( ARGA_V_csa1_3 NAND ARGB_V_csa1_3 ) = NAND_V_csa1_3   and
+               ( ARGA_V_csa1_4 NAND ARGB_V_csa1_4 ) = NAND_V_csa1_4   and
+               ( ARGA_V_usa1_1 NAND ARGB_V_usa1_1 ) = NAND_V_usa1_1   and
+               ( ARGA_V_usa1_2 NAND ARGB_V_usa1_2 ) = NAND_V_usa1_2   and
+               ( ARGA_V_usa1_3 NAND ARGB_V_usa1_3 ) = NAND_V_usa1_3   and
+               ( ARGA_V_usa1_4 NAND ARGB_V_usa1_4 ) = NAND_V_usa1_4   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01947 - Logical operator NAND for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01947arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1948.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1948.vhd
new file mode 100644
index 0000000..70490e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1948.vhd
@@ -0,0 +1,308 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1948.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01948pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- -----------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01948pkg.all;
+ENTITY c07s02b01x00p01n02i01948ent IS
+END c07s02b01x00p01n02i01948ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01948arch OF c07s02b01x00p01n02i01948ent IS
+--
+--          CONSTANT Declarations
+--
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  CONSTANT  NOR_C_csa1_1 : t_csa1_1          := ( '0', '0', '0', '1' );
+  CONSTANT  NOR_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
+  
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  NOR_C_csa1_2 : t_csa1_2          := ( FALSE, FALSE, FALSE,  TRUE );
+  CONSTANT  NOR_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE,  TRUE );
+  
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  CONSTANT ARGB_C_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  CONSTANT  NOR_C_csa1_3 : t_csa1_3          := ( '0', '0', '0', '1' );
+  CONSTANT  NOR_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  NOR_C_csa1_4 : t_csa1_4          := ( FALSE, FALSE, FALSE,  TRUE );
+  CONSTANT  NOR_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE,  TRUE );
+--
+--          SIGNAL Declarations
+--
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  SIGNAL  NOR_S_csa1_1 : t_csa1_1          := ( '0', '0', '0', '1' );
+  SIGNAL  NOR_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  NOR_S_csa1_2 : t_csa1_2          := ( FALSE, FALSE, FALSE,  TRUE );
+  SIGNAL  NOR_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE,  TRUE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  SIGNAL  NOR_S_csa1_3 : t_csa1_3          := ( '0', '0', '0', '1' );
+  SIGNAL  NOR_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  NOR_S_csa1_4 : t_csa1_4          := ( FALSE, FALSE, FALSE,  TRUE );
+  SIGNAL  NOR_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE,  TRUE );
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+    VARIABLE  NOR_V_csa1_1 : t_csa1_1          := ( '0', '0', '0', '1' );
+    VARIABLE  NOR_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '0', '1' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  NOR_V_csa1_2 : t_csa1_2          := ( FALSE, FALSE, FALSE,  TRUE );
+    VARIABLE  NOR_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE, FALSE,  TRUE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+    VARIABLE  NOR_V_csa1_3 : t_csa1_3          := ( '0', '0', '0', '1' );
+    VARIABLE  NOR_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '0', '1' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  NOR_V_csa1_4 : t_csa1_4          := ( FALSE, FALSE, FALSE,  TRUE );
+    VARIABLE  NOR_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE, FALSE,  TRUE ); 
+
+  BEGIN
+--
+--          Test NOR operator on: CONSTANTs
+--
+    ASSERT ( ARGA_C_csa1_1 NOR  ARGB_C_csa1_1 ) =  NOR_C_csa1_1
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_2 NOR  ARGB_C_csa1_2 ) =  NOR_C_csa1_2
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_3 NOR  ARGB_C_csa1_3 ) =  NOR_C_csa1_3
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_4 NOR  ARGB_C_csa1_4 ) =  NOR_C_csa1_4
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_1 NOR  ARGB_C_usa1_1 ) =  NOR_C_usa1_1
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_2 NOR  ARGB_C_usa1_2 ) =  NOR_C_usa1_2
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_3 NOR  ARGB_C_usa1_3 ) =  NOR_C_usa1_3
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_4 NOR  ARGB_C_usa1_4 ) =  NOR_C_usa1_4
+      REPORT "ERROR: composite NOR operator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NOR operator on: SIGNALs
+--
+    ASSERT ( ARGA_S_csa1_1 NOR  ARGB_S_csa1_1 ) =  NOR_S_csa1_1
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_2 NOR  ARGB_S_csa1_2 ) =  NOR_S_csa1_2
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_3 NOR  ARGB_S_csa1_3 ) =  NOR_S_csa1_3
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_4 NOR  ARGB_S_csa1_4 ) =  NOR_S_csa1_4
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_1 NOR  ARGB_S_usa1_1 ) =  NOR_S_usa1_1
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_2 NOR  ARGB_S_usa1_2 ) =  NOR_S_usa1_2
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_3 NOR  ARGB_S_usa1_3 ) =  NOR_S_usa1_3
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_4 NOR  ARGB_S_usa1_4 ) =  NOR_S_usa1_4
+      REPORT "ERROR: composite NOR operator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NOR operator on: VARIABLEs
+--
+    ASSERT ( ARGA_V_csa1_1 NOR  ARGB_V_csa1_1 ) =  NOR_V_csa1_1
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_2 NOR  ARGB_V_csa1_2 ) =  NOR_V_csa1_2
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_3 NOR  ARGB_V_csa1_3 ) =  NOR_V_csa1_3
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_4 NOR  ARGB_V_csa1_4 ) =  NOR_V_csa1_4
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_1 NOR  ARGB_V_usa1_1 ) =  NOR_V_usa1_1
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_2 NOR  ARGB_V_usa1_2 ) =  NOR_V_usa1_2
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_3 NOR  ARGB_V_usa1_3 ) =  NOR_V_usa1_3
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_4 NOR  ARGB_V_usa1_4 ) =  NOR_V_usa1_4
+      REPORT "ERROR: composite NOR operator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( ARGA_C_csa1_1 NOR  ARGB_C_csa1_1 ) =  NOR_C_csa1_1   and
+                  ( ARGA_C_csa1_2 NOR  ARGB_C_csa1_2 ) =  NOR_C_csa1_2   and
+                  ( ARGA_C_csa1_3 NOR  ARGB_C_csa1_3 ) =  NOR_C_csa1_3   and
+                  ( ARGA_C_csa1_4 NOR  ARGB_C_csa1_4 ) =  NOR_C_csa1_4   and
+                  ( ARGA_C_usa1_1 NOR  ARGB_C_usa1_1 ) =  NOR_C_usa1_1   and
+                  ( ARGA_C_usa1_2 NOR  ARGB_C_usa1_2 ) =  NOR_C_usa1_2   and
+                  ( ARGA_C_usa1_3 NOR  ARGB_C_usa1_3 ) =  NOR_C_usa1_3   and
+                  ( ARGA_C_usa1_4 NOR  ARGB_C_usa1_4 ) =  NOR_C_usa1_4   and
+                  ( ARGA_S_csa1_1 NOR  ARGB_S_csa1_1 ) =  NOR_S_csa1_1   and
+                  ( ARGA_S_csa1_2 NOR  ARGB_S_csa1_2 ) =  NOR_S_csa1_2   and
+                  ( ARGA_S_csa1_3 NOR  ARGB_S_csa1_3 ) =  NOR_S_csa1_3   and
+                  ( ARGA_S_csa1_4 NOR  ARGB_S_csa1_4 ) =  NOR_S_csa1_4   and
+                  ( ARGA_S_usa1_1 NOR  ARGB_S_usa1_1 ) =  NOR_S_usa1_1   and
+                  ( ARGA_S_usa1_2 NOR  ARGB_S_usa1_2 ) =  NOR_S_usa1_2   and
+                  ( ARGA_S_usa1_3 NOR  ARGB_S_usa1_3 ) =  NOR_S_usa1_3   and
+                  ( ARGA_S_usa1_4 NOR  ARGB_S_usa1_4 ) =  NOR_S_usa1_4   and
+                  ( ARGA_V_csa1_1 NOR  ARGB_V_csa1_1 ) =  NOR_V_csa1_1   and
+                  ( ARGA_V_csa1_2 NOR  ARGB_V_csa1_2 ) =  NOR_V_csa1_2   and
+                  ( ARGA_V_csa1_3 NOR  ARGB_V_csa1_3 ) =  NOR_V_csa1_3   and
+                  ( ARGA_V_csa1_4 NOR  ARGB_V_csa1_4 ) =  NOR_V_csa1_4   and
+                  ( ARGA_V_usa1_1 NOR  ARGB_V_usa1_1 ) =  NOR_V_usa1_1   and
+                  ( ARGA_V_usa1_2 NOR  ARGB_V_usa1_2 ) =  NOR_V_usa1_2   and
+                  ( ARGA_V_usa1_3 NOR  ARGB_V_usa1_3 ) =  NOR_V_usa1_3   and
+                  ( ARGA_V_usa1_4 NOR  ARGB_V_usa1_4 ) =  NOR_V_usa1_4   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01948" 
+      severity NOTE;
+    assert (   ( ARGA_C_csa1_1 NOR  ARGB_C_csa1_1 ) =  NOR_C_csa1_1   and
+               ( ARGA_C_csa1_2 NOR  ARGB_C_csa1_2 ) =  NOR_C_csa1_2   and
+               ( ARGA_C_csa1_3 NOR  ARGB_C_csa1_3 ) =  NOR_C_csa1_3   and
+               ( ARGA_C_csa1_4 NOR  ARGB_C_csa1_4 ) =  NOR_C_csa1_4   and
+               ( ARGA_C_usa1_1 NOR  ARGB_C_usa1_1 ) =  NOR_C_usa1_1   and
+               ( ARGA_C_usa1_2 NOR  ARGB_C_usa1_2 ) =  NOR_C_usa1_2   and
+               ( ARGA_C_usa1_3 NOR  ARGB_C_usa1_3 ) =  NOR_C_usa1_3   and
+               ( ARGA_C_usa1_4 NOR  ARGB_C_usa1_4 ) =  NOR_C_usa1_4   and
+               ( ARGA_S_csa1_1 NOR  ARGB_S_csa1_1 ) =  NOR_S_csa1_1   and
+               ( ARGA_S_csa1_2 NOR  ARGB_S_csa1_2 ) =  NOR_S_csa1_2   and
+               ( ARGA_S_csa1_3 NOR  ARGB_S_csa1_3 ) =  NOR_S_csa1_3   and
+               ( ARGA_S_csa1_4 NOR  ARGB_S_csa1_4 ) =  NOR_S_csa1_4   and
+               ( ARGA_S_usa1_1 NOR  ARGB_S_usa1_1 ) =  NOR_S_usa1_1   and
+               ( ARGA_S_usa1_2 NOR  ARGB_S_usa1_2 ) =  NOR_S_usa1_2   and
+               ( ARGA_S_usa1_3 NOR  ARGB_S_usa1_3 ) =  NOR_S_usa1_3   and
+               ( ARGA_S_usa1_4 NOR  ARGB_S_usa1_4 ) =  NOR_S_usa1_4   and
+               ( ARGA_V_csa1_1 NOR  ARGB_V_csa1_1 ) =  NOR_V_csa1_1   and
+               ( ARGA_V_csa1_2 NOR  ARGB_V_csa1_2 ) =  NOR_V_csa1_2   and
+               ( ARGA_V_csa1_3 NOR  ARGB_V_csa1_3 ) =  NOR_V_csa1_3   and
+               ( ARGA_V_csa1_4 NOR  ARGB_V_csa1_4 ) =  NOR_V_csa1_4   and
+               ( ARGA_V_usa1_1 NOR  ARGB_V_usa1_1 ) =  NOR_V_usa1_1   and
+               ( ARGA_V_usa1_2 NOR  ARGB_V_usa1_2 ) =  NOR_V_usa1_2   and
+               ( ARGA_V_usa1_3 NOR  ARGB_V_usa1_3 ) =  NOR_V_usa1_3   and
+               ( ARGA_V_usa1_4 NOR  ARGB_V_usa1_4 ) =  NOR_V_usa1_4   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01948 - Logical operator NOR for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01948arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1949.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1949.vhd
new file mode 100644
index 0000000..0639833
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1949.vhd
@@ -0,0 +1,307 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1949.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01949pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- -----------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01949pkg.all;
+ENTITY c07s02b01x00p01n02i01949ent IS
+END c07s02b01x00p01n02i01949ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01949arch OF c07s02b01x00p01n02i01949ent IS
+--
+--          CONSTANT Declarations
+-- 
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' ); 
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' ); 
+  CONSTANT ARGB_C_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' ); 
+  CONSTANT ARGB_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' ); 
+  CONSTANT  XOR_C_csa1_1 : t_csa1_1          := ( '0', '1', '1', '0' ); 
+  CONSTANT  XOR_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '0' );
+  
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  XOR_C_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE, FALSE );
+  CONSTANT  XOR_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE, FALSE );
+  
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' ); 
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' ); 
+  CONSTANT ARGB_C_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' ); 
+  CONSTANT ARGB_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' ); 
+  CONSTANT  XOR_C_csa1_3 : t_csa1_3          := ( '0', '1', '1', '0' ); 
+  CONSTANT  XOR_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '0' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGB_C_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT ARGB_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  CONSTANT  XOR_C_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE, FALSE );
+  CONSTANT  XOR_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE, FALSE );
+-- 
+--          SIGNAL Declarations
+-- 
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );   
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+  SIGNAL  XOR_S_csa1_1 : t_csa1_1          := ( '0', '1', '1', '0' );
+  SIGNAL  XOR_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '0' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  XOR_S_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE, FALSE );
+  SIGNAL  XOR_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE, FALSE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL ARGB_S_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+  SIGNAL ARGB_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+  SIGNAL  XOR_S_csa1_3 : t_csa1_3          := ( '0', '1', '1', '0' );
+  SIGNAL  XOR_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '0' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGB_S_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL ARGB_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+  SIGNAL  XOR_S_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE, FALSE );
+  SIGNAL  XOR_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE, FALSE );
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_1 : t_csa1_1          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '0', '1', '0' );
+    VARIABLE  XOR_V_csa1_1 : t_csa1_1          := ( '0', '1', '1', '0' );
+    VARIABLE  XOR_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '1', '1', '0' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_2 : t_csa1_2          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  XOR_V_csa1_2 : t_csa1_2          := ( FALSE,  TRUE,  TRUE, FALSE );
+    VARIABLE  XOR_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE,  TRUE,  TRUE, FALSE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE ARGB_V_csa1_3 : t_csa1_3          := ( '1', '0', '1', '0' );
+    VARIABLE ARGB_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '0', '1', '0' );
+    VARIABLE  XOR_V_csa1_3 : t_csa1_3          := ( '0', '1', '1', '0' );
+    VARIABLE  XOR_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '1', '1', '0' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGB_V_csa1_4 : t_csa1_4          := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE ARGB_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE, FALSE,  TRUE, FALSE );
+    VARIABLE  XOR_V_csa1_4 : t_csa1_4          := ( FALSE,  TRUE,  TRUE, FALSE );
+    VARIABLE  XOR_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE,  TRUE,  TRUE, FALSE );
+  BEGIN
+--
+--          Test XOR operator on: CONSTANTs
+--
+    ASSERT ( ARGA_C_csa1_1 XOR  ARGB_C_csa1_1 ) =  XOR_C_csa1_1
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_2 XOR  ARGB_C_csa1_2 ) =  XOR_C_csa1_2
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_3 XOR  ARGB_C_csa1_3 ) =  XOR_C_csa1_3
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_csa1_4 XOR  ARGB_C_csa1_4 ) =  XOR_C_csa1_4
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_1 XOR  ARGB_C_usa1_1 ) =  XOR_C_usa1_1
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_2 XOR  ARGB_C_usa1_2 ) =  XOR_C_usa1_2
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_3 XOR  ARGB_C_usa1_3 ) =  XOR_C_usa1_3
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_C_usa1_4 XOR  ARGB_C_usa1_4 ) =  XOR_C_usa1_4
+      REPORT "ERROR: composite XOR operator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test XOR operator on: SIGNALs
+--
+    ASSERT ( ARGA_S_csa1_1 XOR  ARGB_S_csa1_1 ) =  XOR_S_csa1_1
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_2 XOR  ARGB_S_csa1_2 ) =  XOR_S_csa1_2
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_3 XOR  ARGB_S_csa1_3 ) =  XOR_S_csa1_3
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_csa1_4 XOR  ARGB_S_csa1_4 ) =  XOR_S_csa1_4
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_1 XOR  ARGB_S_usa1_1 ) =  XOR_S_usa1_1
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_2 XOR  ARGB_S_usa1_2 ) =  XOR_S_usa1_2
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_3 XOR  ARGB_S_usa1_3 ) =  XOR_S_usa1_3
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_S_usa1_4 XOR  ARGB_S_usa1_4 ) =  XOR_S_usa1_4
+      REPORT "ERROR: composite XOR operator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test XOR operator on: VARIABLEs
+--
+    ASSERT ( ARGA_V_csa1_1 XOR  ARGB_V_csa1_1 ) =  XOR_V_csa1_1
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_2 XOR  ARGB_V_csa1_2 ) =  XOR_V_csa1_2
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_3 XOR  ARGB_V_csa1_3 ) =  XOR_V_csa1_3
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_csa1_4 XOR  ARGB_V_csa1_4 ) =  XOR_V_csa1_4
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_1 XOR  ARGB_V_usa1_1 ) =  XOR_V_usa1_1
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_2 XOR  ARGB_V_usa1_2 ) =  XOR_V_usa1_2
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_3 XOR  ARGB_V_usa1_3 ) =  XOR_V_usa1_3
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( ARGA_V_usa1_4 XOR  ARGB_V_usa1_4 ) =  XOR_V_usa1_4
+      REPORT "ERROR: composite XOR operator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( ARGA_C_csa1_1 XOR  ARGB_C_csa1_1 ) =  XOR_C_csa1_1   and
+                  ( ARGA_C_csa1_2 XOR  ARGB_C_csa1_2 ) =  XOR_C_csa1_2   and
+                  ( ARGA_C_csa1_3 XOR  ARGB_C_csa1_3 ) =  XOR_C_csa1_3   and
+                  ( ARGA_C_csa1_4 XOR  ARGB_C_csa1_4 ) =  XOR_C_csa1_4   and
+                  ( ARGA_C_usa1_1 XOR  ARGB_C_usa1_1 ) =  XOR_C_usa1_1   and
+                  ( ARGA_C_usa1_2 XOR  ARGB_C_usa1_2 ) =  XOR_C_usa1_2   and
+                  ( ARGA_C_usa1_3 XOR  ARGB_C_usa1_3 ) =  XOR_C_usa1_3   and
+                  ( ARGA_C_usa1_4 XOR  ARGB_C_usa1_4 ) =  XOR_C_usa1_4   and
+                  ( ARGA_S_csa1_1 XOR  ARGB_S_csa1_1 ) =  XOR_S_csa1_1   and
+                  ( ARGA_S_csa1_2 XOR  ARGB_S_csa1_2 ) =  XOR_S_csa1_2   and
+                  ( ARGA_S_csa1_3 XOR  ARGB_S_csa1_3 ) =  XOR_S_csa1_3   and
+                  ( ARGA_S_csa1_4 XOR  ARGB_S_csa1_4 ) =  XOR_S_csa1_4   and
+                  ( ARGA_S_usa1_1 XOR  ARGB_S_usa1_1 ) =  XOR_S_usa1_1   and
+                  ( ARGA_S_usa1_2 XOR  ARGB_S_usa1_2 ) =  XOR_S_usa1_2   and
+                  ( ARGA_S_usa1_3 XOR  ARGB_S_usa1_3 ) =  XOR_S_usa1_3   and
+                  ( ARGA_S_usa1_4 XOR  ARGB_S_usa1_4 ) =  XOR_S_usa1_4   and
+                  ( ARGA_V_csa1_1 XOR  ARGB_V_csa1_1 ) =  XOR_V_csa1_1   and
+                  ( ARGA_V_csa1_2 XOR  ARGB_V_csa1_2 ) =  XOR_V_csa1_2   and
+                  ( ARGA_V_csa1_3 XOR  ARGB_V_csa1_3 ) =  XOR_V_csa1_3   and
+                  ( ARGA_V_csa1_4 XOR  ARGB_V_csa1_4 ) =  XOR_V_csa1_4   and
+                  ( ARGA_V_usa1_1 XOR  ARGB_V_usa1_1 ) =  XOR_V_usa1_1   and
+                  ( ARGA_V_usa1_2 XOR  ARGB_V_usa1_2 ) =  XOR_V_usa1_2   and
+                  ( ARGA_V_usa1_3 XOR  ARGB_V_usa1_3 ) =  XOR_V_usa1_3   and
+                  ( ARGA_V_usa1_4 XOR  ARGB_V_usa1_4 ) =  XOR_V_usa1_4   )   
+      report "***PASSED TEST: c07s02b01x00p01n02i01949" 
+      severity NOTE;
+    assert (   ( ARGA_C_csa1_1 XOR  ARGB_C_csa1_1 ) =  XOR_C_csa1_1   and
+               ( ARGA_C_csa1_2 XOR  ARGB_C_csa1_2 ) =  XOR_C_csa1_2   and
+               ( ARGA_C_csa1_3 XOR  ARGB_C_csa1_3 ) =  XOR_C_csa1_3   and
+               ( ARGA_C_csa1_4 XOR  ARGB_C_csa1_4 ) =  XOR_C_csa1_4   and
+               ( ARGA_C_usa1_1 XOR  ARGB_C_usa1_1 ) =  XOR_C_usa1_1   and
+               ( ARGA_C_usa1_2 XOR  ARGB_C_usa1_2 ) =  XOR_C_usa1_2   and
+               ( ARGA_C_usa1_3 XOR  ARGB_C_usa1_3 ) =  XOR_C_usa1_3   and
+               ( ARGA_C_usa1_4 XOR  ARGB_C_usa1_4 ) =  XOR_C_usa1_4   and
+               ( ARGA_S_csa1_1 XOR  ARGB_S_csa1_1 ) =  XOR_S_csa1_1   and
+               ( ARGA_S_csa1_2 XOR  ARGB_S_csa1_2 ) =  XOR_S_csa1_2   and
+               ( ARGA_S_csa1_3 XOR  ARGB_S_csa1_3 ) =  XOR_S_csa1_3   and
+               ( ARGA_S_csa1_4 XOR  ARGB_S_csa1_4 ) =  XOR_S_csa1_4   and
+               ( ARGA_S_usa1_1 XOR  ARGB_S_usa1_1 ) =  XOR_S_usa1_1   and
+               ( ARGA_S_usa1_2 XOR  ARGB_S_usa1_2 ) =  XOR_S_usa1_2   and
+               ( ARGA_S_usa1_3 XOR  ARGB_S_usa1_3 ) =  XOR_S_usa1_3   and
+               ( ARGA_S_usa1_4 XOR  ARGB_S_usa1_4 ) =  XOR_S_usa1_4   and
+               ( ARGA_V_csa1_1 XOR  ARGB_V_csa1_1 ) =  XOR_V_csa1_1   and
+               ( ARGA_V_csa1_2 XOR  ARGB_V_csa1_2 ) =  XOR_V_csa1_2   and
+               ( ARGA_V_csa1_3 XOR  ARGB_V_csa1_3 ) =  XOR_V_csa1_3   and
+               ( ARGA_V_csa1_4 XOR  ARGB_V_csa1_4 ) =  XOR_V_csa1_4   and
+               ( ARGA_V_usa1_1 XOR  ARGB_V_usa1_1 ) =  XOR_V_usa1_1   and
+               ( ARGA_V_usa1_2 XOR  ARGB_V_usa1_2 ) =  XOR_V_usa1_2   and
+               ( ARGA_V_usa1_3 XOR  ARGB_V_usa1_3 ) =  XOR_V_usa1_3   and
+               ( ARGA_V_usa1_4 XOR  ARGB_V_usa1_4 ) =  XOR_V_usa1_4   )   
+      report "***FAILED TEST: c07s02b01x00p01n02i01949 - Logical operator XOR for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01949arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1950.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1950.vhd
new file mode 100644
index 0000000..549ae9a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1950.vhd
@@ -0,0 +1,283 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1950.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s02b01x00p01n02i01950pkg is
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     4;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Logic types for subelements
+--
+  SUBTYPE st_scl1 IS BIT;
+  SUBTYPE st_scl2 IS BOOLEAN;
+
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Unconstrained arrays
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF BIT;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF BOOLEAN;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF BIT;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF BOOLEAN;
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1);
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2);
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3);
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4);
+-- -----------------------------------------------------------------------------------------
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+end;
+
+use work.c07s02b01x00p01n02i01950pkg.all;
+ENTITY c07s02b01x00p01n02i01950ent IS
+END c07s02b01x00p01n02i01950ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01950arch OF c07s02b01x00p01n02i01950ent IS
+-- 
+--          CONSTANT Declarations
+-- 
+  CONSTANT ARGA_C_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  CONSTANT  NOT_C_csa1_1 : t_csa1_1          := ( '0', '0', '1', '1' );
+  CONSTANT  NOT_C_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '1', '1' );
+
+  CONSTANT ARGA_C_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT  NOT_C_csa1_2 : t_csa1_2          := ( FALSE, FALSE,  TRUE,  TRUE );
+  CONSTANT  NOT_C_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE,  TRUE,  TRUE );
+
+  CONSTANT ARGA_C_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  CONSTANT ARGA_C_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  CONSTANT  NOT_C_csa1_3 : t_csa1_3          := ( '0', '0', '1', '1' );
+  CONSTANT  NOT_C_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '1', '1' );
+  
+  CONSTANT ARGA_C_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT ARGA_C_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  CONSTANT  NOT_C_csa1_4 : t_csa1_4          := ( FALSE, FALSE,  TRUE,  TRUE );
+  CONSTANT  NOT_C_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE,  TRUE,  TRUE );
+--
+--          SIGNAL Declarations
+--
+  SIGNAL ARGA_S_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+  SIGNAL  NOT_S_csa1_1 : t_csa1_1          := ( '0', '0', '1', '1' );
+  SIGNAL  NOT_S_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '1', '1' );
+  
+  SIGNAL ARGA_S_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL  NOT_S_csa1_2 : t_csa1_2          := ( FALSE, FALSE,  TRUE,  TRUE );
+  SIGNAL  NOT_S_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE,  TRUE,  TRUE );
+  
+  SIGNAL ARGA_S_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+  SIGNAL ARGA_S_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+  SIGNAL  NOT_S_csa1_3 : t_csa1_3          := ( '0', '0', '1', '1' );
+  SIGNAL  NOT_S_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '1', '1' );
+  
+  SIGNAL ARGA_S_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL ARGA_S_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+  SIGNAL  NOT_S_csa1_4 : t_csa1_4          := ( FALSE, FALSE,  TRUE,  TRUE );
+  SIGNAL  NOT_S_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE,  TRUE,  TRUE );
+BEGIN
+  TESTING: PROCESS
+-- 
+--          VARIABLE Declarations
+--
+    VARIABLE ARGA_V_csa1_1 : t_csa1_1          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_1 : t_usa1_1(st_ind1) := ( '1', '1', '0', '0' );
+    VARIABLE  NOT_V_csa1_1 : t_csa1_1          := ( '0', '0', '1', '1' );
+    VARIABLE  NOT_V_usa1_1 : t_usa1_1(st_ind1) := ( '0', '0', '1', '1' );
+    
+    VARIABLE ARGA_V_csa1_2 : t_csa1_2          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_2 : t_usa1_2(st_ind2) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE  NOT_V_csa1_2 : t_csa1_2          := ( FALSE, FALSE,  TRUE,  TRUE );
+    VARIABLE  NOT_V_usa1_2 : t_usa1_2(st_ind2) := ( FALSE, FALSE,  TRUE,  TRUE );
+    
+    VARIABLE ARGA_V_csa1_3 : t_csa1_3          := ( '1', '1', '0', '0' );
+    VARIABLE ARGA_V_usa1_3 : t_usa1_3(st_ind3) := ( '1', '1', '0', '0' );
+    VARIABLE  NOT_V_csa1_3 : t_csa1_3          := ( '0', '0', '1', '1' );
+    VARIABLE  NOT_V_usa1_3 : t_usa1_3(st_ind3) := ( '0', '0', '1', '1' );
+    
+    VARIABLE ARGA_V_csa1_4 : t_csa1_4          := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE ARGA_V_usa1_4 : t_usa1_4(st_ind4) := (  TRUE,  TRUE, FALSE, FALSE );
+    VARIABLE  NOT_V_csa1_4 : t_csa1_4          := ( FALSE, FALSE,  TRUE,  TRUE );
+    VARIABLE  NOT_V_usa1_4 : t_usa1_4(st_ind4) := ( FALSE, FALSE,  TRUE,  TRUE );
+  BEGIN
+--
+--          Test AND operator on: CONSTANTs
+--
+    ASSERT ( NOT  ARGA_C_csa1_1 ) =  NOT_C_csa1_1
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_csa1_2 ) =  NOT_C_csa1_2
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_csa1_3 ) =  NOT_C_csa1_3
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_csa1_4 ) =  NOT_C_csa1_4
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_usa1_1 ) =  NOT_C_usa1_1
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_usa1_2 ) =  NOT_C_usa1_2
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_usa1_3 ) =  NOT_C_usa1_3
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_C_usa1_4 ) =  NOT_C_usa1_4
+      REPORT "ERROR: composite NOT operator failed; CONSTANT; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NOT operator on: SIGNALs
+--
+    ASSERT ( NOT  ARGA_S_csa1_1 ) =  NOT_S_csa1_1
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_csa1_2 ) =  NOT_S_csa1_2
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_csa1_3 ) =  NOT_S_csa1_3
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_csa1_4 ) =  NOT_S_csa1_4
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_usa1_1 ) =  NOT_S_usa1_1
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_usa1_2 ) =  NOT_S_usa1_2
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_usa1_3 ) =  NOT_S_usa1_3
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_S_usa1_4 ) =  NOT_S_usa1_4
+      REPORT "ERROR: composite NOT operator failed; SIGNAL; usa1_4"
+      SEVERITY FAILURE;
+--
+--          Test NOT operator on: VARIABLEs
+--
+    ASSERT ( NOT  ARGA_V_csa1_1 ) =  NOT_V_csa1_1
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_csa1_2 ) =  NOT_V_csa1_2
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_csa1_3 ) =  NOT_V_csa1_3
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_csa1_4 ) =  NOT_V_csa1_4
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; csa1_4"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_usa1_1 ) =  NOT_V_usa1_1
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_1"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_usa1_2 ) =  NOT_V_usa1_2
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_2"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_usa1_3 ) =  NOT_V_usa1_3
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_3"
+      SEVERITY FAILURE;
+    ASSERT ( NOT  ARGA_V_usa1_4 ) =  NOT_V_usa1_4
+      REPORT "ERROR: composite NOT operator failed; VARIABLE; usa1_4"
+      SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   ( NOT  ARGA_C_csa1_1 ) =  NOT_C_csa1_1   and
+                  ( NOT  ARGA_C_csa1_2 ) =  NOT_C_csa1_2   and
+                  ( NOT  ARGA_C_csa1_3 ) =  NOT_C_csa1_3   and
+                  ( NOT  ARGA_C_csa1_4 ) =  NOT_C_csa1_4   and
+                  ( NOT  ARGA_C_usa1_1 ) =  NOT_C_usa1_1   and
+                  ( NOT  ARGA_C_usa1_2 ) =  NOT_C_usa1_2   and
+                  ( NOT  ARGA_C_usa1_3 ) =  NOT_C_usa1_3   and
+                  ( NOT  ARGA_C_usa1_4 ) =  NOT_C_usa1_4   and
+                  ( NOT  ARGA_S_csa1_1 ) =  NOT_S_csa1_1   and
+                  ( NOT  ARGA_S_csa1_2 ) =  NOT_S_csa1_2   and
+                  ( NOT  ARGA_S_csa1_3 ) =  NOT_S_csa1_3   and
+                  ( NOT  ARGA_S_csa1_4 ) =  NOT_S_csa1_4   and
+                  ( NOT  ARGA_S_usa1_1 ) =  NOT_S_usa1_1   and
+                  ( NOT  ARGA_S_usa1_2 ) =  NOT_S_usa1_2   and
+                  ( NOT  ARGA_S_usa1_3 ) =  NOT_S_usa1_3   and
+                  ( NOT  ARGA_S_usa1_4 ) =  NOT_S_usa1_4   and
+                  ( NOT  ARGA_V_csa1_1 ) =  NOT_V_csa1_1   and
+                  ( NOT  ARGA_V_csa1_2 ) =  NOT_V_csa1_2   and
+                  ( NOT  ARGA_V_csa1_3 ) =  NOT_V_csa1_3   and
+                  ( NOT  ARGA_V_csa1_4 ) =  NOT_V_csa1_4   and
+                  ( NOT  ARGA_V_usa1_1 ) =  NOT_V_usa1_1   and
+                  ( NOT  ARGA_V_usa1_2 ) =  NOT_V_usa1_2   and
+                  ( NOT  ARGA_V_usa1_3 ) =  NOT_V_usa1_3   and
+                  ( NOT  ARGA_V_usa1_4 ) =  NOT_V_usa1_4   )
+      report "***PASSED TEST: c07s02b01x00p01n02i01950" 
+      severity NOTE;
+    assert (   ( NOT  ARGA_C_csa1_1 ) =  NOT_C_csa1_1   and
+               ( NOT  ARGA_C_csa1_2 ) =  NOT_C_csa1_2   and
+               ( NOT  ARGA_C_csa1_3 ) =  NOT_C_csa1_3   and
+               ( NOT  ARGA_C_csa1_4 ) =  NOT_C_csa1_4   and
+               ( NOT  ARGA_C_usa1_1 ) =  NOT_C_usa1_1   and
+               ( NOT  ARGA_C_usa1_2 ) =  NOT_C_usa1_2   and
+               ( NOT  ARGA_C_usa1_3 ) =  NOT_C_usa1_3   and
+               ( NOT  ARGA_C_usa1_4 ) =  NOT_C_usa1_4   and
+               ( NOT  ARGA_S_csa1_1 ) =  NOT_S_csa1_1   and
+               ( NOT  ARGA_S_csa1_2 ) =  NOT_S_csa1_2   and
+               ( NOT  ARGA_S_csa1_3 ) =  NOT_S_csa1_3   and
+               ( NOT  ARGA_S_csa1_4 ) =  NOT_S_csa1_4   and
+               ( NOT  ARGA_S_usa1_1 ) =  NOT_S_usa1_1   and
+               ( NOT  ARGA_S_usa1_2 ) =  NOT_S_usa1_2   and
+               ( NOT  ARGA_S_usa1_3 ) =  NOT_S_usa1_3   and
+               ( NOT  ARGA_S_usa1_4 ) =  NOT_S_usa1_4   and
+               ( NOT  ARGA_V_csa1_1 ) =  NOT_V_csa1_1   and
+               ( NOT  ARGA_V_csa1_2 ) =  NOT_V_csa1_2   and
+               ( NOT  ARGA_V_csa1_3 ) =  NOT_V_csa1_3   and
+               ( NOT  ARGA_V_csa1_4 ) =  NOT_V_csa1_4   and
+               ( NOT  ARGA_V_usa1_1 ) =  NOT_V_usa1_1   and
+               ( NOT  ARGA_V_usa1_2 ) =  NOT_V_usa1_2   and
+               ( NOT  ARGA_V_usa1_3 ) =  NOT_V_usa1_3   and
+               ( NOT  ARGA_V_usa1_4 ) =  NOT_V_usa1_4   )
+      report "***FAILED TEST: c07s02b01x00p01n02i01950 - Logical operator NOT for any user-defined one-dimensional array type test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01950arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1952.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1952.vhd
new file mode 100644
index 0000000..7e05325
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1952.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1952.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01952ent IS
+END c07s02b01x00p02n02i01952ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01952arch OF c07s02b01x00p02n02i01952ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a and b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01952"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01952 - Logical operation of 'AND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01952arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1953.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1953.vhd
new file mode 100644
index 0000000..68affd2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1953.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1953.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01953ent IS
+END c07s02b01x00p02n02i01953ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01953arch OF c07s02b01x00p02n02i01953ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a and b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01953"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01953 - Logical operation of 'AND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01953arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1954.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1954.vhd
new file mode 100644
index 0000000..6441460
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1954.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1954.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01954ent IS
+END c07s02b01x00p02n02i01954ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01954arch OF c07s02b01x00p02n02i01954ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a and b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01954"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01954 - Logical operation of 'AND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01954arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1955.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1955.vhd
new file mode 100644
index 0000000..f3bccbd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1955.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1955.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01955ent IS
+END c07s02b01x00p02n02i01955ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01955arch OF c07s02b01x00p02n02i01955ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a and b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01955"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01955 - Logical operation of 'AND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01955arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1956.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1956.vhd
new file mode 100644
index 0000000..3099d05
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1956.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1956.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01956ent IS
+END c07s02b01x00p02n02i01956ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01956arch OF c07s02b01x00p02n02i01956ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a or b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01956"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01956 - Logical operation of 'OR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01956arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1957.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1957.vhd
new file mode 100644
index 0000000..772d8f5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1957.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1957.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01957ent IS
+END c07s02b01x00p02n02i01957ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01957arch OF c07s02b01x00p02n02i01957ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a or b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01957"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01957 - Logical operation of 'OR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01957arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1958.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1958.vhd
new file mode 100644
index 0000000..2035fd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1958.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1958.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01958ent IS
+END c07s02b01x00p02n02i01958ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01958arch OF c07s02b01x00p02n02i01958ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a or b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01958"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01958 - Logical operation of 'OR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01958arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1959.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1959.vhd
new file mode 100644
index 0000000..5682a5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1959.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1959.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01959ent IS
+END c07s02b01x00p02n02i01959ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01959arch OF c07s02b01x00p02n02i01959ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a or b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01959"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01959 - Logical operation of 'OR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01959arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1960.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1960.vhd
new file mode 100644
index 0000000..a88f706
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1960.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1960.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01960ent IS
+END c07s02b01x00p02n02i01960ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01960arch OF c07s02b01x00p02n02i01960ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a xor b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01960"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01960 - Logical operation of 'XOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01960arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1961.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1961.vhd
new file mode 100644
index 0000000..215dac4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1961.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1961.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01961ent IS
+END c07s02b01x00p02n02i01961ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01961arch OF c07s02b01x00p02n02i01961ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a xor b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01961"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01961 - Logical operation of 'XOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01961arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1962.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1962.vhd
new file mode 100644
index 0000000..74d097a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1962.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1962.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01962ent IS
+END c07s02b01x00p02n02i01962ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01962arch OF c07s02b01x00p02n02i01962ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a xor b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01962"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01962 - Logical operation of 'XOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01962arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1963.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1963.vhd
new file mode 100644
index 0000000..5f67ca2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1963.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1963.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01963ent IS
+END c07s02b01x00p02n02i01963ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01963arch OF c07s02b01x00p02n02i01963ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a xor b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01963"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01963 - Logical operation of 'XOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01963arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1964.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1964.vhd
new file mode 100644
index 0000000..461ac4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1964.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1964.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01964ent IS
+END c07s02b01x00p02n02i01964ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01964arch OF c07s02b01x00p02n02i01964ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a nand b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01964"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01964 - Logical operation of 'NAND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01964arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1965.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1965.vhd
new file mode 100644
index 0000000..4f523ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1965.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1965.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01965ent IS
+END c07s02b01x00p02n02i01965ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01965arch OF c07s02b01x00p02n02i01965ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a nand b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01965"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01965 - Logical operation of 'NAND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01965arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1966.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1966.vhd
new file mode 100644
index 0000000..c811c31
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1966.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1966.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01966ent IS
+END c07s02b01x00p02n02i01966ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01966arch OF c07s02b01x00p02n02i01966ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a nand b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01966"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01966 - Logical operation of 'NAND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01966arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1967.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1967.vhd
new file mode 100644
index 0000000..f338edd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1967.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1967.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01967ent IS
+END c07s02b01x00p02n02i01967ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01967arch OF c07s02b01x00p02n02i01967ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a nand b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01967"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01967 - Logical operation of 'NAND'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01967arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1968.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1968.vhd
new file mode 100644
index 0000000..e37c97d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1968.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1968.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01968ent IS
+END c07s02b01x00p02n02i01968ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01968arch OF c07s02b01x00p02n02i01968ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a nor b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01968"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01968 - Logical operation of 'NOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01968arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1969.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1969.vhd
new file mode 100644
index 0000000..06e036e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1969.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1969.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01969ent IS
+END c07s02b01x00p02n02i01969ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01969arch OF c07s02b01x00p02n02i01969ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a nor b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01969"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01969 - Logical operation of 'NOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01969arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1970.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1970.vhd
new file mode 100644
index 0000000..d52642a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1970.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1970.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01970ent IS
+END c07s02b01x00p02n02i01970ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01970arch OF c07s02b01x00p02n02i01970ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := TRUE;
+    variable c : boolean;
+  BEGIN
+    c := a nor b;   
+    assert NOT(c=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01970"
+      severity NOTE;
+    assert ( c=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01970 - Logical operation of 'NOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01970arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1971.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1971.vhd
new file mode 100644
index 0000000..15aecac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1971.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1971.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01971ent IS
+END c07s02b01x00p02n02i01971ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01971arch OF c07s02b01x00p02n02i01971ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+    variable b : boolean := FALSE;
+    variable c : boolean;
+  BEGIN
+    c := a nor b;   
+    assert NOT(c=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01971"
+      severity NOTE;
+    assert ( c=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01971 - Logical operation of 'NOR'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01971arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1972.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1972.vhd
new file mode 100644
index 0000000..7d27566
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1972.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1972.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01972ent IS
+END c07s02b01x00p02n02i01972ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01972arch OF c07s02b01x00p02n02i01972ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := TRUE;
+  BEGIN
+    a := not a;   
+    assert NOT(a=FALSE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01972"
+      severity NOTE;
+    assert ( a=FALSE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01972 - Logical operation of 'NOT'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01972arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1973.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1973.vhd
new file mode 100644
index 0000000..c6032f0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1973.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1973.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01973ent IS
+END c07s02b01x00p02n02i01973ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01973arch OF c07s02b01x00p02n02i01973ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : boolean := FALSE;
+  BEGIN
+    a := not a;   
+    assert NOT(a=TRUE)
+      report "***PASSED TEST: c07s02b01x00p02n02i01973"
+      severity NOTE;
+    assert ( a=TRUE )
+      report "***FAILED TEST: c07s02b01x00p02n02i01973 - Logical operation of 'NOT'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01973arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1974.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1974.vhd
new file mode 100644
index 0000000..ee8ae7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1974.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1974.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01974ent IS
+END c07s02b01x00p02n02i01974ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01974arch OF c07s02b01x00p02n02i01974ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant L : BIT_VECTOR(1 to 4) := "0101";
+    constant R : BIT_VECTOR(1 to 4) := "0011";
+
+    constant N  : BIT_VECTOR(1 TO 4) := not L;
+    constant A  : BIT_VECTOR(1 TO 4) := L and R;
+    constant O  : BIT_VECTOR(1 TO 4) := L or R;
+    constant NA : BIT_VECTOR(1 TO 4) := L nand R;
+    constant NO : BIT_VECTOR(1 TO 4) := L nor R;
+    constant X  : BIT_VECTOR(1 TO 4) := L xor R;
+  BEGIN
+
+    assert N  = "1010"      report "FAIL: NOT";
+    assert A  = "0001"      report "FAIL: AND";
+    assert O  = "0111"      report "FAIL: OR";
+    assert NA = "1110"      report "FAIL: NAND";
+    assert NO = "1000"      report "FAIL: NOR";
+    assert X  = "0110"      report "FAIL: XOR";
+
+    assert N = not L        report "FAIL: NOT (composite check)";
+    assert A  = (L and R)   report "FAIL: AND (composite check)";
+    assert O  = (L or R)    report "FAIL: OR (composite check)";
+    assert NA = (L nand R)  report "FAIL: NAND (composite check)";
+    assert NO = (L nor R)   report "FAIL: NOR (composite check)";
+    assert X  = (L xor R)   report "FAIL: XOR (composite check)";
+    
+    for i in 1 to 4 loop
+      assert N(i)  = not L(i)             report "FAIL: NOT";
+      assert A(i)  = (L(i) and R(i))      report "FAIL: AND";
+      assert O(i)  = (L(i) or R(i))       report "FAIL: OR";
+      assert NA(i) = (L(i) nand R(i))     report "FAIL: NAND";
+      assert NO(i) = (L(i) nor R(i))      report "FAIL: NOR";
+      assert X(i)  = (L(i) xor R(i))      report "FAIL: XOR";
+    end loop;
+
+    assert NOT(    N  = "1010"         and 
+                   A  = "0001"         and 
+                   O  = "0111"         and
+                   NA = "1110"         and
+                   NO = "1000"         and
+                   X  = "0110"         and
+                   N  = not L           and 
+                   A  = (L and R)      and 
+                   O  = (L or R)       and 
+                   NA = (L nand R)     and 
+                   NO = (L nor R)      and 
+                   X  = (L xor R)      )
+      report "***PASSED TEST: c07s02b01x00p02n02i01974"
+      severity NOTE;
+    assert (    N  = "1010"         and 
+                A  = "0001"         and 
+                O  = "0111"         and
+                NA = "1110"         and
+                NO = "1000"         and
+                X  = "0110"         and
+                N  = not L           and 
+                A  = (L and R)      and 
+                O  = (L or R)       and 
+                NA = (L nand R)     and 
+                NO = (L nor R)      and 
+                X  = (L xor R)      )
+      report "***FAILED TEST: c07s02b01x00p02n02i01974 - BIT_VECTOR type truth table test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01974arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1975.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1975.vhd
new file mode 100644
index 0000000..4bfd50e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1975.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1975.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p02n02i01975ent IS
+  constant T:bit := '1';
+  constant F:bit := '0';
+END c07s02b01x00p02n02i01975ent;
+
+ARCHITECTURE c07s02b01x00p02n02i01975arch OF c07s02b01x00p02n02i01975ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A1 : bit := T;
+    variable A2 : bit := F;
+  BEGIN
+    assert NOT(    (A1 and A1) = '1'   and
+                   (A1 and A2) = '0'   and
+                   (A2 and A1) = '0'   and
+                   (A2 and A2) = '0'   and
+                   (A1 or A1) = '1'   and
+                   (A1 or A2) = '1'   and
+                   (A2 or A1) = '1'   and
+                   (A2 or A2) = '0'   and
+                   (A1 xor A1) = '0'   and
+                   (A1 xor A2) = '1'   and
+                   (A2 xor A1) = '1'   and
+                   (A2 xor A2) = '0'   and
+                   (A1 nand A1) = '0'   and
+                   (A1 nand A2) = '1'   and
+                   (A2 nand A1) = '1'   and
+                   (A2 nand A2) = '1'   and
+                   (A1 nor A1) = '0'   and
+                   (A1 nor A2) = '0'   and
+                   (A2 nor A1) = '0'   and
+                   (A2 nor A2) = '1'   and
+                   (not A1) = '0'      and
+                   (not A2) = '1')
+      report "***PASSED TEST: c07s02b01x00p02n02i01975"
+      severity NOTE;
+    assert (    (A1 and A1) = '1'   and
+                (A1 and A2) = '0'   and
+                (A2 and A1) = '0'   and
+                (A2 and A2) = '0'   and
+                (A1 or A1) = '1'   and
+                (A1 or A2) = '1'   and
+                (A2 or A1) = '1'   and
+                (A2 or A2) = '0'   and
+                (A1 xor A1) = '0'   and
+                (A1 xor A2) = '1'   and
+                (A2 xor A1) = '1'   and
+                (A2 xor A2) = '0'   and
+                (A1 nand A1) = '0'   and
+                (A1 nand A2) = '1'   and
+                (A2 nand A1) = '1'   and
+                (A2 nand A2) = '1'   and
+                (A1 nor A1) = '0'   and
+                (A1 nor A2) = '0'   and
+                (A2 nor A1) = '0'   and
+                (A2 nor A2) = '1'   and
+                (not A1) = '0'      and
+                (not A2) = '1')
+      report "***FAILED TEST: c07s02b01x00p02n02i01975 - BIT type truth table test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p02n02i01975arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1976.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1976.vhd
new file mode 100644
index 0000000..8514536
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1976.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1976.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p03n01i01976ent IS
+END c07s02b01x00p03n01i01976ent;
+
+ARCHITECTURE c07s02b01x00p03n01i01976arch OF c07s02b01x00p03n01i01976ent IS
+  signal s : integer := 0;
+  function temp(s:integer) return boolean is
+  begin
+    assert FALSE
+      report "***FAILED TEST: c07s02b01x00p03n01i01976 - The right operand is evaluated only if the value of the left operand is not sufficient to determine the result of the operation."
+      severity ERROR;
+    return true;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable x : boolean := false;
+  BEGIN
+    if x and (temp(s)) then
+      NULL;
+    end if;
+    wait for 1 ns;
+    assert FALSE
+      report "***PASSED TEST: c07s02b01x00p03n01i01976 - This test needs manual check, only when the FAILED TEST assertion do not appear then the test is passed."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p03n01i01976arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1978.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1978.vhd
new file mode 100644
index 0000000..1c391cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1978.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1978.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p01n02i01978ent IS
+END c07s02b02x00p01n02i01978ent;
+
+ARCHITECTURE c07s02b02x00p01n02i01978arch OF c07s02b02x00p01n02i01978ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c07s02b02x00p01n02i01978"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c07s02b02x00p01n02i01978"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c07s02b02x00p01n02i01978arch;
+
+-- CONFIGURATION c07s02b02x00p01n02i01978cfg OF c07s02b02x00p01n02i01978ent IS
+--     FOR c07s02b02x00p01n02i01978arch
+--     END FOR;
+-- END c07s02b02x00p01n02i01978cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc198.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc198.vhd
new file mode 100644
index 0000000..1804bdf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc198.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc198.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p04n01i00198ent IS
+END c03s01b00x00p04n01i00198ent;
+
+ARCHITECTURE c03s01b00x00p04n01i00198arch OF c03s01b00x00p04n01i00198ent IS
+  type t1 is range (1+1) to (10+2);
+BEGIN
+  TESTING: PROCESS
+    variable k : t1 := 6;
+  BEGIN
+    k := 5;   
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b00x00p04n01i00198" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b00x00p04n01i00198- The range must be either a range attribute name or two simple expressions combined with a direction operator." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p04n01i00198arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1981.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1981.vhd
new file mode 100644
index 0000000..d0634a9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1981.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1981.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p01n03i01981ent IS
+END c07s02b02x00p01n03i01981ent;
+
+ARCHITECTURE c07s02b02x00p01n03i01981arch OF c07s02b02x00p01n03i01981ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i, j, k, l, m, n, o, p : integer := 1;
+  BEGIN
+    if (i<j or (i>= 0) ) then  -- No_failure_here    
+      k := 5;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p01n03i01981"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c07s02b02x00p01n03i01981 - The result type of each relational operator is the predefined type BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p01n03i01981arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1982.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1982.vhd
new file mode 100644
index 0000000..d8498c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1982.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1982.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p01n03i01982ent IS
+END c07s02b02x00p01n03i01982ent;
+
+ARCHITECTURE c07s02b02x00p01n03i01982arch OF c07s02b02x00p01n03i01982ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i, j, k, l, m, n, o, p : integer := 1;
+  BEGIN
+    if (m=n) then  -- No_failure_here    
+      k := 5;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p01n03i01982"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c07s02b02x00p01n03i01982 - The result type of each relational operator is the predefined type BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p01n03i01982arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1983.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1983.vhd
new file mode 100644
index 0000000..ab8a25c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1983.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1983.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01983ent IS
+  type color is (red, green, blue);
+  constant azure : color := blue;
+  constant first : color := color'low;
+END c07s02b02x00p02n01i01983ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01983arch OF c07s02b02x00p02n01i01983ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A1, A2   : color;
+    variable A3    : color := blue;
+    alias AA1 :color is A1;
+  BEGIN
+
+    AA1:= first;
+    A2 := color'succ(A1);
+
+    assert NOT(     A2 = green   and
+                    green = A2   and
+                    A2 > AA1   and
+                    red >= A1   and
+                    A1 >= red   and
+                    A3 <= blue   and
+                    blue <= A3   and
+                    A1 < green   and
+                    green < A3   and
+                    red < azure    )
+      report "***PASSED TEST: c07s02b02x00p02n01i01983"
+      severity NOTE;
+    assert (     A2 = green   and
+                 green = A2   and
+                 A2 > AA1   and
+                 red >= A1   and
+                 A1 >= red   and
+                 A3 <= blue   and
+                 blue <= A3   and
+                 A1 < green   and
+                 green < A3   and
+                 red < azure    )
+      report "***FAILED TEST: c07s02b02x00p02n01i01983 - Relational operators truth table test for data type of Enumeration failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01983arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1984.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1984.vhd
new file mode 100644
index 0000000..167b16d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1984.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1984.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01984ent IS
+END c07s02b02x00p02n01i01984ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01984arch OF c07s02b02x00p02n01i01984ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable B1 : boolean := true;
+    variable B2 : boolean := false;
+    variable A1 : bit := '1';
+    variable A2 : bit := '0';
+  BEGIN
+
+    assert NOT(     A1 = '1'   and
+                    '1' = A1   and
+                    B2 = false   and
+                    false = B2   and
+                    A1 /= A2   and
+                    B1 /= B2   and
+                    A2 < A1   and
+                    B2 < B1   and
+                    A1 > A2   and
+                    B1 > B2   and
+                    A2 <= A1   and
+                    B2 <= B1   and
+                    A1 >= A2   and
+                    B1 >= B2   and
+                    A1 <= A1   and
+                    B1 <= B1   and
+                    B2 <= B2   and
+                    A2 <= A2   )   
+      report "***PASSED TEST: c07s02b02x00p02n01i01984"
+      severity NOTE;
+    assert (     A1 = '1'   and
+                 '1' = A1   and
+                 B2 = false   and
+                 false = B2   and
+                 A1 /= A2   and
+                 B1 /= B2   and
+                 A2 < A1   and
+                 B2 < B1   and
+                 A1 > A2   and
+                 B1 > B2   and
+                 A2 <= A1   and
+                 B2 <= B1   and
+                 A1 >= A2   and
+                 B1 >= B2   and
+                 A1 <= A1   and
+                 B1 <= B1   and
+                 B2 <= B2   and
+                 A2 <= A2   )   
+      report "***FAILED TEST: c07s02b02x00p02n01i01984 - Relational operators true table test for data type of BIT and BOOLEAN failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01984arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1985.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1985.vhd
new file mode 100644
index 0000000..005daf6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1985.vhd
@@ -0,0 +1,153 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1985.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01985ent IS
+END c07s02b02x00p02n01i01985ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01985arch OF c07s02b02x00p02n01i01985ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant meg       : integer := 1000000;
+    variable bigpos    : integer := 2000 * meg;
+    variable bigneg    : integer := -2000 * meg;
+    variable smallpos    : integer := 2000;
+    variable smallneg    : integer := -2000;
+    variable zero       : integer := 0;
+  BEGIN
+
+    assert NOT(    ( bigneg < smallneg)   and
+                   ( bigneg < zero)   and
+                   ( bigneg < smallpos)   and
+                   ( bigneg < bigpos)   and
+                   ( smallneg < zero)   and
+                   ( smallneg < smallpos)   and
+                   ( smallneg < bigpos)   and
+                   ( zero < smallpos)   and
+                   ( zero < bigpos)   and
+                   ( smallpos < bigpos)   and
+                   ( not(bigneg >= smallneg))   and
+                   ( not(bigneg >= zero))      and
+                   ( not(bigneg >= smallpos))   and
+                   ( not(bigneg >= bigpos))   and
+                   ( not(smallneg >= zero))   and
+                   ( not(smallneg >= smallpos))   and
+                   ( not(smallneg >= bigpos))   and
+                   ( not(zero >= smallpos))   and
+                   ( not(zero >= bigpos))      and
+                   ( not(smallpos >= bigpos))   and
+                   ( bigneg <= smallneg)   and
+                   ( bigneg <= zero)   and
+                   ( bigneg <= smallpos)   and
+                   ( bigneg <= bigpos)   and
+                   ( smallneg <= zero)   and
+                   ( smallneg <= smallpos)   and
+                   ( smallneg <= bigpos)   and
+                   ( zero <= smallpos)   and
+                   ( zero <= bigpos)   and
+                   ( smallpos <= bigpos)   and
+                   ( bigneg <= bigneg)   and
+                   ( smallneg <= smallneg)   and
+                   ( zero <=  zero)   and
+                   ( smallpos <= smallpos)   and
+                   ( bigpos <= bigpos)   and
+                   ( not(bigneg > smallneg))   and
+                   ( not(bigneg > zero))      and
+                   ( not(bigneg > smallpos))   and
+                   ( not(bigneg > bigpos))      and
+                   ( not(smallneg > zero))      and
+                   ( not(smallneg > smallpos))   and
+                   ( not(smallneg > bigpos))   and
+                   ( not(zero > smallpos))      and
+                   ( not(zero > bigpos))      and
+                   ( not(smallpos > bigpos))   and
+                   ( not(bigneg > bigneg))      and
+                   ( not(smallneg > smallneg))   and
+                   ( not(zero >  zero))      and
+                   ( not(smallpos > smallpos))   and
+                   ( not(bigpos > bigpos))      ) 
+      report "***PASSED TEST: c07s02b02x00p02n01i01985"
+      severity NOTE;
+    assert (    ( bigneg < smallneg)   and
+                ( bigneg < zero)   and
+                ( bigneg < smallpos)   and
+                ( bigneg < bigpos)   and
+                ( smallneg < zero)   and
+                ( smallneg < smallpos)   and
+                ( smallneg < bigpos)   and
+                ( zero < smallpos)   and
+                ( zero < bigpos)   and
+                ( smallpos < bigpos)   and
+                ( not(bigneg >= smallneg))   and
+                ( not(bigneg >= zero))      and
+                ( not(bigneg >= smallpos))   and
+                ( not(bigneg >= bigpos))   and
+                ( not(smallneg >= zero))   and
+                ( not(smallneg >= smallpos))   and
+                ( not(smallneg >= bigpos))   and
+                ( not(zero >= smallpos))   and
+                ( not(zero >= bigpos))      and
+                ( not(smallpos >= bigpos))   and
+                ( bigneg <= smallneg)   and
+                ( bigneg <= zero)   and
+                ( bigneg <= smallpos)   and
+                ( bigneg <= bigpos)   and
+                ( smallneg <= zero)   and
+                ( smallneg <= smallpos)   and
+                ( smallneg <= bigpos)   and
+                ( zero <= smallpos)   and
+                ( zero <= bigpos)   and
+                ( smallpos <= bigpos)   and
+                ( bigneg <= bigneg)   and
+                ( smallneg <= smallneg)   and
+                ( zero <=  zero)   and
+                ( smallpos <= smallpos)   and
+                ( bigpos <= bigpos)   and
+                ( not(bigneg > smallneg))   and
+                ( not(bigneg > zero))      and
+                ( not(bigneg > smallpos))   and
+                ( not(bigneg > bigpos))      and
+                ( not(smallneg > zero))      and
+                ( not(smallneg > smallpos))   and
+                ( not(smallneg > bigpos))   and
+                ( not(zero > smallpos))      and
+                ( not(zero > bigpos))      and
+                ( not(smallpos > bigpos))   and
+                ( not(bigneg > bigneg))      and
+                ( not(smallneg > smallneg))   and
+                ( not(zero >  zero))      and
+                ( not(smallpos > smallpos))   and
+                ( not(bigpos > bigpos))      ) 
+      report "***FAILED TEST: c07s02b02x00p02n01i01985 - Relational operators truth table test for data type of Integer failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01985arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1986.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1986.vhd
new file mode 100644
index 0000000..b7fcb45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1986.vhd
@@ -0,0 +1,149 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1986.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01986ent IS
+  type omega is range (-100) to 100
+    units
+      o1;
+      o2  = 5 o1;
+      o3  = 10 o1;
+    end units;
+END c07s02b02x00p02n01i01986ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01986arch OF c07s02b02x00p02n01i01986ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable om1, om2, om3 : omega;
+
+    --alias in A of variable in A of E physical type
+    
+    alias al1 : omega is om1;
+    alias al2 : omega is om2;
+    alias al3 : omega is om3;
+  BEGIN
+    om1 := 4 o1;
+    om2 := 5 o1;
+    om3 := 6 o1;
+
+    assert NOT(     5 o1 = 5 o1      and
+                    5 o1 = abs(5 o1)   and
+                    5 o1 = abs(-5 o1)   and
+                    4 o1 /= 5 o1      and
+                    4 o1 /= abs(5 o1)   and
+                    4 o1 /= abs(-5 o1)   and
+                    4 o1 <= 5 o1      and
+                    4 o1 <= abs(5 o1)   and
+                    4 o1 <= abs(-5 o1)   and
+                    5 o1 <= abs(-5 o1)   and
+                    4 o1 < 5 o1      and
+                    4 o1 < abs(5 o1)   and
+                    4 o1 < abs(-5 o1)   and
+                    6 o1 >= 5 o1      and
+                    6 o1 >= abs(5 o1)   and
+                    6 o1 >= abs(-5 o1)   and
+                    5 o1 >= abs(-5 o1)   and
+                    6 o1 > 5 o1      and
+                    6 o1 > abs(5 o1)   and
+                    6 o1 > abs(-5 o1)   and
+                    
+--relation operators with variables
+                    
+                    om1 = om1      and
+                    om2 = abs(om2)      and
+                    om2 = abs(-om2)   and
+                    om1 /= om2      and
+                    om1 /= abs(om2)   and
+                    om1 /= abs(-om2)   and
+                    om1 <= om2      and
+                    om1 <= abs(om2)   and
+                    om1 <= abs(-om2)   and
+                    om2 <= abs(-om2)   and
+                    om1 < om2      and
+                    om1 < abs(om2)      and
+                    om1 < abs(-om2)   and
+                    om2 >= om1      and
+                    om2 >= abs(om1)   and
+                    om2 >= abs(-om1)   and
+                    om2 >= abs(-om1)   and
+                    om2 > om1      and
+                    om2 > abs(om1)      and
+                    om2 > abs(-om1)   )
+      report "***PASSED TEST: c07s02b02x00p02n01i01986"
+      severity NOTE;
+    assert (     5 o1 = 5 o1      and
+                 5 o1 = abs(5 o1)   and
+                 5 o1 = abs(-5 o1)   and
+                 4 o1 /= 5 o1      and
+                 4 o1 /= abs(5 o1)   and
+                 4 o1 /= abs(-5 o1)   and
+                 4 o1 <= 5 o1      and
+                 4 o1 <= abs(5 o1)   and
+                 4 o1 <= abs(-5 o1)   and
+                 5 o1 <= abs(-5 o1)   and
+                 4 o1 < 5 o1      and
+                 4 o1 < abs(5 o1)   and
+                 4 o1 < abs(-5 o1)   and
+                 6 o1 >= 5 o1      and
+                 6 o1 >= abs(5 o1)   and
+                 6 o1 >= abs(-5 o1)   and
+                 5 o1 >= abs(-5 o1)   and
+                 6 o1 > 5 o1      and
+                 6 o1 > abs(5 o1)   and
+                 6 o1 > abs(-5 o1)   and
+                 
+--relation operators with variables
+                 
+                 om1 = om1      and
+                 om2 = abs(om2)      and
+                 om2 = abs(-om2)   and
+                 om1 /= om2      and
+                 om1 /= abs(om2)   and
+                 om1 /= abs(-om2)   and
+                 om1 <= om2      and
+                 om1 <= abs(om2)   and
+                 om1 <= abs(-om2)   and
+                 om2 <= abs(-om2)   and
+                 om1 < om2      and
+                 om1 < abs(om2)      and
+                 om1 < abs(-om2)   and
+                 om2 >= om1      and
+                 om2 >= abs(om1)   and
+                 om2 >= abs(-om1)   and
+                 om2 >= abs(-om1)   and
+                 om2 > om1      and
+                 om2 > abs(om1)      and
+                 om2 > abs(-om1)   )
+      report "***FAILED TEST: c07s02b02x00p02n01i01986 - Relational operators truth table test for data type of Physical failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01986arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1987.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1987.vhd
new file mode 100644
index 0000000..a8d01ca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1987.vhd
@@ -0,0 +1,117 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1987.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01987ent IS
+END c07s02b02x00p02n01i01987ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01987arch OF c07s02b02x00p02n01i01987ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable r1, r2, r3, r4 : real;
+  BEGIN
+
+    r1 := 69.0;
+    r2 := 50.0;
+    r3 := (-69.0);
+    r4 := (-50.0);
+
+    assert NOT(     real'high > real'low   and
+                    real'high >= real'low   and
+                    real'high > 0.0   and
+                    real'high >= 0.0   and
+                    real'low < 0.0      and
+                    real'low <= 0.0   and
+                    real'high /= real'low   and
+
+                    r1 > r2   and
+                    r1 >= r2   and
+                    r1 > 0.0   and
+                    r1 /= r2   and
+                    r2 < r1   and
+                    r2 <= r1   and
+                    
+                    r4 > r3   and
+                    r4 >= r3   and
+                    r4 < 0.0   and
+                    r4 /= r3   and
+                    r3 < r4   and
+                    r3 <= r4   and
+                    
+                    r1 > r3   and
+                    r2 >= r4   and
+                    r4 < r1   and
+                    r1 /= r3   and
+                    r2 /= r4   and
+                    r3 < r1   and
+                    r4 <= r2   and
+                    
+                    3.14E1 > 3.10E1   and
+                    5.7E-9 < 5.7E+9 )
+      report "***PASSED TEST: c07s02b02x00p02n01i01987"
+      severity NOTE;
+    assert (     real'high > real'low   and
+                 real'high >= real'low   and
+                 real'high > 0.0   and
+                 real'high >= 0.0   and
+                 real'low < 0.0      and
+                 real'low <= 0.0   and
+                 real'high /= real'low   and
+
+                 r1 > r2   and
+                 r1 >= r2   and
+                 r1 > 0.0   and
+                 r1 /= r2   and
+                 r2 < r1   and
+                 r2 <= r1   and
+                 
+                 r4 > r3   and
+                 r4 >= r3   and
+                 r4 < 0.0   and
+                 r4 /= r3   and
+                 r3 < r4   and
+                 r3 <= r4   and
+                 
+                 r1 > r3   and
+                 r2 >= r4   and
+                 r4 < r1   and
+                 r1 /= r3   and
+                 r2 /= r4   and
+                 r3 < r1   and
+                 r4 <= r2   and
+                 
+                 3.14E1 > 3.10E1   and
+                 5.7E-9 < 5.7E+9 )
+      report "***FAILED TEST: c07s02b02x00p02n01i01987 - Relational operators truth table test for data type of Real failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01987arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1988.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1988.vhd
new file mode 100644
index 0000000..45e875d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1988.vhd
@@ -0,0 +1,204 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1988.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p02n01i01988ent IS
+END c07s02b02x00p02n01i01988ent;
+
+ARCHITECTURE c07s02b02x00p02n01i01988arch OF c07s02b02x00p02n01i01988ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A : bit_vector (1 to 32);
+    variable B : bit_vector (32 downto 1);
+    variable C : bit_vector (15 downto 0);
+    variable D : bit_vector (0 to 15);
+    variable E : bit_vector (0 to 47);
+    variable F : bit_vector (47 downto 0);
+  BEGIN
+
+    A := x"ffffffff";
+    B := x"00000000";
+    C := x"ffff";
+    D := x"0000";
+    E := x"ffffffffffff";
+    F := x"000000000000";
+
+    assert NOT(    A = A      and
+                   A /= B      and
+                   A /= C      and
+                   A /= D      and
+                   A /= E      and
+                   A /= F      and
+                   B /= A      and
+                   B = B      and
+                   B /= C      and
+                   B /= D      and
+                   B /= E      and
+                   B /= F      and
+                   C /= A      and
+                   C /= B      and
+                   C = C      and
+                   C /= D      and
+                   C /= E      and
+                   C /= F      and
+                   D /= A      and
+                   D /= B      and
+                   D /= C      and
+                   D = D      and
+                   D /= E      and
+                   D /= F      and
+                   E /= A      and
+                   E /= B      and
+                   E /= C      and
+                   E /= D      and
+                   E = E      and
+                   E /= F      and
+                   F /= A      and
+                   F /= B      and
+                   F /= C      and
+                   F /= D      and
+                   F /= E      and
+                   F = F      and
+                   A <= A      and
+                   A > B      and
+                   A > C      and
+                   A > D      and
+                   A < E      and
+                   A > F      and
+                   B < A      and
+                   B <= B      and
+                   B < C      and
+                   B > D      and
+                   B < E      and
+                   B < F      and
+                   C < A      and
+                   C > B      and
+                   C <= C      and
+                   C > D      and
+                   C < E      and
+                   C > F      and
+                   D < A      and
+                   D < B      and
+                   D < C      and
+                   D <= D      and
+                   D < E      and
+                   D < F      and
+                   E > A      and
+                   E > B      and
+                   E > C      and
+                   E > D      and
+                   E <= E      and
+                   E > F      and
+                   F < A      and
+                   F > B      and
+                   F < C      and
+                   F > D      and
+                   F < E      and
+                   F <= F)
+      report "***PASSED TEST: c07s02b02x00p02n01i01988"
+      severity NOTE;
+    assert (    A = A      and
+                A /= B      and
+                A /= C      and
+                A /= D      and
+                A /= E      and
+                A /= F      and
+                B /= A      and
+                B = B      and
+                B /= C      and
+                B /= D      and
+                B /= E      and
+                B /= F      and
+                C /= A      and
+                C /= B      and
+                C = C      and
+                C /= D      and
+                C /= E      and
+                C /= F      and
+                D /= A      and
+                D /= B      and
+                D /= C      and
+                D = D      and
+                D /= E      and
+                D /= F      and
+                E /= A      and
+                E /= B      and
+                E /= C      and
+                E /= D      and
+                E = E      and
+                E /= F      and
+                F /= A      and
+                F /= B      and
+                F /= C      and
+                F /= D      and
+                F /= E      and
+                F = F      and
+                A <= A      and
+                A > B      and
+                A > C      and
+                A > D      and
+                A < E      and
+                A > F      and
+                B < A      and
+                B <= B      and
+                B < C      and
+                B > D      and
+                B < E      and
+                B < F      and
+                C < A      and
+                C > B      and
+                C <= C      and
+                C > D      and
+                C < E      and
+                C > F      and
+                D < A      and
+                D < B      and
+                D < C      and
+                D <= D      and
+                D < E      and
+                D < F      and
+                E > A      and
+                E > B      and
+                E > C      and
+                E > D      and
+                E <= E      and
+                E > F      and
+                F < A      and
+                F > B      and
+                F < C      and
+                F > D      and
+                F < E      and
+                F <= F)
+      report "***FAILED TEST: c07s02b02x00p02n01i01988 - Relational operators truth table test for data type of Bit_vector failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p02n01i01988arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1991.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1991.vhd
new file mode 100644
index 0000000..17952c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1991.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1991.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01991ent IS
+END c07s02b02x00p07n01i01991ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01991arch OF c07s02b02x00p07n01i01991ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type   ENUM is ( ONE, TWO, THREE, FOUR, FIVE );
+    variable k : integer := 0;
+  BEGIN
+    if (ONE /= TWO) then
+      k := 5;
+    else
+      k := 3;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p07n01i01991" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p07n01i01991 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01991arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1992.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1992.vhd
new file mode 100644
index 0000000..6efeae5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1992.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1992.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01992ent IS
+END c07s02b02x00p07n01i01992ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01992arch OF c07s02b02x00p07n01i01992ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 6;
+  BEGIN
+    if (m /= 5) then
+      k := 5;
+    else
+      k := 3;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p07n01i01992"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p07n01i01992 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01992arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1993.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1993.vhd
new file mode 100644
index 0000000..1a9d15e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1993.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1993.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01993ent IS
+END c07s02b02x00p07n01i01993ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01993arch OF c07s02b02x00p07n01i01993ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : real    := 5.5;
+  BEGIN
+    if (m /= 4.5) then
+      k := 5;
+    else
+      k := 3;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p07n01i01993" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p07n01i01993 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01993arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1994.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1994.vhd
new file mode 100644
index 0000000..bc3c073
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1994.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1994.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01994ent IS
+END c07s02b02x00p07n01i01994ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01994arch OF c07s02b02x00p07n01i01994ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CHAR_RECORD is record
+                          C1, C2, C3 : CHARACTER;
+                        end record;
+    variable k : integer     := 0;
+    variable m : CHAR_RECORD := ('a','b','c');
+  BEGIN
+    if (m /= ('a','b','b')) then
+      k := 5;
+    else
+      k := 3;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p07n01i01994" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p07n01i01994 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01994arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1995.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1995.vhd
new file mode 100644
index 0000000..4494382
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1995.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1995.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01995ent IS
+END c07s02b02x00p07n01i01995ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01995arch OF c07s02b02x00p07n01i01995ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 1 to 260
+      units
+        A;
+        B = 10 A;
+        C = 10 B;
+      end units;
+    variable k : integer    := 0;
+    variable m : PHYS    := 10 A; 
+  BEGIN
+    if (m /= 2 B) then
+      k := 5;
+    else
+      k := 3;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p07n01i01995"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p07n01i01995 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01995arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1996.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1996.vhd
new file mode 100644
index 0000000..5e75162
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1996.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1996.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i01996ent IS
+END c07s02b02x00p07n02i01996ent;
+
+ARCHITECTURE c07s02b02x00p07n02i01996arch OF c07s02b02x00p07n02i01996ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM is ( ONE, TWO, THREE, FOUR, FIVE );
+    variable k : integer := 0;
+  BEGIN
+    if (ONE = ONE) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i01996"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i01996 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i01996arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1997.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1997.vhd
new file mode 100644
index 0000000..6b7e2c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1997.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1997.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i01997ent IS
+END c07s02b02x00p07n02i01997ent;
+
+ARCHITECTURE c07s02b02x00p07n02i01997arch OF c07s02b02x00p07n02i01997ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 5;
+  BEGIN
+    if (m = 5) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i01997"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i01997 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i01997arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1998.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1998.vhd
new file mode 100644
index 0000000..ab5c00a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1998.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1998.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i01998ent IS
+END c07s02b02x00p07n02i01998ent;
+
+ARCHITECTURE c07s02b02x00p07n02i01998arch OF c07s02b02x00p07n02i01998ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : real    := 5.5;
+  BEGIN
+    if (m = 5.5) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i01998"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i01998 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i01998arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc1999.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc1999.vhd
new file mode 100644
index 0000000..66cd6f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc1999.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1999.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i01999ent IS
+END c07s02b02x00p07n02i01999ent;
+
+ARCHITECTURE c07s02b02x00p07n02i01999arch OF c07s02b02x00p07n02i01999ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 1 to 1000
+      units
+        A;
+        B = 10 A;
+        C = 10 B;
+      end units;
+    variable k : integer := 0;
+    variable m : PHYS    := 10 A;
+  BEGIN
+    if (m = 1 B) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i01999"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i01999 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i01999arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2000.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2000.vhd
new file mode 100644
index 0000000..d968b30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2000.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2000.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i02000ent IS
+END c07s02b02x00p07n02i02000ent;
+
+ARCHITECTURE c07s02b02x00p07n02i02000arch OF c07s02b02x00p07n02i02000ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    ENUM       is ( ONE, TWO, THREE, FOUR, FIVE );
+    type    NEW_INTEGER     is range integer'left to integer'right;
+    type    UN_INT_ARRAY    is array ( ENUM range <>) of NEW_INTEGER;
+    subtype INT_ARRAY       is UN_INT_ARRAY( ONE to TWO );
+    variable k : integer  := 0;
+    variable m : INT_ARRAY:= (1,2);
+  BEGIN
+    if (m = INT_ARRAY'(1,2)) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i02000"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i02000 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i02000arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2001.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2001.vhd
new file mode 100644
index 0000000..10188b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2001.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2001.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n02i02001ent IS
+END c07s02b02x00p07n02i02001ent;
+
+ARCHITECTURE c07s02b02x00p07n02i02001arch OF c07s02b02x00p07n02i02001ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CHAR_RECORD is record
+                          C1, C2, C3 : CHARACTER;
+                        end record;
+    variable k : integer  := 0;
+    variable m : CHAR_RECORD := ('a','b','c');
+  BEGIN
+    if (m = CHAR_RECORD'('a','b','c')) then
+      k := 5;
+    else
+      k := 0;
+    end if;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p07n02i02001"
+      severity NOTE;
+    assert (k=5)
+      report "***FAILED TEST: c07s02b02x00p07n02i02001 - The equality operator returns the value TRUE if the two operands are equal, and the value FALSE otherwise."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n02i02001arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2004.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2004.vhd
new file mode 100644
index 0000000..e3a1189
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2004.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2004.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p08n02i02004ent IS
+END c07s02b02x00p08n02i02004ent;
+
+ARCHITECTURE c07s02b02x00p08n02i02004arch OF c07s02b02x00p08n02i02004ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    array_x    is array (positive range <>) of integer;
+    subtype    array_three    is array_x (1 to 6) ;
+    subtype    array_four     is array_x (6 downto 1) ;
+    variable    x : array_four  := (1,2,3,4,5,6);
+    variable    y : array_three := (1,2,3,4,5,6);
+  BEGIN
+    assert NOT(x=y)
+      report "***PASSED TEST: c07s02b02x00p08n02i02004"
+      severity NOTE;
+    assert ( x=y )
+      report "***FAILED TEST: c07s02b02x00p08n02i02004 - Two composite values of the same type are equal if and only if for each element of the left operand there is a matching element of the right operand and vice versa."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p08n02i02004arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2005.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2005.vhd
new file mode 100644
index 0000000..f487125
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2005.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2005.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p08n02i02005ent IS
+END c07s02b02x00p08n02i02005ent;
+
+ARCHITECTURE c07s02b02x00p08n02i02005arch OF c07s02b02x00p08n02i02005ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_type is array (1 to 10) of integer;
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : real;
+                  ele_3 : boolean;
+                  ele_4 : array_type;
+                end record;
+    variable x : rec := (1,1.2,true,(1,2,3,4,5,6,7,8,9,0));
+    variable y : rec := (1,1.2,true,(0,1,2,3,4,5,6,7,8,9));
+  BEGIN
+    assert NOT(x/=y)
+      report "***PASSED TEST: c07s02b02x00p08n02i02005"
+      severity NOTE;
+    assert ( x/=y )
+      report "***FAILED TEST: c07s02b02x00p08n02i02005 - Two composite values of the same type are equal if and only if for each element of the left operand there is a matching element of the right operand and vice versa."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p08n02i02005arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2006.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2006.vhd
new file mode 100644
index 0000000..e62e192
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2006.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2006.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p08n02i02006ent IS
+END c07s02b02x00p08n02i02006ent;
+
+ARCHITECTURE c07s02b02x00p08n02i02006arch OF c07s02b02x00p08n02i02006ent IS
+
+  TYPE    real_vector is array (integer range <>) of REAL;
+  SUBTYPE real_8 is real_vector(0 to 7);
+  SUBTYPE real_4 is real_vector(0 to 3);
+
+BEGIN
+  TESTING: PROCESS
+
+    CONSTANT slice_8a : real_8 := (1.0,2.0,3.0,4.0,5.0,6.0,7.0,8.0);
+    VARIABLE slice_8b : real_8 := (1.0,2.0,3.0,4.0,5.0,6.0,7.0,8.0);
+    VARIABLE target_1 : boolean;
+    VARIABLE target_2 : boolean;
+
+  BEGIN
+    target_1 := slice_8a (3 to 3)  = slice_8b (3 to 3);
+    target_2 := slice_8a (3 to 3) /= slice_8b (4 to 4);
+
+    assert NOT(target_1 and target_2) 
+      report "***PASSED TEST: c07s02b02x00p08n02i02006"
+      severity NOTE;
+    assert (target_1 and target_2) 
+      report "***FAILED TEST: c07s02b02x00p08n02i02006 - Two single element REAL slices are operable over the set of relational operations." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p08n02i02006arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2007.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2007.vhd
new file mode 100644
index 0000000..61261ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2007.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2007.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p08n03i02007ent IS
+END c07s02b02x00p08n03i02007ent;
+
+ARCHITECTURE c07s02b02x00p08n03i02007arch OF c07s02b02x00p08n03i02007ent IS
+  signal Q : BIT_VECTOR(0 downto 7);
+  signal S : BIT_VECTOR(7 to 0) ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(S=Q)
+      report "***PASSED TEST: c07s02b02x00p08n03i02007"
+      severity NOTE;
+    assert ( S=Q )
+      report "***FAILED TEST: c07s02b02x00p08n03i02007 - Two null arrays of the same type are always equal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p08n03i02007arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2008.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2008.vhd
new file mode 100644
index 0000000..532b757
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2008.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2008.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p08n04i02008ent IS
+END c07s02b02x00p08n04i02008ent;
+
+ARCHITECTURE c07s02b02x00p08n04i02008arch OF c07s02b02x00p08n04i02008ent IS
+  type ARR is access BIT_VECTOR ;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : ARR := null ;
+    variable V2 : ARR := null ;
+  BEGIN
+    assert NOT( V1=V2 )
+      report "***PASSED TEST: c07s02b02x00p08n04i02008"
+      severity NOTE;
+    assert ( V1=V2 )
+      report "***FAILED TEST: c07s02b02x00p08n04i02008 - Two values of an access type are equal if both are equal to the null value of the access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p08n04i02008arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc201.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc201.vhd
new file mode 100644
index 0000000..6443b8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc201.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc201.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p04n01i00201ent IS
+END c03s01b00x00p04n01i00201ent;
+
+ARCHITECTURE c03s01b00x00p04n01i00201arch OF c03s01b00x00p04n01i00201ent IS
+  type a is range (1+1) to 10;
+BEGIN
+  TESTING: PROCESS
+    variable k : a := 6;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b00x00p04n01i00201" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b00x00p04n01i00201 -The range must be either a range attribute name or two simple expressions combined with a direction operator." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p04n01i00201arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2010.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2010.vhd
new file mode 100644
index 0000000..883aaea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2010.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2010.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p10n01i02010ent IS
+END c07s02b02x00p10n01i02010ent;
+
+ARCHITECTURE c07s02b02x00p10n01i02010arch OF c07s02b02x00p10n01i02010ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type a1 is array (1 to 5) of integer;
+    variable a : a1 := (1,2,3,4,5);
+    variable b : a1 := (2,3,4,5,6);
+    variable k : integer := 0;
+  BEGIN
+    if ((a < b) or (a <= b) or (a > b) or (a >= b)) then
+      -- No_failure_here
+      k := 5;
+    end if;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c07s02b02x00p10n01i02010" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c07s02b02x00p10n01i02010 - Ordering operators are defined only for scalar type or any discrete array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p10n01i02010arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2011.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2011.vhd
new file mode 100644
index 0000000..80a1baa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2011.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2011.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p10n01i02011ent IS
+END c07s02b02x00p10n01i02011ent;
+
+ARCHITECTURE c07s02b02x00p10n01i02011arch OF c07s02b02x00p10n01i02011ent IS
+
+  TYPE    int_vector is array (integer range <>) of INTEGER;
+  SUBTYPE int_8 is int_vector(0 to 7);
+  SUBTYPE int_4 is int_vector(0 to 3);
+
+BEGIN
+  TESTING: PROCESS
+    CONSTANT slice_8a : int_8 := (1,2,3,4,5,6,7,8);
+    VARIABLE slice_8b : int_8 := (1,2,3,4,5,6,7,8);
+    VARIABLE target_1 : boolean;
+    VARIABLE target_2 : boolean;
+    VARIABLE target_3 : boolean;
+    VARIABLE target_4 : boolean;
+  BEGIN
+
+    target_1 := slice_8a (3 to 3) < slice_8b (6 to 6);
+    
+    target_2 := slice_8a (3 to 3) <= slice_8b (7 to 7);
+    
+    target_3 := slice_8a (3 to 3) > slice_8b (2 to 2);
+    
+    target_4 := slice_8a (3 to 3) >= slice_8b (1 to 1);
+
+    wait for 5 ns;
+    assert NOT(   target_1 and
+                  target_2 and
+                  target_3 and
+                  target_4 )
+      report "***PASSED TEST: c07s02b02x00p10n01i02011" 
+      severity NOTE;
+    assert (   target_1 and
+               target_2 and
+               target_3 and
+               target_4 )
+      report "***FAILED TEST: c07s02b02x00p10n01i02011 - Ordering operators are loperable over the set of relational operations." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p10n01i02011arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2012.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2012.vhd
new file mode 100644
index 0000000..9ccadd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2012.vhd
@@ -0,0 +1,251 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2012.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p10n01i02012ent IS
+END c07s02b02x00p10n01i02012ent;
+
+ARCHITECTURE c07s02b02x00p10n01i02012arch OF c07s02b02x00p10n01i02012ent IS
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     8;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+
+  SUBTYPE st_scl1 IS CHARACTER                              ;
+  SUBTYPE st_scl3 IS INTEGER   RANGE   1   TO   INTEGER'HIGH;
+  
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
+
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
+
+  CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
+  CONSTANT C2_scl1 : st_scl1 := 'Z' ;
+  CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
+  CONSTANT C2_scl3 : st_scl3 :=   8 ;
+
+  CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
+  CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
+                                     OTHERS                      =>C0_scl1);
+  CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
+  CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
+                                     OTHERS                      =>C0_scl3);
+
+BEGIN
+  TESTING: PROCESS
+--
+--          Constant declarations - for unconstrained types
+--           other composite type declarations are in package "COMPOSITE"
+--
+    CONSTANT C0_usa1_1 : t_usa1_1 (st_ind1 ) := C0_csa1_1;
+    CONSTANT C0_usa1_3 : t_usa1_3 (st_ind3 ) := C0_csa1_3;
+
+    CONSTANT C2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
+    CONSTANT C2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
+--
+--          Composite VARIABLE declarations
+--
+    VARIABLE V0_usa1_1 : t_usa1_1 (st_ind1 ) ;
+    VARIABLE V0_usa1_3 : t_usa1_3 (st_ind3 ) ;
+    VARIABLE V0_csa1_1 : t_csa1_1 ;
+    VARIABLE V0_csa1_3 : t_csa1_3 ;
+
+    VARIABLE V2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
+    VARIABLE V2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
+    VARIABLE V2_csa1_1 : t_csa1_1 := C2_csa1_1;
+    VARIABLE V2_csa1_3 : t_csa1_3 := C2_csa1_3;
+--
+--          Arrays of the same type, element values, different length
+--
+    VARIABLE V3_usa1_1 : t_usa1_1 ( 1  TO  7  ) ;
+    VARIABLE V3_usa1_3 : t_usa1_3 ('a' TO 'c' ) ;
+--
+    CONSTANT msg1 : STRING := "ERROR: less than operator failure: ";
+    CONSTANT msg2 : STRING := "ERROR: less than or equal operator failure: ";
+  BEGIN
+--
+--          Check less than operator - CONSTANTS (from package 'composite')
+    --
+    ASSERT C0_usa1_1 < C2_usa1_1 REPORT msg1 & "C0<C2_usa1_1" SEVERITY FAILURE;
+    ASSERT C0_usa1_3 < C2_usa1_3 REPORT msg1 & "C0<C2_usa1_3" SEVERITY FAILURE;
+    ASSERT C0_csa1_1 < C2_csa1_1 REPORT msg1 & "C0<C2_csa1_1" SEVERITY FAILURE;
+    ASSERT C0_csa1_3 < C2_csa1_3 REPORT msg1 & "C0<C2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than operator - VARIABLES
+--
+    ASSERT V0_usa1_1 < V2_usa1_1 REPORT msg1 & "V0<V2_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 < V2_usa1_3 REPORT msg1 & "V0<V2_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 < V2_csa1_1 REPORT msg1 & "V0<V2_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 < V2_csa1_3 REPORT msg1 & "V0<V2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than operator - VARIABLES and CONSTANTS
+--
+    ASSERT V0_usa1_1 < C2_usa1_1 REPORT msg1 & "V0<C2_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 < C2_usa1_3 REPORT msg1 & "V0<C2_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 < C2_csa1_1 REPORT msg1 & "V0<C2_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 < C2_csa1_3 REPORT msg1 & "V0<C2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than operator - same type, element values : diff array length
+--
+    ASSERT V3_usa1_1 < V2_usa1_1 REPORT msg1 & "V3<V2_usa1_1" SEVERITY FAILURE;
+    ASSERT V3_usa1_3 < V2_usa1_3 REPORT msg1 & "V3<V2_usa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - CONSTANTS (from package 'composite')
+--
+    ASSERT C0_usa1_1 <= C2_usa1_1 REPORT msg2 & "C0<=C2_usa1_1" SEVERITY FAILURE;
+    ASSERT C0_usa1_3 <= C2_usa1_3 REPORT msg2 & "C0<=C2_usa1_3" SEVERITY FAILURE;
+    ASSERT C0_csa1_1 <= C2_csa1_1 REPORT msg2 & "C0<=C2_csa1_1" SEVERITY FAILURE;
+    ASSERT C0_csa1_3 <= C2_csa1_3 REPORT msg2 & "C0<=C2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - VARIABLES
+--
+    ASSERT V0_usa1_1 <= V2_usa1_1 REPORT msg2 & "V0<=V2_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 <= V2_usa1_3 REPORT msg2 & "V0<=V2_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 <= V2_csa1_1 REPORT msg2 & "V0<=V2_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 <= V2_csa1_3 REPORT msg2 & "V0<=V2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - VARIABLES and CONSTANTS
+--
+    ASSERT V0_usa1_1 <= C2_usa1_1 REPORT msg2 & "V0<=C2_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 <= C2_usa1_3 REPORT msg2 & "V0<=C2_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 <= C2_csa1_1 REPORT msg2 & "V0<=C2_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 <= C2_csa1_3 REPORT msg2 & "V0<=C2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - same type, element values : diff array length
+--
+    ASSERT V3_usa1_1 <= V2_usa1_1 REPORT msg2 & "V3<=V2_usa1_1" SEVERITY FAILURE;
+    ASSERT V3_usa1_3 <= V2_usa1_3 REPORT msg2 & "V3<=V2_usa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - CONSTANTS (from package 'composite')
+--
+    ASSERT C2_usa1_1 <= C2_usa1_1 REPORT msg2 & "C2<=C2_usa1_1" SEVERITY FAILURE;
+    ASSERT C2_usa1_3 <= C2_usa1_3 REPORT msg2 & "C2<=C2_usa1_3" SEVERITY FAILURE;
+    ASSERT C2_csa1_1 <= C2_csa1_1 REPORT msg2 & "C2<=C2_csa1_1" SEVERITY FAILURE;
+    ASSERT C2_csa1_3 <= C2_csa1_3 REPORT msg2 & "C2<=C2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - VARIABLES
+--
+    ASSERT V2_usa1_1 <= V2_usa1_1 REPORT msg2 & "V2<=V2_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 <= V2_usa1_3 REPORT msg2 & "V2<=V2_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 <= V2_csa1_1 REPORT msg2 & "V2<=V2_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 <= V2_csa1_3 REPORT msg2 & "V2<=V2_csa1_3" SEVERITY FAILURE;
+--
+--          Check less than or equal operator - VARIABLES and CONSTANTS
+--
+    ASSERT V2_usa1_1 <= C2_usa1_1 REPORT msg2 & "V2<=C2_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 <= C2_usa1_3 REPORT msg2 & "V2<=C2_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 <= C2_csa1_1 REPORT msg2 & "V2<=C2_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 <= C2_csa1_3 REPORT msg2 & "V2<=C2_csa1_3" SEVERITY FAILURE;
+    assert NOT(   C0_usa1_1 < C2_usa1_1   and
+                  C0_usa1_3 < C2_usa1_3   and
+                  C0_csa1_1 < C2_csa1_1   and
+                  C0_csa1_3 < C2_csa1_3   and
+                  V0_usa1_1 < V2_usa1_1   and
+                  V0_usa1_3 < V2_usa1_3   and
+                  V0_csa1_1 < V2_csa1_1   and
+                  V0_csa1_3 < V2_csa1_3   and
+                  V0_usa1_1 < C2_usa1_1   and
+                  V0_usa1_3 < C2_usa1_3   and
+                  V0_csa1_1 < C2_csa1_1   and
+                  V0_csa1_3 < C2_csa1_3   and
+                  V3_usa1_1 < V2_usa1_1   and
+                  V3_usa1_3 < V2_usa1_3   and
+                  C0_usa1_1 <= C2_usa1_1   and
+                  C0_usa1_3 <= C2_usa1_3   and
+                  C0_csa1_1 <= C2_csa1_1   and
+                  C0_csa1_3 <= C2_csa1_3   and
+                  V0_usa1_1 <= V2_usa1_1   and
+                  V0_usa1_3 <= V2_usa1_3   and
+                  V0_csa1_1 <= V2_csa1_1   and
+                  V0_csa1_3 <= V2_csa1_3   and
+                  V0_usa1_1 <= C2_usa1_1   and
+                  V0_usa1_3 <= C2_usa1_3   and
+                  V0_csa1_1 <= C2_csa1_1   and
+                  V0_csa1_3 <= C2_csa1_3   and
+                  V3_usa1_1 <= V2_usa1_1   and
+                  V3_usa1_3 <= V2_usa1_3   and
+                  C2_usa1_1 <= C2_usa1_1   and
+                  C2_usa1_3 <= C2_usa1_3   and
+                  C2_csa1_1 <= C2_csa1_1   and
+                  C2_csa1_3 <= C2_csa1_3   and
+                  V2_usa1_1 <= V2_usa1_1   and
+                  V2_usa1_3 <= V2_usa1_3   and
+                  V2_csa1_1 <= V2_csa1_1   and
+                  V2_csa1_3 <= V2_csa1_3   and
+                  V2_usa1_1 <= C2_usa1_1   and
+                  V2_usa1_3 <= C2_usa1_3   and
+                  V2_csa1_1 <= C2_csa1_1   and
+                  V2_csa1_3 <= C2_csa1_3   )
+      report "***PASSED TEST: c07s02b02x00p10n01i02012" 
+      severity NOTE;
+    assert (   C0_usa1_1 < C2_usa1_1   and
+               C0_usa1_3 < C2_usa1_3   and
+               C0_csa1_1 < C2_csa1_1   and
+               C0_csa1_3 < C2_csa1_3   and
+               V0_usa1_1 < V2_usa1_1   and
+               V0_usa1_3 < V2_usa1_3   and
+               V0_csa1_1 < V2_csa1_1   and
+               V0_csa1_3 < V2_csa1_3   and
+               V0_usa1_1 < C2_usa1_1   and
+               V0_usa1_3 < C2_usa1_3   and
+               V0_csa1_1 < C2_csa1_1   and
+               V0_csa1_3 < C2_csa1_3   and
+               V3_usa1_1 < V2_usa1_1   and
+               V3_usa1_3 < V2_usa1_3   and
+               C0_usa1_1 <= C2_usa1_1   and
+               C0_usa1_3 <= C2_usa1_3   and
+               C0_csa1_1 <= C2_csa1_1   and
+               C0_csa1_3 <= C2_csa1_3   and
+               V0_usa1_1 <= V2_usa1_1   and
+               V0_usa1_3 <= V2_usa1_3   and
+               V0_csa1_1 <= V2_csa1_1   and
+               V0_csa1_3 <= V2_csa1_3   and
+               V0_usa1_1 <= C2_usa1_1   and
+               V0_usa1_3 <= C2_usa1_3   and
+               V0_csa1_1 <= C2_csa1_1   and
+               V0_csa1_3 <= C2_csa1_3   and
+               V3_usa1_1 <= V2_usa1_1   and
+               V3_usa1_3 <= V2_usa1_3   and
+               C2_usa1_1 <= C2_usa1_1   and
+               C2_usa1_3 <= C2_usa1_3   and
+               C2_csa1_1 <= C2_csa1_1   and
+               C2_csa1_3 <= C2_csa1_3   and
+               V2_usa1_1 <= V2_usa1_1   and
+               V2_usa1_3 <= V2_usa1_3   and
+               V2_csa1_1 <= V2_csa1_1   and
+               V2_csa1_3 <= V2_csa1_3   and
+               V2_usa1_1 <= C2_usa1_1   and
+               V2_usa1_3 <= C2_usa1_3   and
+               V2_csa1_1 <= C2_csa1_1   and
+               V2_csa1_3 <= C2_csa1_3   )
+      report "***FAILED TEST: c07s02b02x00p10n01i02012 - Ordering operators <, <= for composite type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p10n01i02012arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2013.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2013.vhd
new file mode 100644
index 0000000..4d43b28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2013.vhd
@@ -0,0 +1,252 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2013.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p10n01i02013ent IS
+END c07s02b02x00p10n01i02013ent;
+
+ARCHITECTURE c07s02b02x00p10n01i02013arch OF c07s02b02x00p10n01i02013ent IS
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     8;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+
+  SUBTYPE st_scl1 IS CHARACTER                              ;
+  SUBTYPE st_scl3 IS INTEGER   RANGE   1   TO   INTEGER'HIGH;
+  
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
+
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
+
+  CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
+  CONSTANT C2_scl1 : st_scl1 := 'Z' ;
+  CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
+  CONSTANT C2_scl3 : st_scl3 :=   8 ;
+
+  CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
+  CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
+                                     OTHERS                      =>C0_scl1);
+  CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
+  CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
+                                     OTHERS                      =>C0_scl3);
+
+BEGIN
+  TESTING: PROCESS
+--
+--          Constant declarations - for unconstrained types
+--           other composite type declarations are in package "COMPOSITE"
+--
+    CONSTANT C0_usa1_1 : t_usa1_1 (st_ind1 ) := C0_csa1_1;
+    CONSTANT C0_usa1_3 : t_usa1_3 (st_ind3 ) := C0_csa1_3;
+
+    CONSTANT C2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
+    CONSTANT C2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
+--
+--          Composite VARIABLE declarations
+--
+    VARIABLE V0_usa1_1 : t_usa1_1 (st_ind1 ) ;
+    VARIABLE V0_usa1_3 : t_usa1_3 (st_ind3 ) ;
+    VARIABLE V0_csa1_1 : t_csa1_1 ;
+    VARIABLE V0_csa1_3 : t_csa1_3 ;
+
+    VARIABLE V2_usa1_1 : t_usa1_1 (st_ind1 ) := C2_csa1_1;
+    VARIABLE V2_usa1_3 : t_usa1_3 (st_ind3 ) := C2_csa1_3;
+    VARIABLE V2_csa1_1 : t_csa1_1 := C2_csa1_1;
+    VARIABLE V2_csa1_3 : t_csa1_3 := C2_csa1_3;
+--
+--          Arrays of the same type, element values, different length
+--
+    VARIABLE V3_usa1_1 : t_usa1_1 ( 1  TO  7  ) ;
+    VARIABLE V3_usa1_3 : t_usa1_3 ('a' TO 'c' ) ;
+--
+    CONSTANT msg1 : STRING := "ERROR: greater than operator failure: ";
+    CONSTANT msg2 : STRING := "ERROR: greater than or equal operator failure: ";
+  BEGIN
+--
+--          Check greater than operator - CONSTANTS (from package 'composite')
+--
+    ASSERT C2_usa1_1 > C0_usa1_1 REPORT msg1 & "C2>C0_usa1_1" SEVERITY FAILURE;
+    ASSERT C2_usa1_3 > C0_usa1_3 REPORT msg1 & "C2>C0_usa1_3" SEVERITY FAILURE;
+    ASSERT C2_csa1_1 > C0_csa1_1 REPORT msg1 & "C2>C0_csa1_1" SEVERITY FAILURE;
+    ASSERT C2_csa1_3 > C0_csa1_3 REPORT msg1 & "C2>C0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than operator - VARIABLES
+--
+    ASSERT V2_usa1_1 > V0_usa1_1 REPORT msg1 & "V2>V0_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 > V0_usa1_3 REPORT msg1 & "V2>V0_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 > V0_csa1_1 REPORT msg1 & "V2>V0_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 > V0_csa1_3 REPORT msg1 & "V2>V0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than operator - VARIABLES and CONSTANTS
+--
+    ASSERT V2_usa1_1 > C0_usa1_1 REPORT msg1 & "V2>C0_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 > C0_usa1_3 REPORT msg1 & "V2>C0_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 > C0_csa1_1 REPORT msg1 & "V2>C0_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 > C0_csa1_3 REPORT msg1 & "V2>C0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than operator - same type, element values : diff array length
+--
+    ASSERT V2_usa1_1 > V3_usa1_1 REPORT msg1 & "V2>V3_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 > V3_usa1_3 REPORT msg1 & "V2>V3_usa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - CONSTANTS (from package 'composite')
+--
+    ASSERT C2_usa1_1 >= C0_usa1_1 REPORT msg2 & "C2>=C0_usa1_1" SEVERITY FAILURE;
+    ASSERT C2_usa1_3 >= C0_usa1_3 REPORT msg2 & "C2>=C0_usa1_3" SEVERITY FAILURE;
+    ASSERT C2_csa1_1 >= C0_csa1_1 REPORT msg2 & "C2>=C0_csa1_1" SEVERITY FAILURE;
+    ASSERT C2_csa1_3 >= C0_csa1_3 REPORT msg2 & "C2>=C0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - VARIABLES
+--
+    ASSERT V2_usa1_1 >= V0_usa1_1 REPORT msg2 & "V2>=V0_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 >= V0_usa1_3 REPORT msg2 & "V2>=V0_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 >= V0_csa1_1 REPORT msg2 & "V2>=V0_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 >= V0_csa1_3 REPORT msg2 & "V2>=V0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - VARIABLES and CONSTANTS
+--
+    ASSERT V2_usa1_1 >= C0_usa1_1 REPORT msg2 & "V2>=C0_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 >= C0_usa1_3 REPORT msg2 & "V2>=C0_usa1_3" SEVERITY FAILURE;
+    ASSERT V2_csa1_1 >= C0_csa1_1 REPORT msg2 & "V2>=C0_csa1_1" SEVERITY FAILURE;
+    ASSERT V2_csa1_3 >= C0_csa1_3 REPORT msg2 & "V2>=C0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - same type, element values : diff array length
+--
+    ASSERT V2_usa1_1 >= V3_usa1_1 REPORT msg2 & "V2>=V3_usa1_1" SEVERITY FAILURE;
+    ASSERT V2_usa1_3 >= V3_usa1_3 REPORT msg2 & "V2>=V3_usa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - CONSTANTS (from package 'composite')
+--
+    ASSERT C0_usa1_1 >= C0_usa1_1 REPORT msg2 & "C0>=C0_usa1_1" SEVERITY FAILURE;
+    ASSERT C0_usa1_3 >= C0_usa1_3 REPORT msg2 & "C0>=C0_usa1_3" SEVERITY FAILURE;
+    ASSERT C0_csa1_1 >= C0_csa1_1 REPORT msg2 & "C0>=C0_csa1_1" SEVERITY FAILURE;
+    ASSERT C0_csa1_3 >= C0_csa1_3 REPORT msg2 & "C0>=C0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - VARIABLES
+--
+    ASSERT V0_usa1_1 >= V0_usa1_1 REPORT msg2 & "V0>=V0_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 >= V0_usa1_3 REPORT msg2 & "V0>=V0_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 >= V0_csa1_1 REPORT msg2 & "V0>=V0_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 >= V0_csa1_3 REPORT msg2 & "V0>=V0_csa1_3" SEVERITY FAILURE;
+--
+--          Check greater than or equal operator - VARIABLES and CONSTANTS
+--
+    ASSERT V0_usa1_1 >= C0_usa1_1 REPORT msg2 & "V0>=C0_usa1_1" SEVERITY FAILURE;
+    ASSERT V0_usa1_3 >= C0_usa1_3 REPORT msg2 & "V0>=C0_usa1_3" SEVERITY FAILURE;
+    ASSERT V0_csa1_1 >= C0_csa1_1 REPORT msg2 & "V0>=C0_csa1_1" SEVERITY FAILURE;
+    ASSERT V0_csa1_3 >= C0_csa1_3 REPORT msg2 & "V0>=C0_csa1_3" SEVERITY FAILURE;
+    wait for 5 ns;
+    assert NOT(   C2_usa1_1 > C0_usa1_1   and
+                  C2_usa1_3 > C0_usa1_3   and
+                  C2_csa1_1 > C0_csa1_1   and
+                  C2_csa1_3 > C0_csa1_3   and
+                  V2_usa1_1 > V0_usa1_1   and
+                  V2_usa1_3 > V0_usa1_3   and
+                  V2_csa1_1 > V0_csa1_1   and
+                  V2_csa1_3 > V0_csa1_3   and
+                  V2_usa1_1 > C0_usa1_1   and
+                  V2_usa1_3 > C0_usa1_3   and
+                  V2_csa1_1 > C0_csa1_1   and
+                  V2_csa1_3 > C0_csa1_3   and
+                  V2_usa1_1 > V3_usa1_1   and
+                  V2_usa1_3 > V3_usa1_3   and
+                  C2_usa1_1 >= C0_usa1_1   and
+                  C2_usa1_3 >= C0_usa1_3   and
+                  C2_csa1_1 >= C0_csa1_1   and
+                  C2_csa1_3 >= C0_csa1_3   and
+                  V2_usa1_1 >= V0_usa1_1   and
+                  V2_usa1_3 >= V0_usa1_3   and
+                  V2_csa1_1 >= V0_csa1_1   and
+                  V2_csa1_3 >= V0_csa1_3   and
+                  V2_usa1_1 >= C0_usa1_1   and
+                  V2_usa1_3 >= C0_usa1_3   and
+                  V2_csa1_1 >= C0_csa1_1   and   
+                  V2_csa1_3 >= C0_csa1_3   and
+                  V2_usa1_1 >= V3_usa1_1   and
+                  V2_usa1_3 >= V3_usa1_3   and
+                  C0_usa1_1 >= C0_usa1_1   and
+                  C0_usa1_3 >= C0_usa1_3   and
+                  C0_csa1_1 >= C0_csa1_1   and
+                  C0_csa1_1 >= C0_csa1_1   and
+                  V0_usa1_1 >= V0_usa1_1   and
+                  V0_usa1_3 >= V0_usa1_3   and
+                  V0_csa1_1 >= V0_csa1_1   and
+                  V0_csa1_3 >= V0_csa1_3   and
+                  V0_usa1_1 >= C0_usa1_1   and
+                  V0_usa1_3 >= C0_usa1_3   and
+                  V0_csa1_1 >= C0_csa1_1   and
+                  V0_csa1_3 >= C0_csa1_3   )
+      report "***PASSED TEST: c07s02b02x00p10n01i02013" 
+      severity NOTE;
+    assert (   C2_usa1_1 > C0_usa1_1   and
+               C2_usa1_3 > C0_usa1_3   and
+               C2_csa1_1 > C0_csa1_1   and
+               C2_csa1_3 > C0_csa1_3   and
+               V2_usa1_1 > V0_usa1_1   and
+               V2_usa1_3 > V0_usa1_3   and
+               V2_csa1_1 > V0_csa1_1   and
+               V2_csa1_3 > V0_csa1_3   and
+               V2_usa1_1 > C0_usa1_1   and
+               V2_usa1_3 > C0_usa1_3   and
+               V2_csa1_1 > C0_csa1_1   and
+               V2_csa1_3 > C0_csa1_3   and
+               V2_usa1_1 > V3_usa1_1   and
+               V2_usa1_3 > V3_usa1_3   and
+               C2_usa1_1 >= C0_usa1_1   and
+               C2_usa1_3 >= C0_usa1_3   and
+               C2_csa1_1 >= C0_csa1_1   and
+               C2_csa1_3 >= C0_csa1_3   and
+               V2_usa1_1 >= V0_usa1_1   and
+               V2_usa1_3 >= V0_usa1_3   and
+               V2_csa1_1 >= V0_csa1_1   and
+               V2_csa1_3 >= V0_csa1_3   and
+               V2_usa1_1 >= C0_usa1_1   and
+               V2_usa1_3 >= C0_usa1_3   and
+               V2_csa1_1 >= C0_csa1_1   and   
+               V2_csa1_3 >= C0_csa1_3   and
+               V2_usa1_1 >= V3_usa1_1   and
+               V2_usa1_3 >= V3_usa1_3   and
+               C0_usa1_1 >= C0_usa1_1   and
+               C0_usa1_3 >= C0_usa1_3   and
+               C0_csa1_1 >= C0_csa1_1   and
+               C0_csa1_1 >= C0_csa1_1   and
+               V0_usa1_1 >= V0_usa1_1   and
+               V0_usa1_3 >= V0_usa1_3   and
+               V0_csa1_1 >= V0_csa1_1   and
+               V0_csa1_3 >= V0_csa1_3   and
+               V0_usa1_1 >= C0_usa1_1   and
+               V0_usa1_3 >= C0_usa1_3   and
+               V0_csa1_1 >= C0_csa1_1   and
+               V0_csa1_3 >= C0_csa1_3   )
+      report "***FAILED TEST: c07s02b02x00p10n01i02013 - Ordering operators >, >= for composite type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p10n01i02013arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2014.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2014.vhd
new file mode 100644
index 0000000..38de4b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2014.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2014.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p11n02i02014ent IS
+END c07s02b02x00p11n02i02014ent;
+
+ARCHITECTURE c07s02b02x00p11n02i02014arch OF c07s02b02x00p11n02i02014ent IS
+  signal S1 : BIT_VECTOR(0 downto 7);
+  signal S2 : BIT_VECTOR(0 to 7) := "10101010"; 
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if (S1 < S2) then
+      k := 5;
+    end if;
+    wait for 1 ns;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p11n02i02014"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c07s02b02x00p11n02i02014 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p11n02i02014arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2015.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2015.vhd
new file mode 100644
index 0000000..0d2f943
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2015.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2015.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p11n02i02015ent IS
+END c07s02b02x00p11n02i02015ent;
+
+ARCHITECTURE c07s02b02x00p11n02i02015arch OF c07s02b02x00p11n02i02015ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_three is array (1 to 6) of integer;
+    variable array_1 : array_three := (6,5,4,3,2,1);
+    variable array_2 : array_three := (6,5,4,4,3,2);
+    variable k       : integer;
+  BEGIN
+    if array_1 < array_2 then  -- No_failure_here
+      k := 5;
+    end if;
+    wait for 5 ns;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p11n02i02015"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c07s02b02x00p11n02i02015 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p11n02i02015arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2016.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2016.vhd
new file mode 100644
index 0000000..95fa31c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2016.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2016.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p16n02i02016ent IS
+END c07s02b02x00p16n02i02016ent;
+
+ARCHITECTURE c07s02b02x00p16n02i02016arch OF c07s02b02x00p16n02i02016ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_three is array (1 to 6) of integer;
+    variable array_1 : array_three := (6,5,4,3,2,1);
+    variable array_2 : array_three := (6,5,4,1,2,3);
+    variable k : integer := 0;
+  BEGIN
+    if array_1 > array_2 then
+      k := 5;
+    end if;
+    wait for 5 ns;
+    assert NOT(k=5)
+      report "***PASSED TEST: c07s02b02x00p16n02i02016"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c07s02b02x00p16n02i02016 - The relations > (greater than) and >= (greater than or equal) are defined to be the complements of the <= and < operators respectively for the same two operands."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p16n02i02016arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2017.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2017.vhd
new file mode 100644
index 0000000..f9a4051
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2017.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2017.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02017ent IS
+END c07s02b04x00p01n01i02017ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02017arch OF c07s02b04x00p01n01i02017ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := k + 5 + 7;
+    assert NOT(k=12)
+      report "***PASSED TEST: c07s02b04x00p01n01i02017"
+      severity NOTE;
+    assert ( k=12 )
+      report "***FAILED TEST: c07s02b04x00p01n01i02017 - The adding operator + has its conventional meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02017arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2021.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2021.vhd
new file mode 100644
index 0000000..3778b21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2021.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2021.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02021ent IS
+END c07s02b04x00p01n01i02021ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02021arch OF c07s02b04x00p01n01i02021ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable w : real := 3.0 + 2.0;   -- No_failure_here
+                                          -- w should be 5.0
+  BEGIN
+    assert NOT(w=5.0) 
+      report "***PASSED TEST: c07s02b04x00p01n01i02021" 
+      severity NOTE;
+    assert (w=5.0) 
+      report "***FAILED TEST: c07s02b04x00p01n01i02021 - The adding operators are predefined only for numeric types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02021arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2022.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2022.vhd
new file mode 100644
index 0000000..fd9e937
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2022.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2022.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02022ent IS
+END c07s02b04x00p01n01i02022ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02022arch OF c07s02b04x00p01n01i02022ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable w : real := 3.0 - 2.0;   -- No_failure_here
+                                          -- w should be 1.0
+  BEGIN
+    assert NOT(w=1.0) 
+      report "***PASSED TEST: c07s02b04x00p01n01i02022"
+      severity NOTE;
+    assert (w=1.0) 
+      report "***FAILED TEST: c07s02b04x00p01n01i02022 - The adding operators are predefined only for numeric types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02022arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc203.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc203.vhd
new file mode 100644
index 0000000..137255d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc203.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc203.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p07n01i00203ent IS
+END c03s01b00x00p07n01i00203ent;
+
+ARCHITECTURE c03s01b00x00p07n01i00203arch OF c03s01b00x00p07n01i00203ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    loop1:
+    for J in 1 downto 30 loop
+      k := k + J;
+    end loop LOOP1;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c03s01b00x00p07n01i00203"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c03s01b00x00p07n01i00203 - It is valid to have a null range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p07n01i00203arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc204.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc204.vhd
new file mode 100644
index 0000000..0c15890
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc204.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc204.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p07n02i00204ent IS
+END c03s01b00x00p07n02i00204ent;
+
+ARCHITECTURE c03s01b00x00p07n02i00204arch OF c03s01b00x00p07n02i00204ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for I in 5 downto 50 loop
+      k := k + 1;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c03s01b00x00p07n02i00204"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c03s01b00x00p07n02i00204 - In the case of L downto R, if L < R then the range is a null range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p07n02i00204arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc205.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc205.vhd
new file mode 100644
index 0000000..792c812
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc205.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc205.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p08n01i00205ent IS
+END c03s01b00x00p08n01i00205ent;
+
+ARCHITECTURE c03s01b00x00p08n01i00205arch OF c03s01b00x00p08n01i00205ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k:bit;
+  BEGIN
+    k := bit'leftof('1');
+    assert NOT( k='0' )
+      report "***PASSED TEST: c03s01b00x00p08n01i00205"      severity NOTE;
+    assert ( k='0' )
+      report "***FAILED TEST: c03s01b00x00p08n01i00205 - Left of the value testing failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p08n01i00205arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc206.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc206.vhd
new file mode 100644
index 0000000..421f834
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc206.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc206.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p08n01i00206ent IS
+  type i is range 3 downto 1;
+END c03s01b00x00p08n01i00206ent;
+
+ARCHITECTURE c03s01b00x00p08n01i00206arch OF c03s01b00x00p08n01i00206ent IS
+  constant r:i:=2;
+BEGIN
+  TESTING: PROCESS
+    variable m:i;
+  BEGIN
+    m := i'leftof(r);
+    assert NOT( m=3 ) 
+      report "***PASSED TEST: c03s01b00x00p08n01i00206"
+      severity NOTE;
+    assert ( m=3 ) 
+      report "***FAILED TEST: c03s01b00x00p08n01i00206 - Left of the value testing failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p08n01i00206arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2061.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2061.vhd
new file mode 100644
index 0000000..1451f8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2061.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2061.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02061ent IS
+END c07s02b04x00p01n02i02061ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02061arch OF c07s02b04x00p01n02i02061ent IS
+  signal S1 : Integer;
+  signal S2 : Integer;
+  signal S3 : BIT_VECTOR(0 to 7);
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2 : Integer := 10;
+    variable V3,V4 : BIT_VECTOR(0 to 3) := "0101" ;
+  BEGIN
+    S1 <= V1 + V2;
+    wait for 1 ns;
+    assert NOT(S1 = 20) 
+      report "***PASSED TEST: c07s02b04x00p01n02i02061" 
+      severity NOTE;
+    assert (S1 = 20) 
+      report "***FAILED TEST: c07s02b04x00p01n02i02061 - Operands must be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02061arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2062.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2062.vhd
new file mode 100644
index 0000000..e2c53fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2062.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2062.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02062ent IS
+END c07s02b04x00p01n02i02062ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02062arch OF c07s02b04x00p01n02i02062ent IS
+  signal S2 : Integer;
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2 : Integer := 10;
+  BEGIN
+    S2 <= V1 - V2;
+    wait for 1 ns;
+    assert NOT(S2 = 0) 
+      report "***PASSED TEST: c07s02b04x00p01n02i02062"
+      severity NOTE;
+    assert (S2 = 0) 
+      report "***FAILED TEST: c07s02b04x00p01n02i02062 - Operands must be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02062arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2063.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2063.vhd
new file mode 100644
index 0000000..5b18f04
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2063.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2063.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02063ent IS
+END c07s02b04x00p01n02i02063ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02063arch OF c07s02b04x00p01n02i02063ent IS
+  signal S1 : Integer;
+  signal S2 : Integer;
+  signal S3 : BIT_VECTOR(0 to 7);
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2 : Integer := 10;
+    variable V3,V4 : BIT_VECTOR(0 to 3) := "0101" ;
+  BEGIN
+    S3 <= V3&V4;
+    wait for 1 ns;
+    assert NOT(S3 = "01010101") 
+      report "***PASSED TEST: c07s02b04x00p01n02i02063" 
+      severity NOTE;
+    assert (S3 = "01010101") 
+      report "***FAILED TEST: c07s02b04x00p01n02i02063 - Operands must be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02063arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2077.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2077.vhd
new file mode 100644
index 0000000..d5abd4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2077.vhd
@@ -0,0 +1,169 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2077.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02077ent IS
+END c07s02b04x00p01n02i02077ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02077arch OF c07s02b04x00p01n02i02077ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A : bit_vector (1 to 32);
+    constant AA : bit_vector (1 to 32) := x"0000ffff";
+    variable B : bit_vector (32 downto 1);
+    variable C : bit_vector (15 downto 0);
+    variable D, DD : bit_vector (0 to 15);
+    variable E : bit_vector (0 to 47);
+    variable F : bit_vector (47 downto 0);
+    alias FF : bit_vector (47 downto 0) is F;
+    variable Q, R : bit;
+  BEGIN
+
+    A := x"ffffffff";
+    B := x"00000000";
+    C := x"ffff";
+    D := x"0000";
+    E := x"ffffffffffff";
+    FF := x"000000000000";
+    Q := '1';
+    R := '0';
+
+    assert NOT(   ( C & Q = b"11111111111111111")   and
+                  ( C & R = b"11111111111111110")   and
+                  ( D & Q = b"00000000000000001")   and
+                  ( D & R = b"00000000000000000")   and
+                  ( Q & C = b"11111111111111111")   and
+                  ( R & C = b"01111111111111111")   and
+                  ( Q & D = b"10000000000000000")   and
+                  ( R & D = b"00000000000000000")   and
+                  ( A & Q = Q & A)   and
+                  ( B & R = R & B)   and
+                  ( A & R = C & (C & R))   and
+                  ( R & A = (R & C) & C)   and
+                  ( R & R & R & R  & C = x"0ffff")   and
+                  ( C & R & R & R & R = x"ffff0")      and
+                  ( E & Q = Q & E)   and
+                  ( F & Q = not (E & R))   and
+                  ( A & A = x"ffffffffffffffff")   and
+                  ( A & B = x"ffffffff00000000")   and
+                  ( A & C = x"ffffffffffff")   and
+                  ( A & D = x"ffffffff0000")   and
+                  ( A & E = x"ffffffffffffffffffff")   and
+                  ( A & F = x"ffffffff000000000000")   and
+                  ( B & A = x"00000000ffffffff")   and
+                  ( B & B = x"0000000000000000")   and
+                  ( B & C = x"00000000ffff")   and
+                  ( B & D = x"000000000000")   and
+                  ( B & E = x"00000000ffffffffffff")   and
+                  ( B & F = x"00000000000000000000")   and
+                  ( C & A = x"ffffffffffff")   and
+                  ( C & B = x"ffff00000000")   and
+                  ( C & C = x"ffffffff")      and
+                  ( C & D = x"ffff0000")      and
+                  ( C & E = x"ffffffffffffffff")   and
+                  ( C & F = x"ffff000000000000")   and
+                  ( D & A = x"0000ffffffff")   and
+                  ( D & B = x"000000000000")   and
+                  ( D & C = x"0000ffff")      and
+                  ( D & D = x"00000000")      and
+                  ( D & E = x"0000ffffffffffff")   and
+                  ( D & F = x"0000000000000000")   and
+                  ( E & A = x"ffffffffffffffffffff")   and
+                  ( E & B = x"ffffffffffff00000000")   and
+                  ( E & C = x"ffffffffffffffff")      and
+                  ( E & D = x"ffffffffffff0000")      and
+                  ( E & E = x"ffffffffffffffffffffffff")   and
+                  ( E & F = x"ffffffffffff000000000000")   and
+                  ( F & A = x"000000000000ffffffff")   and
+                  ( F & B = x"00000000000000000000")   and
+                  ( F & C = x"000000000000ffff")      and
+                  ( F & D = x"0000000000000000")      and
+                  ( F & E = x"000000000000ffffffffffff")   and
+                  ( F & F = x"000000000000000000000000")   )    
+      report "***PASSED TEST: c07s02b04x00p01n02i02077" 
+      severity NOTE;
+    assert (   ( C & Q = b"11111111111111111")   and
+               ( C & R = b"11111111111111110")   and
+               ( D & Q = b"00000000000000001")   and
+               ( D & R = b"00000000000000000")   and
+               ( Q & C = b"11111111111111111")   and
+               ( R & C = b"01111111111111111")   and
+               ( Q & D = b"10000000000000000")   and
+               ( R & D = b"00000000000000000")   and
+               ( A & Q = Q & A)   and
+               ( B & R = R & B)   and
+               ( A & R = C & (C & R))   and
+               ( R & A = (R & C) & C)   and
+               ( R & R & R & R  & C = x"0ffff")   and
+               ( C & R & R & R & R = x"ffff0")      and
+               ( E & Q = Q & E)   and
+               ( F & Q = not (E & R))   and
+               ( A & A = x"ffffffffffffffff")   and
+               ( A & B = x"ffffffff00000000")   and
+               ( A & C = x"ffffffffffff")   and
+               ( A & D = x"ffffffff0000")   and
+               ( A & E = x"ffffffffffffffffffff")   and
+               ( A & F = x"ffffffff000000000000")   and
+               ( B & A = x"00000000ffffffff")   and
+               ( B & B = x"0000000000000000")   and
+               ( B & C = x"00000000ffff")   and
+               ( B & D = x"000000000000")   and
+               ( B & E = x"00000000ffffffffffff")   and
+               ( B & F = x"00000000000000000000")   and
+               ( C & A = x"ffffffffffff")   and
+               ( C & B = x"ffff00000000")   and
+               ( C & C = x"ffffffff")      and
+               ( C & D = x"ffff0000")      and
+               ( C & E = x"ffffffffffffffff")   and
+               ( C & F = x"ffff000000000000")   and
+               ( D & A = x"0000ffffffff")   and
+               ( D & B = x"000000000000")   and
+               ( D & C = x"0000ffff")      and
+               ( D & D = x"00000000")      and
+               ( D & E = x"0000ffffffffffff")   and
+               ( D & F = x"0000000000000000")   and
+               ( E & A = x"ffffffffffffffffffff")   and
+               ( E & B = x"ffffffffffff00000000")   and
+               ( E & C = x"ffffffffffffffff")      and
+               ( E & D = x"ffffffffffff0000")      and
+               ( E & E = x"ffffffffffffffffffffffff")   and
+               ( E & F = x"ffffffffffff000000000000")   and
+               ( F & A = x"000000000000ffffffff")   and
+               ( F & B = x"00000000000000000000")   and
+               ( F & C = x"000000000000ffff")      and
+               ( F & D = x"0000000000000000")      and
+               ( F & E = x"000000000000ffffffffffff")   and
+               ( F & F = x"000000000000000000000000")   )    
+      report "***FAILED TEST: c07s02b04x00p01n02i02077 - The operation of operator & test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02077arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2078.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2078.vhd
new file mode 100644
index 0000000..466ec4f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2078.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2078.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02078ent IS
+END c07s02b04x00p20n01i02078ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02078arch OF c07s02b04x00p20n01i02078ent IS
+
+  procedure CheckConcat(
+    result       : STRING;
+    reference    : STRING;
+    left, right    : INTEGER
+    ) is
+    variable match : BOOLEAN;
+  begin
+    if result'LENGTH /= reference'LENGTH then
+      assert FALSE report "FAIL: length does not match";
+    elsif result'LEFT /= left then
+      assert FALSE report "FAIL: 'LEFT is wrong";
+    elsif result'RIGHT /= right then
+      assert FALSE report "FAIL: 'RIGHT is wrong";
+    elsif result /= reference then
+      assert FALSE report "FAIL: value is wrong";
+    else
+      assert result = reference report "FAIL: value is wrong";
+    end if;
+    assert NOT(   result'LENGTH = reference'LENGTH   and
+                  result'LEFT = left         and
+                  result'RIGHT = right         and
+                  result = reference         )
+      report "***PASSED TEST: c07s02b04x00p20n01i02078"
+      severity NOTE;
+    assert (   result'LENGTH = reference'LENGTH   and
+               result'LEFT = left         and
+               result'RIGHT = right         and
+               result = reference         )
+      report "***FAILED TEST: c07s02b04x00p20n01i02078 - Concatenation of string in function call test failed."
+      severity ERROR;
+  end;
+
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    CheckConcat("1" & "2", "12", 1, 2);
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02078arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2079.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2079.vhd
new file mode 100644
index 0000000..54f4648
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2079.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2079.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02079ent IS
+END c07s02b04x00p20n01i02079ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02079arch OF c07s02b04x00p20n01i02079ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_type is array (positive range <>) of integer;
+    -- No_failure_here
+    constant a : array_type (1 to 3) := (1, 2, 3);
+    constant b : array_type (1 to 5) := (1, 2, 3, 4, 5);
+    constant x : array_type := a & b;
+  BEGIN
+    assert NOT(x=(1,2,3,1,2,3,4,5))
+      report "***PASSED TEST: c07s02b04x00p20n01i02079"
+      severity NOTE;
+    assert (x=(1,2,3,1,2,3,4,5))
+      report "***FAILED TEST: c07s02b04x00p20n01i02079 - The result of the concatenation of two one-dimensional arrays is a one-dimensional array whose length is the sum of the lengths of its operands, and whose elements consist of the elements of the left operand (in left to right order) followed by the elements of the right operand (in left to right order)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02079arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc208.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc208.vhd
new file mode 100644
index 0000000..360dc89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc208.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc208.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p09n01i00208ent IS
+END c03s01b00x00p09n01i00208ent;
+
+ARCHITECTURE c03s01b00x00p09n01i00208arch OF c03s01b00x00p09n01i00208ent IS
+  type week is (Mon, Tue, Wed, Thur, Fri, Sat, Sun);
+  subtype weekend is integer range 5 to 6;
+BEGIN
+  TESTING: PROCESS
+    variable k : weekend := 6;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b00x00p09n01i00208" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b00x00p09n01i00208 - Constraints for the subtype declaration must match the base type of integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p09n01i00208arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2080.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2080.vhd
new file mode 100644
index 0000000..122941e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2080.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2080.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02080ent IS
+END c07s02b04x00p20n01i02080ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02080arch OF c07s02b04x00p20n01i02080ent IS
+  TYPE real_vector is array (INTEGER range <>) of REAL;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE target  : real_vector (1 to 10) ;
+    VARIABLE slice_1 : real_vector (1 to 4)  := (1.0,2.0,3.0,4.0);
+    VARIABLE slice_2 : real_vector (-2 to 4) :=
+      (5.0,6.0,7.0,8.0,9.0,10.0,11.0);
+  BEGIN
+
+    target (2 to 8):= slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
+
+    assert NOT(target(2 to 8) = (1.0,2.0,3.0,6.0,7.0,8.0,9.0))
+      report "***PASSED TEST: c07s02b04x00p20n01i02080"
+      severity NOTE;
+    assert (target(2 to 8) = (1.0,2.0,3.0,6.0,7.0,8.0,9.0))
+      report "***FAILED TEST: c07s02b04x00p20n01i02080 - One dimensional array of REAL type concatenation failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02080arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2081.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2081.vhd
new file mode 100644
index 0000000..d76d8c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2081.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2081.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02081ent IS
+END c07s02b04x00p20n01i02081ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02081arch OF c07s02b04x00p20n01i02081ent IS
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE target  : string (1 to 10) ;
+    VARIABLE slice_1 : string (1 to 10) := "0123456789";
+    VARIABLE slice_2 : string (1 to 10) := "abcdefghji";
+  BEGIN
+
+    target (2 to 8 ):= slice_1 ( 1 to 3 ) & slice_2 ( 4 to 7 );
+
+    assert NOT(target(2 to 8) = "012defg") 
+      report "***PASSED TEST: c07s02b04x00p20n01i02081"
+      severity NOTE;
+    assert (target(2 to 8) = "012defg") 
+      report "***FAILED TEST: c07s02b04x00p20n01i02081 - One dimensional array of STRING type concatenation failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02081arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2082.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2082.vhd
new file mode 100644
index 0000000..a2d4d90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2082.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2082.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02082ent IS
+END c07s02b04x00p20n01i02082ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02082arch OF c07s02b04x00p20n01i02082ent IS
+  TYPE real_vector is array (INTEGER range <>) of REAL;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE target  : real_vector (1 to 7) ;
+    VARIABLE slice_1 : real_vector (1 to 4) := (1.0,2.0,3.0,4.0);
+    VARIABLE slice_2 : real_vector (-2 to 4) :=
+      (5.0,6.0,7.0,8.0,9.0,10.0,11.0);
+  BEGIN
+
+    target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
+
+    assert NOT(target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
+      report "***PASSED TEST: c07s02b04x00p20n01i02082"
+      severity NOTE;
+    assert (target=(1.0,2.0,3.0,6.0,7.0,8.0,9.0))
+      report "***FAILED TEST: c07s02b04x00p20n01i02082 - One dimensional array of REAL type concatenation into a larger ARRAY failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02082arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2083.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2083.vhd
new file mode 100644
index 0000000..a9ee963
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2083.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2083.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02083ent IS
+END c07s02b04x00p20n01i02083ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02083arch OF c07s02b04x00p20n01i02083ent IS
+  TYPE int_vector is array (INTEGER range <>) of INTEGER;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE target  : int_vector (1 to 7) ;
+    VARIABLE slice_1 : int_vector (1 to 4) := (1,2,3,4);
+    VARIABLE slice_2 : int_vector (-2 to 4) := (5,6,7,8,9,10,11);
+  BEGIN
+
+    target := slice_1 ( 1 to 3 ) & slice_2 ( -1 to 2 );
+
+    assert NOT(target=(1,2,3,6,7,8,9))
+      report "***PASSED TEST: c07s02b04x00p20n01i02083"
+      severity NOTE;
+    assert (target=(1,2,3,6,7,8,9))
+      report "***FAILED TEST: c07s02b04x00p20n01i02083 - One dimensional array of INTEGER type concatenation into a larger ARRAY failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02083arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2084.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2084.vhd
new file mode 100644
index 0000000..6e40233
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2084.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2084.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02084ent IS
+END c07s02b04x00p20n01i02084ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02084arch OF c07s02b04x00p20n01i02084ent IS
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE target  : string (1 to 7) ;
+    VARIABLE slice_1 : string (1 to 10) := "0123456789";
+    VARIABLE slice_2 : string (1 to 10) := "abcdefghji";
+  BEGIN
+
+    target := slice_1 ( 1 to 3 ) & slice_2 ( 4 to 7 );
+
+    assert NOT(target="012defg")
+      report "***PASSED TEST: c07s02b04x00p20n01i02084"
+      severity NOTE;
+    assert (target="012defg")
+      report "***FAILED TEST: c07s02b04x00p20n01i02084 - One dimensional array of STRING type concatenation into a larger ARRAY failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02084arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2085.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2085.vhd
new file mode 100644
index 0000000..e689b8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2085.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2085.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02085ent IS
+END c07s02b04x00p20n01i02085ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02085arch OF c07s02b04x00p20n01i02085ent IS
+
+  TYPE    boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE     boolean_4_up     is boolean_v (1 to 4);
+  SUBTYPE     boolean_4_dwn     is boolean_v (4 downto 1);
+  SUBTYPE     boolean_8_dwn     is boolean_v (4 downto -3);
+
+BEGIN
+  TESTING: PROCESS
+    variable r_operand : boolean_4_up := (true, true, false, false);
+    variable l_operand : boolean_4_dwn:= (false, false, true, true);
+    variable result    : boolean_8_dwn;
+  BEGIN
+
+    result := l_operand & r_operand;
+    assert ( result (4)  = false )
+      report  "result (4) /= false" severity FAILURE;
+    assert ( result (1)  = true )
+      report  "result (1) /= true" severity FAILURE;
+    assert ( result (0)  = true )
+      report  "result (0) /= true" severity FAILURE;
+    assert ( result (-3)  = false )
+      report  "result (-3) /= false" severity FAILURE;
+
+    assert NOT((result(4)=false) and (result=(false,false,true,true,true,true,false,false)))
+      report "***PASSED TEST: c07s02b04x00p20n01i02085"
+      severity NOTE;
+    assert ((result(4)=false) and (result=(false,false,true,true,true,true,false,false)))
+      report "***FAILED TEST: c07s02b04x00p20n01i02085 - Concatenated array is descending and that the left bound is that of the first operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02085arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2086.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2086.vhd
new file mode 100644
index 0000000..4d789e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2086.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2086.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02086ent IS
+END c07s02b04x00p20n01i02086ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02086arch OF c07s02b04x00p20n01i02086ent IS
+
+  TYPE    boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE     boolean_4_up     is boolean_v (1 to 4);
+  SUBTYPE     boolean_4_null  is boolean_v (4 to 3);
+  SUBTYPE     boolean_8_up     is boolean_v (1 to 8);
+
+BEGIN
+  TESTING: PROCESS
+    variable l_operand : boolean_4_null ;
+    variable r_operand : boolean_4_up   := (false, false, true, true);
+    variable result    : boolean_4_up;
+  BEGIN
+
+    result := l_operand & r_operand;
+    assert ( result (1)  = false )
+      report  "result (1) /= false" severity FAILURE;
+    assert ( result (4)  = true )
+      report  "result (4) /= true" severity FAILURE;
+
+    assert NOT((result(1)=false) and (result=(false,false,true,true)))
+      report "***PASSED TEST: c07s02b04x00p20n01i02086"
+      severity NOTE;
+    assert ((result(1)=false) and (result=(false,false,true,true)))
+      report "***FAILED TEST: c07s02b04x00p20n01i02086 - The left bound of the concatenated array is that of the second operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02086arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2087.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2087.vhd
new file mode 100644
index 0000000..14d62b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2087.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2087.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02087ent IS
+END c07s02b04x00p20n01i02087ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02087arch OF c07s02b04x00p20n01i02087ent IS
+
+  TYPE        boolean_v is array    (integer range <>) of boolean;
+  SUBTYPE     boolean_4 is boolean_v    (1 to 4);
+  SUBTYPE     boolean_8 is boolean_v    (1 to 8);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_8;
+    variable l_operand : boolean_4 := (true,false,true,false);
+    variable r_operand : boolean_4 := (false,false,true,true);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true,false,true,false,false,false,true,true)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02087"
+      severity NOTE;
+    assert ((result = (true,false,true,false,false,false,true,true)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02087 - Concatenation of two BOOLEAN arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02087arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2088.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2088.vhd
new file mode 100644
index 0000000..e3893c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2088.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2088.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02088ent IS
+END c07s02b04x00p20n01i02088ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02088arch OF c07s02b04x00p20n01i02088ent IS
+
+  TYPE     boolean_v    is array    (integer range <>) of boolean;
+  SUBTYPE     boolean_4    is boolean_v    (1 to 4);
+  SUBTYPE     boolean_null    is boolean_v    (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_4;
+    variable l_operand : boolean_4 := (true,false,true,false);
+    variable r_operand : boolean_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true,false,true,false)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02088"
+      severity NOTE;
+    assert ((result = (true,false,true,false)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02088 - Concatenation of null and BOOLEAN arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02088arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2089.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2089.vhd
new file mode 100644
index 0000000..19b89ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2089.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2089.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02089ent IS
+END c07s02b04x00p20n01i02089ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02089arch OF c07s02b04x00p20n01i02089ent IS
+
+  TYPE     bit_v       is array (integer range <>) of bit;
+  SUBTYPE     bit_4       is bit_v (1 to 4);
+  SUBTYPE     bit_null    is bit_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : bit_4;
+    variable l_operand : bit_4    := ('1','0','1','0');
+    variable r_operand : bit_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = ('1','0','1','0')) and (result(1) = '1'))
+      report "***PASSED TEST: c07s02b04x00p20n01i02089"
+      severity NOTE;
+    assert ((result = ('1','0','1','0')) and (result(1) = '1'))
+      report "***FAILED TEST: c07s02b04x00p20n01i02089 - Concatenation of null and BIT array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02089arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc209.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc209.vhd
new file mode 100644
index 0000000..26b0354
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc209.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc209.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p09n01i00209ent IS
+END c03s01b00x00p09n01i00209ent;
+
+ARCHITECTURE c03s01b00x00p09n01i00209arch OF c03s01b00x00p09n01i00209ent IS
+  type CLSI is (Jasmine, Jim, Milan, Paul, Saurin);
+  constant x: CLSI := Jasmine;
+  constant y: CLSI := Saurin;
+  subtype People is CLSI range y downto x; 
+BEGIN
+  TESTING: PROCESS
+    variable k : People;
+  BEGIN
+    k := Jim;
+    assert NOT(k=Jim) 
+      report "***PASSED TEST: c03s01b00x00p09n01i00209" 
+      severity NOTE;
+    assert (k=Jim) 
+      report "***FAILED TEST: c03s01b00x00p09n01i00209 - Constraints for the subtype declaration must match the base type of integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p09n01i00209arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2090.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2090.vhd
new file mode 100644
index 0000000..ac46403
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2090.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2090.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02090ent IS
+END c07s02b04x00p20n01i02090ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02090arch OF c07s02b04x00p20n01i02090ent IS
+
+  TYPE     boolean_v is array (integer range <>) of boolean;
+  SUBTYPE     boolean_8 is boolean_v (1 to 8);
+  SUBTYPE     boolean_4 is boolean_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_4;
+    variable l_operand : boolean_4 := (true,false,true,false);
+    variable r_operand : boolean_4 := (false,false,true,true);
+    alias    l_alias   : boolean_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : boolean_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 5 ns;
+    assert NOT((result = (false,true,true,true)) and (result(1) = false))
+      report "***PASSED TEST: c07s02b04x00p20n01i02090"
+      severity NOTE;
+    assert ((result = (false,true,true,true)) and (result(1) = false))
+      report "***FAILED TEST: c07s02b04x00p20n01i02090 - Concatenation of two BOOLEAN aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02090arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2091.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2091.vhd
new file mode 100644
index 0000000..f6b002a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2091.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2091.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02091ent IS
+END c07s02b04x00p20n01i02091ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02091arch OF c07s02b04x00p20n01i02091ent IS
+
+  TYPE     bit_v is array (integer range <>) of bit;
+  SUBTYPE     bit_8 is bit_v (1 to 8);
+  SUBTYPE     bit_4 is bit_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : bit_4;
+    variable l_operand : bit_4 := ('1','0','1','0');
+    variable r_operand : bit_4 := ('0','0','1','1');
+    alias    l_alias   : bit_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : bit_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 5 ns;
+    assert NOT((result = ('0','1','1','1')) and (result(1) = '0'))
+      report "***PASSED TEST: c07s02b04x00p20n01i02091"
+      severity NOTE;
+    assert ((result = ('0','1','1','1')) and (result(1) = '0'))
+      report "***FAILED TEST: c07s02b04x00p20n01i02091 - Concatenation of two BOOLEAITses failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02091arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2092.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2092.vhd
new file mode 100644
index 0000000..189e802
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2092.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2092.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02092ent IS
+END c07s02b04x00p20n01i02092ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02092arch OF c07s02b04x00p20n01i02092ent IS
+
+  TYPE    boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE     boolean_4_up     is boolean_v (1 to 4);
+  SUBTYPE     boolean_8_up     is boolean_v (1 to 8);
+  SUBTYPE     boolean_4_dwn     is boolean_v (4 downto 1);
+
+BEGIN
+  TESTING: PROCESS
+    variable l_operand : boolean_4_up := (true, true, false, false);
+    variable r_operand : boolean_4_dwn:= (false, false, true, true); 
+    variable result    : boolean_8_up;
+  BEGIN
+
+    result := l_operand & r_operand;
+    assert ( result (1)  = true )
+      report  "result (1) /= true" severity FAILURE;
+    assert ( result (4)  = false )
+      report  "result (4) /= false" severity FAILURE;
+    assert ( result (5)  = false )
+      report  "result (5) /= false" severity FAILURE;
+    assert ( result (8)  = true )
+      report  "result (8) /= true" severity FAILURE;
+
+    assert NOT((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
+      report "***PASSED TEST: c07s02b04x00p20n01i02092"
+      severity NOTE;
+    assert ((result(1)=true) and (result=(true,true,false,false,false,false,true,true)))
+      report "***FAILED TEST: c07s02b04x00p20n01i02092 - Concatenated array should be ascending and the left bound is that of the first operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02092arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2093.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2093.vhd
new file mode 100644
index 0000000..0f7d461
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2093.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2093.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02093ent IS
+END c07s02b04x00p20n01i02093ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02093arch OF c07s02b04x00p20n01i02093ent IS
+
+  TYPE    boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE     boolean_4_dwn     is boolean_v (4 downto 1);
+  SUBTYPE     boolean_4_null  is boolean_v (4 downto 5);
+  SUBTYPE     boolean_8_dwn     is boolean_v (8 downto 1);
+
+BEGIN
+  TESTING: PROCESS
+    variable l_operand : boolean_4_null ;
+    variable r_operand : boolean_4_dwn  := (false, false, true, true);
+    variable result    : boolean_4_dwn;
+  BEGIN
+
+    result := l_operand & r_operand;
+    assert ( result (4)  = false )
+      report  "result (4) /= false" severity FAILURE;
+    assert ( result (1)  = true )
+      report  "result (1) /= true" severity FAILURE;
+
+    assert NOT((result(4)=false) and (result=(false,false,true,true)))
+      report "***PASSED TEST: c07s02b04x00p20n01i02093"
+      severity NOTE;
+    assert ((result(4)=false) and (result=(false,false,true,true)))
+      report "***FAILED TEST: c07s02b04x00p20n01i02093 - The left bound of the concatenated array is that of the second operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02093arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2094.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2094.vhd
new file mode 100644
index 0000000..981c61c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2094.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2094.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02094ent IS
+END c07s02b04x00p20n01i02094ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02094arch OF c07s02b04x00p20n01i02094ent IS
+
+  TYPE  boolean_v is array (integer range <>) of boolean;
+  SUBTYPE boolean_4  is boolean_v (1 to 4);
+  SUBTYPE boolean_8  is boolean_v (1 to 8);
+
+  FUNCTION return_array RETURN boolean_4 is
+    constant l_operand : boolean_4 := (true,false,true,false);
+  begin
+    RETURN l_operand;
+  end return_array;
+
+BEGIN
+  l : block
+    generic ( info : boolean_8 );
+    generic map ( return_array & return_array );
+  begin
+    assert NOT(info = (true,false,true,false,true,false,true,false))
+      report "***PASSED TEST: c07s02b04x00p20n01i02094"
+      severity NOTE;
+    assert (info = (true,false,true,false,true,false,true,false))
+      report "***FAILED TEST: c07s02b04x00p20n01i02094 - Function array concatenation did not succeed."
+      severity ERROR;
+  end block;
+
+END c07s02b04x00p20n01i02094arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2095.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2095.vhd
new file mode 100644
index 0000000..eeae6c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2095.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2095.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02095ent IS
+END c07s02b04x00p20n01i02095ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02095arch OF c07s02b04x00p20n01i02095ent IS
+
+BEGIN
+  l : block
+    generic ( info : string );
+    generic map ( "VHDL" & " Technology" & " Group" );
+  begin
+    assert NOT(info = "VHDL Technology Group")
+      report "***PASSED TEST: c07s02b04x00p20n01i02095"
+      severity NOTE;
+    assert (info = "VHDL Technology Group")
+      report "***FAILED TEST: c07s02b04x00p20n01i02095 - Literal concatenation did not succeed."
+      severity ERROR;
+  end block;
+
+END c07s02b04x00p20n01i02095arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2096.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2096.vhd
new file mode 100644
index 0000000..93aa9f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2096.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2096.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02096ent IS
+END c07s02b04x00p20n01i02096ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02096arch OF c07s02b04x00p20n01i02096ent IS
+  TYPE     boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE    boolean_4     is boolean_v (1 to 4);
+  SUBTYPE    boolean_8     is boolean_v (1 to 8);
+
+  constant l_operand : boolean_4 := (true,false,true,false);
+  constant r_operand : boolean_4 := (false,false,true,true);
+BEGIN
+  l : block
+    generic ( info : boolean_8 );
+    generic map ( l_operand & r_operand );
+  begin
+    assert NOT(info = (true,false,true,false,false,false,true,true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02096"
+      severity NOTE;
+    assert (info = (true,false,true,false,false,false,true,true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02096 - Constant concatenation did not succeed."
+      severity ERROR;
+  end block;
+
+END c07s02b04x00p20n01i02096arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2097.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2097.vhd
new file mode 100644
index 0000000..5b75f0e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2097.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2097.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02097ent IS
+END c07s02b04x00p20n01i02097ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02097arch OF c07s02b04x00p20n01i02097ent IS
+  TYPE     boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE    boolean_4     is boolean_v (1 to 4);
+  SUBTYPE    boolean_8     is boolean_v (1 to 8);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : boolean_8;
+    variable l_operand : boolean_4 := (true,false,true,false);
+    variable r_operand : boolean_4 := (false,false,true,true);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result = (true,false,true,false,false,false,true,true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02097"
+      severity NOTE;
+    assert (result = (true,false,true,false,false,false,true,true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02097 - Variable concatenation did not succeed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02097arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2098.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2098.vhd
new file mode 100644
index 0000000..b7eb7b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2098.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2098.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02098ent IS
+END c07s02b04x00p20n01i02098ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02098arch OF c07s02b04x00p20n01i02098ent IS
+
+  TYPE   boolean_v   is array (integer range <>) of boolean;
+  SUBTYPE    boolean_4     is boolean_v (1 to 4);
+  SUBTYPE    boolean_8     is boolean_v (1 to 8);
+
+  signal result    : boolean_8;
+  signal l_operand : boolean_4 := (true,false,true,false);
+  signal r_operand : boolean_4 := (false,false,true,true);
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    result <= l_operand & r_operand after 10 ns;
+    wait for 20 ns;
+    assert NOT(result = (true,false,true,false,false,false,true,true)) 
+      report "***PASSED TEST: c07s02b04x00p20n01i02098"
+      severity NOTE;
+    assert (result = (true,false,true,false,false,false,true,true)) 
+      report "***FAILED TEST: c07s02b04x00p20n01i02098- Signals concatenation did not succeed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02098arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2099.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2099.vhd
new file mode 100644
index 0000000..31a25c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2099.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2099.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02099ent IS
+END c07s02b04x00p20n01i02099ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02099arch OF c07s02b04x00p20n01i02099ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE     record_8 is record_v (1 to 8);
+  SUBTYPE     record_4 is record_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : record_4;
+    variable l_operand : record_4 := ( (12,34) , (56,78) , (12,34) , (56,78) );
+    variable r_operand : record_4 := ( (56,78) , (56,78) , (12,34) , (12,34) );
+    alias    l_alias   : record_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : record_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT(result = ( (56,78) , (12,34) , (12,34) , (12,34) ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02099"
+      severity NOTE;
+    assert (result = ( (56,78) , (12,34) , (12,34) , (12,34) ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02099 - Concatenation of two RECORD aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02099arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2100.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2100.vhd
new file mode 100644
index 0000000..adcbda4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2100.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2100.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02100ent IS
+END c07s02b04x00p20n01i02100ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02100arch OF c07s02b04x00p20n01i02100ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE     record_null    is record_v (1 to 0);
+  SUBTYPE     record_4    is record_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : record_4;
+    variable l_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
+    variable r_operand : record_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02100"
+      severity NOTE;
+    assert (result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02100 - Concatenation of null and RECORD arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02100arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2101.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2101.vhd
new file mode 100644
index 0000000..4aadc84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2101.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2101.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02101ent IS
+END c07s02b04x00p20n01i02101ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02101arch OF c07s02b04x00p20n01i02101ent IS
+
+  TYPE  simple_record is record
+                           data_1 : integer;
+                           data_2 : integer;
+                         end record;
+  TYPE     record_v    is array (integer range <>) of simple_record;
+  SUBTYPE     record_null    is record_v (1 to 0);
+  SUBTYPE     record_4    is record_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : record_4;
+    variable l_operand : record_null;
+    variable r_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02101"
+      severity NOTE;
+    assert (result = ( (12,34) , (56,78) , (12,34) , (56,78) ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02101 - Concatenation of null and RECORD arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02101arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2102.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2102.vhd
new file mode 100644
index 0000000..7223c95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2102.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2102.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02102ent IS
+END c07s02b04x00p20n01i02102ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02102arch OF c07s02b04x00p20n01i02102ent IS
+
+  TYPE  simple_record is record
+                           data_1 : integer;
+                           data_2 : integer;
+                         end record;
+  TYPE     record_v    is array (integer range <>) of simple_record;
+  SUBTYPE     record_8    is record_v (1 to 8);
+  SUBTYPE     record_4    is record_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : record_8;
+    variable l_operand : record_4 := ( (12,34) , (56,78) , (12,34) , (56,78) );
+    variable r_operand : record_4 := ( (56,78) , (56,78) , (12,34) , (12,34) );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ((12,34),(56,78),(12,34),(56,78),(56,78),(56,78),(12,34),(12,34)))
+      report "***PASSED TEST: c07s02b04x00p20n01i02102"
+      severity NOTE;
+    assert (result = ((12,34),(56,78),(12,34),(56,78),(56,78),(56,78),(12,34),(12,34)))
+      report "***FAILED TEST: c07s02b04x00p20n01i02102 - Concatenation of two RECORD arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02102arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2103.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2103.vhd
new file mode 100644
index 0000000..0195e22
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2103.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2103.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02103ent IS
+END c07s02b04x00p20n01i02103ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02103arch OF c07s02b04x00p20n01i02103ent IS
+
+  TYPE     positive_v is array (integer range <>) of positive;
+  SUBTYPE     positive_8 is positive_v (1 to 8);
+  SUBTYPE     positive_4 is positive_v (1 to 4);
+BEGIN
+  TESTING : PROCESS
+    variable result    : positive_4;
+    variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
+    variable r_operand : positive_4 := ( 89 , 89 , 1 , 1 );
+    alias    l_alias   : positive_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : positive_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT(result = ( 89 , 1 , 1 , 1 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02103"
+      severity NOTE;
+    assert (result = ( 89 , 1 , 1 , 1 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02103 - Concatenation of two RECORD arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02103arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2104.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2104.vhd
new file mode 100644
index 0000000..751ba25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2104.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2104.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02104ent IS
+END c07s02b04x00p20n01i02104ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02104arch OF c07s02b04x00p20n01i02104ent IS
+
+  TYPE     positive_v    is array (integer range <>) of positive;
+  SUBTYPE     positive_8    is positive_v (1 to 8);
+  SUBTYPE     positive_4    is positive_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : positive_8;
+    variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
+    variable r_operand : positive_4 := ( 89 , 89 , 1 , 1 );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( 1 , 89 , 1 , 89 , 89 , 89 , 1 , 1 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02104"
+      severity NOTE;
+    assert (result = ( 1 , 89 , 1 , 89 , 89 , 89 , 1 , 1 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02104 - Concatenation of two POSITIVE arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02104arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2105.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2105.vhd
new file mode 100644
index 0000000..d8dae27
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2105.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2105.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02105ent IS
+END c07s02b04x00p20n01i02105ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02105arch OF c07s02b04x00p20n01i02105ent IS
+
+  TYPE     positive_v    is array (integer range <>) of positive;
+  SUBTYPE     positive_4    is positive_v (1 to 4);
+  SUBTYPE     positive_null    is positive_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : positive_4;
+    variable l_operand : positive_null;
+    variable r_operand : positive_4 := ( 1 , 89 , 1 , 89 );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( 1 , 89 , 1 , 89 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02105"
+      severity NOTE;
+    assert (result = ( 1 , 89 , 1 , 89 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02105 - Concatenation of null and POSITIVE arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02105arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2106.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2106.vhd
new file mode 100644
index 0000000..5d17705
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2106.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2106.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02106ent IS
+END c07s02b04x00p20n01i02106ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02106arch OF c07s02b04x00p20n01i02106ent IS
+
+  TYPE     natural_v is array (integer range <>) of natural;
+  SUBTYPE     natural_8 is natural_v (1 to 8);
+  SUBTYPE     natural_4 is natural_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : natural_4;
+    variable l_operand : natural_4 := ( 0 , 23 , 0 , 23 );
+    variable r_operand : natural_4 := ( 23 , 23 , 0 , 0 );
+    alias    l_alias   : natural_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : natural_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT(result = ( 23, 0, 0, 0 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02106"
+      severity NOTE;
+    assert (result = ( 23, 0, 0, 0 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02106 - Concatenation of two NATURAL alias failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02106arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2107.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2107.vhd
new file mode 100644
index 0000000..5562356
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2107.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2107.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02107ent IS
+END c07s02b04x00p20n01i02107ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02107arch OF c07s02b04x00p20n01i02107ent IS
+
+  TYPE     natural_v    is array (integer range <>) of natural;
+  SUBTYPE     natural_4    is natural_v (1 to 4);
+  SUBTYPE     natural_null    is natural_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : natural_4;
+    variable l_operand : natural_4 := ( 0 , 23 , 0 , 23 );
+    variable r_operand : natural_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( 0 , 23 , 0 , 23 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02107"
+      severity NOTE;
+    assert (result = ( 0 , 23 , 0 , 23 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02107 - Concatenation of null and NATURAL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02107arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2108.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2108.vhd
new file mode 100644
index 0000000..c3d1718
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2108.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2108.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02108ent IS
+END c07s02b04x00p20n01i02108ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02108arch OF c07s02b04x00p20n01i02108ent IS
+
+  TYPE     natural_v    is array (integer range <>) of natural;
+  SUBTYPE     natural_4    is natural_v (1 to 4);
+  SUBTYPE     natural_null    is natural_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : natural_4;
+    variable l_operand : natural_null;
+    variable r_operand : natural_4 := ( 0 , 23 , 0 , 23 );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( 0 , 23 , 0 , 23 ))
+      report "***PASSED TEST: c07s02b04x00p20n01i02108"
+      severity NOTE;
+    assert (result = ( 0 , 23 , 0 , 23 ))
+      report "***FAILED TEST: c07s02b04x00p20n01i02108 - Concatenation of null and NATURAL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02108arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2109.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2109.vhd
new file mode 100644
index 0000000..0bd6f82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2109.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2109.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02109ent IS
+END c07s02b04x00p20n01i02109ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02109arch OF c07s02b04x00p20n01i02109ent IS
+
+  TYPE     natural_v is array (integer range <>) of natural;
+  SUBTYPE     natural_8 is natural_v (1 to 8);
+  SUBTYPE     natural_4 is natural_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : natural_8;
+    variable l_operand : natural_4 := ( 0 , 23 , 0 , 23 );
+    variable r_operand : natural_4 := ( 23 , 23 , 0 , 0 );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT(result = ( 0 , 23 , 0 , 23 , 23 , 23 , 0 , 0 )) 
+      report "***PASSED TEST: c07s02b04x00p20n01i02109"
+      severity NOTE;
+    assert (result = ( 0 , 23 , 0 , 23 , 23 , 23 , 0 , 0 )) 
+      report "***FAILED TEST: c07s02b04x00p20n01i02109 - Concatenation of two NATURAL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02109arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc211.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc211.vhd
new file mode 100644
index 0000000..382896c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc211.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc211.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p09n01i00211ent IS
+END c03s01b00x00p09n01i00211ent;
+
+ARCHITECTURE c03s01b00x00p09n01i00211arch OF c03s01b00x00p09n01i00211ent IS
+  type ascending_range is range 0 to 10 ;
+  type descending_range is range 10 downto 0 ;
+  subtype ascending_subrange is descending_range range 2 to 5 ;
+  subtype descending_subrange is ascending_range range 5 downto 2 ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((ascending_range'left = 0) and(descending_range'left = 10) and(ascending_subrange'right = 5) and (descending_subrange'right = 2)) 
+      report "***PASSED TEST: c03s01b00x00p09n01i00211" 
+      severity NOTE;
+    assert ((ascending_range'left = 0) and(descending_range'left = 10) and(ascending_subrange'right = 5) and (descending_subrange'right = 2)) 
+      report "***FAILED TEST: c03s01b00x00p09n01i00211 - The type of expression is not the same as the base type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p09n01i00211arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2110.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2110.vhd
new file mode 100644
index 0000000..595e334
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2110.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2110.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02110ent IS
+END c07s02b04x00p20n01i02110ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02110arch OF c07s02b04x00p20n01i02110ent IS
+
+  TYPE     time_v is array (integer range <>) of time;
+  SUBTYPE     time_8 is time_v (1 to 8);
+  SUBTYPE     time_4 is time_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : time_4;
+    variable l_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
+    variable r_operand : time_4 := ( 23 ns , 23 ns , 78 ns , 78 ns );
+    alias    l_alias   : time_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : time_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT((result = ( 23 ns, 78 ns, 78 ns, 78 ns )) and (result(1) = 23 ns))
+      report "***PASSED TEST: c07s02b04x00p20n01i02110"
+      severity NOTE;
+    assert ((result = ( 23 ns, 78 ns, 78 ns, 78 ns )) and (result(1) = 23 ns))
+      report "***FAILED TEST: c07s02b04x00p20n01i02110 - Concatenation of two TIME aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02110arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2111.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2111.vhd
new file mode 100644
index 0000000..1413e7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2111.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2111.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02111ent IS
+END c07s02b04x00p20n01i02111ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02111arch OF c07s02b04x00p20n01i02111ent IS
+
+  TYPE     time_v       is array (integer range <>) of time;
+  SUBTYPE     time_null    is time_v (1 to 0);
+  SUBTYPE     time_4       is time_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : time_4;
+    variable l_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
+    variable r_operand : time_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
+      report "***PASSED TEST: c07s02b04x00p20n01i02111"
+      severity NOTE;
+    assert ((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
+      report "***FAILED TEST: c07s02b04x00p20n01i02111 - Concatenation of null and TIME array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02111arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2112.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2112.vhd
new file mode 100644
index 0000000..431983e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2112.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2112.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02112ent IS
+END c07s02b04x00p20n01i02112ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02112arch OF c07s02b04x00p20n01i02112ent IS
+
+  TYPE     time_v       is array (integer range <>) of time;
+  SUBTYPE     time_null    is time_v (1 to 0);
+  SUBTYPE     time_4       is time_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : time_4;
+    variable l_operand : time_null;
+    variable r_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
+      report "***PASSED TEST: c07s02b04x00p20n01i02112"
+      severity NOTE;
+    assert ((result = ( 78 ns, 23 ns, 78 ns, 23 ns )) and (result(1) = 78 ns))
+      report "***FAILED TEST: c07s02b04x00p20n01i02112 - Concatenation of null and TIME array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02112arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2113.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2113.vhd
new file mode 100644
index 0000000..ca5c3dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2113.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2113.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02113ent IS
+END c07s02b04x00p20n01i02113ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02113arch OF c07s02b04x00p20n01i02113ent IS
+
+  TYPE     time_v       is array (integer range <>) of time;
+  SUBTYPE     time_4       is time_v (1 to 4);
+  SUBTYPE     time_8       is time_v (1 to 8);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : time_8;
+    variable l_operand : time_4 := ( 78 ns , 23 ns , 78 ns , 23 ns );
+    variable r_operand : time_4 := ( 23 ns , 23 ns , 78 ns , 78 ns );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = ( 78 ns, 23 ns, 78 ns, 23 ns, 23 ns, 23 ns, 78 ns, 78 ns )) and (result(1) = 78 ns))
+      report "***PASSED TEST: c07s02b04x00p20n01i02113"
+      severity NOTE;
+    assert ((result = ( 78 ns, 23 ns, 78 ns, 23 ns, 23 ns, 23 ns, 78 ns, 78 ns )) and (result(1) = 78 ns))
+      report "***FAILED TEST: c07s02b04x00p20n01i02113 - Concatenation of two TIME arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02113arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2114.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2114.vhd
new file mode 100644
index 0000000..3987029
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2114.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2114.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02114ent IS
+END c07s02b04x00p20n01i02114ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02114arch OF c07s02b04x00p20n01i02114ent IS
+
+  TYPE     real_v is array (integer range <>) of real;
+  SUBTYPE     real_8 is real_v (1 to 8);
+  SUBTYPE     real_4 is real_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : real_4;
+    variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
+    variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
+    alias    l_alias   : real_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : real_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
+      report "***PASSED TEST:c07s02b04x00p20n01i02114"
+      severity NOTE;
+    assert ((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
+      report "***FAILED TEST: c07s02b04x00p20n01i02114 - Concatenation of two REAL aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02114arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2115.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2115.vhd
new file mode 100644
index 0000000..ddd9a4c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2115.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2115.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02115ent IS
+END c07s02b04x00p20n01i02115ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02115arch OF c07s02b04x00p20n01i02115ent IS
+
+  TYPE     real_v       is array (integer range <>) of real;
+  SUBTYPE     real_4       is real_v (1 to 4);
+  SUBTYPE     real_null    is real_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : real_4;
+    variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
+    variable r_operand : real_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (12.345, -67.890,12.345, -67.890)) and (result(1) = 12.345))
+      report "***PASSED TEST: c07s02b04x00p20n01i02115"
+      severity NOTE;
+    assert ((result = (12.345, -67.890,12.345, -67.890)) and (result(1) = 12.345))
+      report "***FAILED TEST: c07s02b04x00p20n01i02115 - Concatenation of null and REAL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02115arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2116.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2116.vhd
new file mode 100644
index 0000000..0017fd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2116.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2116.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02116ent IS
+END c07s02b04x00p20n01i02116ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02116arch OF c07s02b04x00p20n01i02116ent IS
+
+  TYPE     real_v is array (integer range <>) of real;
+  SUBTYPE     real_8 is real_v (1 to 8);
+  SUBTYPE     real_4 is real_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : real_8;
+    variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
+    variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
+      report "***PASSED TEST: c07s02b04x00p20n01i02116"
+      severity NOTE;
+    assert ((result = (12.345,-67.890,12.345,-67.890,-67.890,-67.890,12.345,12.345)) and (result(1) = 12.345))
+      report "***FAILED TEST: c07s02b04x00p20n01i02116 - Concatenation of two REAL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02116arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2117.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2117.vhd
new file mode 100644
index 0000000..db929b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2117.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2117.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02117ent IS
+END c07s02b04x00p20n01i02117ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02117arch OF c07s02b04x00p20n01i02117ent IS
+
+  TYPE     integer_v is array (integer range <>) of integer;
+  SUBTYPE     integer_8 is integer_v (1 to 8);
+  SUBTYPE     integer_4 is integer_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : integer_4;
+    variable l_operand : integer_4 := (123,789,123,789);
+    variable r_operand : integer_4 := (789,789,123,123);
+    alias    l_alias   : integer_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : integer_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT((result = (789,123,123,123)) and (result(1) = 789))
+      report "***PASSED TEST: c07s02b04x00p20n01i02117"
+      severity NOTE;
+    assert ((result = (789,123,123,123)) and (result(1) = 789))
+      report "***FAILED TEST: c07s02b04x00p20n01i02117 - Concatenation of two INTEGER aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02117arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2118.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2118.vhd
new file mode 100644
index 0000000..e12baec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2118.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2118.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02118ent IS
+END c07s02b04x00p20n01i02118ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02118arch OF c07s02b04x00p20n01i02118ent IS
+
+  TYPE     integer_v    is array (integer range <>) of integer;
+  SUBTYPE     integer_4    is integer_v (1 to 4);
+  SUBTYPE     integer_null    is integer_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : integer_4;
+    variable l_operand : integer_4 := (123,789,123,789);
+    variable r_operand : integer_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (123,789,123,789)) and (result(1) = 123))
+      report "***PASSED TEST: c07s02b04x00p20n01i02118"
+      severity NOTE;
+    assert ((result = (123,789,123,789)) and (result(1) = 123))
+      report "***FAILED TEST: c07s02b04x00p20n01i02118 - Concatenation of null and INTEGER arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02118arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2119.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2119.vhd
new file mode 100644
index 0000000..7f38400
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2119.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2119.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02119ent IS
+END c07s02b04x00p20n01i02119ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02119arch OF c07s02b04x00p20n01i02119ent IS
+
+  TYPE     integer_v    is array (integer range <>) of integer;
+  SUBTYPE     integer_4    is integer_v (1 to 4);
+  SUBTYPE     integer_null    is integer_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : integer_4;
+    variable l_operand : integer_null;
+    variable r_operand : integer_4 := (123,789,123,789);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (123,789,123,789)) and (result(1) = 123))
+      report "***PASSED TEST: c07s02b04x00p20n01i02119"
+      severity NOTE;
+    assert ((result = (123,789,123,789)) and (result(1) = 123))
+      report "***FAILED TEST: c07s02b04x00p20n01i02119 - Concatenation of null and INTEGER arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02119arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2120.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2120.vhd
new file mode 100644
index 0000000..db7b4fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2120.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2120.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02120ent IS
+END c07s02b04x00p20n01i02120ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02120arch OF c07s02b04x00p20n01i02120ent IS
+
+  TYPE     integer_v is array (integer range <>) of integer;
+  SUBTYPE     integer_8 is integer_v (1 to 8);
+  SUBTYPE     integer_4 is integer_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : integer_8;
+    variable l_operand : integer_4 := (123,789,123,789);
+    variable r_operand : integer_4 := (789,789,123,123);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (123,789,123,789,789,789,123,123)) and (result(1) = 123))
+      report "***PASSED TEST: c07s02b04x00p20n01i02120"
+      severity NOTE;
+    assert ((result = (123,789,123,789,789,789,123,123)) and (result(1) = 123))
+      report "***FAILED TEST: c07s02b04x00p20n01i02120 - Concatenation of null and INTEGER arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02120arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2121.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2121.vhd
new file mode 100644
index 0000000..1481f44
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2121.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2121.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02121ent IS
+END c07s02b04x00p20n01i02121ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02121arch OF c07s02b04x00p20n01i02121ent IS
+
+  TYPE     character_v is array (integer range <>) of character;
+  SUBTYPE     character_8 is character_v (1 to 8);
+  SUBTYPE     character_4 is character_v (1 to 4);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : character_4;
+    variable l_operand : character_4 := ('A','z','A','z');
+    variable r_operand : character_4 := ('z','z','A','A');
+    alias    l_alias   : character_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : character_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 20 ns;
+    assert NOT((result = ('z','A','A','A')) and (result(1)='z'))
+      report "***PASSED TEST: c07s02b04x00p20n01i02121"
+      severity NOTE;
+    assert ((result = ('z','A','A','A')) and (result(1)='z'))
+      report "***FAILED TEST: c07s02b04x00p20n01i02121 - Concatenation of two CHARACTER aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02121arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2122.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2122.vhd
new file mode 100644
index 0000000..78ed21c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2122.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2122.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02122ent IS
+END c07s02b04x00p20n01i02122ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02122arch OF c07s02b04x00p20n01i02122ent IS
+
+  TYPE        severity_level_v    is array (integer range <>) of severity_level;
+  SUBTYPE     severity_level_4    is severity_level_v (1 to 4);
+  SUBTYPE     severity_level_null    is severity_level_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : severity_level_4;
+    variable l_operand : severity_level_null;
+    variable r_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
+      report "***PASSED TEST: c07s02b04x00p20n01i02122"
+      severity NOTE;
+    assert ((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
+      report "***FAILED TEST: c07s02b04x00p20n01i02122 - Concatenation of null and SEVERITY_LEVEL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02122arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2123.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2123.vhd
new file mode 100644
index 0000000..4f68425
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2123.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2123.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02123ent IS
+END c07s02b04x00p20n01i02123ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02123arch OF c07s02b04x00p20n01i02123ent IS
+
+  TYPE        severity_level_v    is array (integer range <>) of severity_level;
+  SUBTYPE     severity_level_4    is severity_level_v (1 to 4);
+  SUBTYPE     severity_level_null    is severity_level_v (1 to 0);
+
+BEGIN
+  TESTING : PROCESS
+    variable result    : severity_level_4;
+    variable l_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
+    variable r_operand : severity_level_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 20 ns;
+    assert NOT((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
+      report "***PASSED TEST: c07s02b04x00p20n01i02123"
+      severity NOTE;
+    assert ((result = (NOTE , FAILURE , NOTE , FAILURE)) and (result(1)=NOTE))
+      report "***FAILED TEST: c07s02b04x00p20n01i02123 - Concatenation of null and SEVERITY_LEVEL arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02123arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2124.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2124.vhd
new file mode 100644
index 0000000..4ea3db2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2124.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2124.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02124ent IS
+END c07s02b04x00p20n01i02124ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02124arch OF c07s02b04x00p20n01i02124ent IS
+
+  procedure CheckConcat(
+    result       : STRING;
+    reference    : STRING;
+    left, right    : INTEGER
+    ) is
+    variable match : BOOLEAN;
+  begin
+    if result'LENGTH /= reference'LENGTH then
+      assert FALSE report "FAIL: length does not match";
+    elsif result'LEFT /= left then
+      assert FALSE report "FAIL: 'LEFT is wrong";
+    elsif result'RIGHT /= right then
+      assert FALSE report "FAIL: 'RIGHT is wrong";
+    elsif result /= reference then
+      assert FALSE report "FAIL: value is wrong";
+    else
+      assert result = reference report "FAIL: value is wrong";
+    end if;
+    assert NOT(   result'LENGTH = reference'LENGTH   and
+                  result'LEFT = left         and
+                  result'RIGHT = right         and
+                  result = reference         )
+      report "***PASSED TEST: c07s02b04x00p20n01i02124"
+      severity NOTE;
+    assert (   result'LENGTH = reference'LENGTH   and
+               result'LEFT = left         and
+               result'RIGHT = right         and
+               result = reference         )
+      report "***FAILED TEST: c07s02b04x00p20n01i02124 - Concatenation of string in function call test failed."
+      severity ERROR;
+  end;
+
+BEGIN
+  TESTING : PROCESS
+    subtype String3to3 is STRING(3 to 3);
+  BEGIN
+    CheckConcat(String3to3'("9") & "A", "9A", 3, 4);
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02124arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2125.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2125.vhd
new file mode 100644
index 0000000..b436717
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2125.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2125.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02125ent IS
+END c07s02b04x00p20n01i02125ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02125arch OF c07s02b04x00p20n01i02125ent IS
+
+  TYPE     boolean_v is array (integer range <>) of boolean;
+  SUBTYPE     boolean_5 is boolean_v (1 to 5);
+  SUBTYPE     boolean_4 is boolean_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_5;
+    variable l_operand : boolean_4    := (true, false, true, false);
+    variable r_operand : boolean    :=  true;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true, false, true, false, true)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02125"
+      severity NOTE;
+    assert ((result = (true, false, true, false, true)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02125 - Concatenation of element and BOOLEAN array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02125arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2126.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2126.vhd
new file mode 100644
index 0000000..0c15786
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2126.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2126.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02126ent IS
+END c07s02b04x00p20n01i02126ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02126arch OF c07s02b04x00p20n01i02126ent IS
+
+  TYPE    integer_v    is array (integer range <>) of integer;
+  SUBTYPE     integer_4     is integer_v (1 to 4);
+  SUBTYPE     integer_8     is integer_v (1 to 8);
+  SUBTYPE     integer_8_dwn     is integer_v (8 downto 1);
+
+BEGIN
+  TESTING: PROCESS
+    variable r_operand : integer_4 := ( 5,6,7,8 );
+    variable l_operand1: integer := 1;
+    variable l_operand2: integer := 2;
+    variable l_operand3: integer := 3;
+    variable l_operand4: integer := 4;
+    variable result    : integer_8;
+    variable result_dwn: integer_8_dwn;
+  BEGIN
+    result_dwn := l_operand1 &
+                  l_operand2 &
+                  l_operand3 &
+                  l_operand4 &
+                  l_operand2 &
+                  l_operand3 &
+                  l_operand2 &
+                  l_operand3;
+    
+    assert (result_dwn = (1,2,3,4,2,3,2,3))
+      report "integer implicit array concatenation failed"
+      severity FAILURE;
+
+    assert NOT(result_dwn = (1,2,3,4,2,3,2,3))
+      report "***PASSED TEST: c07s02b04x00p20n01i02126"
+      severity NOTE;
+    assert (result_dwn = (1,2,3,4,2,3,2,3))
+      report "***FAILED TEST: c07s02b04x00p20n01i02126 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02126arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2127.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2127.vhd
new file mode 100644
index 0000000..c9000b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2127.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2127.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02127ent IS
+END c07s02b04x00p20n01i02127ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02127arch OF c07s02b04x00p20n01i02127ent IS
+
+  TYPE     boolean_v    is array (integer range <>) of boolean;
+  SUBTYPE     boolean_1    is boolean_v (1 to 1);
+  SUBTYPE     boolean_null    is boolean_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_1;
+    variable l_operand : boolean    := true;
+    variable r_operand : boolean_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = true )
+      report "***PASSED TEST: c07s02b04x00p20n01i02127"
+      severity NOTE;
+    assert ( result(1) = true )
+      report "***FAILED TEST: c07s02b04x00p20n01i02127 - Concatenation of null and BOOLEAN element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02127arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2128.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2128.vhd
new file mode 100644
index 0000000..cc3d39b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2128.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2128.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02128ent IS
+END c07s02b04x00p20n01i02128ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02128arch OF c07s02b04x00p20n01i02128ent IS
+
+  TYPE     boolean_v is array (integer range <>) of boolean;
+  SUBTYPE     boolean_5 is boolean_v (1 to 5);
+  SUBTYPE     boolean_4 is boolean_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_5;
+    variable l_operand : boolean    := true;
+    variable r_operand : boolean_4    := (true, false, true, false);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true, true, false, true, false)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02128"
+      severity NOTE;
+    assert ((result = (true, true, false, true, false)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02128 - Concatenation of element and BOOLEAN array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02128arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2129.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2129.vhd
new file mode 100644
index 0000000..232433c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2129.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2129.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02129ent IS
+END c07s02b04x00p20n01i02129ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02129arch OF c07s02b04x00p20n01i02129ent IS
+
+  TYPE     boolean_v is array (integer range <>) of boolean;
+  SUBTYPE     boolean_5 is boolean_v (1 to 5);
+  SUBTYPE     boolean_4 is boolean_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_5;
+    variable l_operand : boolean    := true;
+    variable r_operand : boolean_4    := (true, false, true, false);
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true, true, false, true, false)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p20n01i02129"
+      severity NOTE;
+    assert ((result = (true, true, false, true, false)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p20n01i02129 - Concatenation of element and BOOLEAN array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02129arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc213.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc213.vhd
new file mode 100644
index 0000000..bf34caf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc213.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc213.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p03n01i00213ent IS
+END c03s01b01x00p03n01i00213ent;
+
+ARCHITECTURE c03s01b01x00p03n01i00213arch OF c03s01b01x00p03n01i00213ent IS
+  type pqr is (foo, swath, a, 'a');  -- No_failure_here
+  signal dude1 : pqr := foo;
+  signal dude2 : pqr;      
+  signal dude3 : pqr := a;
+  signal dude4 : pqr := 'a';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(dude1 = foo and dude2 = foo and dude3 = a and dude4 = 'a')
+      report "***PASSED TEST: c03s01b01x00p03n01i00213"
+      severity NOTE;
+    assert (dude1 = foo and dude2 = foo and dude3 = a and dude4 = 'a' )
+      report "***FAILED TEST: c03s01b01x00p03n01i00213 - When an enumeration type is being declared, that both identifiers and literals may be contained in the list of elements."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p03n01i00213arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2130.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2130.vhd
new file mode 100644
index 0000000..0db9fe3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2130.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2130.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02130ent IS
+END c07s02b04x00p21n01i02130ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02130arch OF c07s02b04x00p21n01i02130ent IS
+
+  TYPE     character_v    is array (integer range <>) of character;
+  SUBTYPE     character_1    is character_v (1 to 1);
+  SUBTYPE     character_null    is character_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : character_1;
+    variable l_operand : character_null;
+    variable r_operand : character := 'A';
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = 'A' )
+      report "***PASSED TEST: c07s02b04x00p21n01i02130"
+      severity NOTE;
+    assert ( result(1) = 'A' )
+      report "***FAILED TEST: c07s02b04x00p21n01i02130 - Concatenation of null array and character element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02130arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2131.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2131.vhd
new file mode 100644
index 0000000..9f9c272
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2131.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2131.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p20n01i02131ent IS
+END c07s02b04x00p20n01i02131ent;
+
+ARCHITECTURE c07s02b04x00p20n01i02131arch OF c07s02b04x00p20n01i02131ent IS
+
+  TYPE    integer_v  is array (integer range <>) of integer;
+  SUBTYPE     integer_4  is integer_v (1 to 4);
+  SUBTYPE     integer_8  is integer_v (1 to 8);
+
+BEGIN
+  TESTING: PROCESS
+    variable r_operand : integer_4 := ( 5,6,7,8 );
+    variable l_operand1: integer := 1;
+    variable l_operand2: integer := 2;
+    variable l_operand3: integer := 3;
+    variable l_operand4: integer := 4;
+    variable result    : integer_8;
+  BEGIN
+    result := l_operand1 &
+              l_operand2 &
+              l_operand3 &
+              l_operand4 &
+              r_operand;
+    assert (result = (1,2,3,4,5,6,7,8))
+      report "integer implicit array concatenation failed"
+      severity FAILURE;
+    assert NOT(result = (1,2,3,4,5,6,7,8))
+      report "***PASSED TEST: c07s02b04x00p20n01i02131"
+      severity NOTE;
+    assert (result = (1,2,3,4,5,6,7,8))
+      report "***FAILED TEST: c07s02b04x00p20n01i02131 - The left bound of this implicit array is the left bound of the index subtype of the array and its direction is ascending if the index subtype is ascending."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p20n01i02131arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2132.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2132.vhd
new file mode 100644
index 0000000..9b8ee5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2132.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2132.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02132ent IS
+END c07s02b04x00p21n01i02132ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02132arch OF c07s02b04x00p21n01i02132ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE     record_5 is record_v (1 to 5);
+  SUBTYPE     record_4 is record_v (1 to 4);
+BEGIN
+  TESTING: PROCESS
+    variable result    : record_5;
+    variable l_operand : simple_record :=  (12,34) ;
+    variable r_operand : record_4 := ((12,34), (56,78), (12,34), (56,78));
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ((12,34), (12,34), (56,78), (12,34), (56,78)))
+      report "***PASSED TEST: c07s02b04x00p21n01i02132"
+      severity NOTE;
+    assert ( result = ((12,34), (12,34), (56,78), (12,34), (56,78)))
+      report "***FAILED TEST:c07s02b04x00p21n01i02132 - Concatenation of element and RECORD array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02132arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2133.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2133.vhd
new file mode 100644
index 0000000..c267ac1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2133.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2133.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02133ent IS
+END c07s02b04x00p21n01i02133ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02133arch OF c07s02b04x00p21n01i02133ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE     record_5 is record_v (1 to 5);
+  SUBTYPE     record_4 is record_v (1 to 4);
+BEGIN
+  TESTING: PROCESS
+    variable result    : record_5;
+    variable l_operand : record_4 := ((12,34),(56,78),(12,34),(56,78));
+    variable r_operand : simple_record :=  (12,34);
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ((12,34),(56,78),(12,34),(56,78),(12,34))) 
+      report "***PASSED TEST: c07s02b04x00p21n01i02133"
+      severity NOTE;
+    assert ( result = ((12,34),(56,78),(12,34),(56,78),(12,34))) 
+      report "***FAILED TEST: c07s02b04x00p21n01i02133 - Concatenation of element and RECORD array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02133arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2134.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2134.vhd
new file mode 100644
index 0000000..c504b8e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2134.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2134.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02134ent IS
+END c07s02b04x00p21n01i02134ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02134arch OF c07s02b04x00p21n01i02134ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE  record_null is record_v (1 to 0);
+  SUBTYPE  record_1    is record_v (1 to 1);
+BEGIN
+  TESTING: PROCESS
+    variable result    : record_1;
+    variable l_operand : simple_record :=  (12,34) ;
+    variable r_operand : record_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = (12,34) )
+      report "***PASSED TEST: c07s02b04x00p21n01i02134"
+      severity NOTE;
+    assert ( result(1) = (12,34) )
+      report "***FAILED TEST: c07s02b04x00p21n01i02134 - Concatenation of null and RECORD element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02134arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2135.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2135.vhd
new file mode 100644
index 0000000..0fe47c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2135.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2135.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02135ent IS
+END c07s02b04x00p21n01i02135ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02135arch OF c07s02b04x00p21n01i02135ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE  record_null is record_v (1 to 0);
+  SUBTYPE  record_1    is record_v (1 to 1);
+BEGIN
+  TESTING: PROCESS
+    variable result    : record_1;
+    variable l_operand : record_null;
+    variable r_operand : simple_record :=  (12,34);
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = (12,34) )
+      report "***PASSED TEST: c07s02b04x00p21n01i02135"
+      severity NOTE;
+    assert ( result(1) = (12,34) )
+      report "***FAILED TEST: c07s02b04x00p21n01i02135 - Concatenation of null and RECORD element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02135arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2136.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2136.vhd
new file mode 100644
index 0000000..f860e73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2136.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2136.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02136ent IS
+END c07s02b04x00p21n01i02136ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02136arch OF c07s02b04x00p21n01i02136ent IS
+
+  TYPE     positive_v is array (integer range <>) of positive;
+  SUBTYPE     positive_5 is positive_v (1 to 5);
+  SUBTYPE     positive_4 is positive_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_5;
+    variable l_operand : positive :=  1 ;
+    variable r_operand : positive_4 := ( 1 ,  89 ,  1 ,  89  );
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ( 1 ,  1 ,  89 ,  1 ,  89 ))
+      report "***PASSED TEST: c07s02b04x00p21n01i02136"
+      severity NOTE;
+    assert ( result = ( 1 ,  1 ,  89 ,  1 ,  89 ))
+      report "***FAILED TEST: c07s02b04x00p21n01i02136 - Concatenation of element and POSITIVE array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02136arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2137.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2137.vhd
new file mode 100644
index 0000000..49f8c50
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2137.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2137.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02137ent IS
+END c07s02b04x00p21n01i02137ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02137arch OF c07s02b04x00p21n01i02137ent IS
+
+  TYPE     positive_v is array (integer range <>) of positive;
+  SUBTYPE     positive_5 is positive_v (1 to 5);
+  SUBTYPE     positive_4 is positive_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_5;
+    variable l_operand : positive_4 := ( 12,  56,  12,  56 );
+    variable r_operand : positive    :=  12;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ( 12, 56, 12, 56, 12 ))
+      report "***PASSED TEST: c07s02b04x00p21n01i02137"
+      severity NOTE;
+    assert ( result = ( 12, 56, 12, 56, 12 ))
+      report "***FAILED TEST: c07s02b04x00p21n01i02137 - Concatenation of element and POSITIVE array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02137arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2138.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2138.vhd
new file mode 100644
index 0000000..17dfe04
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2138.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2138.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02138ent IS
+END c07s02b04x00p21n01i02138ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02138arch OF c07s02b04x00p21n01i02138ent IS
+
+  TYPE     positive_v    is array (integer range <>) of positive;
+  SUBTYPE     positive_1    is positive_v (1 to 1);
+  SUBTYPE     positive_null    is positive_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_1;
+    variable l_operand : positive :=  1 ;
+    variable r_operand : positive_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = 1 )
+      report "***PASSED TEST: c07s02b04x00p21n01i02138"
+      severity NOTE;
+    assert ( result(1) = 1 )
+      report "***FAILED TEST: c07s02b04x00p21n01i02138 - Concatenation of null and POSITIVE element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02138arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2139.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2139.vhd
new file mode 100644
index 0000000..382eb4d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2139.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2139.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02139ent IS
+END c07s02b04x00p21n01i02139ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02139arch OF c07s02b04x00p21n01i02139ent IS
+
+  TYPE     positive_v    is array (integer range <>) of positive;
+  SUBTYPE     positive_1    is positive_v (1 to 1);
+  SUBTYPE     positive_null    is positive_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_1;
+    variable l_operand : positive_null;
+    variable r_operand : positive :=  1 ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = 1 )
+      report "***PASSED TEST: c07s02b04x00p21n01i02139"
+      severity NOTE;
+    assert ( result(1) = 1 )
+      report "***FAILED TEST: c07s02b04x00p21n01i02139 - Concatenation of null and POSITIVE element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02139arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2140.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2140.vhd
new file mode 100644
index 0000000..0b1b233
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2140.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2140.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02140ent IS
+END c07s02b04x00p21n01i02140ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02140arch OF c07s02b04x00p21n01i02140ent IS
+
+  TYPE     positive_v    is array (integer range <>) of positive;
+  SUBTYPE     positive_4    is positive_v (1 to 4);
+  SUBTYPE     positive_null    is positive_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_4;
+    variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
+    variable r_operand : positive_null;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ( 1, 89, 1, 89 ) )
+      report "***PASSED TEST: c07s02b04x00p21n01i02140"
+      severity NOTE;
+    assert ( result = ( 1, 89, 1, 89 ) )
+      report "***FAILED TEST: c07s02b04x00p21n01i02140 - Concatenation of null and POSITIVE arrays failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02140arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2141.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2141.vhd
new file mode 100644
index 0000000..b18f6b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2141.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2141.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02141ent IS
+END c07s02b04x00p21n01i02141ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02141arch OF c07s02b04x00p21n01i02141ent IS
+
+  TYPE     natural_v is array (integer range <>) of natural;
+  SUBTYPE     natural_5 is natural_v (1 to 5);
+  SUBTYPE     natural_4 is natural_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : natural_5;
+    variable l_operand : natural :=  0 ;
+    variable r_operand : natural_4 := ( 0 ,  23 ,  0 ,  23  );
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ( 0 ,  0 ,  23 ,  0 ,  23 ))
+      report "***PASSED TEST: c07s02b04x00p21n01i02141"
+      severity NOTE;
+    assert ( result = ( 0 ,  0 ,  23 ,  0 ,  23 ))
+      report "***FAILED TEST: c07s02b04x00p21n01i02141 - Concatenation of element and NATURAL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02141arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2142.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2142.vhd
new file mode 100644
index 0000000..967cd18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2142.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2142.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02142ent IS
+END c07s02b04x00p21n01i02142ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02142arch OF c07s02b04x00p21n01i02142ent IS
+
+  TYPE     natural_v is array (integer range <>) of natural;
+  SUBTYPE     natural_5 is natural_v (1 to 5);
+  SUBTYPE     natural_4 is natural_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : natural_5;
+    variable l_operand : natural_4    := ( 12 ,  56 ,  12 ,  56  );
+    variable r_operand : natural    :=  12 ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result = ( 12 ,  56 ,  12 ,  56 ,  12 ))
+      report "***PASSED TEST: c07s02b04x00p21n01i02142"
+      severity NOTE;
+    assert ( result = ( 12 ,  56 ,  12 ,  56 ,  12 ))
+      report "***FAILED TEST: c07s02b04x00p21n01i02142 - Concatenation of element and NATURAL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02142arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2143.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2143.vhd
new file mode 100644
index 0000000..79591fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2143.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2143.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02143ent IS
+END c07s02b04x00p21n01i02143ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02143arch OF c07s02b04x00p21n01i02143ent IS
+
+  TYPE     natural_v    is array (integer range <>) of natural;
+  SUBTYPE     natural_1    is natural_v (1 to 1);
+  SUBTYPE     natural_null    is natural_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : natural_1;
+    variable l_operand : natural :=  0 ;
+    variable r_operand : natural_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = 0 )
+      report "***PASSED TEST: c07s02b04x00p21n01i02143"
+      severity NOTE;
+    assert ( result(1) = 0 )
+      report "***FAILED TEST: c07s02b04x00p21n01i02143 - Concatenation of null and NATURAL element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02143arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2144.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2144.vhd
new file mode 100644
index 0000000..d5b4927
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2144.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2144.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02144ent IS
+END c07s02b04x00p21n01i02144ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02144arch OF c07s02b04x00p21n01i02144ent IS
+
+  TYPE     natural_v    is array (integer range <>) of natural;
+  SUBTYPE     natural_1    is natural_v (1 to 1);
+  SUBTYPE     natural_null    is natural_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : natural_1;
+    variable l_operand : natural_null;
+    variable r_operand : natural := 0;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT( result(1) = 0 )
+      report "***PASSED TEST: c07s02b04x00p21n01i02144"
+      severity NOTE;
+    assert ( result(1) = 0 )
+      report "***FAILED TEST: c07s02b04x00p21n01i02144 - Concatenation of null and NATURAL element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02144arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2145.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2145.vhd
new file mode 100644
index 0000000..e8c6477
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2145.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2145.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02145ent IS
+END c07s02b04x00p21n01i02145ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02145arch OF c07s02b04x00p21n01i02145ent IS
+
+  TYPE     time_v is array (integer range <>) of time;
+  SUBTYPE     time_4 is time_v (1 to 4);
+  SUBTYPE     time_5 is time_v (1 to 5);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : time_5;
+    variable l_operand : time    :=  78 ns ;
+    variable r_operand : time_4    := ( 78 ns, 23 ns, 78 ns, 23 ns);
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (78 ns, 78 ns, 23 ns, 78 ns, 23 ns)) and (result(1) = 78 ns))
+      report "***PASSED TEST: c07s02b04x00p21n01i02145"
+      severity NOTE;
+    assert ((result = (78 ns, 78 ns, 23 ns, 78 ns, 23 ns)) and (result(1) = 78 ns))
+      report "***FAILED TEST: c07s02b04x00p21n01i02145 - Concatenation of element and TIME array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02145arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2146.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2146.vhd
new file mode 100644
index 0000000..bf914ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2146.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2146.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02146ent IS
+END c07s02b04x00p21n01i02146ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02146arch OF c07s02b04x00p21n01i02146ent IS
+
+  TYPE     time_v is array (integer range <>) of time;
+  SUBTYPE     time_4 is time_v (1 to 4);
+  SUBTYPE     time_5 is time_v (1 to 5);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : time_5;
+    variable l_operand : time_4    := ( 12 ns,  56 ns,  12 ns,  56 ns );
+    variable r_operand : time    :=  12 ns;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (12 ns,  56 ns,  12 ns,  56 ns,  12 ns)) and (result(1) = 12 ns))
+      report "***PASSED TEST: c07s02b04x00p21n01i02146"
+      severity NOTE;
+    assert ((result = (12 ns,  56 ns,  12 ns,  56 ns,  12 ns)) and (result(1) = 12 ns))
+      report "***FAILED TEST: c07s02b04x00p21n01i02146 - Concatenation of element and TIME array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02146arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2147.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2147.vhd
new file mode 100644
index 0000000..c9f1c8e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2147.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2147.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02147ent IS
+END c07s02b04x00p21n01i02147ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02147arch OF c07s02b04x00p21n01i02147ent IS
+
+  TYPE     time_v       is array (integer range <>) of time;
+  SUBTYPE     time_1       is time_v (1 to 1);
+  SUBTYPE     time_null    is time_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : time_1;
+    variable l_operand : time    :=  78 ns ;
+    variable r_operand : time_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1) = 78 ns) 
+      report "***PASSED TEST: c07s02b04x00p21n01i02147"
+      severity NOTE;
+    assert (result(1) = 78 ns) 
+      report "***FAILED TEST: c07s02b04x00p21n01i02147 - Concatenation of null and TIME element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02147arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2148.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2148.vhd
new file mode 100644
index 0000000..a387d65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2148.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2148.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02148ent IS
+END c07s02b04x00p21n01i02148ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02148arch OF c07s02b04x00p21n01i02148ent IS
+
+  TYPE     time_v       is array (integer range <>) of time;
+  SUBTYPE     time_1       is time_v (1 to 1);
+  SUBTYPE     time_null    is time_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : time_1;
+    variable l_operand : time_null;
+    variable r_operand : time :=  78 ns ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1) = 78 ns) 
+      report "***PASSED TEST: c07s02b04x00p21n01i02148"
+      severity NOTE;
+    assert (result(1) = 78 ns) 
+      report "***FAILED TEST: c07s02b04x00p21n01i02148 - Concatenation of null and TIME element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02148arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2149.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2149.vhd
new file mode 100644
index 0000000..56ed0a0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2149.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2149.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02149ent IS
+END c07s02b04x00p21n01i02149ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02149arch OF c07s02b04x00p21n01i02149ent IS
+
+  TYPE     real_v is array (integer range <>) of real;
+  SUBTYPE     real_5 is real_v (1 to 5);
+  SUBTYPE     real_4 is real_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : real_5;
+    variable l_operand : real    := 12.345;
+    variable r_operand : real_4    := (12.345, -67.890, 12.345, -67.890);
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (12.345, 12.345, -67.890, 12.345, -67.890)) and (result(1) = 12.345))
+      report "***PASSED TEST: c07s02b04x00p21n01i02149"
+      severity NOTE;
+    assert ((result = (12.345, 12.345, -67.890, 12.345, -67.890)) and (result(1) = 12.345))
+      report "***FAILED TEST: c07s02b04x00p21n01i02149 - Concatenation of element and REAL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02149arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2150.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2150.vhd
new file mode 100644
index 0000000..18994c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2150.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2150.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02150ent IS
+END c07s02b04x00p21n01i02150ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02150arch OF c07s02b04x00p21n01i02150ent IS
+
+  TYPE     real_v is array (integer range <>) of real;
+  SUBTYPE     real_5 is real_v (1 to 5);
+  SUBTYPE     real_4 is real_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : real_5;
+    variable l_operand : real_4    := ( 12.34,  56.78,  12.34,  56.78 );
+    variable r_operand : real    :=  12.34;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (12.34,  56.78,  12.34,  56.78,  12.34)) and (result(1) = 12.34))
+      report "***PASSED TEST: c07s02b04x00p21n01i02150"
+      severity NOTE;
+    assert ((result = (12.34,  56.78,  12.34,  56.78,  12.34)) and (result(1) = 12.34))
+      report "***FAILED TEST: c07s02b04x00p21n01i02150 - Concatenation of element and REAL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02150arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2151.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2151.vhd
new file mode 100644
index 0000000..38fc528
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2151.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2151.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02151ent IS
+END c07s02b04x00p21n01i02151ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02151arch OF c07s02b04x00p21n01i02151ent IS
+
+  TYPE     real_v       is array (integer range <>) of real;
+  SUBTYPE     real_1       is real_v (1 to 1);
+  SUBTYPE     real_null    is real_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : real_1;
+    variable l_operand : real_null;
+    variable r_operand : real := 12.345;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1) = 12.345)
+      report "***PASSED TEST: c07s02b04x00p21n01i02151"
+      severity NOTE;
+    assert (result(1) = 12.345)
+      report "***FAILED TEST: c07s02b04x00p21n01i02151 - Concatenation of null and REAL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02151arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2152.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2152.vhd
new file mode 100644
index 0000000..6f575d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2152.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2152.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02152ent IS
+END c07s02b04x00p21n01i02152ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02152arch OF c07s02b04x00p21n01i02152ent IS
+
+  TYPE     integer_v is array (integer range <>) of integer;
+  SUBTYPE     integer_5 is integer_v (1 to 5);
+  SUBTYPE     integer_4 is integer_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : integer_5;
+    variable l_operand : integer := 123;
+    variable r_operand : integer_4 := (123, 789, 123, 789 );
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (123, 123, 789, 123, 789)) and (result(1) = 123))
+      report "***PASSED TEST: c07s02b04x00p21n01i02152"
+      severity NOTE;
+    assert ((result = (123, 123, 789, 123, 789)) and (result(1) = 123))
+      report "***FAILED TEST: c07s02b04x00p21n01i02152 - Concatenation of element and INTEGER array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02152arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2153.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2153.vhd
new file mode 100644
index 0000000..6e4ba35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2153.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2153.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02153ent IS
+END c07s02b04x00p21n01i02153ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02153arch OF c07s02b04x00p21n01i02153ent IS
+
+  TYPE     integer_v is array (integer range <>) of integer;
+  SUBTYPE     integer_5 is integer_v (1 to 5);
+  SUBTYPE     integer_4 is integer_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : integer_5;
+    variable l_operand : integer_4    := (123, 789, 123, 789 );
+    variable r_operand : integer    := 123;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (123, 789, 123, 789, 123)) and (result(1) = 123))
+      report "***PASSED TEST: c07s02b04x00p21n01i02153"
+      severity NOTE;
+    assert ((result = (123, 789, 123, 789, 123)) and (result(1) = 123))
+      report "***FAILED TEST: c07s02b04x00p21n01i02153 - Concatenation of element and INTEGER array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02153arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2154.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2154.vhd
new file mode 100644
index 0000000..41f4915
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2154.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2154.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02154ent IS
+END c07s02b04x00p21n01i02154ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02154arch OF c07s02b04x00p21n01i02154ent IS
+
+  TYPE     integer_v    is array (integer range <>) of integer;
+  SUBTYPE     integer_1    is integer_v (1 to 1);
+  SUBTYPE     integer_null    is integer_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : integer_1;
+    variable l_operand : integer    := 123;
+    variable r_operand : integer_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1)=123)
+      report "***PASSED TEST: c07s02b04x00p21n01i02154"
+      severity NOTE;
+    assert (result(1)=123)
+      report "***FAILED TEST: c07s02b04x00p21n01i02154 - Concatenation of null and INTEGER element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02154arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2155.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2155.vhd
new file mode 100644
index 0000000..2b2fed2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2155.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2155.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02155ent IS
+END c07s02b04x00p21n01i02155ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02155arch OF c07s02b04x00p21n01i02155ent IS
+
+  TYPE     integer_v    is array (integer range <>) of integer;
+  SUBTYPE     integer_1    is integer_v (1 to 1);
+  SUBTYPE     integer_null    is integer_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : integer_1;
+    variable l_operand : integer_null;
+    variable r_operand : integer := 123;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1)=123)
+      report "***PASSED TEST: c07s02b04x00p21n01i02155"
+      severity NOTE;
+    assert (result(1)=123)
+      report "***FAILED TEST: c07s02b04x00p21n01i02155 - Concatenation of null and INTEGER element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02155arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2156.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2156.vhd
new file mode 100644
index 0000000..3eb69ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2156.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2156.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02156ent IS
+END c07s02b04x00p21n01i02156ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02156arch OF c07s02b04x00p21n01i02156ent IS
+
+  TYPE     character_v is array (integer range <>) of character;
+  SUBTYPE     character_5 is character_v (1 to 5);
+  SUBTYPE     character_4 is character_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : character_5;
+    variable l_operand : character_4    := ('A', 'z', 'A', 'z' );
+    variable r_operand : character       := 'A';
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result=('A', 'z', 'A', 'z', 'A'))
+      report "***PASSED TEST: c07s02b04x00p21n01i02156"
+      severity NOTE;
+    assert (result=('A', 'z', 'A', 'z', 'A'))
+      report "***FAILED TEST: c07s02b04x00p21n01i02156 - Concatenation of CHARACTER element and CHARACTER array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02156arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2157.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2157.vhd
new file mode 100644
index 0000000..28cd93b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2157.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2157.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02157ent IS
+END c07s02b04x00p21n01i02157ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02157arch OF c07s02b04x00p21n01i02157ent IS
+
+  TYPE     severity_level_v    is array (integer range <>) of severity_level;    
+  SUBTYPE     severity_level_1    is severity_level_v (1 to 1);
+  SUBTYPE     severity_level_null    is severity_level_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : severity_level_1;
+    variable l_operand : severity_level_null;
+    variable r_operand : severity_level :=  NOTE ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1)=NOTE)
+      report "***PASSED TEST: c07s02b04x00p21n01i02157"
+      severity NOTE;
+    assert (result(1)=NOTE)
+      report "***FAILED TEST: c07s02b04x00p21n01i02157 - Concatenation of null and SEVERITY_LEVEL element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02157arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2158.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2158.vhd
new file mode 100644
index 0000000..08122e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2158.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2158.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02158ent IS
+END c07s02b04x00p21n01i02158ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02158arch OF c07s02b04x00p21n01i02158ent IS
+
+  TYPE     severity_level_v    is array (integer range <>) of severity_level;    
+  SUBTYPE     severity_level_1    is severity_level_v (1 to 1);
+  SUBTYPE     severity_level_null    is severity_level_v (1 to 0);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : severity_level_1;
+    variable l_operand : severity_level :=  NOTE ;
+    variable r_operand : severity_level_null;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result(1)=NOTE)
+      report "***PASSED TEST: c07s02b04x00p21n01i02158"
+      severity NOTE;
+    assert (result(1)=NOTE)
+      report "***FAILED TEST: c07s02b04x00p21n01i02158 - Concatenation of null and SEVERITY_LEVEL element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02158arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2159.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2159.vhd
new file mode 100644
index 0000000..1516218
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2159.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2159.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p21n01i02159ent IS
+END c07s02b04x00p21n01i02159ent;
+
+ARCHITECTURE c07s02b04x00p21n01i02159arch OF c07s02b04x00p21n01i02159ent IS
+
+  TYPE     severity_level_v is array (integer range <>) of severity_level;    
+  SUBTYPE  severity_level_5 is severity_level_v (1 to 5);
+  SUBTYPE  severity_level_4 is severity_level_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : severity_level_5;
+    variable l_operand : severity_level :=  NOTE ;
+    variable r_operand : severity_level_4 := ( NOTE ,  FAILURE ,  NOTE ,  FAILURE  );
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
+      report "***PASSED TEST: c07s02b04x00p21n01i02159"
+      severity NOTE;
+    assert ((result=(NOTE,NOTE,FAILURE,NOTE,FAILURE)) and (result(1)=NOTE))
+      report "***FAILED TEST: c07s02b04x00p21n01i02159 - Concatenation of element and SEVERITY_LEVEL array failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p21n01i02159arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2160.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2160.vhd
new file mode 100644
index 0000000..be0ac22
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2160.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2160.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02160ent IS
+END c07s02b04x00p22n01i02160ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02160arch OF c07s02b04x00p22n01i02160ent IS
+
+  TYPE     boolean_v is array (integer range <>) of boolean;
+  SUBTYPE     boolean_2 is boolean_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : boolean_2;
+    variable l_operand : boolean := true;
+    variable r_operand : boolean := false;
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = (true,false)) and (result(1) = true))
+      report "***PASSED TEST: c07s02b04x00p22n01i02160"
+      severity NOTE;
+    assert ((result = (true,false)) and (result(1) = true))
+      report "***FAILED TEST: c07s02b04x00p22n01i02160 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02160arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2161.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2161.vhd
new file mode 100644
index 0000000..d08ca3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2161.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2161.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02161ent IS
+END c07s02b04x00p22n01i02161ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02161arch OF c07s02b04x00p22n01i02161ent IS
+
+  TYPE     bit_v is array (integer range <>) of bit;
+  SUBTYPE     bit_2 is bit_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : bit_2;
+    variable l_operand : bit := '1';
+    variable r_operand : bit := '0';
+  BEGIN
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = ('1','0')) and (result(1) = '1'))
+      report "***PASSED TEST: c07s02b04x00p22n01i02161"
+      severity NOTE;
+    assert ((result = ('1','0')) and (result(1) = '1'))
+      report "***FAILED TEST: c07s02b04x00p22n01i02161 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02161arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2162.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2162.vhd
new file mode 100644
index 0000000..0a04430
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2162.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2162.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02162ent IS
+END c07s02b04x00p22n01i02162ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02162arch OF c07s02b04x00p22n01i02162ent IS
+
+  TYPE     simple_record is record
+                              data_1 : integer;
+                              data_2 : integer;
+                            end record;
+  TYPE     record_v is array (integer range <>) of simple_record;
+  SUBTYPE     record_2 is record_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : record_2;
+    variable l_operand : simple_record :=  (12,34) ;
+    variable r_operand : simple_record :=  (56,78) ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result = ( (12,34), (56,78) ))
+      report "***PASSED TEST: c07s02b04x00p22n01i02162"
+      severity NOTE;
+    assert (result = ( (12,34), (56,78) ))
+      report "***FAILED TEST: c07s02b04x00p22n01i02162 - Concatenation of record element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02162arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2163.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2163.vhd
new file mode 100644
index 0000000..59ad661
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2163.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2163.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02163ent IS
+END c07s02b04x00p22n01i02163ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02163arch OF c07s02b04x00p22n01i02163ent IS
+
+  TYPE     positive_v is array (integer range <>) of positive;
+  SUBTYPE     positive_2 is positive_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : positive_2;
+    variable l_operand : positive :=  1 ;
+    variable r_operand : positive :=  89 ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result = ( 1, 89 )) 
+      report "***PASSED TEST: c07s02b04x00p22n01i02163"
+      severity NOTE;
+    assert (result = ( 1, 89 )) 
+      report "***FAILED TEST: c07s02b04x00p22n01i02163 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02163arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2164.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2164.vhd
new file mode 100644
index 0000000..558940c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2164.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2164.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02164ent IS
+END c07s02b04x00p22n01i02164ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02164arch OF c07s02b04x00p22n01i02164ent IS
+
+  TYPE     natural_v is array (integer range <>) of natural;
+  SUBTYPE     natural_2 is natural_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : natural_2;
+    variable l_operand : natural :=  0 ;
+    variable r_operand : natural :=  23 ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result = ( 0, 23 ))
+      report "***PASSED TEST: c07s02b04x00p22n01i02164"
+      severity NOTE;
+    assert (result = ( 0, 23 ))
+      report "***FAILED TEST: c07s02b04x00p22n01i02164 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02164arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2165.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2165.vhd
new file mode 100644
index 0000000..cd12114
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2165.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2165.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02165ent IS
+END c07s02b04x00p22n01i02165ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02165arch OF c07s02b04x00p22n01i02165ent IS
+
+  TYPE     time_v is array (integer range <>) of time;
+  SUBTYPE     time_2 is time_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : time_2;
+    variable l_operand : time :=  78 ns ;
+    variable r_operand : time :=  23 ns ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(result = ( 78 ns, 23 ns ))
+      report "***PASSED TEST: c07s02b04x00p22n01i02165"
+      severity NOTE;
+    assert (result = ( 78 ns, 23 ns ))
+      report "***FAILED TEST: c07s02b04x00p22n01i02165 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02165arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2166.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2166.vhd
new file mode 100644
index 0000000..9c9d2a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2166.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2166.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02166ent IS
+END c07s02b04x00p22n01i02166ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02166arch OF c07s02b04x00p22n01i02166ent IS
+
+  TYPE     real_v is array (integer range <>) of real;
+  SUBTYPE     real_2 is real_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : real_2;
+    variable l_operand : real := 12.345;
+    variable r_operand : real :=  -67.890;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = ( 12.345,  -67.890 )) and (result(1) = 12.345))
+      report "***PASSED TEST: c07s02b04x00p22n01i02166"
+      severity NOTE;
+    assert ((result = ( 12.345,  -67.890 )) and (result(1) = 12.345))
+      report "***FAILED TEST: c07s02b04x00p22n01i02166 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02166arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2167.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2167.vhd
new file mode 100644
index 0000000..97e648a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2167.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2167.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02167ent IS
+END c07s02b04x00p22n01i02167ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02167arch OF c07s02b04x00p22n01i02167ent IS
+
+  TYPE     character_v is array (integer range <>) of character;
+  SUBTYPE     character_2 is character_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : character_2;
+    variable l_operand : character := 'A';
+    variable r_operand : character := 'z';
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT((result = ('A', 'z')) and (result(1)='A'))
+      report "***PASSED TEST: c07s02b04x00p22n01i02167"
+      severity NOTE;
+    assert ((result = ('A', 'z')) and (result(1)='A'))
+      report "***FAILED TEST: c07s02b04x00p22n01i02167 - Concatenation of CHARACTER element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02167arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2168.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2168.vhd
new file mode 100644
index 0000000..8518523
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2168.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2168.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02168ent IS
+END c07s02b04x00p22n01i02168ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02168arch OF c07s02b04x00p22n01i02168ent IS
+
+  TYPE     severity_level_v is array (integer range <>) of severity_level;    
+  SUBTYPE     severity_level_2 is severity_level_v (1 to 2);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : severity_level_2;
+    variable l_operand : severity_level :=  NOTE ;
+    variable r_operand : severity_level :=  FAILURE ;
+  BEGIN
+--
+-- The element is treated as an implicit single element array !
+--
+    result := l_operand & r_operand;
+    wait for 5 ns;
+    assert NOT(( result = (NOTE,FAILURE)) and (result(1) = NOTE))
+      report "***PASSED TEST: c07s02b04x00p22n01i02168"
+      severity NOTE;
+    assert (( result = (NOTE,FAILURE)) and (result(1) = NOTE))
+      report "***FAILED TEST: c07s02b04x00p22n01i02168 - Concatenation of element and element failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02168arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2169.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2169.vhd
new file mode 100644
index 0000000..35f91ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2169.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2169.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p22n01i02169ent IS
+END c07s02b04x00p22n01i02169ent;
+
+ARCHITECTURE c07s02b04x00p22n01i02169arch OF c07s02b04x00p22n01i02169ent IS
+
+  TYPE     severity_level_v is array (integer range <>) of severity_level;    
+  SUBTYPE  severity_level_8 is severity_level_v (1 to 8);
+  SUBTYPE  severity_level_4 is severity_level_v (1 to 4);
+
+BEGIN
+  TESTING: PROCESS
+    variable result    : severity_level_4;
+    variable l_operand : severity_level_4 := ( NOTE , FAILURE , NOTE , FAILURE );
+    variable r_operand : severity_level_4 := ( FAILURE , FAILURE , NOTE , NOTE );
+    alias    l_alias   : severity_level_v (1 to 2) is l_operand (2 to 3);
+    alias    r_alias   : severity_level_v (1 to 2) is r_operand (3 to 4);
+  BEGIN
+    result := l_alias & r_alias;
+    wait for 5 ns;
+    assert NOT(( result = ( FAILURE , NOTE , NOTE , NOTE )) and ( result(1) =  FAILURE  ))
+      report "***PASSED TEST: c07s02b04x00p22n01i02169"
+      severity NOTE;
+    assert (( result = ( FAILURE , NOTE , NOTE , NOTE )) and ( result(1) =  FAILURE  ))
+      report "***FAILED TEST: c07s02b04x00p22n01i02169 - Concatenation of two SEVERITY_LEVEL aliases failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p22n01i02169arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc217.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc217.vhd
new file mode 100644
index 0000000..dac01fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc217.vhd
@@ -0,0 +1,328 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc217.vhd,v 1.2 2005-03-21 17:33:22 dmartin Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p06n02i00217ent IS
+END c03s01b01x00p06n02i00217ent;
+
+ARCHITECTURE c03s01b01x00p06n02i00217arch OF c03s01b01x00p06n02i00217ent IS
+
+BEGIN
+   TESTING: PROCESS
+   BEGIN
+   assert NOT ((character'pos(NUL) =   0) and
+                    (character'pos(SOH) =   1) and
+                    (character'pos(STX) =   2) and
+                    (character'pos(ETX) =   3) and
+                    (character'pos(EOT) =   4) and
+                    (character'pos(ENQ) =   5) and
+                    (character'pos(ACK) =   6) and
+                    (character'pos(BEL) =   7) and
+                    (character'pos(BS ) =   8) and
+                    (character'pos(HT ) =   9) and
+                    (character'pos(LF ) =  10) and
+                    (character'pos(VT ) =  11) and
+                    (character'pos(FF ) =  12) and
+                    (character'pos(CR ) =  13) and
+                    (character'pos(SO ) =  14) and
+                    (character'pos(SI ) =  15) and
+                    (character'pos(DLE) =  16) and
+                    (character'pos(DC1) =  17) and
+                    (character'pos(DC2) =  18) and
+                    (character'pos(DC3) =  19) and
+                    (character'pos(DC4) =  20) and
+                    (character'pos(NAK) =  21) and
+                    (character'pos(SYN) =  22) and
+                    (character'pos(ETB) =  23) and
+                    (character'pos(CAN) =  24) and
+                    (character'pos(EM ) =  25) and
+                    (character'pos(SUB) =  26) and
+                    (character'pos(ESC) =  27) and
+                    (character'pos(FSP) =  28) and
+                    (character'pos(GSP) =  29) and
+                    (character'pos(RSP) =  30) and
+                    (character'pos(USP) =  31) and
+                    (character'pos(' ') =  32) and
+                    (character'pos('!') =  33) and
+                    (character'pos('"') =  34) and
+                    (character'pos('#') =  35) and
+                    (character'pos('$') =  36) and
+                    (character'pos('%') =  37) and
+                    (character'pos('&') =  38) and
+                    (character'pos(''') =  39) and
+                    (character'pos('(') =  40) and
+                    (character'pos(')') =  41) and
+                    (character'pos('*') =  42) and
+                    (character'pos('+') =  43) and
+                    (character'pos(',') =  44) and
+                    (character'pos('-') =  45) and
+                    (character'pos('.') =  46) and
+                    (character'pos('/') =  47) and
+                    (character'pos('0') =  48) and
+                    (character'pos('1') =  49) and
+                    (character'pos('2') =  50) and
+                    (character'pos('3') =  51) and
+                    (character'pos('4') =  52) and
+                    (character'pos('5') =  53) and
+                    (character'pos('6') =  54) and
+                    (character'pos('7') =  55) and
+                    (character'pos('8') =  56) and
+                    (character'pos('9') =  57) and
+                    (character'pos(':') =  58) and
+                    (character'pos(';') =  59) and
+                    (character'pos('<') =  60) and
+                    (character'pos('=') =  61) and
+                    (character'pos('>') =  62) and
+                    (character'pos('?') =  63) and
+          (character'pos('@') =  64) and
+                    (character'pos('A') =  65) and
+                    (character'pos('B') =  66) and
+                    (character'pos('C') =  67) and
+                    (character'pos('D') =  68) and
+                    (character'pos('E') =  69) and
+                    (character'pos('F') =  70) and
+                    (character'pos('G') =  71) and
+                    (character'pos('H') =  72) and
+                    (character'pos('I') =  73) and
+                    (character'pos('J') =  74) and
+                    (character'pos('K') =  75) and
+                    (character'pos('L') =  76) and
+                    (character'pos('M') =  77) and
+                    (character'pos('N') =  78) and
+                    (character'pos('O') =  79) and
+                    (character'pos('P') =  80) and
+                    (character'pos('Q') =  81) and
+                    (character'pos('R') =  82) and
+                    (character'pos('S') =  83) and
+                    (character'pos('T') =  84) and
+                    (character'pos('U') =  85) and
+                    (character'pos('V') =  86) and
+                    (character'pos('W') =  87) and
+                    (character'pos('X') =  88) and
+                    (character'pos('Y') =  89) and
+                    (character'pos('Z') =  90) and
+                    (character'pos('[') =  91) and
+                    (character'pos('\') =  92) and
+                    (character'pos(']') =  93) and
+                    (character'pos('^') =  94) and
+                    (character'pos('_') =  95) and
+                    (character'pos('`') =  96) and
+                    (character'pos('a') =  97) and
+                    (character'pos('b') =  98) and
+                    (character'pos('c') =  99) and
+                    (character'pos('d') = 100) and
+                    (character'pos('e') = 101) and
+                    (character'pos('f') = 102) and
+                    (character'pos('g') = 103) and
+                    (character'pos('h') = 104) and
+                    (character'pos('i') = 105) and
+                    (character'pos('j') = 106) and
+                    (character'pos('k') = 107) and
+                    (character'pos('l') = 108) and
+                    (character'pos('m') = 109) and
+                    (character'pos('n') = 110) and
+                    (character'pos('o') = 111) and
+                    (character'pos('p') = 112) and
+                    (character'pos('q') = 113) and
+                    (character'pos('r') = 114) and
+                    (character'pos('s') = 115) and
+                    (character'pos('t') = 116) and
+                    (character'pos('u') = 117) and
+                    (character'pos('v') = 118) and
+                    (character'pos('w') = 119) and
+                    (character'pos('x') = 120) and
+                    (character'pos('y') = 121) and
+                    (character'pos('z') = 122) and
+                    (character'pos('{') = 123) and
+                    (character'pos('|') = 124) and
+                    (character'pos('}') = 125) and
+                    (character'pos('~') = 126) and
+                    (character'pos(DEL) = 127) and
+          (character'pos(character'right) = 127) and 
+                    (bit'pos('0') = 0) and
+                    (bit'pos('1') = 1) and
+                    (bit'pos(bit'right) = 1) and
+                    (boolean'pos(false) = 0) and
+                    (boolean'pos(true)  = 1) and
+                    (boolean'pos(boolean'right) = 1) and
+                    (severity_level'pos(NOTE)    = 0) and
+                    (severity_level'pos(WARNING) = 1) and
+                    (severity_level'pos(ERROR)   = 2) and
+                    (severity_level'pos(FAILURE) = 3) and
+                    (severity_level'pos(severity_level'right)
+= 3))
+      report "***PASSED TEST: c03s01b01x00p06n02i00217"
+      severity NOTE;
+   assert (    (character'pos(NUL) =   0) and
+                    (character'pos(SOH) =   1) and
+                    (character'pos(STX) =   2) and
+                    (character'pos(ETX) =   3) and
+                    (character'pos(EOT) =   4) and
+                    (character'pos(ENQ) =   5) and
+                    (character'pos(ACK) =   6) and
+                    (character'pos(BEL) =   7) and
+                    (character'pos(BS ) =   8) and
+                    (character'pos(HT ) =   9) and
+                    (character'pos(LF ) =  10) and
+                    (character'pos(VT ) =  11) and
+                    (character'pos(FF ) =  12) and
+                    (character'pos(CR ) =  13) and
+                    (character'pos(SO ) =  14) and
+                    (character'pos(SI ) =  15) and
+                    (character'pos(DLE) =  16) and
+                    (character'pos(DC1) =  17) and
+                    (character'pos(DC2) =  18) and
+                    (character'pos(DC3) =  19) and
+                    (character'pos(DC4) =  20) and
+                    (character'pos(NAK) =  21) and
+                    (character'pos(SYN) =  22) and
+                    (character'pos(ETB) =  23) and
+                    (character'pos(CAN) =  24) and
+                    (character'pos(EM ) =  25) and
+                    (character'pos(SUB) =  26) and
+                    (character'pos(ESC) =  27) and
+                    (character'pos(FSP) =  28) and
+                    (character'pos(GSP) =  29) and
+                    (character'pos(RSP) =  30) and
+                    (character'pos(USP) =  31) and
+                    (character'pos(' ') =  32) and
+                    (character'pos('!') =  33) and
+                    (character'pos('"') =  34) and
+                    (character'pos('#') =  35) and
+                    (character'pos('$') =  36) and
+                    (character'pos('%') =  37) and
+                    (character'pos('&') =  38) and
+                    (character'pos(''') =  39) and
+                    (character'pos('(') =  40) and
+                    (character'pos(')') =  41) and
+                    (character'pos('*') =  42) and
+                    (character'pos('+') =  43) and
+                    (character'pos(',') =  44) and
+                    (character'pos('-') =  45) and
+                    (character'pos('.') =  46) and
+                    (character'pos('/') =  47) and
+                    (character'pos('0') =  48) and
+                    (character'pos('1') =  49) and
+                    (character'pos('2') =  50) and
+                    (character'pos('3') =  51) and
+                    (character'pos('4') =  52) and
+                    (character'pos('5') =  53) and
+                    (character'pos('6') =  54) and
+                    (character'pos('7') =  55) and
+          (character'pos('8') =  56) and
+                    (character'pos('9') =  57) and
+                    (character'pos(':') =  58) and
+                    (character'pos(';') =  59) and
+                    (character'pos('<') =  60) and
+                    (character'pos('=') =  61) and
+                    (character'pos('>') =  62) and
+                    (character'pos('?') =  63) and
+                    (character'pos('@') =  64) and
+                    (character'pos('A') =  65) and
+                    (character'pos('B') =  66) and
+                    (character'pos('C') =  67) and
+                    (character'pos('D') =  68) and
+                    (character'pos('E') =  69) and
+                    (character'pos('F') =  70) and
+                    (character'pos('G') =  71) and
+                    (character'pos('H') =  72) and
+                    (character'pos('I') =  73) and
+                    (character'pos('J') =  74) and
+                    (character'pos('K') =  75) and
+                    (character'pos('L') =  76) and
+                    (character'pos('M') =  77) and
+                    (character'pos('N') =  78) and
+                    (character'pos('O') =  79) and
+                    (character'pos('P') =  80) and
+                    (character'pos('Q') =  81) and
+                    (character'pos('R') =  82) and
+                    (character'pos('S') =  83) and
+                    (character'pos('T') =  84) and
+                    (character'pos('U') =  85) and
+                    (character'pos('V') =  86) and
+                    (character'pos('W') =  87) and
+                    (character'pos('X') =  88) and
+                    (character'pos('Y') =  89) and
+                    (character'pos('Z') =  90) and
+                    (character'pos('[') =  91) and
+                    (character'pos('\') =  92) and
+                    (character'pos(']') =  93) and
+                    (character'pos('^') =  94) and
+                    (character'pos('_') =  95) and
+                    (character'pos('`') =  96) and
+                    (character'pos('a') =  97) and
+                    (character'pos('b') =  98) and
+                    (character'pos('c') =  99) and
+                    (character'pos('d') = 100) and
+                    (character'pos('e') = 101) and
+                    (character'pos('f') = 102) and
+                    (character'pos('g') = 103) and
+                    (character'pos('h') = 104) and
+                    (character'pos('i') = 105) and
+                    (character'pos('j') = 106) and
+                    (character'pos('k') = 107) and
+                    (character'pos('l') = 108) and
+                    (character'pos('m') = 109) and
+                    (character'pos('n') = 110) and
+                    (character'pos('o') = 111) and
+                    (character'pos('p') = 112) and
+                    (character'pos('q') = 113) and
+                    (character'pos('r') = 114) and
+                    (character'pos('s') = 115) and
+                    (character'pos('t') = 116) and
+                    (character'pos('u') = 117) and
+                    (character'pos('v') = 118) and
+                    (character'pos('w') = 119) and
+          (character'pos('x') = 120) and
+                    (character'pos('y') = 121) and
+                    (character'pos('z') = 122) and
+                    (character'pos('{') = 123) and
+                    (character'pos('|') = 124) and
+                    (character'pos('}') = 125) and
+                    (character'pos('~') = 126) and
+                    (character'pos(DEL) = 127) and
+                    (character'pos(character'right) = 255) and  
+                    (bit'pos('0') = 0) and
+                    (bit'pos('1') = 1) and
+                    (bit'pos(bit'right) = 1) and
+                    (boolean'pos(false) = 0) and
+                    (boolean'pos(true)  = 1) and
+                    (boolean'pos(boolean'right) = 1) and
+                    (severity_level'pos(NOTE)    = 0) and
+                    (severity_level'pos(WARNING) = 1) and
+                    (severity_level'pos(ERROR)   = 2) and
+                    (severity_level'pos(FAILURE) = 3) and
+                    (severity_level'pos(severity_level'right)
+= 3))
+      report "***FAILED TEST: c03s01b01x00p06n02i00217 - The predefined order relations between enumeration values follow the order of corresponding position number."
+      severity ERROR;
+   wait;
+   END PROCESS TESTING;
+
+END c03s01b01x00p06n02i00217arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2172.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2172.vhd
new file mode 100644
index 0000000..d922d46
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2172.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2172.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02172ent IS
+END c07s02b05x00p01n01i02172ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02172arch OF c07s02b05x00p01n01i02172ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x1: integer := + 10;
+  BEGIN
+    assert NOT(x1=10) 
+      report "***PASSED TEST: c07s02b05x00p01n01i02172" 
+      severity NOTE;
+    assert (x1=10) 
+      report "***FAILED TEST: c07s02b05x00p01n01i02172 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02172arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2173.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2173.vhd
new file mode 100644
index 0000000..8f91207
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2173.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2173.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02173ent IS
+END c07s02b05x00p01n01i02173ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02173arch OF c07s02b05x00p01n01i02173ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x1: integer := - 10;
+  BEGIN
+    assert NOT(x1=-10) 
+      report "***PASSED TEST: c07s02b05x00p01n01i02173" 
+      severity NOTE;
+    assert (x1=-10) 
+      report "***FAILED TEST: c07s02b05x00p01n01i02173 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02173arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2174.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2174.vhd
new file mode 100644
index 0000000..3af500a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2174.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2174.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02174ent IS
+END c07s02b05x00p01n01i02174ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02174arch OF c07s02b05x00p01n01i02174ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x1: real := - 10.0;
+  BEGIN
+    assert NOT(x1=-10.0) 
+      report "***PASSED TEST: c07s02b05x00p01n01i02174" 
+      severity NOTE;
+    assert (x1=-10.0) 
+      report "***FAILED TEST: c07s02b05x00p01n01i02174 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02174arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2175.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2175.vhd
new file mode 100644
index 0000000..93f27a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2175.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2175.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02175ent IS
+END c07s02b05x00p01n01i02175ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02175arch OF c07s02b05x00p01n01i02175ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x1: real := + 10.0;
+  BEGIN
+    assert NOT(x1=+10.0) 
+      report "***PASSED TEST: c07s02b05x00p01n01i02175" 
+      severity NOTE;
+    assert (x1=+10.0) 
+      report "***FAILED TEST: c07s02b05x00p01n01i02175 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02175arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2176.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2176.vhd
new file mode 100644
index 0000000..c0d8655
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2176.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2176.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02176ent IS
+END c07s02b05x00p01n01i02176ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02176arch OF c07s02b05x00p01n01i02176ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type phys is range -10 to 100
+      units
+        p1;
+        p2 = 10 p1;
+        p3 = 5  p2;
+      end units;
+    constant a : phys := - p2;
+  BEGIN
+    assert NOT(a = - 10 p1)
+      report "***PASSED TEST: c07s02b05x00p01n01i02176" 
+      severity NOTE;
+    assert (a = - 10 p1)
+      report "***FAILED TEST: c07s02b05x00p01n01i02176 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02176arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2177.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2177.vhd
new file mode 100644
index 0000000..2d15aba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2177.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2177.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02177ent IS
+END c07s02b05x00p01n01i02177ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02177arch OF c07s02b05x00p01n01i02177ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type phys is range -10 to 100
+      units
+        p1;
+        p2 = 10 p1;
+        p3 = 5  p2;
+      end units;
+    constant a : phys := + p2;
+  BEGIN
+    assert NOT(a =  10 p1)
+      report "***PASSED TEST: c07s02b05x00p01n01i02177"
+      severity NOTE;
+    assert (a =  10 p1)
+      report "***FAILED TEST: c07s02b05x00p01n01i02177 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02177arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2178.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2178.vhd
new file mode 100644
index 0000000..6886309
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2178.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2178.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02178ent IS
+END c07s02b05x00p01n02i02178ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02178arch OF c07s02b05x00p01n02i02178ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 5;
+  BEGIN
+    k := + m;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02178"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02178 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02178arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2179.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2179.vhd
new file mode 100644
index 0000000..f4a00fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2179.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2179.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02179ent IS
+END c07s02b05x00p01n02i02179ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02179arch OF c07s02b05x00p01n02i02179ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 5;
+  BEGIN
+    k := - m;
+    assert NOT( k = - 5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02179"
+      severity NOTE;
+    assert ( k = - 5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02179 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02179arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc218.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc218.vhd
new file mode 100644
index 0000000..aa88f2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc218.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc218.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p06n03i00218ent IS
+END c03s01b01x00p06n03i00218ent;
+
+ARCHITECTURE c03s01b01x00p06n03i00218arch OF c03s01b01x00p06n03i00218ent IS
+  subtype BTRUE is BOOLEAN range TRUE to TRUE;
+  type ENUM1 is (ZERO, ONE, TWO, THREE);
+  type ENUM2 is (TRUE, FALSE);
+  type ENUM3 is ('1', '0');
+  type ENUM4 is ('Z', 'Y', 'X');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((ENUM1'POS(ZERO) = 0)
+               and (ENUM1'POS(ONE) = 1)
+               and (ENUM1'POS(TWO) = 2)
+               and (ENUM1'POS(THREE) = 3)
+               and (ENUM2'POS(TRUE) = 0)
+               and (ENUM2'POS(FALSE) = 1)
+               and (ENUM3'POS('1') = 0)
+               and (ENUM3'POS('0') = 1)
+               and (ENUM4'POS('Z') = 0)
+               and (ENUM4'POS('Y') = 1)
+               and (ENUM4'POS('X') = 2) )
+      report "***PASSED TEST: c03s01b01x00p06n03i00218"
+      severity NOTE;
+    assert ( (ENUM1'POS(ZERO) = 0)
+             and (ENUM1'POS(ONE) = 1)
+             and (ENUM1'POS(TWO) = 2)
+             and (ENUM1'POS(THREE) = 3)
+             and (ENUM2'POS(TRUE) = 0)
+             and (ENUM2'POS(FALSE) = 1)
+             and (ENUM3'POS('1') = 0)
+             and (ENUM3'POS('0') = 1)
+             and (ENUM4'POS('Z') = 0)
+             and (ENUM4'POS('Y') = 1)
+             and (ENUM4'POS('X') = 2))
+      report "***FAILED TEST: c03s01b01x00p06n03i00218 - The position value of the nth listed enumeration literal is n-1."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p06n03i00218arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2180.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2180.vhd
new file mode 100644
index 0000000..28f4ddf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2180.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2180.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02180ent IS
+END c07s02b05x00p01n02i02180ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02180arch OF c07s02b05x00p01n02i02180ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable m : integer := 5;
+  BEGIN
+    k := abs m;
+    assert NOT( k =  5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02180"
+      severity NOTE;
+    assert ( k =  5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02180 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02180arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2181.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2181.vhd
new file mode 100644
index 0000000..f55fb91
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2181.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2181.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02181ent IS
+END c07s02b05x00p01n02i02181ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02181arch OF c07s02b05x00p01n02i02181ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real := 0.0;
+    variable m : real := 5.5;
+  BEGIN
+    k := abs (-m);
+    assert NOT( k =  5.5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02181"
+      severity NOTE;
+    assert ( k =  5.5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02181 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02181arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2182.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2182.vhd
new file mode 100644
index 0000000..67349ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2182.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2182.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02182ent IS
+END c07s02b05x00p01n02i02182ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02182arch OF c07s02b05x00p01n02i02182ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real := 0.0;
+    variable m : real := 5.5;
+  BEGIN
+    k := - m;
+    assert NOT( k =  - 5.5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02182"
+      severity NOTE;
+    assert ( k =  - 5.5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02182 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02182arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2183.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2183.vhd
new file mode 100644
index 0000000..51150bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2183.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2183.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02183ent IS
+END c07s02b05x00p01n02i02183ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02183arch OF c07s02b05x00p01n02i02183ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real := 0.0;
+    variable m : real := 5.5;
+  BEGIN
+    k := + m;
+    assert NOT( k =  5.5 )
+      report "***PASSED TEST: c07s02b05x00p01n02i02183"
+      severity NOTE;
+    assert ( k =  5.5 )
+      report "***FAILED TEST: c07s02b05x00p01n02i02183 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02183arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2184.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2184.vhd
new file mode 100644
index 0000000..6157997
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2184.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2184.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02184ent IS
+END c07s02b05x00p01n02i02184ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02184arch OF c07s02b05x00p01n02i02184ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 0 to 1000
+      units
+        A;
+        B = 10 A;
+        C = 10 B;
+        D = 10 C;
+      end units;
+    variable k : PHYS := 1 A;
+    variable m : PHYS := 5 B;
+  BEGIN
+    k := + m;
+    assert NOT( k =  5 B )
+      report "***PASSED TEST: c07s02b05x00p01n02i02184"
+      severity NOTE;
+    assert ( k =  5 B )
+      report "***FAILED TEST: c07s02b05x00p01n02i02184 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02184arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2185.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2185.vhd
new file mode 100644
index 0000000..c3748ca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2185.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2185.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02185ent IS
+END c07s02b05x00p01n02i02185ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02185arch OF c07s02b05x00p01n02i02185ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range -1000 to 1000
+      units
+        A;
+        B = 10 A;
+        C = 10 B;
+        D = 10 C;
+      end units;
+    variable k : PHYS := 1 A;
+    variable m : PHYS := 5 B;
+  BEGIN
+    k := - m;
+    assert NOT( k = - 5 B )
+      report "***PASSED TEST: c07s02b05x00p01n02i02185"
+      severity NOTE;
+    assert ( k =  - 5 B )
+      report "***FAILED TEST: c07s02b05x00p01n02i02185 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02185arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2186.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2186.vhd
new file mode 100644
index 0000000..c6c1c2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2186.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2186.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n02i02186ent IS
+END c07s02b05x00p01n02i02186ent;
+
+ARCHITECTURE c07s02b05x00p01n02i02186arch OF c07s02b05x00p01n02i02186ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 0 to 1000
+      units
+        A;
+        B = 10 A;
+        C = 10 B;
+        D = 10 C;
+      end units;
+    variable k : PHYS := 1 A;
+    variable m : PHYS := 5 B;
+  BEGIN
+    k := abs m;
+    assert NOT( k = 5 B )
+      report "***PASSED TEST: c07s02b05x00p01n02i02186"
+      severity NOTE;
+    assert ( k = 5 B )
+      report "***FAILED TEST: c07s02b05x00p01n02i02186 - For each of these unary operators, the operand and the result have the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n02i02186arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2187.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2187.vhd
new file mode 100644
index 0000000..6e271ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2187.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2187.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02187ent IS
+END c07s02b05x00p01n01i02187ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02187arch OF c07s02b05x00p01n01i02187ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable INTV1   : INTEGER      := 0;
+    variable INTV2   : INTEGER      := 0;
+    variable TIMEV1  : TIME         := 1 ns;
+    variable TIMEV2  : TIME         := 1 ns;
+    variable REALV1  : REAL         := 0.0;
+    variable REALV2  : REAL         := 0.0;
+  BEGIN
+    -- Test negation of simple integers.
+    INTV1 := 14;
+    assert (-INTV1 = -14)
+      report "Negation of simple integers does not work.";
+    INTV2 := INTEGER'HIGH;
+    assert (-INTV2 = -INTEGER'HIGH)
+      report "Negation of simple integers does not work.";
+
+    -- Test identity of simple integers.
+    assert (+14 = 14)
+      report "Identity of simple integers does not work.";
+
+    -- Test negation of "TIME".
+    TIMEV1 := 1 ns;
+    assert (-TIMEV1 = -1 ns)
+      report "Negation of TIME values does not work.";
+    TIMEV2 := TIME'HIGH;
+    assert (-TIMEV2 = -TIME'HIGH)
+      report "Negation of TIME values does not work.";
+    
+    -- Test identify of "TIME".
+    assert (+14 ps = 14 ps)
+      report "Identity of TIME values does not work.";
+    
+    -- Test negation of simple floating point numbers.
+    REALV1 := 14.0;
+    assert (-REALV1 = -14.0)
+      report "Negation of simple integers does not work.";
+    REALV2 := REAL'HIGH;
+    assert (-REALV2 = -REAL'HIGH)
+      report "Negation of simple integers does not work.";
+    
+    -- Test identity of simple floating point numbers.
+    assert (+14.0 = 14.0)
+      report "Identity of simple integers does not work.";
+    wait for 5 fs;
+    assert NOT(   (-INTV1 = -14)         and
+                  (-INTV2 = -INTEGER'HIGH)   and
+                  (+14 = 14)         and
+                  (-TIMEV1 = -1 ns)      and
+                  (-TIMEV2 = -TIME'HIGH)      and
+                  (+14 ps = 14 ps)      and
+                  (-REALV1 = -14.0)      and
+                  (-REALV2 = -REAL'HIGH)      and
+                  (+14.0 = 14.0)         )
+      report "***PASSED TEST: c07s02b05x00p01n01i02187" 
+      severity NOTE;
+    assert (   (-INTV1 = -14)         and
+               (-INTV2 = -INTEGER'HIGH)   and
+               (+14 = 14)         and
+               (-TIMEV1 = -1 ns)      and
+               (-TIMEV2 = -TIME'HIGH)      and
+               (+14 ps = 14 ps)      and
+               (-REALV1 = -14.0)      and
+               (-REALV2 = -REAL'HIGH)      and
+               (+14.0 = 14.0)         )
+      report "***FAILED TEST: c07s02b05x00p01n01i02187 - Identity and nefation function did not work correctly for all numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02187arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc219.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc219.vhd
new file mode 100644
index 0000000..0eb52bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc219.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc219.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p06n03i00219ent IS
+  type e is (EMIN,ETYP,EMAX);
+END c03s01b01x00p06n03i00219ent;
+
+ARCHITECTURE c03s01b01x00p06n03i00219arch OF c03s01b01x00p06n03i00219ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable e1:integer;
+  BEGIN
+    e1 := e'pos(EMIN);
+    assert NOT(e1=0)
+      report "***PASSED TEST: c03s01b01x00p06n03i00219"
+      severity NOTE;
+    assert (e1=0)
+      report "***FAILED TEST: c03s01b01x00p06n03i00219 - The position number of the value of the first listed enumeration literal is zero."  
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p06n03i00219arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2199.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2199.vhd
new file mode 100644
index 0000000..4672d83
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2199.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2199.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02199ent IS
+END c07s02b06x00p01n01i02199ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02199arch OF c07s02b06x00p01n01i02199ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable y : real := -9.0 * (-3.0); -- y should be 27.0
+  BEGIN
+    assert NOT(y=27.0)
+      report "***PASSED TEST: c07s02b06x00p01n01i02199"
+      severity NOTE;
+    assert ( y=27.0 )
+      report "***FAILED TEST: c07s02b06x00p01n01i02199 - The  operators * and / are predefined for any integer type and any floating point type and have their convertional meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02199arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc220.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc220.vhd
new file mode 100644
index 0000000..2a8bbc4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc220.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc220.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p06n03i00220ent IS
+  type e is (EMIN,ETYP,EMAX);
+END c03s01b01x00p06n03i00220ent;
+
+ARCHITECTURE c03s01b01x00p06n03i00220arch OF c03s01b01x00p06n03i00220ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(e'pos(ETYP) < e'pos(EMAX))
+      report "***PASSED TEST: c03s01b01x00p06n03i00220"
+      severity NOTE;
+    assert (e'pos(ETYP) < e'pos(EMAX))
+      report "***FAILED TEST: c03s01b01x00p06n03i00220 - The position number of the value of each additional enumeration literal is one more than that of its predecessor in the list." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p06n03i00220arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2200.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2200.vhd
new file mode 100644
index 0000000..7aa992c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2200.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2200.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02200ent IS
+END c07s02b06x00p01n01i02200ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02200arch OF c07s02b06x00p01n01i02200ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable z : real := -0.01 / (1.0); -- z should be -0.01
+  BEGIN
+    assert NOT(z=-0.01)
+      report "***PASSED TEST: c07s02b06x00p01n01i02200"
+      severity NOTE;
+    assert ( z=-0.01 )
+      report "***FAILED TEST: c07s02b06x00p01n01i02200 - The  operators * and / are predefined for any integer type and any floating point type and have their convertional meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02200arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2203.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2203.vhd
new file mode 100644
index 0000000..2d1b8f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2203.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2203.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02203ent IS
+END c07s02b06x00p01n01i02203ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02203arch OF c07s02b06x00p01n01i02203ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant a : integer := 10 * 12;    -- a should be 120
+  BEGIN
+    assert NOT(a = 120) 
+      report "***PASSED TEST: c07s02b06x00p01n01i02203" 
+      severity NOTE;
+    assert (a = 120) 
+      report "***FAILED TEST: c07s02b06x00p01n01i02203 - Multiplying operators are predefined only for integer and floating point types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02203arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2204.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2204.vhd
new file mode 100644
index 0000000..f9e3f09
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2204.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2204.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02204ent IS
+END c07s02b06x00p01n01i02204ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02204arch OF c07s02b06x00p01n01i02204ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant a : integer := 10 / 2;   
+  BEGIN
+    assert NOT(a = 5) 
+      report "***PASSED TEST: c07s02b06x00p01n01i02204" 
+      severity NOTE;
+    assert (a = 5) 
+      report "***FAILED TEST: c07s02b06x00p01n01i02204 - Multiplying operators are predefined only for integer and floating point types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02204arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2205.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2205.vhd
new file mode 100644
index 0000000..841b6c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2205.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2205.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02205ent IS
+END c07s02b06x00p01n01i02205ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02205arch OF c07s02b06x00p01n01i02205ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant a : real := 10.0 * 2.0;   
+  BEGIN
+    assert NOT(a = 20.0) 
+      report "***PASSED TEST: c07s02b06x00p01n01i02205" 
+      severity NOTE;
+    assert (a = 20.0) 
+      report "***FAILED TEST: c07s02b06x00p01n01i02205 - Multiplying operators are predefined only for integer and floating point types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02205arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2206.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2206.vhd
new file mode 100644
index 0000000..0b07dd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2206.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2206.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02206ent IS
+END c07s02b06x00p01n01i02206ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02206arch OF c07s02b06x00p01n01i02206ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant a : real := 10.0 / 2.0;   
+  BEGIN
+    assert NOT(a = 5.0) 
+      report "***PASSED TEST: c07s02b06x00p01n01i02206" 
+      severity NOTE;
+    assert (a = 5.0) 
+      report "***FAILED TEST: c07s02b06x00p01n01i02206 - Multiplying operators are predefined only for integer and floating point types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02206arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2208.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2208.vhd
new file mode 100644
index 0000000..6977af0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2208.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2208.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02208ent IS
+END c07s02b06x00p01n01i02208ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02208arch OF c07s02b06x00p01n01i02208ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x : integer := 15;
+    constant y : integer := 9;
+    variable z : integer;
+  BEGIN
+    z := x mod y;  -- No_failure_here
+    assert NOT(z=6) 
+      report "***PASSED TEST: c07s02b06x00p01n01i02208" 
+      severity NOTE;
+    assert (z=6) 
+      report "***FAILED TEST: c07s02b06x00p01n01i02208 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02208arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2257.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2257.vhd
new file mode 100644
index 0000000..edd65cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2257.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2257.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p05n01i02257ent IS
+END c07s02b06x00p05n01i02257ent;
+
+ARCHITECTURE c07s02b06x00p05n01i02257arch OF c07s02b06x00p05n01i02257ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant div11 : integer := (1 - 4) / (1 - 4);
+    constant div12 : integer := (1 - 4) / (2 - 4);
+    constant div13 : integer := (1 - 4) / (3 - 4);
+    constant div15 : integer := (1 - 4) / (5 - 4);
+    constant div16 : integer := (1 - 4) / (6 - 4);
+    constant div17 : integer := (1 - 4) / (7 - 4);
+    constant div18 : integer := (1 - 4) / (8 - 4);
+    constant div19 : integer := (1 - 4) / (9 - 4);
+    constant div41 : integer := (4 - 4) / (1 - 4);
+    constant div42 : integer := (4 - 4) / (2 - 4);
+    constant div43 : integer := (4 - 4) / (3 - 4);
+    constant div45 : integer := (4 - 4) / (5 - 4);
+    constant div46 : integer := (4 - 4) / (6 - 4);
+    constant div47 : integer := (4 - 4) / (7 - 4);
+    constant div48 : integer := (4 - 4) / (8 - 4);
+    constant div49 : integer := (4 - 4) / (9 - 4);
+    constant div61 : integer := (6 - 4) / (1 - 4);
+    constant div62 : integer := (6 - 4) / (2 - 4);
+    constant div63 : integer := (6 - 4) / (3 - 4);
+    constant div65 : integer := (6 - 4) / (5 - 4);
+    constant div66 : integer := (6 - 4) / (6 - 4);
+    constant div67 : integer := (6 - 4) / (7 - 4);
+    constant div68 : integer := (6 - 4) / (8 - 4);
+    constant div69 : integer := (6 - 4) / (9 - 4);
+
+    variable four : integer := 4;
+
+  BEGIN
+
+    assert div11 = (1 - four) / (1 - four);
+    assert div12 = (1 - four) / (2 - four);
+    assert div13 = (1 - four) / (3 - four);
+    assert div15 = (1 - four) / (5 - four);
+    assert div16 = (1 - four) / (6 - four);
+    assert div17 = (1 - four) / (7 - four);
+    assert div18 = (1 - four) / (8 - four);
+    assert div19 = (1 - four) / (9 - four);
+    assert div41 = (4 - four) / (1 - four);
+    assert div42 = (4 - four) / (2 - four);
+    assert div43 = (4 - four) / (3 - four);
+    assert div45 = (4 - four) / (5 - four);
+    assert div46 = (4 - four) / (6 - four);
+    assert div47 = (4 - four) / (7 - four);
+    assert div48 = (4 - four) / (8 - four);
+    assert div49 = (4 - four) / (9 - four);
+    assert div61 = (6 - four) / (1 - four);
+    assert div62 = (6 - four) / (2 - four);
+    assert div63 = (6 - four) / (3 - four);
+    assert div65 = (6 - four) / (5 - four);
+    assert div66 = (6 - four) / (6 - four);
+    assert div67 = (6 - four) / (7 - four);
+    assert div68 = (6 - four) / (8 - four);
+    assert div69 = (6 - four) / (9 - four);
+
+    assert NOT((div11 = (1 - four) / (1 - four))   and
+               ( div12 = (1 - four) / (2 - four))   and
+               ( div13 = (1 - four) / (3 - four))   and
+               ( div15 = (1 - four) / (5 - four))   and
+               ( div16 = (1 - four) / (6 - four))   and
+               ( div17 = (1 - four) / (7 - four))   and
+               ( div18 = (1 - four) / (8 - four))   and
+               ( div19 = (1 - four) / (9 - four))   and
+               ( div41 = (4 - four) / (1 - four))   and
+               ( div42 = (4 - four) / (2 - four))   and
+               ( div43 = (4 - four) / (3 - four))   and
+               ( div45 = (4 - four) / (5 - four))   and
+               ( div46 = (4 - four) / (6 - four))   and
+               ( div47 = (4 - four) / (7 - four))   and
+               ( div48 = (4 - four) / (8 - four))   and
+               ( div49 = (4 - four) / (9 - four))   and
+               ( div61 = (6 - four) / (1 - four))   and
+               ( div62 = (6 - four) / (2 - four))   and
+               ( div63 = (6 - four) / (3 - four))   and
+               ( div65 = (6 - four) / (5 - four))   and
+               ( div66 = (6 - four) / (6 - four))   and
+               ( div67 = (6 - four) / (7 - four))   and
+               ( div68 = (6 - four) / (8 - four))   and
+               ( div69 = (6 - four) / (9 - four))   )
+      report "***PASSED TEST: c07s02b06x00p05n01i02257"
+      severity NOTE;
+    assert (( div11 = (1 - four) / (1 - four))   and
+            ( div12 = (1 - four) / (2 - four))   and
+            ( div13 = (1 - four) / (3 - four))   and
+            ( div15 = (1 - four) / (5 - four))   and
+            ( div16 = (1 - four) / (6 - four))   and
+            ( div17 = (1 - four) / (7 - four))   and
+            ( div18 = (1 - four) / (8 - four))   and
+            ( div19 = (1 - four) / (9 - four))   and
+            ( div41 = (4 - four) / (1 - four))   and
+            ( div42 = (4 - four) / (2 - four))   and
+            ( div43 = (4 - four) / (3 - four))   and
+            ( div45 = (4 - four) / (5 - four))   and
+            ( div46 = (4 - four) / (6 - four))   and
+            ( div47 = (4 - four) / (7 - four))   and
+            ( div48 = (4 - four) / (8 - four))   and
+            ( div49 = (4 - four) / (9 - four))   and
+            ( div61 = (6 - four) / (1 - four))   and
+            ( div62 = (6 - four) / (2 - four))   and
+            ( div63 = (6 - four) / (3 - four))   and
+            ( div65 = (6 - four) / (5 - four))   and
+            ( div66 = (6 - four) / (6 - four))   and
+            ( div67 = (6 - four) / (7 - four))   and
+            ( div68 = (6 - four) / (8 - four))   and
+            ( div69 = (6 - four) / (9 - four))   )
+      report "***FAILED TEST: c07s02b06x00p05n01i02257 - Constant integer type division test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p05n01i02257arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2258.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2258.vhd
new file mode 100644
index 0000000..c111322
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2258.vhd
@@ -0,0 +1,159 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2258.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p05n01i02258ent IS
+END c07s02b06x00p05n01i02258ent;
+
+ARCHITECTURE c07s02b06x00p05n01i02258arch OF c07s02b06x00p05n01i02258ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant mul11 : integer := (1 - 4) * (1 - 4);
+    constant mul12 : integer := (1 - 4) * (2 - 4);
+    constant mul13 : integer := (1 - 4) * (3 - 4);
+    constant mul14 : integer := (1 - 4) * (4 - 4);
+    constant mul15 : integer := (1 - 4) * (5 - 4);
+    constant mul16 : integer := (1 - 4) * (6 - 4);
+    constant mul17 : integer := (1 - 4) * (7 - 4);
+    constant mul18 : integer := (1 - 4) * (8 - 4);
+    constant mul19 : integer := (1 - 4) * (9 - 4);
+    constant mul41 : integer := (4 - 4) * (1 - 4);
+    constant mul42 : integer := (4 - 4) * (2 - 4);
+    constant mul43 : integer := (4 - 4) * (3 - 4);
+    constant mul44 : integer := (4 - 4) * (4 - 4);
+    constant mul45 : integer := (4 - 4) * (5 - 4);
+    constant mul46 : integer := (4 - 4) * (6 - 4);
+    constant mul47 : integer := (4 - 4) * (7 - 4);
+    constant mul48 : integer := (4 - 4) * (8 - 4);
+    constant mul49 : integer := (4 - 4) * (9 - 4);
+    constant mul61 : integer := (6 - 4) * (1 - 4);
+    constant mul62 : integer := (6 - 4) * (2 - 4);
+    constant mul63 : integer := (6 - 4) * (3 - 4);
+    constant mul64 : integer := (6 - 4) * (4 - 4);
+    constant mul65 : integer := (6 - 4) * (5 - 4);
+    constant mul66 : integer := (6 - 4) * (6 - 4);
+    constant mul67 : integer := (6 - 4) * (7 - 4);
+    constant mul68 : integer := (6 - 4) * (8 - 4);
+    constant mul69 : integer := (6 - 4) * (9 - 4);
+
+    variable four : integer := 4;
+
+  BEGIN
+
+    assert mul11 = (1 - four) * (1 - four);
+    assert mul12 = (1 - four) * (2 - four);
+    assert mul13 = (1 - four) * (3 - four);
+    assert mul14 = (1 - four) * (4 - four);
+    assert mul15 = (1 - four) * (5 - four);
+    assert mul16 = (1 - four) * (6 - four);
+    assert mul17 = (1 - four) * (7 - four);
+    assert mul18 = (1 - four) * (8 - four);
+    assert mul19 = (1 - four) * (9 - four);
+    assert mul41 = (4 - four) * (1 - four);
+    assert mul42 = (4 - four) * (2 - four);
+    assert mul43 = (4 - four) * (3 - four);
+    assert mul44 = (4 - four) * (4 - four);
+    assert mul45 = (4 - four) * (5 - four);
+    assert mul46 = (4 - four) * (6 - four);
+    assert mul47 = (4 - four) * (7 - four);
+    assert mul48 = (4 - four) * (8 - four);
+    assert mul49 = (4 - four) * (9 - four);
+    assert mul61 = (6 - four) * (1 - four);
+    assert mul62 = (6 - four) * (2 - four);
+    assert mul63 = (6 - four) * (3 - four);
+    assert mul64 = (6 - four) * (4 - four);
+    assert mul65 = (6 - four) * (5 - four);
+    assert mul66 = (6 - four) * (6 - four);
+    assert mul67 = (6 - four) * (7 - four);
+    assert mul68 = (6 - four) * (8 - four);
+    assert mul69 = (6 - four) * (9 - four);
+
+    assert NOT(( mul11 = (1 - four) * (1 - four))   and
+               ( mul12 = (1 - four) * (2 - four))   and
+               ( mul13 = (1 - four) * (3 - four))   and
+               ( mul14 = (1 - four) * (4 - four))   and
+               ( mul15 = (1 - four) * (5 - four))   and
+               ( mul16 = (1 - four) * (6 - four))   and
+               ( mul17 = (1 - four) * (7 - four))   and
+               ( mul18 = (1 - four) * (8 - four))   and
+               ( mul19 = (1 - four) * (9 - four))   and
+               ( mul41 = (4 - four) * (1 - four))   and
+               ( mul42 = (4 - four) * (2 - four))   and
+               ( mul43 = (4 - four) * (3 - four))   and
+               ( mul44 = (4 - four) * (4 - four))   and
+               ( mul45 = (4 - four) * (5 - four))   and
+               ( mul46 = (4 - four) * (6 - four))   and
+               ( mul47 = (4 - four) * (7 - four))   and
+               ( mul48 = (4 - four) * (8 - four))   and
+               ( mul49 = (4 - four) * (9 - four))   and
+               ( mul61 = (6 - four) * (1 - four))   and
+               ( mul62 = (6 - four) * (2 - four))   and
+               ( mul63 = (6 - four) * (3 - four))   and
+               ( mul64 = (6 - four) * (4 - four))   and
+               ( mul65 = (6 - four) * (5 - four))   and
+               ( mul66 = (6 - four) * (6 - four))   and
+               ( mul67 = (6 - four) * (7 - four))   and
+               ( mul68 = (6 - four) * (8 - four))   and
+               ( mul69 = (6 - four) * (9 - four))   )
+      report "***PASSED TEST: c07s02b06x00p05n01i02258"
+      severity NOTE;
+    assert (( mul11 = (1 - four) * (1 - four))   and
+            ( mul12 = (1 - four) * (2 - four))   and
+            ( mul13 = (1 - four) * (3 - four))   and
+            ( mul14 = (1 - four) * (4 - four))   and
+            ( mul15 = (1 - four) * (5 - four))   and
+            ( mul16 = (1 - four) * (6 - four))   and
+            ( mul17 = (1 - four) * (7 - four))   and
+            ( mul18 = (1 - four) * (8 - four))   and
+            ( mul19 = (1 - four) * (9 - four))   and
+            ( mul41 = (4 - four) * (1 - four))   and
+            ( mul42 = (4 - four) * (2 - four))   and
+            ( mul43 = (4 - four) * (3 - four))   and
+            ( mul44 = (4 - four) * (4 - four))   and
+            ( mul45 = (4 - four) * (5 - four))   and
+            ( mul46 = (4 - four) * (6 - four))   and
+            ( mul47 = (4 - four) * (7 - four))   and
+            ( mul48 = (4 - four) * (8 - four))   and
+            ( mul49 = (4 - four) * (9 - four))   and
+            ( mul61 = (6 - four) * (1 - four))   and
+            ( mul62 = (6 - four) * (2 - four))   and
+            ( mul63 = (6 - four) * (3 - four))   and
+            ( mul64 = (6 - four) * (4 - four))   and
+            ( mul65 = (6 - four) * (5 - four))   and
+            ( mul66 = (6 - four) * (6 - four))   and
+            ( mul67 = (6 - four) * (7 - four))   and
+            ( mul68 = (6 - four) * (8 - four))   and
+            ( mul69 = (6 - four) * (9 - four))   )
+      report "***FAILED TEST: c07s02b06x00p05n01i02258 - Constant integer type multiplication test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p05n01i02258arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2259.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2259.vhd
new file mode 100644
index 0000000..cd8fcce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2259.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2259.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p05n01i02259ent IS
+END c07s02b06x00p05n01i02259ent;
+
+ARCHITECTURE c07s02b06x00p05n01i02259arch OF c07s02b06x00p05n01i02259ent IS
+BEGIN
+  TESTING: PROCESS
+    constant mod11 : integer := (1 - 4) mod (1 - 4);
+    constant mod12 : integer := (1 - 4) mod (2 - 4);
+    constant mod13 : integer := (1 - 4) mod (3 - 4);
+    constant mod15 : integer := (1 - 4) mod (5 - 4);
+    constant mod16 : integer := (1 - 4) mod (6 - 4);
+    constant mod17 : integer := (1 - 4) mod (7 - 4);
+    constant mod18 : integer := (1 - 4) mod (8 - 4);
+    constant mod19 : integer := (1 - 4) mod (9 - 4);
+    constant mod41 : integer := (4 - 4) mod (1 - 4);
+    constant mod42 : integer := (4 - 4) mod (2 - 4);
+    constant mod43 : integer := (4 - 4) mod (3 - 4);
+    constant mod45 : integer := (4 - 4) mod (5 - 4);
+    constant mod46 : integer := (4 - 4) mod (6 - 4);
+    constant mod47 : integer := (4 - 4) mod (7 - 4);
+    constant mod48 : integer := (4 - 4) mod (8 - 4);
+    constant mod49 : integer := (4 - 4) mod (9 - 4);
+    constant mod61 : integer := (6 - 4) mod (1 - 4);
+    constant mod62 : integer := (6 - 4) mod (2 - 4);
+    constant mod63 : integer := (6 - 4) mod (3 - 4);
+    constant mod65 : integer := (6 - 4) mod (5 - 4);
+    constant mod66 : integer := (6 - 4) mod (6 - 4);
+    constant mod67 : integer := (6 - 4) mod (7 - 4);
+    constant mod68 : integer := (6 - 4) mod (8 - 4);
+    constant mod69 : integer := (6 - 4) mod (9 - 4);
+
+    variable four : integer := 4;
+
+  BEGIN
+    assert mod11 = (1 - four) mod (1 - four);
+    assert mod12 = (1 - four) mod (2 - four);
+    assert mod13 = (1 - four) mod (3 - four);
+    assert mod15 = (1 - four) mod (5 - four);
+    assert mod16 = (1 - four) mod (6 - four);
+    assert mod17 = (1 - four) mod (7 - four);
+    assert mod18 = (1 - four) mod (8 - four);
+    assert mod19 = (1 - four) mod (9 - four);
+    assert mod41 = (4 - four) mod (1 - four);
+    assert mod42 = (4 - four) mod (2 - four);
+    assert mod43 = (4 - four) mod (3 - four);
+    assert mod45 = (4 - four) mod (5 - four);
+    assert mod46 = (4 - four) mod (6 - four);
+    assert mod47 = (4 - four) mod (7 - four);
+    assert mod48 = (4 - four) mod (8 - four);
+    assert mod49 = (4 - four) mod (9 - four);
+    assert mod61 = (6 - four) mod (1 - four);
+    assert mod62 = (6 - four) mod (2 - four);
+    assert mod63 = (6 - four) mod (3 - four);
+    assert mod65 = (6 - four) mod (5 - four);
+    assert mod66 = (6 - four) mod (6 - four);
+    assert mod67 = (6 - four) mod (7 - four);
+    assert mod68 = (6 - four) mod (8 - four);
+    assert mod69 = (6 - four) mod (9 - four);
+
+    assert NOT((mod11 = (1 - four) mod (1 - four))   and
+               ( mod12 = (1 - four) mod (2 - four))   and
+               ( mod13 = (1 - four) mod (3 - four))   and
+               ( mod15 = (1 - four) mod (5 - four))   and
+               ( mod16 = (1 - four) mod (6 - four))   and
+               ( mod17 = (1 - four) mod (7 - four))   and
+               ( mod18 = (1 - four) mod (8 - four))   and
+               ( mod19 = (1 - four) mod (9 - four))   and
+               ( mod41 = (4 - four) mod (1 - four))   and
+               ( mod42 = (4 - four) mod (2 - four))   and
+               ( mod43 = (4 - four) mod (3 - four))   and
+               ( mod45 = (4 - four) mod (5 - four))   and
+               ( mod46 = (4 - four) mod (6 - four))   and
+               ( mod47 = (4 - four) mod (7 - four))   and
+               ( mod48 = (4 - four) mod (8 - four))   and
+               ( mod49 = (4 - four) mod (9 - four))   and
+               ( mod61 = (6 - four) mod (1 - four))   and
+               ( mod62 = (6 - four) mod (2 - four))   and
+               ( mod63 = (6 - four) mod (3 - four))   and
+               ( mod65 = (6 - four) mod (5 - four))   and
+               ( mod66 = (6 - four) mod (6 - four))   and
+               ( mod67 = (6 - four) mod (7 - four))   and
+               ( mod68 = (6 - four) mod (8 - four))   and
+               ( mod69 = (6 - four) mod (9 - four))   )
+      report "***PASSED TEST: c07s02b06x00p05n01i02259"
+      severity NOTE;
+    assert (( mod11 = (1 - four) mod (1 - four))   and
+            ( mod12 = (1 - four) mod (2 - four))   and
+            ( mod13 = (1 - four) mod (3 - four))   and
+            ( mod15 = (1 - four) mod (5 - four))   and
+            ( mod16 = (1 - four) mod (6 - four))   and
+            ( mod17 = (1 - four) mod (7 - four))   and
+            ( mod18 = (1 - four) mod (8 - four))   and
+            ( mod19 = (1 - four) mod (9 - four))   and
+            ( mod41 = (4 - four) mod (1 - four))   and
+            ( mod42 = (4 - four) mod (2 - four))   and
+            ( mod43 = (4 - four) mod (3 - four))   and
+            ( mod45 = (4 - four) mod (5 - four))   and
+            ( mod46 = (4 - four) mod (6 - four))   and
+            ( mod47 = (4 - four) mod (7 - four))   and
+            ( mod48 = (4 - four) mod (8 - four))   and
+            ( mod49 = (4 - four) mod (9 - four))   and
+            ( mod61 = (6 - four) mod (1 - four))   and
+            ( mod62 = (6 - four) mod (2 - four))   and
+            ( mod63 = (6 - four) mod (3 - four))   and
+            ( mod65 = (6 - four) mod (5 - four))   and
+            ( mod66 = (6 - four) mod (6 - four))   and
+            ( mod67 = (6 - four) mod (7 - four))   and
+            ( mod68 = (6 - four) mod (8 - four))   and
+            ( mod69 = (6 - four) mod (9 - four))   )
+      report "***FAILED TEST: c07s02b06x00p05n01i02259 - Constant integer type mod test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p05n01i02259arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2260.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2260.vhd
new file mode 100644
index 0000000..166f289
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2260.vhd
@@ -0,0 +1,146 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2260.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p05n01i02260ent IS
+END c07s02b06x00p05n01i02260ent;
+
+ARCHITECTURE c07s02b06x00p05n01i02260arch OF c07s02b06x00p05n01i02260ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant rem11 : integer := (1 - 4) rem (1 - 4);
+    constant rem12 : integer := (1 - 4) rem (2 - 4);
+    constant rem13 : integer := (1 - 4) rem (3 - 4);
+    constant rem15 : integer := (1 - 4) rem (5 - 4);
+    constant rem16 : integer := (1 - 4) rem (6 - 4);
+    constant rem17 : integer := (1 - 4) rem (7 - 4);
+    constant rem18 : integer := (1 - 4) rem (8 - 4);
+    constant rem19 : integer := (1 - 4) rem (9 - 4);
+    constant rem41 : integer := (4 - 4) rem (1 - 4);
+    constant rem42 : integer := (4 - 4) rem (2 - 4);
+    constant rem43 : integer := (4 - 4) rem (3 - 4);
+    constant rem45 : integer := (4 - 4) rem (5 - 4);
+    constant rem46 : integer := (4 - 4) rem (6 - 4);
+    constant rem47 : integer := (4 - 4) rem (7 - 4);
+    constant rem48 : integer := (4 - 4) rem (8 - 4);
+    constant rem49 : integer := (4 - 4) rem (9 - 4);
+    constant rem61 : integer := (6 - 4) rem (1 - 4);
+    constant rem62 : integer := (6 - 4) rem (2 - 4);
+    constant rem63 : integer := (6 - 4) rem (3 - 4);
+    constant rem65 : integer := (6 - 4) rem (5 - 4);
+    constant rem66 : integer := (6 - 4) rem (6 - 4);
+    constant rem67 : integer := (6 - 4) rem (7 - 4);
+    constant rem68 : integer := (6 - 4) rem (8 - 4);
+    constant rem69 : integer := (6 - 4) rem (9 - 4);
+
+    variable four : integer := 4;
+
+  BEGIN
+    assert rem11 = (1 - four) rem (1 - four);
+    assert rem12 = (1 - four) rem (2 - four);
+    assert rem13 = (1 - four) rem (3 - four);
+    assert rem15 = (1 - four) rem (5 - four);
+    assert rem16 = (1 - four) rem (6 - four);
+    assert rem17 = (1 - four) rem (7 - four);
+    assert rem18 = (1 - four) rem (8 - four);
+    assert rem19 = (1 - four) rem (9 - four);
+    assert rem41 = (4 - four) rem (1 - four);
+    assert rem42 = (4 - four) rem (2 - four);
+    assert rem43 = (4 - four) rem (3 - four);
+    assert rem45 = (4 - four) rem (5 - four);
+    assert rem46 = (4 - four) rem (6 - four);
+    assert rem47 = (4 - four) rem (7 - four);
+    assert rem48 = (4 - four) rem (8 - four);
+    assert rem49 = (4 - four) rem (9 - four);
+    assert rem61 = (6 - four) rem (1 - four);
+    assert rem62 = (6 - four) rem (2 - four);
+    assert rem63 = (6 - four) rem (3 - four);
+    assert rem65 = (6 - four) rem (5 - four);
+    assert rem66 = (6 - four) rem (6 - four);
+    assert rem67 = (6 - four) rem (7 - four);
+    assert rem68 = (6 - four) rem (8 - four);
+    assert rem69 = (6 - four) rem (9 - four);
+
+    assert NOT((rem11 = (1 - four) rem (1 - four))   and
+               ( rem12 = (1 - four) rem (2 - four))   and
+               ( rem13 = (1 - four) rem (3 - four))   and
+               ( rem15 = (1 - four) rem (5 - four))   and
+               ( rem16 = (1 - four) rem (6 - four))   and
+               ( rem17 = (1 - four) rem (7 - four))   and
+               ( rem18 = (1 - four) rem (8 - four))   and
+               ( rem19 = (1 - four) rem (9 - four))   and
+               ( rem41 = (4 - four) rem (1 - four))   and
+               ( rem42 = (4 - four) rem (2 - four))   and
+               ( rem43 = (4 - four) rem (3 - four))   and
+               ( rem45 = (4 - four) rem (5 - four))   and
+               ( rem46 = (4 - four) rem (6 - four))   and
+               ( rem47 = (4 - four) rem (7 - four))   and
+               ( rem48 = (4 - four) rem (8 - four))   and
+               ( rem49 = (4 - four) rem (9 - four))   and
+               ( rem61 = (6 - four) rem (1 - four))   and
+               ( rem62 = (6 - four) rem (2 - four))   and
+               ( rem63 = (6 - four) rem (3 - four))   and
+               ( rem65 = (6 - four) rem (5 - four))   and
+               ( rem66 = (6 - four) rem (6 - four))   and
+               ( rem67 = (6 - four) rem (7 - four))   and
+               ( rem68 = (6 - four) rem (8 - four))   and
+               ( rem69 = (6 - four) rem (9 - four))   )
+      report "***PASSED TEST: c07s02b06x00p05n01i02260"
+      severity NOTE;
+    assert (( rem11 = (1 - four) rem (1 - four))   and
+            ( rem12 = (1 - four) rem (2 - four))   and
+            ( rem13 = (1 - four) rem (3 - four))   and
+            ( rem15 = (1 - four) rem (5 - four))   and
+            ( rem16 = (1 - four) rem (6 - four))   and
+            ( rem17 = (1 - four) rem (7 - four))   and
+            ( rem18 = (1 - four) rem (8 - four))   and
+            ( rem19 = (1 - four) rem (9 - four))   and
+            ( rem41 = (4 - four) rem (1 - four))   and
+            ( rem42 = (4 - four) rem (2 - four))   and
+            ( rem43 = (4 - four) rem (3 - four))   and
+            ( rem45 = (4 - four) rem (5 - four))   and
+            ( rem46 = (4 - four) rem (6 - four))   and
+            ( rem47 = (4 - four) rem (7 - four))   and
+            ( rem48 = (4 - four) rem (8 - four))   and
+            ( rem49 = (4 - four) rem (9 - four))   and
+            ( rem61 = (6 - four) rem (1 - four))   and
+            ( rem62 = (6 - four) rem (2 - four))   and
+            ( rem63 = (6 - four) rem (3 - four))   and
+            ( rem65 = (6 - four) rem (5 - four))   and
+            ( rem66 = (6 - four) rem (6 - four))   and
+            ( rem67 = (6 - four) rem (7 - four))   and
+            ( rem68 = (6 - four) rem (8 - four))   and
+            ( rem69 = (6 - four) rem (9 - four))   )
+      report "***FAILED TEST: c07s02b06x00p05n01i02260 - Constant integer type rem test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p05n01i02260arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2261.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2261.vhd
new file mode 100644
index 0000000..631bbf4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2261.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2261.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p05n01i02261ent IS
+END c07s02b06x00p05n01i02261ent;
+
+ARCHITECTURE c07s02b06x00p05n01i02261arch OF c07s02b06x00p05n01i02261ent IS
+  
+  constant s4p : real := 4.0;
+  constant s4n : real := (-4.0);
+  constant s5p : real := 5.0;
+  constant s5n : real := (-5.0);
+  
+BEGIN
+  TESTING: PROCESS
+    variable m1 : real :=   4.0  *   5.0 ;
+    variable m2 : real :=   4.0  * (-5.0);
+    variable m3 : real := (-4.0) *   5.0 ;
+    variable m4 : real := (-4.0) * (-5.0);
+    
+    variable d1 : real :=   4.0  /   5.0 ;
+    variable d2 : real :=   4.0  / (-5.0);
+    variable d3 : real := (-4.0) /   5.0 ;
+    variable d4 : real := (-4.0) / (-5.0);
+    
+    variable Em1 : real :=  s4p  *  s5p;
+    variable Em2 : real :=  s4p  *  s5n;
+    variable Em3 : real :=  s4n  *  s5p;
+    variable Em4 : real :=  s4n  *  s5n;
+    
+    variable Ed1 : real :=  s4p  /  s5p;
+    variable Ed2 : real :=  s4p  /  s5n;
+    variable Ed3 : real :=  s4n  /  s5p;
+    variable Ed4 : real :=  s4n  /  s5n;
+  BEGIN
+    assert m1 = Em1;
+    assert m2 = Em2;
+    assert m3 = Em3;
+    assert m4 = Em4;
+    
+    assert d1 = Ed1;
+    assert d2 = Ed2;
+    assert d3 = Ed3;
+    assert d4 = Ed4;
+
+    assert NOT((m1 = Em1)   and
+               ( m2 = Em2)   and
+               ( m3 = Em3)   and
+               ( m4 = Em4)   and
+               ( d1 = Ed1)   and
+               ( d2 = Ed2)   and
+               ( d3 = Ed3)   and
+               ( d4 = Ed4)   )
+      report "***PASSED TEST: c07s02b06x00p05n01i02261"
+      severity NOTE;
+    assert (( m1 = Em1)   and
+            ( m2 = Em2)   and
+            ( m3 = Em3)   and
+            ( m4 = Em4)   and
+            ( d1 = Ed1)   and
+            ( d2 = Ed2)   and
+            ( d3 = Ed3)   and
+            ( d4 = Ed4)   )
+      report "***FAILED TEST: c07s02b06x00p05n01i02261 - Constant real type multiplication and division test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p05n01i02261arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2262.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2262.vhd
new file mode 100644
index 0000000..d3074ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2262.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2262.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02262ent IS
+END c07s02b06x00p11n01i02262ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02262arch OF c07s02b06x00p11n01i02262ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := 10 rem (-3);
+    assert NOT(k=1)
+      report "***PASSED TEST: c07s02b06x00p11n01i02262"
+      severity NOTE;
+    assert ( k=1 )
+      report "***FAILED TEST: c07s02b06x00p11n01i02262 - Integer division and remainder are deined by the following relation : A = (A/B)*B + (A rem B)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02262arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2263.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2263.vhd
new file mode 100644
index 0000000..07cded6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2263.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2263.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02263ent IS
+END c07s02b06x00p11n01i02263ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02263arch OF c07s02b06x00p11n01i02263ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2,V3 : Integer ;
+    variable A : Integer := 10 ;
+    variable B : Integer := 5  ;
+  BEGIN
+    V1 := (-A)/B ;
+    V2 := -(A/B) ;
+    assert NOT(V1 = V2)
+      report "***PASSED TEST: c07s02b06x00p11n01i02263"
+      severity NOTE;
+    assert (V1 = V2)
+      report "***FAILED TEST: c07s02b06x00p11n01i02263 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02263arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2264.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2264.vhd
new file mode 100644
index 0000000..186aaa5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2264.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2264.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02264ent IS
+END c07s02b06x00p11n01i02264ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02264arch OF c07s02b06x00p11n01i02264ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2,V3 : Integer ;
+    variable A : Integer := 10 ;
+    variable B : Integer := 5  ;
+  BEGIN
+    V1 := (-A)/B ;
+    V2 := A/(-B) ;
+    assert NOT(V1 = V2)
+      report "***PASSED TEST: c07s02b06x00p11n01i02264"
+      severity NOTE;
+    assert (V1 = V2)
+      report "***FAILED TEST: c07s02b06x00p11n01i02264 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02264arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2265.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2265.vhd
new file mode 100644
index 0000000..176b09b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2265.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2265.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02265ent IS
+END c07s02b06x00p11n01i02265ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02265arch OF c07s02b06x00p11n01i02265ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1,V2,V3 : Integer ;
+    variable A : Integer := 10 ;
+    variable B : Integer := 5  ;
+  BEGIN
+    V1 := -(A/B) ;
+    V2 := A/(-B) ;
+    assert NOT(V1 = V2)
+      report "***PASSED TEST: c07s02b06x00p11n01i02265"
+      severity NOTE;
+    assert (V1 = V2)
+      report "***FAILED TEST: c07s02b06x00p11n01i02265 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02265arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2266.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2266.vhd
new file mode 100644
index 0000000..60c04e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2266.vhd
@@ -0,0 +1,118 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2266.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02266ent IS
+END c07s02b06x00p11n01i02266ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02266arch OF c07s02b06x00p11n01i02266ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable A, B    : INTEGER;
+    variable OKtest  : INTEGER   := 0;
+  BEGIN
+    -- Test integer division.
+    -- 1. Both positive.
+    for A in 0 to 20 loop
+      for B in 1 to 20 loop
+        if NOT(((-A)/B) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert (((-A)/B) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+        if NOT((A/(-B)) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert ((A/(-B)) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+      end loop;
+    end loop;
+
+    -- 2. A negative, B positive.
+    for A in -1 downto -20 loop
+      for B in 1 to 20 loop
+        if NOT(((-A)/B) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert (((-A)/B) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+        if NOT((A/(-B)) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert ((A/(-B)) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    -- 3. A positive, B negative.
+    for A in 0 to 20 loop
+      for B in -1 downto -20 loop
+        if NOT(((-A)/B) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert (((-A)/B) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+        if NOT((A/(-B)) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert ((A/(-B)) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    -- 4. Both negative.
+    for A in -1 downto -20 loop
+      for B in -1 downto -20 loop
+        if NOT(((-A)/B) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert (((-A)/B) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+        if NOT((A/(-B)) = -(A/B)) then
+          OKtest := 1;
+        end if;
+        assert ((A/(-B)) = -(A/B))
+          report "Integer Division operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    wait for 5 ns;
+
+    assert NOT(OKtest = 0)
+      report "***PASSED TEST: c07s02b06x00p11n01i02266"
+      severity NOTE;
+    assert (OKtest = 0)
+      report "***FAILED TEST: c07s02b06x00p11n01i02266 - Integer division should satisfy the following identity: (-A)/B = -(A/B) = A/(-B)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02266arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2267.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2267.vhd
new file mode 100644
index 0000000..eaea8bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2267.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2267.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p11n01i02267ent IS
+END c07s02b06x00p11n01i02267ent;
+
+ARCHITECTURE c07s02b06x00p11n01i02267arch OF c07s02b06x00p11n01i02267ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable A, B    : INTEGER;
+    variable OKtest  : INTEGER   := 0;
+  BEGIN
+    -- Test integer rem operations.
+    -- 1. Both positive.
+    for A in 1 to 20 loop
+      for B in 1 to 20 loop
+        if NOT(A = ((A / B) * B + (A rem B))) then
+          OKtest := 1;
+        end if;
+        assert (A = ((A / B) * B + (A rem B)))
+          report "Rem operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    -- 2. A negative, B positive.
+    for A in -1 downto -20 loop
+      for B in 1 to 20 loop
+        if NOT(A = ((A / B) * B + (A rem B))) then
+          OKtest := 1;
+        end if;
+        assert (A = ((A / B) * B + (A rem B)))
+          report "Rem operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    -- 3. A positive, B negative.
+    for A in 1 to 20 loop
+      for B in -1 downto -20 loop
+        if NOT(A = ((A / B) * B + (A rem B))) then
+          OKtest := 1;
+        end if;
+        assert (A = ((A / B) * B + (A rem B)))
+          report "Rem operation has failed for positive integers.";
+      end loop;
+    end loop;
+    
+    -- 4. Both negative.
+    for A in -1 downto -20 loop
+      for B in -1 downto -20 loop
+        if NOT(A = ((A / B) * B + (A rem B))) then
+          OKtest := 1;
+        end if;
+        assert (A = ((A / B) * B + (A rem B)))
+          report "Rem operation has failed for positive integers.";
+      end loop;
+    end loop;
+
+    wait for 5 ns;
+
+    assert NOT(OKtest = 0)
+      report "***PASSED TEST: c07s02b06x00p11n01i02267"
+      severity NOTE;
+    assert (OKtest = 0)
+      report "***FAILED TEST: c07s02b06x00p11n01i02267 - Integer division should satisfy the following identity: A = (A/B)*B + (A rem B)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p11n01i02267arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2268.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2268.vhd
new file mode 100644
index 0000000..faa11da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2268.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2268.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p12n01i02268ent IS
+END c07s02b06x00p12n01i02268ent;
+
+ARCHITECTURE c07s02b06x00p12n01i02268arch OF c07s02b06x00p12n01i02268ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := 10 mod (-3);
+    assert NOT(k = -2)
+      report "***PASSED TEST: c07s02b06x00p12n01i02268"
+      severity NOTE;
+    assert (k = -2)
+      report "***FAILED TEST: c07s02b06x00p12n01i02268 - The result of the modulus operation satisfy the relation :A = B*N + (A mod B)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p12n01i02268arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2269.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2269.vhd
new file mode 100644
index 0000000..5ebc3aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2269.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2269.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p12n01i02269ent IS
+END c07s02b06x00p12n01i02269ent;
+
+ARCHITECTURE c07s02b06x00p12n01i02269arch OF c07s02b06x00p12n01i02269ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable A, B    : INTEGER;
+    variable OKtest  : INTEGER := 0;
+  BEGIN
+    -- Test integer mod operations.
+    -- 1. Both positive.
+    for A in 0 to 20 loop
+      for B in 1 to 20 loop
+        if NOT(((A - (A mod B)) rem B) = 0) then
+          Oktest := 1;
+        end if;
+        assert (((A - (A mod B)) rem B) = 0)
+          report "Mod operation has failed for integers.";
+      end loop;
+    end loop;
+    
+    -- 2. A negative, B positive.
+    for A in -1 downto -20 loop
+      for B in 1 to 20 loop
+        if NOT(((A - (A mod B)) rem B) = 0) then
+          Oktest := 1;
+        end if;
+        assert (((A - (A mod B)) rem B) = 0)
+          report "Mod operation has failed for integers.";
+      end loop;
+    end loop;
+    
+    -- 3. A positive, B negative.
+    for A in 0 to 20 loop
+      for B in -1 downto -20 loop
+        if NOT(((A - (A mod B)) rem B) = 0) then
+          Oktest := 1;
+        end if;
+        assert (((A - (A mod B)) rem B) = 0)
+          report "Mod operation has failed for integers.";
+      end loop;
+    end loop;
+    
+    -- 4. Both negative.
+    for A in -1 downto -20 loop
+      for B in -1 downto -20 loop
+        if NOT(((A - (A mod B)) rem B) = 0) then
+          Oktest := 1;
+        end if;
+        assert (((A - (A mod B)) rem B) = 0)
+          report "Mod operation has failed for integers.";
+      end loop;
+    end loop;
+    wait for 5 ns;
+    assert NOT(OKtest=0)
+      report "***PASSED TEST: c07s02b06x00p12n01i02269"
+      severity NOTE;
+    assert (OKtest=0)
+      report "***FAILED TEST: c07s02b06x00p12n01i02269 - The result of the modulus operation satisfy the relation :A = B*N + (A mod B)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p12n01i02269arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2270.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2270.vhd
new file mode 100644
index 0000000..2081cf2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2270.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2270.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02270ent IS
+END c07s02b06x00p14n01i02270ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02270arch OF c07s02b06x00p14n01i02270ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type phys is range -10 to 100
+      units
+        p1;
+        p2 = 10 p1;
+        p3 = 5 p2;
+      end units;
+    variable k : phys := 10 p2;
+  BEGIN
+    assert NOT(k = 2 p3)
+      report "***PASSED TEST: c07s02b06x00p14n01i02270"
+      severity NOTE;
+    assert (k = 2 p3)
+      report "***FAILED TEST: c07s02b06x00p14n01i02270 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02270arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2271.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2271.vhd
new file mode 100644
index 0000000..f49b502
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2271.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2271.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02271ent IS
+END c07s02b06x00p14n01i02271ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02271arch OF c07s02b06x00p14n01i02271ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : time := 2 * 10 ns;
+  BEGIN
+    assert NOT(k = 20 ns)
+      report "***PASSED TEST: c07s02b06x00p14n01i02271"
+      severity NOTE;
+    assert (k = 20 ns)
+      report "***FAILED TEST: c07s02b06x00p14n01i02271 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02271arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2272.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2272.vhd
new file mode 100644
index 0000000..0a30df9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2272.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2272.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02272ent IS
+END c07s02b06x00p14n01i02272ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02272arch OF c07s02b06x00p14n01i02272ent IS
+  signal SS : TIME;
+BEGIN
+  TESTING: PROCESS
+    variable A : TIME    := 3 * 11 ns;
+    variable R : REAL    := 7.9999;
+    variable S : INTEGER    := 1;
+  BEGIN
+    SS <= R * ( S * A );            -- context 4
+    wait for 10 ns;
+    assert NOT((-0.01 ns < (SS - 3*11*7.9999 ns)) and ((SS - 3*11*7.9999 ns) < 0.01 ns))
+      report "***PASSED TEST: c07s02b06x00p14n01i02272"
+      severity NOTE;
+    assert ((-0.01 ns < (SS - 3*11*7.9999 ns)) and ((SS - 3*11*7.9999 ns) < 0.01 ns))
+      report "***FAILED TEST: c07s02b06x00p14n01i02272 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02272arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc228.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc228.vhd
new file mode 100644
index 0000000..37f9331
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc228.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc228.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00228ent IS
+END c03s01b01x00p07n01i00228ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00228arch OF c03s01b01x00p07n01i00228ent IS
+  type MVL is ('0', '1', 'Z') ;
+  type MVL1 is ('0', '1', 'Z', 'X') ;
+  signal S1 : MVL ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= '1' after 10 ns,
+          '0' after 20 ns,
+          'Z' after 50 ns; 
+    wait for 60 ns;
+    assert NOT( S1 = 'Z' )
+      report "***PASSED TEST: c03s01b01x00p07n01i00228"
+      severity NOTE;
+    assert ( S1 = 'Z' )
+      report "***FAILED TEST: c03s01b01x00p07n01i00228 - The type of an overloaded enumeration literal is determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00228arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2283.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2283.vhd
new file mode 100644
index 0000000..e89ca13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2283.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2283.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02283ent IS
+END c07s02b06x00p14n01i02283ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02283arch OF c07s02b06x00p14n01i02283ent IS
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 0 to 80000
+      units
+        PHYS1;
+        PHYS2 = 2 PHYS1;
+        PHYS10 = 10 PHYS1;
+        PHYS100 = 10 PHYS10;
+      end units;
+    function G ( A : PHYS; B : INTEGER; C : REAL ) return PHYS is
+    begin
+      return A / B * C;       
+    end G;
+    variable B : PHYS := 11 PHYS1;
+    variable R : REAL := 7.9999;
+  BEGIN
+    B := G(B,4,1.3) / 4 * 0.0 ;
+    assert NOT(B = 0 PHYS1) 
+      report "***PASSED TEST: c07s02b06x00p14n01i02283" 
+      severity NOTE;
+    assert (B = 0 PHYS1) 
+      report "***FAILED TEST: c07s02b06x00p14n01i02283 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02283arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2285.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2285.vhd
new file mode 100644
index 0000000..a3a6d12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2285.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2285.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02285ent IS
+END c07s02b06x00p14n01i02285ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02285arch OF c07s02b06x00p14n01i02285ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type phys is range -10 to 100
+      units
+        p1;
+        p2 = 10 p1;
+        p3 = 5 p2;
+      end units;
+    constant a : phys := 2 p3;
+    constant b : phys := 10 p2;
+    constant d : integer := a / b;
+  BEGIN
+    assert NOT(d = 1)
+      report "***PASSED TEST: c07s02b06x00p14n01i02285" 
+      severity NOTE;
+    assert (d = 1)
+      report "***FAILED TEST: c07s02b06x00p14n01i02285 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02285arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2286.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2286.vhd
new file mode 100644
index 0000000..05b89d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2286.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2286.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02286ent IS
+END c07s02b06x00p14n01i02286ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02286arch OF c07s02b06x00p14n01i02286ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PHYS is range 1 to 100000
+      units
+        A;
+        B = 100 A;
+        C = 100 B;
+      end units;
+    function F_PHYS ( A : PHYS ) return PHYS is
+    begin   
+      return A;       
+    end F_PHYS;
+    variable P : PHYS    := 1 B;
+    variable Z : integer := time'(1 min) / time'(27 sec);
+  BEGIN
+    Z  := P / F_PHYS(1 A);
+    assert NOT(Z = 100)
+      report "***PASSED TEST: c07s02b06x00p14n01i02286" 
+      severity NOTE;
+    assert (Z = 100)
+      report "***FAILED TEST: c07s02b06x00p14n01i02286 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02286arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2287.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2287.vhd
new file mode 100644
index 0000000..5f9310c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2287.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2287.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02287ent IS
+END c07s02b06x00p32n01i02287ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02287arch OF c07s02b06x00p32n01i02287ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 fs;
+    assert NOT(    ((1 fs * 1000) = 1 ps)    and   
+                   ((1 ps * 1000) = 1 ns)   and
+                   ((1 ns * 1000) = 1 us)   and
+                   ((1000 * 1 fs) = 1 ps)   and
+                   ((1000 * 1 ps) = 1 ns)   and
+                   ((1000 * 1 ns) = 1 us)   )
+      report "***PASSED TEST: c07s02b06x00p32n01i02287"
+      severity NOTE;
+    assert (    ((1 fs * 1000) = 1 ps)    and   
+                ((1 ps * 1000) = 1 ns)   and
+                ((1 ns * 1000) = 1 us)   and
+                ((1000 * 1 fs) = 1 ps)   and
+                ((1000 * 1 ps) = 1 ns)   and
+                ((1000 * 1 ns) = 1 us)   )
+      report "***FAILED TEST: c07s02b06x00p32n01i02287 - Multiplication of a predefined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02287arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2288.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2288.vhd
new file mode 100644
index 0000000..4750ae6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2288.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2288.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02288ent IS
+END c07s02b06x00p32n01i02288ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02288arch OF c07s02b06x00p32n01i02288ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- integer types.
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    ((1 A  * 10)    = 1 nm)   and
+                   ((1 nm * 1000)    = 1 um)   and
+                   ((1 um * 1000)    = 1 mm)   and
+                   ((1 mm * 10)    = 1 cm)   and
+                   ((10   * 1 A)    = 1 nm)   and
+                   ((1000 * 1 nm)    = 1 um)   and
+                   ((1000 * 1 um)    = 1 mm)   and
+                   ((10   * 1 mm)    = 1 cm)   and
+                   ((1 A * 254000) = 1 mil)and
+                   ((1 mil * 1000) = 1 inch)and
+                   ((254000 * 1 A) = 1 mil)and
+                   ((1000 * 1 mil) = 1 inch))
+      report "***PASSED TEST: c07s02b06x00p32n01i02288"
+      severity NOTE;
+    assert (    ((1 A  * 10)    = 1 nm)   and
+                ((1 nm * 1000)    = 1 um)   and
+                ((1 um * 1000)    = 1 mm)   and
+                ((1 mm * 10)    = 1 cm)   and
+                ((10   * 1 A)    = 1 nm)   and
+                ((1000 * 1 nm)    = 1 um)   and
+                ((1000 * 1 um)    = 1 mm)   and
+                ((10   * 1 mm)    = 1 cm)   and
+                ((1 A * 254000) = 1 mil)and
+                ((1 mil * 1000) = 1 inch)and
+                ((254000 * 1 A) = 1 mil)and
+                ((1000 * 1 mil) = 1 inch))
+      report "***FAILED TEST: c07s02b06x00p32n01i02288 - Multiplication of a physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02288arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2289.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2289.vhd
new file mode 100644
index 0000000..4a2bbf1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2289.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2289.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02289ent IS
+END c07s02b06x00p32n01i02289ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02289arch OF c07s02b06x00p32n01i02289ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    ((1 ns * 1000) = 1 us)   and   
+                   ((1 us * 1000) = 1 ms)   and
+                   ((1 ms * 1000) = 1 sec)   and
+                   ((1000 * 1 ns) = 1 us)   and
+                   ((1000 * 1 us) = 1 ms)   and
+                   ((1000 * 1 ms) = 1 sec)   )
+      report "***PASSED TEST: c07s02b06x00p32n01i02289"
+      severity NOTE;
+    assert (    ((1 ns * 1000) = 1 us)   and   
+                ((1 us * 1000) = 1 ms)   and
+                ((1 ms * 1000) = 1 sec)   and
+                ((1000 * 1 ns) = 1 us)   and
+                ((1000 * 1 us) = 1 ms)   and
+                ((1000 * 1 ms) = 1 sec)   )
+      report "***FAILED TEST: c07s02b06x00p32n01i02289 - Multiplication of a predefined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02289arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc229.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc229.vhd
new file mode 100644
index 0000000..dfcdb4e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc229.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc229.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00229ent IS
+  type big    is (a,b,c,d,e,f,g);
+  type small    is (f,g,h,i);
+END c03s01b01x00p07n01i00229ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00229arch OF c03s01b01x00p07n01i00229ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bigf   : big;
+    variable smallf   : small;
+    variable i,l   : integer;
+  BEGIN
+    bigf    := f;
+    smallf    := f;
+    i    := big'pos(f);
+    l    := small'pos(f);
+    assert NOT(i > l) 
+      report "***PASSED TEST: c03s01b01x00p07n01i00229"
+      severity NOTE;
+    assert (i > l) 
+      report "***FAILED TEST: c03s01b01x00p07n01i00229 - The type of an overloaded enumeration literal is determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00229arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2290.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2290.vhd
new file mode 100644
index 0000000..43de405
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2290.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2290.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02290ent IS
+END c07s02b06x00p32n01i02290ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02290arch OF c07s02b06x00p32n01i02290ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ms;
+    assert NOT(    ((1 ms * 1000) = 1 sec)   and
+                   ((1 sec * 60)  = 1 min)   and
+                   ((1 min * 60)  = 1 hr)   and
+                   ((1000 * 1 ms) = 1 sec)   and
+                   ((60 * 1 sec)  = 1 min)   and
+                   ((60 * 1 min)  = 1 hr))
+      report "***PASSED TEST: c07s02b06x00p32n01i02290"
+      severity NOTE;
+    assert (    ((1 ms * 1000) = 1 sec)   and
+                ((1 sec * 60)  = 1 min)   and
+                ((1 min * 60)  = 1 hr)   and
+                ((1000 * 1 ms) = 1 sec)   and
+                ((60 * 1 sec)  = 1 min)   and
+                ((60 * 1 min)  = 1 hr))
+      report "***FAILED TEST: c07s02b06x00p32n01i02290 - Multiplication of a predefined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02290arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2291.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2291.vhd
new file mode 100644
index 0000000..d30c13b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2291.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2291.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02291ent IS
+END c07s02b06x00p32n01i02291ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02291arch OF c07s02b06x00p32n01i02291ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 fs * 1000.0) > 1 fs)
+      report "Assertion error.(28)";
+    assert ((1 ps * 1000.0) > 1 ps)
+      report "Assertion error.(29)";
+    assert ((1 ns * 1000.0) > 1 ns)
+      report "Assertion error.(30)";
+    wait for 5 fs;
+    assert NOT(    ((1 fs * 1000.0) > 1 fs)   and
+                   ((1 ps * 1000.0) > 1 ps)   and
+                   ((1 ns * 1000.0) > 1 ns)   and
+                   ((1000.0 * 1 fs) > 1 fs)   and
+                   ((1000.0 * 1 ps) > 1 ps)   and
+                   ((1000.0 * 1 ns) > 1 ns)   )
+      report "***PASSED TEST: c07s02b06x00p32n01i02291"
+      severity NOTE;
+    assert (    ((1 fs * 1000.0) > 1 fs)   and
+                ((1 ps * 1000.0) > 1 ps)   and
+                ((1 ns * 1000.0) > 1 ns)   and
+                ((1000.0 * 1 fs) > 1 fs)   and
+                ((1000.0 * 1 ps) > 1 ps)   and
+                ((1000.0 * 1 ns) > 1 ns)   )
+      report "***FAILED TEST: c07s02b06x00p32n01i02291 - Multiplication of a predefined physical type by an floating point test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02291arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2292.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2292.vhd
new file mode 100644
index 0000000..952ac12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2292.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2292.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02292ent IS
+END c07s02b06x00p32n01i02292ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02292arch OF c07s02b06x00p32n01i02292ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+  BEGIN
+    wait for 5 ns;
+    assert ((1 A  * 10.0) > 1 A)
+      report "Assertion error.(1)";
+    assert ((1 nm * 1000.0) > 1 nm)
+      report "Assertion error.(2)";
+    assert ((1 um * 1000.0) > 1 um)
+      report "Assertion error.(3)";
+    assert ((1 mm * 10.0) > 1 mm)
+      report "Assertion error.(4)";
+    assert ((10.0  * 1 A) > 1 A)
+      report "Assertion error.(6)";
+    assert ((1000.0 * 1 nm) > 1 nm)
+      report "Assertion error.(7)";
+    assert ((1000.0 * 1 um) > 1 um)
+      report "Assertion error.(8)";
+    assert ((10.0 * 1 mm) > 1 mm)
+      report "Assertion error.(9)";
+    assert ((1 A * 254000.0) > 1 A)
+      report "Assertion error.(16)";
+    assert ((1 mil * 1000.0) > 1 mil)
+      report "Assertion error.(17)";
+    assert ((254000.0 * 1 A) > 1 A)
+      report "Assertion error.(20)";
+    assert ((1000.0 * 1 mil) > 1 mil)
+      report "Assertion error.(21)";
+    assert NOT(    ((1 A  * 10.0) > 1 A)   and
+                   ((1 nm * 1000.0) > 1 nm)and
+                   ((1 um * 1000.0) > 1 um)and
+                   ((1 mm * 10.0) > 1 mm)   and
+                   ((10.0  * 1 A) > 1 A)   and
+                   ((1000.0 * 1 nm) > 1 nm)and
+                   ((1000.0 * 1 um) > 1 um)and
+                   ((10.0 * 1 mm) > 1 mm)   and
+                   ((1 A * 254000.0) > 1 A)   and
+                   ((1 mil * 1000.0) > 1 mil)   and
+                   ((254000.0 * 1 A) > 1 A)   and
+                   ((1000.0 * 1 mil) > 1 mil)   )
+      report "***PASSED TEST: c07s02b06x00p32n01i02292"
+      severity NOTE;
+    assert (    ((1 A  * 10.0) > 1 A)   and
+                ((1 nm * 1000.0) > 1 nm)and
+                ((1 um * 1000.0) > 1 um)and
+                ((1 mm * 10.0) > 1 mm)   and
+                ((10.0  * 1 A) > 1 A)   and
+                ((1000.0 * 1 nm) > 1 nm)and
+                ((1000.0 * 1 um) > 1 um)and
+                ((10.0 * 1 mm) > 1 mm)   and
+                ((1 A * 254000.0) > 1 A)   and
+                ((1 mil * 1000.0) > 1 mil)   and
+                ((254000.0 * 1 A) > 1 A)   and
+                ((1000.0 * 1 mil) > 1 mil)   )
+      report "***FAILED TEST: c07s02b06x00p32n01i02292 - Multiplication of a physical type by an floating point test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02292arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2293.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2293.vhd
new file mode 100644
index 0000000..375e703
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2293.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2293.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02293ent IS
+END c07s02b06x00p32n01i02293ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02293arch OF c07s02b06x00p32n01i02293ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 us * 1000.0) > 1 us)
+      report "Assertion error.(31)";
+    assert ((1 ms * 1000.0) > 1 ms)
+      report "Assertion error.(32)";
+    assert ((1 sec * 60.0)  > 1 sec)
+      report "Assertion error.(33)";
+    wait for 5 us;
+    assert NOT(    ((1 us * 1000.0) > 1 us)   and
+                   ((1 ms * 1000.0) > 1 ms)   and
+                   ((1 sec * 60.0)  > 1 sec)   and
+                   ((1000.0 * 1 us) > 1 us)   and
+                   ((1000.0 * 1 ms) > 1 ms)   and
+                   ((60.0 * 1 sec)  > 1 sec)   )
+      report "***PASSED TEST: c07s02b06x00p32n01i02293"
+      severity NOTE;
+    assert (    ((1 us * 1000.0) > 1 us)   and
+                ((1 ms * 1000.0) > 1 ms)   and
+                ((1 sec * 60.0)  > 1 sec)   and
+                ((1000.0 * 1 us) > 1 us)   and
+                ((1000.0 * 1 ms) > 1 ms)   and
+                ((60.0 * 1 sec)  > 1 sec)   )
+      report "***FAILED TEST: c07s02b06x00p32n01i02293 - Multiplication of a predefined physical type by an floating point test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02293arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2294.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2294.vhd
new file mode 100644
index 0000000..6847fa6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2294.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2294.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p32n01i02294ent IS
+END c07s02b06x00p32n01i02294ent;
+
+ARCHITECTURE c07s02b06x00p32n01i02294arch OF c07s02b06x00p32n01i02294ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 min * 60.0)  > 1 min)
+      report "Assertion error.(34)";
+    assert ((60.0 * 1 min)  > 1 min)
+      report "Assertion error.(41)";
+    wait for 5 ms;
+    assert NOT(    ((1 min * 60.0)  > 1 min)   and
+                   ((60.0 * 1 min)  > 1 min)   ) 
+      report "***PASSED TEST: c07s02b06x00p32n01i02294"
+      severity NOTE;
+    assert (    ((1 min * 60.0)  > 1 min)   and
+                ((60.0 * 1 min)  > 1 min)   ) 
+      report "***FAILED TEST: c07s02b06x00p32n01i02294 - Multiplication of a predefined physical type by an floating point test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p32n01i02294arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2295.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2295.vhd
new file mode 100644
index 0000000..2ef64fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2295.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2295.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p33n01i02295ent IS
+END c07s02b06x00p33n01i02295ent;
+
+ARCHITECTURE c07s02b06x00p33n01i02295arch OF c07s02b06x00p33n01i02295ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 us / 1000) = 1 ns);
+    assert ((1 ns / 1000) = 1 ps);
+    assert ((1 ps / 1000) = 1 fs);
+    wait for 5 fs;
+    assert NOT(    ((1 us / 1000) = 1 ns)   and
+                   ((1 ns / 1000) = 1 ps)   and
+                   ((1 ps / 1000) = 1 fs)   )
+      report "***PASSED TEST: c07s02b06x00p33n01i02295"
+      severity NOTE;
+    assert (    ((1 us / 1000) = 1 ns)   and
+                ((1 ns / 1000) = 1 ps)   and
+                ((1 ps / 1000) = 1 fs)   )
+      report "***FAILED TEST: c07s02b06x00p33n01i02295 - Division of an user-defined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p33n01i02295arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2296.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2296.vhd
new file mode 100644
index 0000000..d9948ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2296.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2296.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p33n01i02296ent IS
+END c07s02b06x00p33n01i02296ent;
+
+ARCHITECTURE c07s02b06x00p33n01i02296arch OF c07s02b06x00p33n01i02296ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+  BEGIN
+    wait for 5 ns;
+    assert NOT(   ((1 cm / 10) = 1 mm)   and
+                  ((1 mm / 1000) = 1 um)   and
+                  ((1 um / 1000) = 1 nm)   and
+                  ((1 nm / 10) = 1 A))
+      report "***PASSED TEST: c07s02b06x00p33n01i02296"
+      severity NOTE;
+    assert (   ((1 cm / 10) = 1 mm)   and
+               ((1 mm / 1000) = 1 um)   and
+               ((1 um / 1000) = 1 nm)   and
+               ((1 nm / 10) = 1 A))
+      report "***FAILED TEST: c07s02b06x00p33n01i02296 - Division of an user-defined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p33n01i02296arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2297.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2297.vhd
new file mode 100644
index 0000000..f1fd555
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2297.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2297.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p33n01i02297ent IS
+END c07s02b06x00p33n01i02297ent;
+
+ARCHITECTURE c07s02b06x00p33n01i02297arch OF c07s02b06x00p33n01i02297ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 min / 60)    = 1 sec);
+    assert ((1 sec / 1000)    = 1 ms);
+    assert ((1 ms / 1000)    = 1 us);
+    wait for 5 us;
+    assert NOT(   ((1 min / 60)    = 1 sec)   and
+                  ((1 sec / 1000) = 1 ms)      and
+                  ((1 ms / 1000)    = 1 us)   )
+      report "***PASSED TEST: c07s02b06x00p33n01i02297"
+      severity NOTE;
+    assert (   ((1 min / 60)    = 1 sec)   and
+               ((1 sec / 1000) = 1 ms)      and
+               ((1 ms / 1000)    = 1 us)   )
+      report "***FAILED TEST: c07s02b06x00p33n01i02297 - Division of an user-defined physical type by an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p33n01i02297arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2298.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2298.vhd
new file mode 100644
index 0000000..3520ee0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2298.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2298.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p35n01i02298ent IS
+END c07s02b06x00p35n01i02298ent;
+
+ARCHITECTURE c07s02b06x00p35n01i02298arch OF c07s02b06x00p35n01i02298ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 ns / 1000.0) < 1 ns);
+    assert ((1 ps / 1000.0) < 1 ps);
+    assert ((1 fs / 1000.0) < 1 fs);
+    wait for 5 fs;
+    assert NOT(    ((1 ns / 1000.0) < 1 ns)   and
+                   ((1 ps / 1000.0) < 1 ps)   and
+                   ((1 fs / 1000.0) < 1 fs))   
+      report "***PASSED TEST: c07s02b06x00p35n01i02298"
+      severity NOTE;
+    assert (    ((1 ns / 1000.0) < 1 ns)   and
+                ((1 ps / 1000.0) < 1 ps)   and
+                ((1 fs / 1000.0) < 1 fs))   
+      report "***FAILED TEST: c07s02b06x00p35n01i02298 - Division of an predefined physical type by a real type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p35n01i02298arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2299.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2299.vhd
new file mode 100644
index 0000000..a828124
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2299.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2299.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p35n01i02299ent IS
+END c07s02b06x00p35n01i02299ent;
+
+ARCHITECTURE c07s02b06x00p35n01i02299arch OF c07s02b06x00p35n01i02299ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+
+  BEGIN
+    -- Test simple user-defined physical type * integer expressions.
+    assert ((1 cm / 10.0) < 1 cm);
+    assert ((1 mm / 1000.0) < 1 mm);
+    assert ((1 um / 1000.0) < 1 um);
+    assert ((1 nm / 10.0) < 1 nm);
+    wait for 5 ns;
+    assert NOT(    ((1 cm / 10.0) < 1 cm)   and
+                   ((1 mm / 1000.0) < 1 mm)and
+                   ((1 um / 1000.0) < 1 um)and
+                   ((1 nm / 10.0) < 1 nm)   )
+      report "***PASSED TEST: c07s02b06x00p35n01i02299"
+      severity NOTE;
+    assert (    ((1 cm / 10.0) < 1 cm)   and
+                ((1 mm / 1000.0) < 1 mm)and
+                ((1 um / 1000.0) < 1 um)and
+                ((1 nm / 10.0) < 1 nm)   )
+      report "***FAILED TEST: c07s02b06x00p35n01i02299 - Division of an user-defined physical type by a real type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p35n01i02299arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc23.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc23.vhd
new file mode 100644
index 0000000..61b2a53
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc23.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc23.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p09n03i00023ent IS
+END c04s02b00x00p09n03i00023ent;
+
+ARCHITECTURE c04s02b00x00p09n03i00023arch OF c04s02b00x00p09n03i00023ent IS
+  type    T1 is     range 0  to 100;
+  subtype T2 is T1 range 20 to 80 ;
+  subtype T3 is T2 range 40 to 60 ;  -- No_failure_here
+  subtype T4 is T3 range 50 to 50 ;
+BEGIN
+  TESTING: PROCESS
+    variable k : T4 := 50;
+  BEGIN
+    assert NOT(k=50) 
+      report "***PASSED TEST: c04s02b00x00p09n03i00023"
+      severity NOTE;
+    assert (k=50) 
+      report "***FAILED TEST: c04s02b00x00p09n03i00023 - Range constraints for the subtype declarations contradict the range of the subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p09n03i00023arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc230.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc230.vhd
new file mode 100644
index 0000000..966021b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc230.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc230.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p02n01i00230ent IS
+END c03s01b02x00p02n01i00230ent;
+
+ARCHITECTURE c03s01b02x00p02n01i00230arch OF c03s01b02x00p02n01i00230ent IS
+  type a is range (((((10-1)-1)-1)-1)-1) to (((((10+1)+1)+1)+1)+1);
+BEGIN
+  TESTING: PROCESS
+    variable k : a := 11;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p02n01i00230" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p02n01i00230 - The right bound in the range constraint is not a locally static expression of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p02n01i00230arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2300.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2300.vhd
new file mode 100644
index 0000000..808e2e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2300.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2300.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p35n01i02300ent IS
+END c07s02b06x00p35n01i02300ent;
+
+ARCHITECTURE c07s02b06x00p35n01i02300arch OF c07s02b06x00p35n01i02300ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 sec / 1000.0) < 1 sec);
+    assert ((1 ms / 1000.0) < 1 ms);
+    assert ((1 us / 1000.0) < 1 us);
+    wait for 5 us;
+    assert NOT(    ((1 sec / 1000.0) < 1 sec)   and
+                   ((1 ms / 1000.0) < 1 ms)   and
+                   ((1 us / 1000.0) < 1 us)   )
+      report "***PASSED TEST: c07s02b06x00p35n01i02300"
+      severity NOTE;
+    assert (    ((1 sec / 1000.0) < 1 sec)   and
+                ((1 ms / 1000.0) < 1 ms)   and
+                ((1 us / 1000.0) < 1 us)   )
+      report "***FAILED TEST: c07s02b06x00p35n01i02300 - Division of an predefined physical type by a real type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p35n01i02300arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2301.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2301.vhd
new file mode 100644
index 0000000..3f9f088
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2301.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2301.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p35n01i02301ent IS
+END c07s02b06x00p35n01i02301ent;
+
+ARCHITECTURE c07s02b06x00p35n01i02301arch OF c07s02b06x00p35n01i02301ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test the predefined type TIME in this respect.
+    assert ((1 hr / 60.0) < 1 hr);
+    assert ((1 min / 60.0) < 1 min);
+    wait for 5 ms;
+    assert NOT(    ((1 hr / 60.0) < 1 hr)      and
+                   ((1 min / 60.0) < 1 min)   )
+      report "***PASSED TEST: c07s02b06x00p35n01i02301"
+      severity NOTE;
+    assert (    ((1 hr / 60.0) < 1 hr)      and
+                ((1 min / 60.0) < 1 min)   )
+      report "***FAILED TEST: c07s02b06x00p35n01i02301 - Division of an predefined physical type by a real type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p35n01i02301arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2302.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2302.vhd
new file mode 100644
index 0000000..773a0ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2302.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2302.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p37n01i02302ent IS
+END c07s02b06x00p37n01i02302ent;
+
+ARCHITECTURE c07s02b06x00p37n01i02302arch OF c07s02b06x00p37n01i02302ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test dividing the predefined type TIME.
+    assert ((1 us / 1 ns) = 1000);
+    assert ((1 ns / 1 ps) = 1000);
+    assert ((1 ps / 1 fs) = 1000);
+    wait for 5 fs;
+    assert NOT(    ((1 us / 1 ns) = 1000)   and
+                   ((1 ns / 1 ps) = 1000)   and
+                   ((1 ps / 1 fs) = 1000)   )
+      report "***PASSED TEST: c07s02b06x00p37n01i02302"
+      severity NOTE;
+    assert (    ((1 us / 1 ns) = 1000)   and
+                ((1 ns / 1 ps) = 1000)   and
+                ((1 ps / 1 fs) = 1000)   )
+      report "***FAILED TEST: c07s02b06x00p37n01i02302 - Division of a physical type by another physical type (predefined TIME) test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p37n01i02302arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2303.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2303.vhd
new file mode 100644
index 0000000..811f3f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2303.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2303.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p37n01i02303ent IS
+END c07s02b06x00p37n01i02303ent;
+
+ARCHITECTURE c07s02b06x00p37n01i02303arch OF c07s02b06x00p37n01i02303ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+  BEGIN
+    -- Test dividing user-defined physical type values.
+    assert ((1 cm / 1 mm) = 10);
+    assert ((1 mm / 1 um) = 1000);
+    assert ((1 um / 1 nm) = 1000);
+    assert ((1 nm / 1 A) = 10);
+    wait for 5 ns;
+    assert NOT(    ((1 cm / 1 mm) = 10)   and
+                   ((1 mm / 1 um) = 1000)   and
+                   ((1 um / 1 nm) = 1000)   and
+                   ((1 nm / 1 A) = 10)   )
+      report "***PASSED TEST: c07s02b06x00p37n01i02303"
+      severity NOTE;
+    assert (    ((1 cm / 1 mm) = 10)   and
+                ((1 mm / 1 um) = 1000)   and
+                ((1 um / 1 nm) = 1000)   and
+                ((1 nm / 1 A) = 10)   )
+      report "***FAILED TEST: c07s02b06x00p37n01i02303 - Division of a physical type by another physical type (user-defined) test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p37n01i02303arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2304.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2304.vhd
new file mode 100644
index 0000000..0370861
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2304.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2304.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p37n01i02304ent IS
+END c07s02b06x00p37n01i02304ent;
+
+ARCHITECTURE c07s02b06x00p37n01i02304arch OF c07s02b06x00p37n01i02304ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test dividing the predefined type TIME.
+    assert ((1 min / 1 sec) = 60);
+    assert ((1 sec / 1 ms) = 1000);
+    assert ((1 ms / 1 us) = 1000);
+    wait for 5 us;
+    assert NOT(    ((1 min / 1 sec) = 60)   and   
+                   ((1 sec / 1 ms) = 1000)   and
+                   ((1 ms / 1 us) = 1000)   )
+      report "***PASSED TEST: c07s02b06x00p37n01i02304"
+      severity NOTE;
+    assert (    ((1 min / 1 sec) = 60)   and   
+                ((1 sec / 1 ms) = 1000)   and
+                ((1 ms / 1 us) = 1000)   )
+      report "***FAILED TEST: c07s02b06x00p37n01i02304 - Division of a physical type by another physical type (predefined TIME) test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p37n01i02304arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2305.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2305.vhd
new file mode 100644
index 0000000..4baba80
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2305.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2305.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p37n01i02305ent IS
+END c07s02b06x00p37n01i02305ent;
+
+ARCHITECTURE c07s02b06x00p37n01i02305arch OF c07s02b06x00p37n01i02305ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    -- Test dividing the predefined type TIME.
+    assert ((1 hr / 1 min) = 60);
+    assert ((1 min / 1 sec) = 60);
+    wait for 5 sec;
+    assert NOT(    ((1 hr / 1 min) = 60)   and
+                   ((1 min / 1 sec) = 60)   )
+      report "***PASSED TEST: c07s02b06x00p37n01i02305"
+      severity NOTE;
+    assert (    ((1 hr / 1 min) = 60)   and
+                ((1 min / 1 sec) = 60)   )
+      report "***FAILED TEST: c07s02b06x00p37n01i02305 - Division of a physical type by another physical type (predefined TIME) test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p37n01i02305arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2307.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2307.vhd
new file mode 100644
index 0000000..da8b698
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2307.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2307.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02307ent IS
+END c07s02b07x00p01n01i02307ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02307arch OF c07s02b07x00p01n01i02307ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x : integer := abs 10;
+  BEGIN
+    assert NOT(x = 10) 
+      report "***PASSED TEST: c07s02b07x00p01n01i02307" 
+      severity NOTE;
+    assert (x = 10) 
+      report "***FAILED TEST: c07s02b07x00p01n01i02307 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02307arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2308.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2308.vhd
new file mode 100644
index 0000000..ae72cf5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2308.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2308.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02308ent IS
+END c07s02b07x00p01n01i02308ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02308arch OF c07s02b07x00p01n01i02308ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x : real := abs 10.5;
+  BEGIN
+    assert NOT(x = 10.5) 
+      report "***PASSED TEST: c07s02b07x00p01n01i02308" 
+      severity NOTE;
+    assert (x = 10.5) 
+      report "***FAILED TEST: c07s02b07x00p01n01i02308 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02308arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2309.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2309.vhd
new file mode 100644
index 0000000..cc07ae9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2309.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2309.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02309ent IS
+END c07s02b07x00p01n01i02309ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02309arch OF c07s02b07x00p01n01i02309ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type phys is range -10 to 100
+      units
+        p1;
+        p2 = 10 p1;
+        p3 = 5 p2;
+      end units;
+    constant b : phys := abs (10 p2);
+  BEGIN
+    assert NOT(b = 100 p1) 
+      report "***PASSED TEST: c07s02b07x00p01n01i02309" 
+      severity NOTE;
+    assert (b = 100 p1) 
+      report "***FAILED TEST: c07s02b07x00p01n01i02309 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02309arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2324.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2324.vhd
new file mode 100644
index 0000000..8c48162
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2324.vhd
@@ -0,0 +1,175 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2324.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02324ent IS
+END c07s02b07x00p01n01i02324ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02324arch OF c07s02b07x00p01n01i02324ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable INTV1    : INTEGER;
+    variable INTV2    : INTEGER;
+    variable INTV3    : INTEGER;
+    variable INTV4    : INTEGER;
+    variable INTV5    : INTEGER;
+    variable INTV6    : INTEGER;
+    variable INTV7    : INTEGER;
+    variable INTV8    : INTEGER;
+    variable REALV1   : REAL;
+    variable REALV2   : REAL;
+    variable REALV3   : REAL;
+    variable REALV4   : REAL;
+    variable REALV5   : REAL;
+    variable REALV6   : REAL;
+    variable REALV7   : REAL;
+    variable REALV8   : REAL;
+  BEGIN
+    -- Test absolute value of integer literals and variables.
+    INTV1 := abs (-5);
+    assert (INTV1 = 5)
+      report "Assertion Violation(1)";
+    INTV2 := abs 5;
+    assert (INTV2 = 5)
+      report "Assertion Violation(2)";
+    INTV3 := abs 0;
+    assert (INTV3 = 0)
+      report "Assertion Violation(3)";
+    INTV4 := abs INTEGER'HIGH;
+    assert (INTV4 = INTEGER'HIGH)
+      report "Assertion Violation(4)";
+    
+    INTV5 := -5;
+    INTV5 := abs INTV5;
+    assert (INTV5 = 5)
+      report "Assertion Violation(5)";
+    INTV6 := 5;
+    INTV6 := abs 5;
+    assert (INTV6 = 5)
+      report "Assertion Violation(6)";
+    INTV7 := 0;
+    INTV7 := abs 0;
+    assert (INTV7 = 0)
+      report "Assertion Violation(7)";
+    INTV8 := INTEGER'HIGH;
+    INTV8 := abs INTEGER'HIGH;
+    assert (INTV8 = INTEGER'HIGH)
+      report "Assertion Violation(8)";
+    
+    -- Do the same for the predefined physical type TIME.
+    assert (abs (-5 ns) = 5 ns)
+      report "Assertion Violation(9)";
+    assert (abs 5 ns = 5 ns)
+      report "Assertion Violation(10)";
+    assert (abs 0 fs = 0 fs)
+      report "Assertion Violation(11)";
+    assert (abs TIME'HIGH = TIME'HIGH)
+      report "Assertion Violation(12)";
+    
+    -- Test absolute value of real literals and variables.
+    REALV1 := abs (-5.0);
+    assert (REALV1 = 5.0)
+      report "Assertion Violation(13)";
+    REALV2 := abs 5.0;
+    assert (REALV2 = 5.0)
+      report "Assertion Violation(14)";
+    REALV3 := abs 0.0;
+    assert (REALV3 = 0.0)
+      report "Assertion Violation(15)";
+    REALV4 := abs REAL'HIGH;
+    assert (REALV4 = REAL'HIGH)
+      report "Assertion Violation(16)";
+
+    REALV5 := -5.0;
+    REALV5 := abs REALV5;
+    assert (REALV5 = 5.0)
+      report "Assertion Violation(17)";
+    REALV6 := 5.0;
+    REALV6 := abs 5.0;
+    assert (REALV6 = 5.0)
+      report "Assertion Violation(18)";
+    REALV7 := 0.0;
+    REALV7 := abs 0.0;
+    assert (REALV7 = 0.0)
+      report "Assertion Violation(19)";
+    REALV8 := REAL'HIGH;
+    REALV8 := abs REAL'HIGH;
+    assert (REALV8 = REAL'HIGH)
+      report "Assertion Violation(20)";
+    wait for 5 ns;
+    assert NOT(   (INTV1 = 5)      and
+                  (INTV2 = 5)      and
+                  (INTV3 = 0)      and
+                  (INTV4 = INTEGER'HIGH)   and
+                  (INTV5 = 5)      and
+                  (INTV6 = 5)      and
+                  (INTV7 = 0)      and
+                  (INTV8 = INTEGER'HIGH)   and
+                  (abs (-5 ns) = 5 ns)   and
+                  (abs 5 ns = 5 ns)   and
+                  (abs 0 fs = 0 fs)   and
+                  (abs TIME'HIGH = TIME'HIGH)   and
+                  (REALV1 = 5.0)      and
+                  (REALV2 = 5.0)      and
+                  (REALV3 = 0.0)      and
+                  (REALV4 = REAL'HIGH)   and
+                  (REALV5 = 5.0)      and
+                  (REALV6 = 5.0)      and
+                  (REALV7 = 0.0)      and
+                  (REALV8 = REAL'HIGH)   ) 
+      report "***PASSED TEST: c07s02b07x00p01n01i02324" 
+      severity NOTE;
+    assert (   (INTV1 = 5)      and
+               (INTV2 = 5)      and
+               (INTV3 = 0)      and
+               (INTV4 = INTEGER'HIGH)   and
+               (INTV5 = 5)      and
+               (INTV6 = 5)      and
+               (INTV7 = 0)      and
+               (INTV8 = INTEGER'HIGH)   and
+               (abs (-5 ns) = 5 ns)   and
+               (abs 5 ns = 5 ns)   and
+               (abs 0 fs = 0 fs)   and
+               (abs TIME'HIGH = TIME'HIGH)   and
+               (REALV1 = 5.0)      and
+               (REALV2 = 5.0)      and
+               (REALV3 = 0.0)      and
+               (REALV4 = REAL'HIGH)   and
+               (REALV5 = 5.0)      and
+               (REALV6 = 5.0)      and
+               (REALV7 = 0.0)      and
+               (REALV8 = REAL'HIGH)   ) 
+      report "***FAILED TEST: c07s02b07x00p01n01i02324 - Unary operator abs for any numeric type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02324arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2325.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2325.vhd
new file mode 100644
index 0000000..ae13b74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2325.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2325.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i02325ent IS
+END c07s01b00x00p07n01i02325ent;
+
+ARCHITECTURE c07s01b00x00p07n01i02325arch OF c07s01b00x00p07n01i02325ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real := 0.0;
+  BEGIN
+    k := abs (-10.3);
+    assert NOT( k = 10.3 )
+      report "***PASSED TEST: c07s01b00x00p07n01i02325"
+      severity NOTE;
+    assert ( k = 10.3 )
+      report "***FAILED TEST: c07s01b00x00p07n01i02325 - The result of the 'abs' operation must be the absolute value of the operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i02325arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2326.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2326.vhd
new file mode 100644
index 0000000..5a8e5cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2326.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2326.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i02326ent IS
+END c07s01b00x00p07n01i02326ent;
+
+ARCHITECTURE c07s01b00x00p07n01i02326arch OF c07s01b00x00p07n01i02326ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable r1, r2, r3, r4 : real;
+  BEGIN
+    
+    r1 := 69.0;
+    r2 := 50.0;
+    r3 := (-69.0);
+    r4 := (-50.0);
+    wait for 5 ns; 
+    assert NOT(   ( r1 = abs(r3))   and
+                  ( r2 = abs(r4))   and
+                  ( 50.0 = abs(-50.0))   and
+                  ( (-25.0) = (-abs(-25.0)))   and
+                  ( 3.14E-2 = abs(-3.14E-2))   and
+                  ( (-0.379) = (-abs(-0.379)))   ) 
+      report "***PASSED TEST: c07s01b00x00p07n01i02326"
+      severity NOTE;
+    assert (   ( r1 = abs(r3))   and
+               ( r2 = abs(r4))   and
+               ( 50.0 = abs(-50.0))   and
+               ( (-25.0) = (-abs(-25.0)))   and
+               ( 3.14E-2 = abs(-3.14E-2))   and
+               ( (-0.379) = (-abs(-0.379)))   ) 
+      report "***FAILED TEST: c07s01b00x00p07n01i02326 - The result of the 'abs' operation must be the absolute value of the operand."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i02326arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2329.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2329.vhd
new file mode 100644
index 0000000..522af65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2329.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2329.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02329ent IS
+END c07s02b07x00p02n02i02329ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02329arch OF c07s02b07x00p02n02i02329ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
+    function L1 ( A : NEW_INT; B : integer ) return NEW_INT is
+    begin
+      return A ** B;  -- context 1
+    end L1;
+    variable k : NEW_INT := 0;
+  BEGIN
+    k := L1(2,2);
+    assert NOT(k=4) 
+      report "***PASSED TEST: c07s02b07x00p02n02i02329"
+      severity NOTE;
+    assert (k=4) 
+      report "***FAILED TEST: c07s02b07x00p02n02i02329 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02329arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2330.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2330.vhd
new file mode 100644
index 0000000..827fc46
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2330.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2330.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02330ent IS
+END c07s02b07x00p02n02i02330ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02330arch OF c07s02b07x00p02n02i02330ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
+    variable k : NEW_INT := 2 ** 5;
+  BEGIN
+    assert NOT(k=32) 
+      report "***PASSED TEST: c07s02b07x00p02n02i02330" 
+      severity NOTE;
+    assert (k=32) 
+      report "***FAILED TEST: c07s02b07x00p02n02i02330 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02330arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2331.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2331.vhd
new file mode 100644
index 0000000..3121f58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2331.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2331.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02331ent IS
+END c07s02b07x00p02n02i02331ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02331arch OF c07s02b07x00p02n02i02331ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
+    variable k : NEW_INT := 5;
+  BEGIN
+    k := 2 ** 2;
+    assert NOT(k=4) 
+      report "***PASSED TEST: c07s02b07x00p02n02i02331" 
+      severity NOTE;
+    assert (k=4) 
+      report "***FAILED TEST: c07s02b07x00p02n02i02331 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02331arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2332.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2332.vhd
new file mode 100644
index 0000000..b52012c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2332.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2332.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02332ent IS
+END c07s02b07x00p02n02i02332ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02332arch OF c07s02b07x00p02n02i02332ent IS
+  type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
+  signal k : NEW_INT := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 2 ** 2;
+    wait for 1 ns;
+    assert NOT(k=4) 
+      report "***PASSED TEST: c07s02b07x00p02n02i02332" 
+      severity NOTE;
+    assert (k=4) 
+      report "***FAILED TEST: c07s02b07x00p02n02i02332 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02332arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc234.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc234.vhd
new file mode 100644
index 0000000..f81a5f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc234.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc234.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p02n01i00234ent IS
+END c03s01b02x00p02n01i00234ent;
+
+ARCHITECTURE c03s01b02x00p02n01i00234arch OF c03s01b02x00p02n01i00234ent IS
+  type a is range (((((10-1)-1)-1)-1)-1) to (((((10+1)+1)+1)+1)+1);
+BEGIN
+  TESTING: PROCESS
+    variable k : a := 11;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p02n01i00234"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p02n01i00234 - The right bound in the range constraint is not a locally static expression of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p02n01i00234arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2359.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2359.vhd
new file mode 100644
index 0000000..5d92f5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2359.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2359.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p06n01i02359ent IS
+END c07s02b07x00p06n01i02359ent;
+
+ARCHITECTURE c07s02b07x00p06n01i02359arch OF c07s02b07x00p06n01i02359ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable r1,r2,r3,r4,r5,r6   : real;
+    variable r7,r8,r9,r10      : real;
+    variable i1         : integer;
+  BEGIN
+
+    r2 := 2.0;
+    r3 := 10.0;
+    i1 := 10;
+    r1 := 2.0 ** 10;
+    r4 := r2 ** i1;
+    r5 := (-2.0)**10;
+    r6 := 0.0 ** i1;
+    r7 := 0.0 ** 5;
+    r8 := 2.0;
+    r9 := r8 ** 0;
+    r10:= r8 ** (-0);
+    wait for 5 ns;
+    assert NOT(    ( r1 = r4 )   and
+                   ( r1 = 1024.0)   and
+                   ( r1 = r5 )   and
+                   ( r6 = 0.0)   and
+                   ( r6 = r7 )   and
+                   ( r9 = 1.0 )   and
+                   ( r10= r9 )   )
+      report "***PASSED TEST: c07s02b07x00p06n01i02359"
+      severity NOTE;
+    assert (    ( r1 = r4 )   and
+                ( r1 = 1024.0)   and
+                ( r1 = r5 )   and
+                ( r6 = 0.0)   and
+                ( r6 = r7 )   and
+                ( r9 = 1.0 )   and
+                ( r10= r9 )   )
+      report "***FAILED TEST: c07s02b07x00p06n01i02359 - Unary operator exponentiation test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p06n01i02359arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2360.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2360.vhd
new file mode 100644
index 0000000..ad765ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2360.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2360.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p10n01i02360ent IS
+END c07s02b07x00p10n01i02360ent;
+
+ARCHITECTURE c07s02b07x00p10n01i02360arch OF c07s02b07x00p10n01i02360ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real := 0.0;
+  BEGIN
+    k := 2.5**4;
+    wait for 5 ns;
+    assert NOT(k=39.0625)
+      report "***PASSED TEST: c07s02b07x00p10n01i02360"
+      severity NOTE;
+    assert (k=39.0625)
+      report "***FAILED TEST: c07s02b07x00p10n01i02360 - Exponentiation with an integer exponent is equivalent to repeated multiplication of the left operand by itself."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p10n01i02360arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2363.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2363.vhd
new file mode 100644
index 0000000..94ca3ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2363.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2363.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p10n01i02363ent IS
+END c07s02b07x00p10n01i02363ent;
+
+ARCHITECTURE c07s02b07x00p10n01i02363arch OF c07s02b07x00p10n01i02363ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable INTV : INTEGER;
+    variable res  : real;
+  BEGIN
+    INTV := -2;
+    res  := 3.0 ** INTV;
+    wait for 5 ns;
+    assert NOT((0.1111111 < res) and (res < 0.1111112))
+      report "***PASSED TEST: c07s02b07x00p10n01i02363"
+      severity NOTE;
+    assert ((0.1111111 < res) and (res < 0.1111112))
+      report "***FAILED TEST: c07s02b07x00p10n01i02363 - Exponentiation of a real with a negative exponent test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p10n01i02363arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2364.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2364.vhd
new file mode 100644
index 0000000..0cb2b28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2364.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2364.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p01n01i02364ent IS
+END c07s03b01x00p01n01i02364ent;
+
+ARCHITECTURE c07s03b01x00p01n01i02364arch OF c07s03b01x00p01n01i02364ent IS
+  signal S3 : Integer := 1111 ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S3 <= 5555;
+    wait for 1 ns;
+    assert NOT(S3 = 5555)
+      report "***PASSED TEST: c07s03b01x00p01n01i02364"
+      severity NOTE;
+    assert (S3 = 5555)
+      report "***FAILED TEST: c07s03b01x00p01n01i02364 - A literal is a numeric literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p01n01i02364arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2365.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2365.vhd
new file mode 100644
index 0000000..7206f95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2365.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2365.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p01n01i02365ent IS
+END c07s03b01x00p01n01i02365ent;
+
+ARCHITECTURE c07s03b01x00p01n01i02365arch OF c07s03b01x00p01n01i02365ent IS
+  type    MVL is ('0','1','X','Z') ;
+  signal    S2  : MVL := '0';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= 'X';
+    wait for 1 ns;
+    assert NOT(S2 = 'X')
+      report "***PASSED TEST: c07s03b01x00p01n01i02365"
+      severity NOTE;
+    assert (S2 = 'X')
+      report "***FAILED TEST: c07s03b01x00p01n01i02365 - A literal is an enumeration literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p01n01i02365arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2366.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2366.vhd
new file mode 100644
index 0000000..d59b748
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2366.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2366.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p01n01i02366ent IS
+END c07s03b01x00p01n01i02366ent;
+
+ARCHITECTURE c07s03b01x00p01n01i02366arch OF c07s03b01x00p01n01i02366ent IS
+  constant C1 : STRING := "54LS271" ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT( C1 = "54LS271" )
+      report "***PASSED TEST: c07s03b01x00p01n01i02366"
+      severity NOTE;
+    assert ( C1 = "54LS271" )
+      report "***FAILED TEST: c07s03b01x00p01n01i02366 - A literal is a string literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p01n01i02366arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2367.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2367.vhd
new file mode 100644
index 0000000..62381cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2367.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2367.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p01n01i02367ent IS
+END c07s03b01x00p01n01i02367ent;
+
+ARCHITECTURE c07s03b01x00p01n01i02367arch OF c07s03b01x00p01n01i02367ent IS
+  constant C1 : STRING := "" ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT( C1 = "" )
+      report "***PASSED TEST: c07s03b01x00p01n01i02367"
+      severity NOTE;
+    assert ( C1 = "" )
+      report "***FAILED TEST: c07s03b01x00p01n01i02367 - A literal is the literal null." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p01n01i02367arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2368.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2368.vhd
new file mode 100644
index 0000000..c104af7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2368.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2368.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p01n01i02368ent IS
+END c07s03b01x00p01n01i02368ent;
+
+ARCHITECTURE c07s03b01x00p01n01i02368arch OF c07s03b01x00p01n01i02368ent IS
+  constant C1 : bit_vector(0 to 7) := "01010101" ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT( C1 = "01010101" )
+      report "***PASSED TEST: c07s03b01x00p01n01i02368"
+      severity NOTE;
+    assert ( C1 = "01010101" )
+      report "***FAILED TEST: c07s03b01x00p01n01i02368 - A literal is a bit string literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p01n01i02368arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2369.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2369.vhd
new file mode 100644
index 0000000..6bcc22a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2369.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2369.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p06n02i02369ent IS
+END c07s03b01x00p06n02i02369ent;
+
+ARCHITECTURE c07s03b01x00p06n02i02369arch OF c07s03b01x00p06n02i02369ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( O"4777" = B"100_111_111_111" )
+      report "***PASSED TEST: c07s03b01x00p06n02i02369"
+      severity NOTE;
+    assert ( O"4777" = B"100_111_111_111" )
+      report "***FAILED TEST: c07s03b01x00p06n02i02369 - The type of the literal is determinable from the context in which it appears."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p06n02i02369arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2370.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2370.vhd
new file mode 100644
index 0000000..02cacea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2370.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2370.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p06n02i02370ent IS
+END c07s03b01x00p06n02i02370ent;
+
+ARCHITECTURE c07s03b01x00p06n02i02370arch OF c07s03b01x00p06n02i02370ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define a new string type.
+    type KRING is array( natural range <> ) of CHARACTER;
+    variable K : KRING( 1 to 10 ) := "it is cold";
+  BEGIN
+    assert NOT( K = "it is cold" )
+      report "***PASSED TEST: c07s03b01x00p06n02i02370"
+      severity NOTE;
+    assert ( K = "it is cold" )
+      report "***FAILED TEST: c07s03b01x00p06n02i02370 - The type of the literal is determinable from the context in which it appears."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p06n02i02370arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2371.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2371.vhd
new file mode 100644
index 0000000..3cde245
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2371.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2371.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p07n01i02371ent IS
+END c07s03b01x00p07n01i02371ent;
+
+ARCHITECTURE c07s03b01x00p07n01i02371arch OF c07s03b01x00p07n01i02371ent IS
+  constant S1 : BIT_VECTOR := B"111_111_110";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((S1'LEFT = 0) and (S1'RIGHT = 8))
+      report "***PASSED TEST: c07s03b01x00p07n01i02371"
+      severity NOTE;
+    assert ((S1'LEFT = 0) and (S1'RIGHT = 8))
+      report "***FAILED TEST: c07s03b01x00p07n01i02371 - The number of elements in the aggregate is equal to the length of the string or bit string literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p07n01i02371arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2372.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2372.vhd
new file mode 100644
index 0000000..3f2367b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2372.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2372.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p07n02i02372ent IS
+END c07s03b01x00p07n02i02372ent;
+
+ARCHITECTURE c07s03b01x00p07n02i02372arch OF c07s03b01x00p07n02i02372ent IS
+  constant S1 : BIT_VECTOR := B"111_111_110" ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((S1'LEFT = 0) and (S1(0) = '1') and (S1'RIGHT = 8) and (S1(8) = '0')) 
+      report "***PASSED TEST: c07s03b01x00p07n02i02372"
+      severity NOTE;
+    assert ((S1'LEFT = 0) and (S1(0) = '1') and (S1'RIGHT = 8) and (S1(8) = '0')) 
+      report "***FAILED TEST: c07s03b01x00p07n02i02372 - Failure in string literal direction test."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b01x00p07n02i02372arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2373.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2373.vhd
new file mode 100644
index 0000000..fe5703b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2373.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2373.vhd,v 1.1.1.1 2001-08-22 18:20:51 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b01x00p08n01i02373ent IS
+END c07s03b01x00p08n01i02373ent;
+
+ARCHITECTURE c07s03b01x00p08n01i02373arch OF c07s03b01x00p08n01i02373ent IS
+
+BEGIN
+   TESTING: PROCESS
+                        -- Redefine the type CHARACTER.
+                        type NEW_CHAR is (
+                            NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
+                            BS,  HT,  LF,  VT,  FF,  CR,  SO,  SI,
+                            DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
+                            CAN, EM,  SUB, ESC, FSP, GSP, RSP, USP,
+
+                            ' ', '!', '"', '#', '$', '%', '&', ''',
+                            '(', ')', '*', '+', ',', '-', '.', '/',
+                            '2', '3', '4', '5', '6', '7',
+                            '8', '9', ':', ';', '<', '=', '>', '?',
+
+                            '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
+                            'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
+                            'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
+                            'X', 'Y', 'Z', '[', '\', ']', '^', '_' );
+
+                       -- Local declarations.
+                       variable S : STRING( 1 to 12 );
+                       variable B : BIT_VECTOR( 1 to 2 );
+   BEGIN
+                       -- Should be OK,  non-overloaded literals.
+                       S := "hello, world";
+                       B := B"11";
+         wait for 5 ns;
+   assert NOT(    S = "hello, world"   and
+          B = B"11"      )
+      report "***PASSED TEST: c07s03b01x00p08n01i02373"
+      severity NOTE;
+   assert (    S = "hello, world"   and
+          B = B"11"      )
+      report "***FAILED TEST: c07s03b01x00p08n01i02373 - The graphic characters contained within a string literal should be visible."
+      severity ERROR;
+   wait;
+   END PROCESS TESTING;
+
+END c07s03b01x00p08n01i02373arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2374.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2374.vhd
new file mode 100644
index 0000000..2430a73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2374.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2374.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p02n01i02374ent IS
+END c07s03b02x00p02n01i02374ent;
+
+ARCHITECTURE c07s03b02x00p02n01i02374arch OF c07s03b02x00p02n01i02374ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       x1 is array (1 to 2) of integer;
+    constant    v1 :  x1 := (0, 0);   -- Success_here
+  BEGIN
+    assert NOT(v1(1)=0 and v1(2)=0)
+      report "***PASSED TEST: c07s03b02x00p02n01i02374"
+      severity NOTE;
+    assert (v1(1)=0 and v1(2)=0)
+      report "***FAILED TEST: c07s03b02x00p02n01i02374 - The aggregate consists of one or more element associations seperated with commas(,) which are enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p02n01i02374arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2378.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2378.vhd
new file mode 100644
index 0000000..66969a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2378.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2378.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p03n01i02378ent IS
+END c07s03b02x00p03n01i02378ent;
+
+ARCHITECTURE c07s03b02x00p03n01i02378arch OF c07s03b02x00p03n01i02378ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type x1 is array (1 to 2) of integer;
+    constant v1: x1 := (1 => 0, 2 => 0);   -- Success_here
+  BEGIN
+    assert NOT(v1(1)=0 and v1(2)=0)
+      report "***PASSED TEST: c07s03b02x00p03n01i02378"
+      severity NOTE;
+    assert (v1(1)=0 and v1(2)=0)
+      report "***FAILED TEST: c07s03b02x00p03n01i02378 - The element association consists of (optionally) choices followed by an arrow operator (=>) and an expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p03n01i02378arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2380.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2380.vhd
new file mode 100644
index 0000000..9df473a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2380.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2380.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p04n01i02380ent IS
+END c07s03b02x00p04n01i02380ent;
+
+ARCHITECTURE c07s03b02x00p04n01i02380arch OF c07s03b02x00p04n01i02380ent IS
+  type T1 is array (1 to 5) of integer;
+  constant C1 : T1 := (1|2 => 0, others => 4) ; -- No_Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(C1(1)=0 and C1(2)=0 and C1(3)=4 and C1(4)=4 and C1(5)=4)
+      report "***PASSED TEST: c07s03b02x00p04n01i02380"
+      severity NOTE;
+    assert (C1(1)=0 and C1(2)=0 and C1(3)=4 and C1(4)=4 and C1(5)=4)
+      report "***FAILED TEST: c07s03b02x00p04n01i02380 - The choices must be one or more choices separated with vertical bars(|)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p04n01i02380arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2382.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2382.vhd
new file mode 100644
index 0000000..388748b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2382.vhd
@@ -0,0 +1,136 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2382.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p06n02i02382ent IS
+END c07s03b02x00p06n02i02382ent;
+
+ARCHITECTURE c07s03b02x00p06n02i02382arch OF c07s03b02x00p06n02i02382ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype    BYTE    is BIT_VECTOR( 0 to 7 );
+    type    NIBBLE    is ARRAY ( 3 downto 0 ) of BIT;
+
+    -- Declare array variables of these types.
+    variable BYTEV1 : BYTE;
+    variable BYTEV2 : BYTE;
+    variable NIBV1  : NIBBLE;
+    variable NIBV2  : NIBBLE;
+  BEGIN
+    -- Set their values with aggregates and check them.
+    -- 1. Ascending first.
+    BYTEV1 := BYTE'( 7 => '0', 6 | 5 | 4 | 3 | 2 | 1 | 0 => '1' );
+    assert( BYTEV1( 0 ) = '1' );
+    assert( BYTEV1( 1 ) = '1' );
+    assert( BYTEV1( 2 ) = '1' );
+    assert( BYTEV1( 3 ) = '1' );
+    assert( BYTEV1( 4 ) = '1' );
+    assert( BYTEV1( 5 ) = '1' );
+    assert( BYTEV1( 6 ) = '1' );
+    assert( BYTEV1( 7 ) = '0' );
+    BYTEV2 := BYTE'( 7 => '1', 0 | 3 | 2 | 4 | 1 | 5 | 6  => '0' );
+    assert( BYTEV2( 0 ) = '0' );
+    assert( BYTEV2( 1 ) = '0' );
+    assert( BYTEV2( 2 ) = '0' );
+    assert( BYTEV2( 3 ) = '0' );
+    assert( BYTEV2( 4 ) = '0' );
+    assert( BYTEV2( 5 ) = '0' );
+    assert( BYTEV2( 6 ) = '0' );
+    assert( BYTEV2( 7 ) = '1' );
+
+    -- 2. Descending next.
+    NIBV1 := NIBBLE'( 3 | 2 | 1 => '1', 0 downto 0 => '0' );
+    assert( NIBV1( 3 ) = '1' );
+    assert( NIBV1( 2 ) = '1' );
+    assert( NIBV1( 1 ) = '1' );
+    assert( NIBV1( 0 ) = '0' );
+    NIBV2 := NIBBLE'( 2 | 3 => '0', 0 downto 0 | 1 => '1' );
+    assert( NIBV2( 3 ) = '0' );
+    assert( NIBV2( 2 ) = '0' );
+    assert( NIBV2( 1 ) = '1' );
+    assert( NIBV2( 0 ) = '1' );
+    wait for 5 ns;
+    assert NOT(    ( BYTEV1( 0 ) = '1' )   and
+                   ( BYTEV1( 1 ) = '1' )   and
+                   ( BYTEV1( 2 ) = '1' )   and
+                   ( BYTEV1( 3 ) = '1' )   and
+                   ( BYTEV1( 4 ) = '1' )   and
+                   ( BYTEV1( 5 ) = '1' )   and
+                   ( BYTEV1( 6 ) = '1' )   and
+                   ( BYTEV1( 7 ) = '0' )   and
+                   ( BYTEV2( 0 ) = '0' )   and 
+                   ( BYTEV2( 1 ) = '0' )   and
+                   ( BYTEV2( 2 ) = '0' )   and
+                   ( BYTEV2( 3 ) = '0' )   and
+                   ( BYTEV2( 4 ) = '0' )   and
+                   ( BYTEV2( 5 ) = '0' )   and
+                   ( BYTEV2( 6 ) = '0' )   and
+                   ( BYTEV2( 7 ) = '1' )   and
+                   ( NIBV1( 3 ) = '1' )   and 
+                   ( NIBV1( 2 ) = '1' )   and
+                   ( NIBV1( 1 ) = '1' )   and
+                   ( NIBV1( 0 ) = '0' )   and
+                   ( NIBV2( 3 ) = '0' )   and
+                   ( NIBV2( 2 ) = '0' )   and
+                   ( NIBV2( 1 ) = '1' )   and
+                   ( NIBV2( 0 ) = '1' )   )
+      report "***PASSED TEST: c07s03b02x00p06n02i02382"
+      severity NOTE;
+    assert (    ( BYTEV1( 0 ) = '1' )   and
+                ( BYTEV1( 1 ) = '1' )   and
+                ( BYTEV1( 2 ) = '1' )   and
+                ( BYTEV1( 3 ) = '1' )   and
+                ( BYTEV1( 4 ) = '1' )   and
+                ( BYTEV1( 5 ) = '1' )   and
+                ( BYTEV1( 6 ) = '1' )   and
+                ( BYTEV1( 7 ) = '0' )   and
+                ( BYTEV2( 0 ) = '0' )   and 
+                ( BYTEV2( 1 ) = '0' )   and
+                ( BYTEV2( 2 ) = '0' )   and
+                ( BYTEV2( 3 ) = '0' )   and
+                ( BYTEV2( 4 ) = '0' )   and
+                ( BYTEV2( 5 ) = '0' )   and
+                ( BYTEV2( 6 ) = '0' )   and
+                ( BYTEV2( 7 ) = '1' )   and
+                ( NIBV1( 3 ) = '1' )   and 
+                ( NIBV1( 2 ) = '1' )   and
+                ( NIBV1( 1 ) = '1' )   and
+                ( NIBV1( 0 ) = '0' )   and
+                ( NIBV2( 3 ) = '0' )   and
+                ( NIBV2( 2 ) = '0' )   and
+                ( NIBV2( 1 ) = '1' )   and
+                ( NIBV2( 0 ) = '1' )   )
+      report "***FAILED TEST: c07s03b02x00p06n02i02382 - Named association assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p06n02i02382arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2383.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2383.vhd
new file mode 100644
index 0000000..0d5e116
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2383.vhd
@@ -0,0 +1,136 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2383.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p06n02i02383ent IS
+END c07s03b02x00p06n02i02383ent;
+
+ARCHITECTURE c07s03b02x00p06n02i02383arch OF c07s03b02x00p06n02i02383ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype    BYTE    is BIT_VECTOR( 0 to 7 );
+    type    NIBBLE    is ARRAY ( 3 downto 0 ) of BIT;
+
+    -- Declare array variables of these types.
+    variable BYTEV1 : BYTE;
+    variable BYTEV2 : BYTE;
+    variable NIBV1  : NIBBLE;
+    variable NIBV2  : NIBBLE;
+  BEGIN
+    -- Set their values with aggregates and check them.
+    -- 1. Ascending first.
+    BYTEV1 := BYTE'( 7 => '0', others => '1' );
+    assert( BYTEV1( 0 ) = '1' );
+    assert( BYTEV1( 1 ) = '1' );
+    assert( BYTEV1( 2 ) = '1' );
+    assert( BYTEV1( 3 ) = '1' );
+    assert( BYTEV1( 4 ) = '1' );
+    assert( BYTEV1( 5 ) = '1' );
+    assert( BYTEV1( 6 ) = '1' );
+    assert( BYTEV1( 7 ) = '0' );
+    BYTEV2 := BYTE'( 7 => '1', 0 to 6 => '0' );
+    assert( BYTEV2( 0 ) = '0' );
+    assert( BYTEV2( 1 ) = '0' );
+    assert( BYTEV2( 2 ) = '0' );
+    assert( BYTEV2( 3 ) = '0' );
+    assert( BYTEV2( 4 ) = '0' );
+    assert( BYTEV2( 5 ) = '0' );
+    assert( BYTEV2( 6 ) = '0' );
+    assert( BYTEV2( 7 ) = '1' );
+
+    -- 2. Descending next.
+    NIBV1 := NIBBLE'( 3 downto 1 => '1', 0 downto 0 => '0' );
+    assert( NIBV1( 3 ) = '1' );
+    assert( NIBV1( 2 ) = '1' );
+    assert( NIBV1( 1 ) = '1' );
+    assert( NIBV1( 0 ) = '0' );
+    NIBV2 := NIBBLE'( 1 to 3 => '0', 0 downto 0 => '1' );
+    assert( NIBV2( 3 ) = '0' );
+    assert( NIBV2( 2 ) = '0' );
+    assert( NIBV2( 1 ) = '0' );
+    assert( NIBV2( 0 ) = '1' );
+    wait for 5 ns;
+    assert NOT(    ( BYTEV1( 0 ) = '1' )   and
+                   ( BYTEV1( 1 ) = '1' )   and
+                   ( BYTEV1( 2 ) = '1' )   and
+                   ( BYTEV1( 3 ) = '1' )   and
+                   ( BYTEV1( 4 ) = '1' )   and
+                   ( BYTEV1( 5 ) = '1' )   and
+                   ( BYTEV1( 6 ) = '1' )   and
+                   ( BYTEV1( 7 ) = '0' )   and
+                   ( BYTEV2( 0 ) = '0' )   and 
+                   ( BYTEV2( 1 ) = '0' )   and
+                   ( BYTEV2( 2 ) = '0' )   and
+                   ( BYTEV2( 3 ) = '0' )   and
+                   ( BYTEV2( 4 ) = '0' )   and
+                   ( BYTEV2( 5 ) = '0' )   and
+                   ( BYTEV2( 6 ) = '0' )   and
+                   ( BYTEV2( 7 ) = '1' )   and
+                   ( NIBV1( 3 ) = '1' )   and 
+                   ( NIBV1( 2 ) = '1' )   and
+                   ( NIBV1( 1 ) = '1' )   and
+                   ( NIBV1( 0 ) = '0' )   and
+                   ( NIBV2( 3 ) = '0' )   and
+                   ( NIBV2( 2 ) = '0' )   and
+                   ( NIBV2( 1 ) = '0' )   and
+                   ( NIBV2( 0 ) = '1' )   )
+      report "***PASSED TEST: c07s03b02x00p06n02i02383"
+      severity NOTE;
+    assert (    ( BYTEV1( 0 ) = '1' )   and
+                ( BYTEV1( 1 ) = '1' )   and
+                ( BYTEV1( 2 ) = '1' )   and
+                ( BYTEV1( 3 ) = '1' )   and
+                ( BYTEV1( 4 ) = '1' )   and
+                ( BYTEV1( 5 ) = '1' )   and
+                ( BYTEV1( 6 ) = '1' )   and
+                ( BYTEV1( 7 ) = '0' )   and
+                ( BYTEV2( 0 ) = '0' )   and 
+                ( BYTEV2( 1 ) = '0' )   and
+                ( BYTEV2( 2 ) = '0' )   and
+                ( BYTEV2( 3 ) = '0' )   and
+                ( BYTEV2( 4 ) = '0' )   and
+                ( BYTEV2( 5 ) = '0' )   and
+                ( BYTEV2( 6 ) = '0' )   and
+                ( BYTEV2( 7 ) = '1' )   and
+                ( NIBV1( 3 ) = '1' )   and 
+                ( NIBV1( 2 ) = '1' )   and
+                ( NIBV1( 1 ) = '1' )   and
+                ( NIBV1( 0 ) = '0' )   and
+                ( NIBV2( 3 ) = '0' )   and
+                ( NIBV2( 2 ) = '0' )   and
+                ( NIBV2( 1 ) = '0' )   and
+                ( NIBV2( 0 ) = '1' )   )
+      report "***FAILED TEST: c07s03b02x00p06n02i02383 - Named association assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p06n02i02383arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2384.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2384.vhd
new file mode 100644
index 0000000..5a979a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2384.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2384.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p06n03i02384ent IS
+END c07s03b02x00p06n03i02384ent;
+
+ARCHITECTURE c07s03b02x00p06n03i02384arch OF c07s03b02x00p06n03i02384ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype BYTE is BIT_VECTOR( 0 to 7 );
+    type NIBBLE is ARRAY ( 3 downto 0 ) of BIT;
+
+    -- Declare array variables of these types.
+    variable BYTEV : BYTE;
+    variable NIBV  : NIBBLE;
+  BEGIN
+    -- Verify that they were initialized properly.
+    for I in 0 to 7 loop
+      assert( BYTEV( I ) = '0' );
+    end loop;
+    for I in 3 downto 0 loop
+      assert( NIBV( I ) = '0' );
+    end loop;
+
+    -- Set their values with aggregates and check them.
+    -- 1. Ascending first.
+    BYTEV := BYTE'( '1','1','1','1','1','1','1','0' );
+    assert( BYTEV( 0 ) = '1' );
+    assert( BYTEV( 1 ) = '1' );
+    assert( BYTEV( 2 ) = '1' );
+    assert( BYTEV( 3 ) = '1' );
+    assert( BYTEV( 4 ) = '1' );
+    assert( BYTEV( 5 ) = '1' );
+    assert( BYTEV( 6 ) = '1' );
+    assert( BYTEV( 7 ) = '0' );
+
+    -- 2. Descending next.
+    NIBV := NIBBLE'( '1','1','1','0' );
+    assert( NIBV( 1 ) = '1' );
+    assert( NIBV( 2 ) = '1' );
+    assert( NIBV( 3 ) = '1' );
+    assert( NIBV( 0 ) = '0' );
+    wait for 5 ns;
+    assert NOT(    ( BYTEV( 0 ) = '1' )   and 
+                   ( BYTEV( 1 ) = '1' )   and
+                   ( BYTEV( 2 ) = '1' )   and
+                   ( BYTEV( 3 ) = '1' )   and
+                   ( BYTEV( 4 ) = '1' )   and
+                   ( BYTEV( 5 ) = '1' )   and
+                   ( BYTEV( 6 ) = '1' )   and
+                   ( BYTEV( 7 ) = '0' )   and
+                   ( NIBV( 1 ) = '1' )   and 
+                   ( NIBV( 2 ) = '1' )   and
+                   ( NIBV( 3 ) = '1' )   and
+                   ( NIBV( 0 ) = '0' )   )
+      report "***PASSED TEST: c07s03b02x00p06n03i02384"
+      severity NOTE;
+    assert (    ( BYTEV( 0 ) = '1' )   and 
+                ( BYTEV( 1 ) = '1' )   and
+                ( BYTEV( 2 ) = '1' )   and
+                ( BYTEV( 3 ) = '1' )   and
+                ( BYTEV( 4 ) = '1' )   and
+                ( BYTEV( 5 ) = '1' )   and
+                ( BYTEV( 6 ) = '1' )   and
+                ( BYTEV( 7 ) = '0' )   and
+                ( NIBV( 1 ) = '1' )   and 
+                ( NIBV( 2 ) = '1' )   and
+                ( NIBV( 3 ) = '1' )   and
+                ( NIBV( 0 ) = '0' )   )
+      report "***FAILED TEST: c07s03b02x00p06n03i02384 - Element positional association test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p06n03i02384arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2387.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2387.vhd
new file mode 100644
index 0000000..767e225
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2387.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2387.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02387ent IS
+END c07s03b02x00p07n01i02387ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02387arch OF c07s03b02x00p07n01i02387ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2 : BOOLEAN;
+                      end record;
+  signal S2 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= ( FALSE, E2 => TRUE);
+    -- positional and named associations are legal.
+    wait for 1 ns;
+    assert NOT(S2.E1=FALSE and S2.E2=TRUE) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02387" 
+      severity NOTE;
+    assert (S2.E1=FALSE and S2.E2=TRUE) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02387 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02387arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2388.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2388.vhd
new file mode 100644
index 0000000..a9fbbfc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2388.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2388.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02388ent IS
+END c07s03b02x00p07n01i02388ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02388arch OF c07s03b02x00p07n01i02388ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2 : BOOLEAN;
+                      end record;
+  signal S2 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= ( TRUE, TRUE);
+    -- positional and named associations are legal.
+    wait for 1 ns;
+    assert NOT(S2.E1=TRUE and S2.E2=TRUE) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02388" 
+      severity NOTE;
+    assert (S2.E1=TRUE and S2.E2=TRUE) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02388 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02388arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2389.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2389.vhd
new file mode 100644
index 0000000..d7ebbaf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2389.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2389.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02389ent IS
+END c07s03b02x00p07n01i02389ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02389arch OF c07s03b02x00p07n01i02389ent IS
+  type RECORD_TYPE is record
+                        E1,E2 : BOOLEAN;
+                      end record;
+  signal S2 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= ( E1=>TRUE, E2=>TRUE);
+    -- positional and named associations are legal.
+    wait for 1 ns;
+    assert NOT(S2.E1=TRUE and S2.E2=TRUE) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02389"
+      severity NOTE;
+    assert (S2.E1=TRUE and S2.E2=TRUE) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02389 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02389arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc239.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc239.vhd
new file mode 100644
index 0000000..34dc4b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc239.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc239.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00239ent IS
+END c03s01b02x00p04n01i00239ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00239arch OF c03s01b02x00p04n01i00239ent IS
+  type t3 is range (((((10-1)-1)-1)-1)-1) to (((((10+1)+1)+1)+1)+1); 
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 6;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p04n01i00239" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p04n01i00239 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00239arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2390.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2390.vhd
new file mode 100644
index 0000000..e01aad7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2390.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2390.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02390ent IS
+END c07s03b02x00p07n01i02390ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02390arch OF c07s03b02x00p07n01i02390ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2 : BOOLEAN;
+                      end record;
+  signal S2 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= ( E1=>TRUE, E2=>TRUE);
+    -- positional and named associations are legal.
+    wait for 1 ns;
+    assert NOT(S2.E1=TRUE and S2.E2=TRUE) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02390" 
+      severity NOTE;
+    assert (S2.E1=TRUE and S2.E2=TRUE) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02390 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02390arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2391.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2391.vhd
new file mode 100644
index 0000000..600e531
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2391.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2391.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02391ent IS
+END c07s03b02x00p07n01i02391ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02391arch OF c07s03b02x00p07n01i02391ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2,E3,E4,E5 : BOOLEAN;
+                      end record;
+  signal S3 : ARRAY_TYPE(1 to 5);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S3 <= ( 5 => TRUE, 4|2 downto 1 => TRUE, 3 => TRUE);
+    -- named associations may appear in any order.
+    wait for 1 ns;
+    assert NOT(S3(1)=TRUE and S3(2)=TRUE and S3(3)=TRUE and S3(4)=TRUE and S3(5)=TRUE) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02391" 
+      severity NOTE;
+    assert (S3(1)=TRUE and S3(2)=TRUE and S3(3)=TRUE and S3(4)=TRUE and S3(5)=TRUE) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02391 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02391arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2392.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2392.vhd
new file mode 100644
index 0000000..b8d5d94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2392.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2392.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02392ent IS
+END c07s03b02x00p07n01i02392ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02392arch OF c07s03b02x00p07n01i02392ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2,E3,E4,E5 : BOOLEAN;
+                      end record;
+  signal S4 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S4 <= ( E5 => TRUE, E4|E2|E1 => TRUE, E3 => TRUE);
+    -- named associations may appear in any order.
+    wait for 1 ns;
+    assert NOT((S4.E1=TRUE) and (S4.E2=TRUE) and (S4.E3=TRUE) and (S4.E4=TRUE) and (S4.E5=TRUE)) 
+      report "***PASSED TEST: c07s03b02x00p07n01i02392" 
+      severity NOTE;
+    assert ((S4.E1=TRUE) and (S4.E2=TRUE) and (S4.E3=TRUE) and (S4.E4=TRUE) and (S4.E5=TRUE)) 
+      report "***FAILED TEST: c07s03b02x00p07n01i02392 - Both named and positional associations can be used in the same aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02392arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2394.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2394.vhd
new file mode 100644
index 0000000..2eb7b0c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2394.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2394.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n02i02394ent IS
+END c07s03b02x00p07n02i02394ent;
+
+ARCHITECTURE c07s03b02x00p07n02i02394arch OF c07s03b02x00p07n02i02394ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type t26 is record
+                  elem_1: integer;
+                end record;
+    variable v26 : t26;
+  BEGIN
+    v26 := (elem_1 => 26);
+    assert NOT(v26.elem_1=26) 
+      report "***PASSED TEST: c07s03b02x00p07n02i02394"
+      severity NOTE;
+    assert (v26.elem_1=26) 
+      report "***FAILED TEST: c07s03b02x00p07n02i02394 - Aggregate specification should be using named association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n02i02394arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2395.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2395.vhd
new file mode 100644
index 0000000..fcbcdaf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2395.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2395.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n02i02395ent IS
+END c07s03b02x00p07n02i02395ent;
+
+ARCHITECTURE c07s03b02x00p07n02i02395arch OF c07s03b02x00p07n02i02395ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype ONE is BIT_VECTOR( 0 to 0);
+
+    -- Declare array variables of these types.
+    variable ONEV1 : ONE;
+    variable ONEV2 : ONE;
+  BEGIN
+    ONEV1 := ONE'( 0 => '0' );
+    assert( ONEV1( 0 ) = '0' );
+    ONEV2 := ONE'( 0 => '1' );
+    assert( ONEV2( 0 ) = '1' );
+    assert NOT(( ONEV1( 0 ) = '0' )   and ( ONEV2( 0 ) = '1' ))
+      report "***PASSED TEST: c07s03b02x00p07n02i02395" 
+      severity NOTE;
+    assert (( ONEV1( 0 ) = '0' )   and ( ONEV2( 0 ) = '1' ))
+      report "***FAILED TEST: c07s03b02x00p07n02i02395 - Aggregate specification should be using named association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n02i02395arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2396.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2396.vhd
new file mode 100644
index 0000000..96ddff3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2396.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2396.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02396ent IS
+END c07s03b02x00p07n01i02396ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02396arch OF c07s03b02x00p07n01i02396ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype BYTE is BIT_VECTOR( 0 to 7 );
+
+    -- Declare array variables of these types.
+    variable BYTEV : BYTE;
+  BEGIN
+    BYTEV := BYTE'( 7 => '0', 6 => '1', 4 => '1',
+                    2 => '1', 0 => '1', 5 => '0',
+                    3 => '0', 1 => '0' );
+    assert( BYTEV( 1 ) = '0' );
+    assert( BYTEV( 3 ) = '0' );
+    assert( BYTEV( 5 ) = '0' );
+    assert( BYTEV( 7 ) = '0' );
+    assert( BYTEV( 0 ) = '1' );
+    assert( BYTEV( 2 ) = '1' );
+    assert( BYTEV( 4 ) = '1' );
+    assert( BYTEV( 6 ) = '1' );
+    wait for 1 ns;
+    assert NOT(   ( BYTEV( 1 ) = '0' )   and 
+                  ( BYTEV( 3 ) = '0' )   and 
+                  ( BYTEV( 5 ) = '0' )   and 
+                  ( BYTEV( 7 ) = '0' )   and 
+                  ( BYTEV( 0 ) = '1' )   and 
+                  ( BYTEV( 2 ) = '1' )   and 
+                  ( BYTEV( 4 ) = '1' )   and 
+                  ( BYTEV( 6 ) = '1' ))
+      report "***PASSED TEST: c07s03b02x00p07n01i02396" 
+      severity NOTE;
+    assert (   ( BYTEV( 1 ) = '0' )   and 
+               ( BYTEV( 3 ) = '0' )   and 
+               ( BYTEV( 5 ) = '0' )   and 
+               ( BYTEV( 7 ) = '0' )   and 
+               ( BYTEV( 0 ) = '1' )   and 
+               ( BYTEV( 2 ) = '1' )   and 
+               ( BYTEV( 4 ) = '1' )   and 
+               ( BYTEV( 6 ) = '1' ))
+      report "***FAILED TEST: c07s03b02x00p07n01i02396 - Named association should be able to appear in any order."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02396arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2399.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2399.vhd
new file mode 100644
index 0000000..991b85a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2399.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2399.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n01i02399ent IS
+END c07s03b02x00p08n01i02399ent;
+
+ARCHITECTURE c07s03b02x00p08n01i02399arch OF c07s03b02x00p08n01i02399ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_2 : real;
+                  ele_3 : boolean;
+                end record;
+    variable v23 : rec;
+  BEGIN
+    v23 := (ele_2 => 2.3, ele_3 => True); -- No_failure_here
+    assert NOT((v23.ele_2=2.3) and (v23.ele_3=TRUE)) 
+      report "***PASSED TEST: c07s03b02x00p08n01i02399" 
+      severity NOTE;
+    assert ((v23.ele_2=2.3) and (v23.ele_3=TRUE)) 
+      report "***FAILED TEST: c07s03b02x00p08n01i02399 - Element associations by an element simple name is allowed only in record aggregates."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n01i02399arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc24.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc24.vhd
new file mode 100644
index 0000000..ddbe215
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc24.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc24.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p10n01i00024ent IS
+END c04s02b00x00p10n01i00024ent;
+
+ARCHITECTURE c04s02b00x00p10n01i00024arch OF c04s02b00x00p10n01i00024ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    -- Define an ascending subtype.
+    subtype ASC is INTEGER range 0 to 1;
+
+    -- Define a descending subtype.
+    subtype DES is INTEGER range 1 to 0;
+
+    -- Define a 'previous value' variable.
+    variable PREV : INTEGER;
+
+    variable k : integer := 0;
+    variable l : integer := 0;
+  BEGIN
+    -- Test the direction of the ascending range.
+    PREV := -1;
+    for I in ASC loop
+      if (I > PREV) then
+        PREV := I;
+      else
+        k := 1;
+      end if;
+    end loop;
+
+    -- Test the direction of the descending range.
+    PREV := 2;
+    for I in DES loop
+      if (I < PREV) then
+        PREV := I;
+      else
+        l := 1;
+      end if;
+    end loop;
+    assert NOT( k=0 and l=0 )
+      report "***PASSED TEST:c04s02b00x00p10n01i00024"
+      severity NOTE;
+    assert ( k=0 and l=0 )
+      report "***FAILED TEST: c04s02b00x00p10n01i00024 - The direction of a discrete subtype indication is the same as the direction of the range constraint that appears as the constraint of the subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p10n01i00024arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2400.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2400.vhd
new file mode 100644
index 0000000..de9f1b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2400.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2400.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n02i02400ent IS
+END c07s03b02x00p08n02i02400ent;
+
+ARCHITECTURE c07s03b02x00p08n02i02400arch OF c07s03b02x00p08n02i02400ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type t18 is array (1 to 5) of integer;
+    variable v18 : t18;
+  BEGIN
+    v18 := (1 to 2 => 18, others => 0);  -- discrete range in an
+                                         -- array aggregate allowed.
+    assert NOT(v18(1)=18 and v18(2)=18 and v18(3)=0 and v18(4)=0 and v18(5)=0)
+      report "***PASSED TEST: c07s03b02x00p08n02i02400"
+      severity NOTE;
+    assert (v18(1)=18 and v18(2)=18 and v18(3)=0 and v18(4)=0 and v18(5)=0)
+      report "***FAILED TEST: c07s03b02x00p08n02i02400 - An element association with a choice that is a discrete range is allowed in an array aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n02i02400arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2401.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2401.vhd
new file mode 100644
index 0000000..c3c1545
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2401.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2401.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n02i02401ent IS
+END c07s03b02x00p08n02i02401ent;
+
+ARCHITECTURE c07s03b02x00p08n02i02401arch OF c07s03b02x00p08n02i02401ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type t18 is array (1 to 5) of integer;
+    variable v18 : t18;
+  BEGIN
+    v18 := (1+ 2 => 18, others => 0);  -- discrete range in an
+                                           -- array aggregate allowed.
+    assert NOT(v18(1)=0 and v18(2)=0 and v18(3)=18 and v18(4)=0 and v18(5)=0)
+      report "***PASSED TEST: c07s03b02x00p08n02i02401"
+      severity NOTE;
+    assert (v18(1)=0 and v18(2)=0 and v18(3)=18 and v18(4)=0 and v18(5)=0)
+      report "***FAILED TEST: c07s03b02x00p08n02i02401 - An element association with a choice that is a discrete range is allowed in an array aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n02i02401arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2403.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2403.vhd
new file mode 100644
index 0000000..787aff9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2403.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2403.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n05i02403ent IS
+END c07s03b02x00p08n05i02403ent;
+
+ARCHITECTURE c07s03b02x00p08n05i02403arch OF c07s03b02x00p08n05i02403ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  a: integer;
+                  b: integer;
+                  c: integer;
+                  d: integer;
+                end record;
+    constant y: rec := (a => 12, others => 10);
+  BEGIN
+    assert NOT(y.a=12 and y.b=10 and y.c=10 and y.d=10)
+      report "***PASSED TEST: c07s03b02x00p08n05i02403"
+      severity NOTE;
+    assert (y.a=12 and y.b=10 and y.c=10 and y.d=10)
+      report "***FAILED TEST: c07s03b02x00p08n05i02403 - The element association with the choice others is allowed in a record aggregate and if it specifies all the remaining element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n05i02403arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2404.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2404.vhd
new file mode 100644
index 0000000..59f8878
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2404.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2404.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n05i02404ent IS
+END c07s03b02x00p08n05i02404ent;
+
+ARCHITECTURE c07s03b02x00p08n05i02404arch OF c07s03b02x00p08n05i02404ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type arr is array (1 to 3) of integer;
+    constant y: arr := (1 => 12, others => 0);
+  BEGIN
+    assert NOT(y(1)=12 and y(2)=0 and y(3)=0)
+      report "***PASSED TEST: c07s03b02x00p08n05i02404"
+      severity NOTE;
+    assert (y(1)=12 and y(2)=0 and y(3)=0)
+      report "***FAILED TEST: c07s03b02x00p08n05i02404 - The element association with the choice others is allowed in a record aggregate and if it specifies all the remaining element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n05i02404arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2408.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2408.vhd
new file mode 100644
index 0000000..1e0b0d7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2408.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2408.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n05i02408ent IS
+END c07s03b02x00p08n05i02408ent;
+
+ARCHITECTURE c07s03b02x00p08n05i02408arch OF c07s03b02x00p08n05i02408ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare ascending and descending ranges.
+    subtype BYTE is BIT_VECTOR( 0 to 7 );
+
+    -- Declare array variables of these types.
+    variable BYTEV1 : BYTE;
+    variable BYTEV2 : BYTE;
+  BEGIN
+    BYTEV1 := BYTE'( others => '1' );
+    assert( BYTEV1( 0 ) = '1' );
+    assert( BYTEV1( 1 ) = '1' );
+    assert( BYTEV1( 2 ) = '1' );
+    assert( BYTEV1( 3 ) = '1' );
+    assert( BYTEV1( 4 ) = '1' );
+    assert( BYTEV1( 5 ) = '1' );
+    assert( BYTEV1( 6 ) = '1' );
+    assert( BYTEV1( 7 ) = '1' );
+    BYTEV2 := BYTE'( others => '0' );
+    assert( BYTEV2( 0 ) = '0' );
+    assert( BYTEV2( 1 ) = '0' );
+    assert( BYTEV2( 2 ) = '0' );
+    assert( BYTEV2( 3 ) = '0' );
+    assert( BYTEV2( 4 ) = '0' );
+    assert( BYTEV2( 5 ) = '0' );
+    assert( BYTEV2( 6 ) = '0' );
+    assert( BYTEV2( 7 ) = '0' );
+    wait for 5 ns;
+    assert NOT(   ( BYTEV1( 0 ) = '1' )   and
+                  ( BYTEV1( 1 ) = '1' )   and
+                  ( BYTEV1( 2 ) = '1' )   and
+                  ( BYTEV1( 3 ) = '1' )   and
+                  ( BYTEV1( 4 ) = '1' )   and
+                  ( BYTEV1( 5 ) = '1' )   and
+                  ( BYTEV1( 6 ) = '1' )   and
+                  ( BYTEV1( 7 ) = '1' )   and
+                  ( BYTEV2( 0 ) = '0' )   and
+                  ( BYTEV2( 1 ) = '0' )   and
+                  ( BYTEV2( 2 ) = '0' )   and
+                  ( BYTEV2( 3 ) = '0' )   and
+                  ( BYTEV2( 4 ) = '0' )   and
+                  ( BYTEV2( 5 ) = '0' )   and
+                  ( BYTEV2( 6 ) = '0' )   and
+                  ( BYTEV2( 7 ) = '0' )   ) 
+      report "***PASSED TEST: c07s03b02x00p08n05i02408" 
+      severity NOTE;
+    assert (   ( BYTEV1( 0 ) = '1' )   and
+               ( BYTEV1( 1 ) = '1' )   and
+               ( BYTEV1( 2 ) = '1' )   and
+               ( BYTEV1( 3 ) = '1' )   and
+               ( BYTEV1( 4 ) = '1' )   and
+               ( BYTEV1( 5 ) = '1' )   and
+               ( BYTEV1( 6 ) = '1' )   and
+               ( BYTEV1( 7 ) = '1' )   and
+               ( BYTEV2( 0 ) = '0' )   and
+               ( BYTEV2( 1 ) = '0' )   and
+               ( BYTEV2( 2 ) = '0' )   and
+               ( BYTEV2( 3 ) = '0' )   and
+               ( BYTEV2( 4 ) = '0' )   and
+               ( BYTEV2( 5 ) = '0' )   and
+               ( BYTEV2( 6 ) = '0' )   and
+               ( BYTEV2( 7 ) = '0' )   ) 
+      report "***FAILED TEST: c07s03b02x00p08n05i02408 - Others should work well by itself."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n05i02408arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc241.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc241.vhd
new file mode 100644
index 0000000..d38159a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc241.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc241.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00241ent IS
+END c03s01b02x00p04n01i00241ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00241arch OF c03s01b02x00p04n01i00241ent IS
+  type a is range boolean'pos(1=2) to boolean'pos(2=2);
+BEGIN
+  TESTING: PROCESS
+    variable k : a := 1;
+  BEGIN
+    k := 1;
+    assert NOT(k = 1) 
+      report "***PASSED TEST: c03s01b02x00p04n01i00241" 
+      severity NOTE;
+    assert (k = 1) 
+      report "***FAILED TEST: c03s01b02x00p04n01i00241 - The bounds in the range constraint are not locally static expressions of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00241arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2412.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2412.vhd
new file mode 100644
index 0000000..1938b1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2412.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2412.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p09n01i02412ent IS
+END c07s03b02x00p09n01i02412ent;
+
+ARCHITECTURE c07s03b02x00p09n01i02412arch OF c07s03b02x00p09n01i02412ent IS
+  type T1 is array (1 to 5) of integer;
+  constant C : T1 := (1 => 0, 2 => 2, 3 => 3, 4 =>4, others=> 4) ; -- No_Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4) 
+      report "***PASSED TEST: c07s03b02x00p09n01i02412" 
+      severity NOTE;
+    assert (C(1)=0 and C(2)=2 and C(3)=3 and C(4)=4 and C(5)=4) 
+      report "***FAILED TEST: c07s03b02x00p09n01i02412 - Each element of the value defined by an aggregate must be represented once and only once in the aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p09n01i02412arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2415.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2415.vhd
new file mode 100644
index 0000000..7382d61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2415.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2415.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p10n01i02415ent IS
+END c07s03b02x00p10n01i02415ent;
+
+ARCHITECTURE c07s03b02x00p10n01i02415arch OF c07s03b02x00p10n01i02415ent IS
+  type sigrec1 is
+    record
+      B1 : bit;
+      B2 : integer;
+      B3 : bit;
+    end record;
+  
+  signal S1 : bit;
+  signal S2 : integer;
+  signal S3 : bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (S1, S2, S3) <= sigrec1'('0', 2, '1');
+    wait for 1 ns;
+    assert NOT(S1='0' and S2=2 and S3='1')
+      report "***PASSED TEST: c07s03b02x00p10n01i02415" 
+      severity NOTE;
+    assert (S1='0' and S2=2 and S3='1')
+      report "***FAILED TEST: c07s03b02x00p10n01i02415 - Type of the aggregate must be determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p10n01i02415arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2417.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2417.vhd
new file mode 100644
index 0000000..8b9c52b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2417.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2417.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p10n02i02417ent IS
+END c07s03b02x00p10n02i02417ent;
+
+ARCHITECTURE c07s03b02x00p10n02i02417arch OF c07s03b02x00p10n02i02417ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : real;
+                  ele_3 : boolean;
+                  ele_4 : character;
+                  ele_5 : bit;
+                  ele_6 : time;
+                  ele_7 : severity_level;
+                end record;
+    variable v24 : rec;
+  BEGIN
+    v24 := (ele_1=>23,ele_2=>1.4,ele_3=>True,ele_4=>'C',ele_5=>'1',ele_6=>1 ns,ele_7=>error);      
+    assert NOT(   v24.ele_1 = 23      and
+                  v24.ele_2 = 1.4      and
+                  v24.ele_3 = True   and
+                  v24.ele_4 = 'C'      and
+                  v24.ele_5 = '1'      and
+                  v24.ele_6 = 1 ns   and
+                  v24.ele_7 = error   )
+      report "***PASSED TEST: c07s03b02x00p10n02i02417"
+      severity NOTE;
+    assert (   v24.ele_1 = 23      and
+               v24.ele_2 = 1.4      and
+               v24.ele_3 = True   and
+               v24.ele_4 = 'C'      and
+               v24.ele_5 = '1'      and
+               v24.ele_6 = 1 ns   and
+               v24.ele_7 = error   )
+      report "***FAILED TEST: c07s03b02x00p10n02i02417 - Elements of an aggregate should have the same type as that determined by the aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p10n02i02417arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2421.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2421.vhd
new file mode 100644
index 0000000..04c6858
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2421.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2421.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n01i02421ent IS
+END c07s03b02x01p01n01i02421ent;
+
+ARCHITECTURE c07s03b02x01p01n01i02421arch OF c07s03b02x01p01n01i02421ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  a: integer;
+                  b: real;
+                end record;
+    constant y: rec := (a => 12, b => 12.0);
+  BEGIN
+    assert NOT(y.a=12 and y.b=12.0) 
+      report "***PASSED TEST: c07s03b02x01p01n01i02421"
+      severity NOTE;
+    assert (y.a=12 and y.b=12.0) 
+      report "***FAILED TEST: c07s03b02x01p01n01i02421 - Element names must denote elments of the record type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n01i02421arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2425.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2425.vhd
new file mode 100644
index 0000000..103e460
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2425.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2425.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n02i02425ent IS
+END c07s03b02x01p01n02i02425ent;
+
+ARCHITECTURE c07s03b02x01p01n02i02425arch OF c07s03b02x01p01n02i02425ent IS
+  type rec is record
+                a: integer;
+                b: integer;
+                c: integer;
+                d: integer;
+              end record;
+  constant y: rec := (a => 12, others => 10); -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(y.a=12 and y.b=10 and y.c=10 and y.d=10) 
+      report "***PASSED TEST: c07s03b02x01p01n02i02425" 
+      severity NOTE;
+    assert (y.a=12 and y.b=10 and y.c=10 and y.d=10) 
+      report "***FAILED TEST: c07s03b02x01p01n02i02425 - If the choice others is given as a choice of a record aggregate, it must represent at least one element." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n02i02425arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2428.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2428.vhd
new file mode 100644
index 0000000..00e9c02
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2428.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2428.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n03i02428ent IS
+END c07s03b02x01p01n03i02428ent;
+
+ARCHITECTURE c07s03b02x01p01n03i02428arch OF c07s03b02x01p01n03i02428ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_1 : real;
+                  ele_2 : real;
+                end record;
+    constant p  :rec := (ele_1 | ele_2 => 4.5); -- No_failure_here
+  BEGIN
+    assert NOT(p.ele_1=4.5 and p.ele_2=4.5) 
+      report "***PASSED TEST: c07s03b02x01p01n03i02428" 
+      severity NOTE;
+    assert (p.ele_1=4.5 and p.ele_2=4.5) 
+      report "***FAILED TEST: c07s03b02x01p01n03i02428 - Element association with others choice should be used to represent elements of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n03i02428arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2430.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2430.vhd
new file mode 100644
index 0000000..d53fd45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2430.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2430.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n04i02430ent IS
+END c07s03b02x01p01n04i02430ent;
+
+ARCHITECTURE c07s03b02x01p01n04i02430arch OF c07s03b02x01p01n04i02430ent IS
+  type sigrec1 is
+    record
+      B1 : bit;
+      B2 : integer;
+      B3 : bit;
+    end record;
+  signal S1 : sigrec1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= (('0' and '1'), 2, '1');
+    wait for 1 ns;
+    assert NOT(S1.B1='0' and S1.B2=2 and S1.B3='1') 
+      report "***PASSED TEST: c07s03b02x01p01n04i02430" 
+      severity NOTE;
+    assert (S1.B1='0' and S1.B2=2 and S1.B3='1') 
+      report "***FAILED TEST: c07s03b02x01p01n04i02430 - Expression of an element association must have the same type as the associated record element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n04i02430arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2432.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2432.vhd
new file mode 100644
index 0000000..f1bcd82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2432.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2432.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02432ent IS
+END c07s03b02x02p01n01i02432ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02432arch OF c07s03b02x02p01n01i02432ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type arr is array (1 to 3) of integer;
+    variable x: arr;
+  BEGIN
+    x := (1 => 1, 2 => 12, 3 => 24);  -- No_failure_here
+    assert NOT(x(1)=1 and x(2)=12 and x(3)=24) 
+      report "***PASSED TEST: c07s03b02x02p01n01i02432" 
+      severity NOTE;
+    assert (x(1)=1 and x(2)=12 and x(3)=24) 
+      report "***FAILED TEST: c07s03b02x02p01n01i02432 - Expression of each element association must be of the element type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02432arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2435.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2435.vhd
new file mode 100644
index 0000000..3d10ee1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2435.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2435.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n02i02435ent IS
+END c07s03b02x02p01n02i02435ent;
+
+ARCHITECTURE c07s03b02x02p01n02i02435arch OF c07s03b02x02p01n02i02435ent IS
+  type m1 is array (1 to 3) of integer;
+  type m2 is array (1 to 2) of m1;
+  constant c: m2 := ((1, 1, 2), (1, 2, 3));  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(c(1)=(1,1,2) and c(2)=(1,2,3))
+      report "***PASSED TEST: c07s03b02x02p01n02i02435"
+      severity NOTE;
+    assert (c(1)=(1,1,2) and c(2)=(1,2,3))
+      report "***FAILED TEST: c07s03b02x02p01n02i02435 - Multidimensional aggregates are allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n02i02435arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2436.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2436.vhd
new file mode 100644
index 0000000..fca10db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2436.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2436.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n02i02436ent IS
+END c07s03b02x02p01n02i02436ent;
+
+ARCHITECTURE c07s03b02x02p01n02i02436arch OF c07s03b02x02p01n02i02436ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BIT_VECTOR is array
+      (natural range <>, positive range <>) of BIT; 
+    variable NUM1 : BIT_VECTOR(0 to 7, 1 to 2) := (
+      ('0', '0'), ('1', '1'),      
+      ('0', '1'), ('1', '1'),      
+      ('0', '1'), ('0', '1'),      
+      ('1', '0'), ('1', '0')       
+      );
+                                        -- No_failure_here   
+  BEGIN
+    assert NOT( NUM1 =(('0', '0'), ('1', '1'),      
+                       ('0', '1'), ('1', '1'),       
+                       ('0', '1'), ('0', '1'),       
+                       ('1', '0'), ('1', '0')))
+      report "***PASSED TEST: c07s03b02x02p01n02i02436"
+      severity NOTE;
+    assert    ( NUM1 =(('0', '0'), ('1', '1'),      
+                       ('0', '1'), ('1', '1'),       
+                       ('0', '1'), ('0', '1'),       
+                       ('1', '0'), ('1', '0')))
+      report "***FAILED TEST: c07s03b02x02p01n02i02436 - Multidimensional aggregates are allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n02i02436arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2439.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2439.vhd
new file mode 100644
index 0000000..ed47707
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2439.vhd
@@ -0,0 +1,193 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2439.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02439ent IS
+END c07s03b02x02p01n01i02439ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02439arch OF c07s03b02x02p01n01i02439ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Range types are all predefined enumerated types.
+    type CHAR_ARR    is ARRAY( CHARACTER )       of BIT;
+    type BIT_ARR    is ARRAY( BIT )       of BIT;
+    type BOOL_ARR    is ARRAY( BOOLEAN )       of BIT;
+    type SEV_ARR    is ARRAY( SEVERITY_LEVEL )    of BIT;
+
+    -- Declare variables of these types.
+    variable CHARV : CHAR_ARR;
+    variable BITV  : BIT_ARR;
+    variable BOOLV : BOOL_ARR;
+    variable SEVV  : SEV_ARR;
+    variable OKtest: integer := 0;
+  BEGIN
+    -- Assign each of these arrays using aggregates.
+    -- 1. Individual aggregates.
+    CHARV := CHAR_ARR'( 'a' => '1', 'b' => '0', NUL to '`' => '1',
+                        'c' to DEL => '1' );
+    for C in CHARACTER loop
+      if  (C = 'a') then
+        assert( CHARV( C ) = '1' );
+        if NOT( CHARV( C ) = '1' ) then
+          OKtest := 1;
+        end if;
+      elsif (C = 'b') then
+        assert( CHARV( C ) = '0' );
+        if NOT( CHARV( C ) = '0' ) then
+          OKtest := 1;
+        end if;
+      else
+        assert( CHARV( C ) = '1' );
+        if NOT( CHARV( C ) = '1' ) then
+          OKtest := 1;
+        end if;
+      end if;
+    end loop;
+    BITV  := BIT_ARR'( '0' => '0', '1' => '1' );
+    assert( BITV( '0' ) = '0' );
+    if NOT( BITV( '0' ) = '0' ) then
+      OKtest := 1;
+    end if;
+    assert( BITV( '1' ) = '1' );
+    if NOT( BITV( '1' ) = '1' ) then
+      OKtest := 1;
+    end if;
+    BOOLV  := BOOL_ARR'( FALSE => '0', TRUE => '1' );
+    assert( BOOLV( FALSE ) = '0' );
+    if NOT( BOOLV( FALSE ) = '0' ) then
+      OKtest := 1;
+    end if;
+    assert( BOOLV( TRUE ) = '1' );
+    if NOT( BOOLV( TRUE ) = '1' ) then
+      OKtest := 1;
+    end if;
+    SEVV  := SEV_ARR'( NOTE => '0', WARNING => '1', ERROR => '0',
+                       FAILURE => '1' );
+    assert( SEVV( NOTE ) = '0' );
+    assert( SEVV( WARNING ) = '1' );
+    assert( SEVV( ERROR ) = '0' );
+    assert( SEVV( FAILURE ) = '1' );
+    if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
+      OKtest := 1;
+    end if;
+    
+    -- 2. Groups of aggregates.
+    CHARV := CHAR_ARR'( 'a' | 'b' => '1', NUL to '`' => '0',
+                        'c' to DEL => '0' );
+    for C in CHARACTER loop
+      if  (C = 'a') then
+        assert( CHARV( C ) = '1' );
+        if NOT( CHARV( C ) = '1' ) then
+          OKtest := 1;
+        end if;
+      elsif (C = 'b') then
+        assert( CHARV( C ) = '1' );
+        if NOT( CHARV( C ) = '1' ) then
+          OKtest := 1;
+        end if;
+      else
+        assert( CHARV( C ) = '0' );
+        if NOT( CHARV( C ) = '0' ) then
+          OKtest := 1;
+        end if;
+      end if;
+    end loop;
+    BITV  := BIT_ARR'( '0' | '1' => '0' );
+    assert( BITV( '0' ) = '0' );
+    assert( BITV( '1' ) = '0' );
+    if NOT((BITV('0')='0') and (BITV('1')='0')) then
+      OKtest := 1;
+    end if;
+    BOOLV  := BOOL_ARR'( FALSE | TRUE => '1' );
+    assert( BOOLV( FALSE ) = '1' );
+    assert( BOOLV( TRUE ) = '1' );
+    if NOT((BOOLV(FALSE)='1') and (BOOLV(TRUE)='1')) then
+      OKtest := 1;
+    end if;
+    SEVV  := SEV_ARR'( NOTE | ERROR => '0', WARNING | FAILURE => '1' );
+    assert( SEVV( NOTE ) = '0' );
+    assert( SEVV( WARNING ) = '1' );
+    assert( SEVV( ERROR ) = '0' );
+    assert( SEVV( FAILURE ) = '1' );
+    if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
+      OKtest := 1;
+    end if;
+
+    -- 3. Use of 'others' in these aggregates.
+    CHARV := CHAR_ARR'( 'a' | 'b' => '0', others => '1' );
+    for C in CHARACTER loop
+      if  (C = 'a') then
+        assert( CHARV( C ) = '0' );
+        if NOT( CHARV( C ) = '0' ) then
+          OKtest := 1;
+        end if;
+      elsif (C = 'b') then
+        assert( CHARV( C ) = '0' );
+        if NOT( CHARV( C ) = '0' ) then
+          OKtest := 1;
+        end if;
+      else
+        assert( CHARV( C ) = '1' );
+        if NOT( CHARV( C ) = '1' ) then
+          OKtest := 1;
+        end if;
+      end if;
+    end loop;
+    BITV  := BIT_ARR'( others => '1' );
+    assert( BITV( '0' ) = '1' );
+    assert( BITV( '1' ) = '1' );
+    if NOT(( BITV( '0' ) = '1' )and( BITV( '1' ) = '1' ))then
+      OKtest := 1;
+    end if;
+    BOOLV  := BOOL_ARR'( FALSE => '1', others => '0' );
+    assert( BOOLV( FALSE ) = '1' );
+    assert( BOOLV( TRUE ) = '0' );
+    if NOT(( BOOLV( FALSE ) = '1' )and( BOOLV( TRUE ) = '0' ))then
+      OKtest := 1;
+    end if;
+    SEVV  := SEV_ARR'( NOTE | ERROR => '0', others => '1' );
+    assert( SEVV( NOTE ) = '0' );
+    assert( SEVV( WARNING ) = '1' );
+    assert( SEVV( ERROR ) = '0' );
+    assert( SEVV( FAILURE ) = '1' );
+    if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
+      OKtest := 1;
+    end if;
+    wait for 5 ns;
+    assert NOT(OKtest = 0) 
+      report "***PASSED TEST: c07s03b02x02p01n01i02439" 
+      severity NOTE;
+    assert (OKtest = 0) 
+      report "***FAILED TEST: c07s03b02x02p01n01i02439 - Aggregates with different range types test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02439arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2440.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2440.vhd
new file mode 100644
index 0000000..723d240
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2440.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2440.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02440ent IS
+END c07s03b02x02p01n01i02440ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02440arch OF c07s03b02x02p01n01i02440ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Range types are all predefined enumerated types.
+    type    CHAR_ARR    is ARRAY( CHARACTER range <> ) of BIT;
+    subtype    CHAR_PART    is CHAR_ARR( 'a' to 'z' );
+    subtype    CHAR_PART_DESC    is CHAR_ARR( 'z' downto 'a' );
+
+    type    BIT_ARR    is ARRAY( BIT range <> ) of BIT;
+    subtype    BIT_PART    is BIT_ARR( bit'('0') to bit'('0') );
+    subtype    BIT_PART_DESC    is BIT_ARR( bit'('1') downto bit'('0') );
+
+    type    BOOL_ARR    is ARRAY( BOOLEAN range <> ) of BIT;
+    subtype    BOOL_PART    is BOOL_ARR( TRUE to TRUE );
+    subtype    BOOL_PART_DESC    is BOOL_ARR( TRUE downto FALSE );
+
+    type    SEV_ARR    is ARRAY( SEVERITY_LEVEL range <> ) of BIT;
+    subtype    SEV_PART    is SEV_ARR( WARNING to FAILURE );
+    subtype    SEV_PART_DESC    is SEV_ARR( FAILURE downto WARNING );
+
+    -- Declare variables of these types.
+    variable CHARV : CHAR_PART;
+    variable BITV  : BIT_PART;
+    variable BOOLV : BOOL_PART;
+    variable SEVV  : SEV_PART;
+    variable OKtest: integer := 0;
+  BEGIN
+    -- Assign each of these arrays using aggregates.
+    -- 1. Individual aggregates.
+    CHARV := CHAR_PART'( 'a' => '1', 'b' => '0', 'c' to 'z' => '1' );                                    for C in 'a' to 'z' loop
+                                                                                                           if  (C = 'a') then
+                                                                                                             assert( CHARV( C ) = '1' );
+                                                                                                             if NOT( CHARV( C ) = '1' ) then
+                                                                                                               OKtest := 1;
+                                                                                                             end if;
+                                                                                                           elsif (C = 'b') then
+                                                                                                             assert( CHARV( C ) = '0' );
+                                                                                                             if NOT( CHARV( C ) = '0' ) then
+                                                                                                               OKtest := 1;
+                                                                                                             end if;
+                                                                                                           else
+                                                                                                             assert( CHARV( C ) = '1' );
+                                                                                                             if NOT( CHARV( C ) = '1' ) then
+                                                                                                               OKtest := 1;
+                                                                                                             end if;
+                                                                                                           end if;
+  end loop;
+  BITV  := BIT_PART'( '0' => '0' );
+  assert( BITV( '0' ) = '0' );
+  if NOT( BITV( '0' ) = '0' ) then
+    OKtest := 1;
+  end if;
+  BOOLV  := BOOL_PART'( TRUE => '1' );
+  assert( BOOLV( TRUE ) = '1' );
+  if NOT( BOOLV( TRUE ) = '1' ) then
+    OKtest := 1;
+  end if;
+  SEVV  := SEV_PART'( WARNING => '1', ERROR => '0',
+                      FAILURE => '1' );
+  assert( SEVV( WARNING ) = '1' );
+  assert( SEVV( ERROR ) = '0' );
+  assert( SEVV( FAILURE ) = '1' );
+  if NOT((SEVV(WARNING)='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1'))then
+    OKtest := 1;
+  end if;
+  
+  -- 2. Groups of aggregates.
+  CHARV := CHAR_PART'( 'a' | 'b' => '1', 'c' to 'z' => '0' );
+  for C in 'a' to 'z' loop
+    if  (C = 'a') then
+      assert( CHARV( C ) = '1' );
+      if NOT( CHARV( C ) = '1' ) then
+        OKtest := 1;
+      end if;
+    elsif (C = 'b') then
+      assert( CHARV( C ) = '1' );
+      if NOT( CHARV( C ) = '1' ) then
+        OKtest := 1;
+      end if;
+    else
+      assert( CHARV( C ) = '0' );
+      if NOT( CHARV( C ) = '0' ) then
+        OKtest := 1;
+      end if;
+    end if;
+  end loop;
+  BITV  := BIT_PART'( '0' to '0' => '0' );
+  assert( BITV( '0' ) = '0' );
+  if NOT( BITV( '0' ) = '0' ) then
+    OKtest := 1;
+  end if;
+  BOOLV  := BOOL_PART'( TRUE to TRUE => '1' );
+  assert( BOOLV( TRUE ) = '1' );
+  if NOT( BOOLV( TRUE ) = '1' ) then
+    OKtest := 1;
+  end if;
+  SEVV  := SEV_PART'( ERROR => '0', WARNING | FAILURE => '1' );
+  assert( SEVV( WARNING ) = '1' );
+  assert( SEVV( ERROR ) = '0' );
+  assert( SEVV( FAILURE ) = '1' );
+  if NOT((SEVV(WARNING)='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1'))then
+    OKtest := 1;
+  end if;
+
+  -- 3. Use of 'others' in these aggregates.
+  CHARV := CHAR_PART'( 'a' | 'b' => '0', others => '1' );
+  for C in 'a' to 'z' loop
+    if  (C = 'a') then
+      assert( CHARV( C ) = '0' );
+      if NOT( CHARV( C ) = '0' ) then
+        OKtest := 1;
+      end if;
+    elsif (C = 'b') then
+      assert( CHARV( C ) = '0' );
+      if NOT( CHARV( C ) = '0' ) then
+        OKtest := 1;
+      end if;
+    else
+      assert( CHARV( C ) = '1' );
+      if NOT( CHARV( C ) = '1' ) then
+        OKtest := 1;
+      end if;
+    end if;
+  end loop;
+  BITV  := BIT_PART'( others => '1' );
+  assert( BITV( '0' ) = '1' );
+  if NOT( BITV( '0' ) = '1' ) then
+    OKtest := 1;
+  end if;
+  BOOLV  := BOOL_PART'( others => '0' );
+  assert( BOOLV( TRUE ) = '0' );
+  if NOT( BOOLV( TRUE ) = '0' ) then
+    OKtest := 1;
+  end if;
+  SEVV  := SEV_PART'( ERROR => '0', others => '1' );
+  assert( SEVV( WARNING ) = '1' );
+  assert( SEVV( ERROR ) = '0' );
+  assert( SEVV( FAILURE ) = '1' );
+  if NOT((SEVV(WARNING)='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1'))then
+    OKtest := 1;
+  end if;
+  wait for 5 ns;
+  assert NOT(OKtest = 0) 
+    report "***PASSED TEST: c07s03b02x02p01n01i02440" 
+    severity NOTE;
+  assert (OKtest = 0) 
+    report "***FAILED TEST: c07s03b02x02p01n01i02440 - Aggregates with different range types test failed."
+    severity ERROR;
+  wait;
+END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02440arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2446.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2446.vhd
new file mode 100644
index 0000000..bd18a65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2446.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2446.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p02n01i02446ent IS
+END c07s03b02x02p02n01i02446ent;
+
+ARCHITECTURE c07s03b02x02p02n01i02446arch OF c07s03b02x02p02n01i02446ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T1 is array (1 to 10) of Integer;
+    constant C : T1 := (1 => 2, 2=>4, 3 =>6, 4 =>5, others =>10) ; -- No_failure_here
+  BEGIN
+    assert NOT(C(1)=2 and C(2)=4 and C(3)=6 and C(4)=5 and C(5)=10 and C(6)=10) 
+      report "***PASSED TEST: c07s03b02x02p02n01i02446" 
+      severity NOTE;
+    assert (C(1)=2 and C(2)=4 and C(3)=6 and C(4)=5 and C(5)=10 and C(6)=10) 
+      report "***FAILED TEST: c07s03b02x02p02n01i02446 - All element associations of an array aggregate must be either all positional or all named."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p02n01i02446arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2448.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2448.vhd
new file mode 100644
index 0000000..250965a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2448.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2448.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p02n02i02448ent IS
+END c07s03b02x02p02n02i02448ent;
+
+ARCHITECTURE c07s03b02x02p02n02i02448arch OF c07s03b02x02p02n02i02448ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       t13 is array (bit'('0') to bit'('0')) of integer;
+    variable    v13 : t13;
+  BEGIN
+    v13 := (bit'('0') => 13);  -- No_failure_here
+    assert NOT(v13(bit'('0'))=13) 
+      report "***PASSED TEST: c07s03b02x02p02n02i02448" 
+      severity NOTE;
+    assert (v13(bit'('0'))=13) 
+      report "***FAILED TEST: c07s03b02x02p02n02i02448 - Named association of an array aggregate can have a choice that is a null range only if the aggregate includes a single element association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p02n02i02448arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2452.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2452.vhd
new file mode 100644
index 0000000..37da19e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2452.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2452.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02452ent IS
+END c07s03b02x02p03n02i02452ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02452arch OF c07s03b02x02p03n02i02452ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+    subtype CONSTRAINED_ARRAY   is UNCONSTRAINED_ARRAY ( 1 to 5 );
+
+    function F (A:CONSTRAINED_ARRAY) return CONSTRAINED_ARRAY is
+    begin
+      return A;
+    end F;
+
+    function F2 return CONSTRAINED_ARRAY is
+    begin
+      return F( ( others => 'c' ) );
+      -- sole "others" choice is legal.
+    end F2;
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F2;   
+    assert NOT(k="ccccc") 
+      report "***PASSED TEST: c07s03b02x02p03n02i02452" 
+      severity NOTE;
+    assert (k="ccccc") 
+      report "***FAILED TEST: c07s03b02x02p03n02i02452 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02452arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2453.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2453.vhd
new file mode 100644
index 0000000..5b4fb26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2453.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2453.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02453ent IS
+END c07s03b02x02p03n02i02453ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02453arch OF c07s03b02x02p03n02i02453ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+    subtype CONSTRAINED_ARRAY   is UNCONSTRAINED_ARRAY ( 1 to 5 );
+
+    function F (A:CONSTRAINED_ARRAY) return CONSTRAINED_ARRAY is
+    begin
+      return A;
+    end F;
+    function F2 return CONSTRAINED_ARRAY is
+    begin
+      return F( ( 'a','b',others => 'c' ) );
+      -- sole "others" choice is legal.
+    end F2;
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F2;   
+    assert NOT(k="abccc") 
+      report "***PASSED TEST: c07s03b02x02p03n02i02453" 
+      severity NOTE;
+    assert (k="abccc") 
+      report "***FAILED TEST: c07s03b02x02p03n02i02453 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02453arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2454.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2454.vhd
new file mode 100644
index 0000000..108d1d2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2454.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2454.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s03b02x02p03n02i02454pkg is
+  type    UN_ARR    is array (integer range <>) of character;
+  subtype CON_ARR is UN_ARR( 1 to 5) ;
+end c07s03b02x02p03n02i02454pkg;
+
+use work.c07s03b02x02p03n02i02454pkg.all;
+
+ENTITY c07s03b02x02p03n02i02454ent IS
+  port     (P : in CON_ARR := (others => 'A'));  --- No_failure_here
+END c07s03b02x02p03n02i02454ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02454arch OF c07s03b02x02p03n02i02454ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(P(1)='A' and P(2)='A' and P(3)='A' and P(4)='A' and P(5)='A')
+      report "***PASSED TEST: c07s03b02x02p03n02i02454"
+      severity NOTE;
+    assert (P(1)='A' and P(2)='A' and P(3)='A' and P(4)='A' and P(5)='A')
+      report "***FAILED TEST: c07s03b02x02p03n02i02454 - As the default expression defining the default initial value of a port declared to be of a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02454arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2455.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2455.vhd
new file mode 100644
index 0000000..70ca4c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2455.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2455.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02455ent IS
+END c07s03b02x02p03n02i02455ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02455arch OF c07s03b02x02p03n02i02455ent IS
+
+  type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of CHARACTER;
+  subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  function F return CONSTRAINED_ARRAY is
+  begin
+    return ( others => 'c'  );
+    -- sole "others" choice is legal.
+  end F;
+BEGIN
+  TESTING: PROCESS
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F;
+    assert NOT(k(1)='c' and k(2)='c' and k(3)='c')
+      report "***PASSED TEST: c07s03b02x02p03n02i02455"
+      severity NOTE;
+    assert (k(1)='c' and k(2)='c' and k(3)='c')
+      report "***FAILED TEST: c07s03b02x02p03n02i02455 - The others choice should be allowed as the aggregate is the result expression of a function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02455arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2456.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2456.vhd
new file mode 100644
index 0000000..2954f58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2456.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2456.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02456ent IS
+END c07s03b02x02p03n02i02456ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02456arch OF c07s03b02x02p03n02i02456ent IS
+
+  type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of CHARACTER;
+  subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  function F return CONSTRAINED_ARRAY is
+  begin
+    return ( 'a','b', others => 'c' );
+    -- "others" choice is legal.
+  end F;
+BEGIN
+  TESTING: PROCESS
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F;
+    assert NOT(k(1)='a' and k(2)='b' and k(3)='c')
+      report "***PASSED TEST: c07s03b02x02p03n02i02456"
+      severity NOTE;
+    assert (k(1)='a' and k(2)='b' and k(3)='c')
+      report "***FAILED TEST: c07s03b02x02p03n02i02456 - The others choice should be allowed as the aggregate is the result expression of a function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02456arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2457.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2457.vhd
new file mode 100644
index 0000000..37b9116
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2457.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2457.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02457ent IS
+END c07s03b02x02p03n02i02457ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02457arch OF c07s03b02x02p03n02i02457ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of character;
+    subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+    variable V : CONSTRAINED_ARRAY ;
+    -- check in declaration of constrained array variable.
+  BEGIN
+    V := ( others => '$' );
+    -- check in variable assignment to constrained array object.
+    wait for 5 ns;
+    assert NOT( V(1)='$' and V(2)='$' and V(3)='$' )
+      report "***PASSED TEST: c07s03b02x02p03n02i02457"
+      severity NOTE;
+    assert ( V(1)='$' and V(2)='$' and V(3)='$' )
+      report "***FAILED TEST: c07s03b02x02p03n02i02457 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02457arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2458.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2458.vhd
new file mode 100644
index 0000000..8f8966a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2458.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2458.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02458ent IS
+END c07s03b02x02p03n02i02458ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02458arch OF c07s03b02x02p03n02i02458ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+    subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
+    variable V : CONSTRAINED_ARRAY ;
+    -- check in declaration of constrained array variable.
+  BEGIN
+
+    V := ( 'd','x',others => '$' );
+    -- check in variable assignment to constrained array object.
+    wait for 5 ns;
+    assert NOT( V(1)='d' and V(2)='x' and V(3)='$' )
+      report "***PASSED TEST: c07s03b02x02p03n02i02458"
+      severity NOTE;
+    assert ( V(1)='d' and V(2)='x' and V(3)='$' )
+      report "***FAILED TEST: c07s03b02x02p03n02i02458 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02458arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2459.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2459.vhd
new file mode 100644
index 0000000..1cf7b89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2459.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2459.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02459ent IS
+END c07s03b02x02p03n02i02459ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02459arch OF c07s03b02x02p03n02i02459ent IS
+  type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of character;
+  subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  signal  V : CONSTRAINED_ARRAY;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    V <= ( others => '$' );
+    wait for 1 ns;
+    assert NOT( V(1)='$' and V(2)='$' and V(3)='$' )
+      report "***PASSED TEST: c07s03b02x02p03n02i02459"
+      severity NOTE;
+    assert ( V(1)='$' and V(2)='$' and V(3)='$' )
+      report "***FAILED TEST: c07s03b02x02p03n02i02459 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02459arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2460.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2460.vhd
new file mode 100644
index 0000000..f1b3e21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2460.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2460.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02460ent IS
+END c07s03b02x02p03n02i02460ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02460arch OF c07s03b02x02p03n02i02460ent IS
+  type       UNCONSTRAINED_ARRAY    is array ( integer range <> ) of character;
+  subtype    CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  type       AGGREGATE_ARRAY    is array (1 to 2) of CONSTRAINED_ARRAY;
+  signal     V,W          : CONSTRAINED_ARRAY;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (V,W) <= AGGREGATE_ARRAY' (('d', 'x', others => 'a'),  
+                               ('d', 'x', others => 'a')); 
+    wait for 1 ns;
+    assert NOT( V(1)='d' and V(2)='x' and V(3)='a' ) 
+      report "***PASSED TEST: c07s03b02x02p03n02i02460"
+      severity NOTE;
+    assert ( V(1)='d' and V(2)='x' and V(3)='a' ) 
+      report "***FAILED TEST: c07s03b02x02p03n02i02460 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02460arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2461.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2461.vhd
new file mode 100644
index 0000000..e9266b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2461.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2461.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02461ent IS
+END c07s03b02x02p03n02i02461ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02461arch OF c07s03b02x02p03n02i02461ent IS
+  type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of character;
+  subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  signal  V : CONSTRAINED_ARRAY;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    V <= ('d','x', others => '$' );
+    wait for 1 ns;
+    assert NOT( V(1)='d' and V(2)='x' and V(3)='$' ) 
+      report "***PASSED TEST: c07s03b02x02p03n02i02461"
+      severity NOTE;
+    assert ( V(1)='d' and V(2)='x' and V(3)='$' ) 
+      report "***FAILED TEST: c07s03b02x02p03n02i02461 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02461arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2462.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2462.vhd
new file mode 100644
index 0000000..3382831
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2462.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2462.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02462ent IS
+END c07s03b02x02p03n02i02462ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02462arch OF c07s03b02x02p03n02i02462ent IS
+  type    UNCONSTRAINED_ARRAY    is array ( integer range <> ) of character;
+  subtype CONSTRAINED_ARRAY    is UNCONSTRAINED_ARRAY ( 1 to 3 );
+  type    AGGREGATE_ARRAY    is array (1 to 2) of CONSTRAINED_ARRAY;
+  signal  V, W         :  CONSTRAINED_ARRAY;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (W,V) <= (AGGREGATE_ARRAY'((others => '$'),( others => '$' )));
+    wait for 1 ns;
+    assert NOT( V(1)='$' and V(2)='$' and V(3)='$' and W=(('$','$','$')))
+      report "***PASSED TEST: c07s03b02x02p03n02i02462"
+      severity NOTE;
+    assert ( V(1)='$' and V(2)='$' and V(3)='$' and W=(('$','$','$')))
+      report "***FAILED TEST: c07s03b02x02p03n02i02462 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02462arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2463.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2463.vhd
new file mode 100644
index 0000000..0dad7cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2463.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2463.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02463ent IS
+END c07s03b02x02p03n02i02463ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02463arch OF c07s03b02x02p03n02i02463ent IS
+  subtype    BV1 is BIT_VECTOR (2 downto 1);
+  constant    c   : BV1 := ('1', others => '0');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c="10" )
+      report "***PASSED TEST: c07s03b02x02p03n02i02463"
+      severity NOTE;
+    assert ( c="10" )
+      report "***FAILED TEST: c07s03b02x02p03n02i02463 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02463arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2464.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2464.vhd
new file mode 100644
index 0000000..8be786d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2464.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2464.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02464ent IS
+END c07s03b02x02p03n02i02464ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02464arch OF c07s03b02x02p03n02i02464ent IS
+
+  subtype BV1 is BIT_VECTOR (2 downto 1);
+  constant c : BV1 := (1 => '0', others => '1');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c="10" )
+      report "***PASSED TEST: c07s03b02x02p03n02i02464"
+      severity NOTE;
+    assert ( c="10" )
+      report "***FAILED TEST: c07s03b02x02p03n02i02464 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02464arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2465.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2465.vhd
new file mode 100644
index 0000000..356fc58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2465.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2465.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02465ent IS
+END c07s03b02x02p03n02i02465ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02465arch OF c07s03b02x02p03n02i02465ent IS
+  subtype    BV1 is BIT_VECTOR (2 downto 1);
+  constant    c   : BV1 := (2 => '1', others => '0');   
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c="10" )
+      report "***PASSED TEST: c07s03b02x02p03n02i02465"
+      severity NOTE;
+    assert ( c="10" )
+      report "***FAILED TEST: c07s03b02x02p03n02i02465 - An aggregate with an others choice can appear as an expression defining the initial value of a constant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02465arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2466.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2466.vhd
new file mode 100644
index 0000000..9f0171c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2466.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2466.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02466ent IS
+END c07s03b02x02p03n02i02466ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02466arch OF c07s03b02x02p03n02i02466ent IS
+  type    UN_ARR is array (integer range <>) of character;
+  subtype CON_ARR is UN_ARR( 1 to 5 ) ;
+  signal  S : CON_ARR := ('A','Z', others => 'C');     -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT(S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C')
+      report "***PASSED TEST: c07s03b02x02p03n02i02466"
+      severity NOTE;
+    assert (S(1)='A' and S(2)='Z' and S(3)='C' and S(4)='C' and S(5)='C')
+      report "***FAILED TEST: c07s03b02x02p03n02i02466 - An array aggregate with an others choice may appear as the expression defining the initial value of the drivers of one or more signals in an initialization specification."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02466arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2467.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2467.vhd
new file mode 100644
index 0000000..a38a8dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2467.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2467.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02467ent IS
+END c07s03b02x02p03n02i02467ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02467arch OF c07s03b02x02p03n02i02467ent IS
+  type      UN_ARR  is array (integer range <>) of character;
+  subtype   CON_ARR is UN_ARR( 1 to 5 );
+  attribute LOCN : CON_ARR ;
+  signal    S    : Integer ;
+  attribute LOCN of S : signal is ('A', others => 'Z'); -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( S'LOCN(1)='A' and S'LOCN(2)='Z' and S'LOCN(3)='Z' and S'LOCN(4)='Z' and S'LOCN(5)='Z' )
+      report "***PASSED TEST: c07s03b02x02p03n02i02467"
+      severity NOTE;
+    assert ( S'LOCN(1)='A' and S'LOCN(2)='Z' and S'LOCN(3)='Z' and S'LOCN(4)='Z' and S'LOCN(5)='Z' )
+      report "***FAILED TEST: c07s03b02x02p03n02i02467 - An array aggregate with an others choice may appear as the expression defining the value of an attribute in an attribute specification."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02467arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2471.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2471.vhd
new file mode 100644
index 0000000..b7f9023
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2471.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2471.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02471ent IS
+END c07s03b02x02p03n02i02471ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02471arch OF c07s03b02x02p03n02i02471ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+    subtype  CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 4 );
+    function F return CONSTRAINED_ARRAY is
+    begin
+      return CONSTRAINED_ARRAY'(others => '7');
+      -- check in function return statement.
+    end F;
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F;
+    wait for 5 ns;
+    assert NOT(k = "7777") 
+      report "***PASSED TEST: c07s03b02x02p03n02i02471" 
+      severity NOTE;
+    assert (k = "7777") 
+      report "***FAILED TEST: c07s03b02x02p03n02i02471 - Others cannot be used with an unconstrained array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02471arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2472.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2472.vhd
new file mode 100644
index 0000000..c6cd94b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2472.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2472.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02472ent IS
+END c07s03b02x02p03n02i02472ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02472arch OF c07s03b02x02p03n02i02472ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+    subtype  CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 4 );
+    function F return CONSTRAINED_ARRAY is
+    begin
+      return CONSTRAINED_ARRAY'(2 => 'h', others => '7');
+      -- check in function return statement.
+    end F;
+    variable k : CONSTRAINED_ARRAY;
+  BEGIN
+    k := F;
+    assert NOT(k = "7h77") 
+      report "***PASSED TEST: c07s03b02x02p03n02i02472" 
+      severity NOTE;
+    assert (k = "7h77") 
+      report "***FAILED TEST: c07s03b02x02p03n02i02472 - Others cannot be used with an unconstrained array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02472arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2474.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2474.vhd
new file mode 100644
index 0000000..a6106a3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2474.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2474.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n02i02474ent IS
+END c07s03b02x02p13n02i02474ent;
+
+ARCHITECTURE c07s03b02x02p13n02i02474arch OF c07s03b02x02p13n02i02474ent IS
+  type     UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+  subtype  CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
+BEGIN
+  TESTING: PROCESS
+    variable k : CA_DOWN;
+  BEGIN
+    k := CA_DOWN'((10 downto 1 => 'B'));   
+    assert NOT(k="BBBBBBBBBB") 
+      report "***PASSED TEST: c07s03b02x02p13n02i02474"
+      severity NOTE;
+    assert (k="BBBBBBBBBB") 
+      report "***FAILED TEST: c07s03b02x02p13n02i02474 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n02i02474arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2475.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2475.vhd
new file mode 100644
index 0000000..e26ee60
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2475.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2475.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n02i02475ent IS
+END c07s03b02x02p13n02i02475ent;
+
+ARCHITECTURE c07s03b02x02p13n02i02475arch OF c07s03b02x02p13n02i02475ent IS
+  type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+  subtype CA_UP is UNCONSTRAINED_ARRAY ( 1 to 10 );
+  subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
+BEGIN
+  TESTING: PROCESS
+    variable k : CA_UP;
+  BEGIN
+    k := CA_DOWN'((1 to 10 => 'B'));   
+    assert NOT(k="BBBBBBBBBB") 
+      report "***PASSED TEST: c07s03b02x02p13n02i02475" 
+      severity NOTE;
+    assert (k="BBBBBBBBBB") 
+      report "***FAILED TEST: c07s03b02x02p13n02i02475 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n02i02475arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2477.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2477.vhd
new file mode 100644
index 0000000..c65a292
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2477.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2477.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n04i02477ent IS
+END c07s03b02x02p13n04i02477ent;
+
+ARCHITECTURE c07s03b02x02p13n04i02477arch OF c07s03b02x02p13n04i02477ent IS
+  type    index_values is (one, two, three);
+  type    ucarr is array (index_values range <>) of Boolean;      
+  subtype carr  is ucarr (index_values'low to index_values'high);
+  function f2 (i : integer) return carr is
+  begin
+    return (True, True, False);  
+  end f2;
+BEGIN
+  TESTING: PROCESS
+    variable k : carr;
+  BEGIN
+    k := f2(1);
+    assert NOT(k=(True,True,False)) 
+      report "***PASSED TEST: c07s03b02x02p13n04i02477" 
+      severity NOTE;
+    assert (k=(True,True,False)) 
+      report "***FAILED TEST: c07s03b02x02p13n04i02477 - The leftmost bound is determined by the applicable index constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n04i02477arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2478.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2478.vhd
new file mode 100644
index 0000000..d7595a1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2478.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2478.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n04i02478ent IS
+END c07s03b02x02p13n04i02478ent;
+
+ARCHITECTURE c07s03b02x02p13n04i02478arch OF c07s03b02x02p13n04i02478ent IS
+  type    index_values is (one, two, three);
+  type    ucarr is array (index_values range <>) of Boolean;      
+  subtype carr  is ucarr (index_values'low to index_values'high);
+  function f2 (i : integer) return carr is
+  begin
+    return (index_values'LOW => TRUE, others => False);
+  end f2;
+BEGIN
+  TESTING: PROCESS
+    variable k : carr;
+  BEGIN
+    k := f2(1);
+    assert NOT(k=(True,False,False)) 
+      report "***PASSED TEST: c07s03b02x02p13n04i02478"
+      severity NOTE;
+    assert (k=(True,False,False)) 
+      report "***FAILED TEST: c07s03b02x02p13n04i02478 - The leftmost bound is determined by the applicable index constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n04i02478arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2479.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2479.vhd
new file mode 100644
index 0000000..d819686
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2479.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2479.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n04i02479ent IS
+END c07s03b02x02p13n04i02479ent;
+
+ARCHITECTURE c07s03b02x02p13n04i02479arch OF c07s03b02x02p13n04i02479ent IS
+  type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+  subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(CA_DOWN'LEFT = 10)
+      report "***PASSED TEST: c07s03b02x02p13n04i02479"
+      severity NOTE;
+    assert (CA_DOWN'LEFT = 10)
+      report "***FAILED TEST: c07s03b02x02p13n04i02479 - S'LEFT did not return the correct value." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n04i02479arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2480.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2480.vhd
new file mode 100644
index 0000000..d0da580
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2480.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2480.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n04i02480ent IS
+END c07s03b02x02p13n04i02480ent;
+
+ARCHITECTURE c07s03b02x02p13n04i02480arch OF c07s03b02x02p13n04i02480ent IS
+  type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+  subtype CA_UP   is UNCONSTRAINED_ARRAY (1 to 10);
+  subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((CA_DOWN'RIGHT = 1) and (CA_UP'RIGHT = 10))
+      report "***PASSED TEST: c07s03b02x02p13n04i02480" 
+      severity NOTE;
+    assert ((CA_DOWN'RIGHT = 1) and (CA_UP'RIGHT = 10))
+      report "***FAILED TEST: c07s03b02x02p13n04i02480 - Rightmost bounds INCORRECT for positional aggregates." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n04i02480arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2481.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2481.vhd
new file mode 100644
index 0000000..87dbef2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2481.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2481.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p01n02i02481ent IS
+END c07s03b03x00p01n02i02481ent;
+
+ARCHITECTURE c07s03b03x00p01n02i02481arch OF c07s03b03x00p01n02i02481ent IS
+  function f(a, b : INTEGER) return INTEGER is
+  begin
+    return a + b;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable v : INTEGER := 0;
+  BEGIN
+    v := f(1, 2);
+    wait for 5 ns;
+    assert NOT( v=3 )
+      report "***PASSED TEST: c07s03b03x00p01n02i02481"
+      severity NOTE;
+    assert ( v=3 )
+      report "***FAILED TEST: c07s03b03x00p01n02i02481 - Function call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p01n02i02481arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2483.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2483.vhd
new file mode 100644
index 0000000..550baa6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2483.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2483.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p01n01i02483ent IS
+END c07s03b03x00p01n01i02483ent;
+
+ARCHITECTURE c07s03b03x00p01n01i02483arch OF c07s03b03x00p01n01i02483ent IS
+
+  function CreateN(constant size : in INTEGER) return STRING is
+  begin
+    return "This is a test return value";
+  end;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert False 
+      report CreateN(1) 
+      severity NOTE;
+                                        -- should be string above
+    assert FALSE
+      report "***PASSED TEST: c07s03b03x00p01n01i02483 - This test needs manual check to see that 'This is a test return value' assertion note appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p01n01i02483arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2484.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2484.vhd
new file mode 100644
index 0000000..4f8b2a0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2484.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2484.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p01n02i02484ent IS
+END c07s03b03x00p01n02i02484ent;
+
+ARCHITECTURE c07s03b03x00p01n02i02484arch OF c07s03b03x00p01n02i02484ent IS
+  signal t1, t2, t3, t4 : INTEGER := -1;
+BEGIN
+  TESTING: PROCESS
+    constant ref    : INTEGER := 123;
+
+    function FuncN1 return INTEGER is
+      function FuncN2 return INTEGER is
+        function FuncN3 return INTEGER is
+          function FuncN4 return INTEGER is
+            function FuncN5 return INTEGER is
+              function FuncN6 return INTEGER is
+                function FuncN7 return INTEGER is
+                  function FuncN8 return INTEGER is
+                    function FuncN9 return INTEGER is
+                      function FuncN10 return INTEGER is
+                        function FuncN11 return INTEGER is
+                        begin
+                          return ref;
+                        end FuncN11;
+                      begin
+                        return FuncN11;
+                      end FuncN10;
+                    begin
+                      return FuncN10;
+                    end FuncN9;
+                  begin
+                    return FuncN9;
+                  end FuncN8;
+                begin
+                  return FuncN8;
+                end FuncN7;
+              begin
+                return FuncN7;
+              end FuncN6;
+            begin
+              return FuncN6;
+            end FuncN5;
+          begin
+            return FuncN5;
+          end FuncN4;
+        begin
+          return FuncN4;
+        end FuncN3;
+      begin
+        return FuncN3;
+      end FuncN2;
+    begin
+      return FuncN2;
+    end FuncN1;
+    
+    
+    function Func1 return INTEGER is
+    begin
+      return 1;
+    end Func1;
+
+    function Func2(selector : BOOLEAN) return INTEGER is
+    begin
+      if selector then
+        return 11;
+      else
+        return 13;
+      end if;
+    end Func2;
+
+  BEGIN
+    t1 <= func1;
+    t2 <= func2(TRUE);
+    t3 <= func2(FALSE);
+    t4 <= funcN1;
+    wait for 5 ns;
+    assert NOT( t1=1 and t2=11 and t3=13 and t4=123 )
+      report "***PASSED TEST: c07s03b03x00p01n02i02484"
+      severity NOTE;
+    assert ( t1=1 and t2=11 and t3=13 and t4=123 )
+      report "***FAILED TEST: c07s03b03x00p01n02i02484 - Function call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p01n02i02484arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2485.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2485.vhd
new file mode 100644
index 0000000..51d0d6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2485.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2485.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p02n01i02485ent IS
+END c07s03b03x00p02n01i02485ent;
+
+ARCHITECTURE c07s03b03x00p02n01i02485arch OF c07s03b03x00p02n01i02485ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x:integer; y:boolean; z:real) return boolean is
+    begin
+      if y then
+        return true;
+      end if;
+      return false;
+    end;
+    variable p: integer := 3;
+    variable q: boolean := true;
+    variable r: real;
+    variable q1: boolean;
+  BEGIN
+    q1 := check (p,q,r);
+    assert NOT(q1=true)
+      report "***PASSED TEST: c07s03b03x00p02n01i02485"
+      severity NOTE;
+    assert (q1=true)
+      report "***FAILED TEST: c07s03b03x00p02n01i02485 - The function call consists of a function name and (optionally) an actual parameter list enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p02n01i02485arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2486.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2486.vhd
new file mode 100644
index 0000000..ac37a57
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2486.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2486.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p02n01i02486ent IS
+END c07s03b03x00p02n01i02486ent;
+
+ARCHITECTURE c07s03b03x00p02n01i02486arch OF c07s03b03x00p02n01i02486ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check  return boolean is
+    begin
+      return false;
+    end;
+    variable q: boolean ;
+  BEGIN
+    q := check;
+    assert NOT(q=FALSE) 
+      report "***PASSED TEST: c07s03b03x00p02n01i02486" 
+      severity NOTE;
+    assert (q=FALSE) 
+      report "***FAILED TEST: c07s03b03x00p02n01i02486 - The function call consists of a function name and (optionally) an actual parameter list enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p02n01i02486arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2487.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2487.vhd
new file mode 100644
index 0000000..897a057
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2487.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2487.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p02n01i02487ent IS
+END c07s03b03x00p02n01i02487ent;
+
+ARCHITECTURE c07s03b03x00p02n01i02487arch OF c07s03b03x00p02n01i02487ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function typeconv (a1 : real) return integer is
+    begin
+      return 1;
+    end;
+    function func1    (a2 : integer) return integer is
+    begin
+      return 5;
+    end func1;
+    variable x: real := 1.2;
+    variable y: integer;
+  BEGIN
+    y := func1 (typeconv (x));
+    assert NOT(y=5)
+      report "***PASSED TEST: c07s03b03x00p02n01i02487" 
+      severity NOTE;
+    assert (y=5)
+      report "***FAILED TEST: c07s03b03x00p02n01i02487 - The function call consists of a function name and (optionally) an actual parameter list enclosed with parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p02n01i02487arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2494.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2494.vhd
new file mode 100644
index 0000000..34037fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2494.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2494.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n02i02494ent IS
+END c07s03b03x00p04n02i02494ent;
+
+ARCHITECTURE c07s03b03x00p04n02i02494arch OF c07s03b03x00p04n02i02494ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x : integer) return integer is
+    begin
+      return (10 * x);
+    end;
+    variable q1: integer := 12;
+    variable q2: integer ;
+  BEGIN
+    q2 := check (q1) + 24 - check (2);
+    assert NOT( q2 = 124 )
+      report "***PASSED TEST: c07s03b03x00p04n02i02494"
+      severity NOTE;
+    assert ( q2=124 )
+      report "***FAILED TEST: c07s03b03x00p04n02i02494 - The actual parameter can be specified explicitly by an association element in the association list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n02i02494arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2495.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2495.vhd
new file mode 100644
index 0000000..f4adba4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2495.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2495.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n02i02495ent IS
+END c07s03b03x00p04n02i02495ent;
+
+ARCHITECTURE c07s03b03x00p04n02i02495arch OF c07s03b03x00p04n02i02495ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x:integer; y:boolean; z1:real; z2:real:= 1.3)
+      return boolean is    
+    begin
+      if y then
+        return true;
+      end if;
+      return false;
+    end;
+    variable p: integer := 3;
+    variable q: boolean := true;
+    variable s: boolean;
+    variable r: real;
+  BEGIN
+    s := check (p, q, r);  -- No_failure_here
+    assert NOT( s=true ) 
+      report "***PASSED TEST: c07s03b03x00p04n02i02495"
+      severity NOTE;
+    assert ( s=true ) 
+      report "***FAILED TEST: c07s03b03x00p04n02i02495 - The actual parameter can be specified explicitly by an association element in the association list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n02i02495arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2496.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2496.vhd
new file mode 100644
index 0000000..f2ae45d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2496.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2496.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n02i02496ent IS
+END c07s03b03x00p04n02i02496ent;
+
+ARCHITECTURE c07s03b03x00p04n02i02496arch OF c07s03b03x00p04n02i02496ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function func1 (a1 : real; b1 : integer:= 12) return integer is 
+    begin
+      return 5;
+    end;
+    variable x: real := 1.2;
+    variable y: integer ;
+  BEGIN
+    y := func1 (x);
+    assert NOT( y=5 )
+      report "***PASSED TEST: c07s03b03x00p04n02i02496"
+      severity NOTE;
+    assert ( y=5 )
+      report "***FAILED TEST: c07s03b03x00p04n02i02496 - The actual parameter can be specified explicitly by an association element in the association list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n02i02496arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2499.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2499.vhd
new file mode 100644
index 0000000..41274df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2499.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2499.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p05n01i02499ent IS
+END c07s03b03x00p05n01i02499ent;
+
+ARCHITECTURE c07s03b03x00p05n01i02499arch OF c07s03b03x00p05n01i02499ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x : boolean) return boolean is
+    begin
+      return false;
+    end;
+    variable q1: boolean := true;
+    variable q2: boolean ;
+  BEGIN
+    q2 := check (check (q1)); -- q2 should be false
+    assert NOT(q2=FALSE) 
+      report "***PASSED TEST: c07s03b03x00p05n01i02499" 
+      severity NOTE;
+    assert (q2=FALSE) 
+      report "***FAILED TEST: c07s03b03x00p05n01i02499 - Actual parameter must belong to the subtype of the associated formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p05n01i02499arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc25.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc25.vhd
new file mode 100644
index 0000000..5c059f1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc25.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc25.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p10n02i00025ent IS
+END c04s02b00x00p10n02i00025ent;
+
+ARCHITECTURE c04s02b00x00p10n02i00025arch OF c04s02b00x00p10n02i00025ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define an ascending subtype.
+    subtype ASC_B is INTEGER range 0 to 1;
+    subtype ASC is ASC_B;
+
+    -- Define a descending subtype.
+    subtype DES_B is INTEGER range 1 to 0;
+    subtype DES is DES_B;
+
+    -- Define a 'previous value' variable.
+    variable PREV : INTEGER;
+
+    variable k : integer := 0;
+    variable l : integer := 0;
+  BEGIN
+
+    -- Test the direction of the ascending range.
+    PREV := -1;
+    for I in ASC loop
+      if (I > PREV) then
+        PREV := I;
+      else
+        k := 1;
+      end if;
+    end loop;
+
+    -- Test the direction of the descending range.
+    PREV := 2;
+    for I in DES loop
+      if (I < PREV) then
+        PREV := I;
+      else
+        l := 1;
+      end if;
+    end loop;
+
+    assert NOT( k=0 and l=0 )
+      report "***PASSED TEST:c04s02b00x00p10n02i00025"
+      severity NOTE;
+    assert ( k=0 and l=0 )
+      report "***FAILED TEST: c04s02b00x00p10n02i00025 - The direction of a discrete subtype indication is the same as that of the denoted subtype in the absence of an explicit type constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p10n02i00025arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2500.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2500.vhd
new file mode 100644
index 0000000..167c685
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2500.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2500.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p05n01i02500ent IS
+END c07s03b03x00p05n01i02500ent;
+
+ARCHITECTURE c07s03b03x00p05n01i02500arch OF c07s03b03x00p05n01i02500ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function f1(constant p : in STRING) return INTEGER is
+    begin
+      return P'LENGTH;
+    end;
+
+    constant C : STRING := "Testing";
+  BEGIN
+    wait for 5 ns;
+    assert NOT(f1(c) = c'LENGTH)
+      report "***PASSED TEST: c07s03b03x00p05n01i02500"
+      severity NOTE;
+    assert (f1(c) = c'LENGTH)
+      report "***FAILED TEST: c07s03b03x00p05n01i02500 - Evaluation of a function call with actual parameter expressions test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p05n01i02500arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2501.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2501.vhd
new file mode 100644
index 0000000..7c00acb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2501.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2501.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p02n01i02501ent IS
+END c07s03b04x00p02n01i02501ent;
+
+ARCHITECTURE c07s03b04x00p02n01i02501arch OF c07s03b04x00p02n01i02501ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type bit_vctor is array (bit'('0') to bit'('1') ) of integer;
+    variable k : bit_vctor;
+  BEGIN
+    k := (5,6);
+    assert NOT( k=(5,6) )
+      report "***PASSED TEST: c07s03b04x00p02n01i02501"
+      severity NOTE;
+    assert ( k=(5,6) )
+      report "***FAILED TEST: c07s03b04x00p02n01i02501 - The qualified expression must either consist of a type mark, an apostrophe ('), and an expression enclosed with parentheses or consist of a type mark, an apostrophe ('), and an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p02n01i02501arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2502.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2502.vhd
new file mode 100644
index 0000000..443df49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2502.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2502.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p02n01i02502ent IS
+END c07s03b04x00p02n01i02502ent;
+
+ARCHITECTURE c07s03b04x00p02n01i02502arch OF c07s03b04x00p02n01i02502ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        x : bit;
+        y : integer;
+        z : boolean;
+      end record;
+    variable S :rec_type;
+  BEGIN
+    S   := rec_type'(bit'('0'), 1, true);
+    assert NOT(S.x='0' and S.y=1 and S.z=true) 
+      report "***PASSED TEST: c07s03b04x00p02n01i02502"
+      severity NOTE;
+    assert (S.x='0' and S.y=1 and S.z=true) 
+      report "***FAILED TEST: c07s03b04x00p02n01i02502 - The qualified expression must either consist of a type mark, an apostrophe ('), and an expression enclosed with parentheses or consist of a type mark, an apostrophe ('), and an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p02n01i02502arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2506.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2506.vhd
new file mode 100644
index 0000000..2a2d52c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2506.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2506.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p03n01i02506ent IS
+END c07s03b04x00p03n01i02506ent;
+
+ARCHITECTURE c07s03b04x00p03n01i02506arch OF c07s03b04x00p03n01i02506ent IS
+  type rec_type is
+    record
+      x : bit;
+      y : integer;
+      z : boolean;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable S1 :rec_type;
+  BEGIN
+    S1   := rec_type'(bit'('0'), 1, true)  ;-- No_Failure_here
+    assert NOT(S1.x='0' and S1.y=1 and S1.z=true) 
+      report "***PASSED TEST: c07s03b04x00p03n01i02506" 
+      severity NOTE;
+    assert (S1.x='0' and S1.y=1 and S1.z=true) 
+      report "***FAILED TEST: c07s03b04x00p03n01i02506 - Expression type does not match type mark." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p03n01i02506arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc251.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc251.vhd
new file mode 100644
index 0000000..23300a9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc251.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc251.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00251ent IS
+END c03s01b02x00p04n01i00251ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00251arch OF c03s01b02x00p04n01i00251ent IS
+  type I1 is range 1 to 10;
+  type I2 is range 11 to 20;
+  constant V1: I1 := 1;
+  constant V2: I2 := 20;
+  type I5 is range V1 to V2;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 6;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p04n01i00251" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p04n01i00251 - Range constraints in integer type definition need not be of the same integer type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00251arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2511.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2511.vhd
new file mode 100644
index 0000000..f991006
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2511.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2511.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p03n03i02511ent IS
+END c07s03b04x00p03n03i02511ent;
+
+ARCHITECTURE c07s03b04x00p03n03i02511arch OF c07s03b04x00p03n03i02511ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function f1 return integer is
+    begin 
+      return 2; 
+    end;
+    variable k : integer := 0;
+  BEGIN
+    k := integer'(f1/f1);
+    assert NOT( k=1 )
+      report "***PASSED TEST: c07s03b04x00p03n03i02511"
+      severity NOTE;
+    assert ( k=1 )
+      report "***FAILED TEST: c07s03b04x00p03n03i02511 - The evaluation of a qualified expression evaluates the operand and checks that its value belongs to the subtype denoted by the type mark."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p03n03i02511arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2513.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2513.vhd
new file mode 100644
index 0000000..d5171cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2513.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2513.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p02n01i02513ent IS
+END c07s03b05x00p02n01i02513ent;
+
+ARCHITECTURE c07s03b05x00p02n01i02513arch OF c07s03b05x00p02n01i02513ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k1 : integer    := 65;
+    variable k2 : real   := 1.2;
+  BEGIN
+    k1 := integer(k2);
+    wait for 1 ns;
+    assert NOT(k1 = 1) 
+      report "***PASSED TEST: c07s03b05x00p02n01i02513" 
+      severity NOTE;
+    assert (k1 = 1) 
+      report "***FAILED TEST: c07s03b05x00p02n01i02513 - Missing expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p02n01i02513arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2515.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2515.vhd
new file mode 100644
index 0000000..f04846f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2515.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2515.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n02i02515ent IS
+END c07s03b05x00p03n02i02515ent;
+
+ARCHITECTURE c07s03b05x00p03n02i02515arch OF c07s03b05x00p03n02i02515ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type century is range 1 to 10;
+    
+    function f(a:century) return century is
+    begin 
+      return century'(1); 
+    end;
+    
+    type millenia is ('1', '2', '3', '4', '5');
+    
+    function f (a:millenia) return millenia is
+    begin 
+      return millenia'('2'); 
+    end;
+    
+    variable hundreds : century  ;
+  BEGIN
+    hundreds := century (f(hundreds));
+    assert NOT(hundreds = 1) 
+      report "***PASSED TEST: c07s03b05x00p03n02i02515" 
+      severity NOTE;
+    assert (hundreds = 1) 
+      report "***FAILED TEST: c07s03b05x00p03n02i02515 - Type of operand must be determinable independent of the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n02i02515arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2519.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2519.vhd
new file mode 100644
index 0000000..4dd38db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2519.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2519.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n04i02519ent IS
+END c07s03b05x00p03n04i02519ent;
+
+ARCHITECTURE c07s03b05x00p03n04i02519arch OF c07s03b05x00p03n04i02519ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type century is range 1 to 10;
+    variable hundreds : century  ;
+    type millenia is range 1 to 10;
+    variable thousand : millenia ;
+  BEGIN
+    thousand := millenia (hundreds);
+    assert NOT( thousand = 1 )
+      report "***PASSED TEST: c07s03b05x00p03n04i02519"
+      severity NOTE;
+    assert ( thousand = 1 )
+      report "***FAILED TEST: c07s03b05x00p03n04i02519 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n04i02519arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2520.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2520.vhd
new file mode 100644
index 0000000..4bae3f7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2520.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2520.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n04i02520ent IS
+END c07s03b05x00p03n04i02520ent;
+
+ARCHITECTURE c07s03b05x00p03n04i02520arch OF c07s03b05x00p03n04i02520ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type century is range 1 to 10;
+    function f return century is
+    begin 
+      return (century'(3)); 
+    end;
+    variable hundreds : century  ;
+    type millenia is range 1 to 10;
+    variable thousand : millenia ;
+  BEGIN
+    thousand := millenia (f);
+    assert NOT( thousand = 3 )
+      report "***PASSED TEST: c07s03b05x00p03n04i02520"
+      severity NOTE;
+    assert ( thousand = 3 )
+      report "***FAILED TEST: c07s03b05x00p03n04i02520 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n04i02520arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2522.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2522.vhd
new file mode 100644
index 0000000..66743ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2522.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2522.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p04n01i02522ent IS
+END c07s03b05x00p04n01i02522ent;
+
+ARCHITECTURE c07s03b05x00p04n01i02522arch OF c07s03b05x00p04n01i02522ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Apples  is range 0 to 75;
+    type Oranges is range 0 to 75;
+    variable Macintosh : Apples;
+    variable Seville   : Oranges := 5;
+  BEGIN
+    Macintosh := Apples (Seville)  ;
+    Seville  :=  Oranges (Macintosh) ;    -- No_Failure_here
+    wait for 1 ns;
+    assert NOT( Seville = 5 )
+      report "***PASSED TEST: c07s03b05x00p04n01i02522"
+      severity NOTE;
+    assert ( Seville = 5 )
+      report "***FAILED TEST: c07s03b05x00p04n01i02522 - Conversion consists of conversion to the target type followed by a check that the result of the conversion belongs to the subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p04n01i02522arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2524.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2524.vhd
new file mode 100644
index 0000000..5872a1a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2524.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2524.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p05n02i02524ent IS
+END c07s03b05x00p05n02i02524ent;
+
+ARCHITECTURE c07s03b05x00p05n02i02524arch OF c07s03b05x00p05n02i02524ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Grapes is (Sweet, Sour);
+    variable Green : Grapes;
+  BEGIN
+    Green := Grapes (Sweet);
+    assert NOT( Green = Sweet )
+      report "***PASSED TEST: c07s03b05x00p05n02i02524"
+      severity NOTE;
+    assert ( Green = Sweet )
+      report "***FAILED TEST: c07s03b05x00p05n02i02524 - Conversion of an operand of a given type to the type itself is allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p05n02i02524arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2525.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2525.vhd
new file mode 100644
index 0000000..a75f2b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2525.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2525.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n02i02525ent IS
+END c07s03b05x00p06n02i02525ent;
+
+ARCHITECTURE c07s03b05x00p06n02i02525arch OF c07s03b05x00p06n02i02525ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Apples  is range 0 to 75;
+    type Oranges is range 0 to 75;
+    variable Macintosh : Apples   := 7;
+    variable Seville   : Oranges    := 5;
+  BEGIN
+    Macintosh := Apples (Seville);
+    assert NOT( Macintosh=5 )
+      report "***PASSED TEST: c07s03b05x00p06n02i02525"
+      severity NOTE;
+    assert ( Macintosh=5 )
+      report "***FAILED TEST: c07s03b05x00p06n02i02525 - The operand can be of any integer type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n02i02525arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2527.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2527.vhd
new file mode 100644
index 0000000..2372ff5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2527.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2527.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n04i02527ent IS
+END c07s03b05x00p06n04i02527ent;
+
+ARCHITECTURE c07s03b05x00p06n04i02527arch OF c07s03b05x00p06n04i02527ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Integer;
+  BEGIN
+    V1 := Integer (10.2);
+    assert NOT( V1 = 10 )
+      report "***PASSED TEST: c07s03b05x00p06n04i02527"
+      severity NOTE;
+    assert ( V1 = 10 )
+      report "***FAILED TEST: c07s03b05x00p06n04i02527 - The conversion of a floating point value to an integer type rounds to the nearest integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n04i02527arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2528.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2528.vhd
new file mode 100644
index 0000000..9c6d815
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2528.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2528.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n04i02528ent IS
+END c07s03b05x00p06n04i02528ent;
+
+ARCHITECTURE c07s03b05x00p06n04i02528arch OF c07s03b05x00p06n04i02528ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Integer;
+  BEGIN
+    V1 := Integer (10.7);
+    assert NOT( V1 = 11 )
+      report "***PASSED TEST: c07s03b05x00p06n04i02528"
+      severity NOTE;
+    assert ( V1 = 11 )
+      report "***FAILED TEST: c07s03b05x00p06n04i02528 - The conversion of a floating point value to an integer type rounds to the nearest integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n04i02528arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2529.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2529.vhd
new file mode 100644
index 0000000..8773c71
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2529.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2529.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n04i02529ent IS
+END c07s03b05x00p06n04i02529ent;
+
+ARCHITECTURE c07s03b05x00p06n04i02529arch OF c07s03b05x00p06n04i02529ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Integer;
+  BEGIN
+    V1 := Integer (10.5);
+    assert NOT((V1 = 10) or ( V1 = 11 ))
+      report "***PASSED TEST: c07s03b05x00p06n04i02529"
+      severity NOTE;
+    assert ((V1 = 10) or ( V1 = 11 ))
+      report "***FAILED TEST: c07s03b05x00p06n04i02529 - The conversion of a floating point to an integer point, if the value is halfway between two integers, rounding may be up or down."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n04i02529arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2530.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2530.vhd
new file mode 100644
index 0000000..ca1c915
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2530.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2530.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n04i02530ent IS
+END c07s03b05x00p06n04i02530ent;
+
+ARCHITECTURE c07s03b05x00p06n04i02530arch OF c07s03b05x00p06n04i02530ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Integer;
+  BEGIN
+    V1 := Integer (-3.2147483647);
+    assert NOT( V1 = -3 )
+      report "***PASSED TEST: c07s03b05x00p06n04i02530"
+      severity NOTE;
+    assert ( V1 = -3 )
+      report "***FAILED TEST: c07s03b05x00p06n04i02530 - The conversion of a floating point value to an integer type rounds to the nearest integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n04i02530arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2531.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2531.vhd
new file mode 100644
index 0000000..c84e756
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2531.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2531.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n02i02531ent IS
+END c07s03b05x00p06n02i02531ent;
+
+ARCHITECTURE c07s03b05x00p06n02i02531arch OF c07s03b05x00p06n02i02531ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k1 : integer    := 5;
+    variable k2 : real    := 1.1;
+  BEGIN
+    k2 := real (k1);
+    assert NOT( k2=5.0 )
+      report "***PASSED TEST: c07s03b05x00p06n02i02531"
+      severity NOTE;
+    assert ( k2=5.0 )
+      report "***FAILED TEST: c07s03b05x00p06n02i02531 - The type conversion from integer to real failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n02i02531arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2532.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2532.vhd
new file mode 100644
index 0000000..e135cf3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2532.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2532.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n02i02532ent IS
+END c07s03b05x00p06n02i02532ent;
+
+ARCHITECTURE c07s03b05x00p06n02i02532arch OF c07s03b05x00p06n02i02532ent IS
+  signal R1 : REAL    := 10.0;
+  signal I2 : INTEGER    := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    I2 <= INTEGER(R1);
+    wait for 5 ns;
+    assert NOT( I2=10 )
+      report "***PASSED TEST: c07s03b05x00p06n02i02532"
+      severity NOTE;
+    assert ( I2=10 )
+      report "***FAILED TEST: c07s03b05x00p06n02i02532 - The type conversion from real to integer type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n02i02532arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2533.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2533.vhd
new file mode 100644
index 0000000..af67db2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2533.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2533.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p10n01i02533ent IS
+END c07s03b05x00p10n01i02533ent;
+
+ARCHITECTURE c07s03b05x00p10n01i02533arch OF c07s03b05x00p10n01i02533ent IS
+  type Memory is array (Integer range <>) of Integer;
+  subtype T1 is Memory (1 to 6) ;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T1 ;
+    variable V2 : T1 := (2,3,4,2,5,6) ;
+  BEGIN
+    V1 := Memory (V2) ;    -- No_Failure_her
+    assert NOT(V1=(2,3,4,2,5,6))
+      report "***PASSED TEST: c07s03b05x00p10n01i02533"
+      severity NOTE;
+    assert (V1=(2,3,4,2,5,6))
+      report "***FAILED TEST: c07s03b05x00p10n01i02533 - The bounds of the operand are converted to the corresponding index type of the target type when the type mark is an unconstrained array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p10n01i02533arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2535.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2535.vhd
new file mode 100644
index 0000000..6b3277a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2535.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2535.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p13n03i02535ent IS
+END c07s03b05x00p13n03i02535ent;
+
+ARCHITECTURE c07s03b05x00p13n03i02535arch OF c07s03b05x00p13n03i02535ent IS
+  type Memory is array (Integer range <>) of Integer;
+  subtype T1 is Memory (1 to 6) ;
+  subtype T2 is Memory (1 to 6) ;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T1 ;
+    variable V2 : T1 := (2,3,6,3,4,5) ;
+  BEGIN
+    V1 := T2 (V2) ;    -- No_Failure_here
+    wait for 1 ns;
+    assert NOT(V1 = (2,3,6,3,4,5)) 
+      report "***PASSED TEST: c07s03b05x00p13n03i02535" 
+      severity NOTE;
+    assert (V1 = (2,3,6,3,4,5)) 
+      report "***FAILED TEST: c07s03b05x00p13n03i02535 - A check is made that for each element of the operand there is a matching element of the target subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p13n03i02535arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc254.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc254.vhd
new file mode 100644
index 0000000..c09161d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc254.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc254.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p06n01i00254ent IS
+END c03s01b02x00p06n01i00254ent;
+
+ARCHITECTURE c03s01b02x00p06n01i00254arch OF c03s01b02x00p06n01i00254ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer;
+  BEGIN
+    k := integer'POS(2);
+    assert NOT( k=2 )
+      report "***PASSED TEST: c03s01b02x00p06n01i00254"
+      severity NOTE;
+    assert ( k=2 )
+      report "***FAILED TEST: c03s01b02x00p06n01i00254 - The position number of an integer value is the corresponding value of the type universal_integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p06n01i00254arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2546.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2546.vhd
new file mode 100644
index 0000000..d29cddc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2546.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2546.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02546ent IS
+END c07s03b05x00p14n01i02546ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02546arch OF c07s03b05x00p14n01i02546ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer;
+  BEGIN
+    i := 100 ns / 20 ns;     -- no_failure_here
+    assert NOT(i=5) 
+      report "***PASSED TEST: c07s03b05x00p14n01i02546" 
+      severity NOTE;
+    assert (i=5) 
+      report "***FAILED TEST: c07s03b05x00p14n01i02546 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02546arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2547.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2547.vhd
new file mode 100644
index 0000000..d85a1f0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2547.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2547.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02547ent IS
+END c07s03b05x00p14n01i02547ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02547arch OF c07s03b05x00p14n01i02547ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : real;
+  BEGIN
+    i := 100.5 * 0.5;     -- no_failure_here
+    assert NOT(i=50.25) 
+      report "***PASSED TEST: c07s03b05x00p14n01i02547" 
+      severity NOTE;
+    assert (i=50.25) 
+      report "***FAILED TEST: c07s03b05x00p14n01i02547 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02547arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2550.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2550.vhd
new file mode 100644
index 0000000..37e6322
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2550.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2550.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p08n01i02550ent IS
+END c07s03b05x00p08n01i02550ent;
+
+ARCHITECTURE c07s03b05x00p08n01i02550arch OF c07s03b05x00p08n01i02550ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type century is  array (1 to 5) of integer ;
+    type millenia is array (5 downto 1) of integer;
+    variable hundreds : century  := (1,1,1,1,1);
+    variable thousand : millenia ;
+  BEGIN
+    thousand := millenia (hundreds);
+    assert NOT(thousand = (1,1,1,1,1)) 
+      report "***PASSED TEST: c07s03b05x00p08n01i02550" 
+      severity NOTE;
+    assert (thousand = (1,1,1,1,1)) 
+      report "***FAILED TEST: c07s03b05x00p08n01i02550 - Operand and the target type should have the same index type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p08n01i02550arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2551.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2551.vhd
new file mode 100644
index 0000000..f07a68f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2551.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2551.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p02n01i02551ent IS
+END c07s03b06x00p02n01i02551ent;
+
+ARCHITECTURE c07s03b06x00p02n01i02551arch OF c07s03b06x00p02n01i02551ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T is
+      record
+        a:integer;
+        b:integer;
+      end record;
+    type A is access T;
+    variable B1, B2: A := new T'(0, 0);
+    variable C : T;
+  BEGIN
+    C  := B1.all;
+    assert NOT(C.a = 0 and C.b = 0 )
+      report "***PASSED TEST: c07s03b06x00p02n01i02551"
+      severity NOTE;
+    assert (C.a = 0 and C.b = 0 )
+      report "***FAILED TEST: c07s03b06x00p02n01i02551 - The allocator must either consist of the reserved word new and a subtype indication or consist of the reserved word new and a qualified expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p02n01i02551arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2558.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2558.vhd
new file mode 100644
index 0000000..99ea00a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2558.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2558.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p03n02i02558ent IS
+END c07s03b06x00p03n02i02558ent;
+
+ARCHITECTURE c07s03b06x00p03n02i02558arch OF c07s03b06x00p03n02i02558ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CELL;
+    type LINK is access CELL;
+    type CELL is
+      record
+        VALUE : Bit;
+        SUCC  : Bit;
+      end record;
+    variable HEAD : LINK :=  new CELL ;
+  BEGIN
+    assert NOT(HEAD.VALUE='0')
+      report "***PASSED TEST: c07s03b06x00p03n02i02558"
+      severity NOTE;
+    assert (HEAD.VALUE='0')
+      report "***FAILED TEST: c07s03b06x00p03n02i02558 - The initial value of the created object is the same as the default initial value for an explicitly declared variable of the designated subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p03n02i02558arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2559.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2559.vhd
new file mode 100644
index 0000000..13e0af9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2559.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2559.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p05n01i02559ent IS
+END c07s03b06x00p05n01i02559ent;
+
+ARCHITECTURE c07s03b06x00p05n01i02559arch OF c07s03b06x00p05n01i02559ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CELL;
+    type LINK is access CELL;
+    type CELL is
+      record
+        VALUE : Bit;
+        SUCC  : Bit;
+      end record;
+    type T1 is access BIT_VECTOR ;
+    variable HEAD : LINK := new CELL'('1','0') ;
+    variable V2   : T1   := new BIT_VECTOR(0 to 7) ;     --- No_failure_here
+  BEGIN
+    assert NOT((V2.all="00000000") and (HEAD.VALUE='1') and (HEAD.SUCC='0'))
+      report "***PASSED TEST: c07s03b06x00p05n01i02559"
+      severity NOTE;
+    assert ((V2.all="00000000") and (HEAD.VALUE='1') and (HEAD.SUCC='0'))
+      report "***FAILED TEST: c07s03b06x00p05n01i02559 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p05n01i02559arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2562.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2562.vhd
new file mode 100644
index 0000000..4a108f8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2562.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2562.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p06n02i02562ent IS
+END c07s03b06x00p06n02i02562ent;
+
+ARCHITECTURE c07s03b06x00p06n02i02562arch OF c07s03b06x00p06n02i02562ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEM is array (Integer range <>) of Integer;
+    subtype T1 is MEM (1 to 6) ;
+    type LINK is access T1;
+    variable HEAD : LINK :=  new T1 ;
+  BEGIN
+    assert NOT(HEAD'LOW = 1)
+      report "***PASSED TEST: c07s03b06x00p06n02i02562"
+      severity NOTE;
+    assert (HEAD'LOW = 1)
+      report "***FAILED TEST: c07s03b06x00p06n02i02562 - The created object is constrained by the subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p06n02i02562arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2563.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2563.vhd
new file mode 100644
index 0000000..e208770
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2563.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2563.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p06n03i02563ent IS
+END c07s03b06x00p06n03i02563ent;
+
+ARCHITECTURE c07s03b06x00p06n03i02563arch OF c07s03b06x00p06n03i02563ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEM is array (Integer range <>) of Integer;
+    subtype T1 is MEM (1 to 6) ;
+    type LINK is access BIT_VECTOR;
+    variable HEAD : LINK :=  new BIT_VECTOR'("00110110") ;
+  BEGIN
+    assert NOT(HEAD'HIGH=7)
+      report "***PASSED TEST: c07s03b06x00p06n03i02563"
+      severity NOTE;
+    assert (HEAD'HIGH=7)
+      report "***FAILED TEST: c07s03b06x00p06n03i02563 - The created object is con strained by the bounds of the initial value defined by that expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p06n03i02563arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2564.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2564.vhd
new file mode 100644
index 0000000..85b75b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2564.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2564.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p08n01i02564ent IS
+END c07s03b06x00p08n01i02564ent;
+
+ARCHITECTURE c07s03b06x00p08n01i02564arch OF c07s03b06x00p08n01i02564ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       LINK is access BIT_VECTOR;
+    variable    HEAD : LINK :=  new BIT_VECTOR'("00110110") ;
+    variable    TAIL : LINK;
+  BEGIN
+    TAIL := HEAD;
+    wait for 1 ns;
+    assert NOT( TAIL(3) = '1' )
+      report "***PASSED TEST: c07s03b06x00p08n01i02564"
+      severity NOTE;
+    assert ( TAIL(3) = '1' )
+      report "***FAILED TEST: c07s03b06x00p08n01i02564 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p08n01i02564arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2565.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2565.vhd
new file mode 100644
index 0000000..7848d44
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2565.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2565.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s04b01x00p08n01i02565ent IS
+END c07s04b01x00p08n01i02565ent;
+
+ARCHITECTURE c07s04b01x00p08n01i02565arch OF c07s04b01x00p08n01i02565ent IS
+  SUBTYPE s10 IS STRING (1 TO 4);
+
+  ATTRIBUTE attr1 : INTEGER;
+--
+  ATTRIBUTE attr1 OF s10 : SUBTYPE IS 4;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE v : s10;
+  BEGIN
+--
+--      The expressions in a named assocition list of more than 1 element
+--      must be locally static.
+--
+    v := (1 | s10'attr1 => 'a', OTHERS => 'b' );
+    wait for 5 ns;
+    assert NOT( v="abba" )
+      report "***PASSED TEST: c07s04b01x00p08n01i02565"
+      severity NOTE;
+    assert ( v="abba" )
+      report "***FAILED TEST: c07s04b01x00p08n01i02565 - Bad value for named aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s04b01x00p08n01i02565arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2566.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2566.vhd
new file mode 100644
index 0000000..94ba289
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2566.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2566.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s04b02x00p15n01i02566ent_a IS
+  GENERIC ( gen_prm : INTEGER );
+END c07s04b02x00p15n01i02566ent_a;
+
+ARCHITECTURE c07s04b02x00p15n01i02566arch_a OF c07s04b02x00p15n01i02566ent_a IS
+  SIGNAL s : BIT;
+
+  ATTRIBUTE attr1 : INTEGER;
+  ATTRIBUTE attr1 OF s : SIGNAL IS gen_prm;
+--
+--      Usage of user-defined attribute as a globally-static expression
+--
+  CONSTANT c0 : INTEGER := s'attr1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c0 = gen_prm )
+      report "***PASSED TEST: c07s04b02x00p15n01i02566"
+      severity NOTE;
+    assert ( c0 = gen_prm )
+      report "***FAILED TEST: c07s04b02x00p15n01i02566 - Constant initialization to user-attribute value failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s04b02x00p15n01i02566arch_a;
+
+
+
+ENTITY c07s04b02x00p15n01i02566ent IS
+END c07s04b02x00p15n01i02566ent;
+
+ARCHITECTURE c07s04b02x00p15n01i02566arch OF c07s04b02x00p15n01i02566ent IS
+
+  COMPONENT c07s04b02x00p15n01i02566ent_a
+    GENERIC ( gen_prm : INTEGER );
+  END COMPONENT;
+
+  for cmp : c07s04b02x00p15n01i02566ent_a use entity work.c07s04b02x00p15n01i02566ent_a(c07s04b02x00p15n01i02566arch_a);
+
+BEGIN
+
+  cmp : c07s04b02x00p15n01i02566ent_a generic map (123);
+END c07s04b02x00p15n01i02566arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2567.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2567.vhd
new file mode 100644
index 0000000..51d8306
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2567.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2567.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s05b00x00p02n01i02567ent IS
+END c07s05b00x00p02n01i02567ent;
+
+ARCHITECTURE c07s05b00x00p02n01i02567arch OF c07s05b00x00p02n01i02567ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(2E6 = (2E3*1E3))
+      report "***PASSED TEST: c07s05b00x00p02n01i02567"
+      severity NOTE;
+    assert (2E6 = (2E3*1E3))
+      report "***FAILED TEST: c07s05b00x00p02n01i02567 - The same operations are defined for the type universal_integer as for any integer type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s05b00x00p02n01i02567arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2569.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2569.vhd
new file mode 100644
index 0000000..86460b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2569.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2569.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s05b00x00p16n02i02569ent IS
+END c07s05b00x00p16n02i02569ent;
+
+ARCHITECTURE c07s05b00x00p16n02i02569arch OF c07s05b00x00p16n02i02569ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(2E6 = (2E3*1E3))
+      report "***PASSED TEST: c07s05b00x00p16n02i02569"
+      severity NOTE;
+    assert ( 2E6 = (2E3*1E3) )
+      report "***FAILED TEST: c07s05b00x00p16n02i02569 - The values of the operands and the result lie within the range of the integer type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s05b00x00p16n02i02569arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2570.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2570.vhd
new file mode 100644
index 0000000..c85b28e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2570.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2570.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s05b00x00p16n02i02570ent IS
+END c07s05b00x00p16n02i02570ent;
+
+ARCHITECTURE c07s05b00x00p16n02i02570arch OF c07s05b00x00p16n02i02570ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(2.12E6 = (1.06E3*2.0E3))
+      report "***PASSED TEST: c07s05b00x00p16n02i02570"
+      severity NOTE;
+    assert ( 2.12E6 = (1.06E3*2.0E3) ) 
+      report "***FAILED TEST: c07s05b00x00p16n02i02570 - The values of the operands and the result lie within the range of the floating point type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s05b00x00p16n02i02570arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2573.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2573.vhd
new file mode 100644
index 0000000..5f41d55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2573.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2573.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s02b00x00p02n01i02573ent IS
+  type ONE    is range 10#1#    to 1;
+  type TWO    is range 2    to 2;
+  type THREE    is range 3    to 3;
+  type FOUR    is range 4    to 4;
+  type A1    is array(FOUR range<>)of FOUR;
+  type FIVE    is range 1    to 5;
+  type U1    is range 1    to 200
+    units
+      SINGLE;
+      EVEN   =2 SINGLE;
+      DOUBLE   =10#1#E1 EVEN;
+      QUAD   =2E1 EVEN;
+    end units;
+END c13s02b00x00p02n01i02573ent;
+
+ARCHITECTURE c13s02b00x00p02n01i02573arch OF c13s02b00x00p02n01i02573ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c13s02b00x00p02n01i02573"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s02b00x00p02n01i02573arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2575.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2575.vhd
new file mode 100644
index 0000000..adeca5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2575.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2575.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s02b00x00p02n02i02575ent IS
+END c13s02b00x00p02n02i02575ent;
+
+ARCHITECTURE c13s02b00x00p02n02i02575arch OF c13s02b00x00p02n02i02575ent IS
+  type MEM is range 4 to 5;     -- Space is a separator except in this comment section
+  type M1  is range 2 to 4;     -- End of line is a separator between the
+  -- earlier comment section and this type.
+BEGIN
+  TESTING: PROCESS
+    variable j : MEM := 4;
+    variable n : M1  := 2;
+  BEGIN
+    assert NOT(j=4 and n=2) 
+      report "***PASSED TEST: c13s02b00x00p02n02i02575"
+      severity NOTE;
+    assert (j=4 and n=2) 
+      report "***FAILED TEST: c13s02b00x00p02n02i02575 - Lexical test failed."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s02b00x00p02n02i02575arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2578.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2578.vhd
new file mode 100644
index 0000000..628008b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2578.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2578.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s02b00x00p05n01i02578ent IS
+END c13s02b00x00p05n01i02578ent;
+
+ARCHITECTURE c13s02b00x00p05n01i02578arch OF c13s02b00x00p05n01i02578ent IS
+  constant c1: character :='A';   -- NO_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(c1 = 'A') 
+      report "***PASSED TEST: c13s02b00x00p05n01i02578" 
+      severity NOTE;
+    assert (c1 = 'A') 
+      report "***FAILED TEST: c13s02b00x00p05n01i02578 - Lexical delimiter test failed." 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s02b00x00p05n01i02578arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc258.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc258.vhd
new file mode 100644
index 0000000..282dd2a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc258.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc258.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p08n01i00258ent IS
+END c03s01b02x00p08n01i00258ent;
+
+ARCHITECTURE c03s01b02x00p08n01i00258arch OF c03s01b02x00p08n01i00258ent IS
+BEGIN
+  TESTING: PROCESS
+    variable V1 : integer := -2147483647;  -- No_failure_here
+    variable V2 : integer := +2147483647;  -- No_failure_here
+  BEGIN
+    assert NOT( V1 = -2147483647 and V2 = +2147483647 ) 
+      report "***PASSED TEST: c03s01b02x00p08n01i00258" 
+      severity NOTE;
+    assert ( V1 = -2147483647 and V2 = +2147483647 ) 
+      report "***FAILED TEST: c03s01b02x00p08n01i00258 - Integer declared outside bounds."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p08n01i00258arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc26.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc26.vhd
new file mode 100644
index 0000000..c959df3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc26.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc26.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p10n02i00026ent IS
+END c04s02b00x00p10n02i00026ent;
+
+ARCHITECTURE c04s02b00x00p10n02i00026arch OF c04s02b00x00p10n02i00026ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define an ascending subtype.
+    subtype ASC_B is INTEGER range 0 to 1;
+    subtype ASC is ASC_B;
+
+    -- Define a descending subtype.
+    subtype DES_B is INTEGER range 1 downto 0;
+    subtype DES is DES_B;
+
+    -- Define a 'previous value' variable.
+    variable PREV : INTEGER;
+
+    variable k : integer := 0;
+    variable l : integer := 0;
+  BEGIN
+
+    -- Test the direction of the ascending range.
+    PREV := 0;
+    for I in ASC loop
+      if (I >= PREV) then
+        PREV := I;
+      else
+        k := 1;
+      end if;
+    end loop;
+
+    -- Test the direction of the descending range.
+    PREV := 1;
+    for I in DES loop
+      if (I <= PREV) then
+        PREV := I;
+      else
+        l := 1;
+      end if;
+    end loop;
+
+    assert NOT( k=0 and l=0 )
+      report "***PASSED TEST: c04s02b00x00p10n02i00026"
+      severity NOTE;
+    assert ( k=0 and l=0 )
+      report "***FAILED TEST: c04s02b00x00p10n02i00026 - The direction of a discrete subtype indication is the same as that of the denoted subtype in the absence of an explicit type constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p10n02i00026arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2642.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2642.vhd
new file mode 100644
index 0000000..ecc3acb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2642.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2642.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTI is
+end;
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTIT is
+end;
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTITY is
+end;
+
+entity This_Entity_Name_Is_Not_Long is
+end;
+
+architecture This_Arch_Name_Is_Not_Long of This_Entity_Name_Is_Not_Long is
+begin
+end;
+
+ENTITY c13s03b01x00p02n01i02642ent IS
+END c13s03b01x00p02n01i02642ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02642arch OF c13s03b01x00p02n01i02642ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c13s03b01x00p02n01i02642" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02642arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2643.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2643.vhd
new file mode 100644
index 0000000..fccf425
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2643.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2643.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTI is
+end;
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTIT is
+end;
+
+entity THIS_IS_A_PRETTY_LONG_NAME_FOR_AN_ENTITY is
+end;
+
+entity This_Entity_Name_Is_Not_Long is
+end;
+
+architecture This_Arch_Name_Is_Not_Long of This_Entity_Name_Is_Not_Long is
+begin
+end;
+
+ENTITY c13s03b01x00p02n01i02643ent IS
+END c13s03b01x00p02n01i02643ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02643arch OF c13s03b01x00p02n01i02643ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c13s03b01x00p02n01i02643" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02643arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc265.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc265.vhd
new file mode 100644
index 0000000..9f489b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc265.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc265.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p02n01i00265ent IS
+END c03s01b03x00p02n01i00265ent;
+
+ARCHITECTURE c03s01b03x00p02n01i00265arch OF c03s01b03x00p02n01i00265ent IS
+  type J is           -- physical type decl
+    range 0 to 1000
+    units
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+  type J1 is access J;   -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : J; 
+  BEGIN
+    k := 10 C;
+    assert NOT( k=100 B )
+      report "***PASSED TEST: c03s01b03x00p02n01i00265"
+      severity NOTE;
+    assert ( k=100 B)
+      report "***FAILED TEST: c03s01b03x00p02n01i00265 - In the physical type definition, the range constraint is immediately followed by reserved word units."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p02n01i00265arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2675.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2675.vhd
new file mode 100644
index 0000000..8f28517
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2675.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2675.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p04n01i02675ent IS
+END c13s03b01x00p04n01i02675ent;
+
+ARCHITECTURE c13s03b01x00p04n01i02675arch OF c13s03b01x00p04n01i02675ent IS
+  constant Qwerty_tyur_RT_456T : Integer := 10 ; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( Qwerty_tyur_RT_456T = 10 )
+      report "***PASSED TEST: c13s03b01x00p04n01i02675"
+      severity NOTE;
+    assert ( Qwerty_tyur_RT_456T = 10 )
+      report "***FAILED TEST: c13s03b01x00p04n01i02675 - Both upper and lower case letter should be able used in an identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p04n01i02675arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2676.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2676.vhd
new file mode 100644
index 0000000..00cf372
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2676.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2676.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p05n01i02676ent IS
+END c13s03b01x00p05n01i02676ent;
+
+ARCHITECTURE c13s03b01x00p05n01i02676arch OF c13s03b01x00p05n01i02676ent IS
+  constant   a234567_10_234567_20_234567a : integer := 2;
+  constant   a234567_10_234567_20_234567b : integer := 7;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
+      report "***PASSED TEST: c13s03b01x00p05n01i02676"
+      severity NOTE;
+    assert ( a234567_10_234567_20_234567a /= a234567_10_234567_20_234567b )
+      report "***FAILED TEST: c13s03b01x00p05n01i02676 - All characters of an identifier are significant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p05n01i02676arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2677.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2677.vhd
new file mode 100644
index 0000000..945287b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2677.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2677.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p05n01i02677ent IS
+END c13s03b01x00p05n01i02677ent;
+
+ARCHITECTURE c13s03b01x00p05n01i02677arch OF c13s03b01x00p05n01i02677ent IS
+  constant   a234567_aa : integer := 2;
+  constant   a234567aa  : integer := 7;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a234567_aa /= a234567aa )
+      report "***PASSED TEST: c13s03b01x00p05n01i02677"
+      severity NOTE;
+    assert ( a234567_aa /= a234567aa )
+      report "***FAILED TEST: c13s03b01x00p05n01i02677 - All characters of an identifier are significant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p05n01i02677arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2679.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2679.vhd
new file mode 100644
index 0000000..fde19bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2679.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2679.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c13s03b01x00p05n02i02679pkg is
+  fUnction F rEturn BooLEAN;
+end c13s03b01x00p05n02i02679pkg ;
+
+package body c13s03b01x00p05n02i02679pkg is
+  fUnction F rEturn BooLEAN is
+    tYpe TyP_1 is ranGe 1 to 10;
+    suBtyPe STYp_1 is TYP_1 range 1 to 5;
+    type ReC_1 is rEcorD
+                    RV_1: BOOlean;
+                    RV_2: intEGER;
+                    RV_3: REal;
+                  end RECord;
+    VariabLe V1: STYP_1;
+  beGin
+    v1 := 4;
+    rETurn FalSe;
+  enD f;
+end c13s03b01x00p05n02i02679pkg ;
+
+ENTITY c13s03b01x00p05n02i02679ent IS
+END c13s03b01x00p05n02i02679ent;
+
+ARCHITECTURE c13s03b01x00p05n02i02679arch OF c13s03b01x00p05n02i02679ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c13s03b01x00p05n02i02679"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p05n02i02679arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2690.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2690.vhd
new file mode 100644
index 0000000..eef9bff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2690.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2690.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02690ent IS
+  constant TIP_OFTHEICE    : Integer := 10 ;
+  constant TIPOFTHEICE     : Real    := 0.546 ;
+  constant T1       : Real := 3.14159_26 ;
+  constant T2       : Real := 1.0E+6 ; --- No_failure_here
+END c13s04b01x00p02n01i02690ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02690arch OF c13s04b01x00p02n01i02690ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   TIP_OFTHEICE = 10   and
+                  TIPOFTHEICE  = 0.546   and
+                  T1        =3.14159_26   and
+                  T2        = 1.0E+6   )
+      report "***PASSED TEST: c13s04b01x00p02n01i02690"
+      severity NOTE;
+    assert (   TIP_OFTHEICE = 10   and
+               TIPOFTHEICE  = 0.546   and
+               T1        =3.14159_26   and
+               T2        = 1.0E+6   )
+      report "***FAILED TEST: c13s04b01x00p02n01i02690 - Correct decimal literal test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02690arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2697.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2697.vhd
new file mode 100644
index 0000000..86984f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2697.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2697.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n01i02697ent IS
+END c13s04b01x00p05n01i02697ent;
+
+ARCHITECTURE c13s04b01x00p05n01i02697arch OF c13s04b01x00p05n01i02697ent IS
+  constant   a : real := 2.34;
+  constant   b : real := 2.3_4;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a=b )
+      report "***PASSED TEST: c13s04b01x00p05n01i02697"
+      severity NOTE;
+    assert ( a=b )
+      report "***FAILED TEST: c13s04b01x00p05n01i02697 - The underline character inserted between adjacent digits of a real literal should not affect the value of this abstract literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n01i02697arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2698.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2698.vhd
new file mode 100644
index 0000000..03194cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2698.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2698.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n01i02698ent IS
+END c13s04b01x00p05n01i02698ent;
+
+ARCHITECTURE c13s04b01x00p05n01i02698arch OF c13s04b01x00p05n01i02698ent IS
+  constant   a : real := 234.1;
+  constant   b : real := 23_4.1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a=b )
+      report "***PASSED TEST: c13s04b01x00p05n01i02698"
+      severity NOTE;
+    assert ( a=b )
+      report "***FAILED TEST: c13s04b01x00p05n01i02698 - The underline character inserted between adjacent digits of a decimal literal should not affect the value of this abstract literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n01i02698arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2699.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2699.vhd
new file mode 100644
index 0000000..713efd1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2699.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2699.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n01i02699ent IS
+END c13s04b01x00p05n01i02699ent;
+
+ARCHITECTURE c13s04b01x00p05n01i02699arch OF c13s04b01x00p05n01i02699ent IS
+  constant   a : integer := 234;
+  constant   b : integer := 2_3_4;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a=b )
+      report "***PASSED TEST: c13s04b01x00p05n01i02699"
+      severity NOTE;
+    assert ( a=b )
+      report "***FAILED TEST: c13s04b01x00p05n01i02699 - The underline character inserted between adjacent digits of an integer literal should not affect the value of this abstract literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n01i02699arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc27.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc27.vhd
new file mode 100644
index 0000000..a11725b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc27.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc27.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p10n04i00027ent IS
+END c04s02b00x00p10n04i00027ent;
+
+ARCHITECTURE c04s02b00x00p10n04i00027arch OF c04s02b00x00p10n04i00027ent IS
+
+  subtype s1 is integer range 1  to 10;      -- No_failure_here
+  subtype s2 is integer range 10 downto 1;   -- No_failure_here
+
+  -- the following are null ranges
+  subtype s3 is integer range 1  downto 10;  -- No_failure_here
+  subtype s4 is integer range 10 to 1;       -- No_failure_here
+  
+BEGIN
+  TESTING: PROCESS
+    variable k1 : s1 := 1;
+    variable k2 : s2 := 10;
+    variable k  : integer := 0;
+  BEGIN
+    for i in s1 loop
+      if (i /= k1) then
+        k := 1;
+      end if;
+      if (k1 < 10) then
+        k1 := k1 + 1;
+      end if;
+    end loop;
+    for i in s2 loop
+      if (i /= k2) then
+        k := 1;
+      end if;
+      if (k2 > 1) then
+        k2 := k2 - 1;
+      end if;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c04s02b00x00p10n04i00027"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c04s02b00x00p10n04i00027 - The direction of a discrete subtype is the same as the direction of its subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p10n04i00027arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2700.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2700.vhd
new file mode 100644
index 0000000..7886fbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2700.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2700.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n02i02700ent IS
+END c13s04b01x00p05n02i02700ent;
+
+ARCHITECTURE c13s04b01x00p05n02i02700arch OF c13s04b01x00p05n02i02700ent IS
+  constant   i : real := 12.3E6;
+  constant   e : real := 12.3e6;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(i = e)
+      report "***PASSED TEST: c13s04b01x00p05n02i02700"
+      severity NOTE;
+    assert ( i= e )
+      report "***FAILED TEST: c13s04b01x00p05n02i02700 - The letter E of the exponent of the real can be written either in lower case or in upper case with the same meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n02i02700arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2701.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2701.vhd
new file mode 100644
index 0000000..9af2db7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2701.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2701.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n02i02701ent IS
+END c13s04b01x00p05n02i02701ent;
+
+ARCHITECTURE c13s04b01x00p05n02i02701arch OF c13s04b01x00p05n02i02701ent IS
+  constant   i : integer := 12E6;
+  constant   e : integer := 12e6;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(i = e)
+      report "***PASSED TEST: c13s04b01x00p05n02i02701"
+      severity NOTE;
+    assert ( i= e )
+      report "***FAILED TEST: c13s04b01x00p05n02i02701 - The letter E of the exponent of the integer can be written either in lower case or in upper case with the same meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n02i02701arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2702.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2702.vhd
new file mode 100644
index 0000000..3791815
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2702.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2702.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p05n02i02702ent IS
+END c13s04b01x00p05n02i02702ent;
+
+ARCHITECTURE c13s04b01x00p05n02i02702arch OF c13s04b01x00p05n02i02702ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(      (1e2 = 1E2)
+                     and    (1.2e1 = 1.2E1)
+                     and    (1.2e-1 = 1.2E-1)
+                     and    (16#F#e1 = 16#F#E1)
+                     and    (16#F.F#e1 = 16#F.F#E1))
+      report "***PASSED TEST: c13s04b01x00p05n02i02702"
+      severity NOTE;
+    assert (      (1e2 = 1E2)
+                  and    (1.2e1 = 1.2E1)
+                  and    (1.2e-1 = 1.2E-1)
+                  and    (16#F#e1 = 16#F#E1)
+                  and    (16#F.F#e1 = 16#F.F#E1))
+      report "***FAILED TEST: c13s04b01x00p05n02i02702 - Upper case and lower case E that used to indicate exponent in both integer and real literals test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p05n02i02702arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2703.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2703.vhd
new file mode 100644
index 0000000..2429f6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2703.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2703.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p06n01i02703ent IS
+END c13s04b01x00p06n01i02703ent;
+
+ARCHITECTURE c13s04b01x00p06n01i02703arch OF c13s04b01x00p06n01i02703ent IS
+  constant   i : real := 12.3;
+  constant   m : real := 1.23e1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( i=m )
+      report "***PASSED TEST: c13s04b01x00p06n01i02703"
+      severity NOTE;
+    assert ( i=m )
+      report "***FAILED TEST: c13s04b01x00p06n01i02703 - An exponent indicaters the power of ten to obtain the value of the decimal literal without the exponent." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p06n01i02703arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2704.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2704.vhd
new file mode 100644
index 0000000..b64f41d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2704.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2704.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p06n01i02704ent IS
+END c13s04b01x00p06n01i02704ent;
+
+ARCHITECTURE c13s04b01x00p06n01i02704arch OF c13s04b01x00p06n01i02704ent IS
+  constant   i : integer := 12300;
+  constant   m : integer := 123e2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( i=m )
+      report "***PASSED TEST: c13s04b01x00p06n01i02704"
+      severity NOTE;
+    assert ( i=m )
+      report "***FAILED TEST: c13s04b01x00p06n01i02704 - An exponent indicaters the power of ten to obtain the value of the decimal literal without the exponent." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p06n01i02704arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2705.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2705.vhd
new file mode 100644
index 0000000..66d3355
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2705.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2705.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p06n01i02705ent IS
+END c13s04b01x00p06n01i02705ent;
+
+ARCHITECTURE c13s04b01x00p06n01i02705arch OF c13s04b01x00p06n01i02705ent IS
+  constant   i : real := 0.12;
+  constant   m : real := 1.2e-1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( abs(i-m) < 0.00000000001 )
+      report "***PASSED TEST: c13s04b01x00p06n01i02705"
+      severity NOTE;
+    assert ( abs(i-m) < 0.00000000001 )
+      report "***FAILED TEST: c13s04b01x00p06n01i02705 - An exponent indicaters the power of ten to obtain the value of the decimal literal without the exponent." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p06n01i02705arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2707.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2707.vhd
new file mode 100644
index 0000000..9d5d313
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2707.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2707.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p11n01i02707ent IS
+END c13s04b01x00p11n01i02707ent;
+
+ARCHITECTURE c13s04b01x00p11n01i02707arch OF c13s04b01x00p11n01i02707ent IS
+  constant   i : integer := 003;
+  constant   k : integer :=   3;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( i=k )
+      report "***PASSED TEST: c13s04b01x00p11n01i02707"
+      severity NOTE;
+    assert ( i=k )
+      report "***FAILED TEST: c13s04b01x00p11n01i02707 - Leading zeros should be allowed for an integer literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p11n01i02707arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2708.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2708.vhd
new file mode 100644
index 0000000..95bc8c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2708.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2708.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p11n01i02708ent IS
+END c13s04b01x00p11n01i02708ent;
+
+ARCHITECTURE c13s04b01x00p11n01i02708arch OF c13s04b01x00p11n01i02708ent IS
+  constant   i : real := 00567.8;
+  constant   k : real :=   567.8;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( i=k )
+      report "***PASSED TEST: c13s04b01x00p11n01i02708"
+      severity NOTE;
+    assert ( i=k )
+      report "***FAILED TEST: c13s04b01x00p11n01i02708 - Leading zeros should be allowed for an real literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p11n01i02708arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2709.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2709.vhd
new file mode 100644
index 0000000..a026f2a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2709.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2709.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p13n01i02709ent IS
+END c13s04b01x00p13n01i02709ent;
+
+ARCHITECTURE c13s04b01x00p13n01i02709arch OF c13s04b01x00p13n01i02709ent IS
+  constant   k : integer := 3E0;
+  constant   i : integer := 3  ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( k=i )
+      report "***PASSED TEST: c13s04b01x00p13n01i02709"
+      severity NOTE;
+    assert ( k=i )
+      report "***FAILED TEST: c13s04b01x00p13n01i02709 - A zero exponent should be allowed for an integer liiteral."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p13n01i02709arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2710.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2710.vhd
new file mode 100644
index 0000000..e8b694d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2710.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2710.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p11n01i02710ent IS
+END c13s04b01x00p11n01i02710ent;
+
+ARCHITECTURE c13s04b01x00p11n01i02710arch OF c13s04b01x00p11n01i02710ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(       (5 = 000005)
+                      and (10#030# = 10#30#)
+                      and (1E004 = 1E4)
+                      and (10#01_2#E1 = 0010#1_2#E1)) 
+      report "***PASSED TEST: c13s04b01x00p11n01i02710"
+      severity NOTE;
+    assert (       (5 = 000005)
+                   and (10#030# = 10#30#)
+                   and (1E004 = 1E4)
+                   and (10#01_2#E1 = 0010#1_2#E1)) 
+      report "***FAILED TEST: c13s04b01x00p11n01i02710 - Leading zeros should be allowed in integral parts of integer literals."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p11n01i02710arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2711.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2711.vhd
new file mode 100644
index 0000000..d5125a1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2711.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2711.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p01n01i02711ent IS
+END c13s04b02x00p01n01i02711ent;
+
+ARCHITECTURE c13s04b02x00p01n01i02711arch OF c13s04b02x00p01n01i02711ent IS
+  constant   two   : integer := 2#1111_1111#;
+  constant   sixteen   : integer := 16#FF#;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( two=sixteen )
+      report "***PASSED TEST: c13s04b02x00p01n01i02711"
+      severity NOTE;
+    assert ( two=sixteen )
+      report "***FAILED TEST: c13s04b02x00p01n01i02711 - Integer 255 in the base of 2 and 16 should be equal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p01n01i02711arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2712.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2712.vhd
new file mode 100644
index 0000000..2a3924a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2712.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2712.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p01n01i02712ent IS
+END c13s04b02x00p01n01i02712ent;
+
+ARCHITECTURE c13s04b02x00p01n01i02712arch OF c13s04b02x00p01n01i02712ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(      (2#11#=3)
+                     and    (7#66#=48)
+                     and    (12#BB#=143)
+                     and    (16#FF#=255)) 
+      report "***PASSED TEST: c13s04b02x00p01n01i02712"
+      severity NOTE;
+    assert (      (2#11#=3)
+                  and    (7#66#=48)
+                  and    (12#BB#=143)
+                  and    (16#FF#=255)) 
+      report "***FAILED TEST: c13s04b02x00p01n01i02712 - Correct based literal test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p01n01i02712arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2713.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2713.vhd
new file mode 100644
index 0000000..f6b7987
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2713.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2713.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p01n01i02713ent IS
+END c13s04b02x00p01n01i02713ent;
+
+ARCHITECTURE c13s04b02x00p01n01i02713arch OF c13s04b02x00p01n01i02713ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   16#F.FF#E+2 = 2#1.1111_1111_111#E11   and
+                  16#F.FF#E+2 = 4095.0   ) 
+      report "***PASSED TEST: c13s04b02x00p01n01i02713"
+      severity NOTE;
+    assert (   16#F.FF#E+2 = 2#1.1111_1111_111#E11   and
+               16#F.FF#E+2 = 4095.0   ) 
+      report "***FAILED TEST: c13s04b02x00p01n01i02713 - Base literals expressed in two and sixteen test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p01n01i02713arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2718.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2718.vhd
new file mode 100644
index 0000000..89905c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2718.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2718.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p02n01i02718ent IS
+END c13s04b02x00p02n01i02718ent;
+
+ARCHITECTURE c13s04b02x00p02n01i02718arch OF c13s04b02x00p02n01i02718ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable total_time : real := 5#1234.4321#E-10;   --No_failure_here
+  BEGIN
+    wait for 5 ns;
+    assert NOT( total_time = 5#1234.4321#E-10 )
+      report "***PASSED TEST: c13s04b02x00p02n01i02718"
+      severity NOTE;
+    assert ( total_time = 5#1234.4321#E-10 )
+      report "***FAILED TEST: c13s04b02x00p02n01i02718 - Based literal literal test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p02n01i02718arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2719.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2719.vhd
new file mode 100644
index 0000000..eda6823
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2719.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2719.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p03n01i02719ent IS
+END c13s04b02x00p03n01i02719ent;
+
+ARCHITECTURE c13s04b02x00p03n01i02719arch OF c13s04b02x00p03n01i02719ent IS
+  constant T1 : Integer := 16#E#E1;
+  constant T2 : Real    := 5#1234.4321#; --- No_Failure_here
+
+  constant T3 : Integer := 2#1111_1111#;
+  constant T4 : Integer := 16#FF#;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   T1 = 16#E#E1      and
+                  T2 = 5#1234.4321#   and
+                  T3 = 2#1111_1111#   and
+                  T4 = 16#FF#      )   
+      report "***PASSED TEST: c13s04b02x00p03n01i02719" 
+      severity NOTE;
+    assert (   T1 = 16#E#E1      and
+               T2 = 5#1234.4321#   and
+               T3 = 2#1111_1111#   and
+               T4 = 16#FF#      )   
+      report "***FAILED TEST: c13s04b02x00p03n01i02719 - Base literal as an integer test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p03n01i02719arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc272.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc272.vhd
new file mode 100644
index 0000000..5d1289c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc272.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc272.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p06n01i00272ent IS
+END c03s01b03x00p06n01i00272ent;
+
+ARCHITECTURE c03s01b03x00p06n01i00272arch OF c03s01b03x00p06n01i00272ent IS
+  type small is range 0 to 2_000_000_000      --   < 2**31-1
+    units
+      lu;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable   smaller : small;
+  BEGIN
+    smaller := 2000000000 lu;
+    wait for 5 ns;
+    assert NOT( smaller = 2000000000 lu ) 
+      report "***PASSED TEST: c03s01b03x00p06n01i00272" 
+      severity NOTE;
+    assert ( smaller = 2000000000 lu ) 
+      report "***FAILED TEST: c03s01b03x00p06n01i00272 - Large physical type declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p06n01i00272arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2722.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2722.vhd
new file mode 100644
index 0000000..e8f06bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2722.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2722.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p06n01i02722ent IS
+END c13s04b02x00p06n01i02722ent;
+
+ARCHITECTURE c13s04b02x00p06n01i02722arch OF c13s04b02x00p06n01i02722ent IS
+  constant a1:integer   :=16#987_654#;
+  constant b1:integer   :=16#987654#;
+  constant a2:integer   :=16#A_B#;
+  constant b2:integer   :=16#AB#;
+  constant a3:integer   :=10#7_8#;
+  constant b3:integer   :=10#78#;
+  constant a4:integer   :=2#11_11#;
+  constant b4:integer   :=2#1111#;
+  constant a5:real   :=16#C.C_D#;
+  constant b5:real   :=16#C.CD#;
+  constant a6:real   :=10#8.9_7#;
+  constant b6:real   :=10#8.97#;
+  constant a7:real   :=2#11_11.11_11#;
+  constant b7:real   :=2#1111.1111#;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert (a1=b1) report "Underline affects the value of a based literal" severity failure;
+    assert (a2=b2) report "Underline affects the value of a based literal" severity failure;
+    assert (a3=b3) report "Underline affects the value of a based literal" severity failure;
+    assert (a4=b4) report "Underline affects the value of a based literal" severity failure;
+    assert (a5=b5) report "Underline affects the value of a based literal" severity failure;
+    assert (a6=b6) report "Underline affects the value of a based literal" severity failure;
+    assert (a7=b7) report "Underline affects the value of a based literal" severity failure;
+    assert NOT(   a1=b1   and
+                  a2=b2   and
+                  a3=b3   and
+                  a4=b4   and
+                  a5=b5   and
+                  a6=b6   and
+                  a7=b7   )
+      report "***PASSED TEST: c13s04b02x00p06n01i02722"
+      severity NOTE;
+    assert (   a1=b1   and
+               a2=b2   and
+               a3=b3   and
+               a4=b4   and
+               a5=b5   and
+               a6=b6   and
+               a7=b7   )
+      report "***FAILED TEST: c13s04b02x00p06n01i02722 - An underline character inserted between adjacent digits of a based literal does not affect the value of this abstract literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p06n01i02722arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2724.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2724.vhd
new file mode 100644
index 0000000..ff4075e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2724.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2724.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p06n04i02724ent IS
+END c13s04b02x00p06n04i02724ent;
+
+ARCHITECTURE c13s04b02x00p06n04i02724arch OF c13s04b02x00p06n04i02724ent IS
+  constant a1   :integer:=16#A#;
+  constant b1   :integer:=16#a#;
+  constant a2   :integer:=16#B#;
+  constant b2   :integer:=16#b#;
+  constant a3   :integer:=16#C#;
+  constant b3   :integer:=16#c#;
+  constant a4   :integer:=16#D#;
+  constant b4   :integer:=16#d#;
+  constant a5   :integer:=16#E#;
+  constant b5   :integer:=16#e#;
+  constant a6   :integer:=16#F#;
+  constant b6   :integer:=16#f#;
+
+  constant a7   :real:=16#A.A#;
+  constant b7   :real:=16#a.a#;
+  constant a8   :real:=16#B.B#;
+  constant b8   :real:=16#b.b#;
+  constant a9   :real:=16#C.C#;
+  constant b9   :real:=16#c.c#;
+  constant a10   :real:=16#D.D#;
+  constant b10   :real:=16#d.d#;
+  constant a11   :real:=16#E.E#;
+  constant b11   :real:=16#e.e#;
+  constant a12   :real:=16#F.F#;
+  constant b12   :real:=16#f.f#;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert (a1=b1) report "A & a not the same for an extended digit in an integer based literal" severity failure;
+    assert (a2=b2) report "B & b not the same for an extended digit in an integer based literal" severity failure;
+    assert (a3=b3) report "C & c not the same for an extended digit in an integer based literal" severity failure;
+    assert (a4=b4) report "D & d not the same for an extended digit in an integer based literal" severity failure;
+    assert (a5=b5) report "E & e not the same for an extended digit in an integer based literal" severity failure;
+    assert (a6=b6) report "F & f not the same for an extended digit in an integer based literal" severity failure;
+    
+    assert (a7=b7) report "A & a not the same for an extended digit in a real based literal" severity failure;
+    assert (a8=b8) report "B & b not the same for an extended digit in a real based literal" severity failure;
+    assert (a9=b9) report "C & c not the same for an extended digit in a real based literal" severity failure;
+    assert (a10=b10) report "D & d not the same for an extended digit in a real based literal" severity failure;
+    assert (a11=b11) report "E & e not the same for an extended digit in a real based literal" severity failure;
+    assert (a12=b12) report "F & f not the same for an extended digit in a real based literal" severity failure;
+    assert NOT(    a1   = b1    and
+                   a2   = b2   and
+                   a3   = b3   and
+                   a4   = b4   and
+                   a5   = b5   and
+                   a6   = b6   and
+                   a7   = b7   and
+                   a8   = b8   and
+                   a9   = b9   and
+                   a10   = b10   and
+                   a11   = b11   and
+                   a12   = b12   )
+      report "***PASSED TEST: c13s04b02x00p06n04i02724"
+      severity NOTE;
+    assert (    a1   = b1    and
+                a2   = b2   and
+                a3   = b3   and
+                a4   = b4   and
+                a5   = b5   and
+                a6   = b6   and
+                a7   = b7   and
+                a8   = b8   and
+                a9   = b9   and
+                a10   = b10   and
+                a11   = b11   and
+                a12   = b12   )
+      report "***FAILED TEST: c13s04b02x00p06n04i02724 - Upper and lower case should be allowed for a letter in integer and real based literal with the came meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p06n04i02724arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2725.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2725.vhd
new file mode 100644
index 0000000..ed50cc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2725.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2725.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p06n03i02725ent IS
+END c13s04b02x00p06n03i02725ent;
+
+ARCHITECTURE c13s04b02x00p06n03i02725arch OF c13s04b02x00p06n03i02725ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(       (16#ABCDEF#=16#abcdef#)
+                      and    (16#abcd.EF#=16#ABCD.ef#))
+      report "***PASSED TEST: c13s04b02x00p06n03i02725"
+      severity NOTE;
+    assert (       (16#ABCDEF#=16#abcdef#)
+                   and    (16#abcd.EF#=16#ABCD.ef#))
+      report "***FAILED TEST: c13s04b02x00p06n03i02725d - The only letters allowed as extended digits are the letters A through F."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p06n03i02725arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2726.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2726.vhd
new file mode 100644
index 0000000..33ef3e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2726.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2726.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p07n02i02726ent IS
+END c13s04b02x00p07n02i02726ent;
+
+ARCHITECTURE c13s04b02x00p07n02i02726arch OF c13s04b02x00p07n02i02726ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( 16#E#E1 = 224 )
+      report "***PASSED TEST: c13s04b02x00p07n02i02726"
+      severity NOTE;
+    assert ( 16#E#E1 = 224 )
+      report "***FAILED TEST: c13s04b02x00p07n02i02726 - Value of a based literal with the exponent test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p07n02i02726arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2733.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2733.vhd
new file mode 100644
index 0000000..89bb05c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2733.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2733.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s05b00x00p01n01i02733ent IS
+END c13s05b00x00p01n01i02733ent;
+
+ARCHITECTURE c13s05b00x00p01n01i02733arch OF c13s05b00x00p01n01i02733ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type      grph is array (1 to 95) of character;
+    variable   k : grph;
+  BEGIN
+    k(1) := 'A';
+    k(2) := 'B';
+    assert NOT(   k(1) = 'A'   and
+                  k(2) = 'B'   ) 
+      report "***PASSED TEST: c13s05b00x00p01n01i02733"
+      severity NOTE;
+    assert (   k(1) = 'A'   and
+               k(2) = 'B'   ) 
+      report "***FAILED TEST: c13s05b00x00p01n01i02733 - Graphic charcters be used as a character literal test fail." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s05b00x00p01n01i02733arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2734.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2734.vhd
new file mode 100644
index 0000000..7b1dead
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2734.vhd
@@ -0,0 +1,333 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2734.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s05b00x00p01n01i02734ent IS
+END c13s05b00x00p01n01i02734ent;
+
+ARCHITECTURE c13s05b00x00p01n01i02734arch OF c13s05b00x00p01n01i02734ent IS
+
+BEGIN
+   TESTING: PROCESS
+    type      grph is array (1 to 95) of character;
+    variable   k : grph;
+   BEGIN
+      k(1)  := 'A';
+      k(2)  := 'B';
+      k(3)  := 'C';
+      k(4)  := 'D';
+      k(5)  := 'E';
+      k(6)  := 'F';
+      k(7)  := 'G';
+      k(8)  := 'H';
+      k(9)  := 'I';
+      k(10) := 'J';
+      k(11) := 'K';
+      k(12) := 'L';
+      k(13) := 'M';
+      k(14) := 'N';
+      k(15) := 'O';
+      k(16) := 'P';
+      k(17) := 'Q';
+      k(18) := 'R';
+      k(19) := 'S';
+      k(20) := 'T';
+      k(21) := 'U';
+      k(22) := 'V';
+      k(23) := 'W';
+      k(24) := 'X';
+      k(25) := 'Y';
+      k(26) := 'Z';
+      k(27) := '0';
+      k(28) := '1';
+      k(29) := '2';
+      k(30) := '3';
+      k(31) := '4';
+      k(32) := '5';
+      k(33) := '6';
+      k(34) := '7';
+      k(35) := '8';
+      k(36) := '9';
+      k(37) := '"';
+      k(38) := '#';
+      k(39) := '&';
+      k(40) := ''';
+      k(41) := '(';
+      k(42) := ')';
+      k(43) := '*';
+      k(44) := '+';
+      k(45) := ',';
+      k(46) := '-';
+      k(47) := '.';
+      k(48) := '/';
+      k(49) := ':';
+      k(50) := ';';
+      k(51) := '<';
+      k(52) := '=';
+      k(53) := '>';
+      k(54) := '_';
+      k(55) := '|';
+      k(56) := ' ';
+      k(57) := 'a';
+      k(58) := 'b';
+      k(59) := 'c';
+      k(60) := 'd';
+      k(61) := 'e';
+      k(62) := 'f';
+      k(63) := 'g';
+      k(64) := 'h';
+      k(65) := 'i';
+      k(66) := 'j';
+      k(67) := 'k';
+      k(68) := 'l';
+      k(69) := 'm';
+      k(70) := 'n';
+      k(71) := 'o';
+      k(72) := 'p';
+      k(73) := 'q';
+      k(74) := 'r';
+      k(75) := 's';
+      k(76) := 't';
+      k(77) := 'u';
+      k(78) := 'v';
+      k(79) := 'w';
+      k(80) := 'x';
+      k(81) := 'y';
+      k(82) := 'z';
+      k(83) := '!';
+      k(84) := '$';
+      k(85) := '%';
+      k(86) := '@';
+      k(87) := '?';
+      k(88) := '[';
+      k(89) := '\';
+      k(90) := ']';
+      k(91) := '^';
+      k(92) := '`';
+      k(93) := '{';
+      k(94) := '}';
+      k(95) := '~';
+   assert NOT(   k(1)  = 'A'   and
+         k(2)  = 'B'   and 
+         k(3)  = 'C'   and
+         k(4)  = 'D'   and
+         k(5)  = 'E'   and
+         k(6)  = 'F'   and
+         k(7)  = 'G'   and
+         k(8)  = 'H'   and
+         k(9)  = 'I'   and
+         k(10) = 'J'   and
+         k(11) = 'K'   and
+         k(12) = 'L'   and
+         k(13) = 'M'   and
+         k(14) = 'N'   and
+         k(15) = 'O'   and
+         k(16) = 'P'   and
+         k(17) = 'Q'   and
+         k(18) = 'R'   and
+         k(19) = 'S'   and
+         k(20) = 'T'   and
+         k(21) = 'U'   and
+         k(22) = 'V'   and
+         k(23) = 'W'   and
+         k(24) = 'X'   and
+         k(25) = 'Y'   and
+         k(26) = 'Z'   and
+         k(27) = '0'   and
+         k(28) = '1'   and
+         k(29) = '2'   and
+         k(30) = '3'   and
+         k(31) = '4'   and
+         k(32) = '5'   and
+         k(33) = '6'   and
+         k(34) = '7'   and
+         k(35) = '8'   and
+         k(36) = '9'   and
+         k(37) = '"'   and
+         k(38) = '#'   and
+         k(39) = '&'   and
+         k(40) = '''   and
+         k(41) = '('   and
+         k(42) = ')'   and
+         k(43) = '*'   and
+         k(44) = '+'   and
+         k(45) = ','   and
+         k(46) = '-'   and
+         k(47) = '.'   and
+         k(48) = '/'   and
+         k(49) = ':'   and
+         k(50) = ';'   and
+         k(51) = '<'   and
+         k(52) = '='   and
+         k(53) = '>'   and
+         k(54) = '_'   and
+         k(55) = '|'   and
+         k(56) = ' '   and
+         k(57) = 'a'   and
+         k(58) = 'b'   and
+         k(59) = 'c'   and
+         k(60) = 'd'   and
+         k(61) = 'e'   and
+         k(62) = 'f'   and
+         k(63) = 'g'   and
+         k(64) = 'h'   and
+         k(65) = 'i'   and
+         k(66) = 'j'   and
+         k(67) = 'k'   and
+         k(68) = 'l'   and
+         k(69) = 'm'   and
+         k(70) = 'n'   and
+         k(71) = 'o'   and
+         k(72) = 'p'   and
+         k(73) = 'q'   and
+         k(74) = 'r'   and
+         k(75) = 's'   and
+         k(76) = 't'   and
+         k(77) = 'u'   and
+         k(78) = 'v'   and
+         k(79) = 'w'   and
+         k(80) = 'x'   and
+         k(81) = 'y'   and
+         k(82) = 'z'   and
+         k(83) = '!'   and
+         k(84) = '$'   and
+         k(85) = '%'   and
+         k(86) = '@'   and
+         k(87) = '?'   and
+         k(88) = '['   and
+         k(89) = '\'   and
+         k(90) = ']'   and
+         k(91) = '^'   and
+         k(92) = '`'   and
+         k(93) = '{'   and
+         k(94) = '}'   and
+         k(95) = '~'   )
+      report "***PASSED TEST: /src/ch13/sc05/p001-002/s010107.vhd" 
+      severity NOTE;
+   assert (   k(1)  = 'A'   and
+         k(2)  = 'B'   and 
+         k(3)  = 'C'   and
+         k(4)  = 'D'   and
+         k(5)  = 'E'   and
+         k(6)  = 'F'   and
+         k(7)  = 'G'   and
+         k(8)  = 'H'   and
+         k(9)  = 'I'   and
+         k(10) = 'J'   and
+         k(11) = 'K'   and
+         k(12) = 'L'   and
+         k(13) = 'M'   and
+         k(14) = 'N'   and
+         k(15) = 'O'   and
+         k(16) = 'P'   and
+         k(17) = 'Q'   and
+         k(18) = 'R'   and
+         k(19) = 'S'   and
+         k(20) = 'T'   and
+         k(21) = 'U'   and
+         k(22) = 'V'   and
+         k(23) = 'W'   and
+         k(24) = 'X'   and
+         k(25) = 'Y'   and
+         k(26) = 'Z'   and
+         k(27) = '0'   and
+         k(28) = '1'   and
+         k(29) = '2'   and
+         k(30) = '3'   and
+         k(31) = '4'   and
+         k(32) = '5'   and
+         k(33) = '6'   and
+         k(34) = '7'   and
+         k(35) = '8'   and
+         k(36) = '9'   and
+         k(37) = '"'   and
+         k(38) = '#'   and
+         k(39) = '&'   and
+         k(40) = '''   and
+         k(41) = '('   and
+         k(42) = ')'   and
+         k(43) = '*'   and
+         k(44) = '+'   and
+         k(45) = ','   and
+         k(46) = '-'   and
+         k(47) = '.'   and
+         k(48) = '/'   and
+         k(49) = ':'   and
+         k(50) = ';'   and
+         k(51) = '<'   and
+         k(52) = '='   and
+         k(53) = '>'   and
+         k(54) = '_'   and
+         k(55) = '|'   and
+         k(56) = ' '   and
+         k(57) = 'a'   and
+         k(58) = 'b'   and
+         k(59) = 'c'   and
+         k(60) = 'd'   and
+         k(61) = 'e'   and
+         k(62) = 'f'   and
+         k(63) = 'g'   and
+         k(64) = 'h'   and
+         k(65) = 'i'   and
+         k(66) = 'j'   and
+         k(67) = 'k'   and
+         k(68) = 'l'   and
+         k(69) = 'm'   and
+         k(70) = 'n'   and
+         k(71) = 'o'   and
+         k(72) = 'p'   and
+         k(73) = 'q'   and
+         k(74) = 'r'   and
+         k(75) = 's'   and
+         k(76) = 't'   and
+         k(77) = 'u'   and
+         k(78) = 'v'   and
+         k(79) = 'w'   and
+         k(80) = 'x'   and
+         k(81) = 'y'   and
+         k(82) = 'z'   and
+         k(83) = '!'   and
+         k(84) = '$'   and
+         k(85) = '%'   and
+         k(86) = '@'   and
+         k(87) = '?'   and
+         k(88) = '['   and
+         k(89) = '\'   and
+         k(90) = ']'   and
+         k(91) = '^'   and
+         k(92) = '`'   and
+         k(93) = '{'   and
+         k(94) = '}'   and
+         k(95) = '~'   )
+      report "***FAILED TEST: c13s05b00x00p01n01i02734 - Any one of the 95 graphic characters should be a character literal." 
+      severity ERROR;
+   wait;
+   END PROCESS TESTING;
+
+END c13s05b00x00p01n01i02734arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2735.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2735.vhd
new file mode 100644
index 0000000..7634419
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2735.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2735.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p01n01i02735ent IS
+END c13s06b00x00p01n01i02735ent;
+
+ARCHITECTURE c13s06b00x00p01n01i02735arch OF c13s06b00x00p01n01i02735ent IS
+  constant S : STRING := "";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   S = ""   ) 
+      report "***PASSED TEST: c13s06b00x00p01n01i02735"
+      severity NOTE;
+    assert (   S = ""   ) 
+      report "***FAILED TEST: c13s06b00x00p01n01i02735 - Null string as string literal lexical test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p01n01i02735arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2736.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2736.vhd
new file mode 100644
index 0000000..38a6cbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2736.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2736.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p01n01i02736ent IS
+END c13s06b00x00p01n01i02736ent;
+
+ARCHITECTURE c13s06b00x00p01n01i02736arch OF c13s06b00x00p01n01i02736ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable S45 : STRING (1 to 44);
+    variable S50 : STRING (1 to 50);
+  BEGIN
+    S45 := "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,";
+    S50 := "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~";
+    wait for 5 ns;
+    assert NOT(       S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
+                      and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
+      report "***PASSED TEST: c13s06b00x00p01n01i02736"
+      severity NOTE;
+    assert (       S45 = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789#&'()*+,"
+                   and S50 = "-./:;<=>_| abcdefghijklmnopqrstuvwxyz!$%@?[\]^`{}~")
+      report "***FAILED TEST: c13s06b00x00p01n01i02736 - String literal lexical test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p01n01i02736arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2737.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2737.vhd
new file mode 100644
index 0000000..b2ddd22
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2737.vhd
@@ -0,0 +1,526 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2737.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p03n01i02737ent IS
+END c13s06b00x00p03n01i02737ent;
+
+ARCHITECTURE c13s06b00x00p03n01i02737arch OF c13s06b00x00p03n01i02737ent IS
+  constant s01: string:="A ";   --  1
+  constant s02: string:="B ";   --  2
+  constant s03: string:="C ";   --  3
+  constant s04: string:="D ";   --  4
+  constant s05: string:="E ";   --  5
+  constant s06: string:="F ";   --  6
+  constant s07: string:="G ";   --  7
+  constant s08: string:="H ";   --  8
+  constant s09: string:="I ";   --  9
+  constant s10: string:="J ";   -- 10
+  constant s11: string:="K ";   -- 11
+  constant s12: string:="L ";   -- 12
+  constant s13: string:="M ";   -- 13
+  constant s14: string:="N ";   -- 14
+  constant s15: string:="O ";   -- 15
+  constant s16: string:="P ";   -- 16
+  constant s17: string:="Q ";   -- 17
+  constant s18: string:="R ";   -- 18
+  constant s19: string:="S ";   -- 19
+  constant s20: string:="T ";   -- 20
+  constant s21: string:="U ";   -- 21
+  constant s22: string:="V ";   -- 22
+  constant s23: string:="W ";   -- 23
+  constant s24: string:="X ";   -- 24
+  constant s25: string:="Y ";   -- 25
+  constant s26: string:="Z ";   -- 26
+  constant s27: string:="0 ";   -- 27
+  constant s28: string:="1 ";   -- 28
+  constant s29: string:="2 ";   -- 29
+  constant s30: string:="3 ";   -- 30
+  constant s31: string:="4 ";   -- 31
+  constant s32: string:="5 ";   -- 32
+  constant s33: string:="6 ";   -- 33
+  constant s34: string:="7 ";   -- 34
+  constant s35: string:="8 ";   -- 35
+  constant s36: string:="9 ";   -- 36
+  constant s37: string:=""" ";   -- 37
+  constant s38: string:="# ";   -- 38
+  constant s39: string:="& ";   -- 39
+  constant s40: string:="' ";   -- 40
+  constant s41: string:="( ";   -- 41
+  constant s42: string:=") ";   -- 42
+  constant s43: string:="* ";   -- 43
+  constant s44: string:="+ ";   -- 44
+  constant s45: string:=", ";   -- 45
+  constant s46: string:="- ";   -- 46
+  constant s47: string:=". ";   -- 47
+  constant s48: string:="/ ";   -- 48
+  constant s49: string:=": ";   -- 49
+  constant s50: string:="; ";   -- 50
+  constant s51: string:="< ";   -- 51
+  constant s52: string:="= ";   -- 52
+  constant s53: string:="> ";   -- 53
+  constant s54: string:="_ ";   -- 54
+  constant s55: string:="| ";   -- 55
+  constant s56: string:="  ";   -- 56
+  constant s57: string:="a ";   -- 57
+  constant s58: string:="b ";   -- 58
+  constant s59: string:="c ";   -- 59
+  constant s60: string:="d ";   -- 60
+  constant s61: string:="e ";   -- 61
+  constant s62: string:="f ";   -- 62
+  constant s63: string:="g ";   -- 63
+  constant s64: string:="h ";   -- 64
+  constant s65: string:="i ";   -- 65
+  constant s66: string:="j ";   -- 66
+  constant s67: string:="k ";   -- 67
+  constant s68: string:="l ";   -- 68
+  constant s69: string:="m ";   -- 69
+  constant s70: string:="n ";   -- 70
+  constant s71: string:="o ";   -- 71
+  constant s72: string:="p ";   -- 72
+  constant s73: string:="q ";   -- 73
+  constant s74: string:="r ";   -- 74
+  constant s75: string:="s ";   -- 75
+  constant s76: string:="t ";   -- 76
+  constant s77: string:="u ";   -- 77
+  constant s78: string:="v ";   -- 78
+  constant s79: string:="w ";   -- 79
+  constant s80: string:="x ";   -- 80
+  constant s81: string:="y ";   -- 81
+  constant s82: string:="z ";   -- 82
+  constant s83: string:="! ";   -- 83
+  constant s84: string:="$ ";   -- 84
+  constant s85: string:="% ";   -- 85
+  constant s86: string:="@ ";   -- 86
+  constant s87: string:="? ";   -- 87
+  constant s88: string:="[ ";   -- 88
+  constant s89: string:="\ ";   -- 89
+  constant s90: string:="] ";   -- 90
+  constant s91: string:="^ ";   -- 91
+  constant s92: string:="` ";   -- 92
+  constant s93: string:="{ ";   -- 93
+  constant s94: string:="} ";   -- 94
+  constant s95: string:="~ ";   -- 95
+  
+------------------------------------------------------------
+  
+  constant c01: string:=('A',' ');   --  1
+  constant c02: string:=('B',' ');   --  2
+  constant c03: string:=('C',' ');   --  3
+  constant c04: string:=('D',' ');   --  4
+  constant c05: string:=('E',' ');   --  5
+  constant c06: string:=('F',' ');   --  6
+  constant c07: string:=('G',' ');   --  7
+  constant c08: string:=('H',' ');   --  8
+  constant c09: string:=('I',' ');   --  9
+  constant c10: string:=('J',' ');   -- 10
+  constant c11: string:=('K',' ');   -- 11
+  constant c12: string:=('L',' ');   -- 12
+  constant c13: string:=('M',' ');   -- 13
+  constant c14: string:=('N',' ');   -- 14
+  constant c15: string:=('O',' ');   -- 15
+  constant c16: string:=('P',' ');   -- 16
+  constant c17: string:=('Q',' ');   -- 17  
+  constant c18: string:=('R',' ');   -- 18
+  constant c19: string:=('S',' ');   -- 19
+  constant c20: string:=('T',' ');   -- 20
+  constant c21: string:=('U',' ');   -- 21
+  constant c22: string:=('V',' ');   -- 22
+  constant c23: string:=('W',' ');   -- 23
+  constant c24: string:=('X',' ');   -- 24
+  constant c25: string:=('Y',' ');   -- 25
+  constant c26: string:=('Z',' ');   -- 26
+  constant c27: string:=('0',' ');   -- 27
+  constant c28: string:=('1',' ');   -- 28
+  constant c29: string:=('2',' ');   -- 29
+  constant c30: string:=('3',' ');   -- 30
+  constant c31: string:=('4',' ');   -- 31
+  constant c32: string:=('5',' ');   -- 32
+  constant c33: string:=('6',' ');   -- 33
+  constant c34: string:=('7',' ');   -- 34
+  constant c35: string:=('8',' ');   -- 35
+  constant c36: string:=('9',' ');   -- 36
+  constant c37: string:=('"',' ');   -- 37
+  constant c38: string:=('#',' ');   -- 38
+  constant c39: string:=('&',' ');   -- 39
+  constant c40: string:=(''',' ');   -- 40
+  constant c41: string:=('(',' ');   -- 41
+                         constant c42: string:=(')',' ');   -- 42
+  constant c43: string:=('*',' ');   -- 43
+  constant c44: string:=('+',' ');   -- 44
+  constant c45: string:=(',',' ');   -- 45
+  constant c46: string:=('-',' ');   -- 46
+  constant c47: string:=('.',' ');   -- 47
+  constant c48: string:=('/',' ');   -- 48
+  constant c49: string:=(':',' ');   -- 49
+  constant c50: string:=(';',' ');   -- 50
+  constant c51: string:=('<',' ');   -- 51
+  constant c52: string:=('=',' ');   -- 52
+  constant c53: string:=('>',' ');   -- 53
+  constant c54: string:=('_',' ');   -- 54
+  constant c55: string:=('|',' ');   -- 55
+  constant c56: string:=(' ',' ');   -- 56
+  constant c57: string:=('a',' ');   -- 57
+  constant c58: string:=('b',' ');   -- 58
+  constant c59: string:=('c',' ');   -- 59
+  constant c60: string:=('d',' ');   -- 60
+  constant c61: string:=('e',' ');   -- 61
+  constant c62: string:=('f',' ');   -- 62
+  constant c63: string:=('g',' ');   -- 63
+  constant c64: string:=('h',' ');   -- 64
+  constant c65: string:=('i',' ');   -- 65
+  constant c66: string:=('j',' ');   -- 66
+  constant c67: string:=('k',' ');   -- 67
+  constant c68: string:=('l',' ');   -- 68
+  constant c69: string:=('m',' ');   -- 69
+  constant c70: string:=('n',' ');   -- 70
+  constant c71: string:=('o',' ');   -- 71
+  constant c72: string:=('p',' ');   -- 72
+  constant c73: string:=('q',' ');   -- 73
+  constant c74: string:=('r',' ');   -- 74  
+  constant c75: string:=('s',' ');   -- 75
+  constant c76: string:=('t',' ');   -- 76
+  constant c77: string:=('u',' ');   -- 77
+  constant c78: string:=('v',' ');   -- 78
+  constant c79: string:=('w',' ');   -- 79
+  constant c80: string:=('x',' ');   -- 80
+  constant c81: string:=('y',' ');   -- 81
+  constant c82: string:=('z',' ');   -- 82
+  constant c83: string:=('!',' ');   -- 83
+  constant c84: string:=('$',' ');   -- 84
+  constant c85: string:=('%',' ');   -- 85
+  constant c86: string:=('@',' ');   -- 86
+  constant c87: string:=('?',' ');   -- 87
+  constant c88: string:=('[',' ');   -- 88
+                         constant c89: string:=('\',' ');   -- 89
+                         constant c90: string:=(']',' ');   -- 90
+  constant c91: string:=('^',' ');   -- 91
+  constant c92: string:=('`',' ');   -- 92
+  constant c93: string:=('{',' ');   -- 93
+                         constant c94: string:=('}',' ');   -- 94
+  constant c95: string:=('~',' ');   -- 95
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    assert (s01=c01) report "problem with  1  - 'A' " severity failure;
+    assert (s02=c02) report "problem with  2  - 'B' " severity failure;
+    assert (s03=c03) report "problem with  3  - 'C' " severity failure;
+    assert (s04=c04) report "problem with  4  - 'D' " severity failure;
+    assert (s05=c05) report "problem with  5  - 'E' " severity failure;
+    assert (s06=c06) report "problem with  6  - 'F' " severity failure;
+    assert (s07=c07) report "problem with  7  - 'G' " severity failure;
+    assert (s08=c08) report "problem with  8  - 'H' " severity failure;
+    assert (s09=c09) report "problem with  9  - 'I' " severity failure;
+    assert (s10=c10) report "problem with  10 - 'J' " severity failure;
+    assert (s11=c11) report "problem with  11 - 'K' " severity failure;
+    assert (s12=c12) report "problem with  12 - 'L' " severity failure;
+    assert (s13=c13) report "problem with  13 - 'M' " severity failure;
+    assert (s14=c14) report "problem with  14 - 'N' " severity failure;
+    assert (s15=c15) report "problem with  15 - 'O' " severity failure;
+    assert (s16=c16) report "problem with  16 - 'P' " severity failure;
+    assert (s17=c17) report "problem with  17 - 'Q' " severity failure;
+    assert (s18=c18) report "problem with  18 - 'R' " severity failure;
+    assert (s19=c19) report "problem with  19 - 'S' " severity failure;
+    assert (s20=c20) report "problem with  20 - 'T' " severity failure;
+    assert (s21=c21) report "problem with  21 - 'U' " severity failure;
+    assert (s22=c22) report "problem with  22 - 'V' " severity failure;
+    assert (s23=c23) report "problem with  23 - 'W' " severity failure;
+    assert (s24=c24) report "problem with  24 - 'X' " severity failure;
+    assert (s25=c25) report "problem with  25 - 'Y' " severity failure;
+    assert (s26=c26) report "problem with  26 - 'Z' " severity failure;
+    assert (s27=c27) report "problem with  27 - '0' " severity failure;
+    assert (s28=c28) report "problem with  28 - '1' " severity failure;
+    assert (s29=c29) report "problem with  29 - '2' " severity failure;
+    assert (s30=c30) report "problem with  30 - '3' " severity failure;
+    assert (s31=c31) report "problem with  31 - '4' " severity failure;
+    assert (s32=c32) report "problem with  32 - '5' " severity failure;
+    assert (s33=c33) report "problem with  33 - '6' " severity failure;
+    assert (s34=c34) report "problem with  34 - '7' " severity failure;
+    assert (s35=c35) report "problem with  35 - '8' " severity failure;
+    assert (s36=c36) report "problem with  36 - '9' " severity failure;
+    assert (s37=c37) report "problem with  37 - '""' " severity failure;
+    assert (s38=c38) report "problem with  38 - '#' " severity failure;
+    assert (s39=c39) report "problem with  39 - '&' " severity failure;
+    assert (s40=c40) report "problem with  40 - ''' " severity failure;
+    assert (s41=c41) report "problem with  41 - '(' " severity failure;
+    assert (s42=c42) report "problem with  42 - ')' " severity failure;
+    assert (s43=c43) report "problem with  43 - '*' " severity failure;
+    assert (s44=c44) report "problem with  44 - '+' " severity failure;
+    assert (s45=c45) report "problem with  45 - ',' " severity failure;
+    assert (s46=c46) report "problem with  46 - '-' " severity failure;
+    assert (s47=c47) report "problem with  47 - '.' " severity failure;
+    assert (s48=c48) report "problem with  48 - '/' " severity failure;
+    assert (s49=c49) report "problem with  49 - ':' " severity failure;
+    assert (s50=c50) report "problem with  50 - ';' " severity failure;
+    assert (s51=c51) report "problem with  51 - '<' " severity failure;
+    assert (s52=c52) report "problem with  52 - '=' " severity failure;
+    assert (s53=c53) report "problem with  53 - '>' " severity failure;
+    assert (s54=c54) report "problem with  54 - '_' " severity failure;
+    assert (s55=c55) report "problem with  55 - '|' " severity failure;
+    assert (s56=c56) report "problem with  56 - ' ' " severity failure;
+    assert (s57=c57) report "problem with  57 - 'a' " severity failure;
+    assert (s58=c58) report "problem with  58 - 'b' " severity failure;    
+    assert (s59=c59) report "problem with  59 - 'c' " severity failure;
+    assert (s60=c60) report "problem with  60 - 'd' " severity failure;
+    assert (s61=c61) report "problem with  61 - 'e' " severity failure;
+    assert (s62=c62) report "problem with  62 - 'f' " severity failure;
+    assert (s63=c63) report "problem with  63 - 'g' " severity failure;
+    assert (s64=c64) report "problem with  64 - 'h' " severity failure;
+    assert (s65=c65) report "problem with  65 - 'i' " severity failure;
+    assert (s66=c66) report "problem with  66 - 'j' " severity failure;
+    assert (s67=c67) report "problem with  67 - 'k' " severity failure;
+    assert (s68=c68) report "problem with  68 - 'l' " severity failure;
+    assert (s69=c69) report "problem with  69 - 'm' " severity failure;
+    assert (s70=c70) report "problem with  70 - 'n' " severity failure;
+    assert (s71=c71) report "problem with  71 - 'o' " severity failure;
+    assert (s72=c72) report "problem with  72 - 'p' " severity failure;
+    assert (s73=c73) report "problem with  73 - 'q' " severity failure;
+    assert (s74=c74) report "problem with  74 - 'r' " severity failure;
+    assert (s75=c75) report "problem with  75 - 's' " severity failure;
+    assert (s76=c76) report "problem with  76 - 't' " severity failure;
+    assert (s77=c77) report "problem with  77 - 'u' " severity failure;
+    assert (s78=c78) report "problem with  78 - 'v' " severity failure;
+    assert (s79=c79) report "problem with  79 - 'w' " severity failure;
+    assert (s80=c80) report "problem with  80 - 'x' " severity failure;
+    assert (s81=c81) report "problem with  81 - 'y' " severity failure;
+    assert (s82=c82) report "problem with  82 - 'z' " severity failure;
+    assert (s83=c83) report "problem with  83 - '!' " severity failure;
+    assert (s84=c84) report "problem with  84 - '$' " severity failure;
+    assert (s85=c85) report "problem with  85 - '%' " severity failure;
+    assert (s86=c86) report "problem with  86 - '@' " severity failure;
+    assert (s87=c87) report "problem with  87 - '?' " severity failure;
+    assert (s88=c88) report "problem with  88 - '[' " severity failure;
+    assert (s89=c89) report "problem with  89 - '\' " severity failure;
+    assert (s90=c90) report "problem with  90 - ']' " severity failure;
+    assert (s91=c91) report "problem with  91 - '^' " severity failure;
+    assert (s92=c92) report "problem with  92 - '`' " severity failure;
+    assert (s93=c93) report "problem with  93 - '{' " severity failure;
+    assert (s94=c94) report "problem with  94 - '}' " severity failure;
+    assert (s95=c95) report "problem with  95 - '~' " severity failure;
+
+    assert NOT(   (s01=c01) and 
+                  (s02=c02) and 
+                  (s03=c03) and 
+                  (s04=c04) and 
+                  (s05=c05) and 
+                  (s06=c06) and 
+                  (s07=c07) and 
+                  (s08=c08) and 
+                  (s09=c09) and 
+                  (s10=c10) and 
+                  (s11=c11) and 
+                  (s12=c12) and 
+                  (s13=c13) and 
+                  (s14=c14) and 
+                  (s15=c15) and 
+                  (s16=c16) and 
+                  (s17=c17) and 
+                  (s18=c18) and 
+                  (s19=c19) and 
+                  (s20=c20) and 
+                  (s21=c21) and 
+                  (s22=c22) and 
+                  (s23=c23) and 
+                  (s24=c24) and 
+                  (s25=c25) and 
+                  (s26=c26) and 
+                  (s27=c27) and 
+                  (s28=c28) and 
+                  (s29=c29) and 
+                  (s30=c30) and 
+                  (s31=c31) and 
+                  (s32=c32) and 
+                  (s33=c33) and 
+                  (s34=c34) and 
+                  (s35=c35) and 
+                  (s36=c36) and 
+                  (s37=c37) and 
+                  (s38=c38) and 
+                  (s39=c39) and 
+                  (s40=c40) and 
+                  (s41=c41) and 
+                  (s42=c42) and 
+                  (s43=c43) and 
+                  (s44=c44) and 
+                  (s45=c45) and 
+                  (s46=c46) and 
+                  (s47=c47) and 
+                  (s48=c48) and 
+                  (s49=c49) and 
+                  (s50=c50) and 
+                  (s51=c51) and 
+                  (s52=c52) and 
+                  (s53=c53) and 
+                  (s54=c54) and 
+                  (s55=c55) and 
+                  (s56=c56) and 
+                  (s57=c57) and 
+                  (s58=c58) and 
+                  (s59=c59) and 
+                  (s60=c60) and 
+                  (s61=c61) and 
+                  (s62=c62) and 
+                  (s63=c63) and 
+                  (s64=c64) and 
+                  (s65=c65) and 
+                  (s66=c66) and 
+                  (s67=c67) and 
+                  (s68=c68) and 
+                  (s69=c69) and 
+                  (s70=c70) and 
+                  (s71=c71) and 
+                  (s72=c72) and 
+                  (s73=c73) and 
+                  (s74=c74) and 
+                  (s75=c75) and 
+                  (s76=c76) and 
+                  (s77=c77) and 
+                  (s78=c78) and 
+                  (s79=c79) and 
+                  (s80=c80) and 
+                  (s81=c81) and 
+                  (s82=c82) and 
+                  (s83=c83) and 
+                  (s84=c84) and 
+                  (s85=c85) and 
+                  (s86=c86) and 
+                  (s87=c87) and 
+                  (s88=c88) and 
+                  (s89=c89) and 
+                  (s90=c90) and 
+                  (s91=c91) and 
+                  (s92=c92) and 
+                  (s93=c93) and 
+                  (s94=c94) and 
+                  (s95=c95) ) 
+      report "***PASSED TEST: c13s06b00x00p03n01i02737"
+      severity NOTE;
+    assert (   (s01=c01) and 
+               (s02=c02) and 
+               (s03=c03) and 
+               (s04=c04) and 
+               (s05=c05) and 
+               (s06=c06) and 
+               (s07=c07) and 
+               (s08=c08) and 
+               (s09=c09) and 
+               (s10=c10) and 
+               (s11=c11) and 
+               (s12=c12) and 
+               (s13=c13) and 
+               (s14=c14) and 
+               (s15=c15) and 
+               (s16=c16) and 
+               (s17=c17) and 
+               (s18=c18) and 
+               (s19=c19) and 
+               (s20=c20) and 
+               (s21=c21) and 
+               (s22=c22) and 
+               (s23=c23) and 
+               (s24=c24) and 
+               (s25=c25) and 
+               (s26=c26) and 
+               (s27=c27) and 
+               (s28=c28) and 
+               (s29=c29) and 
+               (s30=c30) and 
+               (s31=c31) and 
+               (s32=c32) and 
+               (s33=c33) and 
+               (s34=c34) and 
+               (s35=c35) and 
+               (s36=c36) and 
+               (s37=c37) and 
+               (s38=c38) and 
+               (s39=c39) and 
+               (s40=c40) and 
+               (s41=c41) and 
+               (s42=c42) and 
+               (s43=c43) and 
+               (s44=c44) and 
+               (s45=c45) and 
+               (s46=c46) and 
+               (s47=c47) and 
+               (s48=c48) and 
+               (s49=c49) and 
+               (s50=c50) and 
+               (s51=c51) and 
+               (s52=c52) and 
+               (s53=c53) and 
+               (s54=c54) and 
+               (s55=c55) and 
+               (s56=c56) and 
+               (s57=c57) and 
+               (s58=c58) and 
+               (s59=c59) and 
+               (s60=c60) and 
+               (s61=c61) and 
+               (s62=c62) and 
+               (s63=c63) and 
+               (s64=c64) and 
+               (s65=c65) and 
+               (s66=c66) and 
+               (s67=c67) and 
+               (s68=c68) and 
+               (s69=c69) and 
+               (s70=c70) and 
+               (s71=c71) and 
+               (s72=c72) and 
+               (s73=c73) and 
+               (s74=c74) and 
+               (s75=c75) and 
+               (s76=c76) and 
+               (s77=c77) and 
+               (s78=c78) and 
+               (s79=c79) and 
+               (s80=c80) and 
+               (s81=c81) and 
+               (s82=c82) and 
+               (s83=c83) and 
+               (s84=c84) and 
+               (s85=c85) and 
+               (s86=c86) and 
+               (s87=c87) and 
+               (s88=c88) and 
+               (s89=c89) and 
+               (s90=c90) and 
+               (s91=c91) and 
+               (s92=c92) and 
+               (s93=c93) and 
+               (s94=c94) and 
+               (s95=c95) ) 
+      report "***FAILED TEST: c13s06b00x00p03n01i02737 - All string literal of length 1 are equal in value to their corresponding character values."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p03n01i02737arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2738.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2738.vhd
new file mode 100644
index 0000000..25f15b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2738.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2738.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p03n02i02738ent IS
+END c13s06b00x00p03n02i02738ent;
+
+ARCHITECTURE c13s06b00x00p03n02i02738arch OF c13s06b00x00p03n02i02738ent IS
+  constant   c : string := ('"',' ');
+  constant   s : string := """ ";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( c=s )
+      report "***PASSED TEST: c13s06b00x00p03n02i02738"
+      severity NOTE;
+    assert ( c=s )
+      report "***FAILED TEST: c13s06b00x00p03n02i02738 - A string literal that includes two adjacent quotation characters is interpreted as one quotation character."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p03n02i02738arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2739.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2739.vhd
new file mode 100644
index 0000000..db4ea6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2739.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2739.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p03n01i02739ent IS
+END c13s06b00x00p03n01i02739ent;
+
+ARCHITECTURE c13s06b00x00p03n01i02739arch OF c13s06b00x00p03n01i02739ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(('A'/='a')and("ABCDE"/=string'("abcde")))
+      report "***PASSED TEST: c13s06b00x00p03n01i02739"
+      severity NOTE;
+    assert (('A'/='a')and("ABCDE"/=string'("abcde")))
+      report "***FAILED TEST: c13s06b00x00p03n01i02739 - Uppercase and lowercase letters should distinct within a string literal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p03n01i02739arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2740.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2740.vhd
new file mode 100644
index 0000000..f31945a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2740.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2740.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p03n02i02740ent IS
+END c13s06b00x00p03n02i02740ent;
+
+ARCHITECTURE c13s06b00x00p03n02i02740arch OF c13s06b00x00p03n02i02740ent IS
+  constant C1 : CHARACTER := '"';
+  constant S1 : STRING (1 to 1) := """";
+  constant S3 : STRING (1 to 3) := "A""C";
+  constant S5 : STRING (1 to 5) := """B""D""";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(      (S1(1)=C1)
+                     and (S3(2)=C1)
+                     and (S5(1)=C1)
+                     and (S5(3)=C1)
+                     and (S5(5)=C1)) 
+      report "***PASSED TEST: c13s06b00x00p03n02i02740"
+      severity NOTE;
+    assert (      (S1(1)=C1)
+                  and (S3(2)=C1)
+                  and (S5(1)=C1)
+                  and (S5(3)=C1)
+                  and (S5(5)=C1)) 
+      report "***FAILED TEST: c13s06b00x00p03n02i02740 - A string literal that includes two adjacent quotation characters is interpreted as one quotation character."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p03n02i02740arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2742.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2742.vhd
new file mode 100644
index 0000000..c14bed0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2742.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2742.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p04n01i02742ent IS
+END c13s06b00x00p04n01i02742ent;
+
+ARCHITECTURE c13s06b00x00p04n01i02742arch OF c13s06b00x00p04n01i02742ent IS
+  constant   mystring : string := "123456789";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( mystring'length = 9 )
+      report "***PASSED TEST: c13s06b00x00p04n01i02742"
+      severity NOTE;
+    assert ( mystring'length = 9 )
+      report "***FAILED TEST: c13s06b00x00p04n01i02742 - The length of a digit string is the number of character values in the sequence represented."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p04n01i02742arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2743.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2743.vhd
new file mode 100644
index 0000000..dcf7a48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2743.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2743.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p04n01i02743ent IS
+END c13s06b00x00p04n01i02743ent;
+
+ARCHITECTURE c13s06b00x00p04n01i02743arch OF c13s06b00x00p04n01i02743ent IS
+  constant   mystring : string := "abcdefghijklmnopqrstuvwxyz";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( mystring'length = 26 )
+      report "***PASSED TEST: c13s06b00x00p04n01i02743"
+      severity NOTE;
+    assert ( mystring'length = 26 )
+      report "***FAILED TEST: c13s06b00x00p04n01i02743 - The length of a character string is the number of character values in the sequence represented."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p04n01i02743arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2744.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2744.vhd
new file mode 100644
index 0000000..ef8269c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2744.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2744.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p04n02i02744ent IS
+END c13s06b00x00p04n02i02744ent;
+
+ARCHITECTURE c13s06b00x00p04n02i02744arch OF c13s06b00x00p04n02i02744ent IS
+  constant   a : string := """";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a'length=1 )
+      report "***PASSED TEST: c13s06b00x00p04n02i02744"
+      severity NOTE;
+    assert ( a'length=1 )
+      report "***FAILED TEST: c13s06b00x00p04n02i02744 - Double quote should be treated as signle character."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p04n02i02744arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2745.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2745.vhd
new file mode 100644
index 0000000..719215d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2745.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2745.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p10n01i02745ent IS
+END c13s06b00x00p10n01i02745ent;
+
+ARCHITECTURE c13s06b00x00p10n01i02745arch OF c13s06b00x00p10n01i02745ent IS
+  constant   mystring : string :=    "This string has too " &
+                                     "many characters.";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT( mystring="This string has too many characters." )
+      report "***PASSED TEST: c13s06b00x00p10n01i02745"
+      severity NOTE;
+    assert ( mystring="This string has too many characters." )
+      report "***FAILED TEST: c13s06b00x00p10n01i02745 - Use of & as a continuation for a string test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p10n01i02745arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2747.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2747.vhd
new file mode 100644
index 0000000..30684ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2747.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2747.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p02n01i02747ent IS
+END c13s07b00x00p02n01i02747ent;
+
+ARCHITECTURE c13s07b00x00p02n01i02747arch OF c13s07b00x00p02n01i02747ent IS
+  type       x1 is array (1 to 10) of bit;
+  constant    v1 : x1 := B"00_11_00_11_00";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(v1 = B"00_11_00_11_00") 
+      report "***PASSED TEST: c13s07b00x00p02n01i02747" 
+      severity NOTE;
+    assert (v1 = B"00_11_00_11_00") 
+      report "***FAILED TEST: c13s07b00x00p02n01i02747 - A bit string literal consists of a sequence of extended digits enclosed between two quotations and is preceded by a base specifier." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p02n01i02747arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2758.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2758.vhd
new file mode 100644
index 0000000..dc21077
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2758.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2758.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p05n01i02758ent IS
+END c13s07b00x00p05n01i02758ent;
+
+ARCHITECTURE c13s07b00x00p05n01i02758arch OF c13s07b00x00p05n01i02758ent IS
+  constant   bcap : bit_vector := x"F_F_F";
+  constant   blow : bit_vector := x"FFF";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( bcap=blow )
+      report "***PASSED TEST: c13s07b00x00p05n01i02758"
+      severity NOTE;
+    assert ( bcap=blow )
+      report "***FAILED TEST: c13s07b00x00p05n01i02758 - Underscore in bit string value should not change the value."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p05n01i02758arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2759.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2759.vhd
new file mode 100644
index 0000000..bd174a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2759.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2759.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- Dale Martin modified this file by adding qualification to the 
+-- bit string literals in the comparisons to make them VHDL-93 compliant.
+
+ENTITY c13s07b00x00p05n02i02759ent IS
+END c13s07b00x00p05n02i02759ent;
+
+ARCHITECTURE c13s07b00x00p05n02i02759arch OF c13s07b00x00p05n02i02759ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( bit_vector'(X"123456789ABCDEF") /= B"1111_1011_1011" )
+      report "***PASSED TEST: c13s07b00x00p05n02i02759"
+      severity NOTE;
+    assert ( bit_vector'(X"123456789ABCDEF") /= B"1111_1011_1011" )
+      report "***FAILED TEST: c13s07b00x00p05n02i02759 - Extended digit test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p05n02i02759arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc276.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc276.vhd
new file mode 100644
index 0000000..1c063f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc276.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc276.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00276ent IS
+END c03s01b03x00p07n01i00276ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00276arch OF c03s01b03x00p07n01i00276ent IS
+  type twos_complement_integer1 is range -32768 to 0;
+  type twos_complement_integer2 is range 0 to 32767;
+  type J is
+    range   twos_complement_integer1'(-32000) to
+    twos_complement_integer2'( 32000)      -- Success_here
+    units
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : J := 31000 A;
+  BEGIN
+    k := 5 A;
+    assert NOT(k=5 A) 
+      report "***PASSED TEST: c03s01b03x00p07n01i00276" 
+      severity NOTE;
+    assert (k=5 A) 
+      report "***FAILED TEST: c03s01b03x00p07n01i00276 - The bounds in the range constraint are not locally static expressions."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00276arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2760.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2760.vhd
new file mode 100644
index 0000000..c595135
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2760.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2760.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p05n03i02760ent IS
+END c13s07b00x00p05n03i02760ent;
+
+ARCHITECTURE c13s07b00x00p05n03i02760arch OF c13s07b00x00p05n03i02760ent IS
+  constant   bcap   : bit_vector := x"FfF";
+  constant   blow   : bit_vector := x"fFf";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( bcap=blow )
+      report "***PASSED TEST: c13s07b00x00p05n03i02760"
+      severity NOTE;
+    assert ( bcap=blow )
+      report "***FAILED TEST: c13s07b00x00p05n03i02760 - A letter in a bit string literal should be able to be written either in lower case or in upper case with the same meaning."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p05n03i02760arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2761.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2761.vhd
new file mode 100644
index 0000000..a1efc71
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2761.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2761.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p05n01i02761ent IS
+END c13s07b00x00p05n01i02761ent;
+
+-- Dale Martin modified this file to make the bit string literal comparisons
+-- VHDL '93 compliant, by qualifying them with bit_string_literal'(
+
+ARCHITECTURE c13s07b00x00p05n01i02761arch OF c13s07b00x00p05n01i02761ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( ( bit_vector'(B"01_111_101") = B"0111_1101" )
+		and ( bit_vector'(O"17_5") = O"1_75")
+		and ( bit_vector'(X"7D") = X"7_D")) 
+      report "***PASSED TEST: c13s07b00x00p05n01i02761"
+      severity NOTE;
+    assert ( ( bit_vector'(B"01_111_101") = B"0111_1101" )
+	     and ( bit_vector'(O"17_5")=O"1_75")
+	     and ( bit_vector'(X"7D")=X"7_D")) 
+      report "***FAILED TEST: c13s07b00x00p05n01i02761 - Underline character should not affect the value of the bit string literal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p05n01i02761arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2765.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2765.vhd
new file mode 100644
index 0000000..f22554a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2765.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2765.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p06n02i02765ent IS
+END c13s07b00x00p06n02i02765ent;
+
+ARCHITECTURE c13s07b00x00p06n02i02765arch OF c13s07b00x00p06n02i02765ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant clear : bit_vector := O"123_67_34";   -- no_failure_here
+  BEGIN
+    assert NOT(clear = O"123_67_34") 
+      report "***PASSED TEST: c13s07b00x00p06n02i02765" 
+      severity NOTE;
+    assert (clear = O"123_67_34") 
+      report "***FAILED TEST: c13s07b00x00p06n02i02765 - For the base specifier `O', the extended digits are restricted to the digits 0 through 7."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p06n02i02765arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2767.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2767.vhd
new file mode 100644
index 0000000..52da4aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2767.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2767.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- Dale Martin modified this file to make the bit string literal comparisons
+-- valid for VHDL 93, by qualifying them with bit_vector'()
+
+ENTITY c13s07b00x00p08n01i02767ent IS
+END c13s07b00x00p08n01i02767ent;
+
+ARCHITECTURE c13s07b00x00p08n01i02767arch OF c13s07b00x00p08n01i02767ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( ( bit_vector'(B"1111_0101_1101_1010") = bit_vector'(X"F5DA") )   and
+		(bit_vector'(B"101_110_001_111") = bit_vector'(O"5617")))
+      report "***PASSED TEST: c13s07b00x00p08n01i02767"
+      severity NOTE;
+    assert ( ( bit_vector'(B"1111_0101_1101_1010") = bit_vector'(X"F5DA"))   and
+	     (bit_vector'(B"101_110_001_111") = bit_vector'(O"5617")))
+      report "***FAILED TEST: c13s07b00x00p08n01i02767 - Bit value test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p08n01i02767arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2768.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2768.vhd
new file mode 100644
index 0000000..25d378b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2768.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2768.vhd,v 1.1.1.1 2001-08-22 18:20:52 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- Dale Martin updated the bit_vectors in this file with bit_vector'()
+-- qualification to make it VHDL '93 compliant. (It's still '87 compliant
+-- as well.)
+
+ENTITY c13s07b00x00p08n01i02768ent IS
+END c13s07b00x00p08n01i02768ent;
+
+ARCHITECTURE c13s07b00x00p08n01i02768arch OF c13s07b00x00p08n01i02768ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( bit_vector'(O"0") = "000"   and 
+		bit_vector'(O"1") = "001"   and
+		bit_vector'(O"2") = "010"   and
+		bit_vector'(O"3") = "011"   and
+		bit_vector'(O"4") = "100"   and
+		bit_vector'(O"5") = "101"   and
+		bit_vector'(O"6") = "110"   and
+		bit_vector'(O"7") = "111"   and
+		bit_vector'(O"01")    = "000001"   and
+		bit_vector'(O"10")    = "001000"   and
+		bit_vector'(O"0_1") = "000001"   and
+		bit_vector'(X"0") = "0000"   and  
+		bit_vector'(X"1") = "0001"   and
+		bit_vector'(X"2") = "0010"   and
+		bit_vector'(X"3") = "0011"   and
+		bit_vector'(X"4") = "0100"   and
+		bit_vector'(X"5") = "0101"   and
+		bit_vector'(X"6") = "0110"   and
+		bit_vector'(X"7") = "0111"   and
+		bit_vector'(X"8") = "1000"   and
+		bit_vector'(X"9") = "1001"   and
+		bit_vector'(X"A") = "1010"   and
+                bit_vector'(X"a") = "1010"   and
+		bit_vector'(X"B") = "1011"   and
+                bit_vector'(X"b") = "1011"   and
+		bit_vector'(X"C") = "1100"   and
+                bit_vector'(X"c") = "1100"   and
+		bit_vector'(X"D") = "1101"   and
+                bit_vector'(X"d") = "1101"   and
+		bit_vector'(X"E") = "1110"   and
+                bit_vector'(X"e") = "1110"   and
+		bit_vector'(X"F") = "1111"   and
+                bit_vector'(X"f") = "1111"   and
+		bit_vector'(X"01") = "00000001"   and
+		bit_vector'(X"10") = "00010000"   and
+		bit_vector'(X"0_1") = "00000001"   and
+		bit_vector'(X"E_7") = "11100111"   and
+		bit_vector'(X"DEAD_BEEF") = B"1101_1110_1010_1101_1011_1110_1110_1111")
+      report "***PASSED TEST: c13s07b00x00p08n01i02768"
+      severity NOTE;
+    assert ( bit_vector'(O"0") = "000"   and 
+	     bit_vector'(O"1") = "001"   and
+	     bit_vector'(O"2") = "010"   and
+	     bit_vector'(O"3") = "011"   and
+	     bit_vector'(O"4") = "100"   and
+	     bit_vector'(O"5") = "101"   and
+	     bit_vector'(O"6") = "110"   and
+	     bit_vector'(O"7") = "111"   and
+	     bit_vector'(O"01") = "000001"   and
+	     bit_vector'(O"10") = "001000"   and
+	     bit_vector'(O"0_1") = "000001"   and
+	     bit_vector'(X"0") = "0000"   and  
+	     bit_vector'(X"1") = "0001"   and
+	     bit_vector'(X"2") = "0010"   and
+	     bit_vector'(X"3") = "0011"   and
+	     bit_vector'(X"4") = "0100"   and
+	     bit_vector'(X"5") = "0101"   and
+	     bit_vector'(X"6") = "0110"   and
+	     bit_vector'(X"7") = "0111"   and
+	     bit_vector'(X"8") = "1000"   and
+	     bit_vector'(X"9") = "1001"   and
+	     bit_vector'(X"A") = "1010"   and
+	     bit_vector'(X"a") = "1010"   and
+	     bit_vector'(X"B") = "1011"   and
+	     bit_vector'(X"b") = "1011"   and
+	     bit_vector'(X"C") = "1100"   and
+	     bit_vector'(X"c") = "1100"   and
+	     bit_vector'(X"D") = "1101"   and
+	     bit_vector'(X"d") = "1101"   and
+	     bit_vector'(X"E") = "1110"   and
+	     bit_vector'(X"e") = "1110"   and
+	     bit_vector'(X"F") = "1111"   and
+	     bit_vector'(X"f") = "1111"   and
+	     bit_vector'(X"01") = "00000001"   and
+	     bit_vector'(X"10") = "00010000"   and
+	     bit_vector'(X"0_1") = "00000001"   and
+	     bit_vector'(X"E_7") = "11100111"   and
+	     bit_vector'(X"DEAD_BEEF") = B"1101_1110_1010_1101_1011_1110_1110_1111")
+      report "***FAILED TEST: c13s07b00x00p08n01i02768 - Bit string literal and base specifier 'O' and 'X' value transfer test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p08n01i02768arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2769.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2769.vhd
new file mode 100644
index 0000000..2cb9221
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2769.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2769.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p09n01i02769ent IS
+END c13s07b00x00p09n01i02769ent;
+
+ARCHITECTURE c13s07b00x00p09n01i02769arch OF c13s07b00x00p09n01i02769ent IS
+  constant   aaa : bit_vector := B"101101";
+  constant   bbb : bit_vector := O"777";
+  constant   ccc : bit_vector := X"FFFF";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
+      report "***PASSED TEST: c13s07b00x00p09n01i02769"
+      severity NOTE;
+    assert ( aaa'length = 6 and bbb'length = 9 and ccc'length = 16 )
+      report "***FAILED TEST: c13s07b00x00p09n01i02769 - The length of a bit string literal is the length of its string literal value."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p09n01i02769arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc277.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc277.vhd
new file mode 100644
index 0000000..ca22b65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc277.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc277.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00277ent IS
+END c03s01b03x00p07n01i00277ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00277arch OF c03s01b03x00p07n01i00277ent IS
+  type twos_complement_integer1 is range -32768 to 0;
+  constant r1: twos_complement_integer1 := -32000;
+  type twos_complement_integer2 is range 0 to 32767;
+  constant r2: twos_complement_integer2 := 32000;
+  type J is
+    range r1 to r2  -- Success_here
+    units
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : J := 31000 A;
+  BEGIN
+    k := 5 A;
+    assert NOT(k=5 A) 
+      report "***PASSED TEST: c03s01b03x00p07n01i00277"
+      severity NOTE;
+    assert (k=5 A) 
+      report "***FAILED TEST: c03s01b03x00p07n01i00277 - The bounds in the range constraint are not locally static expressions."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00277arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2771.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2771.vhd
new file mode 100644
index 0000000..0365a93
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2771.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2771.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c13s08b00x00p01n01i02771pkg is
+  function--This is a valid comment.
+    F1 return BOOLEAN;
+  function F2 return BOOLEAN;
+end c13s08b00x00p01n01i02771pkg;
+
+package body c13s08b00x00p01n01i02771pkg is
+  function--This is a valid comment.
+    F1 return BOOLEAN is
+
+  begin
+    return --This comment occurs within a statement!
+      FALSE-- Comments can occur anywhere and need not be
+      --           preceded by a blank
+      ;
+  end F1;
+
+  function F2 return BOOLEAN is
+    type TYP_1 is range 1 to 10;
+    variable V1--This is all one comment--not two  --  or more!
+              : TYP_1 := 2;
+  begin
+    assert TRUE
+      report "--This is not a comment--";
+    return FALSE;
+  end F2;
+end c13s08b00x00p01n01i02771pkg;
+
+ENTITY c13s08b00x00p01n01i02771ent IS
+  port (PT:BOOLEAN) ;
+  --This is a NULL entity
+END c13s08b00x00p01n01i02771ent;
+
+ARCHITECTURE c13s08b00x00p01n01i02771arch OF c13s08b00x00p01n01i02771ent IS
+
+--
+--(that was a blank comment)
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c13s08b00x00p01n01i02771" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING
+--that wasn't so quick!
+    ;--semicolon
+
+
+END c13s08b00x00p01n01i02771arch; --architecture A ("A comment can appear on any line of a VHDL description.")
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc278.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc278.vhd
new file mode 100644
index 0000000..9d60c03
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc278.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc278.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00278ent IS
+END c03s01b03x00p07n01i00278ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00278arch OF c03s01b03x00p07n01i00278ent IS
+  type twos_complement_integer is range -32768 to 32767;
+  type J is
+    range twos_complement_integer'low to twos_complement_integer'high
+    units         -- Success_here
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : J := 31000 A;
+  BEGIN
+    k := 5 A;
+    assert NOT(k=5 A) 
+      report "***PASSED TEST: c03s01b03x00p07n01i00278" 
+      severity NOTE;
+    assert (k=5 A) 
+      report "***FAILED TEST: c03s01b03x00p07n01i00278 - The bounds in the range constraint are not locally static expressions."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00278arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc279.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc279.vhd
new file mode 100644
index 0000000..b4d939a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc279.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc279.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00279ent IS
+END c03s01b03x00p07n01i00279ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00279arch OF c03s01b03x00p07n01i00279ent IS
+  type T1 is range 1 to 10;
+  type T2 is range 100 to 1000;
+  constant V1: T1 := 5;
+  constant V2: T2 := 500;
+  type T is
+    range V1 to V2  -- No_failure_here
+    units
+      I ;  
+      J = 2 I;
+      K = 2 J;
+      L = 10 K;
+      M =    L;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : T := 310 I;
+  BEGIN
+    k := 5 I;
+    assert NOT(k=5 I) 
+      report "***PASSED TEST: c03s01b03x00p07n01i00279" 
+      severity NOTE;
+    assert (k=5 I) 
+      report "***FAILED TEST: c03s01b03x00p07n01i00279 - The bounds in the range constraint are not locally static expressions."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00279arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc281.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc281.vhd
new file mode 100644
index 0000000..9f99881
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc281.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc281.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p08n02i00281ent IS
+END c03s01b03x00p08n02i00281ent;
+
+ARCHITECTURE c03s01b03x00p08n02i00281arch OF c03s01b03x00p08n02i00281ent IS
+  type UPLE is range 1 to 8
+    units
+      single;
+      duple = 2 single;
+      triple = 3 single;
+      quadruple = 2 duple;
+      pentuple = 5 single;
+      sextuple = 2 triple;
+      septuple = 7 single;
+      octuple = 2 quadruple;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : UPLE := 1 duple;
+  BEGIN
+    assert NOT(k = 2 single) 
+      report "***PASSED TEST: c03s01b03x00p08n02i00281" 
+      severity NOTE;
+    assert (k = 2 single) 
+      report "***FAILED TEST: c03s01b03x00p08n02i00281 - The relative order of secondary unit declarations is not fixed as long as units are not used before they are declared." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p08n02i00281arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc284.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc284.vhd
new file mode 100644
index 0000000..9e204be
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc284.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc284.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p12n01i00284ent IS
+END c03s01b03x00p12n01i00284ent;
+
+ARCHITECTURE c03s01b03x00p12n01i00284arch OF c03s01b03x00p12n01i00284ent IS
+  type distance is range 0 to 2e9
+    units
+      -- base unit
+      mil;
+      inch = 1000 mil;
+      ft   = 12   inch;
+      yd   = 3    ft;
+      fm   = 6    ft;
+      mi   = 5280 ft;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable k : distance := 12 ft;
+  BEGIN
+    assert NOT((k=144 inch) and (k=4 yd) and (k=2 fm) and (k=144000 mil))
+      report "***PASSED TEST: c03s01b03x00p12n01i00284"
+      severity NOTE;
+    assert ((k=144 inch) and (k=4 yd) and (k=2 fm) and (k=144000 mil))
+      report "***FAILED TEST: c03s01b03x00p12n01i00284 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p12n01i00284arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc285.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc285.vhd
new file mode 100644
index 0000000..85b7e14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc285.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc285.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p12n01i00285ent IS
+END c03s01b03x00p12n01i00285ent;
+
+ARCHITECTURE c03s01b03x00p12n01i00285arch OF c03s01b03x00p12n01i00285ent IS
+  type time is range 0 to 1E8 units
+                                fs;
+                                ps = 10 fs;
+                              end units;
+BEGIN
+  TESTING: PROCESS
+    variable i : integer; 
+  BEGIN
+    i:=time'pos(ps);
+    assert NOT(i=10)
+      report "***PASSED TEST: c03s01b03x00p12n01i00285"
+      severity NOTE;
+    assert (i=10)
+      report "***FAILED TEST: c03s01b03x00p12n01i00285 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p12n01i00285arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2853.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2853.vhd
new file mode 100644
index 0000000..36a0a8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2853.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2853.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p02n01i02853ent IS
+END c13s10b00x00p02n01i02853ent;
+
+ARCHITECTURE c13s10b00x00p02n01i02853arch OF c13s10b00x00p02n01i02853ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype   BYTE is BIT_VECTOR (0 to 7);
+    variable   b1 : BYTE;
+    variable    b2 : BYTE;
+  BEGIN
+    b1 := BYTE'(0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 => '1');
+    b2 := BYTE'(0 ! 1 ! 2 ! 3 ! 4 ! 5 ! 6 ! 7 => '1');
+    assert NOT( b1=b2 )
+      report "***PASSED TEST: c13s10b00x00p02n01i02853"
+      severity NOTE;
+    assert ( b1=b2 )
+      report "***FAILED TEST: c13s10b00x00p02n01i02853 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p02n01i02853arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2854.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2854.vhd
new file mode 100644
index 0000000..f0786c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2854.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2854.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p03n01i02854ent IS
+END c13s10b00x00p03n01i02854ent;
+
+ARCHITECTURE c13s10b00x00p03n01i02854arch OF c13s10b00x00p03n01i02854ent IS
+  constant   one    : integer := 16:E:E1;
+  constant   two    : integer := 16#E#E1;
+  constant   three   : integer := 16#FF#;
+  constant   four   : integer := 16:FF:;
+  constant   five   : integer := 2#1110_0000#;
+  constant   six   : integer := 2:1110_0000:;
+  constant   seven   : integer := 8#776#;
+  constant   eight   : integer := 8:776:;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    one=two    and 
+                   three=four    and 
+                   five=six    and 
+                   seven=eight    )
+      report "***PASSED TEST: c13s10b00x00p03n01i02854"
+      severity NOTE;
+    assert (    one=two    and 
+                three=four    and 
+                five=six    and 
+                seven=eight    )
+      report "***FAILED TEST: c13s10b00x00p03n01i02854 - Colon(:) can replace the sharp character(#) in based literal definition."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p03n01i02854arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc286.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc286.vhd
new file mode 100644
index 0000000..362d81d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc286.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc286.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p12n01i00286ent IS
+END c03s01b03x00p12n01i00286ent;
+
+ARCHITECTURE c03s01b03x00p12n01i00286arch OF c03s01b03x00p12n01i00286ent IS
+  type time is range 0 to 1E8 units
+                                fs;
+                                ps = 10 fs;
+                              end units;
+BEGIN
+  TESTING: PROCESS
+    variable i : integer; 
+  BEGIN
+    i:=time'pos(3 ps);
+    assert NOT(i=30)
+      report "***PASSED TEST: c03s01b03x00p12n01i00286"
+      severity NOTE;
+    assert (i=30)
+      report "***FAILED TEST: c03s01b03x00p12n01i00286 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p12n01i00286arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2860.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2860.vhd
new file mode 100644
index 0000000..9347d7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2860.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2860.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p04n02i02860ent IS
+END c13s10b00x00p04n02i02860ent;
+
+ARCHITECTURE c13s10b00x00p04n02i02860arch OF c13s10b00x00p04n02i02860ent IS
+  constant   a : string := %%%%;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( a'length=1 and a="%" )
+      report "***PASSED TEST: c13s10b00x00p04n02i02860"
+      severity NOTE;
+    assert ( a'length=1 and a="%" )
+      report "***FAILED TEST: c13s10b00x00p04n02i02860 - Double percent will be treated as single character."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p04n02i02860arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2861.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2861.vhd
new file mode 100644
index 0000000..b7de3cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2861.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2861.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p03n01i02861ent IS
+END c13s10b00x00p03n01i02861ent;
+
+ARCHITECTURE c13s10b00x00p03n01i02861arch OF c13s10b00x00p03n01i02861ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable total_time : real;
+  BEGIN
+    total_time := 5:1234.4321:E-10;      -- no_failure_here
+    assert NOT(total_time = 5:1234.4321:E-10) 
+      report "***PASSED TEST: c13s10b00x00p03n01i02861"
+      severity NOTE;
+    assert (total_time = 5:1234.4321:E-10) 
+      report "***FAILED TEST: c13s10b00x00p03n01i02861 - Sharp character test failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p03n01i02861arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2862.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2862.vhd
new file mode 100644
index 0000000..bd3ea8b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2862.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2862.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p04n03i02862ent IS
+END c13s10b00x00p04n03i02862ent;
+
+ARCHITECTURE c13s10b00x00p04n03i02862arch OF c13s10b00x00p04n03i02862ent IS
+  constant   one   : bit_vector := X"FF";
+  constant   two   : bit_vector := X%FF%;
+  constant   three   : bit_vector := o"77";
+  constant   four   : bit_vector := o%77%;
+  constant   five   : bit_vector := b"1111_1111";
+  constant   six   : bit_vector := b%1111_1111%;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    one=two    and 
+                   three=four    and 
+                   five=six    )
+      report "***PASSED TEST: c13s10b00x00p04n03i02862"
+      severity NOTE;
+    assert (    one=two    and 
+                three=four    and 
+                five=six    )
+      report "***FAILED TEST: c13s10b00x00p04n03i02862 - Percent character (%) can replace the quotation character ("") in bit string literals."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p04n03i02862arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2863.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2863.vhd
new file mode 100644
index 0000000..9d70b82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2863.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2863.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02863ent IS
+END c02s01b00x00p03n01i02863ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02863arch OF c02s01b00x00p03n01i02863ent IS
+
+BEGIN
+  TESTING: PROCESS
+    procedure mytest (fpl:integer);
+    procedure mytest (fpl:integer) is
+    begin
+      assert NOT( fpl = 5 )
+        report "***PASSED TEST: c02s01b00x00p03n01i02863"
+        severity NOTE;
+      assert ( fpl = 5 )
+        report "***FAILED TEST: c02s01b00x00p03n01i02863 - Subprogram syntax test failed."
+        severity ERROR;
+    end mytest;
+  BEGIN
+    mytest(5);
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02863arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2864.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2864.vhd
new file mode 100644
index 0000000..8760698
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2864.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2864.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02864ent IS
+END c02s01b00x00p03n01i02864ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02864arch OF c02s01b00x00p03n01i02864ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function greater (i,l:time) return boolean;
+    function greater (i,l:time) return boolean is
+    begin
+      if i > l then
+        return TRUE;
+      else
+        return FALSE;
+      end if;
+    end greater;
+    variable result : boolean;   
+  BEGIN
+    result := greater (10 ns, 5 ns);
+    assert NOT( result = true )
+      report "***PASSED TEST: c02s01b00x00p03n01i02864"
+      severity NOTE;
+    assert ( result = true )
+      report "***FAILED TEST: c02s01b00x00p03n01i02864 - Funcation call syntax test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02864arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2865.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2865.vhd
new file mode 100644
index 0000000..e203edd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2865.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2865.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02865ent IS
+  procedure mytime;
+  procedure mytime is
+  begin
+    assert NOT( true )
+      report "***PASSED TEST: c02s01b00x00p03n01i02865"
+      severity NOTE;
+    assert ( true )
+      report "***FAILED TEST: c02s01b00x00p03n01i02865 - Subprogram declaration syntax test failed."
+      severity ERROR;
+  end mytime;
+END c02s01b00x00p03n01i02865ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02865arch OF c02s01b00x00p03n01i02865ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    mytime;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02865arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2866.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2866.vhd
new file mode 100644
index 0000000..7d0c7ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2866.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2866.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02866ent IS
+  function mytime return boolean is
+  begin
+    return TRUE;
+  end mytime;
+END c02s01b00x00p03n01i02866ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02866arch OF c02s01b00x00p03n01i02866ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : boolean;
+  BEGIN
+    k:=mytime;
+    assert NOT( k )
+      report "***PASSED TEST: c02s01b00x00p03n01i02866"
+      severity NOTE;
+    assert ( k )
+      report "***FAILED TEST: c02s01b00x00p03n01i02866 - Wrong value returned from function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02866arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2868.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2868.vhd
new file mode 100644
index 0000000..7b3af37
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2868.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2868.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02868ent IS
+END c02s01b00x00p03n01i02868ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02868arch OF c02s01b00x00p03n01i02868ent IS
+  procedure subprog is
+  begin
+    assert FALSE
+      report "***PASSED TEST: c02s01b00x00p03n01i02868" 
+      severity NOTE;
+  end subprog;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    subprog;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02868arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc287.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc287.vhd
new file mode 100644
index 0000000..71a0cf2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc287.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc287.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p12n03i00287ent IS
+END c03s01b03x00p12n03i00287ent;
+
+ARCHITECTURE c03s01b03x00p12n03i00287arch OF c03s01b03x00p12n03i00287ent IS
+  type UPLE is range 1 to 8
+    units
+      single;
+      double    = 2 single;
+      quadruple    = 2 double;
+      octuple    = 2 quadruple;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((UPLE'POS(3 double) = 3 * UPLE'POS(double)) and (UPLE'POS(0.5 octuple) = 4))
+      report "***PASSED TEST: c03s01b03x00p12n03i00287"
+      severity NOTE;
+    assert ((UPLE'POS(3 double) = 3 * UPLE'POS(double)) and (UPLE'POS(0.5 octuple) = 4))
+      report "***FAILED TEST: c03s01b03x00p12n03i00287 - The position number of a physical literal with an abstract literal part is rounded up to the nearest integer of the product of the abstract literal part of physical literal and the position number of its unit name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p12n03i00287arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2870.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2870.vhd
new file mode 100644
index 0000000..65baa43
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2870.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2870.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02870ent IS
+END c02s01b00x00p03n01i02870ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02870arch OF c02s01b00x00p03n01i02870ent IS
+  
+  function func return integer is
+  begin
+    return 100 ;
+  end func ;
+  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(func = 100)
+      report "***PASSED TEST: c02s01b00x00p03n01i02870" 
+      severity NOTE;
+    assert (func = 100)
+      report "***FAILED TEST: c02s01b00x00p03n01i02870 - Function specification without optional formal parameter failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02870arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2874.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2874.vhd
new file mode 100644
index 0000000..e916f79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2874.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2874.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p06n05i02874ent IS
+  function "+" (I1:Bit) return bit;  --- No_Failure_here
+END c02s01b00x00p06n05i02874ent;
+
+ARCHITECTURE c02s01b00x00p06n05i02874arch OF c02s01b00x00p06n05i02874ent IS
+  function "+" (I1:Bit) return bit is
+  begin
+    if (I1 = '1') then
+      return '1';
+    else
+      return '0';
+    end if;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit := '0';
+  BEGIN
+    k := "+"('1');
+    assert NOT(k='1')
+      report "***PASSED TEST: c02s01b00x00p06n05i02874" 
+      severity NOTE;
+    assert (k='1')
+      report "***FAILED TEST: c02s01b00x00p06n05i02874 - Operator symbol as the function designator test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p06n05i02874arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2876.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2876.vhd
new file mode 100644
index 0000000..f08be5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2876.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2876.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p06n04i02876ent IS
+END c02s01b00x00p06n04i02876ent;
+
+ARCHITECTURE c02s01b00x00p06n04i02876arch OF c02s01b00x00p06n04i02876ent IS
+  procedure PX (I1 : Bit) is
+  begin
+    if (I1 = '1') then
+      assert FALSE
+        report "***PASSED TEST: c02s01b00x00p06n04i02876" 
+        severity NOTE;
+    else
+      assert FALSE
+        report "***FAILED TEST: c02s01b00x00p06n04i02876 - A procedure designator must always be an identifier."
+        severity ERROR;
+    end if;
+  end PX;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    PX('1');
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p06n04i02876arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2879.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2879.vhd
new file mode 100644
index 0000000..f4614a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2879.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2879.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p07n01i02879ent IS
+  function func1(constant flag:in integer) return integer;
+  
+  function func1(constant flag:in integer) return integer is
+    variable v1 : integer;
+  begin
+    if (flag = 0) then
+      return 0;
+    else
+      return ((func1(flag-1)) + 1);
+    end if;
+  end func1;
+END c02s01b00x00p07n01i02879ent;
+
+ARCHITECTURE c02s01b00x00p07n01i02879arch OF c02s01b00x00p07n01i02879ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x:integer;
+  BEGIN
+    x:=99;
+    assert (x=99) report "Initialization of integer variables incorrect"
+      severity failure;
+    x:= func1(3);
+    assert NOT( x=3 )
+      report "***PASSED TEST: c02s01b00x00p07n01i02879"
+      severity NOTE;
+    assert ( x=3 )
+      report "***FAILED TEST: c02s01b00x00p07n01i02879 - Functions resursion call test incorrect."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p07n01i02879arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc288.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc288.vhd
new file mode 100644
index 0000000..6a132ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc288.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc288.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p13n01i00288ent IS
+END c03s01b03x00p13n01i00288ent;
+
+ARCHITECTURE c03s01b03x00p13n01i00288arch OF c03s01b03x00p13n01i00288ent IS
+  type distance is range 0 to 2e9
+    units
+      -- base unit
+      mil;
+      inch = 1000 mil;
+      ft = 12 inch;
+      yd = 3 ft;
+      fm = 6 ft;
+      mi = 5280 ft;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT((880 * (yd + yd)) = 5280 * ft)
+      report "***PASSED TEST: c03s01b03x00p13n01i00288"
+      severity NOTE;
+    assert ((880 * (yd + yd)) = 5280 * ft)
+      report "***FAILED TEST: c03s01b03x00p13n01i00288 - The same arithmetic operations are defined for all physical types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p13n01i00288arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2880.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2880.vhd
new file mode 100644
index 0000000..756ac7e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2880.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2880.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p07n01i02880ent IS
+  procedure proc1(constant flag:in integer; variable ret:inout integer);
+  procedure proc1(constant flag:in integer; variable ret:inout integer) is
+  begin
+    if (flag = 0) then
+      ret:= -1;
+    else
+      proc1((flag-1),ret);
+    end if;
+    ret:= ret + 1;
+  end proc1;
+END c02s01b00x00p07n01i02880ent;
+
+ARCHITECTURE c02s01b00x00p07n01i02880arch OF c02s01b00x00p07n01i02880ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x:integer;
+  BEGIN
+    x:=99;
+    assert (x=99) report "Initialization of integer variables incorrect"
+      severity failure;
+    proc1(3,x);
+    assert NOT( x=3 )
+      report "***PASSED TEST: c02s01b00x00p07n01i02880"
+      severity NOTE;
+    assert ( x=3 )
+      report "***FAILED TEST: c02s01b00x00p07n01i02880 - Procedure resursion call test incorrect."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p07n01i02880arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2881.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2881.vhd
new file mode 100644
index 0000000..67eb1fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2881.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2881.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p07n01i02881ent IS
+  function func2(constant flag:in integer) return integer;
+  function func3(constant flag:in integer) return integer;
+  
+  function func2(constant flag:in integer) return integer is
+  begin
+    if (flag = 0) then
+      return 0;
+    else  
+      return ((func3(flag-1)) + 1);
+    end if;
+  end func2;
+  
+  function func3(constant flag:in integer) return integer is
+  begin
+    if (flag = 0) then
+      return 0;
+    else  
+      return ((func2(flag-1)) + 1);
+    end if;
+  end func3;
+END c02s01b00x00p07n01i02881ent;
+
+ARCHITECTURE c02s01b00x00p07n01i02881arch OF c02s01b00x00p07n01i02881ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x:integer;
+  BEGIN
+    x:=99;
+    assert (x=99) report "Initialization of integer variables incorrect"
+      severity failure;
+    x:= func2(3);
+    assert NOT( x=3 )
+      report "***PASSED TEST: c02s01b00x00p07n01i02881"
+      severity NOTE;
+    assert ( x=3 )
+      report "***FAILED TEST: c02s01b00x00p07n01i02881 - Functions resursion call test incorrect (A-B-A type)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p07n01i02881arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2882.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2882.vhd
new file mode 100644
index 0000000..4fe3414
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2882.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2882.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p07n01i02882ent IS
+  procedure proc2(constant flag:in integer; variable ret:inout integer);
+  procedure proc3(constant flag:in integer; variable ret:inout integer);
+
+  procedure proc2(constant flag:in integer; variable ret:inout integer) is
+  begin
+    if (flag = 0) then
+      ret:= -1;
+    else
+      proc3((flag-1),ret);
+    end if;
+    ret:= ret + 1;
+  end proc2;
+
+  procedure proc3(constant flag:in integer; variable ret:inout integer) is
+  begin
+    if (flag = 0) then
+      ret:= -1;
+    else
+      proc2((flag-1),ret);
+    end if;
+    ret:= ret + 1;
+  end proc3;
+END c02s01b00x00p07n01i02882ent;
+
+ARCHITECTURE c02s01b00x00p07n01i02882arch OF c02s01b00x00p07n01i02882ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x:integer;
+  BEGIN
+    x:=99;
+    assert (x=99) report "Initialization of integer variables incorrect"
+      severity failure;
+    proc2(3,x);
+    assert NOT( x=3 )
+      report "***PASSED TEST: c02s01b00x00p07n01i02882"
+      severity NOTE;
+    assert ( x=3 )
+      report "***FAILED TEST: c02s01b00x00p07n01i02882 - Procedures resursion call test incorrect (A-B-A type)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p07n01i02882arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2883.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2883.vhd
new file mode 100644
index 0000000..7dfc368
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2883.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2883.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p03n01i02883ent IS
+  procedure howe (k:in real; v:out real) is
+  begin
+    v := k;
+  end howe;
+END c02s01b01x00p03n01i02883ent;
+
+ARCHITECTURE c02s01b01x00p03n01i02883arch OF c02s01b01x00p03n01i02883ent IS
+  constant k:real:=3.1415;
+BEGIN
+  TESTING: PROCESS
+    variable v:real;
+  BEGIN
+    howe(k,v);
+    wait for 5 ns;
+    assert NOT( k=v )
+      report "***PASSED TEST: c02s01b01x00p03n01i02883"
+      severity NOTE;
+    assert ( k=v )
+      report "***FAILED TEST: c02s01b01x00p03n01i02883 - Wrong value returned from procedure."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p03n01i02883arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc29.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc29.vhd
new file mode 100644
index 0000000..4ee1cce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc29.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc29.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p12n01i00029ent IS
+END c04s02b00x00p12n01i00029ent;
+
+ARCHITECTURE c04s02b00x00p12n01i00029arch OF c04s02b00x00p12n01i00029ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define a subtype indication of the type INTEGER.
+    subtype SUBINT is INTEGER;
+
+    -- Declare variables of both types.
+    variable INTV : INTEGER;
+    variable SUBV : SUBINT;
+  BEGIN
+    -- Verify that we can perform "same type" operations on the
+    -- two variables.
+    SUBV := 1;
+    INTV := SUBV;
+    SUBV := INTV;
+
+    assert NOT( SUBV = INTV )
+      report "***PASSED TEST: c04s02b00x00p12n01i00029"
+      severity NOTE;
+    assert ( SUBV = INTV )
+      report "***FAILED TEST: c04s02b00x00p12n01i00029 - A subtype declaration does not define a new type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p12n01i00029arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc290.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc290.vhd
new file mode 100644
index 0000000..b4d35ce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc290.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc290.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p13n01i00290ent IS
+  type mytime is range 1 to 30 
+    units
+      fs;
+    end units;
+END c03s01b03x00p13n01i00290ent;
+
+ARCHITECTURE c03s01b03x00p13n01i00290arch OF c03s01b03x00p13n01i00290ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable t,a   :mytime;
+    variable b   :integer;
+  BEGIN
+    a:=30 fs;
+    b := 10;
+    t:= a/b;
+    assert NOT(t = 3 fs) 
+      report "***PASSED TEST: c03s01b03x00p13n01i00290" 
+      severity NOTE;
+    assert (t = 3 fs) 
+      report "***FAILED TEST: c03s01b03x00p13n01i00290 - Physical type value arithmetic operation failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p13n01i00290arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2900.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2900.vhd
new file mode 100644
index 0000000..cf6ac1f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2900.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2900.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x01p02n02i02900ent IS
+END c02s01b01x01p02n02i02900ent;
+
+ARCHITECTURE c02s01b01x01p02n02i02900arch OF c02s01b01x01p02n02i02900ent IS
+  type    t1 is (one,two,three);
+  signal    s1 : t1;
+  constant    c1 : integer:=65;
+
+  function func1(constant cc1:in integer; signal ss1:in t1)
+    return real is
+  begin
+    assert (cc1=65)
+      report "Constants of mode in for functions are not copied properly"         
+      severity failure;
+    assert (ss1=three)
+      report "Signals of mode in for functions are not copied properly"
+      severity failure;
+    return 4.1;
+  end func1;
+BEGIN
+  TESTING: PROCESS
+    variable v1:real;
+  BEGIN
+    s1<=three;
+    wait for 5 ns;
+    v1:=func1(c1,s1);
+    assert NOT( v1 = 4.1 )
+      report "***PASSED TEST: c02s01b01x01p02n02i02900"
+      severity NOTE;
+    assert ( v1 = 4.1 )
+      report "***FAILED TEST: c02s01b01x01p02n02i02900 - Values of actual parameters of mode in are not copied into their associated formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x01p02n02i02900arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2901.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2901.vhd
new file mode 100644
index 0000000..6dd2b0a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2901.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2901.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x01p02n03i02901ent IS
+END c02s01b01x01p02n03i02901ent;
+
+ARCHITECTURE c02s01b01x01p02n03i02901arch OF c02s01b01x01p02n03i02901ent IS
+  type    t1 is (one,two,three);
+  signal    s1 : t1;
+  constant    c1 : integer:=65;
+  procedure proc1(variable vv1:inout real; signal ss1:inout t1) is
+  begin
+    ss1<=two;
+    vv1:=43.1;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+    variable v1:real;
+  BEGIN
+    s1<=three;
+    v1:=65.3;
+    wait for 5 ns;
+    proc1(v1,s1);
+    wait for 5 ns;
+    assert (v1=43.1)
+      report "Variables of mode inout for procedures are not copied properly"
+      severity failure;
+    assert (s1=two)
+      report "Signals of mode inout for procedures are not copied properly"
+      severity failure;
+    assert NOT( v1=43.1 and s1=two )
+      report "***PASSED TEST: c02s01b01x01p02n03i02901"
+      severity NOTE;
+    assert ( v1=43.1 and s1=two )
+      report "***FAILED TEST: c02s01b01x01p02n03i02901 - Mode inout for procedures are not copied properly"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x01p02n03i02901arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2902.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2902.vhd
new file mode 100644
index 0000000..9e5088e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2902.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2902.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x01p02n02i02902ent IS
+END c02s01b01x01p02n02i02902ent;
+
+ARCHITECTURE c02s01b01x01p02n02i02902arch OF c02s01b01x01p02n02i02902ent IS
+  type    t1 is (one,two,three);
+  signal    s1 : t1;
+  constant    c1 : integer:=65;
+
+  procedure proc1(constant cc1:in integer;variable vv1:in real;signal ss1:in t1) is
+  begin
+    assert (cc1=65)
+      report "Constants of mode in for procedures are not copied properly"
+      severity failure;
+    assert (vv1=43.1)
+      report "Variables of mode in for procedures are not copied properly"
+      severity failure;
+    assert (ss1=two)
+      report "Signals of mode in for procedures are not copied properly"
+      severity failure;
+    assert NOT( cc1=65 and vv1=43.1 and ss1=two )
+      report "***PASSED TEST: c02s01b01x01p02n02i02902"
+      severity NOTE;
+    assert ( cc1=65 and vv1=43.1 and ss1=two )
+      report "***FAILED TEST: c02s01b01x01p02n02i02902 - Values of actual parameters of mode in are not copied into their associated formal parameter."
+      severity ERROR;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+    variable v1:real;
+  BEGIN
+    s1<=two;
+    v1:=43.1;
+    wait for 5 ns;
+    proc1(c1,v1,s1);
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x01p02n02i02902arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2903.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2903.vhd
new file mode 100644
index 0000000..2d756ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2903.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2903.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x01p02n02i02903ent IS
+END c02s01b01x01p02n02i02903ent;
+
+ARCHITECTURE c02s01b01x01p02n02i02903arch OF c02s01b01x01p02n02i02903ent IS
+  type    t1 is (one,two,three);
+  signal    s1 : t1;
+  constant    c1 : integer:=65;
+
+  procedure proc1(variable vv1:inout real; signal ss1:inout t1) is
+  begin
+    assert (vv1=43.1)
+      report "Variables of mode inout for procedures are not copied properly"
+      severity failure;
+    assert (ss1=two)
+      report "Signals of mode inout for procedures are not copied properly"
+      severity failure;
+    assert NOT( vv1=43.1 and ss1=two )
+      report "***PASSED TEST: c02s01b01x01p02n02i02903"
+      severity NOTE;
+    assert ( vv1=43.1 and ss1=two )
+      report "***FAILED TEST: c02s01b01x01p02n02i02903 - Values of actual parameters of mode inout are not copied into their associated formal parameter."
+      severity ERROR;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+    variable v1:real;
+  BEGIN
+    s1<=two;
+    v1:=43.1;
+    wait for 5 ns;
+    proc1(v1,s1);
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x01p02n02i02903arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2904.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2904.vhd
new file mode 100644
index 0000000..6808c61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2904.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2904.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x01p02n03i02904ent IS
+END c02s01b01x01p02n03i02904ent;
+
+ARCHITECTURE c02s01b01x01p02n03i02904arch OF c02s01b01x01p02n03i02904ent IS
+  procedure PX (I1 : in Bit; I2 : out Bit; I3 : inout Integer);
+  procedure PX (I1 : in Bit; I2 : out Bit; I3 : inout Integer) is
+  begin
+    I2 := I1;
+    I3 := 10;
+  end PX;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : Bit;
+    variable V2 : Integer;
+  BEGIN
+    PX('1',V1,V2);
+    wait for 5 ns;
+    assert NOT( V1='1' and V2=10 )
+      report "***PASSED TEST: c02s01b01x01p02n03i02904"
+      severity NOTE;
+    assert ( V1='1' and V2=10 )
+      report "***FAILED TEST: c02s01b01x01p02n03i02904 - Mode out for procedures are not copied properly"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x01p02n03i02904arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc291.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc291.vhd
new file mode 100644
index 0000000..2d3dfdb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc291.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc291.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p14n01i00291ent IS
+END c03s01b03x00p14n01i00291ent;
+
+ARCHITECTURE c03s01b03x00p14n01i00291arch OF c03s01b03x00p14n01i00291ent IS
+  type T is
+    range -2147483647 to 2147483647   -- No_failure_here
+    units
+      I ;  
+      J = 2 I;
+      K = 2 J;
+      L = 10 K;
+      M = 1000 L;
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable kk : T := 1 L;
+  BEGIN
+    assert NOT( kk = 20 J )
+      report "***PASSED TEST: c03s01b03x00p14n01i00291"
+      severity NOTE;
+    assert ( kk = 20 J )
+      report "***FAILED TEST: c03s01b03x00p14n01i00291 - The declaration of any physical type whose range is wholly contained within the bounds -2147483647 and +2147483647, inclusive."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p14n01i00291arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2917.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2917.vhd
new file mode 100644
index 0000000..38a7cdc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2917.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2917.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p05n01i02917ent IS
+END c02s01b01x02p05n01i02917ent;
+
+ARCHITECTURE c02s01b01x02p05n01i02917arch OF c02s01b01x02p05n01i02917ent IS
+  type    t1 is (one,two,three);
+  signal    s1 : t1;
+  signal    s2 : integer;
+
+  procedure proc1(signal ss1:inout t1; signal ss2:out integer) is
+  begin
+    ss1<=two after 5 ns;
+    ss2<=2 after 5 ns;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    s1<=three;
+    s2<=3;
+    wait for 5 ns;
+    assert (s1=three)
+      report "Error in initial conditions detected"
+      severity failure;
+    assert (s2=3)
+      report "Error in initial conditions detected"
+      severity failure;
+    proc1(s1,s2);
+    wait for 10 ns;
+    assert (s1=two)
+      report "Error detected in signal assignment for S1"
+      severity failure;
+    assert (s2=2)
+      report "Error detected in signal assignment for S2"
+      severity failure;
+    assert NOT( s1=two and s2=2 )
+      report "***PASSED TEST: c02s01b01x02p05n01i02917"
+      severity NOTE;
+    assert ( s1=two and s2=2 )
+      report "***FAILED TEST: c02s01b01x02p05n01i02917 - Error detected in signal assignemnts."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p05n01i02917arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2918.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2918.vhd
new file mode 100644
index 0000000..c9cbd30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2918.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2918.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p06n01i02918ent IS
+END c02s01b01x02p06n01i02918ent;
+
+ARCHITECTURE c02s01b01x02p06n01i02918arch OF c02s01b01x02p06n01i02918ent IS
+
+  function bit_func ( x : bit) return bit is
+  begin
+    return x;
+  end bit_func ;
+  function bit_vector_func ( x : bit_vector) return bit_vector is
+  begin
+    return x;
+  end bit_vector_func ;
+  function boolean_func ( x : boolean) return boolean is
+  begin
+    return x;
+  end boolean_func ;
+  function character_func ( x : character) return character is   
+  begin
+    return x;
+  end character_func ;
+  function integer_func ( x : integer) return integer is
+  begin
+    return x;
+  end integer_func ;
+  function real_func ( x : real) return real is
+  begin
+    return x;
+  end real_func ;
+  function string_func ( x : string) return string is  
+  begin
+    return x;
+  end string_func ;
+  function time_func ( x : time) return time is
+  begin
+    return x;
+  end time_func ;
+
+BEGIN
+  TESTING: PROCESS
+    variable v : bit_vector (1 to 3) ;
+  BEGIN
+    v(1) := '0';
+    v(2) := '1';
+    v(3) := '0';
+    assert NOT(   (bit_func('1') = '1')       and
+                  (bit_vector_func(v) = v)    and
+                  (boolean_func(true) = true)    and
+                  (character_func('X') = 'X')    and
+                  (integer_func(6) = 6)       and
+                  (real_func(3.14159) = 3.14159)    and
+                  (string_func("qwertyuiop") = "qwertyuiop") and
+                  (time_func(2 ns) = 2 ns)) 
+      report "***PASSED TEST: c02s01b01x02p06n01i02918" 
+      severity NOTE;
+    assert (   (bit_func('1') = '1')       and
+               (bit_vector_func(v) = v)    and
+               (boolean_func(true) = true)    and
+               (character_func('X') = 'X')    and
+               (integer_func(6) = 6)       and
+               (real_func(3.14159) = 3.14159)    and
+               (string_func("qwertyuiop") = "qwertyuiop") and
+               (time_func(2 ns) = 2 ns)) 
+      report "***FAILED TEST: c02s01b01x02p06n01i02918 - Static signal as actual test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p06n01i02918arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc292.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc292.vhd
new file mode 100644
index 0000000..b105417
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc292.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc292.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p26n01i00292ent IS
+  type mytime is range 0 to 30 
+    units
+      fs;
+    end units;
+END c03s01b03x00p26n01i00292ent;
+
+ARCHITECTURE c03s01b03x00p26n01i00292arch OF c03s01b03x00p26n01i00292ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i:integer;
+    variable t:mytime;
+  BEGIN
+    t:= 20 fs;
+    i:= mytime'POS(t);
+    assert NOT( i=20 )
+      report "***PASSED TEST: c03s01b03x00p26n01i00292"
+      severity NOTE;
+    assert ( i=20 )
+      report "***FAILED TEST: c03s01b03x00p26n01i00292 - POS attribute can be used to convert between abstract values and physical values."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p26n01i00292arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc293.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc293.vhd
new file mode 100644
index 0000000..5e1ab01
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc293.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc293.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p26n01i00293ent IS
+  type mytime is range 0 to 30 
+    units
+      fs;
+    end units;
+END c03s01b03x00p26n01i00293ent;
+
+ARCHITECTURE c03s01b03x00p26n01i00293arch OF c03s01b03x00p26n01i00293ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i:integer;
+    variable t:mytime;
+  BEGIN
+    i:= 20;
+    t:= mytime'VAL(i);
+    assert NOT(t=20 fs) 
+      report "***PASSED TEST: c03s01b03x00p26n01i00293"
+      severity NOTE;
+    assert (t=20 fs) 
+      report "***FAILED TEST: c03s01b03x00p26n01i00293 - POS attribute can be used to convert between abstract values and physical values."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p26n01i00293arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2932.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2932.vhd
new file mode 100644
index 0000000..25bbb3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2932.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2932.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p07n01i02932ent IS
+END c02s02b00x00p07n01i02932ent;
+
+ARCHITECTURE c02s02b00x00p07n01i02932arch OF c02s02b00x00p07n01i02932ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable global_int : integer := 0;
+    
+    procedure Recursive_subr ( x: integer ) is
+    begin
+      global_int := global_int + 1;
+      if x > 1 then
+        Recursive_subr (x-1);
+      end if;
+    end Recursive_subr ;
+  BEGIN
+    Recursive_subr (10);
+    wait for 5 ns;
+    assert NOT( global_int = 10 )
+      report "***PASSED TEST: c02s02b00x00p07n01i02932"
+      severity NOTE;
+    assert ( global_int = 10 )
+      report "***FAILED TEST: c02s02b00x00p07n01i02932 - Recursive procedure test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n01i02932arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc294.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc294.vhd
new file mode 100644
index 0000000..82668e2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc294.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc294.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n02i00294ent IS
+END c03s01b03x01p01n02i00294ent;
+
+ARCHITECTURE c03s01b03x01p01n02i00294arch OF c03s01b03x01p01n02i00294ent IS
+  signal T1 : TIME := -2147483647 ns;
+  signal T2 : TIME := +2147483467 ns;   -- no_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(T1=-2147483647 ns and T2=+2147483467 ns)
+      report "***PASSED TEST:c03s01b03x01p01n02i00294"
+      severity NOTE;
+    assert (T1=-2147483647 ns and T2=+2147483467 ns)
+      report "***FAILED TEST: c03s01b03x01p01n02i00294 - The range of TIME is guaranteed to include the range -2147483647 to +2147483467."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n02i00294arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2945.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2945.vhd
new file mode 100644
index 0000000..90cb3bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2945.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2945.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p07n05i02945pkg is
+  function F1 (i : integer) return Boolean;
+end c02s02b00x00p07n05i02945pkg;
+
+package body c02s02b00x00p07n05i02945pkg is
+  function F1 (i : integer) return Boolean is
+  begin
+    return TRUE;
+  end F1;
+end c02s02b00x00p07n05i02945pkg;
+
+
+use work.c02s02b00x00p07n05i02945pkg.all;
+ENTITY c02s02b00x00p07n05i02945ent IS
+END c02s02b00x00p07n05i02945ent;
+
+ARCHITECTURE c02s02b00x00p07n05i02945arch OF c02s02b00x00p07n05i02945ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : boolean;
+  BEGIN
+    k := F1(2);
+    assert NOT( k=TRUE )
+      report "***PASSED TEST: c02s02b00x00p07n05i02945"
+      severity NOTE;
+    assert ( k=TRUE )
+      report "***FAILED TEST: c02s02b00x00p07n05i02945 - Subprogram Function declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n05i02945arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2948.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2948.vhd
new file mode 100644
index 0000000..5e0fb61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2948.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2948.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p08n02i02948ent IS
+END c02s02b00x00p08n02i02948ent;
+
+ARCHITECTURE c02s02b00x00p08n02i02948arch OF c02s02b00x00p08n02i02948ent IS
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+  begin
+    I2   <= '1';
+    I3   <=  6;
+  end PX;    -- No_failure_here
+
+  signal S1 : Bit    := '1';
+  signal S2 : Integer    := 5;
+  signal S3 : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    PX(S1,S3,S2);
+    wait for 5 ns;
+    assert NOT(S3='1' and S2=6)
+      report "***PASSED TEST: c02s02b00x00p08n02i02948"
+      severity NOTE;
+    assert (S3='1' and S2=6)
+      report "***FAILED TEST: c02s02b00x00p08n02i02948 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p08n02i02948arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2949.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2949.vhd
new file mode 100644
index 0000000..55a4315
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2949.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2949.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p12n01i02949ent IS
+END c02s02b00x00p12n01i02949ent;
+
+ARCHITECTURE c02s02b00x00p12n01i02949arch OF c02s02b00x00p12n01i02949ent IS
+
+  function CreateN(constant size : in INTEGER) return STRING is
+    variable result : STRING(1 to size);
+    variable ch : CHARACTER;
+  begin
+    ch := 'A';
+    for i in result'RANGE loop
+      result(i) := ch;
+      ch := CHARACTER'SUCC(ch);
+      if ch > 'Z' then
+        ch := 'Z';
+      end if;
+    end loop;
+    return result;
+  end;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert "A" = CreateN(1) report CreateN(1);
+    assert "AB" = CreateN(2) report CreateN(2);
+    assert "ABCDEFGHIJ" = CreateN(10) report CreateN(10);
+
+    assert NOT(    "A" = CreateN(1)   and
+                   "AB" = CreateN(2)   and
+                   "ABCDEFGHIJ" = CreateN(10))
+      report "***PASSED TEST: c02s02b00x00p12n01i02949"
+      severity NOTE;
+    assert (    "A" = CreateN(1)   and
+                "AB" = CreateN(2)   and
+                "ABCDEFGHIJ" = CreateN(10))
+      report "***FAILED TEST: c02s02b00x00p12n01i02949 - The execution of a subprogram test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p12n01i02949arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc295.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc295.vhd
new file mode 100644
index 0000000..fb83cc4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc295.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc295.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n03i00295ent IS
+END c03s01b03x01p01n03i00295ent;
+
+ARCHITECTURE c03s01b03x01p01n03i00295arch OF c03s01b03x01p01n03i00295ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( (time'pos(fs) = 1)    and
+                (ps  = 1000 fs)    and
+                (ns  = 1000 ps) )
+      report "***PASSED TEST: c03s01b03x01p01n03i00295"
+      severity NOTE;
+    assert ( (time'pos(fs) = 1) and
+             (ps  = 1000 fs) and
+             (ns  = 1000 ps) )
+      report "***FAILED TEST: c03s01b03x01p01n03i00295 - Type TIME is defined with an ascending ragne."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n03i00295arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2950.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2950.vhd
new file mode 100644
index 0000000..f6bd51c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2950.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2950.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p12n01i02950ent IS
+END c02s02b00x00p12n01i02950ent;
+
+ARCHITECTURE c02s02b00x00p12n01i02950arch OF c02s02b00x00p12n01i02950ent IS
+
+  function Concat(
+    constant in1 : in STRING;
+    constant in2 : in STRING
+    ) return STRING is
+    variable result : STRING(1 to (in1'LENGTH + in2'LENGTH));
+  begin
+    for i in in1'RANGE loop
+      result(result'left + i - in1'left) := in1(i);
+    end loop;
+    for i in in2'RANGE loop
+      result(result'left + in1'length + i - in2'left) := in2(i);
+    end loop;
+    return result;
+  end;
+
+BEGIN
+  TESTING: PROCESS
+    constant in1 : STRING := "PASS IF more:";
+    constant in2 : STRING := " HEY, THIS IS MORE!";
+  BEGIN
+
+    assert NOT( Concat(in1, in2) = "PASS IF more: HEY, THIS IS MORE!" )
+      report "***PASSED TEST: c02s02b00x00p12n01i02950"
+      severity NOTE;
+    assert ( Concat(in1, in2) = "PASS IF more: HEY, THIS IS MORE!" )
+      report "***FAILED TEST: c02s02b00x00p12n01i02950 - The execution of a subprogram test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p12n01i02950arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2951.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2951.vhd
new file mode 100644
index 0000000..806feaf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2951.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2951.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p12n01i02951ent IS
+END c02s02b00x00p12n01i02951ent;
+
+ARCHITECTURE c02s02b00x00p12n01i02951arch OF c02s02b00x00p12n01i02951ent IS
+
+  function Concat(
+    constant in1 : in STRING;
+    constant in2 : in STRING
+    ) return STRING is
+    variable result : STRING(1 to (in1'LENGTH + in2'LENGTH));
+  begin
+    for i in in1'RANGE loop
+      result(result'left + i - in1'left) := in1(i);
+    end loop;
+    for i in in2'RANGE loop
+      result(result'left + in1'length + i - in2'left) := in2(i);
+    end loop;
+    return result;
+  end;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT( Concat( Concat("Let's ","try "), Concat("multiple ", "levels!")) =
+                "Let's try multiple levels!" )
+      report "***PASSED TEST: c02s02b00x00p12n01i02951"
+      severity NOTE;
+    assert ( Concat( Concat("Let's ","try "), Concat("multiple ", "levels!")) =
+             "Let's try multiple levels!" )
+      report "***FAILED TEST: c02s02b00x00p12n01i02951 - The execution of a subprogram test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p12n01i02951arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2952.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2952.vhd
new file mode 100644
index 0000000..7f67132
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2952.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2952.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p24n01i02952pkg is
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
+end c02s02b00x00p24n01i02952pkg;
+
+use work.c02s02b00x00p24n01i02952pkg.all;
+ENTITY c02s02b00x00p24n01i02952ent IS
+END c02s02b00x00p24n01i02952ent;
+
+ARCHITECTURE c02s02b00x00p24n01i02952arch OF c02s02b00x00p24n01i02952ent IS
+  signal S1 : Bit    := '1';
+  signal S2 : Integer    := 5;
+  signal S3 : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    PX(S1,S3,S2) ;            ---  No_failure_here
+    wait for 5 ns;
+    assert NOT(S3='1' and S2=12)
+      report "***PASSED TEST: c02s02b00x00p24n01i02952" 
+      severity NOTE;
+    assert (S3='1' and S2=12)
+      report "***FAILED TEST: c02s02b00x00p24n01i02952 - Subprogram declaration should appear before call of subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p24n01i02952arch;
+
+
+package body c02s02b00x00p24n01i02952pkg is
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+  begin
+    assert (I1 /= '1')
+      report "No failure on test" 
+      severity note;
+    assert (I3 /= 5)
+      report "No failure on test" 
+      severity note;
+    I2 <=   '1';
+    I3 <=   12;
+  end PX;
+end c02s02b00x00p24n01i02952pkg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2955.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2955.vhd
new file mode 100644
index 0000000..02d008e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2955.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2955.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p02n01i02955ent IS
+  procedure greater (i:integer; res:out boolean);
+  procedure greater (i:integer; res:out boolean) is
+    type       mine    is (vero,falso);
+    subtype    digit    is integer range 1 to 10;
+    constant    high   :integer:=10;
+    variable    zero   :integer;
+    variable    itl   :mine;
+  begin
+    zero := 0;
+    if i <= high then
+      itl:= vero;
+      res:= TRUE;
+    else 
+      res:= FALSE;
+    end if;
+  end greater;
+END c02s02b00x00p02n01i02955ent;
+
+ARCHITECTURE c02s02b00x00p02n01i02955arch OF c02s02b00x00p02n01i02955ent IS
+  subtype digit is integer range 1 to 10;
+BEGIN
+  TESTING: PROCESS
+    variable i:digit;
+    variable k:boolean;
+  BEGIN
+    i:= 5;
+    greater (i,k);
+    wait for 5 ns;
+    assert NOT( k=TRUE )
+      report "***PASSED TEST: c02s02b00x00p02n01i02955"
+      severity NOTE;
+    assert ( k=TRUE )
+      report "***FAILED TEST: c02s02b00x00p02n01i02955 - Subprogram body syntax test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p02n01i02955arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2959.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2959.vhd
new file mode 100644
index 0000000..77ca383
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2959.vhd
@@ -0,0 +1,155 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2959.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s03b00x00p02n01i02959pkg is
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN bit_vector;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN boolean;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN character;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN real;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN string;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN time;
+end c02s03b00x00p02n01i02959pkg;
+
+package body c02s03b00x00p02n01i02959pkg is
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN time IS
+  BEGIN
+    assert false report "boo with TIME returned" severity note;
+    RETURN 10 ns;
+  END;
+
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN string IS
+  BEGIN
+    assert false report "boo with STRING returned" severity note;
+    RETURN "STRING";
+  END;
+
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN real IS
+  BEGIN
+    assert false report "boo with REAL returned" severity note;
+    RETURN 10.01;
+  END;
+
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN integer IS
+  BEGIN
+    assert false report "boo with INTEGER returned" severity note;
+    RETURN 55;
+  END;
+
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN character IS
+  BEGIN
+    assert false report "boo with CHARACTER returned" severity note;
+    RETURN 'Z';
+  END;
+
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN boolean IS
+  BEGIN
+    assert false report "boo with BOOLEAN returned" severity note;
+    RETURN TRUE;
+  END;
+  
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN bit_vector IS
+  BEGIN
+    assert false report "boo with BIT_VECTOR returned" severity
+      note;
+    RETURN "1010";
+  END;
+  
+  FUNCTION boo (  PARM_VAL : bit_vector) RETURN bit IS
+  BEGIN
+    assert false report "boo with BIT returned" severity note;
+    RETURN '1';
+  END;
+end c02s03b00x00p02n01i02959pkg;
+
+ENTITY c02s03b00x00p02n01i02959ent IS
+  PORT (bb: INOUT bit;
+        bv: INOUT bit_vector(0 TO 3);
+        bo: INOUT boolean;
+        cc: INOUT character;
+        ii: INOUT integer;
+        rr: INOUT real;
+        ss: INOUT string(1 TO 6);
+        tt: INOUT time);
+  SUBTYPE bv_4 IS bit_vector(1 TO 4);
+  SUBTYPE bv_6 IS bit_vector(1 TO 6);
+  
+  FUNCTION foo (  PARM_VAL : bv_4) RETURN bit_vector IS
+  BEGIN
+    assert false report "function foo in entity e" severity note;
+    RETURN PARM_VAL;
+  END;
+END c02s03b00x00p02n01i02959ent;
+
+use work.c02s03b00x00p02n01i02959pkg.all;
+ARCHITECTURE c02s03b00x00p02n01i02959arch OF c02s03b00x00p02n01i02959ent IS
+  SIGNAL c1 : bv_4;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    c1 <= boo ( bv_6'(OTHERS => '1'));
+    bb <= boo (c1);
+    bv <= boo (c1);
+    bo <= boo (c1);
+    cc <= boo (c1);
+    ii <= boo (c1);
+    rr <= boo (c1);
+    ss <= boo (c1);
+    tt <= boo (c1);
+    
+    WAIT FOR 1 ns;
+    assert NOT(    (c1 = "1010") AND
+                   (bb = '1') AND
+                   (bv = "1010") AND
+                   (bo = TRUE) AND
+                   (cc = 'Z') AND
+                   (ii = 55) AND
+                   (rr = 10.01) AND
+                   (ss = "STRING") AND
+                   (tt = 10 ns))
+      report "***PASSED TEST: c02s03b00x00p02n01i02959"
+      severity NOTE;
+    assert (    (c1 = "1010") AND
+                (bb = '1') AND
+                (bv = "1010") AND
+                (bo = TRUE) AND
+                (cc = 'Z') AND
+                (ii = 55) AND
+                (rr = 10.01) AND
+                (ss = "STRING") AND
+                (tt = 10 ns))
+      report "***FAILED TEST: c02s03b00x00p02n01i02959 - Overloaded functions test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p02n01i02959arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2960.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2960.vhd
new file mode 100644
index 0000000..879a913
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2960.vhd
@@ -0,0 +1,151 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2960.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s03b00x00p02n01i02960pkg is
+  FUNCTION boo ( PARM_VAL : bit) RETURN integer;
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
+  FUNCTION boo ( PARM_VAL : boolean) RETURN integer;
+  FUNCTION boo ( PARM_VAL : character) RETURN integer;
+  FUNCTION boo ( PARM_VAL : integer) RETURN integer;
+  FUNCTION boo ( PARM_VAL : real) RETURN integer;
+  FUNCTION boo ( PARM_VAL : string) RETURN integer;
+  FUNCTION boo ( PARM_VAL : time) RETURN integer;
+end c02s03b00x00p02n01i02960pkg;
+
+package body c02s03b00x00p02n01i02960pkg is
+  FUNCTION boo ( PARM_VAL : bit) RETURN integer IS
+  BEGIN
+    assert false report "boo with BIT param" severity note;
+    RETURN 1;
+  END;
+
+  FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer IS
+  BEGIN
+    assert false report "boo with BIT_VECTOR param" severity note;
+    RETURN 2;
+  END;
+
+  FUNCTION boo ( PARM_VAL : boolean) RETURN integer IS
+  BEGIN
+    assert false report "boo with BOOLEAN param" severity note;
+    RETURN 3;
+  END;
+
+  FUNCTION boo ( PARM_VAL : character) RETURN integer IS
+  BEGIN
+    assert false report "boo with CHARACTER param" severity note;
+    RETURN 4;
+  END;
+
+  FUNCTION boo ( PARM_VAL : integer) RETURN integer IS
+  BEGIN
+    assert false report "boo with INTEGER param" severity note;
+    RETURN 5;
+  END;
+
+  FUNCTION boo ( PARM_VAL : real) RETURN integer IS
+  BEGIN
+    assert false report "boo with REAL param" severity note;
+    RETURN 6;
+  END;
+  
+  FUNCTION boo ( PARM_VAL : string) RETURN integer IS
+  BEGIN
+    assert false report "boo with STRING param" severity note;
+    RETURN 7;
+  END;
+  
+  FUNCTION boo ( PARM_VAL : time) RETURN integer IS
+  BEGIN
+    assert false report "boo with TIME param" severity note;
+    RETURN 8;
+  END;
+end c02s03b00x00p02n01i02960pkg;
+
+ENTITY c02s03b00x00p02n01i02960ent IS
+  PORT (bb: INOUT bit;
+        bv: INOUT bit_vector(0 TO 3);
+        bo: INOUT boolean;
+        cc: INOUT character;
+        ii: INOUT integer;
+        rr: INOUT real;
+        ss: INOUT string(1 TO 6);
+        tt: INOUT time);
+  SUBTYPE bv_4 IS bit_vector(1 TO 4);
+  SUBTYPE bv_6 IS bit_vector(1 TO 6);
+  
+  FUNCTION foo (  PARM_VAL : bv_4) RETURN bit_vector IS
+  BEGIN
+    assert false report "function foo in entity e" severity note;
+    RETURN PARM_VAL;
+  END;
+END c02s03b00x00p02n01i02960ent;
+
+use work.c02s03b00x00p02n01i02960pkg.all;
+ARCHITECTURE c02s03b00x00p02n01i02960arch OF c02s03b00x00p02n01i02960ent IS
+  SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    c1 <= boo(bb);
+    c2 <= boo(bv);
+    c3 <= boo(bo);
+    c4 <= boo(cc);
+    c5 <= boo(ii);
+    c6 <= boo(rr);
+    c7 <= boo(ss);
+    c8 <= boo(tt);
+    
+    WAIT FOR 1 ns;
+    assert NOT(   (c1 = 1) AND
+                  (c2 = 2) AND
+                  (c3 = 3) AND
+                  (c4 = 4) AND
+                  (c5 = 5) AND
+                  (c6 = 6) AND
+                  (c7 = 7) AND
+                  (c8 = 8)) 
+      report "***PASSED TEST: c02s03b00x00p02n01i02960"
+      severity NOTE;
+    assert (   (c1 = 1) AND
+               (c2 = 2) AND
+               (c3 = 3) AND
+               (c4 = 4) AND
+               (c5 = 5) AND
+               (c6 = 6) AND
+               (c7 = 7) AND
+               (c8 = 8)) 
+      report "***FAILED TEST: c02s03b00x00p02n01i02960 - Overloaded functions test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p02n01i02960arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2961.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2961.vhd
new file mode 100644
index 0000000..a9cdb47
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2961.vhd
@@ -0,0 +1,143 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2961.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s03b00x00p02n01i02961pkg is
+  FUNCTION boo ( PARM_VAL: bit:='1')       RETURN bit;
+  FUNCTION boo ( PARM_VAL: bit_vector:="1010")RETURN bit_vector;
+  FUNCTION boo ( PARM_VAL: boolean:=TRUE)    RETURN boolean;
+  FUNCTION boo ( PARM_VAL: character:='Z')    RETURN character;
+  FUNCTION boo ( PARM_VAL: integer:=55)    RETURN integer;
+  FUNCTION boo ( PARM_VAL: real:=10.01)    RETURN real;
+  FUNCTION boo ( PARM_VAL: string:="STRING")    RETURN string;
+  FUNCTION boo ( PARM_VAL: time:=10 ns)    RETURN time;
+end c02s03b00x00p02n01i02961pkg;
+
+package body c02s03b00x00p02n01i02961pkg is
+  FUNCTION boo ( PARM_VAL: bit:='1') RETURN bit IS
+  BEGIN
+    assert false report "boo with BIT param" severity note;
+    RETURN PARM_VAL;
+  END;
+
+  FUNCTION boo ( PARM_VAL: bit_vector:="1010") RETURN bit_vector IS
+  BEGIN
+    assert false report "boo with BIT_VECTOR param" severity note;
+    RETURN PARM_VAL;
+  END;
+
+  FUNCTION boo ( PARM_VAL: boolean:=TRUE) RETURN boolean IS
+  BEGIN
+    assert false report "boo with BOOLEAN param" severity note;
+    RETURN PARM_VAL;
+  END;
+
+  FUNCTION boo ( PARM_VAL: character:='Z') RETURN character IS
+  BEGIN
+    assert false report "boo with CHARACTER param" severity note;
+    RETURN PARM_VAL;
+  END;
+
+  FUNCTION boo ( PARM_VAL: integer:=55) RETURN integer IS
+  BEGIN
+    assert false report "boo with INTEGER param" severity note;
+    RETURN PARM_VAL;
+  END;
+  
+  FUNCTION boo ( PARM_VAL: real:=10.01) RETURN real IS
+  BEGIN
+    assert false report "boo with REAL param" severity note;
+    RETURN PARM_VAL;
+  END;
+  
+  FUNCTION boo ( PARM_VAL: string:="STRING") RETURN string IS
+  BEGIN
+    assert false report "boo with STRING param" severity note;
+    RETURN PARM_VAL;
+  END;
+  
+  FUNCTION boo ( PARM_VAL: time:=10 ns) RETURN time IS
+  BEGIN
+    assert false report "boo with TIME param" severity note;
+    RETURN PARM_VAL;
+  END;
+end c02s03b00x00p02n01i02961pkg;
+
+ENTITY c02s03b00x00p02n01i02961ent IS
+  PORT (bb: INOUT bit;
+        bv: INOUT bit_vector(0 TO 3);
+        bo: INOUT boolean;
+        cc: INOUT character;
+        ii: INOUT integer;
+        rr: INOUT real;
+        ss: INOUT string(1 TO 6);
+        tt: INOUT time);
+END c02s03b00x00p02n01i02961ent;
+
+use work.c02s03b00x00p02n01i02961pkg.all;
+ARCHITECTURE c02s03b00x00p02n01i02961arch OF c02s03b00x00p02n01i02961ent IS
+  SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    bb <= boo;
+    bv <= boo;
+    bo <= boo;
+    cc <= boo;
+    ii <= boo;
+    rr <= boo;
+    ss <= boo;
+    tt <= boo;
+    
+    WAIT FOR 1 ns;
+    assert NOT(   (bb = '1')    AND
+                  (bv = "1010")    AND
+                  (bo = TRUE)    AND
+                  (cc = 'Z')    AND
+                  (ii = 55)    AND
+                  (rr = 10.01)    AND
+                  (ss = "STRING") AND
+                  (tt = 10 ns))   
+      report "***PASSED TEST: c02s03b00x00p02n01i02961"
+      severity NOTE;
+    assert (   (bb = '1')    AND
+               (bv = "1010")    AND
+               (bo = TRUE)    AND
+               (cc = 'Z')    AND
+               (ii = 55)    AND
+               (rr = 10.01)    AND
+               (ss = "STRING") AND
+               (tt = 10 ns))   
+      report "***FAILED TEST: c02s03b00x00p02n01i02961 - Overloaded functions test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p02n01i02961arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2962.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2962.vhd
new file mode 100644
index 0000000..ecc8041
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2962.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2962.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b00x00p02n01i02962ent IS
+  port    (f,h,i    : out integer);
+  type    tripe    is (alpha,beta,gamma,delta,epsilon);
+  subtype subt    is tripe range beta to epsilon;
+END c02s03b00x00p02n01i02962ent;
+
+ARCHITECTURE c02s03b00x00p02n01i02962arch OF c02s03b00x00p02n01i02962ent IS
+  function funk (signal fa,fb : tripe) return integer is
+  begin
+    return (1);
+  end;
+  function funk (signal fa,fb : bit) return integer is
+  begin
+    return (2);
+  end;
+  signal bv1       : bit_vector (1 to 40);
+  signal a,b,c    : subt;
+  signal d,e,g    : integer;
+BEGIN
+  d <= funk(a,b);
+  TESTING: PROCESS
+    variable x : integer;
+  BEGIN
+    WAIT FOR 1 ns;
+    e <= funk(c,a);
+    x := funk(c,b);
+    g <= funk(bv1(2),bv1(6));
+    wait for 5 ns;
+    assert NOT(e=1 and x=1 and g=2)
+      report "***PASSED TEST: c02s03b00x00p02n01i02962"
+      severity NOTE;
+    assert (e=1 and x=1 and g=2)
+      report "***FAILED TEST: c02s03b00x00p02n01i02962 - Overloaded functions test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p02n01i02962arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2964.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2964.vhd
new file mode 100644
index 0000000..d6311ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2964.vhd
@@ -0,0 +1,184 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2964.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b00x00p03n01i02964ent IS
+END c02s03b00x00p03n01i02964ent;
+
+ARCHITECTURE c02s03b00x00p03n01i02964arch OF c02s03b00x00p03n01i02964ent IS
+  function f1a(constant c1 : in integer) return integer is
+  begin
+    return 12;
+  end;
+  function f1a(constant c1,c2 : in integer) return integer is
+  begin
+    return 25;
+  end;
+  function f2b(constant c1 : in integer) return integer is
+  begin
+    return 22;
+  end;
+  function f2b(constant c1 : in real) return integer is
+  begin
+    return 28;
+  end;
+  function f3c(constant c0:integer; constant c1:real) return integer is
+  begin
+    return 32;
+  end;
+  function f3c(constant c1:real; constant c0:integer) return integer is
+  begin
+    return 38;
+  end;
+  function f4d(constant c1 : in integer) return integer is
+  begin
+    return 42;
+  end;
+  function f4d(constant c1 : in integer) return real is
+  begin
+    return 48.0;
+  end;
+  function f5e(constant c1 : in integer) return integer is
+  begin
+    return 52;
+  end;
+  procedure f5e(constant c1 : in integer) is
+  begin
+    return;
+  end;
+  function f6f(constant c0 : in real;constant c1 : in integer) return integer is
+  begin
+    return 62;
+  end;
+  function f6f(constant c2 : in integer;constant c3 : in real) return integer is
+  begin
+    return 68;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable i1 : integer;
+    variable r1 : real;
+    variable k  : integer := 0;
+  BEGIN
+    i1 := 8;
+    if (i1 /= 8) then
+      k := 1;
+    end if;
+    assert (i1=8)
+      report "Error in initial conditions detected"
+      severity failure;
+    i1:= f1a(4);
+    if (i1 /= 12) then
+      k := 1;
+    end if;
+    assert (i1=12)
+      report "Error differentiating overloaded subprog by number of formals"
+      severity failure;
+    i1:=f1a(16,23);
+    if (i1 /= 25) then
+      k := 1;
+    end if;
+    assert (i1=25)
+      report "Error differentiating overloaded subprog by number of formals"
+      severity failure;
+    i1:= f2b(4);
+    if (i1 /= 22) then
+      k := 1;
+    end if;
+    assert (i1=22)
+      report "Error differentiating overloaded subprog by type of formals"
+      severity failure;
+    i1:=f2b(4.0);
+    if (i1 /= 28) then
+      k := 1;
+    end if;
+    assert (i1=28)
+      report "Error differentiating overloaded subprog by type of formals"
+      severity failure;
+    i1:= f3c(4,4.0);
+    if (i1 /= 32) then
+      k := 1;
+    end if;
+    assert (i1=32)
+      report "Error differentiating overloaded subprog by order of formals"
+      severity failure;
+    i1:= f3c(4.0,4);
+    if (i1 /= 38) then
+      k := 1;
+    end if;
+    assert (i1=38)
+      report "Error differentiating overloaded subprog by order of formals"
+      severity failure;
+    i1:= f4d(4);
+    if (i1 /= 42) then
+      k := 1;
+    end if;
+    assert (i1=42)
+      report "Error differentiating overloaded subprog by return type"
+      severity failure;
+
+    r1:= f4d(4);
+    if (r1 /= 48.0) then
+      k := 1;
+    end if;
+    assert (r1=48.0)
+      report "Error differentiating overloaded subprog by return type"
+      severity failure;
+    i1:= f5e(4);
+    if (i1 /= 52) then
+      k := 1;
+    end if;
+    assert (i1=52)
+      report "Error differentiating overloaded subprog by having a return"
+      severity failure;
+    i1:= f6f(c1 => 4, c0 => 4.4);
+    if (i1 /= 62) then
+      k := 1;
+    end if;
+    assert (i1=62)
+      report "Error differentiating overloaded subprog by name of formals"
+      severity failure;
+    i1:= f6f(c3 => 4.4, c2 => 4);
+    if (i1 /= 68) then
+      k := 1;
+    end if;
+    assert (i1=68)
+      report "Error differentiating overloaded subprog by name of formals"
+      severity failure;
+    wait for 5 ns;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c02s03b00x00p03n01i02964"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c02s03b00x00p03n01i02964 - Overload subprogram call test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p03n01i02964arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2966.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2966.vhd
new file mode 100644
index 0000000..19e3863
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2966.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2966.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p01n01i02966ent IS
+END c02s03b01x00p01n01i02966ent;
+
+ARCHITECTURE c02s03b01x00p01n01i02966arch OF c02s03b01x00p01n01i02966ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function "and" (a, b: in integer) return boolean is
+    begin
+      return false;
+    end;
+    variable i1, i2    :integer := 2;
+    variable b1, b2    :boolean := true;
+    variable q1      :boolean ;
+    variable q2      :boolean ;
+    variable q3      :boolean ;
+  BEGIN
+    q1 := i1 and i2;
+    q2 := b1 and b2;
+    q3 := "and" (i1, i2);
+    wait for 5 ns;
+    assert NOT( q1=false and q2=true and q3=false )
+      report "***PASSED TEST: c02s03b01x00p01n01i02966"
+      severity NOTE;
+    assert ( q1=false and q2=true and q3=false )
+      report "***FAILED TEST: c02s03b01x00p01n01i02966 - Function overload test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p01n01i02966arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2967.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2967.vhd
new file mode 100644
index 0000000..a7f7fe5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2967.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2967.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p02n01i02967ent IS
+END c02s03b01x00p02n01i02967ent;
+
+ARCHITECTURE c02s03b01x00p02n01i02967arch OF c02s03b01x00p02n01i02967ent IS
+  function "not" (I1:Bit) return bit is
+  begin
+    if (I1 = '1') then
+      return '1';
+    else
+      return '0';
+    end if;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit;
+  BEGIN
+    k := not('1');
+    assert NOT(k='1')
+      report "***PASSED TEST: c02s03b01x00p02n01i02967" 
+      severity NOTE;
+    assert (k='1')
+      report "***FAILED TEST: c02s03b01x00p02n01i02967 - The subprogram specification of a unary operator must have only a single parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p02n01i02967arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2968.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2968.vhd
new file mode 100644
index 0000000..90c94f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2968.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2968.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p02n02i02968ent IS
+END c02s03b01x00p02n02i02968ent;
+
+ARCHITECTURE c02s03b01x00p02n02i02968arch OF c02s03b01x00p02n02i02968ent IS
+  type newt is (one,two,three,four);
+  function "abs" (constant c1 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of right operator"
+      severity failure;
+    assert NOT( c1=10 )
+      report "***PASSED TEST: c02s03b01x00p02n02i02968"
+      severity NOTE;
+    assert ( c1=10 )
+      report "***FAILED TEST: c02s03b01x00p02n02i02968 - Error in association of operands."
+      severity ERROR;
+    return three;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    wait for 5 ns;
+    n1 := two;
+    assert (n1=two)
+      report "Error in initial conditions detected"
+      severity failure;
+    n1:= abs 10;
+    assert (n1=three)
+      report "Error in call to operloaded operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p02n02i02968arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2969.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2969.vhd
new file mode 100644
index 0000000..58871ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2969.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2969.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p02n02i02969ent IS
+END c02s03b01x00p02n02i02969ent;
+
+ARCHITECTURE c02s03b01x00p02n02i02969arch OF c02s03b01x00p02n02i02969ent IS
+  type newt is (one,two,three,four);
+  function "mod" (constant c1,c2 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of left operator"
+      severity failure;
+    assert (c2=20)
+      report "Error in association of right operator"
+      severity failure;
+    assert NOT( c1=10 and c2=20 )
+      report "***PASSED TEST: c02s03b01x00p02n02i02969"
+      severity NOTE;
+    assert ( c1=10 and c2=20 )
+      report "***FAILED TEST: c02s03b01x00p02n02i02969 - Error in association of operands."
+      severity ERROR;
+    return three;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    wait for 5 ns;
+    n1 := two;
+    assert (n1=two)
+      report "Error in initial conditions detected"
+      severity failure;
+    n1:= 10 mod 20;
+    assert (n1=three)
+      report "Error in call to operloaded operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p02n02i02969arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc297.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc297.vhd
new file mode 100644
index 0000000..72dd46f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc297.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc297.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n04i00297ent IS
+END c03s01b03x01p01n04i00297ent;
+
+ARCHITECTURE c03s01b03x01p01n04i00297arch OF c03s01b03x01p01n04i00297ent IS
+  constant T1 : TIME := 10 ns;
+  signal   S : BIT ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S <= '1' after T1;   
+    wait for 20 ns;
+    assert NOT(S='1') 
+      report "***PASSED TEST: c03s01b03x01p01n04i00297" 
+      severity NOTE;
+    assert (S='1') 
+      report "***FAILED TEST: c03s01b03x01p01n04i00297 - The delay specification is not of type TIME."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n04i00297arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2972.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2972.vhd
new file mode 100644
index 0000000..d27ced3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2972.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2972.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p03n01i02972ent IS
+END c02s03b01x00p03n01i02972ent;
+
+ARCHITECTURE c02s03b01x00p03n01i02972arch OF c02s03b01x00p03n01i02972ent IS
+  type newt is (one,two,three,four);
+  function "+" (constant c1 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of unary + operator"
+      severity failure;
+    assert NOT( c1=10 )
+      report "***PASSED TEST: c02s03b01x00p03n01i02972"
+      severity NOTE;
+    assert ( c1=10 )
+      report "***FAILED TEST: c02s03b01x00p03n01i02972 - Error in + overloading as unary operator."
+      severity ERROR;
+    return four;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    n1:= +10;
+    assert (n1=four)
+      report "Error in call to overloaded unary + operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p03n01i02972arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2973.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2973.vhd
new file mode 100644
index 0000000..93eb39c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2973.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2973.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p03n01i02973ent IS
+END c02s03b01x00p03n01i02973ent;
+
+ARCHITECTURE c02s03b01x00p03n01i02973arch OF c02s03b01x00p03n01i02973ent IS
+  type newt is (one,two,three,four);
+  function "+" (constant c1,c2 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of left binary  + operator"
+      severity failure;
+    assert (c2=20)
+      report "Error in association of right binary + operator"
+      severity failure;
+    assert NOT( c1=10 and c2=20 )
+      report "***PASSED TEST: c02s03b01x00p03n01i02973"
+      severity NOTE;
+    assert ( c1=10 and c2=20 )
+      report "***FAILED TEST: c02s03b01x00p03n01i02973 - Error in + overloading as binary operator."
+      severity ERROR;
+    return three;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    n1 := two;
+    assert (n1=two)
+      report "Error in initial conditions detected"
+      severity failure;
+    n1:= 10 + 20;
+    assert (n1=three)
+      report "Error in call to overloaded binary + operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p03n01i02973arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2974.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2974.vhd
new file mode 100644
index 0000000..f36bdfd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2974.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2974.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p03n01i02974ent IS
+END c02s03b01x00p03n01i02974ent;
+
+ARCHITECTURE c02s03b01x00p03n01i02974arch OF c02s03b01x00p03n01i02974ent IS
+  type newt is (one,two,three,four);
+  function "-" (constant c1 : in integer) return newt is
+  begin
+    assert (c1=70)
+      report "Error in association of unary - operator"
+      severity failure;
+    assert NOT( c1=70 )
+      report "***PASSED TEST: c02s03b01x00p03n01i02974"
+      severity NOTE;
+    assert ( c1=70 )
+      report "***FAILED TEST: c02s03b01x00p03n01i02974 - Error in - overloading as unary operator."
+      severity ERROR;
+    return four;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    n1:= -70;
+    assert (n1=four)
+      report "Error in call to overloaded unary - operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p03n01i02974arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2975.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2975.vhd
new file mode 100644
index 0000000..5389786
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2975.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2975.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p03n01i02975ent IS
+END c02s03b01x00p03n01i02975ent;
+
+ARCHITECTURE c02s03b01x00p03n01i02975arch OF c02s03b01x00p03n01i02975ent IS
+  type newt is (one,two,three,four);
+  function "-" (constant c1,c2 : in integer) return newt is
+  begin
+    assert (c1=70)
+      report "Error in association of left binary  - operator"
+      severity failure;
+    assert (c2=80)
+      report "Error in association of right binary - operator"
+      severity failure;
+    assert NOT( c1=70 )
+      report "***PASSED TEST: c02s03b01x00p03n01i02975"
+      severity NOTE;
+    assert ( c1=70 )
+      report "***FAILED TEST: c02s03b01x00p03n01i02975 - Error in - overloading as binary operator."
+      severity ERROR;
+    return three;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    n1 := two;
+    assert (n1=two)
+      report "Error in initial conditions detected"
+      severity failure;
+    n1:= 70 - 80;
+    assert (n1=three)
+      report "Error in call to overloaded binary - operator"
+      severity failure;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p03n01i02975arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2976.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2976.vhd
new file mode 100644
index 0000000..b56cea0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2976.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2976.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p05n01i02976ent IS
+END c02s03b01x00p05n01i02976ent;
+
+ARCHITECTURE c02s03b01x00p05n01i02976arch OF c02s03b01x00p05n01i02976ent IS
+  subtype    si is integer range 1 to 4;
+  constant    c1 :  si := 2;
+  signal    s1 :  integer;
+
+  function "=" (constant c1,c2 : in integer) return boolean is
+  begin
+    return false;
+  end;
+
+BEGIN
+  with (c1) select
+    s1 <= 1 after 5 ns when 1,
+    2 after 5 ns when 2,
+    3 after 5 ns when 3,
+    4 after 5 ns when others;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT( (s1<=2) and (s1>=2) )
+      report "***PASSED TEST: c02s03b01x00p05n01i02976"
+      severity NOTE;
+    assert ( (s1<=2) and (s1>=2) )
+      report "***FAILED TEST: c02s03b01x00p05n01i02976 - Error in use of overloaded equality operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p05n01i02976arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2977.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2977.vhd
new file mode 100644
index 0000000..ae01c31
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2977.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2977.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p05n01i02977ent IS
+END c02s03b01x00p05n01i02977ent;
+
+ARCHITECTURE c02s03b01x00p05n01i02977arch OF c02s03b01x00p05n01i02977ent IS
+  function "and" (constant c1,c2 : in boolean) return boolean is
+  begin
+    return true;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable b1 : boolean := true;
+    variable bf : boolean := false;
+    variable bt : boolean := true;
+  BEGIN
+    assert (b1=true)
+      report "Error in initial conditions detected"
+      severity failure;
+    assert (bf=false)
+      report "Error in initial conditions detected"
+      severity failure;
+    assert (bt=true)
+      report "Error in initial conditions detected"
+      severity failure;
+    b1 := bf and bt;
+    assert NOT( b1=true )
+      report "***PASSED TEST: c02s03b01x00p05n01i02977"
+      severity NOTE;
+    assert ( b1=true )
+      report "***FAILED TEST: c02s03b01x00p05n01i02977 - Error in invocation overloaded operator and."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p05n01i02977arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2978.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2978.vhd
new file mode 100644
index 0000000..8d62a1b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2978.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2978.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p07n01i02978ent IS
+END c02s03b01x00p07n01i02978ent;
+
+ARCHITECTURE c02s03b01x00p07n01i02978arch OF c02s03b01x00p07n01i02978ent IS
+  type newt is (one,two,three,four);
+  function "abs" (constant c1 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of right operator"
+      severity failure;
+    return one;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    wait for 5 ns;
+    n1:= "abs"(10);
+    assert (n1=one)
+      report "Error in call to operloaded operator"
+      severity failure;
+    assert NOT( n1=one )
+      report "***PASSED TEST: c02s03b01x00p07n01i02978"
+      severity NOTE;
+    assert ( n1=one )
+      report "***FAILED TEST: c02s03b01x00p07n01i02978 - Error in call to operloaded operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p07n01i02978arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2979.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2979.vhd
new file mode 100644
index 0000000..1229817
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2979.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2979.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p07n01i02979ent IS
+END c02s03b01x00p07n01i02979ent;
+
+ARCHITECTURE c02s03b01x00p07n01i02979arch OF c02s03b01x00p07n01i02979ent IS
+  type newt is (one,two,three,four);
+  function "mod" (constant c1,c2 : in integer) return newt is
+  begin
+    assert (c1=10)
+      report "Error in association of left operator"
+      severity failure;
+    assert (c2=20)
+      report "Error in association of right operator"
+      severity failure;
+    return three;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable n1 : newt;
+  BEGIN
+    wait for 5 ns;
+    n1 := two;
+    assert (n1=two)
+      report "Error in initial conditions detected"
+      severity failure;
+    n1:= "mod"(10,20);
+    assert NOT( n1=three )
+      report "***PASSED TEST: c02s03b01x00p07n01i02979"
+      severity NOTE;
+    assert ( n1=three )
+      report "***FAILED TEST: c02s03b01x00p07n01i02979 - Error in call to operloaded operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p07n01i02979arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc298.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc298.vhd
new file mode 100644
index 0000000..0aeb385
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc298.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc298.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n03i00298ent IS
+END c03s01b03x01p01n03i00298ent;
+
+ARCHITECTURE c03s01b03x01p01n03i00298arch OF c03s01b03x01p01n03i00298ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( (us  = 1000 ns) and
+                (ms  = 1000 us) and
+                (sec = 1000 ms) )
+      report "***PASSED TEST: c03s01b03x01p01n03i00298"
+      severity NOTE;
+    assert (    (us  = 1000 ns) and
+                (ms  = 1000 us) and
+                (sec = 1000 ms) )
+      report "***FAILED TEST: c03s01b03x01p01n03i00298 - Type TIME is defined with an ascending ragne."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n03i00298arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2980.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2980.vhd
new file mode 100644
index 0000000..03e1369
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2980.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2980.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s04b00x00p03n02i02980ent IS
+END c02s04b00x00p03n02i02980ent;
+
+ARCHITECTURE c02s04b00x00p03n02i02980arch OF c02s04b00x00p03n02i02980ent IS
+  -- Create low-level resolution function and its subtypes.
+  function Always_Zero( S : BIT_VECTOR ) return BIT is
+  begin
+    return( '0' );
+  end Always_Zero;
+
+  subtype BIT_SUB is Always_Zero BIT;
+  type NEW_BIT_VECTOR is array( 1 to 10 ) of BIT_SUB;
+  
+  -- Create the composite signal resolved at both levels.
+  signal ONE   : NEW_BIT_VECTOR;
+BEGIN
+  
+  -- Create two drivers for the composite.
+  ONE  <= NEW_BIT_VECTOR'(B"1111111111") after 10 ns;
+  ONE  <= NEW_BIT_VECTOR'(B"0000000000") after 20 ns;
+  
+  TESTING: PROCESS(one)
+  BEGIN
+    assert NOT( ONE = B"0000000000" )
+      report "***PASSED TEST: c02s04b00x00p03n02i02980"
+      severity NOTE;
+    assert ( ONE = B"0000000000" )
+      report "***FAILED TEST: c02s04b00x00p03n02i02980 - Low level resolution function does not got called."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c02s04b00x00p03n02i02980arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2981.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2981.vhd
new file mode 100644
index 0000000..75c5eba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2981.vhd
@@ -0,0 +1,118 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2981.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s04b00x00p04n04i02981ent IS
+END c02s04b00x00p04n04i02981ent;
+
+ARCHITECTURE c02s04b00x00p04n04i02981arch OF c02s04b00x00p04n04i02981ent IS
+  -- Define an array of integers.
+  type INT_ARRAY is array( NATURAL range <> ) of INTEGER;
+
+  -- Define a resolution function.
+  function RESFUNC( S : INT_ARRAY ) return INTEGER is
+    -- local variables.
+    variable MAX : INTEGER := INTEGER'LOW;
+
+  begin
+    if  (S'LENGTH = 0) then
+      return INTEGER'LOW;
+    else
+      for I in S'RANGE loop
+        if  (S(I) > MAX) then
+          MAX := S(I);
+        end if;
+      end loop;
+      return MAX;
+    end if;
+  end;
+
+  -- Define a subtype of integer.
+  subtype SINT is RESFUNC INTEGER;
+
+  -- Define a bus signal.
+  signal B : SINT bus := 0;
+BEGIN
+  -- One process driving B.
+  process
+  begin
+    -- Verify initial conditions.
+    assert( B = 0 );
+    
+    -- Go to NULL.
+    B <=       null  after 10 ns;
+    
+    -- Wait until B gets updated.
+    wait on B;
+    
+    -- Verify that both drivers have been turned off.
+    assert( B = INTEGER'LOW );
+    
+    -- Turn a driver on again.
+    B <= 47 after 10 ns;
+    
+    -- Wait for B to be updated.
+    wait on B;
+    
+    -- Verify that B was updated accordingly.
+    assert( B = 47 );
+    
+    -- End of test.
+    wait;
+  end process;
+  
+  -- Second process driving B.
+  process
+  begin
+    -- Verify initial conditions.
+    assert( B = 0 );
+    
+    -- Go to NULL.
+    B <=       null  after 10 ns;
+    
+    -- Wait until B gets updated.
+    wait on B;
+    
+    -- Verify that both drivers have been turned off.
+    assert( B = INTEGER'LOW );
+    
+    -- End of test.
+    wait;
+  end process;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 50 ns;
+    assert FALSE
+      report "***PASSED TEST: c02s04b00x00p04n04i02981 - This test needs manual check to make sure there is no other ERROR or FAILURE assertion notice."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c02s04b00x00p04n04i02981arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2982.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2982.vhd
new file mode 100644
index 0000000..ecaa350
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2982.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2982.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p01n01i02982pkg is
+  type       tristate    is ('0','1','Z');
+  subtype    bi       is integer range 1 to 2;
+  constant    lowstate   : tristate:='0';
+end c02s05b00x00p01n01i02982pkg;
+
+
+ENTITY c02s05b00x00p01n01i02982ent IS
+END c02s05b00x00p01n01i02982ent;
+
+ARCHITECTURE c02s05b00x00p01n01i02982arch OF c02s05b00x00p01n01i02982ent IS
+  use work.c02s05b00x00p01n01i02982pkg.all;
+BEGIN
+  TESTING: PROCESS
+    variable locz:tristate   :='Z';
+    variable loch:bi   :=2;
+  BEGIN
+    locz:=lowstate;
+    loch:=1;
+    wait for 5 ns;
+    assert NOT( locz='0' and loch<2 )
+      report "***PASSED TEST: c02s05b00x00p01n01i02982"
+      severity NOTE;
+    assert ( locz='0' and loch<2 )
+      report "***FAILED TEST: c02s05b00x00p01n01i02982 - Package declaration syntax test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p01n01i02982arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2987.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2987.vhd
new file mode 100644
index 0000000..557e4ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2987.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2987.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p06n01i02987pkg is
+  constant wtime: time := 5 ns;
+end c02s05b00x00p06n01i02987pkg;
+
+ENTITY c02s05b00x00p06n01i02987ent IS
+END c02s05b00x00p06n01i02987ent;
+
+ARCHITECTURE c02s05b00x00p06n01i02987arch OF c02s05b00x00p06n01i02987ent IS
+  use work.c02s05b00x00p06n01i02987pkg.wtime;
+BEGIN
+  TESTING: PROCESS
+    variable TimeCount : time := 0 ns;
+  BEGIN
+    TimeCount   := NOW;
+    wait for wtime;
+    TimeCount   := NOW - TimeCount;   
+    assert NOT( TimeCount = 5 ns )
+      report "***PASSED TEST: c02s05b00x00p06n01i02987"
+      severity NOTE;
+    assert ( TimeCount = 5 ns )
+      report "***FAILED TEST: c02s05b00x00p06n01i02987 - Package declaration visibility test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p06n01i02987arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2988.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2988.vhd
new file mode 100644
index 0000000..bb1b930
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2988.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2988.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p06n01i02988pkg is
+  constant var : integer := 5;
+end c02s05b00x00p06n01i02988pkg;
+
+ENTITY c02s05b00x00p06n01i02988ent IS
+END c02s05b00x00p06n01i02988ent;
+
+ARCHITECTURE c02s05b00x00p06n01i02988arch OF c02s05b00x00p06n01i02988ent IS
+  use work.c02s05b00x00p06n01i02988pkg.var;
+BEGIN
+  TESTING: PROCESS
+    variable fin : time := 1 ns;
+  BEGIN
+    fin := fin * var;
+    assert NOT( fin = 5 ns )
+      report "***PASSED TEST: c02s05b00x00p06n01i02988"
+      severity NOTE;
+    assert ( fin = 5 ns )
+      report "***FAILED TEST: c02s05b00x00p06n01i02988 - Package declaration visibility test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p06n01i02988arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2989.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2989.vhd
new file mode 100644
index 0000000..29c23ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2989.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2989.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p06n01i02989pkg is
+  constant    c1    : INTEGER;
+  function    f    return INTEGER;
+  procedure    p(x : inout INTEGER);
+end c02s05b00x00p06n01i02989pkg;
+
+package body c02s05b00x00p06n01i02989pkg is
+  constant c1 : INTEGER := 10;
+  constant c2 : INTEGER := 20;
+  function f return INTEGER is
+  begin
+    return c1 + c2;
+  end;
+  procedure p( x: inout INTEGER) is
+  begin
+    x := c1 + c2;
+  end;
+end c02s05b00x00p06n01i02989pkg;
+
+
+ENTITY c02s05b00x00p06n01i02989ent IS
+END c02s05b00x00p06n01i02989ent;
+
+ARCHITECTURE c02s05b00x00p06n01i02989arch OF c02s05b00x00p06n01i02989ent IS
+  signal s1 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
+  signal s2 : INTEGER := WORK.c02s05b00x00p06n01i02989pkg.c1;
+BEGIN
+  TESTING: PROCESS
+    variable temp : INTEGER;
+  BEGIN
+    s1 <= WORK.c02s05b00x00p06n01i02989pkg.F;
+
+    WORK.c02s05b00x00p06n01i02989pkg.P(temp);
+    s2 <= temp;
+    wait for 5 ns;
+    assert NOT( s1 = 30 and s2 = 30 )
+      report "***PASSED TEST: c02s05b00x00p06n01i02989"
+      severity NOTE;
+    assert ( s1 = 30 and s2 = 30 )
+      report "***FAILED TEST: c02s05b00x00p06n01i02989 - Package declaration visibility test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p06n01i02989arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc299.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc299.vhd
new file mode 100644
index 0000000..ae1626e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc299.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc299.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n03i00299ent IS
+END c03s01b03x01p01n03i00299ent;
+
+ARCHITECTURE c03s01b03x01p01n03i00299arch OF c03s01b03x01p01n03i00299ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( (sec = 1000 ms) and
+                (min =  60 sec) and
+                (hr  =  60 min))
+      report "***PASSED TEST:c03s01b03x01p01n03i00299"
+      severity NOTE;
+    assert (    (sec = 1000 ms) and
+                (min =  60 sec) and
+                (hr  =  60 min))
+      report "***FAILED TEST: c03s01b03x01p01n03i00299 - Type TIME is defined with an ascending ragne."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n03i00299arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc2990.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc2990.vhd
new file mode 100644
index 0000000..73d519e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc2990.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2990.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p06n01i02990pkg is
+  signal s_p : INTEGER := 1;
+end c02s05b00x00p06n01i02990pkg;
+ENTITY c02s05b00x00p06n01i02990ent IS
+  signal s_e : INTEGER := 2;
+END c02s05b00x00p06n01i02990ent;
+
+use work.c02s05b00x00p06n01i02990pkg.s_p;
+ARCHITECTURE c02s05b00x00p06n01i02990arch OF c02s05b00x00p06n01i02990ent IS
+  signal s_a : INTEGER := 3;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    s_e <= s_p;
+    wait for 1 ns;
+    s_a <= s_e;
+    wait for 5 ns;
+    assert NOT( s_a = 1 )
+      report "***PASSED TEST: c02s05b00x00p06n01i02990"
+      severity NOTE;
+    assert ( s_a = 1 )
+      report "***FAILED TEST: c02s05b00x00p06n01i02990 - Package declaration visibility test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p06n01i02990arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc30.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc30.vhd
new file mode 100644
index 0000000..b4a84f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc30.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc30.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b00x00p14n04i00030ent IS
+END c04s03b00x00p14n04i00030ent;
+
+ARCHITECTURE c04s03b00x00p14n04i00030arch OF c04s03b00x00p14n04i00030ent IS
+  signal       M1 : BIT_VECTOR(0 to 7) ;
+  constant    M2 : BIT := '1' ;
+BEGIN
+  TESTING: PROCESS
+    variable   V1 : BIT; 
+  BEGIN
+    M1(3) <=    '1' after 10 ns;
+    --- No_failure_here
+    --- M1(3) is also a signal; so this signal
+    --- assignment is possible.
+    V1    :=    M2;   
+    wait for 10 ns;
+    assert NOT( M1(3)='1' and V1='1' )
+      report "***PASSED TEST: c04s03b00x00p14n04i00030"
+      severity NOTE;
+    assert ( M1(3)='1' and V1='1' )
+      report "***FAILED TEST:c04s03b00x00p14n04i00030 - Each subelement of that object is itself an object of the same class as the given object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b00x00p14n04i00030arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3001.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3001.vhd
new file mode 100644
index 0000000..e93bf02
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3001.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3001.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p02n01i03001pkg is
+end c02s06b00x00p02n01i03001pkg;
+
+package body c02s06b00x00p02n01i03001pkg is
+end;
+
+ENTITY c02s06b00x00p02n01i03001ent IS
+END c02s06b00x00p02n01i03001ent;
+
+ARCHITECTURE c02s06b00x00p02n01i03001arch OF c02s06b00x00p02n01i03001ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c02s06b00x00p02n01i03001" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p02n01i03001arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3005.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3005.vhd
new file mode 100644
index 0000000..d4b08e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3005.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3005.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p07n01i03005pkg is
+  constant t: time;
+end c02s06b00x00p07n01i03005pkg;
+
+package body c02s06b00x00p07n01i03005pkg is
+  constant t: time:= 5 ns;
+end c02s06b00x00p07n01i03005pkg;
+
+ENTITY c02s06b00x00p07n01i03005ent IS
+END c02s06b00x00p07n01i03005ent;
+
+ARCHITECTURE c02s06b00x00p07n01i03005arch OF c02s06b00x00p07n01i03005ent IS
+  use work.c02s06b00x00p07n01i03005pkg.all;
+BEGIN
+  TESTING: PROCESS
+    variable x: time;
+  BEGIN
+    x := t;
+    wait for 5 ns;
+    assert NOT( x = 5 ns )
+      report "***PASSED TEST: c02s06b00x00p07n01i03005"
+      severity NOTE;
+    assert ( x = 5 ns )
+      report "***FAILED TEST: c02s06b00x00p07n01i03005 - Deferred constant test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p07n01i03005arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc301.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc301.vhd
new file mode 100644
index 0000000..5e00be8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc301.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc301.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p03n01i00301ent IS
+END c03s01b04x00p03n01i00301ent;
+
+ARCHITECTURE c03s01b04x00p03n01i00301arch OF c03s01b04x00p03n01i00301ent IS
+  type REAL1 is range REAL'LOW to REAL'HIGH;
+BEGIN
+  TESTING: PROCESS
+    variable k : REAL1 := 6.0;
+  BEGIN
+    k := 5.0;
+    assert NOT(k=5.0) 
+      report "***PASSED TEST: c03s01b04x00p03n01i00301" 
+      severity NOTE;
+    assert (k=5.0) 
+      report "***FAILED TEST: c03s01b04x00p03n01i00301 - The range of the type defined by the floating point type is within the range given by the floating point defintion." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p03n01i00301arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3010.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3010.vhd
new file mode 100644
index 0000000..4b87adb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3010.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3010.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p07n01i03010pkg is
+  constant X1 : integer;
+  constant X2 : integer;
+end c02s06b00x00p07n01i03010pkg;
+
+package body c02s06b00x00p07n01i03010pkg is
+  constant X1: integer := 1;
+  constant X2: integer := X1;
+end c02s06b00x00p07n01i03010pkg;
+
+use work.c02s06b00x00p07n01i03010pkg.all;
+ENTITY c02s06b00x00p07n01i03010ent IS
+END c02s06b00x00p07n01i03010ent;
+
+ARCHITECTURE c02s06b00x00p07n01i03010arch OF c02s06b00x00p07n01i03010ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(X1=1 and X2=1)
+      report "***PASSED TEST: c02s06b00x00p07n01i03010" 
+      severity NOTE;
+    assert (X1=1 and X2=1)
+      report "***FAILED TEST: c02s06b00x00p07n01i03010 - Deferred constant declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p07n01i03010arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3016.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3016.vhd
new file mode 100644
index 0000000..0b848ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3016.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3016.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library WORK, STD;
+use STD.STANDARD.all;   -- No_failure_here
+
+ENTITY c11s02b00x00p05n02i03016ent IS
+END c11s02b00x00p05n02i03016ent;
+
+ARCHITECTURE c11s02b00x00p05n02i03016arch OF c11s02b00x00p05n02i03016ent IS
+  signal BV : BIT_VECTOR(0 to 7);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    BV <= "01010111" after 5 ns;
+    wait for 10 ns;
+    assert NOT( BV = "01010111" )
+      report "***PASSED TEST: c11s02b00x00p05n02i03016"
+      severity NOTE;
+    assert ( BV = "01010111" )
+      report "***FAILED TEST: c11s02b00x00p05n02i03016 - Library clause should appear as part of a context clause at the beginning of a design unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s02b00x00p05n02i03016arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3022.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3022.vhd
new file mode 100644
index 0000000..6bb2199
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3022.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3022.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c11s03b00x00p04n02i03022pkg is
+  type T is (one,two,three,four);
+  subtype SIN is INTEGER;
+end c11s03b00x00p04n02i03022pkg;
+
+use work.c11s03b00x00p04n02i03022pkg.all;
+ENTITY c11s03b00x00p04n02i03022ent IS
+END c11s03b00x00p04n02i03022ent;
+
+ARCHITECTURE c11s03b00x00p04n02i03022arch OF c11s03b00x00p04n02i03022ent IS
+  signal S1 : T;      -- type T should be visible
+  signal S2 : SIN;    -- subtype SIN should be visible
+  signal S3 : REAL;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= one;      --literal "one" should be visible
+    S2 <= 1234;
+    wait for 5 ns;
+    assert NOT( S1 = one and S2 = 1234 )
+      report "***PASSED TEST: c11s03b00x00p04n02i03022"
+      severity NOTE;
+    assert ( S1 = one and S2 = 1234 )
+      report "***FAILED TEST: c11s03b00x00p04n02i03022 - A use clause should make certain declarations directly visible within the design unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s03b00x00p04n02i03022arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3023.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3023.vhd
new file mode 100644
index 0000000..876fae9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3023.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3023.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library WORK, STD;
+
+ENTITY c11s02b00x00p05n01i03023ent IS
+END c11s02b00x00p05n01i03023ent;
+
+ARCHITECTURE c11s02b00x00p05n01i03023arch OF c11s02b00x00p05n01i03023ent IS
+  signal S1 : STD.STANDARD.bit;   -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= '1' after 20 ns;
+    wait for 30 ns;
+    assert NOT( S1 = '1' )
+      report "***PASSED TEST: c11s02b00x00p05n01i03023"
+      severity NOTE;
+    assert ( S1 = '1' )
+      report "***FAILED TEST: c11s02b00x00p05n01i03023 - Library logical name may be referenced in the design unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s02b00x00p05n01i03023arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3024.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3024.vhd
new file mode 100644
index 0000000..8bee475
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3024.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3024.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c11s03b00x00p02n01i03024pkg is
+  type T is (one,two);
+end c11s03b00x00p02n01i03024pkg;
+
+ENTITY c11s03b00x00p02n01i03024ent IS
+END c11s03b00x00p02n01i03024ent;
+
+ARCHITECTURE c11s03b00x00p02n01i03024arch OF c11s03b00x00p02n01i03024ent IS
+  signal S : boolean;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S <= TRUE;
+    wait for 3 ns;
+    assert NOT( S = TRUE )
+      report "***PASSED TEST: c11s03b00x00p02n01i03024"
+      severity NOTE;
+    assert ( S = TRUE )
+      report "***FAILED TEST: c11s03b00x00p02n01i03024 - A context clause can contain zero context item."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s03b00x00p02n01i03024arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3029.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3029.vhd
new file mode 100644
index 0000000..306ba99
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3029.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3029.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c11s04b00x00p02n01i03029pkg is
+  type MVL is ('0', '1', 'X', 'Z') ;
+  function F1 (INPUT : Bit) return Bit;
+end c11s04b00x00p02n01i03029pkg;
+
+package body c11s04b00x00p02n01i03029pkg is
+  constant C1 : MVL := '1' ;
+  function F1 (INPUT : Bit) return Bit is
+  begin
+    if Input = '1' then
+      return '0' ;
+    else
+      return '1' ;
+    end if;
+  end F1;
+end c11s04b00x00p02n01i03029pkg;
+
+use work.c11s04b00x00p02n01i03029pkg.all;
+ENTITY c11s04b00x00p02n01i03029ent IS
+END c11s04b00x00p02n01i03029ent;
+
+ARCHITECTURE c11s04b00x00p02n01i03029arch OF c11s04b00x00p02n01i03029ent IS
+  signal S1  : MVL;
+  signal S2  : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= 'Z'    after 20 ns;
+    S2 <= F1('1')    after 50 ns;
+    wait for 60 ns;
+    assert NOT(S1 = 'Z' and S2 = '0')
+      report "***PASSED TEST: c11s04b00x00p02n01i03029" 
+      severity NOTE;
+    assert (S1 = 'Z' and S2 = '0')
+      report "***FAILED TEST: c11s04b00x00p02n01i03029 - Primary unit must be analyzed before the analysis of the unit that references it."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s04b00x00p02n01i03029arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3032.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3032.vhd
new file mode 100644
index 0000000..6784ea9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3032.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3032.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b01x00p01n02i03032ent IS
+END c12s02b01x00p01n02i03032ent;
+
+ARCHITECTURE c12s02b01x00p01n02i03032arch OF c12s02b01x00p01n02i03032ent IS
+  subtype subi is integer range 1   to 10;
+  subtype subr is real    range 1.0 to 10.0;
+  subtype subb is bit     range '1' to '1';
+  type c_a is array(integer range <>) of subi;
+
+  signal s1, s2, s3 : c_a(1 to 3);
+BEGIN
+  -- test array generics
+  bl1: block
+    generic(gi : c_a(1 to 3));
+    generic map (gi => (1,1,1));
+    port   (s11 : OUT c_a(1 to 3));
+    port map (s11 => s1);
+  begin
+    assert ((gi(1)=1) and (gi(2)=1) and (gi(3)=1))
+      report "Generic array GI did not take on the correct low value of 1"
+      severity failure;
+    s11 <= gi;
+  end block;
+  bl2: block
+    generic(gi : c_a(1 to 3));
+    generic map (gi => (5,5,5));
+    port   (s22 : OUT c_a(1 to 3));
+    port map (s22 => s2);
+  begin
+    assert ((gi(1)=5) and (gi(2)=5) and (gi(3)=5))
+      report "Generic array GI did not take on the correct middle value of 5"
+      severity failure;
+    s22 <= gi;
+  end block;
+  bl3: block
+    generic(gi : c_a(1 to 3));
+    generic map (gi => (10,10,10));
+    port   (s33 : OUT c_a(1 to 3));
+    port map (s33 => s3);
+  begin
+    assert ((gi(1)=10) and (gi(2)=10) and (gi(3)=10))
+      report "Generic array GI did not take on the correct high value of 10"
+      severity failure;
+    s33 <= gi;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( s1 = (1,1,1) and s2 = (5,5,5) and s3 = (10,10,10) )
+      report "***PASSED TEST: c12s02b01x00p01n02i03032"
+      severity NOTE;
+    assert ( s1 = (1,1,1) and s2 = (5,5,5) and s3 = (10,10,10) )
+      report "***FAILED TEST: c12s02b01x00p01n02i03032 - Generic constants does not conform to their subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s02b01x00p01n02i03032arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3033.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3033.vhd
new file mode 100644
index 0000000..a900c43
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3033.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3033.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b01x00p01n02i03033ent IS
+END c12s02b01x00p01n02i03033ent;
+
+ARCHITECTURE c12s02b01x00p01n02i03033arch OF c12s02b01x00p01n02i03033ent IS
+  subtype subi is integer range 1 to 10;
+  signal   s1,s2,s3 : subi;
+BEGIN
+
+  bl1: block
+    generic (gi : subi);
+    generic map (gi => 1);
+    port    (s11 : OUT subi);
+    port map (s11 => s1);
+  begin
+    assert (gi=1)
+      report "Generic GI did not take on the correct low value of 1"
+      severity failure;
+    s11 <= gi;
+  end block;
+  bl2: block
+    generic (gi : subi);
+    generic map (gi => 5);
+    port    (s22 : OUT subi);
+    port map (s22 => s2);
+  begin
+    assert (gi=5)
+      report "Generic GI did not take on the correct middle value of 5"         
+      severity failure;
+    s22 <= gi;
+  end block;
+  bl3: block
+    generic (gi : subi);
+    generic map (gi => 10);
+    port    (s33 : OUT subi);
+    port map (s33 => s3);
+  begin
+    assert (gi=10)
+      report "Generic GI did not take on the correct high value of 10"
+      severity failure;
+    s33 <= gi;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( s1 = 1 and s2 = 5 and s3 = 10 )
+      report "***PASSED TEST: c12s02b01x00p01n02i03033"
+      severity NOTE;
+    assert ( s1 = 1 and s2 = 5 and s3 = 10 )
+      report "***FAILED TEST: c12s02b01x00p01n02i03033 - Generic constants does not conform to their subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s02b01x00p01n02i03033arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3034.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3034.vhd
new file mode 100644
index 0000000..73e3567
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3034.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3034.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b01x00p01n02i03034ent IS
+END c12s02b01x00p01n02i03034ent;
+
+ARCHITECTURE c12s02b01x00p01n02i03034arch OF c12s02b01x00p01n02i03034ent IS
+  subtype subi is integer range 1   to 10;
+  subtype subr is real    range 1.0 to 10.0;
+  subtype subb is bit     range '1' to '1';
+
+  type c_r is
+    record
+      i : subi;
+      r : subr;
+      b : subb;
+    end record;
+
+  signal s1, s2, s3 : c_r;
+BEGIN
+  -- test record generics
+  bl4: block
+    generic(gr : c_r);
+    generic map (gr => (1,1.0,'1'));
+    port   (s11 : OUT c_r);
+    port map (s11 => s1);
+  begin
+    assert ((gr.i=1) and (gr.r=1.0) and (gr.b='1'))
+      report "Generic record GR did not take on the correct low value"
+      severity failure;
+    s11 <= gr;
+  end block;
+  bl5: block
+    generic(gr : c_r);
+    generic map (gr => (5,5.0,'1'));
+    port   (s22 : OUT c_r);
+    port map (s22 => s2);
+  begin
+    assert ((gr.i=5) and (gr.r=5.0) and (gr.b='1'))
+      report "Generic record GR did not take on the correct middle value"
+      severity failure;
+    s22 <= gr;
+  end block;
+  bl6: block
+    generic(gr : c_r);
+    generic map (gr => (10,10.0,'1'));
+    port   (s33 : OUT c_r);
+    port map (s33 => s3);
+  begin
+    assert ((gr.i=10) and (gr.r=10.0) and (gr.b='1'))
+      report "Generic record GR did not take on the correct high value"         
+      severity failure;
+    s33 <= gr;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( s1 = (1,1.0,'1') and s2 = (5,5.0,'1') and s3 = (10,10.0,'1') )
+      report "***PASSED TEST: c12s02b01x00p01n02i03034"
+      severity NOTE;
+    assert ( s1 = (1,1.0,'1') and s2 = (5,5.0,'1') and s3 = (10,10.0,'1') )
+      report "***FAILED TEST: c12s02b01x00p01n02i03034 - Generic constants does not conform to their subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s02b01x00p01n02i03034arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3035.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3035.vhd
new file mode 100644
index 0000000..897efd7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3035.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3035.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03035ent IS
+END c12s02b02x00p01n02i03035ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03035arch OF c12s02b02x00p01n02i03035ent IS
+
+BEGIN
+
+  -- test for first element association
+  bl2: block
+    generic(i:integer:=10; r:real:=3.4; b:bit:='1');
+    generic map(i=>5);
+  begin
+    assert (i=5)
+      report "Generic map value for integer generic not correct"
+      severity failure;
+    assert (r=3.4)
+      report "Default value for real generic not correct"
+      severity failure;
+    assert (b='1')
+      report "Default value for bit generic not correct"
+      severity failure;
+
+    assert NOT( i=5 and r=3.4 and b='1')
+      report "***PASSED TEST: c12s02b02x00p01n02i03035"
+      severity NOTE;
+    assert ( i=5 and r=3.4 and b='1')
+      report "***FAILED TEST: c12s02b02x00p01n02i03035 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03035arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3036.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3036.vhd
new file mode 100644
index 0000000..689b53d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3036.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3036.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03036ent IS
+END c12s02b02x00p01n02i03036ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03036arch OF c12s02b02x00p01n02i03036ent IS
+
+BEGIN
+  -- test for no associations
+  bl1: block
+    generic(i:integer:=10; r:real:=3.4; b:bit:='1');
+  begin
+    assert (i=10)
+      report "Default value for integer generic not correct"
+      severity failure;
+    assert (r=3.4)
+      report "Default value for real generic not correct"
+      severity failure;
+    assert (b='1')
+      report "Default value for bit generic not correct"
+      severity failure;
+    assert NOT( i=10 and r=3.4 and b='1')
+      report "***PASSED TEST: c12s02b02x00p01n02i03036"
+      severity NOTE;
+    assert ( i=10 and r=3.4 and b='1')
+      report "***FAILED TEST: c12s02b02x00p01n02i03036 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03036arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3037.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3037.vhd
new file mode 100644
index 0000000..fdd5059
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3037.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3037.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03037ent IS
+END c12s02b02x00p01n02i03037ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03037arch OF c12s02b02x00p01n02i03037ent IS
+
+BEGIN
+
+  -- test for last element association
+  bl3: block
+    generic(i:integer:=10; r:real:=3.4; b:bit:='1');
+    generic map(b=>'0');
+  begin
+    assert (i=10)
+      report "Default value for integer generic not correct"
+      severity failure;
+    assert (r=3.4)
+      report "Default value for real generic not correct"
+      severity failure;
+    assert (b='0')
+      report "Generic map value for bit generic not correct"
+      severity failure;
+
+    assert NOT( i=10 and r=3.4 and b='0')
+      report "***PASSED TEST: c12s02b02x00p01n02i03037"
+      severity NOTE;
+    assert ( i=10 and r=3.4 and b='0')
+      report "***FAILED TEST: c12s02b02x00p01n02i03037 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03037arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3038.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3038.vhd
new file mode 100644
index 0000000..eecbc88
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3038.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3038.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03038ent IS
+END c12s02b02x00p01n02i03038ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03038arch OF c12s02b02x00p01n02i03038ent IS
+
+BEGIN
+  -- test for middle element association
+  bl4: block
+    generic(i:integer:=10; r:real:=3.4; b:bit:='1');
+    generic map(r=>6.7);
+  begin
+    assert (i=10)
+      report "Default value for integer generic not correct"
+      severity failure;
+    assert (r=6.7)
+      report "Generic map value for real generic not correct"
+      severity failure;
+    assert (b='1')
+      report "Default value for bit generic not correct"
+      severity failure;
+
+    assert NOT( i=10 and r=6.7 and b='1')
+      report "***PASSED TEST: c12s02b02x00p01n02i03038"
+      severity NOTE;
+    assert ( i=10 and r=6.7 and b='1')
+      report "***FAILED TEST: c12s02b02x00p01n02i03038 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03038arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3039.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3039.vhd
new file mode 100644
index 0000000..306a35b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3039.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3039.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03039ent IS
+END c12s02b02x00p01n02i03039ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03039arch OF c12s02b02x00p01n02i03039ent IS
+
+BEGIN
+  -- test for first and last element associations
+  bl5: block
+    generic(i:integer:=10; r:real:=3.4; b:bit:='1');
+    generic map(i=>5,b=>'0');
+  begin
+    assert (i=5)
+      report "Generic map value for integer generic not correct"
+      severity failure;
+    assert (r=3.4)
+      report "Default value for real generic not correct"
+      severity failure;
+    assert (b='0')
+      report "Generic map value for bit generic not correct"
+      severity failure;
+
+    assert NOT( i=5 and r=3.4 and b='0')
+      report "***PASSED TEST: c12s02b02x00p01n02i03039"
+      severity NOTE;
+    assert ( i=5 and r=3.4 and b='0')
+      report "***FAILED TEST: c12s02b02x00p01n02i03039 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03039arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3040.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3040.vhd
new file mode 100644
index 0000000..f13ce57
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3040.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3040.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03040ent IS
+END c12s02b02x00p01n02i03040ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03040arch OF c12s02b02x00p01n02i03040ent IS
+  type c_a is array(integer range <>) of integer;
+  type c_r is
+    record
+      i : integer;
+      r : real;
+      b : bit;
+    end record;
+BEGIN
+  -- test for no associations
+  bl1 : block
+    generic(i:c_a(1 to 3):=(10,10,10); r:c_r:=(10,3.4,'1'));
+  begin
+    assert ((i(1)=10) and (i(2)=10) and (i(3)=10))
+      report "Default value for array generic not correct"
+      severity failure;
+    assert ((r.i=10) and (r.r=3.4) and (r.b='1'))
+      report "Default value for record generic not correct"
+      severity failure;
+
+    assert NOT((i(1)=10) and (i(2)=10) and (i(3)=10) and (r.i=10) and (r.r=3.4) and (r.b='1')) 
+      report "***PASSED TEST: c12s02b02x00p01n02i03040"
+      severity NOTE;
+    assert ((i(1)=10) and (i(2)=10) and (i(3)=10) and (r.i=10) and (r.r=3.4) and (r.b='1')) 
+      report "***FAILED TEST: c12s02b02x00p01n02i03040 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03040arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3041.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3041.vhd
new file mode 100644
index 0000000..8750385
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3041.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3041.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03041ent IS
+END c12s02b02x00p01n02i03041ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03041arch OF c12s02b02x00p01n02i03041ent IS
+  type c_a is array(integer range <>) of integer;
+  type c_r is
+    record
+      i : integer;
+      r : real;
+      b : bit;
+    end record;
+BEGIN
+  -- test for first associations
+  bl2 : block
+    generic(i:c_a(1 to 3):=(10,10,10); r:c_r:=(10,3.4,'1'));
+    generic map(i=>(5,5,5));
+  begin
+    assert ((i(1)=5) and (i(2)=5) and (i(3)=5))
+      report "Generic map value for array generic not correct"
+      severity failure;
+    assert ((r.i=10) and (r.r=3.4) and (r.b='1'))
+      report "Default value for record generic not correct"
+      severity failure;
+
+    assert NOT((i(1)=5) and (i(2)=5) and (i(3)=5) and (r.i=10) and (r.r=3.4) and (r.b='1'))
+      report "***PASSED TEST: c12s02b02x00p01n02i03041"
+      severity NOTE;
+    assert ((i(1)=5) and (i(2)=5) and (i(3)=5) and (r.i=10) and (r.r=3.4) and (r.b='1'))
+      report "***FAILED TEST: c12s02b02x00p01n02i03041 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03041arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3042.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3042.vhd
new file mode 100644
index 0000000..5728a05
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3042.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3042.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p01n02i03042ent IS
+END c12s02b02x00p01n02i03042ent;
+
+ARCHITECTURE c12s02b02x00p01n02i03042arch OF c12s02b02x00p01n02i03042ent IS
+  type c_a is array(integer range <>) of integer;
+  type c_r is
+    record
+      i : integer;
+      r : real;
+      b : bit;
+    end record;
+BEGIN
+  -- test for last associations
+  bl3 : block
+    generic(i:c_a(1 to 3):=(10,10,10); r:c_r:=(10,3.4,'1'));
+    generic map(r=>(5,6.7,'0'));
+  begin
+    assert ((i(1)=10) and (i(2)=10) and (i(3)=10))
+      report "Default value for array generic not correct"
+      severity failure;
+    assert ((r.i=5) and (r.r=6.7) and (r.b='0'))
+      report "Generic map value for record generic not correct"
+      severity failure;
+
+    assert NOT((i(1)=10) and (i(2)=10) and (i(3)=10) and (r.i=5) and (r.r=6.7) and (r.b='0'))
+      report "***PASSED TEST: c12s02b02x00p01n02i03042"
+      severity NOTE;
+    assert ((i(1)=10) and (i(2)=10) and (i(3)=10) and (r.i=5) and (r.r=6.7) and (r.b='0'))
+      report "***FAILED TEST: c12s02b02x00p01n02i03042 - The actual part of an implicit association element is the default expression test failed."
+      severity ERROR;
+  end block;
+
+
+END c12s02b02x00p01n02i03042arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3043.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3043.vhd
new file mode 100644
index 0000000..0180eef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3043.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3043.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p02n03i03043ent IS
+END c12s02b02x00p02n03i03043ent;
+
+ARCHITECTURE c12s02b02x00p02n03i03043arch OF c12s02b02x00p02n03i03043ent IS
+
+BEGIN
+  bl1: block
+    generic (i1:integer; i2:integer; i3:integer; i4:integer);
+    generic map(i2=>-5, i1=>3, i4=>-4, i3=>6);
+  begin
+    assert (i1=3)
+      report "Generic association for first element I1 incorrect"
+      severity failure;
+    assert (i2=-5)
+      report "Generic association for second element I2 incorrect"
+      severity failure;
+    assert (i3=6)
+      report "Generic association for third element I3 incorrect"
+      severity failure;
+    assert (i4=-4)
+      report "Generic association for fourth element I4 incorrect"
+      severity failure;
+    assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***PASSED TEST: c12s02b02x00p02n03i03043"
+      severity NOTE;
+    assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***FAILED TEST: c12s02b02x00p02n03i03043 - Named association of generics creates constnats without the correct values."
+      severity ERROR;
+  end block;
+
+END c12s02b02x00p02n03i03043arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3044.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3044.vhd
new file mode 100644
index 0000000..273eeee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3044.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3044.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p02n03i03044ent IS
+END c12s02b02x00p02n03i03044ent;
+
+ARCHITECTURE c12s02b02x00p02n03i03044arch OF c12s02b02x00p02n03i03044ent IS
+
+BEGIN
+  bl1: block
+    generic (i1:integer; i2:integer; i3:integer; i4:integer);
+    generic map(3, -5, 6, -4);
+  begin
+    assert (i1=3)
+      report "Generic association for first element I1 incorrect"
+      severity failure;
+    assert (i2=-5)
+      report "Generic association for second element I2 incorrect"
+      severity failure;
+    assert (i3=6)
+      report "Generic association for third element I3 incorrect"
+      severity failure;
+    assert (i4=-4)
+      report "Generic association for fourth element I4 incorrect"
+      severity failure;
+    assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***PASSED TEST: c12s02b02x00p02n03i03044"
+      severity NOTE;
+    assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***FAILED TEST: c12s02b02x00p02n03i03044 - Positional association of generics creates constants without the correct values."
+      severity ERROR;
+  end block;
+
+END c12s02b02x00p02n03i03044arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3045.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3045.vhd
new file mode 100644
index 0000000..f3cb669
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3045.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3045.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b02x00p02n03i03045ent IS
+END c12s02b02x00p02n03i03045ent;
+
+ARCHITECTURE c12s02b02x00p02n03i03045arch OF c12s02b02x00p02n03i03045ent IS
+
+BEGIN
+  bl1: block
+    generic (i1:integer; i2:integer; i3:integer; i4:integer);
+    generic map(3, -5, i4=>-4, i3=>6);
+  begin
+    assert (i1=3)
+      report "Generic association for first element I1 incorrect"
+      severity failure;
+    assert (i2=-5)
+      report "Generic association for second element I2 incorrect"
+      severity failure;
+    assert (i3=6)
+      report "Generic association for third element I3 incorrect"
+      severity failure;
+    assert (i4=-4)
+      report "Generic association for fourth element I4 incorrect"
+      severity failure;
+    assert NOT( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***PASSED TEST: c12s02b02x00p02n03i03045"
+      severity NOTE;
+    assert ( i1=3 and i2=-5 and i3=6 and i4=-4 )
+      report "***FAILED TEST: c12s02b02x00p02n03i03045 - Named association and positional association of generics creates constnats without the correct values."
+      severity ERROR;
+  end block;
+
+END c12s02b02x00p02n03i03045arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3046.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3046.vhd
new file mode 100644
index 0000000..468aea1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3046.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3046.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b03x00p01n02i03046ent IS
+  type c_r is
+    record
+      i1 : integer;
+      r1 : real;
+      b1 : bit;
+    end record;
+  type c_a is array(1 to 3) of bit;
+END c12s02b03x00p01n02i03046ent;
+
+ARCHITECTURE c12s02b03x00p01n02i03046arch OF c12s02b03x00p01n02i03046ent IS
+  signal sr : c_r := (14,1.4,'1');
+  signal sa : c_a := "101";
+BEGIN
+  b1: block
+    port(r:c_r; a:c_a);
+    port map (r=>sr, a=>sa);
+  begin
+    TESTING: PROCESS
+    BEGIN
+      wait for 5 ns;
+      assert NOT( r=(14,1.4,'1') and a="101")
+        report "***PASSED TEST: c12s02b03x00p01n02i03046"
+        severity NOTE;
+      assert ( r=(14,1.4,'1') and a="101")
+        report "***FAILED TEST: c12s02b03x00p01n02i03046 - Ports should conform to their subtype indication."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b03x00p01n02i03046arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3047.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3047.vhd
new file mode 100644
index 0000000..5c36f74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3047.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3047.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b03x00p01n02i03047ent IS
+END c12s02b03x00p01n02i03047ent;
+
+ARCHITECTURE c12s02b03x00p01n02i03047arch OF c12s02b03x00p01n02i03047ent IS
+  signal si : integer;
+  signal sr : real;
+  signal sb : bit;
+BEGIN
+  si <= 4    after 1 ns;
+  sr <= 3.2    after 1 ns;
+  sb <= '1'    after 1 ns;
+  b1: block
+    port (i:in integer := 3; r:in real := 4.5; b:in bit := '0');
+    port map (i=>si, r=>sr, b=>sb);
+  begin
+    TESTING: PROCESS
+    BEGIN
+      wait for 5 ns;
+      assert NOT( i=4 and r=3.2 and b='1')
+        report "***PASSED TEST: c12s02b03x00p01n02i03047"
+        severity NOTE;
+      assert ( i=4 and r=3.2 and b='1')
+        report "***FAILED TEST: c12s02b03x00p01n02i03047 - Ports should conform to their subtype indication."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b03x00p01n02i03047arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3048.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3048.vhd
new file mode 100644
index 0000000..c1c3cb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3048.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3048.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03048ent IS
+END c12s02b04x00p03n01i03048ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03048arch OF c12s02b04x00p03n01i03048ent IS
+  signal si:integer   := 14;
+  signal sr:real   := 1.4;
+  signal sb:bit   := '0';
+BEGIN
+  -- test for first port associated
+  bl2: block
+    port (i:integer:=4;r:real:=6.4;b:bit:='1');
+    port map (i=>si);
+  begin
+    assert (r=6.4)
+      report "Default expression for unassociated real port R incorrect"
+      severity failure;
+    assert (b='1')
+      report "Default expression for unassociated bit port B incorrect"         
+      severity failure;
+    TESTING: PROCESS
+    BEGIN
+      assert NOT( i=14 and r=6.4 and b='1' )
+        report "***PASSED TEST: c12s02b04x00p03n01i03048"
+        severity NOTE;
+      assert ( i=14 and r=6.4 and b='1' )
+        report "***FAILED TEST: c12s02b04x00p03n01i03048 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b04x00p03n01i03048arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3049.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3049.vhd
new file mode 100644
index 0000000..fbc645c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3049.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3049.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03049ent_a IS
+  port(con : in BIT := '1'; clk : out BIT);
+END c12s02b04x00p03n01i03049ent_a;
+
+ARCHITECTURE c12s02b04x00p03n01i03049arch_a OF c12s02b04x00p03n01i03049ent_a IS
+BEGIN
+  process(con)
+  begin
+    clk <= con;
+  end process;
+END c12s02b04x00p03n01i03049arch_a;
+
+
+ENTITY c12s02b04x00p03n01i03049ent IS
+END c12s02b04x00p03n01i03049ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03049arch OF c12s02b04x00p03n01i03049ent IS
+  signal C : bit := '0';
+  component c12s02b04x00p03n01i03049ent_aa
+    port (   con : IN    bit := '1';
+             clk : OUT   bit   );
+  end component;   
+  for all : c12s02b04x00p03n01i03049ent_aa use entity work.c12s02b04x00p03n01i03049ent_a(c12s02b04x00p03n01i03049arch_a);
+BEGIN
+
+  T1 : c12s02b04x00p03n01i03049ent_aa port map (open, C);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( C = '1' )
+      report "***PASSED TEST: c12s02b04x00p03n01i03049"
+      severity NOTE;
+    assert ( C = '1' )
+      report "***FAILED TEST: c12s02b04x00p03n01i03049 - A port of mode in assumes the value of the default expression when there is no associated signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s02b04x00p03n01i03049arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3050.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3050.vhd
new file mode 100644
index 0000000..0fa2ab0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3050.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3050.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03050ent IS
+END c12s02b04x00p03n01i03050ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03050arch OF c12s02b04x00p03n01i03050ent IS
+  signal si:integer;
+  signal sr:real;
+  signal sb:bit;
+BEGIN
+  -- test for no associated ports
+  bl1: block
+    port (i:integer:=4;r:real:=6.4;b:bit:='1');
+  begin
+    assert (i=4)
+      report "Default expression for unassociated integer port I incorrect"
+      severity failure;
+    assert (r=6.4)
+      report "Default expression for unassociated real port R incorrect"
+      severity failure;
+    assert (b='1')
+      report "Default expression for unassociated bit port B incorrect"         
+      severity failure;
+    TESTING: PROCESS
+    BEGIN
+      assert NOT( i=4 and r=6.4 and b='1' )
+        report "***PASSED TEST: c12s02b04x00p03n01i03050"
+        severity NOTE;
+      assert ( i=4 and r=6.4 and b='1' )
+        report "***FAILED TEST: c12s02b04x00p03n01i03050 - Unassociated ports are not correctly evaluated for the ports of a block."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b04x00p03n01i03050arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3051.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3051.vhd
new file mode 100644
index 0000000..0960fb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3051.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3051.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03051ent IS
+END c12s02b04x00p03n01i03051ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03051arch OF c12s02b04x00p03n01i03051ent IS
+  signal si:integer   := 14;
+  signal sr:real   := 1.4;
+  signal sb:bit   := '0';
+BEGIN
+  -- test for middle port associated
+  bl3: block
+    port (i:integer:=4;r:real:=6.4;b:bit:='1');
+    port map (r=>sr);
+  begin
+    assert (i=4)
+      report "Default expression for unassociated integer port I incorrect"
+      severity failure;
+    assert (b='1')
+      report "Default expression for unassociated bit port B incorrect"         
+      severity failure;
+    TESTING: PROCESS
+    BEGIN
+      assert NOT( i=4 and r=1.4 and b='1' )
+        report "***PASSED TEST: c12s02b04x00p03n01i03051"
+        severity NOTE;
+      assert ( i=4 and r=1.4 and b='1' )
+        report "***FAILED TEST: c12s02b04x00p03n01i03051 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b04x00p03n01i03051arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3052.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3052.vhd
new file mode 100644
index 0000000..fee4bdc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3052.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3052.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03052ent IS
+END c12s02b04x00p03n01i03052ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03052arch OF c12s02b04x00p03n01i03052ent IS
+  signal si:integer   := 14;
+  signal sr:real   := 1.4;
+  signal sb:bit   := '0';
+BEGIN
+  -- test for last port associated
+  bl4: block
+    port (i:integer:=4;r:real:=6.4;b:bit:='1');
+    port map (b=>sb);
+  begin
+    assert (i=4)
+      report "Default expression for unassociated integer port I incorrect"
+      severity failure;
+    assert (r=6.4)
+      report "Default expression for unassociated real port R incorrect"
+      severity failure;
+    TESTING: PROCESS
+    BEGIN
+      assert NOT( i=4 and r=6.4 and b='0' )
+        report "***PASSED TEST: c12s02b04x00p03n01i03052"
+        severity NOTE;
+      assert ( i=4 and r=6.4 and b='0' )
+        report "***FAILED TEST: c12s02b04x00p03n01i03052 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b04x00p03n01i03052arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3053.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3053.vhd
new file mode 100644
index 0000000..149a86f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3053.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3053.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s02b04x00p03n01i03053ent IS
+END c12s02b04x00p03n01i03053ent;
+
+ARCHITECTURE c12s02b04x00p03n01i03053arch OF c12s02b04x00p03n01i03053ent IS
+  signal si:integer   := 14;
+  signal sr:real   := 1.4;
+  signal sb:bit   := '0';
+BEGIN
+  -- test for end ports associated
+  bl5: block
+    port (i:integer:=4;r:real:=6.4;b:bit:='1');
+    port map (i=>si, b=>sb);
+  begin
+    assert (r=6.4)
+      report "Default expression for unassociated real port R incorrect"
+      severity failure;
+    TESTING: PROCESS
+    BEGIN
+      assert NOT( i=14 and r=6.4 and b='0' )
+        report "***PASSED TEST: c12s02b04x00p03n01i03053"
+        severity NOTE;
+      assert ( i=14 and r=6.4 and b='0' )
+        report "***FAILED TEST: c12s02b04x00p03n01i03053 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s02b04x00p03n01i03053arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3054.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3054.vhd
new file mode 100644
index 0000000..427d744
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3054.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3054.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b00x00p07n03i03054ent IS
+END c12s03b00x00p07n03i03054ent;
+
+ARCHITECTURE c12s03b00x00p07n03i03054arch OF c12s03b00x00p07n03i03054ent IS
+
+BEGIN
+  bl1: block
+    signal si : integer := 3;
+    function int (signal sf : in integer) return integer is
+      constant err:integer := sf;
+    begin
+      return err;
+    end;
+  begin
+    TESTING: PROCESS
+    BEGIN
+      wait for 5 ns;
+      assert NOT( si = int(si) )
+        report "***PASSED TEST: c12s03b00x00p07n03i03054"
+        severity NOTE;
+      assert ( si = int(si) )
+        report "***FAILED TEST: c12s03b00x00p07n03i03054 - Name of a signal used in the declarative part of a subprogram test failed."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c12s03b00x00p07n03i03054arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3055.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3055.vhd
new file mode 100644
index 0000000..d87384e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3055.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3055.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s03b01x00p02n03i03055pkg is
+  subtype BYTE is BIT_VECTOR(7 downto 0);
+  function BIN_TO_INTG (IN_DATA : BYTE) return INTEGER;
+end c12s03b01x00p02n03i03055pkg;
+
+package body c12s03b01x00p02n03i03055pkg is
+  function BIN_TO_INTG (IN_DATA : BYTE) return INTEGER is
+    variable SUM : INTEGER := 0;
+  begin
+    for I in 7 downto 0 loop
+      if (IN_DATA(I) = '1') then
+        SUM := SUM + (2**I);
+      end if;
+    end loop;
+    return SUM;
+  end BIN_TO_INTG;
+end c12s03b01x00p02n03i03055pkg;
+
+use WORK.c12s03b01x00p02n03i03055pkg.all;
+ENTITY c12s03b01x00p02n03i03055ent IS
+END c12s03b01x00p02n03i03055ent;
+
+ARCHITECTURE c12s03b01x00p02n03i03055arch OF c12s03b01x00p02n03i03055ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable S1 : BYTE := "00001111";
+    variable X  : INTEGER;
+  BEGIN
+    X := BIN_TO_INTG(S1) ;
+    assert NOT(X = 15)
+      report "***PASSED TEST: c12s03b01x00p02n03i03055" 
+      severity NOTE;
+    assert (X = 15)
+      report "***FAILED TEST: c12s03b01x00p02n03i03055 - Subprogram Body should be elaaborated before subprogram call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b01x00p02n03i03055arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3057.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3057.vhd
new file mode 100644
index 0000000..ee3c0ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3057.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3057.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b01x04p10n01i03057ent IS
+END c12s03b01x04p10n01i03057ent;
+
+ARCHITECTURE c12s03b01x04p10n01i03057arch OF c12s03b01x04p10n01i03057ent IS
+
+  function f1(constant sb : in bit) return bit is
+    constant b : bit := sb;
+  begin
+    assert (b=sb)
+      report "Constant B in function F1 set to non-static variable failed"
+      severity failure;
+    assert NOT( b=sb )
+      report "***PASSED TEST: c12s03b01x04p10n01i03057"
+      severity NOTE;
+    assert ( b=sb )
+      report "***FAILED TEST: c12s03b01x04p10n01i03057 - Non-static expression initializing a constant failed."
+      severity ERROR;
+    return '1';
+  end;
+
+BEGIN
+  TESTING: PROCESS
+    variable vbi,vbr : bit;
+  BEGIN
+    vbi:='1';
+    vbr:=f1(vbi);
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b01x04p10n01i03057arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3059.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3059.vhd
new file mode 100644
index 0000000..7c6bd05
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3059.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3059.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b01x05p01n02i03059ent IS
+END c12s03b01x05p01n02i03059ent;
+
+ARCHITECTURE c12s03b01x05p01n02i03059arch OF c12s03b01x05p01n02i03059ent IS
+  signal R_NUM : BIT_VECTOR(0 to 15) := "1010101001010101";
+  alias  NUMB  : BIT_VECTOR(7 downto 0) is R_NUM(8 to 15);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( NUMB = "01010101" )
+      report "***PASSED TEST: c12s03b01x05p01n02i03059"
+      severity NOTE;
+    assert ( NUMB = "01010101" )
+      report "***FAILED TEST: c12s03b01x05p01n02i03059 - Alias for an array object has a matching element for each element of the named object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b01x05p01n02i03059arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3060.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3060.vhd
new file mode 100644
index 0000000..f4385d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3060.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3060.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b02x01p06n03i03060ent IS
+  ATTRIBUTE attr1 : string;
+END c12s03b02x01p06n03i03060ent;
+
+ARCHITECTURE c12s03b02x01p06n03i03060arch OF c12s03b02x01p06n03i03060ent IS
+
+  FUNCTION f1 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  RETURN i+1;  END;
+  FUNCTION f2 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  RETURN i+2;  END;
+
+  ATTRIBUTE attr1 OF f1 : FUNCTION IS "a string of pearls";
+  ATTRIBUTE attr1 OF f2 : FUNCTION IS "TLA";
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    ASSERT f1'attr1 = "a string of pearls" 
+      REPORT "ERROR: Bad value for f1'attr1" 
+      SEVERITY FAILURE;
+    ASSERT f2'attr1 = "TLA"                
+      REPORT "ERROR: Bad value for f2'attr1" 
+      SEVERITY FAILURE;
+--
+    ASSERT f1'attr1(1) = 'a' REPORT "ERROR: Bad value for f1'attr1(1)" SEVERITY FAILURE;
+    ASSERT f2'attr1(3) = 'A' REPORT "ERROR: Bad value for f2'attr1(3)" SEVERITY FAILURE;
+--
+    assert NOT(    f1'attr1 = "a string of pearls"   and
+                   f2'attr1 = "TLA"      and
+                   f1'attr1(1) = 'a'      and
+                   f2'attr1(3) = 'A'      )
+      report "***PASSED TEST: c12s03b02x01p06n03i03060"
+      severity NOTE;
+    assert (    f1'attr1 = "a string of pearls"   and
+                f2'attr1 = "TLA"      and
+                f1'attr1(1) = 'a'      and
+                f2'attr1(3) = 'A'      )
+      report "***FAILED TEST: c12s03b02x01p06n03i03060 - No an implicit subtype conversion is necessary for an attribute of an unconstrained array type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b02x01p06n03i03060arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3061.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3061.vhd
new file mode 100644
index 0000000..dc2095d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3061.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3061.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b02x01p06n02i03061ent IS
+  SUBTYPE    s10 IS STRING (10 DOWNTO 1);
+  ATTRIBUTE    attr1 : s10;
+END c12s03b02x01p06n02i03061ent;
+
+ARCHITECTURE c12s03b02x01p06n02i03061arch OF c12s03b02x01p06n02i03061ent IS
+  
+  FUNCTION f1 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  RETURN i+1;  END;
+  FUNCTION f2 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  RETURN i+2;  END;
+  
+  ATTRIBUTE attr1 OF f1,f2 : FUNCTION IS "ABCDEFGHIJ";
+  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(    f1'attr1 = "ABCDEFGHIJ"   and
+                   f2'attr1 = "ABCDEFGHIJ"   and
+                   f1'attr1( 1) = 'J'   and
+                   f2'attr1(10) = 'A'   )
+      report "***PASSED TEST: c12s03b02x01p06n02i03061"
+      severity NOTE;
+    assert (    f1'attr1 = "ABCDEFGHIJ"   and
+                f2'attr1 = "ABCDEFGHIJ"   and
+                f1'attr1( 1) = 'J'   and
+                f2'attr1(10) = 'A'   )
+      report "***FAILED TEST: c12s03b02x01p06n02i03061 - An attribute of a constrained array type, an implicit sutype conversion is first applied as for an assignment statement test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b02x01p06n02i03061arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3062.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3062.vhd
new file mode 100644
index 0000000..f8f6792
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3062.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3062.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b02x01p07n01i03062ent IS
+  function setatt return integer is
+  begin
+    return 5;
+  end;
+END c12s03b02x01p07n01i03062ent;
+
+ARCHITECTURE c12s03b02x01p07n01i03062arch OF c12s03b02x01p07n01i03062ent IS
+  signal    sa    :bit;
+  attribute    ai   :integer;
+  attribute    ai of sa:signal is setatt;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert (sa'ai = setatt)
+      report "Attribute AI of signal SA was not set to the correct non-static value"
+      severity failure;
+    assert NOT( sa'ai = setatt )
+      report "***PASSED TEST: c12s03b02x01p07n01i03062"
+      severity NOTE;
+    assert ( sa'ai = setatt )
+      report "***FAILED TEST: c12s03b02x01p07n01i03062 - Non-static expression as an attribute specification test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b02x01p07n01i03062arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3063.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3063.vhd
new file mode 100644
index 0000000..e25cd59
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3063.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3063.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b02x02p01n01i03063ent IS
+  ATTRIBUTE attr1 : INTEGER;
+END c12s03b02x02p01n01i03063ent;
+
+ARCHITECTURE c12s03b02x02p01n01i03063arch OF c12s03b02x02p01n01i03063ent IS
+  
+  FUNCTION f1 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  
+    RETURN i+1;  
+  END;
+  FUNCTION f2 ( i : INTEGER ) RETURN INTEGER IS
+  BEGIN  
+    RETURN i+2;  
+  END;
+  
+  ATTRIBUTE attr1 OF f1,f2 : FUNCTION IS f1(f2(1));
+  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( f1'attr1 = 4 and f2'attr1 = 4 )
+      report "***PASSED TEST: c12s03b02x02p01n01i03063"
+      severity NOTE;
+    assert ( f1'attr1 = 4 and f2'attr1 = 4 )
+      report "***FAILED TEST: c12s03b02x02p01n01i03063 - Elaboration of an attribute test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b02x02p01n01i03063arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3066.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3066.vhd
new file mode 100644
index 0000000..d6d0d68
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3066.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3066.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s04b02x00p02n01i03066ent IS
+END c12s04b02x00p02n01i03066ent;
+
+ARCHITECTURE c12s04b02x00p02n01i03066arch OF c12s04b02x00p02n01i03066ent IS
+  signal    V :    BIT_VECTOR(1 to 4);
+BEGIN
+  FG1: for i in V'range generate
+    B: block
+    begin
+      V(i) <= '0', '1' after i * 10 ns;
+      -- signals should get different delays
+    end block;
+  end generate;
+
+  TESTING: PROCESS(V)
+    variable ok : integer := 1;
+  BEGIN
+    if (Now = 10 ns) then
+      if not(V(1)'event and V(1) = '1') then
+        ok := 0;
+      end if;
+    elsif (Now = 20 ns) then
+      if not(V(2)'event and V(2) = '1') then
+        ok := 0;
+      end if;
+    elsif (Now = 30 ns) then
+      if not(V(3)'event and V(3) = '1') then
+        ok := 0;
+      end if;
+    end if;
+    if (Now > 30 ns) then
+      assert NOT( ok = 1 )
+        report "***PASSED TEST: c12s04b02x00p02n01i03066"
+        severity NOTE;
+      assert ( ok = 1 )
+        report "***FAILED TEST: c12s04b02x00p02n01i03066 - Generate statement semantic test failed."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c12s04b02x00p02n01i03066arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3067.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3067.vhd
new file mode 100644
index 0000000..d8b358f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3067.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3067.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s04b02x00p06n01i03067ent IS
+END c12s04b02x00p06n01i03067ent;
+
+ARCHITECTURE c12s04b02x00p06n01i03067arch OF c12s04b02x00p06n01i03067ent IS
+
+BEGIN
+  G1: if TRUE generate
+    assert FALSE 
+      report "***This assertion note should occur.***" 
+      severity NOTE;
+  end generate;
+  G2: if FALSE generate
+    assert FALSE 
+      report "***This assertion note should not occur.***" 
+      severity ERROR;
+  end generate;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c12s04b02x00p06n01i03067 - This test needs manual check to make sure CORRECT assertion note appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c12s04b02x00p06n01i03067arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3068.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3068.vhd
new file mode 100644
index 0000000..3fc0479
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3068.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3068.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03068pkg is
+  type   severity_level_cons_vector is array (15 downto 0) of severity_level;
+  constant C19 : severity_level_cons_vector := (others => note);
+end c12s06b02x00p06n01i03068pkg;
+
+use work.c12s06b02x00p06n01i03068pkg.all;
+ENTITY c12s06b02x00p06n01i03068ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   severity_level_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03068ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03068arch_a OF c12s06b02x00p06n01i03068ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03068arch_a;
+
+
+use work.c12s06b02x00p06n01i03068pkg.all;
+ENTITY c12s06b02x00p06n01i03068ent IS
+END c12s06b02x00p06n01i03068ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03068arch OF c12s06b02x00p06n01i03068ent IS
+  function scalar_complex(s : integer) return severity_level_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   severity_level_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03068ent_a(c12s06b02x00p06n01i03068arch_a);
+  signal S1 : severity_level_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03068"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03068 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03068arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3069.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3069.vhd
new file mode 100644
index 0000000..937fcb9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3069.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3069.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03069pkg is
+  type   boolean_cons_vector is array (15 downto 0) of boolean;
+  constant C19 : boolean_cons_vector := (others => true);
+end c12s06b02x00p06n01i03069pkg;
+
+use work.c12s06b02x00p06n01i03069pkg.all;
+ENTITY c12s06b02x00p06n01i03069ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   boolean_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03069ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03069arch_a OF c12s06b02x00p06n01i03069ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03069arch_a;
+
+
+use work.c12s06b02x00p06n01i03069pkg.all;
+ENTITY c12s06b02x00p06n01i03069ent IS
+END c12s06b02x00p06n01i03069ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03069arch OF c12s06b02x00p06n01i03069ent IS
+  function scalar_complex(s : integer) return boolean_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   boolean_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03069ent_a(c12s06b02x00p06n01i03069arch_a);
+  signal S1 : boolean_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03069"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03069 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03069arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3070.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3070.vhd
new file mode 100644
index 0000000..1973e65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3070.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3070.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03070pkg is
+  type   integer_cons_vector is array (15 downto 0) of integer;
+  constant C19 : integer_cons_vector := (others => 3);
+end c12s06b02x00p06n01i03070pkg;
+
+use work.c12s06b02x00p06n01i03070pkg.all;
+ENTITY c12s06b02x00p06n01i03070ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   integer_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03070ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03070arch_a OF c12s06b02x00p06n01i03070ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03070arch_a;
+
+
+use work.c12s06b02x00p06n01i03070pkg.all;
+ENTITY c12s06b02x00p06n01i03070ent IS
+END c12s06b02x00p06n01i03070ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03070arch OF c12s06b02x00p06n01i03070ent IS
+  function scalar_complex(s : integer) return integer_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   integer_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03070ent_a(c12s06b02x00p06n01i03070arch_a);
+  signal S1 : integer_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03070"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03070 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03070arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3071.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3071.vhd
new file mode 100644
index 0000000..4014ca4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3071.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3071.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03071pkg is
+  type   time_cons_vector is array (15 downto 0) of time;
+  constant C19 : time_cons_vector := (others => 3 ns);
+end c12s06b02x00p06n01i03071pkg;
+
+use work.c12s06b02x00p06n01i03071pkg.all;
+ENTITY c12s06b02x00p06n01i03071ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   time_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03071ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03071arch_a OF c12s06b02x00p06n01i03071ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03071arch_a;
+
+
+use work.c12s06b02x00p06n01i03071pkg.all;
+ENTITY c12s06b02x00p06n01i03071ent IS
+END c12s06b02x00p06n01i03071ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03071arch OF c12s06b02x00p06n01i03071ent IS
+  function scalar_complex(s : integer) return time_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   time_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03071ent_a(c12s06b02x00p06n01i03071arch_a);
+  signal S1 : time_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03071"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03071 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03071arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3072.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3072.vhd
new file mode 100644
index 0000000..c3ab548
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3072.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3072.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03072pkg is
+  type   natural_cons_vector is array (15 downto 0) of natural;
+  constant C19 : natural_cons_vector := (others => 3);
+end c12s06b02x00p06n01i03072pkg;
+
+use work.c12s06b02x00p06n01i03072pkg.all;
+ENTITY c12s06b02x00p06n01i03072ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   natural_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03072ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03072arch_a OF c12s06b02x00p06n01i03072ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03072arch_a;
+
+
+use work.c12s06b02x00p06n01i03072pkg.all;
+ENTITY c12s06b02x00p06n01i03072ent IS
+END c12s06b02x00p06n01i03072ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03072arch OF c12s06b02x00p06n01i03072ent IS
+  function scalar_complex(s : integer) return natural_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   natural_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03072ent_a(c12s06b02x00p06n01i03072arch_a);
+  signal S1 : natural_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03072"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03072 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03072arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3073.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3073.vhd
new file mode 100644
index 0000000..0840682
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3073.vhd
@@ -0,0 +1,129 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3073.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03073pkg is
+  type   positive_cons_vector is array (15 downto 0) of positive;
+  constant C19 : positive_cons_vector := (others => 3);
+end c12s06b02x00p06n01i03073pkg;
+
+use work.c12s06b02x00p06n01i03073pkg.all;
+ENTITY c12s06b02x00p06n01i03073ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   positive_cons_vector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03073ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03073arch_a OF c12s06b02x00p06n01i03073ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03073arch_a;
+
+
+use work.c12s06b02x00p06n01i03073pkg.all;
+ENTITY c12s06b02x00p06n01i03073ent IS
+END c12s06b02x00p06n01i03073ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03073arch OF c12s06b02x00p06n01i03073ent IS
+  function scalar_complex(s : integer) return positive_cons_vector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   positive_cons_vector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03073ent_a(c12s06b02x00p06n01i03073arch_a);
+  signal S1 : positive_cons_vector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03073"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03073 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03073arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3074.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3074.vhd
new file mode 100644
index 0000000..cbf738f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3074.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3074.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03074pkg is
+  type    boolean_cons_vector is array (15 downto 0) of boolean;
+  type    boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
+  constant C19 : boolean_cons_vectorofvector := (others => (others => true));
+end c12s06b02x00p06n01i03074pkg;
+
+use work.c12s06b02x00p06n01i03074pkg.all;
+ENTITY c12s06b02x00p06n01i03074ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   boolean_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03074ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03074arch_a OF c12s06b02x00p06n01i03074ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03074arch_a;
+
+
+use work.c12s06b02x00p06n01i03074pkg.all;
+ENTITY c12s06b02x00p06n01i03074ent IS
+END c12s06b02x00p06n01i03074ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03074arch OF c12s06b02x00p06n01i03074ent IS
+  function scalar_complex(s : integer) return boolean_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   boolean_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03074ent_a(c12s06b02x00p06n01i03074arch_a);
+  signal S1 : boolean_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03074"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03074 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03074arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3075.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3075.vhd
new file mode 100644
index 0000000..953f056
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3075.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3075.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03075pkg is
+  type    severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type    severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  constant C19 : severity_level_cons_vectorofvector := (others => (others => note));
+end c12s06b02x00p06n01i03075pkg;
+
+use work.c12s06b02x00p06n01i03075pkg.all;
+ENTITY c12s06b02x00p06n01i03075ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   severity_level_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03075ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03075arch_a OF c12s06b02x00p06n01i03075ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03075arch_a;
+
+
+use work.c12s06b02x00p06n01i03075pkg.all;
+ENTITY c12s06b02x00p06n01i03075ent IS
+END c12s06b02x00p06n01i03075ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03075arch OF c12s06b02x00p06n01i03075ent IS
+  function scalar_complex(s : integer) return severity_level_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   severity_level_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03075ent_a(c12s06b02x00p06n01i03075arch_a);
+  signal S1 : severity_level_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03075"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03075 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03075arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3076.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3076.vhd
new file mode 100644
index 0000000..93ebb63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3076.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3076.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03076pkg is
+  type    integer_cons_vector is array (15 downto 0) of integer;
+  type    integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector;
+  constant C19 : integer_cons_vectorofvector := (others => (others => 3));
+end c12s06b02x00p06n01i03076pkg;
+
+use work.c12s06b02x00p06n01i03076pkg.all;
+ENTITY c12s06b02x00p06n01i03076ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   integer_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03076ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03076arch_a OF c12s06b02x00p06n01i03076ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03076arch_a;
+
+
+use work.c12s06b02x00p06n01i03076pkg.all;
+ENTITY c12s06b02x00p06n01i03076ent IS
+END c12s06b02x00p06n01i03076ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03076arch OF c12s06b02x00p06n01i03076ent IS
+  function scalar_complex(s : integer) return integer_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   integer_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03076ent_a(c12s06b02x00p06n01i03076arch_a);
+  signal S1 : integer_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03076"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03076 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03076arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3077.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3077.vhd
new file mode 100644
index 0000000..0337fd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3077.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3077.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03077pkg is
+  type    real_cons_vector is array (15 downto 0) of real;
+  type    real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
+  constant C19 : real_cons_vectorofvector := (others => (others => 3.0));
+end c12s06b02x00p06n01i03077pkg;
+
+use work.c12s06b02x00p06n01i03077pkg.all;
+ENTITY c12s06b02x00p06n01i03077ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   real_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03077ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03077arch_a OF c12s06b02x00p06n01i03077ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03077arch_a;
+
+
+use work.c12s06b02x00p06n01i03077pkg.all;
+ENTITY c12s06b02x00p06n01i03077ent IS
+END c12s06b02x00p06n01i03077ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03077arch OF c12s06b02x00p06n01i03077ent IS
+  function scalar_complex(s : integer) return real_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   real_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03077ent_a(c12s06b02x00p06n01i03077arch_a);
+  signal S1 : real_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03077"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03077 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03077arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3078.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3078.vhd
new file mode 100644
index 0000000..84c1abd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3078.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3078.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03078pkg is
+  type    time_cons_vector is array (15 downto 0) of time;
+  type    time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
+  constant C19 : time_cons_vectorofvector := (others => (others => 3 ns));
+end c12s06b02x00p06n01i03078pkg;
+
+use work.c12s06b02x00p06n01i03078pkg.all;
+ENTITY c12s06b02x00p06n01i03078ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   time_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03078ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03078arch_a OF c12s06b02x00p06n01i03078ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03078arch_a;
+
+
+use work.c12s06b02x00p06n01i03078pkg.all;
+ENTITY c12s06b02x00p06n01i03078ent IS
+END c12s06b02x00p06n01i03078ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03078arch OF c12s06b02x00p06n01i03078ent IS
+  function scalar_complex(s : integer) return time_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   time_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03078ent_a(c12s06b02x00p06n01i03078arch_a);
+  signal S1 : time_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03078"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03078 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03078arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3079.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3079.vhd
new file mode 100644
index 0000000..d8aa950
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3079.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3079.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03079pkg is
+  type    natural_cons_vector is array (15 downto 0) of natural;
+  type    natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
+  constant C19 : natural_cons_vectorofvector := (others => (others => 3));
+end c12s06b02x00p06n01i03079pkg;
+
+use work.c12s06b02x00p06n01i03079pkg.all;
+ENTITY c12s06b02x00p06n01i03079ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   natural_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03079ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03079arch_a OF c12s06b02x00p06n01i03079ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03079arch_a;
+
+
+use work.c12s06b02x00p06n01i03079pkg.all;
+ENTITY c12s06b02x00p06n01i03079ent IS
+END c12s06b02x00p06n01i03079ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03079arch OF c12s06b02x00p06n01i03079ent IS
+  function scalar_complex(s : integer) return natural_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   natural_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03079ent_a(c12s06b02x00p06n01i03079arch_a);
+  signal S1 : natural_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03079"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03079 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03079arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc308.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc308.vhd
new file mode 100644
index 0000000..2606663
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc308.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc308.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p04n01i00308ent IS
+END c03s01b04x00p04n01i00308ent;
+
+ARCHITECTURE c03s01b04x00p04n01i00308arch OF c03s01b04x00p04n01i00308ent IS
+  type REAL1 is range 1.0 to 10.0;
+  type REAL2 is range 10.0 to 20.0;
+  constant V1: REAL1 := 1.0;
+  constant V2: REAL2 := 20.0;
+  type REAL5 is range V1 to V2;
+BEGIN
+  TESTING: PROCESS
+    variable k : REAL5 := 6.0;
+  BEGIN
+    k := 5.0;
+    assert NOT(k=5.0) 
+      report "***PASSED TEST: c03s01b04x00p04n01i00308" 
+      severity NOTE;
+    assert (k=5.0) 
+      report "***FAILED TEST: c03s01b04x00p04n01i00308 - Expressions in floating point constraints in floating point type definitions need not be of the same floating point type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p04n01i00308arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3080.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3080.vhd
new file mode 100644
index 0000000..4477345
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3080.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3080.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s06b02x00p06n01i03080pkg is
+  type    positive_cons_vector is array (15 downto 0) of positive;
+  type    positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
+  constant C19 : positive_cons_vectorofvector := (others => (others => 3));
+end c12s06b02x00p06n01i03080pkg;
+
+use work.c12s06b02x00p06n01i03080pkg.all;
+ENTITY c12s06b02x00p06n01i03080ent_a IS
+  PORT
+    (
+      F1:  OUT  integer ;
+      F3:  IN   positive_cons_vectorofvector;
+      FF:  OUT  integer := 0
+      );
+END c12s06b02x00p06n01i03080ent_a;
+
+ARCHITECTURE c12s06b02x00p06n01i03080arch_a OF c12s06b02x00p06n01i03080ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    F1 <= 3;
+    wait for 0 ns;
+    assert F3'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(0)'active = true)) then
+      F1 <= 11;
+    end if;
+    assert F3(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    if (not(F3(15)'active = true)) then
+      F1 <= 11;
+    end if;
+    wait;
+  END PROCESS;
+
+END c12s06b02x00p06n01i03080arch_a;
+
+
+use work.c12s06b02x00p06n01i03080pkg.all;
+ENTITY c12s06b02x00p06n01i03080ent IS
+END c12s06b02x00p06n01i03080ent;
+
+ARCHITECTURE c12s06b02x00p06n01i03080arch OF c12s06b02x00p06n01i03080ent IS
+  function scalar_complex(s : integer) return positive_cons_vectorofvector is
+  begin
+    return C19;
+  end scalar_complex;
+  component model
+    PORT
+      (    
+        F1:  OUT  integer;
+        F3:  IN   positive_cons_vectorofvector;
+        FF:  OUT  integer
+        );
+  end component;
+  for T1 : model use entity work.c12s06b02x00p06n01i03080ent_a(c12s06b02x00p06n01i03080arch_a);
+  signal S1 : positive_cons_vectorofvector;
+  signal S3 : integer;
+  signal SS : integer := 0;
+BEGIN
+  T1: model
+    port map (
+      scalar_complex(F1) => S1,
+      F3 => scalar_complex(S3),
+      FF => SS
+      );
+  TESTING: PROCESS
+  BEGIN
+
+    S3 <= 3;
+    wait for 0 ns;
+    assert S1'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(0)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+    assert S1(15)'active = true
+      report"no activity on F3 when there is activity on actual" 
+      severity failure;
+
+    assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***PASSED TEST: c12s06b02x00p06n01i03080"
+      severity NOTE;
+    assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
+      report "***FAILED TEST: c12s06b02x00p06n01i03080 - Not every scalar subelement is active if the source itself is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p06n01i03080arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3081.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3081.vhd
new file mode 100644
index 0000000..683916a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3081.vhd
@@ -0,0 +1,138 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3081.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b02x00p05n01i03081ent IS
+END c12s06b02x00p05n01i03081ent;
+
+ARCHITECTURE c12s06b02x00p05n01i03081arch OF c12s06b02x00p05n01i03081ent IS
+  -- Define the resolution function we'll be using.
+  function WIRED_OR( Inputs: BIT_VECTOR) return BIT is
+    constant FLoatValue :BIT := '0';
+  begin
+    for I in Inputs'Range loop
+      if Inputs(I) = '1' then
+        return '1';
+      end if;
+    end loop;
+    return '0';
+  end;
+  
+  -- Define the subtype that has this resolution function.
+  subtype RBIT is WIRED_OR BIT;
+  
+  -- This signal will have its 'ACTIVE flag monitored.
+  signal MONITOR : RBIT := '0';
+  
+  -- This signal will be used to check MONITOR'ACTIVE whenever
+  -- we want to verify that is value is OK.
+  signal CHECK   : RBIT := '0';
+BEGIN
+
+  TESTING: PROCESS
+    variable   testOK   : integer := 0;
+  BEGIN
+    -- Perform a signal value change on both signals.
+    MONITOR <= not MONITOR after 10 ns;
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+    
+    -- Verify that the flags say what we want.
+    assert( not( MONITOR'STABLE ) );
+    if (MONITOR'STABLE) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'EVENT );
+    if (not(MONITOR'EVENT)) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'ACTIVE );
+    if (not(MONITOR'ACTIVE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'QUIET ) );
+    if (MONITOR'QUIET) then
+      testOK := 1;
+    end if;
+    
+    -- Perform no signal value change on MONITOR.
+    MONITOR <=     MONITOR after 10 ns;
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+    
+    -- Verify that the flags say what we want.
+    assert( MONITOR'STABLE );
+    if (not(MONITOR'STABLE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'EVENT ) );
+    if (MONITOR'EVENT) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'ACTIVE );
+    if (not(MONITOR'ACTIVE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'QUIET ) );
+    if (MONITOR'QUIET) then
+      testOK := 1;
+    end if;
+    
+    -- Perform no activity at all on MONITOR.
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+    
+    -- Verify that the flags say what we want.
+    assert( MONITOR'STABLE );
+    if (not(MONITOR'STABLE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'EVENT ) );
+    if (MONITOR'EVENT) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'ACTIVE ) );
+    if (MONITOR'ACTIVE) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'QUIET  );
+    if (not(MONITOR'QUIET)) then
+      testOK := 1;
+    end if;
+    
+    assert NOT( testOK = 0 )
+      report "***PASSED TEST: c12s06b02x00p05n01i03081"
+      severity NOTE;
+    assert ( testOK = 0 )
+      report "***FAILED TEST: c12s06b02x00p05n01i03081 - A signal should be active if one of its sources is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p05n01i03081arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3082.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3082.vhd
new file mode 100644
index 0000000..f248e26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3082.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3082.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b02x00p02n01i03082ent IS
+END c12s06b02x00p02n01i03082ent;
+
+ARCHITECTURE c12s06b02x00p02n01i03082arch OF c12s06b02x00p02n01i03082ent IS
+  -- This signal will have its 'ACTIVE flag monitored.
+  signal MONITOR : BIT := '0';
+
+  -- This signal will be used to check MONITOR'ACTIVE whenever we want to verify that 
+  -- its value is OK.
+  signal CHECK : BIT := '0';
+BEGIN
+
+  TESTING: PROCESS
+    variable   testOK   : integer := 0;
+  BEGIN
+    -- Perform a signal value change on both signals.
+    MONITOR <= not MONITOR after 10 ns;
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+
+    -- Verify that the flags say what we want.
+    assert( not( MONITOR'STABLE ) );
+    if (MONITOR'STABLE) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'EVENT );
+    if (not(MONITOR'EVENT)) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'ACTIVE );
+    if (not(MONITOR'ACTIVE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'QUIET ) );
+    if (MONITOR'QUIET) then
+      testOK := 1;
+    end if;
+
+    -- Perform no signal value change on MONITOR.
+    MONITOR <=     MONITOR after 10 ns;
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+    
+    -- Verify that the flags say what we want.
+    assert( MONITOR'STABLE );
+    if (not(MONITOR'STABLE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'EVENT ) );
+    if (MONITOR'EVENT) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'ACTIVE );
+    if (not(MONITOR'ACTIVE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'QUIET ) );
+    if (MONITOR'QUIET) then
+      testOK := 1;
+    end if;
+    
+    -- Perform no activity at all on MONITOR.
+    CHECK   <= not CHECK   after 10 ns;
+    wait on CHECK;
+    
+    -- Verify that the flags say what we want.
+    assert( MONITOR'STABLE );
+    if (not(MONITOR'STABLE)) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'EVENT ) );
+    if (MONITOR'EVENT) then
+      testOK := 1;
+    end if;
+    assert( not( MONITOR'ACTIVE ) );
+    if (MONITOR'ACTIVE) then
+      testOK := 1;
+    end if;
+    assert( MONITOR'QUIET  );
+    if (not(MONITOR'QUIET)) then
+      testOK := 1;
+    end if;
+    
+    assert NOT( testOK = 0 )
+      report "***PASSED TEST: c12s06b02x00p02n01i03082"
+      severity NOTE;
+    assert ( testOK = 0 )
+      report "***FAILED TEST: c12s06b02x00p02n01i03082 - A signal should be active if one of its sources is active."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b02x00p02n01i03082arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3083.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3083.vhd
new file mode 100644
index 0000000..def581d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3083.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3083.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b03x00p02n01i03083ent IS
+END c12s06b03x00p02n01i03083ent;
+
+ARCHITECTURE c12s06b03x00p02n01i03083arch OF c12s06b03x00p02n01i03083ent IS
+  signal S1 : BIT;
+  signal X1 : BIT;
+  signal S  : integer := 1;
+BEGIN
+
+  S1 <= transport '1' after 5 ns;
+
+  A : block(X1 = '1')
+  begin
+    process(GUARD)
+    begin
+      if GUARD then
+        assert false
+          report "Failure on test. Guard value shouldn't have been changed" ;
+        S <= 0;
+      end if;
+    end process;
+  end block A;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(S = 1)
+      report "***PASSED TEST: c12s06b03x00p02n01i03083" 
+      severity NOTE;
+    assert (S = 1)
+      report "***FAILED TEST: c12s06b03x00p02n01i03083 - GUARD signal is not modified in the test." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b03x00p02n01i03083arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3084.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3084.vhd
new file mode 100644
index 0000000..80bb6fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3084.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3084.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b03x00p02n01i03084ent IS
+END c12s06b03x00p02n01i03084ent;
+
+ARCHITECTURE c12s06b03x00p02n01i03084arch OF c12s06b03x00p02n01i03084ent IS
+  signal S1 : BIT;
+BEGIN
+
+  S1 <= transport '1' after 5 ns,
+        '0' after 15 ns;
+
+  A : block(S1 = '1')
+  begin
+    process
+    begin
+      wait on GUARD;
+      if GUARD then
+        assert false
+          report "No failure; Changes on signal S1 have modified the GUARD signal" 
+          severity NOTE;
+      else
+        assert false
+          report "No failure; Changes on signal S1 have modified the GUARD signal"
+          severity NOTE;
+      end if;
+    end process;
+  end block A;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 50 ns;
+    assert FALSE
+      report "***PASSED TEST: c12s06b03x00p02n01i03084 - This test needs manual check to see other two PASS assertion note."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b03x00p02n01i03084arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3085.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3085.vhd
new file mode 100644
index 0000000..51f239f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3085.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3085.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b03x00p03n01i03085ent IS
+END c12s06b03x00p03n01i03085ent;
+
+ARCHITECTURE c12s06b03x00p03n01i03085arch OF c12s06b03x00p03n01i03085ent IS
+  signal S1 : BIT;
+BEGIN
+  S1 <= transport '1' after 5 ns;
+  TESTING: PROCESS
+  BEGIN
+    wait on S1;
+    assert ( S1'STABLE )
+      report "***PASSED TEST: c12s06b03x00p03n01i03085"
+      severity NOTE;
+    assert NOT( S1'STABLE )
+      report "***FAILED TEST: c12s06b03x00p03n01i03085 - An event occurred on S in this simulation cycle and the current value of the signal is modified."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b03x00p03n01i03085arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3086.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3086.vhd
new file mode 100644
index 0000000..de2702f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3086.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3086.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b04x00p02n01i03086ent IS
+END c12s06b04x00p02n01i03086ent;
+
+ARCHITECTURE c12s06b04x00p02n01i03086arch OF c12s06b04x00p02n01i03086ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable X : TIME;
+  BEGIN
+    X := NOW;
+    assert NOT( X = 0 ns )
+      report "***PASSED TEST: c12s06b04x00p02n01i03086"
+      severity NOTE;
+    assert ( X = 0 ns )
+      report "***FAILED TEST: c12s06b04x00p02n01i03086 - The time at the beginning of the simulation is not 0 ns."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b04x00p02n01i03086arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc309.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc309.vhd
new file mode 100644
index 0000000..0218892
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc309.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc309.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p06n01i00309ent IS
+END c03s01b04x00p06n01i00309ent;
+
+ARCHITECTURE c03s01b04x00p06n01i00309arch OF c03s01b04x00p06n01i00309ent IS
+  type R1 is range -10.0 to 10.0;
+  constant C1 : R1 := 2.0 ;
+  type R2 is range REAL'LOW to REAL'HIGH;
+  signal S1 : R1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= C1 * 2.0 after 5 ns;
+    wait for 10 ns;
+    assert NOT(S1 = 4.0)
+      report "***PASSED TEST: c03s01b04x00p06n01i00309"
+      severity NOTE;
+    assert ( S1=4.0)
+      report "***FAILED TEST: c03s01b04x00p06n01i00309 - The result of an arithmetic operation results in a value belonging to the floating point type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p06n01i00309arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3099.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3099.vhd
new file mode 100644
index 0000000..e2e7c02
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3099.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3099.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p09n01i03099ent IS
+  ATTRIBUTE attr1 : INTEGER;
+END c05s01b00x00p09n01i03099ent;
+
+ARCHITECTURE c05s01b00x00p09n01i03099arch OF c05s01b00x00p09n01i03099ent IS
+  SIGNAL s1,s2,s3 : BIT;
+  SIGNAL s4,s5    : INTEGER;
+  SIGNAL s6,s7    : STRING(1 TO 3);
+
+  ATTRIBUTE attr1 OF s1,s2,s3,s4,s5,s6,s7 : SIGNAL IS 101;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT s1'attr1 = 101 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
+    ASSERT s2'attr1 = 101 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
+    ASSERT s3'attr1 = 101 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
+    ASSERT s4'attr1 = 101 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
+    ASSERT s5'attr1 = 101 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
+    ASSERT s6'attr1 = 101 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
+    ASSERT s7'attr1 = 101 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
+    assert NOT(    s1'attr1 = 101   and
+                   s2'attr1 = 101   and
+                   s3'attr1 = 101   and
+                   s4'attr1 = 101   and
+                   s5'attr1 = 101   and
+                   s6'attr1 = 101   and
+                   s7'attr1 = 101   )
+      report "***PASSED TEST: c05s01b00x00p09n01i03099"
+      severity NOTE;
+    assert (    s1'attr1 = 101   and
+                s2'attr1 = 101   and
+                s3'attr1 = 101   and
+                s4'attr1 = 101   and
+                s5'attr1 = 101   and
+                s6'attr1 = 101   and
+                s7'attr1 = 101   )
+      report "***FAILED TEST: c05s01b00x00p09n01i03099 - Attribute specification applies to the entity designators list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p09n01i03099arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc31.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc31.vhd
new file mode 100644
index 0000000..da82c99
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc31.vhd
@@ -0,0 +1,355 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc31.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p01n01i00031ent IS
+END c04s03b01x01p01n01i00031ent;
+
+ARCHITECTURE c04s03b01x01p01n01i00031arch OF c04s03b01x01p01n01i00031ent IS
+
+--
+--
+--          Declaration of composite types
+--           - array types and subtypes
+--
+  TYPE    ut_chary    IS ARRAY (CHARACTER RANGE <>) OF INTEGER;      -- unconstrained array type    
+  TYPE    ct_word     IS ARRAY (0 TO 15)            OF BIT;          -- constrained array type
+
+  SUBTYPE ust_subchary IS ut_chary;                                  -- unconstrained array subtype
+  SUBTYPE cst_str10    IS STRING    ( 1  TO 10 );                    -- constrained array subtype
+  SUBTYPE cst_digit    IS ut_chary  ('0' TO '9');                    -- constrained array subtype
+--
+--          Declaration of composite types
+--           - records types and subtypes
+--
+  TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+  TYPE rt_date IS
+    RECORD
+      day   : INTEGER RANGE 1 TO 31;
+      month : month_name;
+      year  : INTEGER RANGE 0 TO 4000;
+    END RECORD;
+--
+  SUBTYPE rst_date IS rt_date;
+
+BEGIN
+  TESTING: PROCESS
+--
+--          Constant declarations - without range constraint
+--
+    CONSTANT     STRING_con_1 :     STRING := "sailing";
+    CONSTANT     STRING_con_2 :     STRING := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
+    CONSTANT BIT_VECTOR_con_1 : BIT_VECTOR := B"10101110";
+    CONSTANT BIT_VECTOR_con_2 : BIT_VECTOR := ( '1', '0', '1', '0', '1', '1', '1', '0');
+    CONSTANT   ut_chary_con   :   ut_chary := ( 1, 2, 3, 9, 8, 7);
+    CONSTANT    ct_word_con   :    ct_word := ( '0', '0', '0', '0', '0', '0', '0', '0',
+                                                '0', '0', '0', '0', '0', '0', '0', '0');
+    CONSTANT  cst_str10_con_1 :  cst_str10 := "abcdefghij";
+    CONSTANT  cst_str10_con_2 :  cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');    
+    CONSTANT  cst_digit_con   :  cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
+    CONSTANT    rt_date_con   :    rt_date := (1, Jan, 1989);
+    CONSTANT   rst_date_con   :   rst_date := (1, Apr, 2000);
+    
+----------------------------------------------------------------------------------------------------------
+  BEGIN
+    ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
+
+    ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ut_chary_con(NUL) = 1 REPORT "ut_chary_con('a') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con(SOH) = 2 REPORT "ut_chary_con('b') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con(STX) = 3 REPORT "ut_chary_con('c') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con(ETX) = 9 REPORT "ut_chary_con('d') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con(EOT) = 8 REPORT "ut_chary_con('e') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con(ENQ) = 7 REPORT "ut_chary_con('f') not properly intialized" SEVERITY FAILURE;
+    
+    FOR I IN 0 TO 15
+    LOOP
+      ASSERT ct_word_con(I) = '0' REPORT "ct_word_con(I) not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    
+    ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_digit_con('0') = 0 REPORT "cst_digit_con('0') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('1') = 1 REPORT "cst_digit_con('1') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('2') = 2 REPORT "cst_digit_con('2') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('3') = 3 REPORT "cst_digit_con('3') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('4') = 4 REPORT "cst_digit_con('4') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('5') = 5 REPORT "cst_digit_con('5') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('6') = 6 REPORT "cst_digit_con('6') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('7') = 7 REPORT "cst_digit_con('7') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('8') = 8 REPORT "cst_digit_con('8') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con('9') = 9 REPORT "cst_digit_con('9') not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rt_date_con.day   = 1    REPORT "rt_date_con.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rt_date_con.month = Jan  REPORT "rt_date_con.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rt_date_con.year  = 1989 REPORT "rt_date_con.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_con.day   = 1    REPORT "rst_date_con.day   not properly intialized" SEVERITY
+      FAILURE;
+    ASSERT rst_date_con.month = Apr  REPORT "rst_date_con.month not properly intialized" SEVERITY
+      FAILURE;
+    ASSERT rst_date_con.year  = 2000 REPORT "rst_date_con.year  not properly intialized" SEVERITY
+      FAILURE;
+
+---------------------------------------------------------------------------------------------
+
+    assert NOT(     STRING_con_1(1) = 's'      and 
+                    STRING_con_1(2) = 'a'      and    
+                    STRING_con_1(3) = 'i'      and    
+                    STRING_con_1(4) = 'l'      and    
+                    STRING_con_1(5) = 'i'      and 
+                    STRING_con_1(6) = 'n'      and 
+                    STRING_con_1(7) = 'g'      and 
+                    STRING_con_2(1) = 's'      and 
+                    STRING_con_2(2) = 'a'      and 
+                    STRING_con_2(3) = 'i'      and 
+                    STRING_con_2(4) = 'l'      and 
+                    STRING_con_2(5) = 'i'      and 
+                    STRING_con_2(6) = 'n'      and 
+                    STRING_con_2(7) = 'g'      and 
+                    BIT_VECTOR_con_1(0) = '1'   and 
+                    BIT_VECTOR_con_1(1) = '0'   and 
+                    BIT_VECTOR_con_1(2) = '1'   and 
+                    BIT_VECTOR_con_1(3) = '0'   and 
+                    BIT_VECTOR_con_1(4) = '1'   and 
+                    BIT_VECTOR_con_1(5) = '1'   and 
+                    BIT_VECTOR_con_1(6) = '1'   and 
+                    BIT_VECTOR_con_1(7) = '0'   and 
+                    BIT_VECTOR_con_2(0) = '1'   and 
+                    BIT_VECTOR_con_2(1) = '0'   and 
+                    BIT_VECTOR_con_2(2) = '1'   and 
+                    BIT_VECTOR_con_2(3) = '0'   and 
+                    BIT_VECTOR_con_2(4) = '1'   and 
+                    BIT_VECTOR_con_2(5) = '1'   and 
+                    BIT_VECTOR_con_2(6) = '1'   and 
+                    BIT_VECTOR_con_2(7) = '0'   and 
+                    ut_chary_con(NUL) = 1      and 
+                    ut_chary_con(SOH) = 2      and 
+                    ut_chary_con(STX) = 3      and 
+                    ut_chary_con(ETX) = 9      and 
+                    ut_chary_con(EOT) = 8      and 
+                    ut_chary_con(ENQ) = 7      and  
+                    ct_word_con(0) = '0'      and 
+                    ct_word_con(1) = '0'      and 
+                    ct_word_con(2) = '0'      and 
+                    ct_word_con(3) = '0'      and 
+                    ct_word_con(4) = '0'      and 
+                    ct_word_con(5) = '0'      and 
+                    ct_word_con(6) = '0'      and 
+                    ct_word_con(7) = '0'      and 
+                    ct_word_con(8) = '0'      and 
+                    ct_word_con(9) = '0'      and 
+                    ct_word_con(10) = '0'      and 
+                    ct_word_con(11) = '0'      and 
+                    ct_word_con(12) = '0'      and 
+                    ct_word_con(13) = '0'      and 
+                    ct_word_con(14) = '0'      and 
+                    ct_word_con(15) = '0'      and 
+                    cst_str10_con_1(1) = 'a'   and 
+                    cst_str10_con_1(2) = 'b'   and 
+                    cst_str10_con_1(3) = 'c'   and 
+                    cst_str10_con_1(4) = 'd'   and 
+                    cst_str10_con_1(5) = 'e'   and 
+                    cst_str10_con_1(6) = 'f'   and 
+                    cst_str10_con_1(7) = 'g'   and 
+                    cst_str10_con_1(8) = 'h'   and 
+                    cst_str10_con_1(9) = 'i'   and 
+                    cst_str10_con_1(10)= 'j'   and 
+                    cst_str10_con_2(1) = 'a'   and 
+                    cst_str10_con_2(2) = 'b'   and 
+                    cst_str10_con_2(3) = 'c'   and 
+                    cst_str10_con_2(4) = 'd'   and 
+                    cst_str10_con_2(5) = 'e'   and 
+                    cst_str10_con_2(6) = 'f'   and 
+                    cst_str10_con_2(7) = 'g'   and 
+                    cst_str10_con_2(8) = 'h'   and 
+                    cst_str10_con_2(9) = 'i'   and 
+                    cst_str10_con_2(10)= 'j'   and 
+                    cst_digit_con('0') = 0      and 
+                    cst_digit_con('1') = 1      and 
+                    cst_digit_con('2') = 2      and 
+                    cst_digit_con('3') = 3      and 
+                    cst_digit_con('4') = 4      and 
+                    cst_digit_con('5') = 5      and 
+                    cst_digit_con('6') = 6      and 
+                    cst_digit_con('7') = 7      and 
+                    cst_digit_con('8') = 8      and 
+                    cst_digit_con('9') = 9      and 
+                    rt_date_con.day   = 1      and 
+                    rt_date_con.month = Jan    and 
+                    rt_date_con.year  = 1989   and 
+                    rst_date_con.day   = 1      and 
+                    rst_date_con.month = Apr    and 
+                    rst_date_con.year  = 2000   )    
+      report "***PASSED TEST: /src/ch04/sc03/sb01/ss01/p001/s010101.vhd"
+      severity NOTE;
+    assert (        STRING_con_1(1) = 's'      and 
+                    STRING_con_1(2) = 'a'      and    
+                    STRING_con_1(3) = 'i'      and    
+                    STRING_con_1(4) = 'l'      and    
+                    STRING_con_1(5) = 'i'      and 
+                    STRING_con_1(6) = 'n'      and 
+                    STRING_con_1(7) = 'g'      and 
+                    STRING_con_2(1) = 's'      and 
+                    STRING_con_2(2) = 'a'      and 
+                    STRING_con_2(3) = 'i'      and 
+                    STRING_con_2(4) = 'l'      and 
+                    STRING_con_2(5) = 'i'      and 
+                    STRING_con_2(6) = 'n'      and 
+                    STRING_con_2(7) = 'g'      and 
+                    BIT_VECTOR_con_1(0) = '1'   and 
+                    BIT_VECTOR_con_1(1) = '0'   and 
+                    BIT_VECTOR_con_1(2) = '1'   and 
+                    BIT_VECTOR_con_1(3) = '0'   and 
+                    BIT_VECTOR_con_1(4) = '1'   and 
+                    BIT_VECTOR_con_1(5) = '1'   and 
+                    BIT_VECTOR_con_1(6) = '1'   and 
+                    BIT_VECTOR_con_1(7) = '0'   and 
+                    BIT_VECTOR_con_2(0) = '1'   and 
+                    BIT_VECTOR_con_2(1) = '0'   and 
+                    BIT_VECTOR_con_2(2) = '1'   and 
+                    BIT_VECTOR_con_2(3) = '0'   and 
+                    BIT_VECTOR_con_2(4) = '1'   and 
+                    BIT_VECTOR_con_2(5) = '1'   and 
+                    BIT_VECTOR_con_2(6) = '1'   and 
+                    BIT_VECTOR_con_2(7) = '0'   and 
+                    ut_chary_con(NUL) = 1      and 
+                    ut_chary_con(SOH) = 2      and 
+                    ut_chary_con(STX) = 3      and 
+                    ut_chary_con(ETX) = 9      and 
+                    ut_chary_con(EOT) = 8      and 
+                    ut_chary_con(ENQ) = 7      and  
+                    ct_word_con(0) = '0'      and 
+                    ct_word_con(1) = '0'      and 
+                    ct_word_con(2) = '0'      and 
+                    ct_word_con(3) = '0'      and 
+                    ct_word_con(4) = '0'      and 
+                    ct_word_con(5) = '0'      and 
+                    ct_word_con(6) = '0'      and 
+                    ct_word_con(7) = '0'      and 
+                    ct_word_con(8) = '0'      and 
+                    ct_word_con(9) = '0'      and 
+                    ct_word_con(10) = '0'      and 
+                    ct_word_con(11) = '0'      and 
+                    ct_word_con(12) = '0'      and 
+                    ct_word_con(13) = '0'      and 
+                    ct_word_con(14) = '0'      and 
+                    ct_word_con(15) = '0'      and 
+                    cst_str10_con_1(1) = 'a'   and 
+                    cst_str10_con_1(2) = 'b'   and 
+                    cst_str10_con_1(3) = 'c'   and 
+                    cst_str10_con_1(4) = 'd'   and 
+                    cst_str10_con_1(5) = 'e'   and 
+                    cst_str10_con_1(6) = 'f'   and 
+                    cst_str10_con_1(7) = 'g'   and 
+                    cst_str10_con_1(8) = 'h'   and 
+                    cst_str10_con_1(9) = 'i'   and 
+                    cst_str10_con_1(10)= 'j'   and 
+                    cst_str10_con_2(1) = 'a'   and 
+                    cst_str10_con_2(2) = 'b'   and 
+                    cst_str10_con_2(3) = 'c'   and 
+                    cst_str10_con_2(4) = 'd'   and 
+                    cst_str10_con_2(5) = 'e'   and 
+                    cst_str10_con_2(6) = 'f'   and 
+                    cst_str10_con_2(7) = 'g'   and 
+                    cst_str10_con_2(8) = 'h'   and 
+                    cst_str10_con_2(9) = 'i'   and 
+                    cst_str10_con_2(10)= 'j'   and 
+                    cst_digit_con('0') = 0      and 
+                    cst_digit_con('1') = 1      and 
+                    cst_digit_con('2') = 2      and 
+                    cst_digit_con('3') = 3      and 
+                    cst_digit_con('4') = 4      and 
+                    cst_digit_con('5') = 5      and 
+                    cst_digit_con('6') = 6      and 
+                    cst_digit_con('7') = 7      and 
+                    cst_digit_con('8') = 8      and 
+                    cst_digit_con('9') = 9      and 
+                    rt_date_con.day   = 1      and 
+                    rt_date_con.month = Jan    and 
+                    rt_date_con.year  = 1989   and 
+                    rst_date_con.day   = 1      and 
+                    rst_date_con.month = Apr    and 
+                    rst_date_con.year  = 2000   )   
+      report "***FAILED TEST: c04s03b01x01p01n01i00031 - A constant declares a constant of the specified type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p01n01i00031arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3100.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3100.vhd
new file mode 100644
index 0000000..20bc82d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3100.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3100.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p10n01i03100ent IS
+  ATTRIBUTE attr1 : INTEGER;
+END c05s01b00x00p10n01i03100ent;
+
+ARCHITECTURE c05s01b00x00p10n01i03100arch OF c05s01b00x00p10n01i03100ent IS
+  SIGNAL s1,s2,s3 : BIT;
+  SIGNAL s4,s5    : INTEGER;
+  SIGNAL s6,s7    : STRING(1 TO 3);
+  
+  CONSTANT c1,c2,c3 : BIT            :=   '0';
+  CONSTANT c4,c5    : INTEGER        :=     1;
+  CONSTANT c6,c7    : STRING(1 TO 3) := "ABC";
+  
+  ATTRIBUTE attr1 OF s3, s7 : SIGNAL IS 1;
+  ATTRIBUTE attr1 OF OTHERS : SIGNAL IS 20;
+  
+  ATTRIBUTE attr1 OF c1,c2,c3,c4,c5,c6,c7 : CONSTANT IS 101;
+  ATTRIBUTE attr1 OF OTHERS               : CONSTANT IS 20;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    ASSERT s1'attr1 = 20 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
+    ASSERT s2'attr1 = 20 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
+    ASSERT s3'attr1 = 01 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
+    ASSERT s4'attr1 = 20 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
+    ASSERT s5'attr1 = 20 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
+    ASSERT s6'attr1 = 20 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
+    ASSERT s7'attr1 = 01 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
+    
+    ASSERT c1'attr1 = 101 REPORT "Bad value for c1'attr1" SEVERITY FAILURE;
+    ASSERT c2'attr1 = 101 REPORT "Bad value for c2'attr1" SEVERITY FAILURE;
+    ASSERT c3'attr1 = 101 REPORT "Bad value for c3'attr1" SEVERITY FAILURE;
+    ASSERT c4'attr1 = 101 REPORT "Bad value for c4'attr1" SEVERITY FAILURE;
+    ASSERT c5'attr1 = 101 REPORT "Bad value for c5'attr1" SEVERITY FAILURE;
+    ASSERT c6'attr1 = 101 REPORT "Bad value for c6'attr1" SEVERITY FAILURE;
+    ASSERT c7'attr1 = 101 REPORT "Bad value for c7'attr1" SEVERITY FAILURE;
+
+    assert NOT(    s1'attr1 = 20   and
+                   s2'attr1 = 20   and
+                   s3'attr1 = 01   and
+                   s4'attr1 = 20   and
+                   s5'attr1 = 20   and
+                   s6'attr1 = 20   and
+                   s7'attr1 = 01   and
+                   c1'attr1 = 101   and
+                   c2'attr1 = 101   and
+                   c3'attr1 = 101   and
+                   c4'attr1 = 101   and
+                   c5'attr1 = 101   and
+                   c6'attr1 = 101   and
+                   c7'attr1 = 101   )
+      report "***PASSED TEST: c05s01b00x00p10n01i03100"
+      severity NOTE;
+    assert (    s1'attr1 = 20   and
+                s2'attr1 = 20   and
+                s3'attr1 = 01   and
+                s4'attr1 = 20   and
+                s5'attr1 = 20   and
+                s6'attr1 = 20   and
+                s7'attr1 = 01   and
+                c1'attr1 = 101   and
+                c2'attr1 = 101   and
+                c3'attr1 = 101   and
+                c4'attr1 = 101   and
+                c5'attr1 = 101   and
+                c6'attr1 = 101   and
+                c7'attr1 = 101   )
+      report "***FAILED TEST: c05s01b00x00p10n01i03100 - Reserved word others in entity name list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p10n01i03100arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3101.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3101.vhd
new file mode 100644
index 0000000..4e1c66b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3101.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3101.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p11n01i03101ent IS
+  ATTRIBUTE attr1 : INTEGER;
+END c05s01b00x00p11n01i03101ent;
+
+ARCHITECTURE c05s01b00x00p11n01i03101arch OF c05s01b00x00p11n01i03101ent IS
+
+  FUNCTION   one  ( par1      : INTEGER ) RETURN INTEGER IS BEGIN END;
+  FUNCTION   two  ( par1      : INTEGER ) RETURN INTEGER IS BEGIN END;
+  FUNCTION   tww  ( par1,par2 : STRING  ) RETURN INTEGER IS BEGIN END;
+
+  ATTRIBUTE attr1 OF all: FUNCTION IS 99;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT  one'attr1 = 99 REPORT "ERROR: Wrong value for  one 'attr1" SEVERITY FAILURE;
+    ASSERT  two'attr1 = 99 REPORT "ERROR: Wrong value for  two 'attr1" SEVERITY FAILURE;
+    ASSERT  tww'attr1 = 99 REPORT "ERROR: Wrong value for  tww 'attr1" SEVERITY FAILURE;
+
+    assert NOT(    one'attr1    = 99   and   
+                   two'attr1    = 99   and
+                   tww'attr1    = 99   )
+      report "***PASSED TEST: c05s01b00x00p11n01i03101"
+      severity NOTE;
+    assert (    one'attr1    = 99   and   
+                two'attr1    = 99   and
+                tww'attr1    = 99   )
+      report "***FAILED TEST: c05s01b00x00p11n01i03101 - Reserved word all as attribute specification test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p11n01i03101arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3102.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3102.vhd
new file mode 100644
index 0000000..0a32a18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3102.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3102.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p11n01i03102ent IS
+  ATTRIBUTE attr1 : INTEGER;
+END c05s01b00x00p11n01i03102ent;
+
+ARCHITECTURE c05s01b00x00p11n01i03102arch OF c05s01b00x00p11n01i03102ent IS
+  SIGNAL s1,s2,s3 : BIT;
+  SIGNAL s4,s5    : INTEGER;
+  SIGNAL s6,s7    : STRING(1 TO 3);
+
+  CONSTANT c1,c2,c3 : BIT            :=   '0';
+  CONSTANT c4,c5    : INTEGER        :=     1;
+  CONSTANT c6,c7    : STRING(1 TO 3) := "ABC";
+
+  ATTRIBUTE attr1 OF ALL : SIGNAL IS 20;
+
+  ATTRIBUTE attr1 OF ALL : CONSTANT IS 101;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT s1'attr1 = 20 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
+    ASSERT s2'attr1 = 20 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
+    ASSERT s3'attr1 = 20 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
+    ASSERT s4'attr1 = 20 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
+    ASSERT s5'attr1 = 20 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
+    ASSERT s6'attr1 = 20 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
+    ASSERT s7'attr1 = 20 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
+    
+    ASSERT c1'attr1 = 101 REPORT "Bad value for c1'attr1" SEVERITY FAILURE;
+    ASSERT c2'attr1 = 101 REPORT "Bad value for c2'attr1" SEVERITY FAILURE;
+    ASSERT c3'attr1 = 101 REPORT "Bad value for c3'attr1" SEVERITY FAILURE;
+    ASSERT c4'attr1 = 101 REPORT "Bad value for c4'attr1" SEVERITY FAILURE;
+    ASSERT c5'attr1 = 101 REPORT "Bad value for c5'attr1" SEVERITY FAILURE;
+    ASSERT c6'attr1 = 101 REPORT "Bad value for c6'attr1" SEVERITY FAILURE;
+    ASSERT c7'attr1 = 101 REPORT "Bad value for c7'attr1" SEVERITY FAILURE;
+
+    assert NOT(    s1'attr1 = 20   and
+                   s2'attr1 = 20   and
+                   s3'attr1 = 20   and
+                   s4'attr1 = 20   and
+                   s5'attr1 = 20   and
+                   s6'attr1 = 20   and
+                   s7'attr1 = 20   and
+                   c1'attr1 = 101   and
+                   c2'attr1 = 101   and
+                   c3'attr1 = 101   and
+                   c4'attr1 = 101   and
+                   c5'attr1 = 101   and
+                   c6'attr1 = 101   and
+                   c7'attr1 = 101   )
+      report "***PASSED TEST: c05s01b00x00p11n01i03102"
+      severity NOTE;
+    assert (    s1'attr1 = 20   and
+                s2'attr1 = 20   and
+                s3'attr1 = 20   and
+                s4'attr1 = 20   and
+                s5'attr1 = 20   and
+                s6'attr1 = 20   and
+                s7'attr1 = 20   and
+                c1'attr1 = 101   and
+                c2'attr1 = 101   and
+                c3'attr1 = 101   and
+                c4'attr1 = 101   and
+                c5'attr1 = 101   and
+                c6'attr1 = 101   and
+                c7'attr1 = 101   )
+      report "***FAILED TEST: c05s01b00x00p11n01i03102 - Reserved work all as attribute specification test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p11n01i03102arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3109.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3109.vhd
new file mode 100644
index 0000000..dfb5700
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3109.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3109.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c05s01b00x00p17n01i03109pkg is
+  attribute p   : POSITIVE;
+  attribute p    of c05s01b00x00p17n01i03109pkg : package is 10; --- No_Failure_here
+end c05s01b00x00p17n01i03109pkg;
+
+
+use work.c05s01b00x00p17n01i03109pkg.all;
+ENTITY c05s01b00x00p17n01i03109ent IS
+  attribute p    of c05s01b00x00p17n01i03109ent : entity is 20;   -- No_Failure_here
+END c05s01b00x00p17n01i03109ent;
+
+ARCHITECTURE c05s01b00x00p17n01i03109arch OF c05s01b00x00p17n01i03109ent IS
+  attribute p    of c05s01b00x00p17n01i03109arch : architecture is 30;  -- No_Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   c05s01b00x00p17n01i03109ent'p   = 20   and
+                  c05s01b00x00p17n01i03109arch'p = 30   )
+      report "***PASSED TEST: c05s01b00x00p17n01i03109" 
+      severity NOTE;
+    assert (   c05s01b00x00p17n01i03109ent'p   = 20   and
+               c05s01b00x00p17n01i03109arch'p = 30   )
+      report "***FAILED TEST: c05s01b00x00p17n01i03109 - Attribute specification for an attribute of a design unit test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p17n01i03109arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc311.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc311.vhd
new file mode 100644
index 0000000..5ce3bbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc311.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc311.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p07n01i00311ent IS
+END c03s01b04x00p07n01i00311ent;
+
+ARCHITECTURE c03s01b04x00p07n01i00311arch OF c03s01b04x00p07n01i00311ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable radius : real := +1.0E38;  -- No_failure_here
+    variable area   : real := -1.0E38;  -- No_failure_here
+  BEGIN
+    area := radius;
+    assert NOT(area = +1.0E38)
+      report "***PASSED TEST: c03s01b04x00p07n01i00311"
+      severity NOTE;
+    assert (area = +1.0E38)
+      report "***FAILED TEST: c03s01b04x00p07n01i00311 - When a real variable is declared, the value of that variable may be any value between -1E38 and +1E38, inclusive."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p07n01i00311arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3110.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3110.vhd
new file mode 100644
index 0000000..ef48977
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3110.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3110.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p34n01i03110ent_a IS
+  PORT    ( Y : IN   BIT ;
+            Z : OUT   INTEGER );
+  ATTRIBUTE    A : INTEGER;
+  ATTRIBUTE    A OF Y : SIGNAL IS 1;
+END c05s01b00x00p34n01i03110ent_a;
+
+ARCHITECTURE c05s01b00x00p34n01i03110arch_a OF c05s01b00x00p34n01i03110ent_a IS
+
+BEGIN
+  PROCESS
+  BEGIN
+    ASSERT Y'A = 1 
+      REPORT "ERROR: Bad value for Y'A" SEVERITY FAILURE;
+    if (Y'A = 1) then
+      Z <= 100;
+    end if;
+    WAIT;
+  END PROCESS;
+END c05s01b00x00p34n01i03110arch_a;
+
+
+
+ENTITY c05s01b00x00p34n01i03110ent IS
+  ATTRIBUTE A : INTEGER;
+END c05s01b00x00p34n01i03110ent;
+
+ARCHITECTURE c05s01b00x00p34n01i03110arch OF c05s01b00x00p34n01i03110ent IS
+  COMPONENT c05s01b00x00p34n01i03110ent_a
+    PORT (    Y : IN   BIT ;
+              Z : OUT   INTEGER );
+  END COMPONENT;
+  for all : c05s01b00x00p34n01i03110ent_a use entity work.c05s01b00x00p34n01i03110ent_a(c05s01b00x00p34n01i03110arch_a); 
+
+  SIGNAL       X : BIT;
+  SIGNAL       XX: INTEGER;
+  ATTRIBUTE    A OF X : SIGNAL IS 2;
+BEGIN
+
+  inst1 : c05s01b00x00p34n01i03110ent_a PORT MAP ( Y => X , Z => XX );
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( X'A = 2 and XX = 100 )
+      report "***PASSED TEST: c05s01b00x00p34n01i03110"
+      severity NOTE;
+    assert ( X'A = 2 and XX = 100 )
+      report "***FAILED TEST: c05s01b00x00p34n01i03110 - User defined attribute represent local information only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p34n01i03110arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3111.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3111.vhd
new file mode 100644
index 0000000..839a0a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3111.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3111.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b00x00p06n01i03111ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b00x00p06n01i03111ent_a;
+
+ARCHITECTURE c05s02b00x00p06n01i03111arch_a OF c05s02b00x00p06n01i03111ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b00x00p06n01i03111arch_a;
+
+
+
+ENTITY c05s02b00x00p06n01i03111ent IS
+END c05s02b00x00p06n01i03111ent;
+
+ARCHITECTURE c05s02b00x00p06n01i03111arch OF c05s02b00x00p06n01i03111ent IS
+  signal       s1   : Bit := '0';
+  signal       s2   : Bit := '1';
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  for u1 : virtual use entity work.c05s02b00x00p06n01i03111ent_a (c05s02b00x00p06n01i03111arch_a);
+BEGIN
+
+  u1 : virtual
+    generic map ( true ) port map (s1, s2);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 50 ns;
+    assert NOT( s2 = s1 )
+      report "***PASSED TEST: c05s02b00x00p06n01i03111"
+      severity NOTE;
+    assert ( s2 = s1 )
+      report "***FAILED TEST: c05s02b00x00p06n01i03111 - Component instantiation test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b00x00p06n01i03111arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3112.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3112.vhd
new file mode 100644
index 0000000..d65f875
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3112.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3112.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b00x00p06n01i03112ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b00x00p06n01i03112ent_a;
+
+ARCHITECTURE c05s02b00x00p06n01i03112arch_a OF c05s02b00x00p06n01i03112ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b00x00p06n01i03112arch_a;
+
+
+
+ENTITY c05s02b00x00p06n01i03112ent IS
+END c05s02b00x00p06n01i03112ent;
+
+ARCHITECTURE c05s02b00x00p06n01i03112arch OF c05s02b00x00p06n01i03112ent IS
+  signal       s1   : Bit := '0';
+  signal       s2   : Bit := '1';
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+BEGIN
+
+  u1 : virtual generic map ( true ) port map (s1, s2);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 50 ns;
+    assert NOT( s2 = s1 )
+      report "***PASSED TEST: c05s02b00x00p06n01i03112"
+      severity NOTE;
+    assert ( s2 = s1 )
+      report "***FAILED TEST: c05s02b00x00p06n01i03112 - Component instance configuration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b00x00p06n01i03112arch;
+
+
+
+configuration c05s02b00x00p06n01i03112cfg of c05s02b00x00p06n01i03112ent is
+  for c05s02b00x00p06n01i03112arch
+    for u1 : virtual use entity work.c05s02b00x00p06n01i03112ent_a (c05s02b00x00p06n01i03112arch_a);
+    end for;
+  end for;
+end c05s02b00x00p06n01i03112cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3113.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3113.vhd
new file mode 100644
index 0000000..0dbe577
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3113.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3113.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b00x00p07n01i03113ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b00x00p07n01i03113ent_a;
+
+ARCHITECTURE c05s02b00x00p07n01i03113arch_a OF c05s02b00x00p07n01i03113ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b00x00p07n01i03113arch_a;
+
+configuration c05s02b00x00p07n01i03113cfg_a of c05s02b00x00p07n01i03113ent_a is
+  for c05s02b00x00p07n01i03113arch_a
+  end for;
+end c05s02b00x00p07n01i03113cfg_a;
+
+
+
+ENTITY c05s02b00x00p07n01i03113ent IS
+END c05s02b00x00p07n01i03113ent;
+
+ARCHITECTURE c05s02b00x00p07n01i03113arch OF c05s02b00x00p07n01i03113ent IS
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+
+  u1 : virtual
+    generic map ( true )
+    port map (s1, s2);
+  u2 : virtual
+    generic map ( true )
+    port map (s2, s3);
+  u3 : virtual
+    generic map ( true )
+    port map (s3, s4);
+  
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b00x00p07n01i03113"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b00x00p07n01i03113 - The use of the others clause did not properly configure an instance which has not been previously configured in a configuration specification in a configuration block."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b00x00p07n01i03113arch;
+
+
+configuration c05s02b00x00p07n01i03113cfg of c05s02b00x00p07n01i03113ent is
+  for c05s02b00x00p07n01i03113arch
+    for u1     : virtual  use entity work.c05s02b00x00p07n01i03113ent_a(c05s02b00x00p07n01i03113arch_a);
+    end for;
+    for others : virtual  use entity work.c05s02b00x00p07n01i03113ent_a(c05s02b00x00p07n01i03113arch_a);
+    end for;
+  end for;
+end c05s02b00x00p07n01i03113cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3114.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3114.vhd
new file mode 100644
index 0000000..0a45d2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3114.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3114.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b00x00p07n01i03114ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b00x00p07n01i03114ent_a;
+
+ARCHITECTURE c05s02b00x00p07n01i03114arch_a OF c05s02b00x00p07n01i03114ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b00x00p07n01i03114arch_a;
+
+configuration c05s02b00x00p07n01i03114cfg_a of c05s02b00x00p07n01i03114ent_a is
+  for c05s02b00x00p07n01i03114arch_a
+  end for;
+end c05s02b00x00p07n01i03114cfg_a;
+
+
+
+ENTITY c05s02b00x00p07n01i03114ent IS
+END c05s02b00x00p07n01i03114ent;
+
+ARCHITECTURE c05s02b00x00p07n01i03114arch OF c05s02b00x00p07n01i03114ent IS
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  
+  for u1     : virtual  use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
+  for others : virtual  use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
+  
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+
+  u1 : virtual
+    generic map ( true )
+    port map (s1, s2);
+  u2 : virtual
+    generic map ( true )
+    port map (s2, s3);
+  u3 : virtual
+    generic map ( true )
+    port map (s3, s4);
+  
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b00x00p07n01i03114"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b00x00p07n01i03114 - The use of the others clause did not properly configure an instance which has not been previously configured in a configuration specification in an architecture declarative region."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b00x00p07n01i03114arch;
+
+
+configuration c05s02b00x00p07n01i03114cfg of c05s02b00x00p07n01i03114ent is
+  for c05s02b00x00p07n01i03114arch
+  end for;
+end c05s02b00x00p07n01i03114cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3115.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3115.vhd
new file mode 100644
index 0000000..ee2b29d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3115.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3115.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p03n01i03115ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p03n01i03115ent_a;
+
+ARCHITECTURE c05s02b01x01p03n01i03115arch_a OF c05s02b01x01p03n01i03115ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p03n01i03115arch_a;
+
+
+ARCHITECTURE c05s02b01x01p03n01i03115arch_b OF c05s02b01x01p03n01i03115ent_a IS
+
+BEGIN
+  p2 <= p1 after 15 ns;
+END c05s02b01x01p03n01i03115arch_b;
+
+
+configuration c05s02b01x01p03n01i03115cfg_a of c05s02b01x01p03n01i03115ent_a is
+  for c05s02b01x01p03n01i03115arch_a
+  end for;
+end c05s02b01x01p03n01i03115cfg_a;
+
+
+configuration c05s02b01x01p03n01i03115cfg_b of c05s02b01x01p03n01i03115ent_a is
+  for c05s02b01x01p03n01i03115arch_b
+  end for;
+end c05s02b01x01p03n01i03115cfg_b;
+
+
+--
+
+
+ENTITY c05s02b01x01p03n01i03115ent IS
+END c05s02b01x01p03n01i03115ent;
+
+ARCHITECTURE c05s02b01x01p03n01i03115arch OF c05s02b01x01p03n01i03115ent IS
+  component ic_socket
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+  u1 : ic_socket
+    generic map ( true )
+    port map (s1, s2);
+  u2 : ic_socket
+    generic map ( true )
+    port map (s2, s3);
+  u3 : ic_socket
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 60 ns;
+    assert NOT(    s2 = s1    and
+                   s3 = s2      and
+                   s4 = s3      )
+      report "***PASSED TEST: c05s02b01x01p03n01i03115"
+      severity NOTE;
+    assert (    s2 = s1    and
+                s3 = s2      and
+                s4 = s3      )
+      report "***FAILED TEST: c05s02b01x01p03n01i03115 - Absense of an explicit architecture test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p03n01i03115arch;
+
+
+configuration c05s02b01x01p03n01i03115cfg of c05s02b01x01p03n01i03115ent is
+  for c05s02b01x01p03n01i03115arch
+    for all : ic_socket use entity work.c05s02b01x01p03n01i03115ent_a; 
+    end for;
+  end for;
+end c05s02b01x01p03n01i03115cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3116.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3116.vhd
new file mode 100644
index 0000000..7099358
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3116.vhd
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3116.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p03n01i03116ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p03n01i03116ent_a;
+
+ARCHITECTURE c05s02b01x01p03n01i03116arch_a OF c05s02b01x01p03n01i03116ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p03n01i03116arch_a;
+
+
+ARCHITECTURE c05s02b01x01p03n01i03116arch_b OF c05s02b01x01p03n01i03116ent_a IS
+
+BEGIN
+  p2 <= p1 after 15 ns;
+END c05s02b01x01p03n01i03116arch_b;
+
+
+configuration c05s02b01x01p03n01i03116cfg_a of c05s02b01x01p03n01i03116ent_a is
+  for c05s02b01x01p03n01i03116arch_a
+  end for;
+end c05s02b01x01p03n01i03116cfg_a;
+
+
+configuration c05s02b01x01p03n01i03116cfg_b of c05s02b01x01p03n01i03116ent_a is
+  for c05s02b01x01p03n01i03116arch_b
+  end for;
+end c05s02b01x01p03n01i03116cfg_b;
+
+
+--
+
+
+ENTITY c05s02b01x01p03n01i03116ent IS
+END c05s02b01x01p03n01i03116ent;
+
+ARCHITECTURE c05s02b01x01p03n01i03116arch OF c05s02b01x01p03n01i03116ent IS
+  component ic_socket
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+  for all : ic_socket use entity work.c05s02b01x01p03n01i03116ent_a; 
+BEGIN
+  u1 : ic_socket
+    generic map ( true )
+    port map (s1, s2);
+  u2 : ic_socket
+    generic map ( true )
+    port map (s2, s3);
+  u3 : ic_socket
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 60 ns;
+    assert NOT(    s2 = s1    and
+                   s3 = s2      and
+                   s4 = s3      )
+      report "***PASSED TEST: c05s02b01x01p03n01i03116"
+      severity NOTE;
+    assert (    s2 = s1    and
+                s3 = s2      and
+                s4 = s3      )
+      report "***FAILED TEST: c05s02b01x01p03n01i03116 - Absense of an explicit architecture test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p03n01i03116arch;
+
+
+configuration c05s02b01x01p03n01i03116cfg of c05s02b01x01p03n01i03116ent is
+  for c05s02b01x01p03n01i03116arch
+  end for;
+end c05s02b01x01p03n01i03116cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3117.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3117.vhd
new file mode 100644
index 0000000..0ace134
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3117.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3117.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p03n01i03117ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p03n01i03117ent_a;
+
+ARCHITECTURE c05s02b01x01p03n01i03117arch_a OF c05s02b01x01p03n01i03117ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p03n01i03117arch_a;
+
+
+ARCHITECTURE c05s02b01x01p03n01i03117arch_b OF c05s02b01x01p03n01i03117ent_a IS
+
+BEGIN
+  p2 <= p1 after 15 ns;
+END c05s02b01x01p03n01i03117arch_b;
+
+
+configuration c05s02b01x01p03n01i03117cfg_a of c05s02b01x01p03n01i03117ent_a is
+  for c05s02b01x01p03n01i03117arch_a
+  end for;
+end c05s02b01x01p03n01i03117cfg_a;
+
+
+configuration c05s02b01x01p03n01i03117cfg_b of c05s02b01x01p03n01i03117ent_a is
+  for c05s02b01x01p03n01i03117arch_b
+  end for;
+end c05s02b01x01p03n01i03117cfg_b;
+
+
+--
+
+
+ENTITY c05s02b01x01p03n01i03117ent IS
+END c05s02b01x01p03n01i03117ent;
+
+ARCHITECTURE c05s02b01x01p03n01i03117arch OF c05s02b01x01p03n01i03117ent IS
+  component ic_socket
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+  u1 : ic_socket
+    generic map ( true )
+    port map (s1, s2);
+  u2 : ic_socket
+    generic map ( true )
+    port map (s2, s3);
+  u3 : ic_socket
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1    and
+                   s3 = s2      and
+                   s4 = s3      )
+      report "***PASSED TEST: c05s02b01x01p03n01i03117"
+      severity NOTE;
+    assert (    s2 = s1    and
+                s3 = s2      and
+                s4 = s3      )
+      report "***FAILED TEST: c05s02b01x01p03n01i03117 - Entity declaration denoted by the entity name together with an architecture body binding in configuration blocks test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p03n01i03117arch;
+
+
+configuration c05s02b01x01p03n01i03117cfg of c05s02b01x01p03n01i03117ent is
+  for c05s02b01x01p03n01i03117arch
+    for all : ic_socket use entity work.c05s02b01x01p03n01i03117ent_a (c05s02b01x01p03n01i03117arch_a); 
+    end for;
+  end for;
+end c05s02b01x01p03n01i03117cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3118.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3118.vhd
new file mode 100644
index 0000000..d34e814
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3118.vhd
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3118.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p03n01i03118ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p03n01i03118ent_a;
+
+ARCHITECTURE c05s02b01x01p03n01i03118arch_a OF c05s02b01x01p03n01i03118ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p03n01i03118arch_a;
+
+
+ARCHITECTURE c05s02b01x01p03n01i03118arch_b OF c05s02b01x01p03n01i03118ent_a IS
+
+BEGIN
+  p2 <= p1 after 15 ns;
+END c05s02b01x01p03n01i03118arch_b;
+
+
+configuration c05s02b01x01p03n01i03118cfg_a of c05s02b01x01p03n01i03118ent_a is
+  for c05s02b01x01p03n01i03118arch_a
+  end for;
+end c05s02b01x01p03n01i03118cfg_a;
+
+
+configuration c05s02b01x01p03n01i03118cfg_b of c05s02b01x01p03n01i03118ent_a is
+  for c05s02b01x01p03n01i03118arch_b
+  end for;
+end c05s02b01x01p03n01i03118cfg_b;
+
+
+--
+
+
+ENTITY c05s02b01x01p03n01i03118ent IS
+END c05s02b01x01p03n01i03118ent;
+
+ARCHITECTURE c05s02b01x01p03n01i03118arch OF c05s02b01x01p03n01i03118ent IS
+  component ic_socket
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+  for all : ic_socket use entity work.c05s02b01x01p03n01i03118ent_a (c05s02b01x01p03n01i03118arch_a); 
+BEGIN
+  u1 : ic_socket
+    generic map ( true )
+    port map (s1, s2);
+  u2 : ic_socket
+    generic map ( true )
+    port map (s2, s3);
+  u3 : ic_socket
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1    and
+                   s3 = s2      and
+                   s4 = s3      )
+      report "***PASSED TEST: c05s02b01x01p03n01i03118"
+      severity NOTE;
+    assert (    s2 = s1    and
+                s3 = s2      and
+                s4 = s3      )
+      report "***FAILED TEST: c05s02b01x01p03n01i03118 - Entity declaration denoted by the entity name together with an architecture body binding in architecture declaration." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p03n01i03118arch;
+
+
+configuration c05s02b01x01p03n01i03118cfg of c05s02b01x01p03n01i03118ent is
+  for c05s02b01x01p03n01i03118arch
+  end for;
+end c05s02b01x01p03n01i03118cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3119.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3119.vhd
new file mode 100644
index 0000000..151794e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3119.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3119.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p05n01i03119ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p05n01i03119ent_a;
+
+ARCHITECTURE c05s02b01x01p05n01i03119arch_a OF c05s02b01x01p05n01i03119ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p05n01i03119arch_a;
+
+configuration c05s02b01x01p05n01i03119cfg_a of c05s02b01x01p05n01i03119ent_a is
+  for c05s02b01x01p05n01i03119arch_a
+  end for;
+end c05s02b01x01p05n01i03119cfg_a;
+
+
+--
+
+ENTITY c05s02b01x01p05n01i03119ent IS
+END c05s02b01x01p05n01i03119ent;
+
+ARCHITECTURE c05s02b01x01p05n01i03119arch OF c05s02b01x01p05n01i03119ent IS
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+  u1 : virtual
+    generic map ( true )
+    port map (s1, s2);
+  u2 : virtual
+    generic map ( true )
+    port map (s2, s3);
+  u3 : virtual
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b01x01p05n01i03119"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b01x01p05n01i03119 - Use a configuration that is fully bound test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p05n01i03119arch;
+
+
+configuration c05s02b01x01p05n01i03119cfg of c05s02b01x01p05n01i03119ent is
+  for c05s02b01x01p05n01i03119arch
+    for all : virtual use configuration work.c05s02b01x01p05n01i03119cfg_a;
+    end for;
+  end for;
+end c05s02b01x01p05n01i03119cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc312.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc312.vhd
new file mode 100644
index 0000000..7acaec8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc312.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc312.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p07n03i00312ent IS
+END c03s01b04x00p07n03i00312ent;
+
+ARCHITECTURE c03s01b04x00p07n03i00312arch OF c03s01b04x00p07n03i00312ent IS
+  type R1 is range -10.0 to 10.0;
+  type R2 is range REAL'LOW to REAL'HIGH;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : real := 0.000001;
+    variable V2 : real := 0.000002;
+    variable V3 : real ;
+  BEGIN
+    V3 := V2 - V1;
+    assert NOT(V3 = 0.000001)
+      report "***PASSED TEST: c03s01b04x00p07n03i00312"
+      severity NOTE;
+    assert ( V3 = 0.000001 )
+      report "***FAILED TEST: c03s01b04x00p07n03i00312 -  A minimum of six digits of precision is included in the representation of floating point types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p07n03i00312arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3120.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3120.vhd
new file mode 100644
index 0000000..2b10267
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3120.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3120.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p05n01i03120ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p05n01i03120ent_a;
+
+ARCHITECTURE c05s02b01x01p05n01i03120arch_a OF c05s02b01x01p05n01i03120ent_a IS
+
+BEGIN
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p05n01i03120arch_a;
+
+configuration c05s02b01x01p05n01i03120cfg_a of c05s02b01x01p05n01i03120ent_a is
+  for c05s02b01x01p05n01i03120arch_a
+  end for;
+end c05s02b01x01p05n01i03120cfg_a;
+
+
+--
+
+
+ENTITY c05s02b01x01p05n01i03120ent IS
+END c05s02b01x01p05n01i03120ent;
+
+ARCHITECTURE c05s02b01x01p05n01i03120arch OF c05s02b01x01p05n01i03120ent IS
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+  for all : virtual use configuration work.c05s02b01x01p05n01i03120cfg_a;
+BEGIN
+  u1 : virtual
+    generic map ( true )
+    port map (s1, s2);
+  u2 : virtual
+    generic map ( true )
+    port map (s2, s3);
+  u3 : virtual
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b01x01p05n01i03120"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b01x01p05n01i03120 - Use a configuration that is fully bound test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p05n01i03120arch;
+
+
+configuration c05s02b01x01p05n01i03120cfg of c05s02b01x01p05n01i03120ent is
+  for c05s02b01x01p05n01i03120arch
+  end for;
+end c05s02b01x01p05n01i03120cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3121.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3121.vhd
new file mode 100644
index 0000000..bfcb2ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3121.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3121.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p05n01i03121ent_aa IS
+END c05s02b01x01p05n01i03121ent_aa;
+
+ARCHITECTURE c05s02b01x01p05n01i03121arch_aa OF c05s02b01x01p05n01i03121ent_aa IS
+
+BEGIN
+END c05s02b01x01p05n01i03121arch_aa;
+
+
+ARCHITECTURE c05s02b01x01p05n01i03121arch_bb OF c05s02b01x01p05n01i03121ent_aa IS
+
+BEGIN
+END c05s02b01x01p05n01i03121arch_bb;
+
+--
+
+ENTITY c05s02b01x01p05n01i03121ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p05n01i03121ent_a;
+
+ARCHITECTURE c05s02b01x01p05n01i03121arch_a OF c05s02b01x01p05n01i03121ent_a IS
+  component zippy
+  end component;
+BEGIN
+  u1 : zippy;
+  p2 <= p1 after 10 ns;
+END c05s02b01x01p05n01i03121arch_a;
+
+configuration c05s02b01x01p05n01i03121cfg_a of c05s02b01x01p05n01i03121ent_a is
+  for c05s02b01x01p05n01i03121arch_a
+    for u1 : zippy use entity work.c05s02b01x01p05n01i03121ent_aa;
+    end for;
+  end for;
+end c05s02b01x01p05n01i03121cfg_a;
+
+--
+
+ENTITY c05s02b01x01p05n01i03121ent IS
+END c05s02b01x01p05n01i03121ent;
+
+ARCHITECTURE c05s02b01x01p05n01i03121arch OF c05s02b01x01p05n01i03121ent IS
+  component virtual
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+  u1 : virtual
+    generic map ( true )
+    port map (s1, s2);
+  u2 : virtual
+    generic map ( true )
+    port map (s2, s3);
+  u3 : virtual
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b01x01p05n01i03121"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b01x01p05n01i03121 - Use a configuration that is not fully bound test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p05n01i03121arch;
+
+
+
+configuration c05s02b01x01p05n01i03121cfg of c05s02b01x01p05n01i03121ent is
+  for c05s02b01x01p05n01i03121arch
+    for all : virtual use configuration work.c05s02b01x01p05n01i03121cfg_a;
+    end for;
+  end for;
+end c05s02b01x01p05n01i03121cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3122.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3122.vhd
new file mode 100644
index 0000000..170bcf7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3122.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3122.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x01p07n01i03122ent_a IS
+  generic ( g1 : boolean );
+  port    ( p1 : in  Bit;
+            p2 : out Bit );
+END c05s02b01x01p07n01i03122ent_a;
+
+ARCHITECTURE c05s02b01x01p07n01i03122arch_a OF c05s02b01x01p07n01i03122ent_a IS
+
+BEGIN
+  p2 <= p1 after 10  ns;
+END c05s02b01x01p07n01i03122arch_a;
+
+configuration c05s02b01x01p07n01i03122cfg_a of c05s02b01x01p07n01i03122ent_a is
+  for c05s02b01x01p07n01i03122arch_a
+  end for;
+end c05s02b01x01p07n01i03122cfg_a;
+
+
+--
+
+
+ENTITY c05s02b01x01p07n01i03122ent IS
+END c05s02b01x01p07n01i03122ent;
+
+ARCHITECTURE c05s02b01x01p07n01i03122arch OF c05s02b01x01p07n01i03122ent IS
+  component ic_socket
+    generic ( g1 : boolean );
+    port    ( p1 : in  Bit;
+              p2 : out Bit );
+  end component;
+  signal s1,s2,s3,s4 : Bit;
+BEGIN
+
+  u1 : ic_socket
+    generic map ( true )
+    port map (s1, s2);
+  u2 : ic_socket
+    generic map ( true )
+    port map (s2, s3);
+  u3 : ic_socket
+    generic map ( true )
+    port map (s3, s4);
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    s2 = s1   and
+                   s3 = s2   and
+                   s4 = s3   )
+      report "***PASSED TEST: c05s02b01x01p07n01i03122"
+      severity NOTE;
+    assert (    s2 = s1   and
+                s3 = s2   and
+                s4 = s3   )
+      report "***FAILED TEST: c05s02b01x01p07n01i03122 - Explicitly OPEN entity aspects in configuration blocks test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x01p07n01i03122arch;
+
+configuration c05s02b01x01p07n01i03122cfg of c05s02b01x01p07n01i03122ent is
+  for c05s02b01x01p07n01i03122arch
+    for all : ic_socket use OPEN;
+    end for;
+  end for;
+end c05s02b01x01p07n01i03122cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3123.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3123.vhd
new file mode 100644
index 0000000..e92e68f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3123.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3123.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p01n01i03123ent_a IS
+  generic ( socket_g1 : Boolean;
+            socket_g2 : Bit;
+            socket_g3 : character;
+            socket_g4 : severity_level;
+            socket_g5 : integer;
+            socket_g6 : real;
+            socket_g7 : time;
+            socket_g8 : natural;
+            socket_g9 : positive
+            );
+  port    ( socket_p1 : inout Boolean;
+            socket_p2 : inout Bit;
+            socket_p3 : inout character;
+            socket_p4 : inout severity_level;
+            socket_p5 : inout integer;
+            socket_p6 : inout real;
+            socket_p7 : inout time;
+            socket_p8 : inout natural;
+            socket_p9 : inout positive
+            );
+END c05s02b01x02p01n01i03123ent_a;
+
+ARCHITECTURE c05s02b01x02p01n01i03123arch_a OF c05s02b01x02p01n01i03123ent_a IS
+
+BEGIN
+  socket_p1 <= socket_g1 after 22 ns;
+  socket_p2 <= socket_g2 after 22 ns;
+  socket_p3 <= socket_g3 after 22 ns;
+  socket_p4 <= socket_g4 after 22 ns;
+  socket_p5 <= socket_g5 after 22 ns;
+  socket_p6 <= socket_g6 after 22 ns;
+  socket_p7 <= socket_g7 after 22 ns;
+  socket_p8 <= socket_g8 after 22 ns;
+  socket_p9 <= socket_g9 after 22 ns;
+END c05s02b01x02p01n01i03123arch_a;
+
+
+
+ENTITY c05s02b01x02p01n01i03123ent IS
+END c05s02b01x02p01n01i03123ent;
+
+ARCHITECTURE c05s02b01x02p01n01i03123arch OF c05s02b01x02p01n01i03123ent IS
+  component ic_socket
+    generic ( socket_g1 : Boolean;
+              socket_g2 : Bit;
+              socket_g3 : character;
+              socket_g4 : severity_level;
+              socket_g5 : integer;
+              socket_g6 : real;
+              socket_g7 : time;
+              socket_g8 : natural;
+              socket_g9 : positive
+              );
+    port    ( socket_p1 : inout Boolean;
+              socket_p2 : inout Bit;
+              socket_p3 : inout character;
+              socket_p4 : inout severity_level;
+              socket_p5 : inout integer;
+              socket_p6 : inout real;
+              socket_p7 : inout time;
+              socket_p8 : inout natural;
+              socket_p9 : inout positive
+              );
+  end component;
+  signal socket_p1 :  Boolean;
+  signal socket_p2 :  Bit;
+  signal socket_p3 :  character;
+  signal socket_p4 :  severity_level;
+  signal socket_p5 :  integer;
+  signal socket_p6 :  real;
+  signal socket_p7 :  time;
+  signal socket_p8 :  natural;
+  signal socket_p9 :  positive;
+BEGIN
+  instance : ic_socket
+    generic map ( true,
+                  '1',
+                  '$',
+                  warning,
+                  -100002,
+                  -9.999,
+                  20 ns,
+                  23423,
+                  4564576
+                  )
+    port map    ( socket_p1,
+                  socket_p2,
+                  socket_p3,
+                  socket_p4,
+                  socket_p5,
+                  socket_p6,
+                  socket_p7,
+                  socket_p8,
+                  socket_p9
+                  );
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    socket_p1 = true   and
+                   socket_p2 = '1'      and
+                   socket_p3 = '$'      and
+                   socket_p4 = warning   and
+                   socket_p5 = -100002   and
+                   socket_p6 = -9.999   and
+                   socket_p7 = 20 ns   and
+                   socket_p8 = 23423   and
+                   socket_p9 = 4564576   )
+      report "***PASSED TEST: c05s02b01x02p01n01i03123"
+      severity NOTE;
+    assert (    socket_p1 = true   and
+                socket_p2 = '1'      and
+                socket_p3 = '$'      and
+                socket_p4 = warning   and
+                socket_p5 = -100002   and
+                socket_p6 = -9.999   and
+                socket_p7 = 20 ns   and
+                socket_p8 = 23423   and
+                socket_p9 = 4564576   )
+      report "***FAILED TEST: c05s02b01x02p01n01i03123 - Positional association generic and port list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x02p01n01i03123arch;
+
+
+
+
+configuration c05s02b01x02p01n01i03123cfg of c05s02b01x02p01n01i03123ent is
+  for c05s02b01x02p01n01i03123arch
+    for instance : ic_socket use entity work.c05s02b01x02p01n01i03123ent_a (c05s02b01x02p01n01i03123arch_a)
+                               generic map (    socket_g1,
+                                                socket_g2,
+                                                socket_g3,
+                                                socket_g4,
+                                                socket_g5,
+                                                socket_g6,
+                                                socket_g7,
+                                                socket_g8,
+                                                socket_g9
+                                                )
+                               port map    ( socket_p1,
+                                             socket_p2,
+                                             socket_p3,
+                                             socket_p4,
+                                             socket_p5,
+                                             socket_p6,
+                                             socket_p7,
+                                             socket_p8,
+                                             socket_p9
+                                             );
+    end for;
+  end for;
+end c05s02b01x02p01n01i03123cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3125.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3125.vhd
new file mode 100644
index 0000000..7d4df7f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3125.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3125.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p08n01i03125ent_a IS
+  generic ( message : string );
+END c05s02b01x02p08n01i03125ent_a;
+
+ARCHITECTURE c05s02b01x02p08n01i03125arch_a OF c05s02b01x02p08n01i03125ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( message = "Hello there..." )
+      report "***PASSED TEST: c05s02b01x02p08n01i03125"
+      severity NOTE;
+    assert ( message = "Hello there..." )
+      report "***FAILED TEST: c05s02b01x02p08n01i03125 - Generic maps work does not work properly with unconstrained generic elements."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p08n01i03125arch_a;
+
+
+
+ENTITY c05s02b01x02p08n01i03125ent IS
+END c05s02b01x02p08n01i03125ent;
+
+ARCHITECTURE c05s02b01x02p08n01i03125arch OF c05s02b01x02p08n01i03125ent IS
+  component ic_socket
+    generic ( message : string );
+  end component;
+BEGIN
+  u1 : ic_socket generic map ("Hello there...");
+
+END c05s02b01x02p08n01i03125arch;
+
+
+configuration c05s02b01x02p08n01i03125cfg of c05s02b01x02p08n01i03125ent is
+  for c05s02b01x02p08n01i03125arch
+    for u1 : ic_socket use entity work.c05s02b01x02p08n01i03125ent_a(c05s02b01x02p08n01i03125arch_a);
+    end for;
+  end for;
+end c05s02b01x02p08n01i03125cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3126.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3126.vhd
new file mode 100644
index 0000000..310d018
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3126.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3126.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03126ent_a IS
+  generic ( g1 : integer := 3 );
+END c05s02b01x02p12n01i03126ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03126arch_a OF c05s02b01x02p12n01i03126ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 /= 2    report "g1 = 2"    severity FAILURE;
+    assert g1 /= 3    report "g1 = 3"    severity FAILURE;
+    assert g1 = 4     report "g1 /= 4"    severity FAILURE; 
+    assert g1 /= 5    report "g1 = 5"    severity FAILURE;
+    assert g1 /= 6    report "g1 = 6"    severity FAILURE;
+    assert NOT(    g1 /= 2   and
+                   g1 /= 3   and
+                   g1 = 4   and
+                   g1 /= 5   and
+                   g1 /= 6   )
+      report "***PASSED TEST: c05s02b01x02p12n01i03126"
+      severity NOTE;
+    assert (    g1 /= 2   and
+                g1 /= 3   and
+                g1 = 4   and
+                g1 /= 5   and
+                g1 /= 6   )
+      report "***FAILED TEST: c05s02b01x02p12n01i03126 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03126arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03126ent IS
+END c05s02b01x02p12n01i03126ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03126arch OF c05s02b01x02p12n01i03126ent IS
+  component ic_socket
+    generic ( g1 : integer := 2 );
+  end component;
+  for instance : ic_socket use entity work.c05s02b01x02p12n01i03126ent_a (c05s02b01x02p12n01i03126arch_a)
+    generic map ( g1 => g1 + g1 );
+BEGIN
+
+  instance : ic_socket ;
+
+END c05s02b01x02p12n01i03126arch;
+
+
+configuration c05s02b01x02p12n01i03126cfg of c05s02b01x02p12n01i03126ent is
+  for c05s02b01x02p12n01i03126arch
+  end for;
+end c05s02b01x02p12n01i03126cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3127.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3127.vhd
new file mode 100644
index 0000000..ddf9399
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3127.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3127.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03127ent_a IS
+  generic ( g1 : integer := 3 );
+END c05s02b01x02p12n01i03127ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03127arch_a OF c05s02b01x02p12n01i03127ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 /= 2    report "g1 = 2"    severity FAILURE;
+    assert g1 /= 3    report "g1 = 3"    severity FAILURE;
+    assert g1 = 4     report "g1 /= 4"    severity FAILURE; 
+    assert g1 /= 5    report "g1 = 5"    severity FAILURE;
+    assert g1 /= 6    report "g1 = 6"    severity FAILURE;
+    assert NOT(    g1 /= 2   and
+                   g1 /= 3   and
+                   g1 = 4   and
+                   g1 /= 5   and
+                   g1 /= 6   )
+      report "***PASSED TEST: c05s02b01x02p12n01i03127"
+      severity NOTE;
+    assert (    g1 /= 2   and
+                g1 /= 3   and
+                g1 = 4   and
+                g1 /= 5   and
+                g1 /= 6   )
+      report "***FAILED TEST: c05s02b01x02p12n01i03127 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03127arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03127ent IS
+END c05s02b01x02p12n01i03127ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03127arch OF c05s02b01x02p12n01i03127ent IS
+  component ic_socket
+    generic ( g1 : integer := 2 );
+  end component;
+BEGIN
+
+  instance : ic_socket ;
+
+END c05s02b01x02p12n01i03127arch;
+
+
+configuration c05s02b01x02p12n01i03127_cfg of c05s02b01x02p12n01i03127ent is
+  for c05s02b01x02p12n01i03127arch
+    -- takes local generic and associates it to the formal.
+    for instance : ic_socket use entity work.c05s02b01x02p12n01i03127ent_a(c05s02b01x02p12n01i03127arch_a)
+                               generic map (g1 => g1 + g1 );
+    end for;
+  end for;
+end c05s02b01x02p12n01i03127_cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3128.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3128.vhd
new file mode 100644
index 0000000..e042f45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3128.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3128.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03128ent_a IS
+  generic ( g1 : integer := 3 );
+END c05s02b01x02p12n01i03128ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03128arch_a OF c05s02b01x02p12n01i03128ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 /= 2    report "g1 = 2"    severity FAILURE;
+    assert g1 /= 3    report "g1 = 3"    severity FAILURE;
+    assert g1 = 4     report "g1 /= 4"    severity FAILURE; 
+    assert g1 /= 5    report "g1 = 5"    severity FAILURE;
+    assert g1 /= 6    report "g1 = 6"    severity FAILURE;
+    assert NOT(    g1 /= 2   and
+                   g1 /= 3   and
+                   g1 = 4   and
+                   g1 /= 5   and
+                   g1 /= 6   )
+      report "***PASSED TEST: c05s02b01x02p12n01i03128"
+      severity NOTE;
+    assert (    g1 /= 2   and
+                g1 /= 3   and
+                g1 = 4   and
+                g1 /= 5   and
+                g1 /= 6   )
+      report "***FAILED TEST: c05s02b01x02p12n01i03128 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03128arch_a;
+
+
+
+ENTITY c05s02b01x02p12n01i03128ent IS
+END c05s02b01x02p12n01i03128ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03128arch OF c05s02b01x02p12n01i03128ent IS
+
+BEGIN
+  labeled : block
+    component ic_socket
+      generic ( g1 : integer := 2 );
+    end component;
+    for instance : ic_socket use entity work.c05s02b01x02p12n01i03128ent_a (c05s02b01x02p12n01i03128arch_a)
+      generic map ( g1 => g1 + g1 );
+  begin
+    instance : ic_socket ;
+  end block;
+
+END c05s02b01x02p12n01i03128arch;
+
+
+configuration c05s02b01x02p12n01i03128cfg of c05s02b01x02p12n01i03128ent is
+  for c05s02b01x02p12n01i03128arch
+  end for;
+end c05s02b01x02p12n01i03128cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc313.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc313.vhd
new file mode 100644
index 0000000..38d0c6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc313.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc313.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x01p01n02i00313ent IS
+END c03s01b04x01p01n02i00313ent;
+
+ARCHITECTURE c03s01b04x01p01n02i00313arch OF c03s01b04x01p01n02i00313ent IS
+  constant C1 : REAL := -1.0E38 ;
+  constant C2 : REAL := +1.0E38 ;
+BEGIN
+  TESTING: PROCESS
+    variable k1 : real;
+    variable k2 : real;
+  BEGIN
+    k1 := C1;
+    k2 := C2;
+    assert NOT(k1=C1 and k2=C2)
+      report "***PASSED TEST: c03s01b04x01p01n02i00313"
+      severity NOTE;
+    assert (k1=C1 and k2=C2)
+      report "***FAILED TEST: c03s01b04x01p01n02i00313 - The range of REAL is host-independent, but it is guaranteed to include the range -1E38 to +1E38."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x01p01n02i00313arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3137.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3137.vhd
new file mode 100644
index 0000000..ee996fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3137.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3137.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p02n01i03137ent IS
+END c05s02b02x00p02n01i03137ent;
+
+ARCHITECTURE c05s02b02x00p02n01i03137arch OF c05s02b02x00p02n01i03137ent IS
+  component c05s02b02x00p02n01i03137ent_a
+  end component;
+BEGIN
+
+  comp1 : c05s02b02x00p02n01i03137ent_a;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p02n01i03137"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p02n01i03137arch;
+
+
+configuration c05s02b02x00p02n01i03137cfg of c05s02b02x00p02n01i03137ent is
+  for c05s02b02x00p02n01i03137arch
+    for comp1 : c05s02b02x00p02n01i03137ent_a use OPEN;
+    end for;
+  end for;
+end c05s02b02x00p02n01i03137cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3138.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3138.vhd
new file mode 100644
index 0000000..3eabe09
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3138.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3138.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p02n01i03138ent IS
+END c05s02b02x00p02n01i03138ent;
+
+ARCHITECTURE c05s02b02x00p02n01i03138arch OF c05s02b02x00p02n01i03138ent IS
+  component c05s02b02x00p02n01i03138ent_a
+  end component;
+  for comp1 : c05s02b02x00p02n01i03138ent_a use OPEN;
+BEGIN
+
+  comp1 : c05s02b02x00p02n01i03138ent_a;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p02n01i03138"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p02n01i03138arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3139.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3139.vhd
new file mode 100644
index 0000000..24c7c8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3139.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3139.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p02n01i03139ent IS
+END c05s02b02x00p02n01i03139ent;
+
+ARCHITECTURE c05s02b02x00p02n01i03139arch OF c05s02b02x00p02n01i03139ent IS
+
+begin
+  l : block
+    component c05s02b02x00p02n01i03139ent_a
+    end component;
+    for comp1 : c05s02b02x00p02n01i03139ent_a use OPEN;
+  BEGIN
+
+    comp1 : c05s02b02x00p02n01i03139ent_a;
+
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE
+        report "***PASSED TEST: c05s02b02x00p02n01i03139"
+        severity NOTE;
+      wait;
+    END PROCESS TESTING;
+  end block;
+
+END c05s02b02x00p02n01i03139arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc314.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc314.vhd
new file mode 100644
index 0000000..be9f05d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc314.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc314.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x01p01n03i00314ent IS
+END c03s01b04x01p01n03i00314ent;
+
+ARCHITECTURE c03s01b04x01p01n03i00314arch OF c03s01b04x01p01n03i00314ent IS
+  subtype T1 is REAL range 1.0 to 10.0 ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(T1'LEFT < T1'RIGHT)
+      report "***PASSED TEST: c03s01b04x01p01n03i00314"
+      severity NOTE;
+    assert (T1'LEFT < T1'RIGHT)
+      report "***FAILED TEST: c03s01b04x01p01n03i00314 - The range of REAL is defined with an ascending range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x01p01n03i00314arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3140.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3140.vhd
new file mode 100644
index 0000000..916440b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3140.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3140.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03140ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03140ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03140arch_a OF c05s02b02x00p10n01i03140ent_a IS
+
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03140"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03140 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03140arch_a;
+
+
+--
+
+
+ENTITY c05s02b02x00p10n01i03140ent IS
+END c05s02b02x00p10n01i03140ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03140arch OF c05s02b02x00p10n01i03140ent IS
+  component c05s02b02x00p10n01i03140ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p10n01i03140ent_a;
+
+END c05s02b02x00p10n01i03140arch;
+
+
+configuration c05s02b02x00p10n01i03140cfg of c05s02b02x00p10n01i03140ent is
+  for c05s02b02x00p10n01i03140arch
+    for comp1 : c05s02b02x00p10n01i03140ent_a use entity work.c05s02b02x00p10n01i03140ent_a(c05s02b02x00p10n01i03140arch_a);
+    end for;
+  end for;
+end c05s02b02x00p10n01i03140cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3141.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3141.vhd
new file mode 100644
index 0000000..aa5f218
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3141.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3141.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03141ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03141ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03141arch_a OF c05s02b02x00p10n01i03141ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03141"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03141 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03141arch_a;
+
+
+--
+
+
+ENTITY c05s02b02x00p10n01i03141ent IS
+END c05s02b02x00p10n01i03141ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03141arch OF c05s02b02x00p10n01i03141ent IS
+  component c05s02b02x00p10n01i03141ent_a
+  end component;
+  for comp1 : c05s02b02x00p10n01i03141ent_a use entity work.c05s02b02x00p10n01i03141ent_a(c05s02b02x00p10n01i03141arch_a);
+BEGIN
+  comp1 : c05s02b02x00p10n01i03141ent_a;
+
+END c05s02b02x00p10n01i03141arch;
+
+
+configuration c05s02b02x00p10n01i03141_cfg of c05s02b02x00p10n01i03141ent is
+  for c05s02b02x00p10n01i03141arch
+  end for;
+end c05s02b02x00p10n01i03141_cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3142.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3142.vhd
new file mode 100644
index 0000000..310d4da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3142.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3142.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03142ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03142ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03142arch_a OF c05s02b02x00p10n01i03142ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03142"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03142 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03142arch_a;
+
+
+--
+
+
+ENTITY c05s02b02x00p10n01i03142ent IS
+END c05s02b02x00p10n01i03142ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03142arch OF c05s02b02x00p10n01i03142ent IS
+
+begin
+  l : block
+    component c05s02b02x00p10n01i03142ent_a
+    end component;
+    for comp1 : c05s02b02x00p10n01i03142ent_a use entity work.c05s02b02x00p10n01i03142ent_a(c05s02b02x00p10n01i03142arch_a);
+  BEGIN
+    comp1 : c05s02b02x00p10n01i03142ent_a;
+  end block;
+
+END c05s02b02x00p10n01i03142arch;
+
+
+configuration c05s02b02x00p10n01i03142cfg of c05s02b02x00p10n01i03142ent is
+  for c05s02b02x00p10n01i03142arch
+  end for;
+end c05s02b02x00p10n01i03142cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3143.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3143.vhd
new file mode 100644
index 0000000..674f1bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3143.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3143.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03143ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03143ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03143arch_a OF c05s02b02x00p10n01i03143ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03143"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03143 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03143arch_a;
+
+
+--
+
+
+ENTITY c05s02b02x00p10n01i03143ent IS
+END c05s02b02x00p10n01i03143ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03143arch OF c05s02b02x00p10n01i03143ent IS
+  component c05s02b02x00p10n01i03143ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p10n01i03143ent_a;
+END c05s02b02x00p10n01i03143arch;
+
+
+configuration c05s02b02x00p10n01i03143cfg of c05s02b02x00p10n01i03143ent is
+  for c05s02b02x00p10n01i03143arch
+    for comp1 : c05s02b02x00p10n01i03143ent_a use entity work.c05s02b02x00p10n01i03143ent_a(c05s02b02x00p10n01i03143arch_a)
+                                                generic map(OPEN);
+    end for;
+  end for;
+end c05s02b02x00p10n01i03143cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3144.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3144.vhd
new file mode 100644
index 0000000..fc6ac39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3144.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3144.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03144ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03144ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03144arch_a OF c05s02b02x00p10n01i03144ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03144"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03144 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03144arch_a;
+
+--
+
+ENTITY c05s02b02x00p10n01i03144ent IS
+END c05s02b02x00p10n01i03144ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03144arch OF c05s02b02x00p10n01i03144ent IS
+  component c05s02b02x00p10n01i03144ent_a
+  end component;
+  for comp1 : c05s02b02x00p10n01i03144ent_a use entity work.c05s02b02x00p10n01i03144ent_a(c05s02b02x00p10n01i03144arch_a)
+    generic map(OPEN);
+BEGIN
+  comp1 : c05s02b02x00p10n01i03144ent_a;
+END c05s02b02x00p10n01i03144arch;
+
+
+configuration c05s02b02x00p10n01i03144cfg of c05s02b02x00p10n01i03144ent is
+  for c05s02b02x00p10n01i03144arch
+  end for;
+end c05s02b02x00p10n01i03144cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3145.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3145.vhd
new file mode 100644
index 0000000..f4ce821
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3145.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3145.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p10n01i03145ent_a IS
+  generic ( g1 : real := 22.0 );
+END c05s02b02x00p10n01i03145ent_a;
+
+ARCHITECTURE c05s02b02x00p10n01i03145arch_a OF c05s02b02x00p10n01i03145ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( g1 = 22.0 )
+      report "***PASSED TEST: c05s02b02x00p10n01i03145"
+      severity NOTE;
+    assert ( g1 = 22.0 )
+      report "***FAILED TEST: c05s02b02x00p10n01i03145 - The formal generics take on implicit OPENs."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  
+END c05s02b02x00p10n01i03145arch_a;
+
+--
+
+ENTITY c05s02b02x00p10n01i03145ent IS
+END c05s02b02x00p10n01i03145ent;
+
+ARCHITECTURE c05s02b02x00p10n01i03145arch OF c05s02b02x00p10n01i03145ent IS
+begin
+  l : block
+    component c05s02b02x00p10n01i03145ent_a
+    end component;
+    for comp1 : c05s02b02x00p10n01i03145ent_a use entity work.c05s02b02x00p10n01i03145ent_a(c05s02b02x00p10n01i03145arch_a)
+      generic map(OPEN);
+  BEGIN
+    comp1 : c05s02b02x00p10n01i03145ent_a;
+  end block;
+END c05s02b02x00p10n01i03145arch;
+
+
+configuration c05s02b02x00p10n01i03145cfg of c05s02b02x00p10n01i03145ent is
+  for c05s02b02x00p10n01i03145arch
+  end for;
+end c05s02b02x00p10n01i03145cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3146.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3146.vhd
new file mode 100644
index 0000000..cb81136
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3146.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3146.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03146ent_a IS
+END c05s02b02x00p08n01i03146ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03146arch_a OF c05s02b02x00p08n01i03146ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03146 - Architecture did not implicitly choose the most recently analyzed one for the entity."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03146arch_a;
+
+
+--most recently analyzed ...
+ARCHITECTURE c05s02b02x00p08n01i03146arch_b OF c05s02b02x00p08n01i03146ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03146"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03146arch_b;
+
+
+--
+
+ENTITY c05s02b02x00p08n01i03146ent IS
+END c05s02b02x00p08n01i03146ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03146arch OF c05s02b02x00p08n01i03146ent IS
+  component c05s02b02x00p08n01i03146ent_c
+  end component;
+  for comp1 : c05s02b02x00p08n01i03146ent_c use entity work.c05s02b02x00p08n01i03146ent_a;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03146ent_c;
+END c05s02b02x00p08n01i03146arch;
+
+
+
+
+configuration c05s02b02x00p08n01i03146cfg of c05s02b02x00p08n01i03146ent is
+  for c05s02b02x00p08n01i03146arch
+  end for;
+end c05s02b02x00p08n01i03146cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3147.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3147.vhd
new file mode 100644
index 0000000..00b7b2d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3147.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3147.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03147ent_a IS
+END c05s02b02x00p08n01i03147ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03147arch_a OF c05s02b02x00p08n01i03147ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03147 - Architecture did not implicitly choose the most recently analyzed one for the entity."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03147arch_a;
+
+
+ARCHITECTURE c05s02b02x00p08n01i03147arch_b OF c05s02b02x00p08n01i03147ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03147"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03147arch_b;
+
+
+--
+
+
+ENTITY c05s02b02x00p08n01i03147ent IS
+END c05s02b02x00p08n01i03147ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03147arch OF c05s02b02x00p08n01i03147ent IS
+  component c05s02b02x00p08n01i03147ent_c
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03147ent_c;
+END c05s02b02x00p08n01i03147arch;
+
+
+
+configuration c05s02b02x00p08n01i03147cfg of c05s02b02x00p08n01i03147ent is
+  for c05s02b02x00p08n01i03147arch
+    for comp1 : c05s02b02x00p08n01i03147ent_c use entity work.c05s02b02x00p08n01i03147ent_a;
+    end for;
+  end for;
+end c05s02b02x00p08n01i03147cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3148.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3148.vhd
new file mode 100644
index 0000000..c950077
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3148.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3148.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03148ent_a IS
+END c05s02b02x00p08n01i03148ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03148arch_a OF c05s02b02x00p08n01i03148ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03148 - Architecture did not implicitly choose the most recently analyzed one for the entity."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03148arch_a;
+
+
+--most recently analyzed ...
+ARCHITECTURE c05s02b02x00p08n01i03148arch_b OF c05s02b02x00p08n01i03148ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03148"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03148arch_b;
+
+
+--
+
+
+ENTITY c05s02b02x00p08n01i03148ent IS
+END c05s02b02x00p08n01i03148ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03148arch OF c05s02b02x00p08n01i03148ent IS
+
+begin
+  blk : block
+    component c05s02b02x00p08n01i03148ent_c
+    end component;
+    for comp1 : c05s02b02x00p08n01i03148ent_c use entity work.c05s02b02x00p08n01i03148ent_a;
+  BEGIN
+    comp1 : c05s02b02x00p08n01i03148ent_c;
+  end block;
+
+END c05s02b02x00p08n01i03148arch;
+
+
+configuration c05s02b02x00p08n01i03148_cfg of c05s02b02x00p08n01i03148ent is
+  for c05s02b02x00p08n01i03148arch
+  end for;
+end c05s02b02x00p08n01i03148_cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3149.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3149.vhd
new file mode 100644
index 0000000..5c9b660
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3149.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3149.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03149ent_a IS
+END c05s02b02x00p08n01i03149ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03149arch_a OF c05s02b02x00p08n01i03149ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03149 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03149arch_a;
+
+
+ARCHITECTURE c05s02b02x00p08n01i03149arch_b OF c05s02b02x00p08n01i03149ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03149"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03149arch_b;
+
+
+--
+
+
+ENTITY c05s02b02x00p08n01i03149ent IS
+END c05s02b02x00p08n01i03149ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03149arch OF c05s02b02x00p08n01i03149ent IS
+  component c05s02b02x00p08n01i03149ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03149ent_a;
+
+END c05s02b02x00p08n01i03149arch;
+
+
+configuration c05s02b02x00p08n01i03149cfg of c05s02b02x00p08n01i03149ent is
+  for c05s02b02x00p08n01i03149arch
+    for comp1 : c05s02b02x00p08n01i03149ent_a use entity work.c05s02b02x00p08n01i03149ent_a(c05s02b02x00p08n01i03149arch_b);
+    end for;
+  end for;
+end c05s02b02x00p08n01i03149cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3150.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3150.vhd
new file mode 100644
index 0000000..56f1a62
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3150.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3150.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03150ent_a IS
+END c05s02b02x00p08n01i03150ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03150arch_a OF c05s02b02x00p08n01i03150ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03150 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03150arch_a;
+
+
+
+ARCHITECTURE c05s02b02x00p08n01i03150arch_c OF c05s02b02x00p08n01i03150ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03150 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03150arch_c;
+
+
+
+ARCHITECTURE c05s02b02x00p08n01i03150arch_b OF c05s02b02x00p08n01i03150ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03150"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03150arch_b;
+
+--
+
+ENTITY c05s02b02x00p08n01i03150ent IS
+END c05s02b02x00p08n01i03150ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03150arch OF c05s02b02x00p08n01i03150ent IS
+  component c05s02b02x00p08n01i03150ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03150ent_a;
+
+END c05s02b02x00p08n01i03150arch;
+
+
+
+configuration c05s02b02x00p08n01i03150cfg of c05s02b02x00p08n01i03150ent is
+  for c05s02b02x00p08n01i03150arch
+    for comp1 : c05s02b02x00p08n01i03150ent_a use entity work.c05s02b02x00p08n01i03150ent_a;
+    end for;
+  end for;
+end c05s02b02x00p08n01i03150cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3151.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3151.vhd
new file mode 100644
index 0000000..18189fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3151.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3151.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03151ent_a IS
+END c05s02b02x00p08n01i03151ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03151arch_a OF c05s02b02x00p08n01i03151ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03151 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03151arch_a;
+
+
+
+ARCHITECTURE c05s02b02x00p08n01i03151arch_c OF c05s02b02x00p08n01i03151ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03151 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03151arch_c;
+
+
+
+ARCHITECTURE c05s02b02x00p08n01i03151arch_b OF c05s02b02x00p08n01i03151ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03151"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03151arch_b;
+
+--
+
+ENTITY c05s02b02x00p08n01i03151ent IS
+END c05s02b02x00p08n01i03151ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03151arch OF c05s02b02x00p08n01i03151ent IS
+  component c05s02b02x00p08n01i03151ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03151ent_a;
+
+END c05s02b02x00p08n01i03151arch;
+
+
+
+configuration c05s02b02x00p08n01i03151cfg of c05s02b02x00p08n01i03151ent is
+  for c05s02b02x00p08n01i03151arch
+  end for;
+end c05s02b02x00p08n01i03151cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3152.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3152.vhd
new file mode 100644
index 0000000..72ff2d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3152.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3152.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b02x00p08n01i03152ent_a IS
+END c05s02b02x00p08n01i03152ent_a;
+
+ARCHITECTURE c05s02b02x00p08n01i03152arch_a OF c05s02b02x00p08n01i03152ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03152 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03152arch_a;
+
+
+ARCHITECTURE c05s02b02x00p08n01i03152arch_b OF c05s02b02x00p08n01i03152ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s02b02x00p08n01i03152 - The architecture body is not the most recently analyzed architecture body associated with the entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03152arch_b;
+
+
+
+ENTITY c05s02b02x00p08n01i03152ent_c IS
+END c05s02b02x00p08n01i03152ent_c;
+
+ARCHITECTURE c05s02b02x00p08n01i03152arch_c OF c05s02b02x00p08n01i03152ent_c IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c05s02b02x00p08n01i03152"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b02x00p08n01i03152arch_c;
+
+
+
+ENTITY c05s02b02x00p08n01i03152ent IS
+END c05s02b02x00p08n01i03152ent;
+
+ARCHITECTURE c05s02b02x00p08n01i03152arch OF c05s02b02x00p08n01i03152ent IS
+  component c05s02b02x00p08n01i03152ent_a
+  end component;
+BEGIN
+  comp1 : c05s02b02x00p08n01i03152ent_a;
+
+END c05s02b02x00p08n01i03152arch;
+
+
+
+configuration c05s02b02x00p08n01i03152cfg of c05s02b02x00p08n01i03152ent is
+  for c05s02b02x00p08n01i03152arch
+    for comp1 : c05s02b02x00p08n01i03152ent_a use entity work.c05s02b02x00p08n01i03152ent_c;
+    end for;
+  end for;
+end c05s02b02x00p08n01i03152cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3153.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3153.vhd
new file mode 100644
index 0000000..5d6118c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3153.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3153.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p01n01i03153ent IS
+END c05s03b00x00p01n01i03153ent;
+
+ARCHITECTURE c05s03b00x00p01n01i03153arch OF c05s03b00x00p01n01i03153ent IS
+
+begin
+--Enclose the whole schematic in a block
+  L : block
+    -- Define resolution function for SIG:
+    function RESFUNC( S : BIT_VECTOR ) return BIT is
+    begin
+      for I in S'RANGE loop
+        if (S(I) = '1') then
+          return '1';
+        end if;
+      end loop;
+      return '0';
+    end RESFUNC;
+    
+    -- Define the signal.
+    subtype    RBIT    is RESFUNC BIT;
+    signal       SIG    : RBIT bus;
+    
+    -- Define the disconnect specification.
+    disconnect    SIG    : RBIT after 0 ns;
+    
+    -- Define the GUARD signal.
+    signal    GUARD    : BOOLEAN := FALSE;
+  BEGIN
+    -- Define the guarded signal assignment.
+    L1: block
+    begin
+      SIG <= guarded '1';
+    end block L1;
+
+    TESTING: PROCESS
+      variable    pass : integer := 0;
+    BEGIN
+
+      -- 1. Turn on the GUARD, verify that SIG gets toggled.
+      GUARD <= TRUE;
+      wait on SIG;
+      assert( SIG = '1' );
+      if ( SIG = '1' ) then
+        pass := pass + 1;
+      end if;
+      
+      -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+      GUARD <= FALSE;
+      wait on SIG;
+      assert( SIG = '0' );
+      if ( SIG = '0' ) then
+        pass := pass + 1;
+      end if;
+
+      wait for 50 ns; 
+      assert NOT( pass = 2 )
+        report "***PASSED TEST: c05s03b00x00p01n01i03153"
+        severity NOTE;
+      assert ( pass = 2 )
+        report "***FAILED TEST: c05s03b00x00p01n01i03153 - Disconnect in block statement does not work properly."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block L;
+
+END c05s03b00x00p01n01i03153arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3154.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3154.vhd
new file mode 100644
index 0000000..3ca724b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3154.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3154.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p01n01i03154ent IS
+END c05s03b00x00p01n01i03154ent;
+
+ARCHITECTURE c05s03b00x00p01n01i03154arch OF c05s03b00x00p01n01i03154ent IS
+  -- Define res function for SIG:
+  function RESFUNC( S : BIT_VECTOR ) return BIT is
+  begin
+    for I in S'RANGE loop
+      if (S(I) = '1') then
+        return '1';
+      end if;
+    end loop;
+    return '0';
+  end RESFUNC;
+  
+  -- Define the signal.
+  subtype    RBIT    is RESFUNC BIT;
+  signal    SIG    : RBIT bus;
+  
+  -- Define the disconnect specification.
+  disconnect    SIG    : RBIT after 0 ns;
+  
+  -- Define the GUARD signal.
+  signal    GUARD    : BOOLEAN := FALSE;
+BEGIN
+  -- Define the guarded signal assignment.
+  L1: block
+  begin
+    SIG <= guarded '1';
+  end block L1;
+
+  TESTING: PROCESS
+    variable    pass : integer := 0;
+  BEGIN
+
+    -- 1. Turn on the GUARD, verify that SIG gets toggled.
+    GUARD <= TRUE;
+    wait on SIG;
+    assert( SIG = '1' );
+    if ( SIG = '1' ) then
+      pass := pass + 1;
+    end if;
+    
+    -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+    GUARD <= FALSE;
+    wait on SIG;
+    assert( SIG = '0' );
+    if ( SIG = '0' ) then
+      pass := pass + 1;
+    end if;
+
+    wait for 50 ns; 
+    assert NOT( pass = 2 )
+      report "***PASSED TEST: c05s03b00x00p01n01i03154"
+      severity NOTE;
+    assert ( pass = 2 )
+      report "***FAILED TEST: c05s03b00x00p01n01i03154 - Disconnect does not work properly."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s03b00x00p01n01i03154arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3155.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3155.vhd
new file mode 100644
index 0000000..3e2cdb8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3155.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3155.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p01n01i03155ent IS
+END c05s03b00x00p01n01i03155ent;
+
+ARCHITECTURE c05s03b00x00p01n01i03155arch OF c05s03b00x00p01n01i03155ent IS
+
+  -- Define resolution function for SIG:
+  function RESFUNC( S : BIT_VECTOR ) return BIT is
+  begin
+    for I in S'RANGE loop
+      if (S(I) = '1') then
+        return '1';
+      end if;
+    end loop;
+    return '0';
+  end RESFUNC;
+  
+  -- Define the signal.
+  subtype    RBIT    is RESFUNC BIT;
+  signal       SIG    : RBIT bus;
+  
+  -- Define the disconnect specification.
+  disconnect    SIG    : RBIT after 0 ns;
+  
+  -- Define the GUARD signal.
+  signal    GUARD    : BOOLEAN := FALSE;
+BEGIN
+  -- Define the guarded signal assignment.
+  L1: block( GUARD = TRUE )
+  begin
+    SIG <= guarded '1';
+  end block L1;
+
+  TESTING: PROCESS
+    variable    pass : integer := 0;
+  BEGIN
+
+    -- 1. Turn on the GUARD, verify that SIG gets toggled.
+    GUARD <= TRUE;
+    wait on SIG;
+    assert( SIG = '1' );
+    if ( SIG = '1' ) then
+      pass := pass + 1;
+    end if;
+    
+    -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+    GUARD <= FALSE;
+    wait on SIG;
+    assert( SIG = '0' );
+    if ( SIG = '0' ) then
+      pass := pass + 1;
+    end if;
+
+    wait for 50 ns; 
+    assert NOT( pass = 2 )
+      report "***PASSED TEST: c05s03b00x00p01n01i03155"
+      severity NOTE;
+    assert ( pass = 2 )
+      report "***FAILED TEST: c05s03b00x00p01n01i03155 - Disconnect does not work properly."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s03b00x00p01n01i03155arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3156.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3156.vhd
new file mode 100644
index 0000000..ddb3854
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3156.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3156.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p01n01i03156ent IS
+END c05s03b00x00p01n01i03156ent;
+
+ARCHITECTURE c05s03b00x00p01n01i03156arch OF c05s03b00x00p01n01i03156ent IS
+
+begin
+--Enclose the whole schematic in a block.
+  L : block
+    -- Define resolution function for SIG:
+    function RESFUNC( S : BIT_VECTOR ) return BIT is
+    begin
+      for I in S'RANGE loop
+        if (S(I) = '1') then
+          return '1';
+        end if;
+      end loop;
+      return '0';
+    end RESFUNC;
+    
+    -- Define the signal.
+    subtype    RBIT    is RESFUNC BIT;
+    signal       SIG    : RBIT bus;
+    
+    -- Define the disconnect specification.
+    disconnect    SIG    : RBIT after 0 ns;
+    
+    -- Define the GUARD signal.
+    signal    GUARD    : BOOLEAN := FALSE;
+  BEGIN
+    -- Define the guarded signal assignment.
+    L1: block( GUARD = TRUE )
+    begin
+      SIG <= guarded '1';
+    end block L1;
+
+    TESTING: PROCESS
+      variable    pass : integer := 0;
+    BEGIN
+
+      -- 1. Turn on the GUARD, verify that SIG gets toggled.
+      GUARD <= TRUE;
+      wait on SIG;
+      assert( SIG = '1' );
+      if ( SIG = '1' ) then
+        pass := pass + 1;
+      end if;
+      
+      -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+      GUARD <= FALSE;
+      wait on SIG;
+      assert( SIG = '0' );
+      if ( SIG = '0' ) then
+        pass := pass + 1;
+      end if;
+
+      wait for 50 ns; 
+      assert NOT( pass = 2 )
+        report "***PASSED TEST: c05s03b00x00p01n01i03156"
+        severity NOTE;
+      assert ( pass = 2 )
+        report "***FAILED TEST: c05s03b00x00p01n01i03156 - Disconnect in block statement does not work properly."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+  end block L;
+
+END c05s03b00x00p01n01i03156arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3157.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3157.vhd
new file mode 100644
index 0000000..ccd9ede
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3157.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3157.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p16n01i03157ent IS
+  -- Define resolution function for SIG:
+  function RESFUNC( S : BIT_VECTOR ) return BIT is
+  begin
+    for I in S'RANGE loop
+      if (S(I) = '1') then
+        return '1';
+      end if;
+    end loop;
+    return '0';
+  end RESFUNC;
+
+  -- Define the signal.
+  subtype RBIT is RESFUNC BIT;
+  signal SIG : RBIT bus;
+
+  -- Use the implicit disconnect specification here.
+
+  -- Define the GUARD signal.
+  signal GUARD : BOOLEAN := FALSE;
+begin
+END c05s03b00x00p16n01i03157ent;
+
+ARCHITECTURE c05s03b00x00p16n01i03157arch OF c05s03b00x00p16n01i03157ent IS
+
+BEGIN
+
+  -- Define the guarded signal assignment.
+  L1: block
+  begin
+    SIG <= guarded '1';
+  end block L1;
+
+
+  TESTING: PROCESS
+    variable ShouldBeTime : TIME;
+  BEGIN
+    -- 1. Turn on the GUARD, verify that SIG gets toggled.
+    GUARD <= TRUE;
+    ShouldBeTime := NOW;
+    wait on SIG;
+    assert( SIG = '1' ) severity FAILURE;
+    assert( ShouldBeTime = NOW ) severity FAILURE;
+    
+    -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+    GUARD <= FALSE;
+    ShouldBeTime := NOW;
+    wait on SIG;
+    assert( SIG = '0' ) severity FAILURE;
+    assert( ShouldBeTime = NOW ) severity FAILURE;
+
+    assert NOT( SIG = '0' and ShouldBeTime = NOW )
+      report "***PASSED TEST: c05s03b00x00p16n01i03157"
+      severity NOTE;
+    assert ( SIG = '0' and ShouldBeTime = NOW )
+      report "***FAILED TEST: c05s03b00x00p16n01i03157 - Default disconnect specification test failed."
+      severity ERROR;
+    
+    -- Define a second driver for SIG, just for kicks.
+    -- Should never get invoked.  Not have an effect on the value.
+    SIG <= '0' after 10 ns;
+    wait;
+  END PROCESS TESTING;
+
+END c05s03b00x00p16n01i03157arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3158.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3158.vhd
new file mode 100644
index 0000000..458e092
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3158.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3158.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p16n01i03158ent IS
+END c05s03b00x00p16n01i03158ent;
+
+ARCHITECTURE c05s03b00x00p16n01i03158arch OF c05s03b00x00p16n01i03158ent IS
+  -- Define resolution function for SIG:
+  function RESFUNC( S : BIT_VECTOR ) return BIT is
+  begin
+    for I in S'RANGE loop
+      if (S(I) = '1') then
+        return '1';
+      end if;
+    end loop;
+    return '0';
+  end RESFUNC;
+
+  -- Define the signal.
+  subtype RBIT is RESFUNC BIT;
+  signal SIG : RBIT bus;
+
+  -- Use the implicit disconnect specification here.
+
+  -- Define the GUARD signal.
+  signal GUARD : BOOLEAN := FALSE;
+BEGIN
+
+  -- Define the guarded signal assignment.
+  L1: block
+  begin
+    SIG <= guarded '1';
+  end block L1;
+
+
+  TESTING: PROCESS
+    variable ShouldBeTime : TIME;
+  BEGIN
+    -- 1. Turn on the GUARD, verify that SIG gets toggled.
+    GUARD <= TRUE;
+    ShouldBeTime := NOW;
+    wait on SIG;
+    assert( SIG = '1' ) severity FAILURE;
+    assert( ShouldBeTime = NOW ) severity FAILURE;
+    
+    -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+    GUARD <= FALSE;
+    ShouldBeTime := NOW;
+    wait on SIG;
+    assert( SIG = '0' ) severity FAILURE;
+    assert( ShouldBeTime = NOW ) severity FAILURE;
+
+    assert NOT( SIG = '0' and ShouldBeTime = NOW )
+      report "***PASSED TEST: c05s03b00x00p16n01i03158"
+      severity NOTE;
+    assert ( SIG = '0' and ShouldBeTime = NOW )
+      report "***FAILED TEST: c05s03b00x00p16n01i03158 - Default disconnect specification test failed."
+      severity ERROR;
+    
+    -- Define a second driver for SIG, just for kicks.
+    -- Should never get invoked.  Not have an effect on the value.
+    SIG <= '0' after 10 ns;
+    wait;
+  END PROCESS TESTING;
+
+END c05s03b00x00p16n01i03158arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3159.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3159.vhd
new file mode 100644
index 0000000..3aca948
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3159.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3159.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s03b00x00p16n01i03159ent IS
+END c05s03b00x00p16n01i03159ent;
+
+ARCHITECTURE c05s03b00x00p16n01i03159arch OF c05s03b00x00p16n01i03159ent IS
+
+begin
+  L : block
+    -- Define resolution function for SIG:
+    function RESFUNC( S : BIT_VECTOR ) return BIT is
+    begin
+      for I in S'RANGE loop
+        if (S(I) = '1') then
+          return '1';
+        end if;
+      end loop;
+      return '0';
+    end RESFUNC;
+
+    -- Define the signal.
+    subtype RBIT is RESFUNC BIT;
+    signal SIG : RBIT bus;
+
+    -- Use the implicit disconnect specification here.
+
+    -- Define the GUARD signal.
+    signal GUARD : BOOLEAN := FALSE;
+  BEGIN
+
+    -- Define the guarded signal assignment.
+    L1: block
+    begin
+      SIG <= guarded '1';
+    end block L1;
+
+
+    TESTING: PROCESS
+      variable ShouldBeTime : TIME;
+    BEGIN
+      -- 1. Turn on the GUARD, verify that SIG gets toggled.
+      GUARD <= TRUE;
+      ShouldBeTime := NOW;
+      wait on SIG;
+      assert( SIG = '1' ) severity FAILURE;
+      assert( ShouldBeTime = NOW ) severity FAILURE;
+      
+      -- 2. Turn off the GUARD, verify that SIG gets turned OFF.
+      GUARD <= FALSE;
+      ShouldBeTime := NOW;
+      wait on SIG;
+      assert( SIG = '0' ) severity FAILURE;
+      assert( ShouldBeTime = NOW ) severity FAILURE;
+
+      assert NOT( SIG = '0' and ShouldBeTime = NOW )
+        report "***PASSED TEST: c05s03b00x00p16n01i03159"
+        severity NOTE;
+      assert ( SIG = '0' and ShouldBeTime = NOW )
+        report "***FAILED TEST: c05s03b00x00p16n01i03159 - Default disconnect specification test failed."
+        severity ERROR;
+      
+      -- Define a second driver for SIG, just for kicks.
+      -- Should never get invoked.  Not have an effect on the value.
+      SIG <= '0' after 10 ns;
+      wait;
+    END PROCESS TESTING;
+  end block L;
+
+END c05s03b00x00p16n01i03159arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3160.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3160.vhd
new file mode 100644
index 0000000..ecfacad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3160.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3160.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p166n01i03160ent IS
+END c14s01b00x00p166n01i03160ent;
+
+ARCHITECTURE c14s01b00x00p166n01i03160arch OF c14s01b00x00p166n01i03160ent IS
+  signal clk : BIT:= '0';
+BEGIN
+
+  clk <= '1' after 10 ns;
+
+  TESTING: PROCESS(clk)
+  BEGIN
+    if (NOW > 1 ns) then
+      assert NOT( clk'EVENT and NOW = 10 ns )
+        report "***PASSED TEST: c14s01b00x00p166n01i03160"
+        severity NOTE;
+      assert ( clk'EVENT and NOW = 10 ns )
+        report "***FAILED TEST: c14s01b00x00p166n01i03160 - Attribute EVENT test failed."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+END c14s01b00x00p166n01i03160arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3162.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3162.vhd
new file mode 100644
index 0000000..a28b0ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3162.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3162.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p07n01i03162ent IS
+END c14s01b00x00p07n01i03162ent;
+
+ARCHITECTURE c14s01b00x00p07n01i03162arch OF c14s01b00x00p07n01i03162ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    subtype BTRUE    is BOOLEAN range TRUE to TRUE;
+    subtype ST    is INTEGER range -5 to 20;
+
+    type E is (A,B,C,D);
+    type P is range 1 to 24
+      units
+        U;
+        X=3 U;
+        Y=2 X;
+      end units;
+
+  BEGIN
+    wait for 5 ns;
+    assert NOT(       (E'BASE'LEFT   =E'LEFT)
+                      and    (REAL'BASE'HIGH   =REAL'HIGH)
+                      and    (E'BASE'POS(C)   =E'POS(C))
+                      and    (ST'BASE'VAL(1)   =INTEGER'VAL(1))
+                      and    (INTEGER'BASE'PRED(1)   =INTEGER'PRED(1))
+                      and    (P'BASE'SUCC(2 Y)   =P'SUCC(2 Y)))
+      report "***PASSED TEST: /src/ch14/sc01/p007/s010101.vhd"
+      severity NOTE;
+    assert (       (E'BASE'LEFT   =E'LEFT)
+                   and    (REAL'BASE'HIGH   =REAL'HIGH)
+                   and    (E'BASE'POS(C)   =E'POS(C))
+                   and    (ST'BASE'VAL(1)   =INTEGER'VAL(1))
+                   and    (INTEGER'BASE'PRED(1)   =INTEGER'PRED(1))
+                   and    (P'BASE'SUCC(2 Y)   =P'SUCC(2 Y)))
+      report "***FAILED TEST: c14s01b00x00p07n01i03162 - Result of T'BASE must be same as the base type of T."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p07n01i03162arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3163.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3163.vhd
new file mode 100644
index 0000000..b8c9fbf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3163.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3163.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p12n01i03163ent IS
+END c14s01b00x00p12n01i03163ent;
+
+ARCHITECTURE c14s01b00x00p12n01i03163arch OF c14s01b00x00p12n01i03163ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'left = 0    and
+                   roufbit'left = 15   )
+      report "***PASSED TEST: c14s01b00x00p12n01i03163"
+      severity NOTE;
+    assert (    fourbit'left = 0    and
+                roufbit'left = 15   )
+      report "***FAILED TEST: c14s01b00x00p12n01i03163 - Predefined attribute LEFT for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p12n01i03163arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3164.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3164.vhd
new file mode 100644
index 0000000..7ff3b5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3164.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3164.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p12n01i03164ent IS
+END c14s01b00x00p12n01i03164ent;
+
+ARCHITECTURE c14s01b00x00p12n01i03164arch OF c14s01b00x00p12n01i03164ent IS
+  type color is (red, green, blue);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( color'left = red )
+      report "***PASSED TEST: c14s01b00x00p12n01i03164"
+      severity NOTE;
+    assert ( color'left = red )
+      report "***FAILED TEST: c14s01b00x00p12n01i03164 - Predefined attribute LEFT for enumeration type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p12n01i03164arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3165.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3165.vhd
new file mode 100644
index 0000000..9260ddc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3165.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3165.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p12n01i03165ent IS
+END c14s01b00x00p12n01i03165ent;
+
+ARCHITECTURE c14s01b00x00p12n01i03165arch OF c14s01b00x00p12n01i03165ent IS
+  subtype abc is real range 0.0 to 20.0;
+  subtype cba is real range 20.0 downto 0.0;
+  subtype xyz is real range 20.0 to 0.0;
+  subtype zyx is real range 0.0 downto 20.0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    abc'left = 0.0   and
+                   cba'left = 20.0   and
+                   xyz'left = 20.0   and
+                   zyx'left = 0.0   )
+      report "***PASSED TEST: c14s01b00x00p12n01i03165"
+      severity NOTE;
+    assert (    abc'left = 0.0   and
+                cba'left = 20.0   and
+                xyz'left = 20.0   and
+                zyx'left = 0.0   )
+      report "***FAILED TEST: c14s01b00x00p12n01i03165 - Predefined attribute LEFT for floating point type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p12n01i03165arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3166.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3166.vhd
new file mode 100644
index 0000000..50d93f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3166.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3166.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p12n01i03166ent IS
+END c14s01b00x00p12n01i03166ent;
+
+ARCHITECTURE c14s01b00x00p12n01i03166arch OF c14s01b00x00p12n01i03166ent IS
+  constant L : REAL := -10.0;
+  constant R : REAL := 10.0;
+
+  type RT1 is range L to R;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    RT1'left = RT1(L)   )
+      report "***PASSED TEST: c14s01b00x00p12n01i03166"
+      severity NOTE;
+    assert (    RT1'left = RT1(L)   )
+      report "***FAILED TEST: c14s01b00x00p12n01i03166 - Predefined attribute LEFT for floating point type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p12n01i03166arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3167.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3167.vhd
new file mode 100644
index 0000000..a77aeca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3167.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3167.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p17n01i03167ent IS
+END c14s01b00x00p17n01i03167ent;
+
+ARCHITECTURE c14s01b00x00p17n01i03167arch OF c14s01b00x00p17n01i03167ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;   
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'right = 15    and
+                   roufbit'right = 0   )
+      report "***PASSED TEST: c14s01b00x00p17n01i03167"
+      severity NOTE;
+    assert (    fourbit'right = 15    and
+                roufbit'right = 0   )
+      report "***FAILED TEST: c14s01b00x00p17n01i03167 - Predefined attribute RIGHT for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p17n01i03167arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3168.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3168.vhd
new file mode 100644
index 0000000..8de3186
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3168.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3168.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p17n01i03168ent IS
+END c14s01b00x00p17n01i03168ent;
+
+ARCHITECTURE c14s01b00x00p17n01i03168arch OF c14s01b00x00p17n01i03168ent IS
+  type color is (red, green, blue);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( color'right = blue )
+      report "***PASSED TEST: c14s01b00x00p17n01i03168"
+      severity NOTE;
+    assert ( color'right = blue )
+      report "***FAILED TEST: c14s01b00x00p17n01i03168 - Predefined attribute RIGHT for enumeration type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p17n01i03168arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3169.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3169.vhd
new file mode 100644
index 0000000..48ced92
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3169.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3169.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p17n01i03169ent IS
+END c14s01b00x00p17n01i03169ent;
+
+ARCHITECTURE c14s01b00x00p17n01i03169arch OF c14s01b00x00p17n01i03169ent IS
+  subtype abc is real range 0.0 to 20.0;
+  subtype cba is real range 20.0 downto 0.0;
+  subtype xyz is real range 20.0 to 0.0;
+  subtype zyx is real range 0.0 downto 20.0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    abc'right = 20.0   and
+                   cba'right = 0.0      and
+                   xyz'right = 0.0      and
+                   zyx'right = 20.0   )   
+      report "***PASSED TEST: c14s01b00x00p17n01i03169"
+      severity NOTE;
+    assert (    abc'right = 20.0   and
+                cba'right = 0.0      and
+                xyz'right = 0.0      and
+                zyx'right = 20.0   )   
+      report "***FAILED TEST: c14s01b00x00p17n01i03169 - Predefined attribute RIGHT for floating point type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p17n01i03169arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc317.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc317.vhd
new file mode 100644
index 0000000..00e02af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc317.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc317.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b00x00p03n02i00317ent IS
+END c03s02b00x00p03n02i00317ent;
+
+ARCHITECTURE c03s02b00x00p03n02i00317arch OF c03s02b00x00p03n02i00317ent IS
+  type MVL is ('0','1','X','Z') ;
+  type T1 is array (0 to 31) of BIT;
+  type T2 is record
+               D : Integer range 1 to 30;
+               M : Integer range 1 to 12;
+               Y : Integer range 0 to 2000;  -- No_failure_here
+             end record;
+BEGIN
+  TESTING: PROCESS
+    variable k : MVL := 'X';
+  BEGIN
+    assert NOT(k='X') 
+      report "***PASSED TEST: c03s02b00x00p03n02i00317" 
+      severity NOTE;
+    assert (k='X') 
+      report "***FAILED TEST: c03s02b00x00p03n02i00317 - A composite type may contain elements that are of scalar types and composite types (array and record types)." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b00x00p03n02i00317arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3170.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3170.vhd
new file mode 100644
index 0000000..99b07ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3170.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3170.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p17n01i03170ent IS
+END c14s01b00x00p17n01i03170ent;
+
+ARCHITECTURE c14s01b00x00p17n01i03170arch OF c14s01b00x00p17n01i03170ent IS
+  constant L : REAL := -10.0;
+  constant R : REAL := 10.0;
+
+  type RT1 is range L to R;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    RT1'right = RT1(R)   )   
+      report "***PASSED TEST: c14s01b00x00p17n01i03170"
+      severity NOTE;
+    assert (    RT1'right = RT1(R)   )   
+      report "***FAILED TEST: c14s01b00x00p17n01i03170 - Predefined attribute RIGHT for floating point type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p17n01i03170arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3171.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3171.vhd
new file mode 100644
index 0000000..3bae856
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3171.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3171.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p22n01i03171ent IS
+END c14s01b00x00p22n01i03171ent;
+
+ARCHITECTURE c14s01b00x00p22n01i03171arch OF c14s01b00x00p22n01i03171ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   fourbit'high = 15   and
+                  roufbit'high = 15   ) 
+      report "***PASSED TEST: c14s01b00x00p22n01i03171"
+      severity NOTE;
+    assert (   fourbit'high = 15   and
+               roufbit'high = 15   ) 
+      report "***FAILED TEST: c14s01b00x00p22n01i03171 - Predefined attribute HIGH test for integer subtype failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p22n01i03171arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3172.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3172.vhd
new file mode 100644
index 0000000..ace935b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3172.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3172.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p22n01i03172ent IS
+END c14s01b00x00p22n01i03172ent;
+
+ARCHITECTURE c14s01b00x00p22n01i03172arch OF c14s01b00x00p22n01i03172ent IS
+  type color is (red, green, blue);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( color'high = blue )
+      report "***PASSED TEST: c14s01b00x00p22n01i03172"
+      severity NOTE;
+    assert ( color'high = blue )
+      report "***FAILED TEST: c14s01b00x00p22n01i03172 - Predefined attribute HIGH test for enumeration type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p22n01i03172arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3173.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3173.vhd
new file mode 100644
index 0000000..dfa96c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3173.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3173.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p22n01i03173ent IS
+END c14s01b00x00p22n01i03173ent;
+
+ARCHITECTURE c14s01b00x00p22n01i03173arch OF c14s01b00x00p22n01i03173ent IS
+  subtype abc is real range 0.0 to 20.0;
+  subtype cba is real range 20.0 downto 0.0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   abc'high = 20.0   and
+                  cba'high = 20.0   )
+      report "***PASSED TEST: c14s01b00x00p22n01i03173"
+      severity NOTE;
+    assert (   abc'high = 20.0   and
+               cba'high = 20.0   )
+      report "***FAILED TEST: c14s01b00x00p22n01i03173 - Predefined attribute HIGH test for floating point type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p22n01i03173arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3174.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3174.vhd
new file mode 100644
index 0000000..a6730a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3174.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3174.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p22n01i03174ent IS
+END c14s01b00x00p22n01i03174ent;
+
+ARCHITECTURE c14s01b00x00p22n01i03174arch OF c14s01b00x00p22n01i03174ent IS
+  signal gate    : BOOLEAN;
+  signal s    : CHARACTER := NUL;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    gate <= s < CHARACTER'HIGH after 2 ns;
+    wait for 5 ns;
+    assert NOT( gate = TRUE )
+      report "***PASSED TEST: c14s01b00x00p22n01i03174"
+      severity NOTE;
+    assert ( gate = TRUE )
+      report "***FAILED TEST: c14s01b00x00p22n01i03174 - Predefined attribute HIGH test for character type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p22n01i03174arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3175.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3175.vhd
new file mode 100644
index 0000000..2f2eab9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3175.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3175.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p27n01i03175ent IS
+END c14s01b00x00p27n01i03175ent;
+
+ARCHITECTURE c14s01b00x00p27n01i03175arch OF c14s01b00x00p27n01i03175ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   fourbit'low = 0      and
+                  roufbit'low = 0      ) 
+      report "***PASSED TEST: c14s01b00x00p27n01i03175"
+      severity NOTE;
+    assert (   fourbit'low = 0      and
+               roufbit'low = 0      ) 
+      report "***FAILED TEST: c14s01b00x00p27n01i03175 - Predefined attribute LOW for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p27n01i03175arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3176.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3176.vhd
new file mode 100644
index 0000000..7d842a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3176.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3176.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p27n01i03176ent IS
+END c14s01b00x00p27n01i03176ent;
+
+ARCHITECTURE c14s01b00x00p27n01i03176arch OF c14s01b00x00p27n01i03176ent IS
+  type color is (red, green, blue);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( color'low = red )
+      report "***PASSED TEST: c14s01b00x00p27n01i03176"
+      severity NOTE;
+    assert ( color'low = red )
+      report "***FAILED TEST: c14s01b00x00p27n01i03176 - Predefined attribute LOW for enumeration type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p27n01i03176arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3177.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3177.vhd
new file mode 100644
index 0000000..b327926
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3177.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3177.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p27n01i03177ent IS
+END c14s01b00x00p27n01i03177ent;
+
+ARCHITECTURE c14s01b00x00p27n01i03177arch OF c14s01b00x00p27n01i03177ent IS
+  subtype abc is real range 0.0 to 20.0;
+  subtype cba is real range 20.0 downto 0.0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   abc'low = 0.0   and
+                  cba'low = 0.0   )
+      report "***PASSED TEST: c14s01b00x00p27n01i03177"
+      severity NOTE;
+    assert (   abc'low = 0.0   and
+               cba'low = 0.0   )
+      report "***FAILED TEST: c14s01b00x00p27n01i03177 - Predefined attribute LOW for floating point type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p27n01i03177arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3178.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3178.vhd
new file mode 100644
index 0000000..31ac87e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3178.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3178.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p64n01i03178ent IS
+END c14s01b00x00p64n01i03178ent;
+
+ARCHITECTURE c14s01b00x00p64n01i03178arch OF c14s01b00x00p64n01i03178ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'succ(0) = 1   and
+                   roufbit'succ(0) = 1   )
+      report "***PASSED TEST: c14s01b00x00p64n01i03178"
+      severity NOTE;
+    assert (    fourbit'succ(0) = 1   and
+                roufbit'succ(0) = 1   )
+      report "***FAILED TEST: c14s01b00x00p64n01i03178 - Predefined attribute SUCC for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p64n01i03178arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3179.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3179.vhd
new file mode 100644
index 0000000..d48db84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3179.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3179.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p71n01i03179ent IS
+END c14s01b00x00p71n01i03179ent;
+
+ARCHITECTURE c14s01b00x00p71n01i03179arch OF c14s01b00x00p71n01i03179ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'pred(15) = 14   and
+                   roufbit'pred(15) = 14   )
+      report "***PASSED TEST: c14s01b00x00p71n01i03179"
+      severity NOTE;
+    assert (    fourbit'pred(15) = 14   and
+                roufbit'pred(15) = 14   )
+      report "***FAILED TEST: c14s01b00x00p71n01i03179 - Predefined attribute PRED for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p71n01i03179arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc318.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc318.vhd
new file mode 100644
index 0000000..d0bf960
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc318.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc318.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p03n01i00318ent IS
+END c03s02b01x00p03n01i00318ent;
+
+ARCHITECTURE c03s02b01x00p03n01i00318arch OF c03s02b01x00p03n01i00318ent IS
+  type MVL is ('0', '1', 'Z') ;
+  type MVL_vector is array (0 to 63)of MVL;
+BEGIN
+  TESTING: PROCESS
+    variable k : MVL_vector;
+  BEGIN
+    k(5) := 'Z';
+    assert NOT(k(5)='Z')
+      report "***PASSED TEST: c03s02b01x00p03n01i00318"
+      severity NOTE;
+    assert (k(5)='Z')
+      report "***FAILED TEST: c03s02b01x00p03n01i00318 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p03n01i00318arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3180.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3180.vhd
new file mode 100644
index 0000000..943ce74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3180.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3180.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p78n01i03180ent IS
+END c14s01b00x00p78n01i03180ent;
+
+ARCHITECTURE c14s01b00x00p78n01i03180arch OF c14s01b00x00p78n01i03180ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'leftof(15) = 14   and
+                   roufbit'leftof(0) = 1   )
+      report "***PASSED TEST: c14s01b00x00p78n01i03180"
+      severity NOTE;
+    assert (    fourbit'leftof(15) = 14   and
+                roufbit'leftof(0) = 1   )
+      report "***FAILED TEST: c14s01b00x00p78n01i03180 - Predefined attribute LEFTOF for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p78n01i03180arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3181.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3181.vhd
new file mode 100644
index 0000000..8afe89d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3181.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3181.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p85n01i03181ent IS
+END c14s01b00x00p85n01i03181ent;
+
+ARCHITECTURE c14s01b00x00p85n01i03181arch OF c14s01b00x00p85n01i03181ent IS
+  subtype fourbit is integer range 0 to 15;
+  subtype roufbit is integer range 15 downto 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    fourbit'rightof(0) = 1   and
+                   roufbit'leftof(0) = 1   )
+      report "***PASSED TEST: c14s01b00x00p85n01i03181"
+      severity NOTE;
+    assert (    fourbit'rightof(0) = 1   and
+                roufbit'leftof(0) = 1   )
+      report "***FAILED TEST: c14s01b00x00p85n01i03181 - Predefined attribute RIGHTOF for integer subtype test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p85n01i03181arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3182.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3182.vhd
new file mode 100644
index 0000000..6ce00dd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3182.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3182.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p116n01i03182ent IS
+END c14s01b00x00p116n01i03182ent;
+
+ARCHITECTURE c14s01b00x00p116n01i03182arch OF c14s01b00x00p116n01i03182ent IS
+
+  constant C : INTEGER := 1;
+--
+  type t2 is array(c to c + c, 1 to 10) of integer;
+  
+-- transitive cases
+  type t3 is array(t2'range(1), t2'reverse_range(2)) of integer;
+  
+-- 'Range (of two-dimensional array type)
+  type rt311 is range t3'range(1);
+  type rt312 is range t3'range(2);
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(    rt311'LEFT = rt311(c)   and
+                   rt311'RIGHT= rt311(c+c)   and
+                   rt312'LEFT = rt312(10)   and
+                   rt312'RIGHT= rt312(1)   )
+      report "***PASSED TEST: c14s01b00x00p116n01i03182"
+      severity NOTE;
+    assert (    rt311'LEFT = rt311(c)   and
+                rt311'RIGHT= rt311(c+c)   and
+                rt312'LEFT = rt312(10)   and
+                rt312'RIGHT= rt312(1)   )
+      report "***FAILED TEST: c14s01b00x00p116n01i03182 - Predefined attribute range test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p116n01i03182arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3183.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3183.vhd
new file mode 100644
index 0000000..da63404
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3183.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3183.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p122n01i03183ent IS
+END c14s01b00x00p122n01i03183ent;
+
+ARCHITECTURE c14s01b00x00p122n01i03183arch OF c14s01b00x00p122n01i03183ent IS
+
+  constant C : INTEGER := 1;
+--
+  type t2 is array(c to c + c, 1 to 10) of integer;
+  
+-- transitive cases
+  type t3 is array(t2'range(1), t2'reverse_range(2)) of integer;
+  
+-- 'Reverse_Range (of two-dimensional array type)
+  type rt321 is range t3'reverse_range(1);
+  type rt322 is range t3'reverse_range(2);
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(    rt321'LEFT = rt321(c+c)   and
+                   rt321'RIGHT= rt321(c)   and
+                   rt322'LEFT = rt322(1)   and
+                   rt322'RIGHT= rt322(10)   )
+      report "***PASSED TEST: c14s01b00x00p122n01i03183"
+      severity NOTE;
+    assert (    rt321'LEFT = rt321(c+c)   and
+                rt321'RIGHT= rt321(c)   and
+                rt322'LEFT = rt322(1)   and
+                rt322'RIGHT= rt322(10)   )
+      report "***FAILED TEST: c14s01b00x00p122n01i03183 - Predefined attribute reverse_range test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p122n01i03183arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3184.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3184.vhd
new file mode 100644
index 0000000..d3bcec6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3184.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3184.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p128n01i03184ent IS
+END c14s01b00x00p128n01i03184ent;
+
+ARCHITECTURE c14s01b00x00p128n01i03184arch OF c14s01b00x00p128n01i03184ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V : STRING(1 to 5) := "Hello";
+  BEGIN
+    assert V'LENGTH = 5;
+    assert V(1) = 'H';
+    assert V(5) = 'o';
+    assert NOT( V'LENGTH = 5 )
+      report "***PASSED TEST: c14s01b00x00p128n01i03184"
+      severity NOTE;
+    assert ( V'LENGTH = 5 )
+      report "***FAILED TEST: c14s01b00x00p128n01i03184 - Attribute of length test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p128n01i03184arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3185.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3185.vhd
new file mode 100644
index 0000000..a223dee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3185.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3185.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03185ent IS
+END c14s03b00x00p42n01i03185ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03185arch OF c14s03b00x00p42n01i03185ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.02";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,integer'(1994));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03185 - This test will write TEXT of integer type into file iofile.02."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03185arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3186.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3186.vhd
new file mode 100644
index 0000000..00a53f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3186.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3186.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03186ent IS
+END c14s03b00x00p42n01i03186ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03186arch OF c14s03b00x00p42n01i03186ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV    : TEXT open write_mode is "iofile.01";
+    variable L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,string'("TEXT test src/c14s03b00x00p42n01i03186"));
+      WRITELINE   (FILEV, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03186 - This test will write TEXT into file s010101.out."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03186arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3187.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3187.vhd
new file mode 100644
index 0000000..a0552a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3187.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3187.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03187ent IS
+END c14s03b00x00p42n01i03187ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03187arch OF c14s03b00x00p42n01i03187ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.04";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,real'(1994.5));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03187 - This test will write TEXT into file iofile.04."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03187arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3188.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3188.vhd
new file mode 100644
index 0000000..b84de21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3188.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3188.vhd,v 1.3 2001-10-29 02:12:44 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03188ent IS
+END c14s03b00x00p42n01i03188ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03188arch OF c14s03b00x00p42n01i03188ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open read_mode is "iofile.06";
+    variable    L   : LINE;
+    variable   vtime   : time;
+    variable   fail   : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vtime);
+      if (vtime /= 1994 ns) then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03188" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03188 - procedure READLINE for time TEXT file test failed, plese check s010106.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03188arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3189.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3189.vhd
new file mode 100644
index 0000000..bcf4b89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3189.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3189.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03189ent IS
+END c14s03b00x00p42n01i03189ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03189arch OF c14s03b00x00p42n01i03189ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open read_mode is "iofile.02";
+    variable    L   : LINE;
+    variable   vinteger: integer;
+    variable   fail   : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vinteger);
+      if (vinteger /= 1994) then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03189" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03189 - procedure READLINE for integer TEXT file test failed, plese check s010102.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03189arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc319.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc319.vhd
new file mode 100644
index 0000000..570bb8a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc319.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc319.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p03n01i00319ent IS
+END c03s02b01x00p03n01i00319ent;
+
+ARCHITECTURE c03s02b01x00p03n01i00319arch OF c03s02b01x00p03n01i00319ent IS
+  type bit_vctor is array (natural range <>) of bit;  -- Success_here
+BEGIN
+  TESTING: PROCESS
+    subtype kk is bit_vctor(0 to 63);
+    variable k : kk;
+  BEGIN
+    k(5) := '0';
+    assert NOT(k(5)='0')
+      report "***PASSED TEST: c03s02b01x00p03n01i00319"
+      severity NOTE;
+    assert (k(5)='0')
+      report "***FAILED TEST: c03s02b01x00p03n01i00319 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p03n01i00319arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3190.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3190.vhd
new file mode 100644
index 0000000..c7674b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3190.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3190.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03190ent IS
+END c14s03b00x00p42n01i03190ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03190arch OF c14s03b00x00p42n01i03190ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.08";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,bit'('1'));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03190 - This test will write TEXT into file iofile.08."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03190arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3191.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3191.vhd
new file mode 100644
index 0000000..e2ca739
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3191.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3191.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03191ent IS
+END c14s03b00x00p42n01i03191ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03191arch OF c14s03b00x00p42n01i03191ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open read_mode is "iofile.04";
+    variable    L   : LINE;
+    variable   vreal   : real;
+    variable   fail   : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vreal);
+      vreal := vreal - 1994.5;
+      if NOT((vreal > -0.00001) and (vreal < 0.00001)) then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03191"
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03191 - procedure READLINE for real TEXT file test failed, plese check s010104.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03191arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3192.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3192.vhd
new file mode 100644
index 0000000..47fed57
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3192.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3192.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03192ent IS
+END c14s03b00x00p42n01i03192ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03192arch OF c14s03b00x00p42n01i03192ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.06";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,time'(1994 ns));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03192 - This test will write TEXT into file iofile.06."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03192arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3193.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3193.vhd
new file mode 100644
index 0000000..65e9bd7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3193.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3193.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03193ent IS
+END c14s03b00x00p42n01i03193ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03193arch OF c14s03b00x00p42n01i03193ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open read_mode is "iofile.08";
+    variable    L   : LINE;
+    variable   vbit   : bit;
+    variable   fail   : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vbit);
+      if (vbit /= '1') then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03193" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03193 - procedure READLINE for bit TEXT file test failed, plese check s010108.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03193arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3194.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3194.vhd
new file mode 100644
index 0000000..9deb9d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3194.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3194.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03194ent IS
+END c14s03b00x00p42n01i03194ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03194arch OF c14s03b00x00p42n01i03194ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.09";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,bit_vector'("11000011"));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03194 - This test will write TEXT into file iofile.09."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03194arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3195.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3195.vhd
new file mode 100644
index 0000000..13087d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3195.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3195.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03195ent IS
+END c14s03b00x00p42n01i03195ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03195arch OF c14s03b00x00p42n01i03195ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F      : TEXT open read_mode is "iofile.09";
+    variable    L      : LINE;
+    variable   vbitvector   : bit_vector(0 to 7);
+    variable   fail      : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vbitvector);
+      if (vbitvector /= "11000011") then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03195" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03195 - procedure READLINE for bit_vector TEXT file test failed, plese check s010110.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03195arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3196.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3196.vhd
new file mode 100644
index 0000000..b0d89c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3196.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3196.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03196ent IS
+END c14s03b00x00p42n01i03196ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03196arch OF c14s03b00x00p42n01i03196ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.10";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,boolean'(TRUE));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03196 - This test will write TEXT into file iofile.10."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03196arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3197.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3197.vhd
new file mode 100644
index 0000000..df91036
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3197.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3197.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03197ent IS
+END c14s03b00x00p42n01i03197ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03197arch OF c14s03b00x00p42n01i03197ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F      : TEXT open read_mode is "iofile.10";
+    variable    L      : LINE;
+    variable   vboolean   : boolean;
+    variable   fail      : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vboolean);
+      if (vboolean /= TRUE) then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03197"
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03197 - procedure READLINE for boolean TEXT file test failed, plese check s010112.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03197arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3198.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3198.vhd
new file mode 100644
index 0000000..8a492e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3198.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3198.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03198ent IS
+END c14s03b00x00p42n01i03198ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03198arch OF c14s03b00x00p42n01i03198ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.12";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,character'('n'));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03198 - This test will write TEXT into file iofile.12."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03198arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3199.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3199.vhd
new file mode 100644
index 0000000..69726b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3199.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3199.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03199ent IS
+END c14s03b00x00p42n01i03199ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03199arch OF c14s03b00x00p42n01i03199ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F      : TEXT open read_mode is "iofile.12";
+    variable    L      : LINE;
+    variable   vcharacter   : character;
+    variable   fail      : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vcharacter);
+      if (vcharacter /= 'n') then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03199" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03199 - procedure READLINE for character TEXT file test failed, plese check s010114.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03199arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc32.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc32.vhd
new file mode 100644
index 0000000..f979ce7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc32.vhd
@@ -0,0 +1,518 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc32.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p01n01i00032ent IS
+END c04s03b01x01p01n01i00032ent;
+
+ARCHITECTURE c04s03b01x01p01n01i00032arch OF c04s03b01x01p01n01i00032ent IS
+
+--
+--          Declaration of composite types
+--
+  TYPE    U1 IS ARRAY (CHARACTER RANGE <>) OF INTEGER;      -- unconstrained array type
+  TYPE    C1 IS ARRAY (5 TO 9)             OF BIT;          -- constrained array type
+--
+--          Declaration of composite types
+--           - records types and subtypes
+--
+  TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+
+  TYPE R1 IS
+    RECORD
+      month : month_name;
+      day   : INTEGER RANGE 0 TO 31;
+      year  : INTEGER RANGE 0 TO 4000;
+    END RECORD;
+--
+--          Declaration of composite - composite types
+--
+  TYPE US1 IS ARRAY (INTEGER RANGE   <>  ) OF STRING     ( 1      TO  8 );
+  TYPE UV1 IS ARRAY (INTEGER RANGE   <>  ) OF BIT_VECTOR ( 3  DOWNTO  0 );
+  TYPE UU1 IS ARRAY (INTEGER RANGE   <>  ) OF U1         ('a'     TO 'd');
+  TYPE UC1 IS ARRAY (INTEGER RANGE   <>  ) OF C1;
+  TYPE UR1 IS ARRAY (INTEGER RANGE   <>  ) OF R1;
+  
+  TYPE CS1 IS ARRAY (INTEGER RANGE 0 TO 3) OF STRING     ( 1      TO  8 );
+  TYPE CV1 IS ARRAY (INTEGER RANGE 0 TO 3) OF BIT_VECTOR ( 3  DOWNTO  0 );
+  TYPE CU1 IS ARRAY (INTEGER RANGE 0 TO 3) OF U1         ('a'     TO 'd');
+  TYPE CC1 IS ARRAY (INTEGER RANGE 0 TO 3) OF C1;
+  TYPE CR1 IS ARRAY (INTEGER RANGE 0 TO 3) OF R1;
+  
+  TYPE RAR IS RECORD
+                eS1 : STRING     ( 1      TO  8 );
+                eV1 : BIT_VECTOR ( 3  DOWNTO  0 );
+                eU1 : U1         ('a'     TO 'd');
+                eC1 : C1                         ;
+                eR1 : R1                         ;
+              END RECORD;
+----------------------------------------------------------------------------------------
+--
+--          CONSTANT declarations - initial aggregate value
+--           NOTE: index constraints for the unconstrained types are
+--                  established by the intial value.
+--
+  CONSTANT US1_con_1 : US1          := (
+    (NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL),
+    (BS,  HT,  LF,  VT,  FF,  CR,  SO,  SI ),
+    (DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB),
+    (CAN, EM,  SUB, ESC, FSP, GSP, RSP, USP)
+    );
+  
+  CONSTANT UV1_con_1 : UV1          := (
+    ('0', '1', '0', '0'),
+    ('1', '0', '1', '1'),
+    ('1', '0', '0', '0'),
+    ('0', '1', '0', '1')
+    );
+  
+  CONSTANT UU1_con_1 : UU1          := (
+    (  1,   2,   3,   4),
+    (  5,   6,   7,   8),
+    (  9,  10,  11,  12),
+    ( 13,  14,  15,  16)
+    );
+  
+  CONSTANT UC1_con_1 : UC1          := (
+    ('0', '1', '0', '0', '1'),
+    ('0', '1', '1', '1', '0'),
+    ('0', '0', '0', '1', '0'),
+    ('1', '0', '0', '0', '1')
+    );
+  
+  CONSTANT UR1_con_1 : UR1          := (   (Feb,05,1701),
+                                           (Apr,10,1802),
+                                           (Jun,15,1903),
+                                           (Aug,20,2004)  );
+  
+  CONSTANT CS1_con_1 : CS1          := (
+    (NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL),
+    (BS,  HT,  LF,  VT,  FF,  CR,  SO,  SI ),
+    (DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB),
+    (CAN, EM,  SUB, ESC, FSP, GSP, RSP, USP)
+
+    );
+  
+  CONSTANT CV1_con_1 : CV1          := (
+    ('0', '1', '0', '0'),
+    ('1', '0', '1', '1'),
+    ('1', '0', '0', '0'),
+    ('0', '1', '0', '1')
+    );
+
+  CONSTANT CU1_con_1 : CU1          := (
+    (  1,   2,   3,   4),
+    (  5,   6,   7,   8),
+    (  9,  10,  11,  12),
+    ( 13,  14,  15,  16)
+    );
+  
+  CONSTANT CC1_con_1 : CC1          := (
+    ('0', '1', '0', '0', '1'),
+    ('0', '1', '1', '1', '0'),
+    ('0', '0', '0', '1', '0'),
+    ('1', '0', '0', '0', '1')
+    );
+  
+  CONSTANT CR1_con_1 : CR1          := ( (Feb,05,1701),
+                                         (Apr,10,1802),
+                                         (Jun,15,1903),
+                                         (Aug,20,2004)  );
+  
+  CONSTANT RAR_con_1 : RAR          := (
+    (SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS ),
+    ('1', '1', '0', '0'),
+    (  1,   2,   3,   4),
+    ('0', '1', '0', '0', '1'),
+    (Feb,29,0108) );
+  
+--
+--          CONSTANT declarations - aggregate of strings initial value
+--
+  CONSTANT US1_con_2 : US1          := ( "@ABCDEFG", "HIJKLMNO", "PQRSTUVW", "XYZ[\]^_" );
+  CONSTANT UV1_con_2 : UV1          := (    B"0100",    B"1011",    B"1000",    B"0101" );
+  CONSTANT UC1_con_2 : UC1          := (   B"01001",   B"01110",   B"00010",   B"10001" );
+  
+  CONSTANT CS1_con_2 : CS1          := ( "@ABCDEFG", "HIJKLMNO", "PQRSTUVW", "XYZ[\]^_" );
+  CONSTANT CV1_con_2 : CV1          := (    B"0100",    B"1011",    B"1000",    B"0101" );
+  CONSTANT CC1_con_2 : CC1          := (   B"01001",   B"01110",   B"00010",   B"10001" );
+  
+  CONSTANT RAR_con_2 : RAR          := ( "@ABCDEFG",    B"1100",  (1,2,3,4),  B"01001", (Feb,29,0108) );
+  
+  
+-----------------------------------------------------------------------------------------
+BEGIN
+  TESTING: PROCESS
+--
+--          Declarationi for generation of BIT test pattern
+--
+    VARIABLE bval  : BIT;
+    VARIABLE index : INTEGER;
+    VARIABLE ii    : INTEGER;
+
+    variable k    : integer := 0;
+    
+    PROCEDURE pattern ( index : INOUT INTEGER; bval : OUT BIT ) IS
+--
+--                if starting index value is 59, the
+--                test pattern is 01001011100001010001111 (repeats)
+--
+    BEGIN
+      IF index > 100
+      THEN  bval  := '1';
+            index := index - 100;
+      ELSE  bval  := '0';
+      END IF;
+      index := index * 2;
+    END;
+
+  BEGIN
+
+----------------------------------------------------------------------------------------
+--
+--              Verify initial values
+--
+    FOR I IN 0 TO 3 LOOP   ii := INTEGER'LEFT + I;
+                           FOR J IN 1 TO 8 LOOP
+                             if (US1_con_1(ii)(J) /= CHARACTER'VAL((I*8)+(J-1))) then
+                               k := 1;
+                             end if;
+                             ASSERT US1_con_1(ii)(J) = CHARACTER'VAL((I*8)+(J-1))
+                               REPORT "ERROR: Bad initial value of US1_con_1" SEVERITY FAILURE;
+                           END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 3 DOWNTO  0 LOOP
+                            pattern ( index, bval );
+                            if (UV1_con_1(ii)(J) /= bval) then
+                              k := 1;
+                            end if;
+                            ASSERT UV1_con_1(ii)(J) = bval
+                              REPORT "ERROR: Bad initial value of UV1_con_1" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+    index := 0;
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 'a' TO 'd' LOOP
+                            index := index + 1;
+                            if (UU1_con_1(ii)(J) /= index) then
+                              k := 1;
+                            end if;
+                            ASSERT UU1_con_1(ii)(J) = index
+                              REPORT "ERROR: Bad initial value of UU1_con_1" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 5 TO 9 LOOP
+                            pattern ( index, bval );
+                            if (UC1_con_1(ii)(J) /= bval) then
+                              k := 1;
+                            end if;
+                            ASSERT UC1_con_1(ii)(J) = bval
+                              REPORT "ERROR: Bad initial value of UC1_con_1" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          if (UR1_con_1(ii).month /= month_name'VAL((I*2)+1)) then
+                            k := 1;
+                          end if;
+                          ASSERT UR1_con_1(ii).month = month_name'VAL((I*2)+1)
+                            REPORT "ERROR: Bad initial value of UR1_con_1(ii).month" SEVERITY FAILURE;
+                          if (UR1_con_1(ii).day /= I*5 +5) then
+                            k := 1;
+                          end if;
+                          ASSERT UR1_con_1(ii).day = I*5 + 5
+                            REPORT "ERROR: Bad initial value of UR1_con_1(ii).day" SEVERITY FAILURE;
+                          if (UR1_con_1(ii).year /= 1701 +(I*101)) then
+                            k := 1;
+                          end if;
+                          ASSERT UR1_con_1(ii).year = 1701 + (I*101)
+                            REPORT "ERROR: Bad initial value of UR1_con_1(ii).year" SEVERITY FAILURE;
+    END LOOP;
+    
+--
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 1 TO 8 LOOP
+        if (CS1_con_1(I)(J) /= CHARACTER'VAL((I*8)+(J-1))) then
+          k := 1;
+        end if;
+        ASSERT CS1_con_1(I)(J) = CHARACTER'VAL((I*8)+(J-1))
+          REPORT "ERROR: Bad initial value of CS1_con_1" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 3 DOWNTO  0 LOOP
+        pattern ( index, bval );
+        if (CV1_con_1(I)(J) /= bval) then
+          k := 1;
+        end if;
+        ASSERT CV1_con_1(I)(J) = bval
+          REPORT "ERROR: Bad initial value of CV1_con_1" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    index := 0;
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 'a' TO 'd' LOOP
+        index := index + 1;
+        if (CU1_con_1(I)(J) /= index) then
+          k := 1;
+        end if;
+        ASSERT CU1_con_1(I)(J) = index
+          REPORT "ERROR: Bad initial value of CU1_con_1" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 5 TO 9 LOOP
+        pattern ( index, bval );
+        if (CC1_con_1(I)(J) /= bval) then
+          k := 1;
+        end if;
+        ASSERT CC1_con_1(I)(J) = bval
+          REPORT "ERROR: Bad initial value of CC1_con_1" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    FOR I IN 0 TO 3 LOOP
+      if (CR1_con_1(I).month /= month_name'VAL((I*2)+1)) then
+        k := 1;
+      end if;
+      ASSERT CR1_con_1(I).month = month_name'VAL((I*2)+1)
+        REPORT "ERROR: Bad initial value of CR1_con_1(I).month" SEVERITY FAILURE;
+      if (CR1_con_1(I).day /= (I+1)*5) then
+        k := 1;
+      end if;
+      ASSERT CR1_con_1(I).day = (I+1)*5
+        REPORT "ERROR: Bad initial value of CR1_con_1(I).day" SEVERITY FAILURE;
+      if (CR1_con_1(I).year /= 1701 + (I*101)) then
+        k := 1;
+      end if;
+      ASSERT CR1_con_1(I).year = 1701 + (I*101)
+        REPORT "ERROR: Bad initial value of CR1_con_1(I).year" SEVERITY FAILURE;
+    END LOOP;
+    
+--
+    FOR J IN 1 TO 8 LOOP
+      if (RAR_con_1.eS1(J) /= CHARACTER'VAL(J)) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_1.eS1(J) = CHARACTER'VAL(J)
+        REPORT "ERROR: Bad initial value of RAR_con_1.eS1" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR J IN 3 DOWNTO  0 LOOP
+      if (RAR_con_1.eV1(J) /= BIT'VAL(J/2)) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_1.eV1(J) = BIT'VAL(J/2)
+        REPORT "ERROR: Bad initial value of RAR_con_1.eV1" SEVERITY FAILURE;
+    END LOOP;
+    
+    index := 0;
+    FOR J IN 'a' TO 'd' LOOP
+      index := index + 1;
+      if (RAR_con_1.eU1(J) /= index) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_1.eU1(J) = index
+        REPORT "ERROR: Bad initial value of RAR_con_1.eU1" SEVERITY FAILURE;
+    END LOOP;
+    
+    index := 59;
+    FOR J IN 5 TO 9 LOOP
+      pattern ( index, bval );
+      if (RAR_con_1.eC1(J) /= bval) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_1.eC1(J) = bval
+        REPORT "ERROR: Bad initial value of RAR_con_1.eC1" SEVERITY FAILURE;
+    END LOOP;
+    
+    if (RAR_con_1.eR1.month /= FEB) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_1.eR1.month = FEB
+      REPORT "ERROR: Bad initial value of RAR_con_1.eR1.month" SEVERITY FAILURE;
+    if (RAR_con_1.eR1.day /= 29) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_1.eR1.day = 29
+      REPORT "ERROR: Bad initial value of RAR_con_1.eR1.day" SEVERITY FAILURE;
+    if (RAR_con_1.eR1.year /= 0108) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_1.eR1.year = 0108
+      REPORT "ERROR: Bad initial value of RAR_con_1.eR1.year" SEVERITY FAILURE;
+    
+-- ----------------------------------------------------------------------------------
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 1 TO 8 LOOP
+                            if (US1_con_2(ii)(J) /= CHARACTER'VAL((I*8)+(J-1)+64)) then
+                              k := 1;
+                            end if;
+                            ASSERT US1_con_2(ii)(J) = CHARACTER'VAL((I*8)+(J-1)+64)
+                              REPORT "ERROR: Bad initial value of US1_con_2" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 3 DOWNTO  0 LOOP
+                            pattern ( index, bval );
+                            if (UV1_con_2(ii)(J) /= bval) then
+                              k := 1;
+                            end if;
+                            ASSERT UV1_con_2(ii)(J) = bval
+                              REPORT "ERROR: Bad initial value of UV1_con_2" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP  ii := INTEGER'LEFT + I;
+                          FOR J IN 5 TO 9 LOOP
+                            pattern ( index, bval );
+                            if (UC1_con_2(ii)(J) /= bval) then
+                              k := 1;
+                            end if;
+                            ASSERT UC1_con_2(ii)(J) = bval
+                              REPORT "ERROR: Bad initial value of UC1_con_2" SEVERITY FAILURE;
+                          END LOOP;
+    END LOOP;
+    
+--
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 1 TO 8 LOOP
+        if (CS1_con_2(I)(J) /= CHARACTER'VAL((I*8)+(J-1)+64)) then
+          k := 1;
+        end if;
+        ASSERT CS1_con_2(I)(J) = CHARACTER'VAL((I*8)+(J-1)+64)
+          REPORT "ERROR: Bad initial value of CS1_con_2" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 3 DOWNTO  0 LOOP
+        pattern ( index, bval );
+        if (CV1_con_2(I)(J) /= bval) then
+          k := 1;
+        end if;
+        ASSERT CV1_con_2(I)(J) = bval
+          REPORT "ERROR: Bad initial value of CV1_con_2" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+    index := 59;
+    FOR I IN 0 TO 3 LOOP
+      FOR J IN 5 TO 9 LOOP
+        pattern ( index, bval );
+        if (CC1_con_2(I)(J) /= bval) then
+          k := 1;
+        end if;
+        ASSERT CC1_con_2(I)(J) = bval
+          REPORT "ERROR: Bad initial value of CC1_con_2" SEVERITY FAILURE;
+      END LOOP;
+    END LOOP;
+    
+--
+    FOR J IN 1 TO 8 LOOP
+      if (RAR_con_2.eS1(J) /= CHARACTER'VAL((J-1)+64)) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_2.eS1(J) = CHARACTER'VAL((J-1)+64)
+        REPORT "ERROR: Bad initial value of RAR_con_2.eS1" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR J IN 3 DOWNTO  0 LOOP
+      if (RAR_con_2.eV1(J) /= BIT'VAL(J/2)) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_2.eV1(J) = BIT'VAL(J/2)
+        REPORT "ERROR: Bad initial value of RAR_con_2.eV1" SEVERITY FAILURE;
+    END LOOP;
+    
+    index := 0;
+    FOR J IN 'a' TO 'd' LOOP
+      index := index + 1;
+      if (RAR_con_2.eU1(J) /= index) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_2.eU1(J) = index
+        REPORT "ERROR: Bad initial value of RAR_con_2.eU1" SEVERITY FAILURE;
+    END LOOP;
+    
+    index := 59;
+    FOR J IN 5 TO 9 LOOP
+      pattern ( index, bval );
+      if (RAR_con_2.eC1(J) /= bval) then
+        k := 1;
+      end if;
+      ASSERT RAR_con_2.eC1(J) = bval
+        REPORT "ERROR: Bad initial value of RAR_con_2.eC1" SEVERITY FAILURE;
+    END LOOP;
+    
+    if (RAR_con_2.eR1.month /= FEB) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_2.eR1.month = FEB
+      REPORT "ERROR: Bad initial value of RAR_con_2.eR1.month" SEVERITY FAILURE;
+    if (RAR_con_2.eR1.day /=29) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_2.eR1.day = 29
+      REPORT "ERROR: Bad initial value of RAR_con_2.eR1.day" SEVERITY FAILURE;
+    if (RAR_con_2.eR1.year /= 0108) then
+      k := 1;
+    end if;
+    ASSERT RAR_con_2.eR1.year = 0108
+      REPORT "ERROR: Bad initial value of RAR_con_1.eR1.year" SEVERITY
+      FAILURE;
+    
+---------------------------------------------------------------------------------------------
+
+    assert NOT(    k = 0  )
+      report "***PASSED TEST: c04s03b01x01p01n01i00032"
+      severity NOTE;
+    assert (    k = 0  )
+      report "***FAILED TEST:c04s03b01x01p01n01i00032 - A constant declares a constant of the specified type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p01n01i00032arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc320.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc320.vhd
new file mode 100644
index 0000000..b00bbfd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc320.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc320.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p03n01i00320ent IS
+END c03s02b01x00p03n01i00320ent;
+
+ARCHITECTURE c03s02b01x00p03n01i00320arch OF c03s02b01x00p03n01i00320ent IS
+  type matrix1 is array (integer range <>, integer range <>) of real;
+  type matrix2 is array (integer range <>, positive range <>) of real;
+  type matrix4 is array (bit range <>, bit range <>) of TIME;
+BEGIN
+  TESTING: PROCESS
+    subtype kk is matrix1(0 to 6,0 to 6);
+    variable k : kk;
+  BEGIN
+    k(5,5) := 0.1;
+    assert NOT(k(5,5)=0.1)
+      report "***PASSED TEST: c03s02b01x00p03n01i00320"
+      severity NOTE;
+    assert (k(5,5)=0.1)
+      report "***FAILED TEST: c03s02b01x00p03n01i00320 - In the unconstrained array definition, the reserved word array has been followed by a list of index subtype definitions enclosed with parentheses and the reserved word of."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p03n01i00320arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3200.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3200.vhd
new file mode 100644
index 0000000..646048f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3200.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3200.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03200ent IS
+END c14s03b00x00p42n01i03200ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03200arch OF c14s03b00x00p42n01i03200ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.14";
+    variable    L   : LINE;
+  BEGIN
+    --write out to the file
+    for I in 1 to 100 loop
+      WRITE       (L,string'("niu"));
+      WRITELINE   (F, L);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p42n01i03200 - This test will write TEXT into file iofile.14."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03200arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3201.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3201.vhd
new file mode 100644
index 0000000..a188a4e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3201.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3201.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.TEXTIO.all;
+ENTITY c14s03b00x00p42n01i03201ent IS
+END c14s03b00x00p42n01i03201ent;
+
+ARCHITECTURE c14s03b00x00p42n01i03201arch OF c14s03b00x00p42n01i03201ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F      : TEXT open read_mode is "iofile.14";
+    variable    L      : LINE;
+    variable   vstring      : string(1 to 3);
+    variable   fail      : integer := 0;
+  BEGIN
+    for I in 1 to 100 loop
+      READLINE   (F, L);
+      READ       (L, vstring);
+      if (vstring /= "niu") then
+        fail := 1;
+      end if;
+    end loop;
+    assert NOT(fail = 0) 
+      report "***PASSED TEST: c14s03b00x00p42n01i03201" 
+      severity NOTE;
+    assert (fail = 0)
+      report "***FAILED TEST: c14s03b00x00p42n01i03201 - procedure READLINE for string TEXT file test failed, plese check s010116.vhd file also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p42n01i03201arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3202.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3202.vhd
new file mode 100644
index 0000000..e3328ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3202.vhd
@@ -0,0 +1,119 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3202.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.textio.all;
+ENTITY c14s03b00x00p56n01i03202ent IS
+END c14s03b00x00p56n01i03202ent;
+
+ARCHITECTURE c14s03b00x00p56n01i03202arch OF c14s03b00x00p56n01i03202ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open read_mode is "iofile.61";
+    variable    L   : LINE;
+    variable    Bi   : BIT;
+    variable    Bo   : BOOLEAN;
+    variable    BV   : Bit_Vector(1 to 60);
+    variable    BV2   : Bit_Vector(1 to 60);
+
+    -- Define the ScanForStars subprogram
+    procedure ScanForStars(L: inout Line) is
+      variable Index : Natural := 1;
+      variable C1, C2: Character := ' ';
+    begin
+      while C1 = ' ' loop
+        Read(L, C1);
+      end loop;
+      Read(L, C2);
+      assert C1 = '*' and C2 = '*'
+        report "Could not find two stars";
+    end;
+  BEGIN
+    -- Read the entire line..
+    READLINE(F, L);
+    assert L.all = "hello world"
+      report "Could not find opening banner...";
+    
+    -- Read the blank line...
+    READLINE(F, L);
+    assert L.all = ""
+      report "Could not find blank line...";
+    
+    -- Read some BITS...
+    for width in 1 to 10 loop
+      READLINE(F, L);
+      READ(L, Bi);
+      assert Bi = '0'
+        report "Failed in Read(BIT).  (Should be '0')";
+      ScanForStars(L);
+      READ(L, Bi);
+      assert Bi = '1'
+        report "Failed in Read(BIT).  (Should be '1')";
+      ScanForStars(L);
+    end loop;
+    READLINE(F, L);
+    
+    -- Read some Bit vectors...
+    for i in BV'Range loop
+      BV(i) := Bit'Val(Boolean'Pos(BV'Right mod i = 0));
+    end loop;
+    
+    for width in 15 downto 1 loop
+      READLINE(F, L);
+      READ(L, BV2(1 to 2*width));
+      assert BV2(1 to 2*width) = BV((15-width)*2+1 to 30)
+        report "Failed in Read(BIT_VECTOR). (Left side)";
+      ScanForStars(L);
+      READ(L, BV2(1 to 2*width));
+      assert BV2(1 to 2*width) = BV(1 to 2*width)
+        report "Failed in Read(BIT_VECTOR). (Right side)";
+    end loop;
+    READLINE(F, L);
+    
+    -- Read some BOOLEANs...
+    for i in 10 downto 1 loop
+      READLINE(F, L);
+      READ(L, Bo);
+      assert Bo = FALSE
+        report "Failed in Read(BOOLEAN).  (Left side)";
+      ScanForStars(L);
+      READ(L, Bo);
+      assert Bo = TRUE
+        report "Failed in Read(BOOLEAN).  (Right side)";
+    end loop;
+    READLINE(F, L);
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p56n01i03202 - This test file will read in an TEXT file with predefined data type BIT, BITVECOTR, BOOLEAN and STRING, and needs manual check to make sure that there is no ERROR assertion note."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p56n01i03202arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3203.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3203.vhd
new file mode 100644
index 0000000..b794010
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3203.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3203.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library std;
+use std.textio.all;
+ENTITY c14s03b00x00p56n01i03203ent IS
+END c14s03b00x00p56n01i03203ent;
+
+ARCHITECTURE c14s03b00x00p56n01i03203arch OF c14s03b00x00p56n01i03203ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F   : TEXT open write_mode is "iofile.61";
+    variable    L   : LINE;
+    variable    BV   : Bit_Vector(1 to 60);
+  BEGIN
+    -- Write an arbitrary line...
+    L := new STRING'("hello world");
+    WRITELINE(F, L);
+    
+    -- Write a blank line...
+    WRITELINE(F, L);
+    
+    -- Write some BITs...
+    for i in 1 to 10 loop
+      WRITE(L, Bit'('0'), RIGHT, i);
+      WRITE(L, String'("**"), RIGHT, 12-i);
+      WRITE(L, Bit'('1'), LEFT, i);
+      WRITE(L, String'("**"), LEFT, 0);
+      WRITELINE(F, L);
+    end loop;
+    WRITELINE(F, L);
+    
+    -- Write some Bit vectors...
+    for i in BV'Range loop
+      BV(i) := Bit'Val(Boolean'Pos(BV'Right mod i = 0));
+    end loop;
+    
+    for i in 15 downto 1 loop
+      WRITE(L, BV((15-i)*2+1 to 30), RIGHT, 30);
+      WRITE(L, String'("**"), RIGHT, 3);
+      WRITE(L, BV(1 to 2*i), LEFT, 30);
+      WRITELINE(F, L);
+    end loop;
+    WRITELINE(F, L);
+    
+    -- Write some BOOLEANs...
+    for i in 10 downto 1 loop
+      WRITE(L, Boolean'(FALSE), RIGHT, i);
+      WRITE(L, String'("**"), RIGHT, 12-i);
+      WRITE(L, Boolean'(TRUE), RIGHT, 11-i);
+      WRITELINE(F, L);
+    end loop;
+    WRITELINE(F, L);
+    wait for 10 ns;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p56n01i03203 - This test file will output an TEXT file with predefined data type BIT, BITVECOTR, BOOLEAN and STRING, and next test file will be used to verify the correctness of the this writing test."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p56n01i03203arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3204.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3204.vhd
new file mode 100644
index 0000000..e1d20da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3204.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3204.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+library STD;
+use STD.TEXTIO.all;
+ENTITY c14s03b00x00p59n01i03204ent IS
+END c14s03b00x00p59n01i03204ent;
+
+ARCHITECTURE c14s03b00x00p59n01i03204arch OF c14s03b00x00p59n01i03204ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F_out   : Text open write_mode is "iofile.47";
+    variable    L_out   : Line;
+    type       TA    is array (INTEGER range <>) of TIME;
+    constant    A   : TA := (-1 fs, 37582 ns, 1 ms + 1 ns + 1 ps);
+  BEGIN
+
+    for i in A'RANGE loop
+      Write(L_out, A(i), UNIT=>fs, FIELD=>25);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>ps, FIELD=>25);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>ns, FIELD=>25);
+      WriteLine(F_out, L_out);
+      WriteLine(F_out, L_out);
+    end loop;
+    wait for 10 fs;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p59n01i03204 - This test will output an output file, and that file will be compared with s010401.ref file."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p59n01i03204arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3205.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3205.vhd
new file mode 100644
index 0000000..d68db12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3205.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library STD;
+use STD.TEXTIO.all;
+ENTITY c14s03b00x00p59n01i03205ent IS
+END c14s03b00x00p59n01i03205ent;
+
+ARCHITECTURE c14s03b00x00p59n01i03205arch OF c14s03b00x00p59n01i03205ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file F_out   : Text open write_mode is "iofile.64";
+    variable    L_out   : Line;
+    type       TA    is array (INTEGER range <>) of TIME;
+    constant    A   : TA := (1 hr, -1 fs, 37582 ns, 1 ms + 1 ns + 1 ps);
+  BEGIN
+
+    for i in A'RANGE loop
+      Write(L_out, A(i), UNIT=>ps);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>ns);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>us);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>ms);
+      WriteLine(F_out, L_out);
+      Write(L_out, A(i), UNIT=>sec);
+      WriteLine(F_out, L_out);
+      WriteLine(F_out, L_out);
+    end loop;
+    wait for 10 fs;
+    assert FALSE
+      report "***PASSED TEST: c14s03b00x00p59n01i03205 - This test will output an output file, and that file will be compared with s010402.ref file."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p59n01i03205arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc3206.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc3206.vhd
new file mode 100644
index 0000000..24c549c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc3206.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library std;
+use std.textio.all;
+ENTITY c14s03b00x00p60n01i03206ent IS
+END c14s03b00x00p60n01i03206ent;
+
+ARCHITECTURE c14s03b00x00p60n01i03206arch OF c14s03b00x00p60n01i03206ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    procedure write1 is
+      file F: TEXT open write_mode is "iofile.64";
+      variable    L: LINE;
+
+    begin
+      write(L, Integer'(12));
+      writeline(F, L);
+      write(L, Integer'(34));
+      writeline(F, L);
+      write(L, Integer'(56));
+      writeline(F, L);
+      write(L, Integer'(78));
+      writeline(F, L);
+      write(L, Integer'(90));
+      writeline(F, L);
+
+    end write1;
+
+    procedure read1 is
+      file F: TEXT open read_mode is "s010301.in";
+      variable    L: LINE;
+      variable    i,v_integer : Integer;
+    begin
+      i := 0;
+      while not ENDFILE(F) loop
+        readline(F, L);
+        i := i + 1;
+      end loop;
+
+      Assert i /= 4
+        report "Line count to ENDFILE is incorrect"
+        severity ERROR;
+      assert NOT( i = 5 )
+        report "***PASSED TEST: c14s03b00x00p60n01i03206"
+        severity NOTE;
+      assert ( i = 5 )
+        report "***FAILED TEST: c14s03b00x00p60n01i03206 - Procedure ENDLINE test failed."
+        severity ERROR;
+    end read1;
+
+  BEGIN
+    write1;
+    wait for 10 ns;
+    read1;
+    wait;
+  END PROCESS TESTING;
+
+END c14s03b00x00p60n01i03206arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc322.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc322.vhd
new file mode 100644
index 0000000..47e9140
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc322.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc322.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p04n01i00322ent IS
+END c03s02b01x00p04n01i00322ent;
+
+ARCHITECTURE c03s02b01x00p04n01i00322arch OF c03s02b01x00p04n01i00322ent IS
+  type bit_vctor is array (0 to 7) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(0 to 7) := "11110000";
+    assert NOT(k(0 to 7)="11110000")
+      report "***PASSED TEST: c03s02b01x00p04n01i00322"
+      severity NOTE;
+    assert ( k(0 to 7)="11110000" )
+      report "***FAILED TEST: c03s02b01x00p04n01i00322 - In the constrainted array definition, the reserved word array is followed by an index constraint and the reserved word if."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p04n01i00322arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc323.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc323.vhd
new file mode 100644
index 0000000..eb99b87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc323.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc323.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p04n01i00323ent IS
+END c03s02b01x00p04n01i00323ent;
+
+ARCHITECTURE c03s02b01x00p04n01i00323arch OF c03s02b01x00p04n01i00323ent IS
+  type bit_vctor is array (14 downto 7) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(14 downto 7) :="11110000";
+    assert NOT(k(14 downto 7)="11110000")
+      report "***PASSED TEST: c03s02b01x00p04n01i00323"
+      severity NOTE;
+    assert ( k(14 downto 7)="11110000" )
+      report "***FAILED TEST: c03s02b01x00p04n01i00323 - In the constrainted array definition, the reserved word array is followed by an index constraint and the reserved word if."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p04n01i00323arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc326.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc326.vhd
new file mode 100644
index 0000000..c9a18d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc326.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc326.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p04n01i00326ent IS
+END c03s02b01x00p04n01i00326ent;
+
+ARCHITECTURE c03s02b01x00p04n01i00326arch OF c03s02b01x00p04n01i00326ent IS
+  type rec_type is
+    record
+      x : integer;
+      y : real;
+      z : boolean;
+      b : bit;
+    end record;
+
+  type array_type is array (1 to 10) of rec_type;  -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : array_type;
+  BEGIN
+    k(1).x := 5;
+    k(1).y := 1.0;
+    k(1).z := true;
+    k(1).b := '1';
+    assert NOT(k(1).x=5 and k(1).y=1.0 and k(1).z=true and k(1).b='1') 
+      report "***PASSED TEST: c03s02b01x00p04n01i00326"
+      severity NOTE;
+    assert (k(1).x=5 and k(1).y=1.0 and k(1).z=true and k(1).b='1') 
+      report "***FAILED TEST: c03s02b01x00p04n01i00326 - The index constraint is not valid." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p04n01i00326arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc33.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc33.vhd
new file mode 100644
index 0000000..ce97d61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc33.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc33.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p01n01i00033ent IS
+END c04s03b01x01p01n01i00033ent;
+
+ARCHITECTURE c04s03b01x01p01n01i00033arch OF c04s03b01x01p01n01i00033ent IS
+  constant  INDEX : integer range 0 to 99 := 0;   --No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( INDEX = 0 )
+      report "***PASSED TEST:c04s03b01x01p01n01i00033"      severity NOTE;
+    assert ( INDEX = 0 )
+      report "***FAILED TEST: c04s03b01x01p01n01i00033 - A constant declares a constant of the specified type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p01n01i00033arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc333.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc333.vhd
new file mode 100644
index 0000000..938d916
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc333.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc333.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p06n01i00333ent IS
+END c03s02b01x00p06n01i00333ent;
+
+ARCHITECTURE c03s02b01x00p06n01i00333arch OF c03s02b01x00p06n01i00333ent IS
+  type bit_vctor is array (1 to 8, 1 to 8) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k :bit_vctor;
+  BEGIN
+    k(1,8) := 56;
+    assert NOT(k(1,8)=56) 
+      report "***PASSED TEST: c03s02b01x00p06n01i00333"
+      severity NOTE;
+    assert (k(1,8)=56) 
+      report "***FAILED TEST: c03s02b01x00p06n01i00333 - The index constraint is a list of discrete ranges enclosed within parentheses." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p06n01i00333arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc334.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc334.vhd
new file mode 100644
index 0000000..5fe1047
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc334.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc334.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p06n01i00334ent IS
+END c03s02b01x00p06n01i00334ent;
+
+ARCHITECTURE c03s02b01x00p06n01i00334arch OF c03s02b01x00p06n01i00334ent IS
+  type bit_vctor is array (1 to 8, 8 downto 1) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k :bit_vctor;
+  BEGIN
+    k(1,8) := 56;
+    assert NOT(k(1,8)=56) 
+      report "***PASSED TEST: c03s02b01x00p06n01i00334" 
+      severity NOTE;
+    assert (k(1,8)=56) 
+      report "***FAILED TEST: c03s02b01x00p06n01i00334 - The index constraint is a list of discrete ranges enclosed within parentheses." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p06n01i00334arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc335.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc335.vhd
new file mode 100644
index 0000000..88a3552
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc335.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc335.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p06n01i00335ent IS
+END c03s02b01x00p06n01i00335ent;
+
+ARCHITECTURE c03s02b01x00p06n01i00335arch OF c03s02b01x00p06n01i00335ent IS
+  type bit_vctor is array (1 to 1) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k :bit_vctor;
+  BEGIN
+    k(1) := 56;
+    assert NOT(k(1)=56) 
+      report "***PASSED TEST: c03s02b01x00p06n01i00335" 
+      severity NOTE;
+    assert (k(1)=56) 
+      report "***FAILED TEST: c03s02b01x00p06n01i00335 - The index constraint is a list of discrete ranges enclosed within parentheses." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p06n01i00335arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc337.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc337.vhd
new file mode 100644
index 0000000..c08b3e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc337.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc337.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p07n01i00337ent IS
+END c03s02b01x00p07n01i00337ent;
+
+ARCHITECTURE c03s02b01x00p07n01i00337arch OF c03s02b01x00p07n01i00337ent IS
+  type bit_vctor is array (positive range 1 to 8) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(1 to 8) := "11110000";
+    assert NOT(k(1 to 8) = "11110000")
+      report "***PASSED TEST: c03s02b01x00p07n01i00337"
+      severity NOTE;
+    assert (k(1 to 8) = "11110000")
+      report "***FAILED TEST: c03s02b01x00p07n01i00337 - The discrete ranges must be either a discrete subtype indication or a range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p07n01i00337arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc339.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc339.vhd
new file mode 100644
index 0000000..ec5941c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc339.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc339.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p07n01i00339ent IS
+END c03s02b01x00p07n01i00339ent;
+
+ARCHITECTURE c03s02b01x00p07n01i00339arch OF c03s02b01x00p07n01i00339ent IS
+  type one is array (integer range 1 to 10) of bit;
+  type two is array (1 to 10, bit range '0' to '1') of bit;
+  type three is array (1 to 10, bit range '0' to '1', character) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : one;
+  BEGIN
+    k(5) := '1';
+    assert NOT(k(5) = '1') 
+      report "***PASSED TEST: c03s02b01x00p07n01i00339" 
+      severity NOTE;
+    assert (k(5)='1') 
+      report "***FAILED TEST: c03s02b01x00p07n01i00339 - The discrete range is neither a valid discrete subtype indication nor a valid range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p07n01i00339arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc341.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc341.vhd
new file mode 100644
index 0000000..51d4c86
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc341.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc341.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p09n02i00341ent IS
+END c03s02b01x00p09n02i00341ent;
+
+ARCHITECTURE c03s02b01x00p09n02i00341arch OF c03s02b01x00p09n02i00341ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       T_A1_S       is ARRAY(INTEGER range <>) of INTEGER;
+    subtype    ST_A1_S    is T_A1_S(INTEGER range 1 to 3);
+    type       T_A1_A1_S    is ARRAY(INTEGER range <>) of ST_A1_S;
+    subtype    ST_A1_A1_S    is T_A1_A1_S(INTEGER range 6 downto 4);
+
+    variable V_A1_A1_S    : ST_A1_A1_S;
+  BEGIN
+    V_A1_A1_S(6)(1) := 61;
+    V_A1_A1_S(6)(2) := 62;
+    V_A1_A1_S(6)(3) := 63;
+    V_A1_A1_S(5)(1) := 51;
+    V_A1_A1_S(5)(2) := 52;
+    V_A1_A1_S(5)(3) := 53;
+    V_A1_A1_S(4)(1) := 41;
+    V_A1_A1_S(4)(2) := 42;
+    V_A1_A1_S(4)(3) := 43;
+    wait for 5 ns;
+    assert NOT(    V_A1_A1_S(6)(1) = 61   and
+                   V_A1_A1_S(6)(2) = 62   and
+                   V_A1_A1_S(6)(3) = 63   and
+                   V_A1_A1_S(5)(1) = 51   and
+                   V_A1_A1_S(5)(2) = 52   and
+                   V_A1_A1_S(5)(3) = 53   and
+                   V_A1_A1_S(4)(1) = 41   and
+                   V_A1_A1_S(4)(2) = 42   and
+                   V_A1_A1_S(4)(3) = 43)
+      report "***PASSED TEST: c03s02b01x00p09n02i00341"
+      severity NOTE;
+    assert (    V_A1_A1_S(6)(1) = 61   and
+                V_A1_A1_S(6)(2) = 62   and
+                V_A1_A1_S(6)(3) = 63   and
+                V_A1_A1_S(5)(1) = 51   and
+                V_A1_A1_S(5)(2) = 52   and
+                V_A1_A1_S(5)(3) = 53   and
+                V_A1_A1_S(4)(1) = 41   and
+                V_A1_A1_S(4)(2) = 42   and
+                V_A1_A1_S(4)(3) = 43)
+      report "***FAILED TEST: c03s02b01x00p09n02i00341 - For each possible sequence of index values that can be formed by selecting one value for each index for a multimensioal array, there is a distinct element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p09n02i00341arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc343.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc343.vhd
new file mode 100644
index 0000000..8177b1a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc343.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc343.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p09n03i00343ent IS
+END c03s02b01x00p09n03i00343ent;
+
+ARCHITECTURE c03s02b01x00p09n03i00343arch OF c03s02b01x00p09n03i00343ent IS
+  type M1 is array (1 to 4) of BIT;
+  signal X1 : M1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X1(1) <= '0' after 10 ns;
+    X1(2) <= '1' after 20 ns;
+    X1(3) <= '1' after 30 ns;
+    X1(4) <= '0' after 40 ns;   -- No_failure_here
+    wait for 50 ns;
+    assert NOT(X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
+      report "***PASSED TEST: c03s02b01x00p09n03i00343"
+      severity NOTE;
+    assert (X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0')
+      report "***FAILED TEST: c03s02b01x00p09n03i00343 - The values in the given index range are not the values that belong to the corresponding range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p09n03i00343arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc344.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc344.vhd
new file mode 100644
index 0000000..0ab8da6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc344.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc344.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p09n01i00344ent IS
+END c03s02b01x00p09n01i00344ent;
+
+ARCHITECTURE c03s02b01x00p09n01i00344arch OF c03s02b01x00p09n01i00344ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       T_A1_S       is ARRAY(INTEGER range <>) of INTEGER;
+    subtype    ST_A1_S    is T_A1_S(INTEGER range 1 to 3);
+
+    variable    V_A1_S       : ST_A1_S;
+  BEGIN
+    V_A1_S(1) := 11;
+    V_A1_S(2) := 22;
+    V_A1_S(3) := 33;
+    wait for 5 ns;
+    assert NOT(   V_A1_S(1) = 11   and
+                  V_A1_S(2) = 22   and
+                  V_A1_S(3) = 33   )
+      report "***PASSED TEST: c03s02b01x00p09n01i00344"
+      severity NOTE;
+    assert (   V_A1_S(1) = 11   and
+               V_A1_S(2) = 22   and
+               V_A1_S(3) = 33   )
+      report "***FAILED TEST: c03s02b01x00p09n01i00344 - For each possible index value there should be a distinct element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p09n01i00344arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc346.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc346.vhd
new file mode 100644
index 0000000..f76562e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc346.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc346.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p10n05i00346ent IS
+END c03s02b01x00p10n05i00346ent;
+
+ARCHITECTURE c03s02b01x00p10n05i00346arch OF c03s02b01x00p10n05i00346ent IS
+  type MEM is array(INTEGER range <>) of BIT;
+BEGIN
+  TESTING: PROCESS
+    variable S1 : MEM(1 to 5);
+    variable S2 : MEM(28 downto 7);
+  BEGIN
+    S1(1 to 5) := "11111";
+    S2(28 downto 21) := "00001111";
+    assert NOT(S1(1 to 5) = "11111" and S2(28 downto 21)= "00001111")
+      report "***PASSED TEST: c03s02b01x00p10n05i00346"
+      severity NOTE;
+    assert (S1(1 to 5) = "11111" and S2(28 downto 21)= "00001111")
+      report "***FAILED TEST: c03s02b01x00p10n05i00346 - Different objects of the same unconstrained array type can have different bounds and direction."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p10n05i00346arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc347.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc347.vhd
new file mode 100644
index 0000000..a3e9dbd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc347.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc347.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p15n01i00347ent IS
+END c03s02b01x00p15n01i00347ent;
+
+ARCHITECTURE c03s02b01x00p15n01i00347arch OF c03s02b01x00p15n01i00347ent IS
+  type MEM is array(5 downto 0) of BIT;  -- No_failure_here
+  signal S1 : MEM := "000000";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(S1(4 downto 3) = "00")
+      report "***PASSED TEST: c03s02b01x00p15n01i00347"
+      severity NOTE;
+    assert (S1(4 downto 3) = "00")
+      report "***FAILED TEST: c03s02b01x00p15n01i00347 - The direction of the discrete range is the same as the direction of the range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p15n01i00347arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc349.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc349.vhd
new file mode 100644
index 0000000..e5edda9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc349.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc349.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p01n01i00349ent IS
+  type atest is array(1 to 20) of bit;
+END c03s02b01x01p01n01i00349ent;
+
+ARCHITECTURE c03s02b01x01p01n01i00349arch OF c03s02b01x01p01n01i00349ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a : integer := 0;
+  BEGIN
+    a:=atest'length;
+    assert NOT( a=20 )
+      report "***PASSED TEST: c03s02b01x01p01n01i00349"
+      severity NOTE;
+    assert ( a=20 )
+      report "***FAILED TEST: c03s02b01x01p01n01i00349 - Array length is not equal the declared array range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p01n01i00349arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc35.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc35.vhd
new file mode 100644
index 0000000..26dbcc5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc35.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc35.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p01n01i00035ent IS
+END c04s03b01x01p01n01i00035ent;
+
+ARCHITECTURE c04s03b01x01p01n01i00035arch OF c04s03b01x01p01n01i00035ent IS
+  type large is range 0 to 2_000_000_000      --   < 2**31-1
+    units
+      sbu; 
+      lbu = 2000000000 sbu;
+    end units;
+  constant   SC : large := sbu;
+  constant   LC : large := lbu;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( LC = 2000000000 * SC )
+      report "***PASSED TEST: c04s03b01x01p01n01i00035"
+      severity NOTE;
+    assert ( LC = 2000000000 * SC )
+      report "***FAILED TEST: c04s03b01x01p01n01i00035 - Large physical type declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p01n01i00035arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc350.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc350.vhd
new file mode 100644
index 0000000..1873354
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc350.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc350.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p01n01i00350ent IS
+END c03s02b01x01p01n01i00350ent;
+
+ARCHITECTURE c03s02b01x01p01n01i00350arch OF c03s02b01x01p01n01i00350ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    V1 :    STRING(1 to 20);
+    subtype    ST is    STRING(1 to 10);
+    variable    V2 :    ST;
+  BEGIN
+    assert V1'LEFT    = 1;
+    assert V1'RIGHT = 20;
+    assert ST'LEFT    = 1;
+    assert ST'RIGHT = 10;
+    assert V2'LEFT    = 1;
+    assert V2'RIGHT = 10;
+    assert NOT(     V1'LEFT  = 1    and
+                    V1'RIGHT = 20   and
+                    ST'LEFT  = 1   and
+                    ST'RIGHT = 10   and
+                    V2'LEFT  = 1   and
+                    V2'RIGHT = 10   )
+      report "***PASSED TEST: c03s02b01x01p01n01i00350"
+      severity NOTE;
+    assert (     V1'LEFT  = 1    and
+                 V1'RIGHT = 20   and
+                 ST'LEFT  = 1   and
+                 ST'RIGHT = 10   and
+                 V2'LEFT  = 1   and
+                 V2'RIGHT = 10   )
+      report "***FAILED TEST: c03s02b01x01p01n01i00350 - Index constraint test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p01n01i00350arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc351.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc351.vhd
new file mode 100644
index 0000000..f9f02ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc351.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc351.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00351ent IS
+END c03s02b01x01p02n01i00351ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00351arch OF c03s02b01x01p02n01i00351ent IS
+  type bit_vctor is array (-1 to 8) of integer;  --Expect_success
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(5) := 5;
+    assert NOT(k(5)=5) 
+      report "***PASSED TEST: c03s02b01x01p02n01i00351" 
+      severity NOTE;
+    assert (k(5)=5) 
+      report "***FAILED TEST: c03s02b01x01p02n01i00351 - An implicit conversion to the predefined type INTEGER is assumed if each bound is either a numeric literal or an attribute, and the type of both bounds(prior to implicit conversion) is the type universal_integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00351arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc355.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc355.vhd
new file mode 100644
index 0000000..786dbfe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc355.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc355.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00355ent IS
+END c03s02b01x01p02n01i00355ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00355arch OF c03s02b01x01p02n01i00355ent IS
+  type bit_vctor is array (-1 to 8) of integer;  --Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(-1) := 5;
+    assert NOT(k(-1)=5) 
+      report "***PASSED TEST: c03s02b01x01p02n01i00355" 
+      severity NOTE;
+    assert (k(-1)=5) 
+      report "***FAILED TEST: c03s02b01x01p02n01i00355 - Both bounds in the constrained array definition must have the same discrete type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00355arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc359.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc359.vhd
new file mode 100644
index 0000000..f1b1386
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc359.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc359.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00359ent IS
+END c03s02b01x01p02n01i00359ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00359arch OF c03s02b01x01p02n01i00359ent IS
+  type sense is (hear, touch, smell, see);
+  type page is array (hear to see) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : page;
+  BEGIN
+    k(hear)   := '0';
+    k(touch):= '1';
+    k(smell):= '0';
+    k(see)  := '1';
+    wait for 2 ns;
+    assert NOT(   k(hear) = '0' and 
+                  k(touch)= '1' and 
+                  k(smell)= '0' and
+                  k(see)  = '1') 
+      report "***PASSED TEST: c03s02b01x01p02n01i00359" 
+      severity NOTE;
+    assert (   k(hear) = '0' and 
+               k(touch)= '1' and 
+               k(smell)= '0' and
+               k(see)  = '1') 
+      report "***FAILED TEST: c03s02b01x01p02n01i00359 - Bounds are of different discrete types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00359arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc36.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc36.vhd
new file mode 100644
index 0000000..36c1eec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc36.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc36.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00036ent IS
+END c04s03b01x01p02n01i00036ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00036arch OF c04s03b01x01p02n01i00036ent IS
+  constant a  : positive := 1;              -- No_failure_here
+  constant b  : natural  := 1;              -- No_failure_here
+  constant a1 : positive := a + 1;          -- No_failure_here
+  constant a2 : positive := a + a;          -- No_failure_here
+  constant a3 : positive := a * (a/a + 1);  -- No_failure_here
+  constant b1 : natural  := b + 1;          -- No_failure_here
+  constant b2 : natural  := b + b;          -- No_failure_here
+  constant b3 : natural  := b * (b/b + 1);  -- No_failure_here
+  constant b4 : natural  := b - b;          -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    a   = 1   and
+                   b   = 1   and
+                   a1   = 2   and
+                   a2   = 2   and
+                   a3   = 2   and
+                   b1   = 2   and
+                   b2   = 2   and
+                   b3   = 2   and
+                   b4   = 0   )
+      report "***PASSED TEST: c04s03b01x01p02n01i00036"
+      severity NOTE;
+    assert (    a   = 1   and
+                b   = 1   and
+                a1   = 2   and
+                a2   = 2   and
+                a3   = 2   and
+                b1   = 2   and
+                b2   = 2   and
+                b3   = 2   and
+                b4   = 0   )
+      report "***FAILED TEST: c04s03b01x01p02n01i00036 - Constant declaration syntactic format test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00036arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc361.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc361.vhd
new file mode 100644
index 0000000..48a0e28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc361.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc361.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00361ent IS
+END c03s02b01x01p02n01i00361ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00361arch OF c03s02b01x01p02n01i00361ent IS
+  type MVL1 is ('0', '1');
+  type MVL2 is ('X', 'Z');
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for I in MVL1'POS('0') to MVL2'POS('Z') loop  -- No_failure_here
+      k := k + 1;
+    end loop;
+    assert NOT(k=2) 
+      report "***PASSED TEST: c03s02b01x01p02n01i00361" 
+      severity NOTE;
+    assert (k=2) 
+      report "***FAILED TEST: c03s02b01x01p02n01i00361 - Both bounds in the constrained array definition must have the same discrete type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00361arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc364.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc364.vhd
new file mode 100644
index 0000000..7c92198
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc364.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc364.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n01i00364ent IS
+END c03s02b01x01p03n01i00364ent;
+
+ARCHITECTURE c03s02b01x01p03n01i00364arch OF c03s02b01x01p03n01i00364ent IS
+  subtype    decade is integer;
+  type       MVL_vector is array (positive range 1 to 50) of decade range 2 to 5;
+BEGIN
+  TESTING: PROCESS
+    variable k : MVL_vector;
+  BEGIN
+    k(1)  := 2;
+    k(50) := 5;
+    assert NOT (k(1)=2 and k(50)=5) 
+      report "***PASSED TEST: c03s02b01x01p03n01i00364" 
+      severity NOTE;
+    assert (k(1)=2 and k(50)=5) 
+      report "***FAILED TEST: c03s02b01x01p03n01i00364 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n01i00364arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc365.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc365.vhd
new file mode 100644
index 0000000..4694654
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc365.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc365.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n01i00365ent IS
+END c03s02b01x01p03n01i00365ent;
+
+ARCHITECTURE c03s02b01x01p03n01i00365arch OF c03s02b01x01p03n01i00365ent IS
+  subtype decade is integer;
+  type MVL_vector is array (decade range 1 to 50) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k : MVL_vector;
+  BEGIN
+    k(1)  := 2;
+    k(50) := 5;
+    assert NOT (k(1)=2 and k(50)=5) 
+      report "***PASSED TEST: c03s02b01x01p03n01i00365" 
+      severity NOTE;
+    assert (k(1)=2 and k(50)=5) 
+      report "***FAILED TEST: c03s02b01x01p03n01i00365 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n01i00365arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc366.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc366.vhd
new file mode 100644
index 0000000..e0a7c54
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc366.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc366.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n01i00366ent IS
+END c03s02b01x01p03n01i00366ent;
+
+ARCHITECTURE c03s02b01x01p03n01i00366arch OF c03s02b01x01p03n01i00366ent IS
+  type MVL is ('0', '1', 'Z') ;
+  type tribit is array (natural range <>) of MVL;
+  subtype word is tribit (0 to 16); -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : word;
+  BEGIN
+    k(0)  := '0';
+    k(16) := 'Z';
+    assert NOT (k(0)='0' and k(16)='Z') 
+      report "***PASSED TEST: c03s02b01x01p03n01i00366" 
+      severity NOTE;
+    assert (k(0)='0' and k(16)='Z') 
+      report "***FAILED TEST: c03s02b01x01p03n01i00366 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n01i00366arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc37.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc37.vhd
new file mode 100644
index 0000000..fa011ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc37.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc37.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00037ent IS
+END c04s03b01x01p02n01i00037ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00037arch OF c04s03b01x01p02n01i00037ent IS
+  constant C1 : Boolean   := true; -- No_failure_here
+  constant C2 : bit       := '0';  -- No_failure_here
+  constant C3 : integer   := 123;  -- No_failure_here
+  constant C4 : positive  := 34;   -- No_failure_here
+  constant C5 : natural   := 12;   -- No_failure_here
+  constant C6 : real      := 1.20; -- No_failure_here
+  constant C7 : character := 'C';  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    C1   = true   and
+                   C2   = '0'   and
+                   C3   = 123   and
+                   C4   = 34   and
+                   C5   = 12   and
+                   C6   = 1.20   and
+                   C7   = 'C'   )   
+      report "***PASSED TEST: c04s03b01x01p02n01i00037"
+      severity NOTE;
+    assert (    C1   = true   and
+                C2   = '0'   and
+                C3   = 123   and
+                C4   = 34   and
+                C5   = 12   and
+                C6   = 1.20   and
+                C7   = 'C'   )   
+      report "***FAILED TEST: c04s03b01x01p02n01i00037 - Constant declaration syntactic format test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00037arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc376.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc376.vhd
new file mode 100644
index 0000000..d33bd8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc376.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc376.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n03i00376ent IS
+END c03s02b01x01p03n03i00376ent;
+
+ARCHITECTURE c03s02b01x01p03n03i00376arch OF c03s02b01x01p03n03i00376ent IS
+  type my_word is array (0 to 3) of bit;
+  type it     is array (integer range my_word'range) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable itt : it;
+  BEGIN
+    assert NOT(itt(0)='0' and itt(1)='0' and itt(2)='0' and itt(3)='0') 
+      report "***PASSED TEST: c03s02b01x01p03n03i00376" 
+      severity NOTE;
+    assert (itt(0)='0' and itt(1)='0' and itt(2)='0' and itt(3)='0') 
+      report "***FAILED TEST: c03s02b01x01p03n03i00376 - The index constraint must provide a discrete range for each index of the array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n03i00376arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc377.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc377.vhd
new file mode 100644
index 0000000..13af3f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc377.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc377.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n03i00377ent IS
+END c03s02b01x01p03n03i00377ent;
+
+ARCHITECTURE c03s02b01x01p03n03i00377arch OF c03s02b01x01p03n03i00377ent IS
+  type it2 is array (bit range '0' to '1') of bit;
+BEGIN
+  TESTING: PROCESS
+    variable k : it2;
+  BEGIN
+    k('0') := '1';
+    k('1') := '0';
+    assert NOT (   k('0') = '1' and 
+                   k('1') = '0') 
+      report "***PASSED TEST: c03s02b01x01p03n03i00377" 
+      severity NOTE;
+    assert  (   k('0') = '1' and 
+                k('1') = '0') 
+      report "***FAILED TEST: c03s02b01x01p03n03i00377 - The index constraint must provide a discrete range for each index of the array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n03i00377arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc378.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc378.vhd
new file mode 100644
index 0000000..1204064
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc378.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc378.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n03i00378ent IS
+END c03s02b01x01p03n03i00378ent;
+
+ARCHITECTURE c03s02b01x01p03n03i00378arch OF c03s02b01x01p03n03i00378ent IS
+  type       M1 is array (positive range <>) of integer;
+  subtype    M2 is M1 (2 to 200);    -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+    variable k : M2;
+  BEGIN
+    k(2)   := 2;
+    k(200) := 200;
+    assert NOT (   k(2) = 2 and 
+                   k(200) = 200) 
+      report "***PASSED TEST: c03s02b01x01p03n03i00378"
+      severity NOTE;
+    assert  (   k(2) = 2 and 
+                k(200) = 200) 
+      report "***FAILED TEST: c03s02b01x01p03n03i00378 - The index constraint must provide a discrete range for each index of the array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n03i00378arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc38.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc38.vhd
new file mode 100644
index 0000000..e316b8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc38.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc38.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00038ent IS
+END c04s03b01x01p02n01i00038ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00038arch OF c04s03b01x01p02n01i00038ent IS
+  constant C1 : Boolean := ( (2 >= 1) or ( (1 <= 10) and (2 = 1 + 1) ) );
+                                        -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( C1 = true )
+      report "***PASSED TEST: c04s03b01x01p02n01i00038"
+      severity NOTE;
+    assert ( C1 = true )
+      report "***FAILED TEST: c04s03b01x01p02n01i00038 - A complex expression assigned to the constant test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00038arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc381.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc381.vhd
new file mode 100644
index 0000000..cc0812a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc381.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc381.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n01i00381ent IS
+END c03s02b01x01p04n01i00381ent;
+
+ARCHITECTURE c03s02b01x01p04n01i00381arch OF c03s02b01x01p04n01i00381ent IS
+  type bit_vctor is array (bit range '0' to '1') of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k('0') := 1;
+    k('1') := 0;
+    assert NOT (k('0') = 1 and
+                k('1') = 0 ) 
+      report "***PASSED TEST: c03s02b01x01p04n01i00381" 
+      severity NOTE;
+    assert     (k('0') = 1 and
+                k('1') = 0 ) 
+      report "***FAILED TEST: c03s02b01x01p04n01i00381 - An index constraint is compatible with the type denoted by the type mark if and only if the constraint defined by each discrete range is compatible with the corresponding subtype." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n01i00381arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc382.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc382.vhd
new file mode 100644
index 0000000..2bd6790
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc382.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc382.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n01i00382ent IS
+END c03s02b01x01p04n01i00382ent;
+
+ARCHITECTURE c03s02b01x01p04n01i00382arch OF c03s02b01x01p04n01i00382ent IS
+  type days is (sun, mon, tue, wed, thu, fri, sat);
+  type bit_vctor is array (days range mon to fri) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vctor;
+  BEGIN
+    k(mon) := 1;
+    k(tue) := 2;
+    k(wed) := 3;
+    k(thu) := 4;
+    k(fri) := 5;
+    assert NOT (   k(mon) = 1 and 
+                   k(tue) = 2 and
+                   k(wed) = 3 and 
+                   k(thu) = 4 and 
+                   k(fri) = 5 )
+      report "***PASSED TEST: c03s02b01x01p04n01i00382"
+      severity NOTE;
+    assert  (   k(mon) = 1 and 
+                k(tue) = 2 and
+                k(wed) = 3 and 
+                k(thu) = 4 and 
+                k(fri) = 5 )
+      report "***FAILED TEST: c03s02b01x01p04n01i00382 - An index constraint is compatible with the type denoted by the type mark if and only if the constraint defined by each discrete range is compatible with the corresponding subtype." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n01i00382arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc385.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc385.vhd
new file mode 100644
index 0000000..ea4abe9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc385.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc385.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n02i00385ent IS
+END c03s02b01x01p04n02i00385ent;
+
+ARCHITECTURE c03s02b01x01p04n02i00385arch OF c03s02b01x01p04n02i00385ent IS
+  type bit_vctor is array (10 to 7) of integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c03s02b01x01p04n02i00385"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n02i00385arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc386.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc386.vhd
new file mode 100644
index 0000000..f7766cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc386.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc386.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n02i00386ent IS
+END c03s02b01x01p04n02i00386ent;
+
+ARCHITECTURE c03s02b01x01p04n02i00386arch OF c03s02b01x01p04n02i00386ent IS
+  type bit_vctor is array (0 downto 7) of integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c03s02b01x01p04n02i00386"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n02i00386arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc387.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc387.vhd
new file mode 100644
index 0000000..70b63c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc387.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc387.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n03i00387ent IS
+END c03s02b01x01p04n03i00387ent;
+
+ARCHITECTURE c03s02b01x01p04n03i00387arch OF c03s02b01x01p04n03i00387ent IS
+  type M1 is array (positive range 1 to 5) of integer;
+  signal S1 : M1 := (1,2,3,4,5); -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(S1(1)=1 and
+               S1(2)=2 and
+               S1(3)=3 and
+               S1(4)=4 and
+               S1(5)=5 )
+      report "***PASSED TEST: c03s02b01x01p04n03i00387"
+      severity NOTE;
+    assert (   S1(1)=1 and
+               S1(2)=2 and
+               S1(3)=3 and
+               S1(4)=4 and
+               S1(5)=5 )
+      report "***FAILED TEST: c03s02b01x01p04n03i00387 - An array value staisfies an index constraint if at each index position the array value and the index constrint have the same index range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n03i00387arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc388.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc388.vhd
new file mode 100644
index 0000000..f57f55c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc388.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc388.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n03i00388ent IS
+END c03s02b01x01p04n03i00388ent;
+
+ARCHITECTURE c03s02b01x01p04n03i00388arch OF c03s02b01x01p04n03i00388ent IS
+  type SQ_ARR is array(0 to 1, 0 to 2) of BIT;
+BEGIN
+  TESTING: PROCESS
+    variable M2 :  SQ_ARR :=  (('0','1','1'),('1','0','0')); -- No_failure_here
+  BEGIN
+    assert NOT(    M2(0,0)='0' and
+                   M2(0,1)='1' and
+                   M2(0,2)='1' and
+                   M2(1,0)='1' and
+                   M2(1,1)='0' and
+                   M2(1,2)='0')   
+      report "***PASSED TEST: c03s02b01x01p04n03i00388"
+      severity NOTE;
+    assert (    M2(0,0)='0' and
+                M2(0,1)='1' and
+                M2(0,2)='1' and
+                M2(1,0)='1' and
+                M2(1,1)='0' and
+                M2(1,2)='0')   
+      report "***FAILED TEST: c03s02b01x01p04n03i00388 - An array value staisfies an index constraint if at each index position the array value and the index constrint have the same index range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n03i00388arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc39.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc39.vhd
new file mode 100644
index 0000000..2b55041
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc39.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc39.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00039ent IS
+END c04s03b01x01p02n01i00039ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00039arch OF c04s03b01x01p02n01i00039ent IS
+  constant C1 : Boolean := 10 = 10;    -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( C1 = true )
+      report "***PASSED TEST: c04s03b01x01p02n01i00039"
+      severity NOTE;
+    assert ( C1 = true )
+      report "***FAILED TEST: c04s03b01x01p02n01i00039 - A boolean expression assigned to the constant test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00039arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc392.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc392.vhd
new file mode 100644
index 0000000..3f61c4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc392.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc392.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n01i00392ent IS
+END c03s02b01x01p06n01i00392ent;
+
+ARCHITECTURE c03s02b01x01p06n01i00392arch OF c03s02b01x01p06n01i00392ent IS
+  type   M1 is array (positive range <>) of integer;
+  signal S1 : M1(3 to 30) ; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1(3)  <= 3  after 3 ns;
+    S1(30) <= 30 after 3 ns;
+    wait for 10 ns;
+    assert NOT(S1(3)=3 and S1(30)=30) 
+      report "***PASSED TEST: c03s02b01x01p06n01i00392" 
+      severity NOTE;
+    assert (S1(3)=3 and S1(30)=30) 
+      report "***FAILED TEST: c03s02b01x01p06n01i00392 - Subtype indication of array object declaration must denote a constrained array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n01i00392arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc393.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc393.vhd
new file mode 100644
index 0000000..570bedf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc393.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc393.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n01i00393ent IS
+END c03s02b01x01p06n01i00393ent;
+
+ARCHITECTURE c03s02b01x01p06n01i00393arch OF c03s02b01x01p06n01i00393ent IS
+  type   M1 is array (positive range <>) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : M1(4 to 10) ;  -- No_failure_here
+  BEGIN
+    V1(4)   := 4;
+    V1(10)   := 10;
+    assert NOT(V1(4)=4 and V1(10)=10)
+      report "***PASSED TEST: c03s02b01x01p06n01i00393" 
+      severity NOTE;
+    assert (V1(4)=4 and V1(10)=10)
+      report "***FAILED TEST: c03s02b01x01p06n01i00393 - Subtype indication of array object declaration must denote a constrained array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n01i00393arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc395.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc395.vhd
new file mode 100644
index 0000000..46acb77
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc395.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc395.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n02i00395ent IS
+END c03s02b01x01p06n02i00395ent;
+
+ARCHITECTURE c03s02b01x01p06n02i00395arch OF c03s02b01x01p06n02i00395ent IS
+  type A1 is array (positive range 1 to 2) of BOOLEAN;
+
+  type R1 is record
+               RE1: A1;  -- no_failure_here
+             end record;
+BEGIN
+  TESTING: PROCESS
+    variable k : R1;
+  BEGIN
+    k.RE1(1) := TRUE;
+    k.RE1(2) := FALSE;
+    assert NOT(    k.RE1(1) = TRUE and 
+                   k.RE1(2) = FALSE )
+      report "***PASSED TEST: c03s02b01x01p06n02i00395"
+      severity NOTE;
+    assert (    k.RE1(1) = TRUE and 
+                k.RE1(2) = FALSE )
+      report "***FAILED TEST: c03s02b01x01p06n02i00395 - Record element cannot be an unconstrained array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n02i00395arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc397.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc397.vhd
new file mode 100644
index 0000000..1eedb7c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc397.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc397.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n02i00397ent IS
+END c03s02b01x01p06n02i00397ent;
+
+ARCHITECTURE c03s02b01x01p06n02i00397arch OF c03s02b01x01p06n02i00397ent IS
+  type I1 is range 1 to 5;
+  type M1 is array (positive range 1 to 6) of integer;
+  type M2 is array (I1'(1) to I1'(2)) of M1; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+    variable k : M2;
+  BEGIN
+    k(1) := (1,2,3,4,5,6);
+    k(2) := (7,8,9,10,11,12);
+    assert NOT(k(1)=(1,2,3,4,5,6) and k(2)=(7,8,9,10,11,12)) 
+      report "***PASSED TEST: c03s02b01x01p06n02i00397" 
+      severity NOTE;
+    assert (k(1)=(1,2,3,4,5,6) and k(2)=(7,8,9,10,11,12)) 
+      report "***FAILED TEST: c03s02b01x01p06n02i00397 - Array element cannot be an unconstrained array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n02i00397arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc398.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc398.vhd
new file mode 100644
index 0000000..8ec5644
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc398.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc398.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p07n01i00398ent IS
+END c03s02b01x01p07n01i00398ent;
+
+ARCHITECTURE c03s02b01x01p07n01i00398arch OF c03s02b01x01p07n01i00398ent IS
+  constant X : BIT_VECTOR := "0101";
+BEGIN
+  TESTING: PROCESS
+    variable i : integer;
+  BEGIN
+    i   := X'length;
+    assert NOT(i=4)
+      report "***PASSED TEST: c03s02b01x01p07n01i00398"
+      severity NOTE;
+    assert (i=4)
+      report "***FAILED TEST: c03s02b01x01p07n01i00398 - For a constant declared by an object declaration, the index ranges are defined by the initial value, if the subtype of the constant is unconstrained."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p07n01i00398arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc399.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc399.vhd
new file mode 100644
index 0000000..b41f7d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc399.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc399.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p07n01i00399ent IS
+END c03s02b01x01p07n01i00399ent;
+
+ARCHITECTURE c03s02b01x01p07n01i00399arch OF c03s02b01x01p07n01i00399ent IS
+  constant X : BIT_VECTOR(0 to 3) := "0101";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(X(0)='0' and X(1)='1' and X(2)='0' and X(3)='1')
+      report "***PASSED TEST: c03s02b01x01p07n01i00399"
+      severity NOTE;
+    assert (X(0)='0' and X(1)='1' and X(2)='0' and X(3)='1')
+      report "***FAILED TEST: c03s02b01x01p07n01i00399 - For a constant declared by an object declaration, the index ranges are defined by the initial value, if the subtype of the constant is unconstrained."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p07n01i00399arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc40.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc40.vhd
new file mode 100644
index 0000000..f273bdd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc40.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc40.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00040ent IS
+END c04s03b01x01p02n01i00040ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00040arch OF c04s03b01x01p02n01i00040ent IS
+  constant C1 : Real := ( (1.23 + 1.45) - (6.04 - 5.99) + ((2.4) / (1.2)) );
+                                        -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( C1 = 4.63 )
+      report "***PASSED TEST: c04s03b01x01p02n01i00040"
+      severity NOTE;
+    assert ( C1 = 4.63 )
+      report "***FAILED TEST: c04s03b01x01p02n01i00040- A complex real expression assigned to the real constant test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00040arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc400.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc400.vhd
new file mode 100644
index 0000000..9fb403a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc400.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc400.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p08n01i00400ent IS
+END c03s02b01x01p08n01i00400ent;
+
+ARCHITECTURE c03s02b01x01p08n01i00400arch OF c03s02b01x01p08n01i00400ent IS
+  type       MEM is array (positive range <>) of BIT;
+  attribute    X  : MEM;
+  attribute    X of MEM: type is ('1','0','1') ; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1')
+      report "***PASSED TEST: c03s02b01x01p08n01i00400"
+      severity NOTE;
+    assert (MEM'X(1)='1' and MEM'X(2)='0' and MEM'X(3)='1')
+      report "***FAILED TEST: c03s02b01x01p08n01i00400 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p08n01i00400arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc401.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc401.vhd
new file mode 100644
index 0000000..c22b7a6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc401.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc401.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p09n01i00401ent IS
+END c03s02b01x01p09n01i00401ent;
+
+ARCHITECTURE c03s02b01x01p09n01i00401arch OF c03s02b01x01p09n01i00401ent IS
+  type MEM is array (integer range <>) of BIT;
+  type LIN is access MEM;
+BEGIN
+  TESTING: PROCESS
+    variable HD : LIN := new MEM'("000111000");   -- No_failure_here
+  BEGIN
+    assert NOT(HD.all = "000111000")
+      report "***PASSED TEST: c03s02b01x01p09n01i00401"
+      severity NOTE;
+    assert (HD.all = "000111000")
+      report "***FAILED TEST: c03s02b01x01p09n01i00401 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p09n01i00401arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc402.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc402.vhd
new file mode 100644
index 0000000..bef475b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc402.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc402.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p11n01i00402ent IS
+END c03s02b01x01p11n01i00402ent;
+
+ARCHITECTURE c03s02b01x01p11n01i00402arch OF c03s02b01x01p11n01i00402ent IS
+  function WR_OR(Input : BIT_VECTOR) return BIT is
+  begin
+    for I in Input'Range loop
+      if Input(I) = '1' then
+        return '1';
+      end if;
+    end loop;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : BIT_VECTOR(0 to 3) := "0101" ;
+    variable V2 : BIT;
+  BEGIN
+    V2 := WR_OR(V1) ;  -- No_failure_here
+    assert NOT(V2 = '1')
+      report "***PASSED TEST: c03s02b01x01p11n01i00402"
+      severity NOTE;
+    assert ( V2 = '1' )
+      report "***FAILED TEST: c03s02b01x01p11n01i00402 - For a formal parameter of a subprogram that is of an unconstrained array type, the index ranges are obtained from the corresponding association element in the applicable subprogram call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p11n01i00402arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc403.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc403.vhd
new file mode 100644
index 0000000..cb8465d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc403.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc403.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p18n01i00403ent IS
+END c03s02b01x01p18n01i00403ent;
+
+ARCHITECTURE c03s02b01x01p18n01i00403arch OF c03s02b01x01p18n01i00403ent IS
+  type MEM is array (positive range <>) of BIT;
+  type ME1 is array (natural range <>) of Integer;
+  subtype ME2 is ME1(0 to 3);
+  subtype M1 is MEM (1 to 5) ;
+  function WR_OR(Input : ME1) return M1 is
+  begin
+    for I in Input'Range loop
+      if Input(I) = 20 then
+        return "11111" ;
+      end if;
+    end loop;
+  end WR_OR;
+  procedure F2 (X1 : in MEM) is
+  begin
+    assert NOT(X1="11111")
+      report "***PASSED TEST: c03s02b01x01p18n01i00403"
+      severity NOTE;
+    assert (X1="11111")
+      report "***FAILED TEST: c03s02b01x01p18n01i00403 - "
+      severity ERROR;
+  end F2;
+BEGIN
+  TESTING: PROCESS
+    variable V1 :ME2  := (10, 20, 30, 40);
+  BEGIN
+    F2(WR_OR(V1)) ;  -- No_failure_here
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p18n01i00403arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc404.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc404.vhd
new file mode 100644
index 0000000..eda2042
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc404.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc404.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p18n01i00404ent IS
+END c03s02b01x01p18n01i00404ent;
+
+ARCHITECTURE c03s02b01x01p18n01i00404arch OF c03s02b01x01p18n01i00404ent IS
+  type MEM is array (positive range <>) of BIT;
+  type ME1 is array (natural range <>) of Integer;
+  subtype ME2 is ME1(0 to 3);
+  subtype M1 is MEM (1 to 5) ;
+  procedure F2 (X1 : in MEM) is
+  begin
+    assert NOT((X1'LOW = 1) and (X1'High = 5))
+      report "***PASSED TEST: c03s02b01x01p18n01i00404" 
+      SEVERITY NOTE;
+    assert ((X1'LOW = 1) and (X1'High = 5))
+      report "***FAILED TEST: c03s02b01x01p18n01i00404 - The index ranges are obtained from the actual designator." 
+      SEVERITY ERROR;
+  end F2;
+  signal S1 : M1 := "01110" ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    F2(S1) ;  -- No_failure_here
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p18n01i00404arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc406.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc406.vhd
new file mode 100644
index 0000000..b6a822b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc406.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc406.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT  integer := 3;
+      F2:  INOUT integer := 3;
+      F3:  IN integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00406ent IS
+END c03s02b01x01p19n01i00406ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00406arch OF c03s02b01x01p19n01i00406ent IS
+
+  constant C1 : boolean := true;
+
+  function complex_scalar(s : boolean) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT  integer;
+        F2:  INOUT integer;
+        F3:  IN integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean;
+  signal S2 : boolean;
+  signal S3 : boolean := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00406" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00406 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00406arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc407.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc407.vhd
new file mode 100644
index 0000000..9ceaa0e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc407.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc407.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT  integer := 3;
+      F2:  INOUT integer := 3;
+      F3:  IN integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00407ent IS
+END c03s02b01x01p19n01i00407ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00407arch OF c03s02b01x01p19n01i00407ent IS
+
+  constant C1 : bit := '1';
+
+  function complex_scalar(s : bit) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return bit is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT  integer;
+        F2:  INOUT integer;
+        F3:  IN integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : bit;
+  signal S2 : bit;
+  signal S3 : bit := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00407" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00407 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00407arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc408.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc408.vhd
new file mode 100644
index 0000000..766774a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc408.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc408.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT  integer := 3;
+      F2:  INOUT integer := 3;
+      F3:  IN integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00408ent IS
+END c03s02b01x01p19n01i00408ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00408arch OF c03s02b01x01p19n01i00408ent IS
+
+  constant C1 : character := 's';
+
+  function complex_scalar(s : character) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return character is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT  integer;
+        F2:  INOUT integer;
+        F3:  IN integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : character;
+  signal S2 : character;
+  signal S3 : character := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00408" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00408 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00408arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc409.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc409.vhd
new file mode 100644
index 0000000..fe818a3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc409.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc409.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00409ent IS
+END c03s02b01x01p19n01i00409ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00409arch OF c03s02b01x01p19n01i00409ent IS
+
+  constant C1 : severity_level := note;
+
+  function complex_scalar(s : severity_level) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level;
+  signal S2 : severity_level;
+  signal S3 : severity_level := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00409" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00409 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00409arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc41.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc41.vhd
new file mode 100644
index 0000000..1b6c3ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc41.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc41.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00041ent IS
+END c04s03b01x01p02n01i00041ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00041arch OF c04s03b01x01p02n01i00041ent IS
+  constant B1 : Bit := '0';         -- No_failure_here
+  constant B2 : Character := '0';   -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( B1 = '0' and B2 = '0' )
+      report "***PASSED TEST: c04s03b01x01p02n01i00041"
+      severity NOTE;
+    assert ( B1 = '0' and B2 = '0' )
+      report "***FAILED TEST: c04s03b01x01p02n01i00041 - Same element contained in two different types assigned to both types in a constant statement test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00041arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc410.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc410.vhd
new file mode 100644
index 0000000..5fb3c3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc410.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc410.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00410ent IS
+END c03s02b01x01p19n01i00410ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00410arch OF c03s02b01x01p19n01i00410ent IS
+
+  constant C1 : integer := 3;
+
+  function complex_scalar(s : integer) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer;
+  signal S2 : integer;
+  signal S3 : integer := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00410" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00410 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00410arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc411.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc411.vhd
new file mode 100644
index 0000000..2cf3762
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc411.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc411.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00411ent IS
+END c03s02b01x01p19n01i00411ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00411arch OF c03s02b01x01p19n01i00411ent IS
+
+  constant C1 : real := 3.0;
+
+  function complex_scalar(s : real) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real;
+  signal S2 : real;
+  signal S3 : real := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00411" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00411 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00411arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc412.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc412.vhd
new file mode 100644
index 0000000..dfab23f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc412.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc412.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00412ent IS
+END c03s02b01x01p19n01i00412ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00412arch OF c03s02b01x01p19n01i00412ent IS
+
+  constant C1 : time := 3 ns;
+
+  function complex_scalar(s : time) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return time is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : time;
+  signal S2 : time;
+  signal S3 : time := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00412" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00412 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00412arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc413.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc413.vhd
new file mode 100644
index 0000000..44f3a28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc413.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc413.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00413ent IS
+END c03s02b01x01p19n01i00413ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00413arch OF c03s02b01x01p19n01i00413ent IS
+
+  constant C1 : natural := 1;
+
+  function complex_scalar(s : natural) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural;
+  signal S2 : natural;
+  signal S3 : natural := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00413" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00413 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00413arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc414.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc414.vhd
new file mode 100644
index 0000000..4eed7e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc414.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc414.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00414ent IS
+END c03s02b01x01p19n01i00414ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00414arch OF c03s02b01x01p19n01i00414ent IS
+
+  constant C1 : positive := 1;
+
+  function complex_scalar(s : positive) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive;
+  signal S2 : positive;
+  signal S3 : positive := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00414" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00414 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00414arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc415.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc415.vhd
new file mode 100644
index 0000000..6a2225c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc415.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc415.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00415ent IS
+END c03s02b01x01p19n01i00415ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00415arch OF c03s02b01x01p19n01i00415ent IS
+
+  type       boolean_cons_vector is array (15 downto 0) of boolean;
+  constant    C1 : boolean_cons_vector := (others => true);
+
+  function complex_scalar(s : boolean_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean_cons_vector;
+  signal S2 : boolean_cons_vector;
+  signal S3 : boolean_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00415" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00415 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00415arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc416.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc416.vhd
new file mode 100644
index 0000000..6d7ad56
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc416.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc416.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00416ent IS
+END c03s02b01x01p19n01i00416ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00416arch OF c03s02b01x01p19n01i00416ent IS
+
+  type       severity_level_cons_vector is array (15 downto 0) of severity_level;
+  constant    C1 : severity_level_cons_vector := (others => note);
+
+  function complex_scalar(s : severity_level_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level_cons_vector;
+  signal S2 : severity_level_cons_vector;
+  signal S3 : severity_level_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00416" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00416 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00416arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc417.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc417.vhd
new file mode 100644
index 0000000..2a560ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc417.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc417.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00417ent IS
+END c03s02b01x01p19n01i00417ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00417arch OF c03s02b01x01p19n01i00417ent IS
+
+  type       real_cons_vector is array (15 downto 0) of real;
+  constant    C1 : real_cons_vector := (others => 3.0);
+
+  function complex_scalar(s : real_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real_cons_vector;
+  signal S2 : real_cons_vector;
+  signal S3 : real_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00417" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00417 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00417arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc418.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc418.vhd
new file mode 100644
index 0000000..0049171
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc418.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc418.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00418ent IS
+END c03s02b01x01p19n01i00418ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00418arch OF c03s02b01x01p19n01i00418ent IS
+
+  type       integer_cons_vector is array (15 downto 0) of integer;
+  constant    C1 : integer_cons_vector := (others => 3);
+
+  function complex_scalar(s : integer_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer_cons_vector;
+  signal S2 : integer_cons_vector;
+  signal S3 : integer_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00418" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00418 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00418arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc419.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc419.vhd
new file mode 100644
index 0000000..cd42bcb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc419.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc419.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00419ent IS
+END c03s02b01x01p19n01i00419ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00419arch OF c03s02b01x01p19n01i00419ent IS
+
+  type       time_cons_vector is array (15 downto 0) of time;
+  constant    C1 : time_cons_vector := (others => 3 ns);
+
+  function complex_scalar(s : time_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return time_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : time_cons_vector;
+  signal S2 : time_cons_vector;
+  signal S3 : time_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00419" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00419 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00419arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc420.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc420.vhd
new file mode 100644
index 0000000..5bb5fbb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc420.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc420.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00420ent IS
+END c03s02b01x01p19n01i00420ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00420arch OF c03s02b01x01p19n01i00420ent IS
+
+  type       natural_cons_vector is array (15 downto 0) of natural;
+  constant    C1 : natural_cons_vector := (others => 1);
+
+  function complex_scalar(s : natural_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural_cons_vector;
+  signal S2 : natural_cons_vector;
+  signal S3 : natural_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00420" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00420 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00420arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc421.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc421.vhd
new file mode 100644
index 0000000..67f6e4d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc421.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc421.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00421ent IS
+END c03s02b01x01p19n01i00421ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00421arch OF c03s02b01x01p19n01i00421ent IS
+
+  type       positive_cons_vector is array (15 downto 0) of positive;
+  constant    C1 : positive_cons_vector := (others => 1);
+
+  function complex_scalar(s : positive_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive_cons_vector;
+  signal S2 : positive_cons_vector;
+  signal S3 : positive_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00421" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00421 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00421arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc422.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc422.vhd
new file mode 100644
index 0000000..02585b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc422.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc422.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00422ent IS
+END c03s02b01x01p19n01i00422ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00422arch OF c03s02b01x01p19n01i00422ent IS
+
+  type       boolean_cons_vector is array (15 downto 0) of boolean;
+  type       boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
+  constant    C1 : boolean_cons_vectorofvector := (others => (others => true));
+
+  function complex_scalar(s : boolean_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean_cons_vectorofvector;
+  signal S2 : boolean_cons_vectorofvector;
+  signal S3 : boolean_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00422" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00422 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00422arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc423.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc423.vhd
new file mode 100644
index 0000000..c220456
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc423.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc423.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00423ent IS
+END c03s02b01x01p19n01i00423ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00423arch OF c03s02b01x01p19n01i00423ent IS
+
+  type       severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type       severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  constant    C1 : severity_level_cons_vectorofvector := (others => (others => note));
+
+  function complex_scalar(s : severity_level_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level_cons_vectorofvector;
+  signal S2 : severity_level_cons_vectorofvector;
+  signal S3 : severity_level_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00423" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00423 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00423arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc424.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc424.vhd
new file mode 100644
index 0000000..599c709
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc424.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc424.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00424ent IS
+END c03s02b01x01p19n01i00424ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00424arch OF c03s02b01x01p19n01i00424ent IS
+
+  type       integer_cons_vector is array (15 downto 0) of integer;
+  type       integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector;
+  constant    C1 : integer_cons_vectorofvector := (others => (others => 3));
+
+  function complex_scalar(s : integer_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer_cons_vectorofvector;
+  signal S2 : integer_cons_vectorofvector;
+  signal S3 : integer_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00424"
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00424 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00424arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc425.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc425.vhd
new file mode 100644
index 0000000..405096c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc425.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc425.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00425ent IS
+END c03s02b01x01p19n01i00425ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00425arch OF c03s02b01x01p19n01i00425ent IS
+
+  type       real_cons_vector is array (15 downto 0) of real;
+  type       real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
+  constant    C1 : real_cons_vectorofvector := (others => (others => 3.0));
+
+  function complex_scalar(s : real_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real_cons_vectorofvector;
+  signal S2 : real_cons_vectorofvector;
+  signal S3 : real_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00425" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00425 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00425arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc426.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc426.vhd
new file mode 100644
index 0000000..c338283
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc426.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc426.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00426ent IS
+END c03s02b01x01p19n01i00426ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00426arch OF c03s02b01x01p19n01i00426ent IS
+
+  type       time_cons_vector is array (15 downto 0) of time;
+  type       time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
+  constant    C1 : time_cons_vectorofvector := (others => (others => 3 ns));
+
+  function complex_scalar(s : time_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return time_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : time_cons_vectorofvector;
+  signal S2 : time_cons_vectorofvector;
+  signal S3 : time_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00426" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00426 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00426arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc427.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc427.vhd
new file mode 100644
index 0000000..b13ee7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc427.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc427.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00427ent IS
+END c03s02b01x01p19n01i00427ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00427arch OF c03s02b01x01p19n01i00427ent IS
+
+  type       natural_cons_vector is array (15 downto 0) of natural;
+  type       natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
+  constant    C1 : natural_cons_vectorofvector := (others => (others => 1));
+
+  function complex_scalar(s : natural_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural_cons_vectorofvector;
+  signal S2 : natural_cons_vectorofvector;
+  signal S3 : natural_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00427" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00427 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00427arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc428.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc428.vhd
new file mode 100644
index 0000000..4c46091
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc428.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc428.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00428ent IS
+END c03s02b01x01p19n01i00428ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00428arch OF c03s02b01x01p19n01i00428ent IS
+
+  type       positive_cons_vector is array (15 downto 0) of positive;
+  type       positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
+  constant    C1 : positive_cons_vectorofvector := (others => (others => 1));
+
+  function complex_scalar(s : positive_cons_vectorofvector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive_cons_vectorofvector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive_cons_vectorofvector;
+  signal S2 : positive_cons_vectorofvector;
+  signal S3 : positive_cons_vectorofvector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00428" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00428 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00428arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc429.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc429.vhd
new file mode 100644
index 0000000..cc123e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc429.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc429.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00429ent IS
+END c03s02b01x01p19n01i00429ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00429arch OF c03s02b01x01p19n01i00429ent IS
+
+  type       column is range 1 to 2;
+  type       row is range 1 to 8;
+  type       s2boolean_cons_vector is array (row,column) of boolean;
+  constant    C1 : s2boolean_cons_vector := (others => (others => true));
+
+  function complex_scalar(s : s2boolean_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2boolean_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2boolean_cons_vector;
+  signal S2 : s2boolean_cons_vector;
+  signal S3 : s2boolean_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00429" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00429 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00429arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc43.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc43.vhd
new file mode 100644
index 0000000..a48679e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc43.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc43.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00043ent IS
+END c04s03b01x01p02n01i00043ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00043arch OF c04s03b01x01p02n01i00043ent IS
+  constant integer:integer := 1;  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(integer = 1)
+      report "***PASSED TEST: c04s03b01x01p02n01i00043" 
+      severity NOTE;
+    assert (integer = 1)
+      report "***FAILED TEST:c04s03b01x01p02n01i00043 - Constant declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00043arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc430.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc430.vhd
new file mode 100644
index 0000000..755215b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc430.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc430.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00430ent IS
+END c03s02b01x01p19n01i00430ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00430arch OF c03s02b01x01p19n01i00430ent IS
+
+  type       column is range 1 to 2;
+  type       row is range 1 to 8;
+  type       s2bit_cons_vector is array (row,column) of bit;
+  constant    C1 : s2bit_cons_vector := (others => (others => '1'));
+
+  function complex_scalar(s : s2bit_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2bit_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2bit_cons_vector;
+  signal S2 : s2bit_cons_vector;
+  signal S3 : s2bit_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00430" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00430 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00430arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc431.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc431.vhd
new file mode 100644
index 0000000..042fa3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc431.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc431.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00431ent IS
+END c03s02b01x01p19n01i00431ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00431arch OF c03s02b01x01p19n01i00431ent IS
+
+  type       column is range 1 to 2;
+  type       row is range 1 to 8;
+  type       s2char_cons_vector is array (row,column) of character;
+  constant    C1 : s2char_cons_vector := (others => (others => 's'));
+
+  function complex_scalar(s : s2char_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2char_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2char_cons_vector;
+  signal S2 : s2char_cons_vector;
+  signal S3 : s2char_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00431" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00431 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00431arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc432.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc432.vhd
new file mode 100644
index 0000000..b373ae6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc432.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc432.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00432ent IS
+END c03s02b01x01p19n01i00432ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00432arch OF c03s02b01x01p19n01i00432ent IS
+
+  type       column is range 1 to 2;
+  type       row is range 1 to 8;
+  type       s2severity_level_cons_vector is array (row,column) of severity_level;
+  constant    C1 : s2severity_level_cons_vector := (others => (others => note));
+
+  function complex_scalar(s : s2severity_level_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2severity_level_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2severity_level_cons_vector;
+  signal S2 : s2severity_level_cons_vector;
+  signal S3 : s2severity_level_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00432" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00432 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00432arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc433.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc433.vhd
new file mode 100644
index 0000000..9fd67a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc433.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc433.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00433ent IS
+END c03s02b01x01p19n01i00433ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00433arch OF c03s02b01x01p19n01i00433ent IS
+
+  type       column is range 1 to 2;
+  type       row is range 1 to 8;
+  type       s2integer_cons_vector is array (row,column) of integer;
+  constant    C1 : s2integer_cons_vector := (others => (others => 3));
+
+  function complex_scalar(s : s2integer_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2integer_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2integer_cons_vector;
+  signal S2 : s2integer_cons_vector;
+  signal S3 : s2integer_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00433" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00433 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00433arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc434.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc434.vhd
new file mode 100644
index 0000000..3c12114
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc434.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc434.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00434ent IS
+END c03s02b01x01p19n01i00434ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00434arch OF c03s02b01x01p19n01i00434ent IS
+
+  type       column    is range 1 to 2;
+  type       row    is range 1 to 8;
+  type       s2real_cons_vector is array (row,column) of real;
+  constant    C1 : s2real_cons_vector := (others => (others => 3.0));
+
+  function complex_scalar(s : s2real_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2real_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2real_cons_vector;
+  signal S2 : s2real_cons_vector;
+  signal S3 : s2real_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00434" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00434 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00434arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc435.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc435.vhd
new file mode 100644
index 0000000..0123503
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc435.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc435.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00435ent IS
+END c03s02b01x01p19n01i00435ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00435arch OF c03s02b01x01p19n01i00435ent IS
+
+  type       column    is range 1 to 2;
+  type       row    is range 1 to 8;
+  type       s2time_cons_vector is array (row,column) of time;
+  constant    C1 : s2time_cons_vector := (others => (others => 3 ns));
+
+  function complex_scalar(s : s2time_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2time_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2time_cons_vector;
+  signal S2 : s2time_cons_vector;
+  signal S3 : s2time_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00435" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00435 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00435arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc436.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc436.vhd
new file mode 100644
index 0000000..915c8d7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc436.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc436.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00436ent IS
+END c03s02b01x01p19n01i00436ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00436arch OF c03s02b01x01p19n01i00436ent IS
+
+  type       column    is range 1 to 2;
+  type       row    is range 1 to 8;
+  type       s2natural_cons_vector is array (row,column) of natural;
+  constant    C1 : s2natural_cons_vector := (others => (others => 1));
+
+  function complex_scalar(s : s2natural_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2natural_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2natural_cons_vector;
+  signal S2 : s2natural_cons_vector;
+  signal S3 : s2natural_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00436" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00436 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00436arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc437.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc437.vhd
new file mode 100644
index 0000000..f8df127
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc437.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc437.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00437ent IS
+END c03s02b01x01p19n01i00437ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00437arch OF c03s02b01x01p19n01i00437ent IS
+
+  type       column    is range 1 to 2;
+  type       row    is range 1 to 8;
+  type       s2positive_cons_vector is array (row,column) of positive;
+  constant    C1 : s2positive_cons_vector := (others => (others => 1));
+
+  function complex_scalar(s : s2positive_cons_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return s2positive_cons_vector is
+  begin
+    return C1;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : s2positive_cons_vector;
+  signal S2 : s2positive_cons_vector;
+  signal S3 : s2positive_cons_vector := C1;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C1) and (S2 = C1)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00437" 
+      severity NOTE;
+    assert ((S1 = C1) and (S2 = C1)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00437 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00437arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc438.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc438.vhd
new file mode 100644
index 0000000..e9dca6c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc438.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc438.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00438ent IS
+END c03s02b01x01p19n01i00438ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00438arch OF c03s02b01x01p19n01i00438ent IS
+
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant    C10 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+
+  function complex_scalar(s : record_std_package) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return record_std_package is
+  begin
+    return C10;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : record_std_package;
+  signal S2 : record_std_package;
+  signal S3 : record_std_package := C10;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C10) and (S2 = C10)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00438" 
+      severity NOTE;
+    assert ((S1 = C10) and (S2 = C10)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00438 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00438arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc439.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc439.vhd
new file mode 100644
index 0000000..10ae3f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc439.vhd
@@ -0,0 +1,137 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc439.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00439ent IS
+END c03s02b01x01p19n01i00439ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00439arch OF c03s02b01x01p19n01i00439ent IS
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+
+  constant    C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+
+  function complex_scalar(s : record_cons_array) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return record_cons_array is
+  begin
+    return C51;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : record_cons_array;
+  signal S2 : record_cons_array;
+  signal S3 : record_cons_array := C51;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C51) and (S2 = C51)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00439" 
+      severity NOTE;
+    assert ((S1 = C51) and (S2 = C51)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00439 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00439arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc440.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc440.vhd
new file mode 100644
index 0000000..679f7c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc440.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc440.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00440ent IS
+END c03s02b01x01p19n01i00440ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00440arch OF c03s02b01x01p19n01i00440ent IS
+
+  type column    is range 1 to 2;
+  type row    is range 1 to 8;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector       is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C41 : s2boolean_cons_vector    := (others => (others => C1));
+  constant C42 : s2bit_cons_vector    := (others => (others => C2));
+  constant C43 : s2char_cons_vector    := (others => (others => C3));
+  constant C44 : s2severity_level_cons_vector := (others => (others => C4));
+  constant C45 : s2integer_cons_vector    := (others => (others => C5));
+  constant C46 : s2real_cons_vector    := (others => (others => C6));
+  constant C47 : s2time_cons_vector    := (others => (others => C7));
+  constant C48 : s2natural_cons_vector    := (others => (others => C8));
+  constant C49 : s2positive_cons_vector    := (others => (others => C9));
+
+  constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+
+  function complex_scalar(s : record_2cons_array) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return record_2cons_array is
+  begin
+    return C52;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : record_2cons_array;
+  signal S2 : record_2cons_array;
+  signal S3 : record_2cons_array := C52;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C52) and (S2 = C52)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00440" 
+      severity NOTE;
+    assert ((S1 = C52) and (S2 = C52)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00440 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00440arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc441.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc441.vhd
new file mode 100644
index 0000000..8b1771d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc441.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc441.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00441ent IS
+END c03s02b01x01p19n01i00441ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00441arch OF c03s02b01x01p19n01i00441ent IS
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type boolean_cons_vectorofvector    is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector       is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector       is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C26 : boolean_cons_vectorofvector    := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector    := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector    := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector    := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector    := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector    := (others => (others => C9));
+
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+
+  function complex_scalar(s : record_cons_arrayofarray) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return record_cons_arrayofarray is
+  begin
+    return C53;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : record_cons_arrayofarray;
+  signal S2 : record_cons_arrayofarray;
+  signal S3 : record_cons_arrayofarray := C53;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C53) and (S2 = C53)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00441" 
+      severity NOTE;
+    assert ((S1 = C53) and (S2 = C53)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00441 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00441arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc442.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc442.vhd
new file mode 100644
index 0000000..653e7be
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc442.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc442.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00442ent IS
+END c03s02b01x01p19n01i00442ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00442arch OF c03s02b01x01p19n01i00442ent IS
+
+  type boolean_vector       is array (natural range <>) of boolean;
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+
+  constant C1 : boolean    := true;
+
+  constant C70 : boolean_vector_st :=(others => C1);
+
+  function complex_scalar(s : boolean_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean_vector_st;
+  signal S2 : boolean_vector_st;
+  signal S3 : boolean_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00442" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00442 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00442arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc443.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc443.vhd
new file mode 100644
index 0000000..ebba779
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc443.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc443.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00443ent IS
+END c03s02b01x01p19n01i00443ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00443arch OF c03s02b01x01p19n01i00443ent IS
+
+  type severity_level_vector is array (natural range <>) of severity_level;
+
+  subtype severity_level_vector_st    is severity_level_vector(0 to 15);
+
+  constant C1 : severity_level    := note;
+
+  constant C70 : severity_level_vector_st :=(others => C1);
+
+  function complex_scalar(s : severity_level_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level_vector_st;
+  signal S2 : severity_level_vector_st;
+  signal S3 : severity_level_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00443" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00443 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00443arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc444.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc444.vhd
new file mode 100644
index 0000000..4b566f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc444.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc444.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00444ent IS
+END c03s02b01x01p19n01i00444ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00444arch OF c03s02b01x01p19n01i00444ent IS
+
+  type integer_vector       is array (natural range <>) of integer;
+  subtype integer_vector_st    is integer_vector(0 to 15);
+
+  constant C1 : integer    := 4;
+
+  constant C70 : integer_vector_st :=(others => C1);
+
+  function complex_scalar(s : integer_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer_vector_st;
+  signal S2 : integer_vector_st;
+  signal S3 : integer_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00444" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00444 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00444arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc445.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc445.vhd
new file mode 100644
index 0000000..810a144
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc445.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc445.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00445ent IS
+END c03s02b01x01p19n01i00445ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00445arch OF c03s02b01x01p19n01i00445ent IS
+
+  type real_vector is array (natural range <>) of real;
+
+  subtype real_vector_st    is real_vector(0 to 15);
+
+  constant C1 : real    := 4.0;
+
+  constant C70 : real_vector_st :=(others => C1);
+
+  function complex_scalar(s : real_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real_vector_st;
+  signal S2 : real_vector_st;
+  signal S3 : real_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00445" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00445 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00445arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc446.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc446.vhd
new file mode 100644
index 0000000..b2aadd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc446.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc446.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00446ent IS
+END c03s02b01x01p19n01i00446ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00446arch OF c03s02b01x01p19n01i00446ent IS
+
+  type time_vector is array (natural range <>) of time;
+
+  subtype time_vector_st    is time_vector(0 to 15);
+
+  constant C1 : time    := 4 ns;
+
+  constant C70 : time_vector_st :=(others => C1);
+
+  function complex_scalar(s : time_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return time_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : time_vector_st;
+  signal S2 : time_vector_st;
+  signal S3 : time_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00446" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00446 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00446arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc447.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc447.vhd
new file mode 100644
index 0000000..9bd4e84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc447.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc447.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00447ent IS
+END c03s02b01x01p19n01i00447ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00447arch OF c03s02b01x01p19n01i00447ent IS
+
+  type natural_vector is array (natural range <>) of natural;
+
+  subtype natural_vector_st    is natural_vector(0 to 15);
+
+  constant C1 : natural    := 4;
+
+  constant C70 : natural_vector_st :=(others => C1);
+
+  function complex_scalar(s : natural_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural_vector_st;
+  signal S2 : natural_vector_st;
+  signal S3 : natural_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00447" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00447 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00447arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc448.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc448.vhd
new file mode 100644
index 0000000..6777c0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc448.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc448.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00448ent IS
+END c03s02b01x01p19n01i00448ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00448arch OF c03s02b01x01p19n01i00448ent IS
+
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype positive_vector_st    is positive_vector(0 to 15);
+
+  constant C1 : positive    := 4;
+
+  constant C70 : positive_vector_st :=(others => C1);
+
+  function complex_scalar(s : positive_vector_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive_vector_st is
+  begin
+    return C70;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive_vector_st;
+  signal S2 : positive_vector_st;
+  signal S3 : positive_vector_st := C70;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C70) and (S2 = C70)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00448" 
+      severity NOTE;
+    assert ((S1 = C70) and (S2 = C70)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00448 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00448arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc449.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc449.vhd
new file mode 100644
index 0000000..098ef16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc449.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc449.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00449ent IS
+END c03s02b01x01p19n01i00449ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00449arch OF c03s02b01x01p19n01i00449ent IS
+
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C70 : boolean_vector_st    :=(others => C1);
+  constant C71 : severity_level_vector_st   :=(others => C4);
+  constant C72 : integer_vector_st   :=(others => C5);
+  constant C73 : real_vector_st      :=(others => C6);
+  constant C74 : time_vector_st      :=(others => C7);
+  constant C75 : natural_vector_st   :=(others => C8);
+  constant C76 : positive_vector_st   :=(others => C9);
+
+  constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+
+  function complex_scalar(s : record_array_st) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return record_array_st is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : record_array_st;
+  signal S2 : record_array_st;
+  signal S3 : record_array_st := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00449" 
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00449 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00449arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc45.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc45.vhd
new file mode 100644
index 0000000..fdb2c86
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc45.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc45.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00045ent IS
+END c04s03b01x01p02n01i00045ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00045arch OF c04s03b01x01p02n01i00045ent IS
+  type    T1_0 is array (integer range <>) of integer;
+  subtype    T1_1 is T1_0 (1 to 2);
+  subtype    T1_2 is T1_0 (1 to 4);
+
+  type    T2_0 is array (integer range <>) of T1_2;
+  subtype    T2_1 is T2_0 (1 to 2);
+  subtype    T2_2 is T2_0 (1 to 4);
+
+  -- Create some constants for constructing the real tests...
+  constant C1   : T1_1 := (1, 2);
+  constant C2   : T1_1 := C1;
+  constant C3   : T1_2 := (1, 2, 3, 4);
+  constant C4   : T1_2 := C3;
+
+  -- Success_here : on all constant declarations below
+  
+  constant C5   : T2_1 := ((1, 2, 3, 4), (5, 6, 7, 8));
+  constant C6   : T2_1 := (C3, C4);
+  constant C7   : T2_1 := (C1 & C2, C2 & C1);
+  constant C8   : T2_1 := (1 & 2 & C2, C3);
+  constant C10: T2_2 := ((1, 2, 3, 4), (5, 6, 7, 8),
+                         (9, 0, 1, 2), (3, 4, 5, 6));
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(   C1 = (1,2)      and
+                  C2 = (1,2)      and
+                  C3 = (1,2,3,4)      and
+                  C4 = (1,2,3,4)      and
+                  C5 = ((1, 2, 3, 4), (5, 6, 7, 8))   and
+                  C6 = ((1, 2, 3, 4), (1, 2, 3, 4))   and
+                  C7 = ((1, 2, 1, 2), (1, 2, 1, 2))   and
+                  C8 = ((1, 2, 1, 2), (1, 2, 3, 4))   and
+                  C10= (   (1, 2, 3, 4), (5, 6, 7, 8),
+                           (9, 0, 1, 2), (3, 4, 5, 6))   )
+      report "***PASSED TEST: c04s03b01x01p02n01i00045"
+      severity NOTE;
+    assert (   C1 = (1,2)      and
+               C2 = (1,2)      and
+               C3 = (1,2,3,4)      and
+               C4 = (1,2,3,4)      and
+               C5 = ((1, 2, 3, 4), (5, 6, 7, 8))   and
+               C6 = ((1, 2, 3, 4), (1, 2, 3, 4))   and
+               C7 = ((1, 2, 1, 2), (1, 2, 1, 2))   and
+               C8 = ((1, 2, 1, 2), (1, 2, 3, 4))   and
+               C10= (   (1, 2, 3, 4), (5, 6, 7, 8),
+                        (9, 0, 1, 2), (3, 4, 5, 6))   )
+      report "***FAILED TEST: c04s03b01x01p02n01i00045 - Syntactic error in constant declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00045arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc450.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc450.vhd
new file mode 100644
index 0000000..e06b208
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc450.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc450.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00450ent IS
+END c03s02b01x01p19n01i00450ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00450arch OF c03s02b01x01p19n01i00450ent IS
+
+  type four_value is ('Z','0','1','X');               --enumerated type
+
+  constant C77 : four_value := 'Z';
+
+  function complex_scalar(s : four_value) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return four_value is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : four_value;
+  signal S2 : four_value;
+  signal S3 : four_value := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00450" 
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00450 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00450arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc451.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc451.vhd
new file mode 100644
index 0000000..1bed837
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc451.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc451.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00451ent IS
+END c03s02b01x01p19n01i00451ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00451arch OF c03s02b01x01p19n01i00451ent IS
+
+  type four_value    is ('Z','0','1','X');               --enumerated type
+  type four_value_map   is array(four_value) of boolean;
+
+  constant C77 : four_value_map := (true,true,true,true);
+
+  function complex_scalar(s : four_value_map) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return four_value_map is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : four_value_map;
+  signal S2 : four_value_map;
+  signal S3 : four_value_map := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00451"
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00451 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00451arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc452.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc452.vhd
new file mode 100644
index 0000000..6494f55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc452.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc452.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00452ent IS
+END c03s02b01x01p19n01i00452ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00452arch OF c03s02b01x01p19n01i00452ent IS
+
+  type    four_value    is ('Z','0','1','X');               --enumerated type
+  subtype binary       is four_value range '0' to '1';
+
+  constant C77 : binary := '0';
+
+  function complex_scalar(s : binary) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return binary is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : binary;
+  signal S2 : binary;
+  signal S3 : binary := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00452" 
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00452 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00452arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc453.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc453.vhd
new file mode 100644
index 0000000..7cee687
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc453.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc453.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00453ent IS
+END c03s02b01x01p19n01i00453ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00453arch OF c03s02b01x01p19n01i00453ent IS
+
+  type    four_value       is ('Z','0','1','X');      --enumerated type
+  type    four_value_vector    is array (natural range <>) of four_value;
+
+  constant C77 : four_value_vector := ('1','0','1','0');
+
+  function complex_scalar(s : four_value_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return four_value_vector is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : four_value_vector(0 to 3);
+  signal S2 : four_value_vector(0 to 3);
+  signal S3 : four_value_vector(0 to 3) := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00453" 
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00453 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00453arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc454.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc454.vhd
new file mode 100644
index 0000000..cc8b5f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc454.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc454.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00454ent IS
+END c03s02b01x01p19n01i00454ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00454arch OF c03s02b01x01p19n01i00454ent IS
+
+  type    byte is array(0 to 7) of bit;
+
+  constant C77 : byte := (others => '0');
+
+  function complex_scalar(s : byte) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return byte is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : byte;
+  signal S2 : byte;
+  signal S3 : byte := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00454"
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00454 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00454arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc455.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc455.vhd
new file mode 100644
index 0000000..aafcd68
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc455.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc455.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00455ent IS
+END c03s02b01x01p19n01i00455ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00455arch OF c03s02b01x01p19n01i00455ent IS
+
+  subtype    word is bit_vector(0 to  15);
+
+  constant C77 : word := (others => '0');
+
+  function complex_scalar(s : word) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return word is
+  begin
+    return C77;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : word;
+  signal S2 : word;
+  signal S3 : word := C77;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C77) and (S2 = C77)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00455" 
+      severity NOTE;
+    assert ((S1 = C77) and (S2 = C77)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00455 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00455arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc456.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc456.vhd
new file mode 100644
index 0000000..f4de737
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc456.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc456.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00456ent IS
+END c03s02b01x01p19n01i00456ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00456arch OF c03s02b01x01p19n01i00456ent IS
+
+
+  type       four_value     is ('Z','0','1','X');
+  type       four_value_vector is array (natural range <>) of four_value;
+  function    resolution14(i:in four_value_vector) return four_value is
+    variable temp : four_value := 'Z';
+  begin
+    return temp;
+  end resolution14;
+
+  subtype    four_value_state is resolution14 four_value;
+  constant    C56 : four_value_state := 'Z';
+
+
+  function complex_scalar(s : four_value_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return four_value_state is
+  begin
+    return C56;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : four_value_state;
+  signal S2 : four_value_state;
+  signal S3 : four_value_state := C56;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C56) and (S2 = C56)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00456" 
+      severity NOTE;
+    assert ((S1 = C56) and (S2 = C56)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00456 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00456arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc457.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc457.vhd
new file mode 100644
index 0000000..2fc9781
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc457.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc457.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00457ent IS
+END c03s02b01x01p19n01i00457ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00457arch OF c03s02b01x01p19n01i00457ent IS
+
+
+  type       four_value     is ('Z','0','1','X');
+  type       four_value_vector is array (natural range <>) of four_value;
+  function    resolution14(i:in four_value_vector) return four_value is
+    variable temp : four_value := 'Z';
+  begin
+    return temp;
+  end resolution14;
+
+  subtype    four_value_state is resolution14 four_value;
+  type       state_vector is array (natural range <>) of four_value_state;
+  constant    C63 : state_vector := ('Z','Z','Z','Z');
+
+  function complex_scalar(s : state_vector) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return state_vector is
+  begin
+    return C63;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : state_vector(0 to 3);
+  signal S2 : state_vector(0 to 3);
+  signal S3 : state_vector(0 to 3) := C63;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C63) and (S2 = C63)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00457"
+      severity NOTE;
+    assert ((S1 = C63) and (S2 = C63)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00457 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00457arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc458.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc458.vhd
new file mode 100644
index 0000000..6940f58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc458.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc458.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00458ent IS
+END c03s02b01x01p19n01i00458ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00458arch OF c03s02b01x01p19n01i00458ent IS
+
+  subtype    word is bit_vector(0 to  15);
+  constant    size :integer := 7;
+  type       primary_memory is array(0 to size) of word;
+
+  constant    C61 : word := (others =>'0' );
+  constant    C64 : primary_memory := (others => C61);
+
+  function complex_scalar(s : primary_memory) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return primary_memory is
+  begin
+    return C64;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : primary_memory;
+  signal S2 : primary_memory;
+  signal S3 : primary_memory:= C64;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C64) and (S2 = C64)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00458" 
+      severity NOTE;
+    assert ((S1 = C64) and (S2 = C64)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00458 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00458arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc459.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc459.vhd
new file mode 100644
index 0000000..d649a97
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc459.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc459.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00459ent IS
+END c03s02b01x01p19n01i00459ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00459arch OF c03s02b01x01p19n01i00459ent IS
+
+  type       four_value    is ('Z','0','1','X');
+  subtype    binary       is four_value range '0' to '1';
+  subtype    word       is bit_vector(0 to  15);
+  constant    size :integer := 7;
+  type       primary_memory    is array(0 to size) of word;
+
+  type primary_memory_module is   
+    record   
+      enable      :binary;
+      memory_number   :primary_memory;
+    end record;   
+
+  constant    C61 : word := (others =>'0' );
+  constant    C64 : primary_memory := (others => C61);
+  constant    C65 : primary_memory_module := ('1',C64);
+
+  function complex_scalar(s : primary_memory_module) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return primary_memory_module is
+  begin
+    return C65;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : primary_memory_module;
+  signal S2 : primary_memory_module;
+  signal S3 : primary_memory_module:= C65;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C65) and (S2 = C65)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00459" 
+      severity NOTE;
+    assert ((S1 = C65) and (S2 = C65)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00459 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00459arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc460.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc460.vhd
new file mode 100644
index 0000000..ba9bfa4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc460.vhd
@@ -0,0 +1,118 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc460.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00460ent IS
+END c03s02b01x01p19n01i00460ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00460arch OF c03s02b01x01p19n01i00460ent IS
+
+  type       four_value    is ('Z','0','1','X');
+  subtype    binary       is four_value range '0' to '1';
+  subtype    word       is bit_vector(0 to  15);
+  constant    size       :integer := 7;
+  type       primary_memory    is array(0 to size) of word;
+
+  type primary_memory_module is   
+    record   
+      enable      :binary;
+      memory_number   :primary_memory;
+    end record;   
+
+  type       whole_memory is array(0 to size) of primary_memory_module;
+
+  constant    C61 : word       := (others =>'0' );
+  constant    C64 : primary_memory    := (others => C61);
+  constant    C65 : primary_memory_module := ('1',C64);
+  constant    C66 : whole_memory    := (others => C65);
+
+  function complex_scalar(s : whole_memory) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return whole_memory is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : whole_memory;
+  signal S2 : whole_memory;
+  signal S3 : whole_memory:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00460" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00460 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00460arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc461.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc461.vhd
new file mode 100644
index 0000000..35b2681
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc461.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc461.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00461ent IS
+END c03s02b01x01p19n01i00461ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00461arch OF c03s02b01x01p19n01i00461ent IS
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+
+  constant    C66 : current := 1 A;
+
+  function complex_scalar(s : current) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return current is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : current;
+  signal S2 : current;
+  signal S3 : current:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00461" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00461 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00461arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc462.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc462.vhd
new file mode 100644
index 0000000..498b9d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc462.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc462.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00462ent IS
+END c03s02b01x01p19n01i00462ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00462arch OF c03s02b01x01p19n01i00462ent IS
+
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm    = 1000 uOhm;
+      Ohm    = 1000 mOhm;
+      KOhm     = 1000 Ohm;
+    end units;
+
+  constant C66 : resistance := 1 Ohm;
+
+  function complex_scalar(s : resistance) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return resistance is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : resistance;
+  signal S2 : resistance;
+  signal S3 : resistance:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00462" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00462 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00462arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc463.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc463.vhd
new file mode 100644
index 0000000..139b718
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc463.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc463.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00463ent IS
+END c03s02b01x01p19n01i00463ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00463arch OF c03s02b01x01p19n01i00463ent IS
+
+  subtype    delay is integer range 1 to 10;
+  constant    C66 : delay := 2;
+
+  function complex_scalar(s : delay) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return delay is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : delay;
+  signal S2 : delay;
+  signal S3 : delay:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00463"
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00463 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00463arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc464.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc464.vhd
new file mode 100644
index 0000000..10ab7bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc464.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc464.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00464ent IS
+END c03s02b01x01p19n01i00464ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00464arch OF c03s02b01x01p19n01i00464ent IS
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       boolean_vector       is array (natural range <>) of boolean;
+  subtype    boolean_vector_range    is boolean_vector(hi_to_low_range);
+  constant    C66: boolean_vector_range := (others => true);
+
+  function complex_scalar(s : boolean_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean_vector_range;
+  signal S2 : boolean_vector_range;
+  signal S3 : boolean_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00464"
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00464 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00464arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc465.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc465.vhd
new file mode 100644
index 0000000..8645c79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc465.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc465.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00465ent IS
+END c03s02b01x01p19n01i00465ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00465arch OF c03s02b01x01p19n01i00465ent IS
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range       is integer range low_number to hi_number;
+  type       severity_level_vector       is array (natural range <>) of severity_level;
+  subtype    severity_level_vector_range    is severity_level_vector(hi_to_low_range);
+  constant    C66: severity_level_vector_range := (others => note);
+
+  function complex_scalar(s : severity_level_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level_vector_range;
+  signal S2 : severity_level_vector_range;
+  signal S3 : severity_level_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00465" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00465 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00465arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc466.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc466.vhd
new file mode 100644
index 0000000..0bef526
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc466.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc466.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00466ent IS
+END c03s02b01x01p19n01i00466ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00466arch OF c03s02b01x01p19n01i00466ent IS
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       integer_vector       is array (natural range <>) of integer;
+  subtype    integer_vector_range    is integer_vector(hi_to_low_range);
+  constant    C66: integer_vector_range := (others => 3);
+
+  function complex_scalar(s : integer_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer_vector_range;
+  signal S2 : integer_vector_range;
+  signal S3 : integer_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00466" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00466 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00466arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc467.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc467.vhd
new file mode 100644
index 0000000..f3a9571
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc467.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc467.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00467ent IS
+END c03s02b01x01p19n01i00467ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00467arch OF c03s02b01x01p19n01i00467ent IS
+
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       real_vector       is array (natural range <>) of real;
+  subtype    real_vector_range    is real_vector(hi_to_low_range);
+  constant    C66: real_vector_range := (others => 3.0);
+
+  function complex_scalar(s : real_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real_vector_range;
+  signal S2 : real_vector_range;
+  signal S3 : real_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00467" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00467 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00467arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc468.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc468.vhd
new file mode 100644
index 0000000..f65bc93
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc468.vhd
@@ -0,0 +1,105 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc468.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00468ent IS
+END c03s02b01x01p19n01i00468ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00468arch of c03s02b01x01p19n01i00468ent IS
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       time_vector       is array (natural range <>) of time;
+  subtype    time_vector_range    is time_vector(hi_to_low_range);
+  constant    C66: time_vector_range := (others => 3 ns);
+
+  function complex_scalar(s : time_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return time_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : time_vector_range;
+  signal S2 : time_vector_range;
+  signal S3 : time_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00468" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00468 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00468arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc469.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc469.vhd
new file mode 100644
index 0000000..f048228
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc469.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc469.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00469ent IS
+END c03s02b01x01p19n01i00469ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00469arch OF c03s02b01x01p19n01i00469ent IS
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       natural_vector       is array (natural range <>) of natural;
+  subtype    natural_vector_range    is natural_vector(hi_to_low_range);
+  constant    C66: natural_vector_range := (others => 1);
+
+  function complex_scalar(s : natural_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural_vector_range;
+  signal S2 : natural_vector_range;
+  signal S3 : natural_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00469" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00469 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00469arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc470.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc470.vhd
new file mode 100644
index 0000000..7cedecb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc470.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc470.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00470ent IS
+END c03s02b01x01p19n01i00470ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00470arch OF c03s02b01x01p19n01i00470ent IS
+
+  constant    low_number : integer := 0;
+  constant    hi_number  : integer := 7;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type       positive_vector    is array (natural range <>) of positive;
+  subtype    positive_vector_range    is positive_vector(hi_to_low_range);
+  constant    C66: positive_vector_range := (others => 1);
+
+  function complex_scalar(s : positive_vector_range) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive_vector_range is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive_vector_range;
+  signal S2 : positive_vector_range;
+  signal S3 : positive_vector_range:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00470" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00470 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00470arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc471.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc471.vhd
new file mode 100644
index 0000000..e07d9c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc471.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc471.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00471ent IS
+END c03s02b01x01p19n01i00471ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00471arch OF c03s02b01x01p19n01i00471ent IS
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  constant C50 : record_std_package    := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C66: array_rec_std(0 to 7)    := (others => C50)  ;
+
+  function complex_scalar(s : array_rec_std(0 to 7)) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_std is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_std(0 to 7);
+  signal S2 : array_rec_std(0 to 7);
+  signal S3 : array_rec_std(0 to 7):= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00471" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00471 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00471arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc472.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc472.vhd
new file mode 100644
index 0000000..de06920
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc472.vhd
@@ -0,0 +1,139 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc472.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00472ent IS
+END c03s02b01x01p19n01i00472ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00472arch OF c03s02b01x01p19n01i00472ent IS
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+  constant C51 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+  constant C66 : array_rec_cons (0 to 7)    := (others => C51);
+
+
+  function complex_scalar(s : array_rec_cons(0 to 7)) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_cons is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_cons(0 to 7);
+  signal S2 : array_rec_cons(0 to 7);
+  signal S3 : array_rec_cons(0 to 7):= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00472" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00472 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00472arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc473.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc473.vhd
new file mode 100644
index 0000000..9f9bf5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc473.vhd
@@ -0,0 +1,147 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc473.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00473ent IS
+END c03s02b01x01p19n01i00473ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00473arch OF c03s02b01x01p19n01i00473ent IS
+
+  type column    is range 1 to 2;
+  type row    is range 1 to 8;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector    is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector    is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+  type array_rec_2cons is array (integer range <>) of record_2cons_array;
+  
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  constant C41 : s2boolean_cons_vector    := (others => (others => C1));
+  constant C42 : s2bit_cons_vector    := (others => (others => C2));
+  constant C43 : s2char_cons_vector    := (others => (others => C3));
+  constant C44 : s2severity_level_cons_vector    := (others => (others => C4));
+  constant C45 : s2integer_cons_vector    := (others => (others => C5));
+  constant C46 : s2real_cons_vector    := (others => (others => C6));
+  constant C47 : s2time_cons_vector    := (others => (others => C7));
+  constant C48 : s2natural_cons_vector    := (others => (others => C8));
+  constant C49 : s2positive_cons_vector    := (others => (others => C9));
+  constant C52 : record_2cons_array    := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+  constant C66 : array_rec_2cons(0 to 7)   := (others => C52) ;
+
+
+  function complex_scalar(s : array_rec_2cons(0 to 7)) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_2cons is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_2cons(0 to 7);
+  signal S2 : array_rec_2cons(0 to 7);
+  signal S3 : array_rec_2cons(0 to 7):= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00473" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00473 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00473arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc474.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc474.vhd
new file mode 100644
index 0000000..cf47d92
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc474.vhd
@@ -0,0 +1,268 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc474.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00474ent IS
+END c03s02b01x01p19n01i00474ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00474arch OF c03s02b01x01p19n01i00474ent IS
+
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type column    is range 1 to 2;
+  type row    is range 1 to 8;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector       is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+  type s2boolean_vector    is array (natural range <>,natural range <>) of boolean;
+  type s2bit_vector    is array (natural range<>,natural range <>) of bit;
+  type s2char_vector    is array (natural range<>,natural range <>) of character;
+  type s2severity_level_vector    is array (natural range <>,natural range <>) of severity_level;
+  type s2integer_vector    is array (natural range <>,natural range <>) of integer;
+  type s2real_vector    is array (natural range <>,natural range <>) of real;
+  type s2time_vector    is array (natural range <>,natural range <>) of time;
+  type s2natural_vector    is array (natural range <>,natural range <>) of natural;
+  type s2positive_vector    is array (natural range <>,natural range <>) of positive;
+
+  type boolean_cons_vectorofvector    is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector       is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector       is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+
+  subtype boolean_vector_st       is  boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st          is  real_vector(0 to 15);
+  subtype time_vector_st          is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st       is  positive_vector(0 to 15);
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                            end record;
+
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C19 : boolean_cons_vector       := (others => C1);
+  constant C20 : severity_level_cons_vector    := (others => C4);
+  constant C21 : integer_cons_vector       := (others => C5);
+  constant C22 : real_cons_vector       := (others => C6);
+  constant C23 : time_cons_vector       := (others => C7);
+  constant C24 : natural_cons_vector       := (others => C8);
+  constant C25 : positive_cons_vector       := (others => C9);
+  constant C26 : boolean_cons_vectorofvector    := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector    :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector    := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector    := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector    := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector    := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector    := (others => (others => C9));
+  constant C41 : s2boolean_cons_vector    := (others => (others => C1));
+  constant C42 : s2bit_cons_vector    := (others => (others => C2));
+  constant C43 : s2char_cons_vector    := (others => (others => C3));
+  constant C44 : s2severity_level_cons_vector    := (others => (others => C4));
+  constant C45 : s2integer_cons_vector    := (others => (others => C5));
+  constant C46 : s2real_cons_vector    := (others => (others => C6));
+  constant C47 : s2time_cons_vector    := (others => (others => C7));
+  constant C48 : s2natural_cons_vector    := (others => (others => C8));
+  constant C49 : s2positive_cons_vector    := (others => (others => C9));
+  constant C50 : record_std_package    := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C51 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+  constant C52 : record_2cons_array    := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70 : boolean_vector_st    := (others => C1);
+  constant C71 : severity_level_vector_st   := (others => C4);
+  constant C72 : integer_vector_st   := (others => C5);
+  constant C73 : real_vector_st      := (others => C6);
+  constant C74 : time_vector_st      := (others => C7);
+  constant C75 : natural_vector_st   := (others => C8);
+  constant C76 : positive_vector_st   := (others => C9);
+
+  constant C77 : record_array_st       := (C70,C71,C72,C73,C74,C75,C76);
+
+  constant C55 : record_of_records    := (C50,C51,C52,C53,C77);
+
+  constant C66 : array_rec_rec(0 to 7)    := (others => C55);
+
+  function complex_scalar(s : array_rec_rec(0 to 7)) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_rec is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_rec(0 to 7);
+  signal S2 : array_rec_rec(0 to 7);
+  signal S3 : array_rec_rec(0 to 7):= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00474" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00474 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00474arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc475.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc475.vhd
new file mode 100644
index 0000000..af23b42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc475.vhd
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc475.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00475ent IS
+END c03s02b01x01p19n01i00475ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00475arch OF c03s02b01x01p19n01i00475ent IS
+
+  type       boolean_vector is array (natural range <>) of boolean;
+
+  function resolution1(i:in boolean_vector) return boolean is
+    variable temp : boolean:= true;
+  begin
+    return temp;
+  end resolution1;
+
+  subtype    boolean_state is resolution1 boolean;
+  constant    C66 : boolean_state   := true;
+
+  function complex_scalar(s : boolean_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return boolean_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : boolean_state;
+  signal S2 : boolean_state;
+  signal S3 : boolean_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00475" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00475 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00475arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc476.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc476.vhd
new file mode 100644
index 0000000..bea5f69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc476.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc476.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00476ent IS
+END c03s02b01x01p19n01i00476ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00476arch OF c03s02b01x01p19n01i00476ent IS
+
+  type    severity_level_vector is array (natural range <>) of severity_level;
+
+  function resolution2(i:in severity_level_vector) return severity_level is
+    variable temp : severity_level := note;
+  begin
+    return temp;
+  end resolution2;
+
+  subtype    severity_level_state is resolution2 severity_level;
+
+  constant    C66 : severity_level_state   := note;
+
+  function complex_scalar(s : severity_level_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return severity_level_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : severity_level_state;
+  signal S2 : severity_level_state;
+  signal S3 : severity_level_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00476" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00476 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00476arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc477.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc477.vhd
new file mode 100644
index 0000000..a7676a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc477.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc477.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00477ent IS
+END c03s02b01x01p19n01i00477ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00477arch OF c03s02b01x01p19n01i00477ent IS
+
+  function resolution3(i:in bit_vector) return bit is
+    variable temp : bit := '1';
+  begin
+    return temp;
+  end resolution3;
+
+  subtype    bit_state is resolution3 bit;
+  constant    C66 : bit_state   := '1';
+
+  function complex_scalar(s : bit_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return bit_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : bit_state;
+  signal S2 : bit_state;
+  signal S3 : bit_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00477" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00477 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00477arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc478.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc478.vhd
new file mode 100644
index 0000000..622ae9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc478.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc478.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00478ent IS
+END c03s02b01x01p19n01i00478ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00478arch OF c03s02b01x01p19n01i00478ent IS
+
+  function resolution4(i:in string) return character is
+    variable temp : character := 's' ;
+  begin
+    return temp;
+  end resolution4;
+  subtype    character_state is resolution4 character;
+  constant    C66 : character_state   := 's';
+
+  function complex_scalar(s : character_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return character_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : character_state;
+  signal S2 : character_state;
+  signal S3 : character_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00478" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00478 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00478arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc479.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc479.vhd
new file mode 100644
index 0000000..0ef6f1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc479.vhd
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc479.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00479ent IS
+END c03s02b01x01p19n01i00479ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00479arch OF c03s02b01x01p19n01i00479ent IS
+
+  type    integer_vector is array (natural range <>) of integer;
+
+  function resolution5(i:in integer_vector) return integer is
+    variable temp : integer := 3;
+  begin
+    return temp;
+  end resolution5;
+
+  subtype    integer_state is resolution5 integer;
+  constant    C66 : integer_state   := 3;
+
+  function complex_scalar(s : integer_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return integer_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : integer_state;
+  signal S2 : integer_state;
+  signal S3 : integer_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00479" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00479 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00479arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc480.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc480.vhd
new file mode 100644
index 0000000..539d0b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc480.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc480.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00480ent IS
+END c03s02b01x01p19n01i00480ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00480arch OF c03s02b01x01p19n01i00480ent IS
+
+  type    real_vector is array (natural range <>) of real;
+  function resolution6(i:in real_vector) return real is
+    variable temp : real := 3.0;
+  begin
+    return temp;
+  end resolution6;
+
+  subtype    real_state is resolution6 real;
+  constant    C66 : real_state   := 3.0;
+
+  function complex_scalar(s : real_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return real_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : real_state;
+  signal S2 : real_state;
+  signal S3 : real_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00480" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00480 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00480arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc481.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc481.vhd
new file mode 100644
index 0000000..a18c2c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc481.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc481.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00481ent IS
+END c03s02b01x01p19n01i00481ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00481arch OF c03s02b01x01p19n01i00481ent IS
+
+  type    natural_vector is array (natural range <>) of natural;
+  function resolution8(i:in natural_vector) return natural is
+    variable temp : natural := 1;
+  begin
+    return temp;
+  end resolution8;
+  subtype    natural_state is resolution8 natural;
+  constant    C66 : natural_state   := 1;
+
+  function complex_scalar(s : natural_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return natural_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : natural_state;
+  signal S2 : natural_state;
+  signal S3 : natural_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00481" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00481 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00481arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc482.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc482.vhd
new file mode 100644
index 0000000..5e0cafa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc482.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc482.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00482ent IS
+END c03s02b01x01p19n01i00482ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00482arch OF c03s02b01x01p19n01i00482ent IS
+
+  type    positive_vector is array (natural range <>) of positive;
+  function resolution9(i:in positive_vector) return positive is
+    variable temp : positive := 1;
+  begin
+    return temp;
+  end resolution9;
+  subtype    positive_state is resolution9 positive;
+  constant    C66 : positive_state   := 1;
+
+  function complex_scalar(s : positive_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return positive_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : positive_state;
+  signal S2 : positive_state;
+  signal S3 : positive_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00482" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00482 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00482arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc483.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc483.vhd
new file mode 100644
index 0000000..67e33b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc483.vhd
@@ -0,0 +1,134 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc483.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00483ent IS
+END c03s02b01x01p19n01i00483ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00483arch OF c03s02b01x01p19n01i00483ent IS
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+
+
+  type    array_rec_std is array (integer range <>) of record_std_package;
+  function resolution10(i:in array_rec_std) return record_std_package is
+    variable temp : record_std_package := C50;
+  begin
+    return temp;
+  end resolution10;
+  subtype    array_rec_std_state is resolution10 record_std_package;
+
+  constant C66 : array_rec_std_state   := C50;
+
+  function complex_scalar(s : array_rec_std_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_std_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_std_state;
+  signal S2 : array_rec_std_state;
+  signal S3 : array_rec_std_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00483" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00483 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00483arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc484.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc484.vhd
new file mode 100644
index 0000000..b539324
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc484.vhd
@@ -0,0 +1,148 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc484.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p19n01i00484ent_a IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END c03s02b01x01p19n01i00484ent_a;
+
+architecture c03s02b01x01p19n01i00484arch_a of c03s02b01x01p19n01i00484ent_a is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00484ent IS
+END c03s02b01x01p19n01i00484ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00484arch OF c03s02b01x01p19n01i00484ent IS
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type array_rec_cons is array (integer range <>) of record_cons_array;   
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector    := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    :=  (others => C7);
+  constant C24 : natural_cons_vector    :=  (others => C8);
+  constant C25 : positive_cons_vector    :=  (others => C9);
+
+  constant C51 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+
+  function resolution11(i:in array_rec_cons) return record_cons_array is
+    variable temp : record_cons_array := C51;
+  begin
+    return temp;
+  end resolution11;
+  subtype array_rec_cons_state is resolution11 record_cons_array;
+
+  constant C66 : array_rec_cons_state   := C51;
+
+  function complex_scalar(s : array_rec_cons_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_cons_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component c03s02b01x01p19n01i00484ent_a1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : c03s02b01x01p19n01i00484ent_a1 use entity work.c03s02b01x01p19n01i00484ent_a(c03s02b01x01p19n01i00484arch_a);
+
+  signal S1 : array_rec_cons_state;
+  signal S2 : array_rec_cons_state;
+  signal S3 : array_rec_cons_state:= C66;
+BEGIN
+  T1: c03s02b01x01p19n01i00484ent_a1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00484" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00484 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00484arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc485.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc485.vhd
new file mode 100644
index 0000000..4adf6d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc485.vhd
@@ -0,0 +1,156 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc485.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p19n01i00485ent_a IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END c03s02b01x01p19n01i00485ent_a;
+
+architecture c03s02b01x01p19n01i00485ent_a of c03s02b01x01p19n01i00485ent_a is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00485ent IS
+END c03s02b01x01p19n01i00485ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00485arch OF c03s02b01x01p19n01i00485ent IS
+
+  type column    is range 1 to 2;
+  type row    is range 1 to 8;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector    is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector    is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  constant C41 : s2boolean_cons_vector    := (others => (others => C1));
+  constant C42 : s2bit_cons_vector    := (others => (others => C2));
+  constant C43 : s2char_cons_vector    := (others => (others => C3));
+  constant C44 : s2severity_level_cons_vector    := (others => (others => C4));
+  constant C45 : s2integer_cons_vector    := (others => (others => C5));
+  constant C46 : s2real_cons_vector    := (others => (others => C6));
+  constant C47 : s2time_cons_vector    := (others => (others => C7));
+  constant C48 : s2natural_cons_vector    := (others => (others => C8));
+  constant C49 : s2positive_cons_vector    := (others => (others => C9));
+
+  constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+
+  type    array_rec_2cons is array (integer range <>) of record_2cons_array;
+
+  function resolution12(i:in array_rec_2cons) return record_2cons_array is
+    variable temp : record_2cons_array := C52;
+  begin
+    return temp;
+  end resolution12;
+  subtype array_rec_2cons_state is resolution12 record_2cons_array;
+
+  constant C66 : array_rec_2cons_state:= C52; 
+
+  function complex_scalar(s : array_rec_2cons_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_2cons_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component c03s02b01x01p19n01i00485ent_a1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : c03s02b01x01p19n01i00485ent_a1 use entity work.c03s02b01x01p19n01i00485ent_a(c03s02b01x01p19n01i00485ent_a);
+
+  signal S1 : array_rec_2cons_state;
+  signal S2 : array_rec_2cons_state;
+  signal S3 : array_rec_2cons_state:= C66;
+BEGIN
+  T1: c03s02b01x01p19n01i00485ent_a1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00485" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00485 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00485arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc486.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc486.vhd
new file mode 100644
index 0000000..33a8db0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc486.vhd
@@ -0,0 +1,270 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc486.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY model IS
+  PORT
+    (
+      F1:  OUT     integer := 3;
+      F2:  INOUT    integer := 3;
+      F3:  IN    integer
+      );
+END model;
+
+architecture model of model is
+begin
+  process
+  begin
+    wait for 1 ns;
+    assert F3= 3
+      report"wrong initialization of F3 through type conversion" severity failure;
+    assert F2 = 3
+      report"wrong initialization of F2 through type conversion" severity failure;
+    wait;
+  end process;
+end;
+
+
+ENTITY c03s02b01x01p19n01i00486ent IS
+END c03s02b01x01p19n01i00486ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00486arch OF c03s02b01x01p19n01i00486ent IS
+
+
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type column    is range 1 to 2;
+  type row    is range 1 to 8;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector    is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector    is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st    is  real_vector(0 to 15);
+  subtype time_vector_st    is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+
+  type boolean_cons_vectorofvector    is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector    is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector    is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector    is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                            end record;
+
+
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+
+  constant C26 : boolean_cons_vectorofvector    := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector    := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector    := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector    := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector    := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector    := (others => (others => C9));
+
+  constant C41 : s2boolean_cons_vector    := (others => (others => C1));
+  constant C42 : s2bit_cons_vector    := (others => (others => C2));
+  constant C43 : s2char_cons_vector    := (others => (others => C3));
+  constant C44 : s2severity_level_cons_vector    := (others => (others => C4));
+  constant C45 : s2integer_cons_vector    := (others => (others => C5));
+  constant C46 : s2real_cons_vector    := (others => (others => C6));
+  constant C47 : s2time_cons_vector    := (others => (others => C7));
+  constant C48 : s2natural_cons_vector    := (others => (others => C8));
+  constant C49 : s2positive_cons_vector    := (others => (others => C9));
+
+  constant C50 : record_std_package    := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C51 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+  constant C52 : record_2cons_array    := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+
+  constant C70 : boolean_vector_st    :=(others => C1);
+  constant C71 : severity_level_vector_st   :=(others => C4);
+  constant C72 : integer_vector_st   :=(others => C5);
+  constant C73 : real_vector_st      :=(others => C6);
+  constant C74 : time_vector_st      :=(others => C7);
+  constant C75 : natural_vector_st   :=(others => C8);
+  constant C76 : positive_vector_st   :=(others => C9);
+
+  constant C77 : record_array_st    := (C70,C71,C72,C73,C74,C75,C76);
+  constant C55 : record_of_records    := (C50,C51,C52,C53,C77);
+
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  function resolution13(i:in array_rec_rec) return record_of_records is
+    variable temp : record_of_records :=C55 ;
+  begin
+    return temp;
+  end resolution13;
+
+  subtype array_rec_rec_state is resolution13 record_of_records;   
+
+  constant C66 : array_rec_rec_state   := C55; 
+
+  function complex_scalar(s : array_rec_rec_state) return integer is
+  begin
+    return 3;
+  end complex_scalar;
+  function scalar_complex(s : integer) return array_rec_rec_state is
+  begin
+    return C66;
+  end scalar_complex;
+  component model1
+    PORT
+      (    
+        F1:  OUT     integer;
+        F2:  INOUT    integer;
+        F3:  IN    integer
+        );
+  end component;
+  for T1 : model1 use entity work.model(model);
+
+  signal S1 : array_rec_rec_state;
+  signal S2 : array_rec_rec_state;
+  signal S3 : array_rec_rec_state:= C66;
+BEGIN
+  T1: model1
+    port map (
+      scalar_complex(F1) => S1,
+      scalar_complex(F2) => complex_scalar(S2),
+      F3 => complex_scalar(S3)
+      );
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT((S1 = C66) and (S2 = C66)) 
+      report "***PASSED TEST: c03s02b01x01p19n01i00486" 
+      severity NOTE;
+    assert ((S1 = C66) and (S2 = C66)) 
+      report "***FAILED TEST: c03s02b01x01p19n01i00486 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00486arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc487.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc487.vhd
new file mode 100644
index 0000000..330e7c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc487.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc487.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p20n01i00487ent IS
+END c03s02b01x01p20n01i00487ent;
+
+ARCHITECTURE c03s02b01x01p20n01i00487arch OF c03s02b01x01p20n01i00487ent IS
+  type MEM is array (positive range <>) of BIT;
+  type ME1 is array (natural range <>) of Integer;
+  subtype ME2 is ME1(0 to 3);
+  subtype M1 is MEM (1 to 5);
+  procedure F2 (X1 : inout MEM) is
+  begin
+    assert NOT((X1'LOW = 1) and (X1'High = 5))
+      report "***PASSED TEST: c03s02b01x01p20n01i00487"
+      severity NOTE;
+    assert ((X1'LOW = 1) and (X1'High = 5))
+      report "***FAILED TEST: c03s02b01x01p20n01i00487 - For an interface object of mode out, inout, or linkage, if the formal part does not contain a type conversion function, then the index ranges are obtained from the object denoted by the actual designator."
+      severity ERROR;
+  end F2;
+BEGIN
+  TESTING: PROCESS
+    variable S1 : M1 := "01110";
+  BEGIN
+    F2(S1) ;  -- No_failure_here
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p20n01i00487arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc488.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc488.vhd
new file mode 100644
index 0000000..b0c4be7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc488.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc488.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00488ent IS
+END c03s02b02x00p01n01i00488ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00488arch OF c03s02b02x00p01n01i00488ent IS
+  type T0 is record
+               el1 : real;
+               el2 : real;
+               el3 : real;
+               el4 : real;
+               el5 : real;
+               el6 : real;
+               el7 : real;
+               el8 : real;
+               el9 : real;
+               el10 : real;
+             end record;
+  type T1 is record
+               el1 : real;
+               el2 : real;
+               el3 : real;
+               el4 : real;
+               el5 : real;
+               el6 : real;
+             end record;
+  type T2 is record
+               el5 : real;
+               el6 : real;
+               el7 : real;
+             end record;
+  function FUNC1(recd1: T0) return T1 is
+    variable recd2:T1;
+  begin -- procedure FUNC1
+    recd2.el1 := recd1.el6;
+    recd2.el2 := recd1.el1;
+    recd2.el3 := recd1.el3;
+    recd2.el4 := recd1.el2;
+    recd2.el5 := recd1.el6;
+    recd2.el6 := recd1.el10;
+    return recd2;
+  end FUNC1;
+
+  function FUNC3(recd1: T0) return T2 is
+    variable recd2:T2;
+  begin -- procedure FUNC3
+    recd2.el5 := recd1.el5;
+    recd2.el6 := recd1.el6;
+    recd2.el7 := recd1.el1;
+    return recd2;
+  end FUNC3;
+  
+  function FUNC4(recd1: T2) return T2 is
+    variable recd2:T2;
+  begin -- procedure FUNC4
+    recd2.el5 := recd1.el7;
+    recd2.el6 := recd1.el5;
+    recd2.el7 := recd1.el5;
+    return recd2;
+  end FUNC4;
+
+BEGIN
+  TESTING: PROCESS
+    variable rec1: T0;
+    variable v1,v2:T1;
+    variable v3,v4:T2;
+  BEGIN
+    rec1 := (1.1,2.2,3.3,4.4,5.5,6.6,7.7,8.8,9.9,10.01);
+    wait for 1 ns;
+    v1 := FUNC1(rec1);
+    v3 := FUNC3(rec1);
+    v4 := FUNC4(v3);
+    wait for 1 ns;
+    assert NOT( (v1 = (6.6,1.1,3.3,2.2,6.6,10.01))    AND
+                (v3 = (5.5,6.6,1.1))       AND
+                (v4 = (1.1,5.5,5.5)))
+      report "***PASSED TEST: c03s02b02x00p01n01i00488"
+      severity NOTE;
+    assert (    (v1 = (6.6,1.1,3.3,2.2,6.6,10.01))    AND
+                (v3 = (5.5,6.6,1.1))       AND
+                (v4 = (1.1,5.5,5.5)))
+      report "***FAILED TEST: c03s02b02x00p01n01i00488 - Values of a record object consist of the value of its elements." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00488arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc489.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc489.vhd
new file mode 100644
index 0000000..a764d5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc489.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc489.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00489ent IS
+  type small is
+    record
+      bt : bit;
+      bv : bit_vector (11 downto 0);
+      r  : real range 0.0 to real'high;
+      bb : boolean;
+      i  : integer range 1 to 20;
+    end record;
+END c03s02b02x00p01n01i00489ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00489arch OF c03s02b02x00p01n01i00489ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A1 : small;
+    alias A1_bv : bit_vector (11 downto 0) is A1.bv;
+    alias A1_bt : bit is A1.bt;
+    alias A1_i  : integer is A1.i;
+    alias A1_r  : real is A1.r;
+    alias A1_bb : boolean is A1.bb;
+  BEGIN
+
+    assert NOT(   ( A1.bv = x"000")   and
+                  ( A1.bt = '0')      and
+                  ( A1.bb = false)   and
+                  ( A1.i  = 1)      and
+                  ( A1.r  = 0.0)      and
+                  ( A1_bv = x"000")   and
+                  ( A1_bt = '0')      and
+                  ( A1_bb = false)   and
+                  ( A1_i  = 1)      and
+                  ( A1_r  = 0.0)      )
+      report "***PASSED TEST: c03s02b02x00p01n01i00489"
+      severity NOTE;
+    assert (   ( A1.bv = x"000")   and
+               ( A1.bt = '0')      and
+               ( A1.bb = false)   and
+               ( A1.i  = 1)      and
+               ( A1.r  = 0.0)      and
+               ( A1_bv = x"000")   and
+               ( A1_bt = '0')      and
+               ( A1_bb = false)   and
+               ( A1_i  = 1)      and
+               ( A1_r  = 0.0)      )
+      report "***FAILED TEST: c03s02b02x00p01n01i00489 - Values of a record object consist of the value of its elements." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00489arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc490.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc490.vhd
new file mode 100644
index 0000000..232ed5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc490.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc490.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00490ent IS
+END c03s02b02x00p01n01i00490ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00490arch OF c03s02b02x00p01n01i00490ent IS
+  type T0 is record
+               el1 : real;
+               el2 : real;
+               el3 : real;
+               el4 : real;
+               el5 : real;
+               el6 : real;
+               el7 : real;
+               el8 : real;
+               el9 : real;
+               el10 : real;
+             end record;
+  type T1 is record
+               el1 : real;
+               el2 : real;
+               el3 : real;
+               el4 : real;
+               el5 : real;
+               el6 : real;
+             end record;
+  type T2 is record
+               el5 : real;
+               el6 : real;
+               el7 : real;
+             end record;
+  function FUNC1(signal recd1: T0) return T1 is
+    variable recd2:T1;
+  begin -- procedure FUNC1
+    recd2.el1 := recd1.el6;
+    recd2.el2 := recd1.el1;
+    recd2.el3 := recd1.el3;
+    recd2.el4 := recd1.el2;
+    recd2.el5 := recd1.el6;
+    recd2.el6 := recd1.el10;
+    return recd2;
+  end FUNC1;
+  
+  function FUNC3(signal recd1: T0) return T2 is
+    variable recd2:T2;
+  begin -- procedure FUNC3
+    recd2.el5 := recd1.el5;
+    recd2.el6 := recd1.el6;
+    recd2.el7 := recd1.el1;
+    return recd2;
+  end FUNC3;
+  
+  function FUNC4(signal recd1: T2) return T2 is
+    variable recd2:T2;
+  begin -- procedure FUNC4
+    recd2.el5 := recd1.el7;
+    recd2.el6 := recd1.el5;
+    recd2.el7 := recd1.el5;
+    return recd2;
+  end FUNC4;
+  
+  signal rec1: T0;
+  signal s1,v2:T1;
+  signal s3,s4:T2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    rec1 <= (1.1,2.2,3.3,4.4,5.5,6.6,7.7,8.8,9.9,10.01);
+    wait for 1 ns;
+    s1 <= FUNC1(rec1);
+    s3 <= FUNC3(rec1);
+    wait for 1 ns;
+    s4 <= FUNC4(s3);
+    wait for 1 ns;
+    assert NOT( (s1 = (6.6,1.1,3.3,2.2,6.6,10.01))    AND
+                (s3 = (5.5,6.6,1.1))       AND
+                (s4 = (1.1,5.5,5.5)))
+      report "***PASSED TEST: c03s02b02x00p01n01i00490"
+      severity NOTE;
+    assert (    (s1 = (6.6,1.1,3.3,2.2,6.6,10.01))    AND
+                (s3 = (5.5,6.6,1.1))       AND
+                (s4 = (1.1,5.5,5.5)))
+      report "***FAILED TEST: c03s02b02x00p01n01i00490 - Values of a record object consist of the value of its elements." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00490arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc491.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc491.vhd
new file mode 100644
index 0000000..b7f6afb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc491.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc491.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00491ent IS
+END c03s02b02x00p01n01i00491ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00491arch OF c03s02b02x00p01n01i00491ent IS
+  type etype is (one,two,three,four,five,six,seven);
+  type T1 is record
+               t    : time;
+               b    : bit;
+               i    : integer;
+               bo    : boolean;
+               r    : real;
+               bv    : bit_vector (0 to 3);
+               e    : etype;
+               c    : character;
+             end record;
+  function FUNC1 return T1 is
+    variable recd2:T1;
+  begin
+    recd2.bv    := "0001";
+    recd2.b    := '1';
+    recd2.bo    := true;
+    recd2.i    := 777;
+    recd2.r    := 333.767;
+    recd2.t    := 44 ms;
+    recd2.e    := seven;
+    recd2.c    := '%';
+    return recd2;
+  end FUNC1;
+BEGIN
+  TESTING: PROCESS
+    variable var2: T1;
+    variable OkayCount: integer := 0;
+  BEGIN
+    wait for 1 ns;
+    var2 := (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    var2 := FUNC1;
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC1" severity note;
+    end if;
+    var2 := (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    if var2 = (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a') then
+      OkayCount := OkayCount + 1;
+    end if;
+    var2.i    := FUNC1.i;
+    var2.b    := FUNC1.b;
+    var2.bo := FUNC1.bo;
+    var2.bv := FUNC1.bv;
+    var2.r    := FUNC1.r;
+    var2.t    := FUNC1.t;
+    var2.e    := FUNC1.e;
+    var2.c    := FUNC1.c;
+    
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC1.element" severity note;
+    end if;
+    wait for 1 ns;
+    assert NOT( OkayCount = 3 )
+      report "***PASSED TEST: c03s02b02x00p01n01i00491"
+      severity NOTE;
+    assert ( OkayCount = 3 )
+      report "***FAILED TEST: c03s02b02x00p01n01i00491 - Problem assigning record subelements in function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00491arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc492.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc492.vhd
new file mode 100644
index 0000000..4361ef5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc492.vhd
@@ -0,0 +1,165 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc492.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00492ent IS
+END c03s02b02x00p01n01i00492ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00492arch OF c03s02b02x00p01n01i00492ent IS
+  type etype is (one,two,three,four,five,six,seven);
+  type TR is record
+               i    : integer;
+               b    : bit;
+               bo    : boolean;
+               bv    : bit_vector (0 to 3);
+               r    : real;
+               t    : time;
+               e    : etype;
+               c    : character;
+             end record;
+  type T1 is record
+               t    : time;
+               b    : bit;
+               i    : integer;
+               bo    : boolean;
+               r    : real;
+               bv    : bit_vector (0 to 3);
+               e    : etype;
+               c    : character;
+             end record;
+  function FUNC1(signal recd1: TR) return T1 is
+    variable recd2:T1;
+  begin
+    recd2.bv    := recd1.bv;
+    recd2.b    := recd1.b;
+    recd2.bo    := recd1.bo;
+    recd2.i    := recd1.i;
+    recd2.r    := recd1.r;
+    recd2.t    := recd1.t;
+    recd2.e    := recd1.e;
+    recd2.c    := recd1.c;
+    return recd2;
+  end FUNC1;
+  function FUNC2(signal recd1: TR) return integer is
+  begin
+    return recd1.i;
+  end;
+  function FUNC3(signal recd1: TR) return bit is
+  begin
+    return recd1.b;
+  end;
+  function FUNC4(signal recd1: TR) return boolean is
+  begin
+    return recd1.bo;
+  end;
+  function FUNC5(signal recd1: TR) return bit_vector is
+  begin
+    return recd1.bv;
+  end;
+  function FUNC6(signal recd1: TR) return real is
+  begin
+    return recd1.r;
+  end;
+  function FUNC7(signal recd1: TR) return time is
+  begin
+    return recd1.t;
+  end;
+  function FUNC8(signal recd1: TR) return etype is
+  begin
+    return recd1.e;
+  end;
+  function FUNC9(signal recd1: TR) return character is
+  begin
+    return recd1.c;
+  end;
+  
+  signal var1: TR;
+  signal var2: T1;
+  
+BEGIN
+  TESTING: PROCESS
+    variable OkayCount : integer := 0;
+  BEGIN
+    wait for 1 ns;
+    var2 <= (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    var1 <= (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%');
+    wait for 1 ns;
+    var2 <= FUNC1(var1);
+    wait for 1 ns;
+    assert var2.bv = "0001" report "var2.bv /= 0001" severity note;
+    assert var2.b = '1'    report "var2.b /= 1"     severity note;
+    assert var2.bo = true    report "var2.bo /= true" severity note;
+    assert var2.i = 777    report "var2.i /= 777"     severity note;
+    assert var2.r = 333.767 report "var2.r /= 333.767"    severity note;
+    assert var2.t = 44 ms    report "var2.t /= 44 ms" severity note;
+    assert var2.e = seven    report "var2.e /= seven" severity note;
+    assert var2.c = '%'    report "var2.c /= c"     severity note;
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC1" severity note;
+    end if;
+    var2 <= (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    wait for 1 ns;
+    if var2 = (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a') then
+      OkayCount := OkayCount + 1;
+    end if;
+    var2.i    <= FUNC2(var1);
+    var2.b    <= FUNC3(var1);
+    var2.bo <= FUNC4(var1);
+    var2.bv <= FUNC5(var1);
+    var2.r    <= FUNC6(var1);
+    var2.t    <= FUNC7(var1);
+    var2.e    <= FUNC8(var1);
+    var2.c    <= FUNC9(var1);
+    wait for 1 ns;
+    assert var2.bv = "0001" report "var2.bv /= 0001" severity note;
+    assert var2.b = '1'    report "var2.b /= 1"     severity note;
+    assert var2.bo = true    report "var2.bo /= true" severity note;
+    assert var2.i = 777    report "var2.i /= 777"     severity note;
+    assert var2.r = 333.767 report "var2.r /= 333.767" severity note;
+    assert var2.t = 44 ms    report "var2.t /= 44 ms" severity note;
+    assert var2.e = seven    report "var2.e /= seven" severity note;
+    assert var2.c = '%'    report "var2.c /= c"     severity note;
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC2-8" severity note;
+    end if;
+    wait for 1 ns;
+    assert NOT( OkayCount = 3 )
+      report "***PASSED TEST: c03s02b02x00p01n01i00492"
+      severity NOTE;
+    assert ( OkayCount = 3 )
+      report "***FAILED TEST: c03s02b02x00p01n01i00492 - Problem assigning record subelements in function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00492arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc493.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc493.vhd
new file mode 100644
index 0000000..706dfb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc493.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc493.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00493ent IS
+END c03s02b02x00p01n01i00493ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00493arch OF c03s02b02x00p01n01i00493ent IS
+  type etype is (one,two,three,four,five,six,seven);
+  type TR is record
+               i    : integer;
+               b    : bit;
+               bo    : boolean;
+               bv    : bit_vector (0 to 3);
+               r    : real;
+               t    : time;
+               e    : etype;
+               c    : character;
+             end record;
+  type T1 is record
+               t    : time;
+               b    : bit;
+               i    : integer;
+               bo    : boolean;
+               r    : real;
+               bv    : bit_vector (0 to 3);
+               e    : etype;
+               c    : character;
+             end record;
+  function FUNC1(recd1: TR) return T1 is
+    variable recd2:T1;
+  begin
+    recd2.bv    := recd1.bv;
+    recd2.b    := recd1.b;
+    recd2.bo    := recd1.bo;
+    recd2.i    := recd1.i;
+    recd2.r    := recd1.r;
+    recd2.t    := recd1.t;
+    recd2.e    := recd1.e;
+    recd2.c    := recd1.c;
+    return recd2;
+  end FUNC1;
+  function FUNC2(recd1: TR) return integer is
+  begin
+    return recd1.i;
+  end;
+  function FUNC3(recd1: TR) return bit is
+  begin
+    return recd1.b;
+  end;
+  function FUNC4(recd1: TR) return boolean is
+  begin
+    return recd1.bo;
+  end;
+  function FUNC5(recd1: TR) return bit_vector is
+  begin
+    return recd1.bv;
+  end;
+  function FUNC6(recd1: TR) return real is
+  begin
+    return recd1.r;
+  end;
+  function FUNC7(recd1: TR) return time is
+  begin
+    return recd1.t;
+  end;
+  function FUNC8(recd1: TR) return etype is
+  begin
+    return recd1.e;
+  end;
+  function FUNC9(recd1: TR) return character is
+  begin
+    return recd1.c;
+  end;
+  
+BEGIN
+  TESTING: PROCESS
+    variable var1: TR;
+    variable var2: T1;
+    variable OkayCount: integer := 0;
+  BEGIN
+    wait for 1 ns;
+    var2 := (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    var1 := (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%');
+    var2 := FUNC1(var1);
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC1" severity note;
+    end if;
+    var2 := (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a');
+    if var2 = (bv=>"0000",b=>'0',bo=>false,i=>0,r=>0.0,t=>1 ms,e=>one,c=>'a') then
+      OkayCount := OkayCount + 1;
+    end if;
+    var2.i    := FUNC2(var1);wait for 1 ns;assert var2.i=777 report "i no good" severity note;
+    var2.b    := FUNC3(var1);wait for 1 ns;assert var2.b='1' report "b no good" severity note;
+    var2.bo := FUNC4(var1);wait for 1 ns;assert var2.bo=true report "bo no good" severity note;
+    var2.bv := FUNC5(var1);wait for 1 ns;assert var2.bv="0001" report "bv no good" severity note;
+    var2.r    := FUNC6(var1);wait for 1 ns;assert var2.r=333.767 report "r no good" severity note;
+    var2.t    := FUNC7(var1);wait for 1 ns;assert var2.t=44 ms report "t no good" severity note;
+    var2.e    := FUNC8(var1);wait for 1 ns;assert var2.e=seven report "e no good" severity note;
+    var2.c    := FUNC9(var1);wait for 1 ns;assert var2.c='%' report "c no good" severity note;
+    
+    if var2 = (bv=>"0001",b=>'1',bo=>true,i=>777,r=>333.767,t=>44 ms,e=>seven,c=>'%') then
+      OkayCount := OkayCount + 1;
+    else
+      assert false report "bad return on FUNC2-9" severity note;
+    end if;
+    wait for 1 ns; 
+    assert NOT( OkayCount = 3 )
+      report "***PASSED TEST: c03s02b02x00p01n01i00493"
+      severity NOTE;
+    assert ( OkayCount = 3 )
+      report "***FAILED TEST: c03s02b02x00p01n01i00493 - Problem assigning record subelements in function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00493arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc494.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc494.vhd
new file mode 100644
index 0000000..54be917
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc494.vhd
@@ -0,0 +1,146 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc494.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00494ent IS
+END c03s02b02x00p01n01i00494ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00494arch OF c03s02b02x00p01n01i00494ent IS
+  type colors is (orange,blue,red,black,white,magenta,ochre,yellow,green);
+  type TR is RECORD
+               i    : integer;
+               ch    : character;
+               bi    : bit;
+               bool    : boolean;
+               bv    : bit_vector (3000 to 3007);
+               r    : real;
+               str    : STRING (1 to 7);
+               ti    : TIME;
+               color    : colors;
+             END RECORD;
+  type TY is array(integer range <>) of TR;
+  subtype T0 is TY (1 to 10);
+  subtype T1 is TY (1 to 6);
+  subtype T2 is TY (5 to 7);
+  
+  function FUNC1(array1: T0) return T1 is -- formal param object class defaults to constant
+    variable array2:T1;
+  begin -- procedure FUNC1
+    array2 := array1(6) & array1(1) & array1(3) & array1(2) & array1(6) & array1(10); --indexed names
+    return array2;
+  end FUNC1;
+  
+  function FUNC2(array1: TY) return T1 is
+    variable array2:T1;
+  begin -- procedure FUNC2
+    array2 := array1(6) & array1(1) & array1(3) & array1(2) & array1(6) & array1(10); --indexed names
+    return array2;
+  end FUNC2;
+  
+  function FUNC3(array1: T0) return T2 is
+    variable array2:T2;
+  begin -- procedure FUNC3
+    array2 := array1(5 to 6) & array1(1 to 1); --slices
+    return array2;
+  end FUNC3;
+  
+  function FUNC4(array1: T2) return T2 is
+    variable array2:T2;
+  begin -- procedure FUNC4
+    array2 := array1 (7 to 7) & array1(5 to 5) &
+              array1(5 to 5); --slices
+    return array2;
+  end FUNC4; 
+BEGIN
+  TESTING: PROCESS
+    variable arr1: T0;
+    variable v1,v2:T1;
+    variable v3,v4:T2;
+  BEGIN
+    arr1(1) := (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange);
+    arr1(2) := (2,'b','1',true, "00000010",2.2,"two    ",2.2 ms,blue);
+    arr1(3) := (3,'c','0',false,"00000011",3.3,"three  ",3.3 ms,red);
+    arr1(4) := (4,'d','1',true, "00000100",4.4,"four   ",4.4 ms,black);
+    arr1(5) := (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white);
+    arr1(6) := (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta);
+    arr1(7) := (7,'g','0',false,"00000111",7.7,"seven  ",7.7 ms,ochre);
+    arr1(8) := (8,'h','1',true, "00001000",8.8,"eight  ",8.8 ms,yellow);
+    arr1(9) := (9,'i','0',false,"00001001",9.9,"nine   ",9.9 ms,green);
+    arr1(10):=(10,'j','1',true, "00001010",10.01,"ten    ",10.01 ms,white);
+    wait for 1 ns;
+    v1 := FUNC1(arr1);
+    v2 := FUNC2(arr1);
+    v3 := FUNC3(arr1);
+    v4 := FUNC4(v3);
+    
+    wait for 1 ns;
+    assert NOT( (v1(1) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                (v1(2) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                (v1(3) = (3,'c','0',false,"00000011",3.3,"three  ",3.3 ms,red)) AND
+                (v1(4) = (2,'b','1',true, "00000010",2.2,"two    ",2.2 ms,blue)) AND
+                (v1(5) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                (v1(6) = (10,'j','1',true, "00001010",10.01,"ten    ",10.01 ms,white)) AND
+                (v2(1) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                (v2(2) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                (v2(3) = (3,'c','0',false,"00000011",3.3,"three  ",3.3 ms,red)) AND
+                (v2(4) = (2,'b','1',true, "00000010",2.2,"two    ",2.2 ms,blue)) AND
+                (v2(5) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                (v2(6) = (10,'j','1',true, "00001010",10.01,"ten    ",10.01 ms,white)) AND
+                (v3(5) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)) AND
+                (v3(6) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                (v3(7) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                (v4(5) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                (v4(6) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)) AND
+                (v4(7) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)))
+      report "***PASSED TEST: c03s02b02x00p01n01i00494"
+      severity NOTE;
+    assert      ( (v1(1) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                  (v1(2) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                  (v1(3) = (3,'c','0',false,"00000011",3.3,"three  ",3.3 ms,red)) AND
+                  (v1(4) = (2,'b','1',true, "00000010",2.2,"two    ",2.2 ms,blue)) AND
+                  (v1(5) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                  (v1(6) = (10,'j','1',true, "00001010",10.01,"ten    ",10.01 ms,white)) AND
+                  (v2(1) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                  (v2(2) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                  (v2(3) = (3,'c','0',false,"00000011",3.3,"three  ",3.3 ms,red)) AND
+                  (v2(4) = (2,'b','1',true, "00000010",2.2,"two    ",2.2 ms,blue)) AND
+                  (v2(5) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                  (v2(6) = (10,'j','1',true, "00001010",10.01,"ten    ",10.01 ms,white)) AND
+                  (v3(5) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)) AND
+                  (v3(6) = (6,'f','1',true, "00000110",6.6,"six    ",6.6 ms,magenta)) AND
+                  (v3(7) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                  (v4(5) = (1,'a','0',false,"00000001",1.1,"one    ",1.1 ms,orange)) AND
+                  (v4(6) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)) AND
+                  (v4(7) = (5,'e','0',false,"00000101",5.5,"five   ",5.5 ms,white)))
+      report "***FAILED TEST:c03s02b02x00p01n01i00494 - Problem assigning record subelements in function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00494arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc495.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc495.vhd
new file mode 100644
index 0000000..df66da6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc495.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc495.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p01n01i00495ent IS
+END c03s02b02x00p01n01i00495ent;
+
+ARCHITECTURE c03s02b02x00p01n01i00495arch OF c03s02b02x00p01n01i00495ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type tRecord1 is
+      record
+        element1 : INTEGER;
+        element2 : CHARACTER;
+      end record;
+
+    type tRecord2 is
+      record
+        element3 : INTEGER;
+        element4 : CHARACTER;
+        element5 : tRecord1;
+      end record;
+
+    variable V1 : tRecord1 := (1, '1');
+    variable V2 : tRecord2 := (2, '2', (3, '3'));
+  BEGIN
+    assert V1.element1 = 1;
+    assert V1.element2 = '1';
+    assert V2.element3 = 2;
+    assert V2.element4 = '2';
+    assert V2.element5.element1 = 3;
+    assert V2.element5.element2 = '3';
+    wait for 1 ns;
+    assert NOT(   V1.element1 = 1      and
+                  V1.element2 = '1'   and
+                  V2.element3 = 2      and
+                  V2.element4 = '2'   and
+                  V2.element5.element1 = 3   and
+                  V2.element5.element2 = '3'   ) 
+      report "***PASSED TEST: c03s02b02x00p01n01i00495"
+      severity NOTE;
+    assert (   V1.element1 = 1      and
+               V1.element2 = '1'   and
+               V2.element3 = 2      and
+               V2.element4 = '2'   and
+               V2.element5.element1 = 3   and
+               V2.element5.element2 = '3'   ) 
+      report "***FAILED TEST: c03s02b02x00p01n01i00495 - Record type in record type declartion test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p01n01i00495arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc496.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc496.vhd
new file mode 100644
index 0000000..fc5f062
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc496.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc496.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00496ent IS
+END c03s02b02x00p02n01i00496ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00496arch OF c03s02b02x00p02n01i00496ent IS
+  type rec_type is
+    record
+      x : bit;
+      y : integer;
+      z : boolean;
+    end record;  -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : rec_type;
+  BEGIN
+    k.x := '1';
+    k.y := 5;
+    k.z := true;
+    assert NOT(k.x='1' and k.y=5 and k.z=true)
+      report "***PASSED TEST: c03s02b02x00p02n01i00496"
+      severity NOTE;
+    assert (k.x='1' and k.y=5 and k.z=true)
+      report "***FAILED TEST: c03s02b02x00p02n01i00496 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00496arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc497.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc497.vhd
new file mode 100644
index 0000000..5c393f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc497.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc497.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00497ent IS
+END c03s02b02x00p02n01i00497ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00497arch OF c03s02b02x00p02n01i00497ent IS
+  type rec_type is
+    record
+      x : bit;
+      y : integer;
+      z : boolean;
+    end record;  -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k,kk : rec_type;
+  BEGIN
+    k.x := '1';
+    k.y := 5;
+    k.z := true;
+    kk  := k;
+    assert NOT(kk.x='1' and kk.y=5 and kk.z=true)
+      report "***PASSED TEST: c03s02b02x00p02n01i00497"
+      severity NOTE;
+    assert (kk.x='1' and kk.y=5 and kk.z=true)
+      report "***FAILED TEST: c03s02b02x00p02n01i00497 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00497arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc498.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc498.vhd
new file mode 100644
index 0000000..114b1e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc498.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc498.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00498ent IS
+END c03s02b02x00p02n01i00498ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00498arch OF c03s02b02x00p02n01i00498ent IS
+  type Month_name is (jan, dec);
+  type Date is
+    record
+      Day      : integer range 1 to 31;
+      Month   : Month_name;
+      Year   : integer range 0 to 4000;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable k : Date;
+  BEGIN
+    k.Day   :=   16;
+    k.Month   :=   jan;
+    k.Year   :=   1993;   
+    assert NOT(k.Day=16 and k.Month=jan and k.Year =1993)
+      report "***PASSED TEST: c03s02b02x00p02n01i00498"
+      severity NOTE;
+    assert (k.Day=16 and k.Month=jan and k.Year =1993)
+      report "***FAILED TEST: c03s02b02x00p02n01i00498 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00498arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc499.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc499.vhd
new file mode 100644
index 0000000..e4eb17f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc499.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc499.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00499ent IS
+END c03s02b02x00p02n01i00499ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00499arch OF c03s02b02x00p02n01i00499ent IS
+  type rec_type is
+    record
+      x : integer;
+      y : real;
+      z : boolean;
+      b : bit;
+    end record;
+  type rec2_type is
+    record
+      x : integer;
+      y : integer;
+      z : boolean;
+      b : rec_type;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable v2 : rec2_type;
+  BEGIN
+    v2.x  := 12;
+    v2.y  := 10;
+    v2.z  := true;
+    v2.b.b  := bit'('0');
+    assert NOT(v2.x=12 and v2.y=10 and v2.z=true and v2.b.b ='0')
+      report "***PASSED TEST: c03s02b02x00p02n01i00499"
+      severity NOTE;
+    assert (v2.x=12 and v2.y=10 and v2.z=true and v2.b.b ='0')
+      report "***FAILED TEST: c03s02b02x00p02n01i00499 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00499arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc500.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc500.vhd
new file mode 100644
index 0000000..2bdf462
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc500.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc500.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00500ent IS
+END c03s02b02x00p02n01i00500ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00500arch OF c03s02b02x00p02n01i00500ent IS
+  type rec_type is
+    record
+      x : integer;
+      y : real;
+      z : boolean;
+      b : bit;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable v1 : rec_type;
+  BEGIN
+    v1.x  := 12;
+    v1.y  := 1.2;
+    v1.z  := true;
+    v1.b  := bit'('0');
+    assert NOT(v1.x=12 and v1.y=1.2 and v1.z=true and v1.b='0')
+      report "***PASSED TEST: c03s02b02x00p02n01i00500"
+      severity NOTE;
+    assert (v1.x=12 and v1.y=1.2 and v1.z=true and v1.b='0')
+      report "***FAILED TEST: c03s02b02x00p02n01i00500 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00500arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc501.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc501.vhd
new file mode 100644
index 0000000..1459d27
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc501.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc501.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00501ent IS
+END c03s02b02x00p02n01i00501ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00501arch OF c03s02b02x00p02n01i00501ent IS
+  type rec_type is
+    record
+      x : integer;
+      y : integer;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable v1 : rec_type;
+  BEGIN
+    v1.x  := 12;
+    v1.y  := v1.x * 111;
+    assert NOT(v1.x=12 and v1.y=1332) 
+      report "***PASSED TEST: c03s02b02x00p02n01i00501"
+      severity NOTE;
+    assert (v1.x=12 and v1.y=1332) 
+      report "***FAILED TEST: c03s02b02x00p02n01i00501 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00501arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc503.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc503.vhd
new file mode 100644
index 0000000..a196805
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc503.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc503.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p03n01i00503ent IS
+END c03s02b02x00p03n01i00503ent;
+
+ARCHITECTURE c03s02b02x00p03n01i00503arch OF c03s02b02x00p03n01i00503ent IS
+  type R2 is record
+               R11,R12 : INTEGER;
+               R21,R22,R23 : BOOLEAN;
+             end record;
+BEGIN
+  TESTING: PROCESS
+    variable k : R2;
+  BEGIN
+    k.R11   := 1;
+    k.R12   := 2;
+    k.R21   := true;
+    k.R22   := false;
+    k.R23   := true;
+    wait for 2 ns;
+    assert NOT(k.R11=1 and k.R12=2 and k.R21=true and k.R22=false and k.R23=true)
+      report "***PASSED TEST: c03s02b02x00p03n01i00503"
+      severity NOTE;
+    assert (k.R11=1 and k.R12=2 and k.R21=true and k.R22=false and k.R23=true)
+      report "***FAILED TEST: c03s02b02x00p03n01i00503 - A multiple object declaration is equivalent to a sequence of the corresponding number of single object declarations."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p03n01i00503arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc505.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc505.vhd
new file mode 100644
index 0000000..f961fd8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc505.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc505.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p06n01i00505ent IS
+  subtype    DAY1    is INTEGER range 1 to 31;
+  type       MONTH1    is (   January, February, March, April, May, June, July,
+                              August, September, October, November, December);
+END c03s02b02x00p06n01i00505ent;
+
+ARCHITECTURE c03s02b02x00p06n01i00505arch OF c03s02b02x00p06n01i00505ent IS
+  type DATE1 is record
+                  day:    DAY1;
+                  month:  MONTH1;
+                  year:   INTEGER range 0 to 4000;
+                end record;
+  type EVENT is record
+                  text:   STRING (1 to 20);
+                  date:   DATE1;
+                end record;
+  signal event_signal : EVENT;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    event_signal <= (text => "Go to Wall Street NY",
+                     date => (27, January, 1991)) after 10 ns;
+    wait for 20 ns;
+    assert NOT( event_signal.text = "Go to Wall Street NY" )
+      report "***PASSED TEST: c03s02b02x00p06n01i00505"
+      severity NOTE;
+    assert ( event_signal.text = "Go to Wall Street NY" )
+      report "***FAILED TEST: c03s02b02x00p06n01i00505 - Element declaration test in record type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p06n01i00505arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc512.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc512.vhd
new file mode 100644
index 0000000..e404b53
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc512.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc512.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p07n01i00512ent IS
+END c03s02b02x00p07n01i00512ent;
+
+ARCHITECTURE c03s02b02x00p07n01i00512arch OF c03s02b02x00p07n01i00512ent IS
+  type DATE is
+    record
+      DAY,D1,D2  : Integer;
+      MONTH : Integer;
+      YEAR : Integer;
+    end record;
+  type DAT is
+    record
+      DAY : Integer;
+      D1  : Integer;
+      D2  : Integer;
+      MONTH : Integer;
+      YEAR : Integer;
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : DATE    := (5,5,5,10,15) ;
+    variable V2 : DAT    := (5,5,5,10,15);
+  BEGIN
+    assert NOT(V1.D1 = V2.D1 and V1.D2 = V2.D2 and V1.DAY = V2.DAY and V1.Month = V2.Month and V1.Year = V2.Year )
+      report "***PASSED TEST: c03s02b02x00p07n01i00512"
+      severity NOTE;
+    assert (V1.D1 = V2.D1 and V1.D2 = V2.D2 and V1.DAY = V2.DAY and V1.Month = V2.Month and V1.Year = V2.Year )
+      report "***FAILED TEST: c03s02b02x00p07n01i00512 - An element declaration with several identifiers is equivalent to a sequence of single element declarations."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p07n01i00512arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc513.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc513.vhd
new file mode 100644
index 0000000..3ee8305
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc513.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc513.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p02n01i00513ent IS
+END c03s03b00x00p02n01i00513ent;
+
+ARCHITECTURE c03s03b00x00p02n01i00513arch OF c03s03b00x00p02n01i00513ent IS
+  type a is range 1 to 10;
+  type b is access a;   -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k :b;
+  BEGIN
+    assert NOT(k = null)
+      report "***PASSED TEST: c03s03b00x00p02n01i00513"
+      severity NOTE;
+    assert ( k = null )
+      report "***FAILED TEST: c03s03b00x00p02n01i00513 - In the access type definition, the reserved word access must be followed by a subtype definition."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p02n01i00513arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc515.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc515.vhd
new file mode 100644
index 0000000..298bb5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc515.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc515.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n01i00515ent IS
+END c03s03b00x00p03n01i00515ent;
+
+ARCHITECTURE c03s03b00x00p03n01i00515arch OF c03s03b00x00p03n01i00515ent IS
+  type A is access integer;
+BEGIN
+  TESTING: PROCESS
+    variable V: A ;
+  BEGIN
+    assert NOT(V = null)
+      report "***PASSED TEST: c03s03b00x00p03n01i00515"
+      severity NOTE;
+    assert ( V = null )
+      report "***FAILED TEST: c03s03b00x00p03n01i00515 - The null value of an access type is the default initial value of the type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n01i00515arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc516.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc516.vhd
new file mode 100644
index 0000000..c03d7bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc516.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc516.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00516ent IS
+END c03s03b00x00p03n04i00516ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00516arch OF c03s03b00x00p03n04i00516ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    type color is (red, green, blue);
+    constant azure : color := blue;
+    constant first : color := color'low;
+
+    type enum_ptr is access color;
+    variable v_enum_ptr1: enum_ptr := new color'(blue);
+    variable v_enum_ptr2: enum_ptr;
+    variable v_enum_ptr3: enum_ptr := v_enum_ptr1;
+    variable v_enum_ptr4: enum_ptr := new color'(red);
+    variable v_enum_ptr5: enum_ptr := v_enum_ptr4;
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+
+    assert v_enum_ptr1.all = blue;
+    if (v_enum_ptr1.all = blue) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_enum_ptr2     = null;
+    if (v_enum_ptr2     = null) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_enum_ptr3.all = blue;
+    if (v_enum_ptr3.all = blue) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_enum_ptr4.all = red;
+    if (v_enum_ptr4.all = red) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_enum_ptr5.all = red;
+    if (v_enum_ptr5.all = red) then
+      OKtest := OKtest + 1;
+    end if;
+
+    v_enum_ptr2 := new color'(green);
+
+    assert v_enum_ptr2.all = green;
+    if (v_enum_ptr2.all = green) then
+      OKtest := OKtest + 1;
+    end if;
+
+    assert (v_enum_ptr3.all = color'succ(green));
+    if (v_enum_ptr3.all = color'succ(green)) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr5.all = color'pred(v_enum_ptr2.all));
+    if (v_enum_ptr5.all = color'pred(v_enum_ptr2.all)) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (color'pred(v_enum_ptr3.all) = green);
+    if (color'pred(v_enum_ptr3.all) = green) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr5.all = color'low);
+    if (v_enum_ptr5.all = color'low) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr3.all = color'high);
+    if (v_enum_ptr3.all = color'high) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr5.all = color'left);
+    if (v_enum_ptr5.all = color'left) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr3.all = color'right);
+    if (v_enum_ptr3.all = color'right) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_enum_ptr3.all > v_enum_ptr5.all) = true;
+    if (v_enum_ptr3.all > v_enum_ptr5.all) then
+      OKtest := OKtest + 1;
+    end if;
+
+    assert NOT(OKtest = 14) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00516"
+      severity NOTE;
+    assert (OKtest = 14) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00516 - Enumeration type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00516arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc517.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc517.vhd
new file mode 100644
index 0000000..a874420
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc517.vhd
@@ -0,0 +1,1380 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc517.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c03s03b00x00p03n04i00517pkg IS
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     8;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)        
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Scalar type for subelements
+--
+  SUBTYPE st_scl1 IS CHARACTER                              ;
+  SUBTYPE st_scl3 IS INTEGER   RANGE   1   TO   INTEGER'HIGH;
+  SUBTYPE st_scl4 IS REAL      RANGE 0.0   TO         1024.0;
+  
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Records of scalars
+--
+  TYPE t_scre_1 IS RECORD
+                     left   :  st_scl1;
+                     second :  TIME;
+                     third  :  st_scl3;
+                     right  :  st_scl4;
+                   END RECORD;
+--
+--          Unconstrained arrays of scalars
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
+  
+  TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
+                          st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+--
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
+  
+  SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 ,                         -- ( i2, i1 ) of CHAR
+                                st_ind1 );
+  SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 ,                         -- ( i3, i2, i1) of CHAR
+                                st_ind2 ,
+                                st_ind1 );
+  SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 ,                         -- ( i4, i3, i2, i1 ) of CHAR
+                                st_ind3 ,
+                                st_ind2 ,
+                                st_ind1 );
+--
+--
+--          constrained arrays of composites
+--
+  TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1;          -- ( i1 ) is RECORD of scalar
+  TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1;          --             ( i2 )( i1 ) is CHAR
+  TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2;          --       ( i3 )( i2 )( i1 ) is CHAR
+  TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3;          -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
+  
+  TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1;          --       ( i3 )( i2,   i1 ) is CHAR
+  TYPE t_cca2_2 IS ARRAY (st_ind4,                       -- ( i4,   i3 )( i2,   i1 ) of CHAR
+                          st_ind3) OF t_csa2_1;
+  TYPE t_cca3_1 IS ARRAY (st_ind4,                       -- ( i4,   i3,   i2 )( i1 ) of CHAR
+                          st_ind3,
+                          st_ind2) OF t_csa1_1;
+  TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1;          -- ( i4 )( i3,   i2,   i1 ) is CHAR
+--
+--          Records of composites
+--
+  TYPE t_cmre_1 IS RECORD
+                     left   :  t_csa1_1;                                   -- .fN(i1) is CHAR
+                     second :  t_scre_1;                                   -- .fN.fN
+                   END RECORD;
+
+  TYPE t_cmre_2 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_csa1_1;                               --        .fN(i1) is CHAR        
+                   END RECORD;
+--
+--          Mixed Records/arrays
+--
+  TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2;          --    (i3).fN(i1) is CHAR        
+  TYPE t_cmre_3 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_cca1_7;                               -- .fN(i3).fN(i1) is CHAR        
+                   END RECORD;
+  
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+  TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
+  TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
+  TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
+  TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
+  TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
+  TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
+  TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
+  TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
+  TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
+  TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
+  TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
+  TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
+  TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
+  TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
+  TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
+--
+--          Declaration of Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
+--
+--          Resolved SUBTYPE declaration
+--
+  SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
+  SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
+  SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
+  SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
+  SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
+  SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
+  SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
+  SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
+  SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
+  SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
+  SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
+  SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
+  SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
+  SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
+  SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
+  SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
+  SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
+  SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
+  SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
+  SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
+--
+--          Functions declarations for multi-dimensional comosite values
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
+  
+-- -------------------------------------------------------------------------------------------
+--      Data values for Composite Types
+-- -------------------------------------------------------------------------------------------
+  CONSTANT CX_scl1 : st_scl1 := 'X' ;
+  CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
+  CONSTANT C1_scl1 : st_scl1 := 'A' ;
+  CONSTANT C2_scl1 : st_scl1 := 'Z' ;
+  
+  CONSTANT CX_scl2 : TIME := 99 fs ;
+  CONSTANT C0_scl2 : TIME := TIME'LEFT ;
+  CONSTANT C1_scl2 : TIME := 0 fs;
+  CONSTANT C2_scl2 : TIME := 2 ns;
+  
+  CONSTANT CX_scl3 : st_scl3 :=  15 ;
+  CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
+  CONSTANT C1_scl3 : st_scl3 :=   6 ;
+  CONSTANT C2_scl3 : st_scl3 :=   8 ;
+  
+  CONSTANT CX_scl4 : st_scl4 := 99.9 ;
+  CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
+  CONSTANT C1_scl4 : st_scl4 :=  1.0 ;
+  CONSTANT C2_scl4 : st_scl4 :=  2.1 ;
+  
+  CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
+  CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
+  CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
+  CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
+  
+  CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
+  CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
+  CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
+  CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
+                                     OTHERS                      =>C0_scl1);
+  
+  CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
+  CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
+  CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
+  CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
+                                     OTHERS                      =>C0_scl2);
+  
+  CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
+  CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
+  CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
+  CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
+                                     OTHERS                      =>C0_scl3);
+  
+  CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
+  CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
+  CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
+  CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
+                                     OTHERS                      =>C0_scl4);
+--
+  CONSTANT CX_csa2_1 : t_csa2_1 ;
+  CONSTANT C0_csa2_1 : t_csa2_1 ;
+  CONSTANT C1_csa2_1 : t_csa2_1 ;
+  CONSTANT C2_csa2_1 : t_csa2_1 ;
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 ;
+  CONSTANT C0_csa3_1 : t_csa3_1 ;
+  CONSTANT C1_csa3_1 : t_csa3_1 ;
+  CONSTANT C2_csa3_1 : t_csa3_1 ;
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 ;
+  CONSTANT C0_csa4_1 : t_csa4_1 ;
+  CONSTANT C1_csa4_1 : t_csa4_1 ;
+  CONSTANT C2_csa4_1 : t_csa4_1 ;
+--
+  CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
+  CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
+  CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
+  CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
+                                     C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 ); 
+  CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 ); 
+  CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
+  CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
+  CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
+  CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 ); 
+  CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
+  CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
+  CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
+  CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 ); 
+  CONSTANT CX_cca2_1 : t_cca2_1 ;
+  CONSTANT C0_cca2_1 : t_cca2_1 ;
+  CONSTANT C1_cca2_1 : t_cca2_1 ;
+  CONSTANT C2_cca2_1 : t_cca2_1 ;
+--
+  CONSTANT CX_cca2_2 : t_cca2_2 ;
+  CONSTANT C0_cca2_2 : t_cca2_2 ;
+  CONSTANT C1_cca2_2 : t_cca2_2 ;
+  CONSTANT C2_cca2_2 : t_cca2_2 ;
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 ;
+  CONSTANT C0_cca3_1 : t_cca3_1 ;
+  CONSTANT C1_cca3_1 : t_cca3_1 ;
+  CONSTANT C2_cca3_1 : t_cca3_1 ;
+--
+  CONSTANT CX_cca3_2 : t_cca3_2 ;
+  CONSTANT C0_cca3_2 : t_cca3_2 ;
+  CONSTANT C1_cca3_2 : t_cca3_2 ;
+  CONSTANT C2_cca3_2 : t_cca3_2 ;
+  
+  CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
+  CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
+  CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
+  CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
+  
+  CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
+  
+  CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
+  CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
+  CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
+  CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 ); 
+  CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
+  CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
+  CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
+  CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
+  
+-- --------------------------------------------------------------------------------------------
+--      Functions for mapping from integer test values to/from values of the Test types
+-- --------------------------------------------------------------------------------------------
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
+  
+  FUNCTION val_i ( i : st_scl1 )  RETURN INTEGER;
+  FUNCTION val_i ( i : TIME )     RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl3 )  RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl4 )  RETURN INTEGER;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
+  
+  FUNCTION val_s ( i : st_scl1 )  RETURN STRING;
+  FUNCTION val_s ( i : TIME )     RETURN STRING;
+  FUNCTION val_s ( i : st_scl3 )  RETURN STRING;
+  FUNCTION val_s ( i : st_scl4 )  RETURN STRING;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
+  
+END;
+
+PACKAGE BODY c03s03b00x00p03n04i00517pkg IS
+  
+  CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
+  CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
+  CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
+  CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 ); 
+  CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
+  CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
+  CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
+  CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
+  CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
+  CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
+  CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
+  
+  CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
+  CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
+  CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
+  CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 ); 
+--
+-- Functions to provide values for multi-dimensional composites
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
+    VARIABLE res : t_csa2_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
+    VARIABLE res : t_csa3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
+    VARIABLE res : t_csa4_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          FOR l IN res'RANGE(4) LOOP
+            res(i,j,k,l) := v0;
+          END LOOP;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
+    VARIABLE res : t_cca2_2;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
+    VARIABLE res : t_cca3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+--
+--          Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_scre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa4_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_7;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+-- 
+-- 
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl1; END IF;
+    IF i = 1 THEN RETURN C1_scl1; END IF;
+    IF i = 2 THEN RETURN C2_scl1; END IF;
+    RETURN CX_scl1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl2; END IF;
+    IF i = 1 THEN RETURN C1_scl2; END IF;
+    IF i = 2 THEN RETURN C2_scl2; END IF;
+    RETURN CX_scl2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl3; END IF;
+    IF i = 1 THEN RETURN C1_scl3; END IF;
+    IF i = 2 THEN RETURN C2_scl3; END IF;
+    RETURN CX_scl3;
+  END;
+
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl4; END IF;
+    IF i = 1 THEN RETURN C1_scl4; END IF;
+    IF i = 2 THEN RETURN C2_scl4; END IF;
+    RETURN CX_scl4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scre_1; END IF;
+    IF i = 1 THEN RETURN C1_scre_1; END IF;
+    IF i = 2 THEN RETURN C2_scre_1; END IF;
+    RETURN CX_scre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_1; END IF;
+    IF i = 1 THEN RETURN C1_csa1_1; END IF;
+    IF i = 2 THEN RETURN C2_csa1_1; END IF;
+    RETURN CX_csa1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_2; END IF;
+    IF i = 1 THEN RETURN C1_csa1_2; END IF;
+    IF i = 2 THEN RETURN C2_csa1_2; END IF;
+    RETURN CX_csa1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_3; END IF;
+    IF i = 1 THEN RETURN C1_csa1_3; END IF;
+    IF i = 2 THEN RETURN C2_csa1_3; END IF;
+    RETURN CX_csa1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_4; END IF;
+    IF i = 1 THEN RETURN C1_csa1_4; END IF;
+    IF i = 2 THEN RETURN C2_csa1_4; END IF;
+    RETURN CX_csa1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa2_1; END IF;
+    IF i = 1 THEN RETURN C1_csa2_1; END IF;
+    IF i = 2 THEN RETURN C2_csa2_1; END IF;
+    RETURN CX_csa2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa3_1; END IF;
+    IF i = 1 THEN RETURN C1_csa3_1; END IF;
+    IF i = 2 THEN RETURN C2_csa3_1; END IF;
+    RETURN CX_csa3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa4_1; END IF;
+    IF i = 1 THEN RETURN C1_csa4_1; END IF;
+    IF i = 2 THEN RETURN C2_csa4_1; END IF;
+    RETURN CX_csa4_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_1; END IF;
+    IF i = 1 THEN RETURN C1_cca1_1; END IF;
+    IF i = 2 THEN RETURN C2_cca1_1; END IF;
+    RETURN CX_cca1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_2; END IF;
+    IF i = 1 THEN RETURN C1_cca1_2; END IF;
+    IF i = 2 THEN RETURN C2_cca1_2; END IF;
+    RETURN CX_cca1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_3; END IF;
+    IF i = 1 THEN RETURN C1_cca1_3; END IF;
+    IF i = 2 THEN RETURN C2_cca1_3; END IF;
+    RETURN CX_cca1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_4; END IF;
+    IF i = 1 THEN RETURN C1_cca1_4; END IF;
+    IF i = 2 THEN RETURN C2_cca1_4; END IF;
+    RETURN CX_cca1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_1; END IF;
+    IF i = 1 THEN RETURN C1_cca2_1; END IF;
+    IF i = 2 THEN RETURN C2_cca2_1; END IF;
+    RETURN CX_cca2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_2; END IF;
+    IF i = 1 THEN RETURN C1_cca2_2; END IF;
+    IF i = 2 THEN RETURN C2_cca2_2; END IF;
+    RETURN CX_cca2_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_1; END IF;
+    IF i = 1 THEN RETURN C1_cca3_1; END IF;
+    IF i = 2 THEN RETURN C2_cca3_1; END IF;
+    RETURN CX_cca3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_2; END IF;
+    IF i = 1 THEN RETURN C1_cca3_2; END IF;
+    IF i = 2 THEN RETURN C2_cca3_2; END IF;
+    RETURN CX_cca3_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_1; END IF;
+    IF i = 1 THEN RETURN C1_cmre_1; END IF;
+    IF i = 2 THEN RETURN C2_cmre_1; END IF;
+    RETURN CX_cmre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_2; END IF;
+    IF i = 1 THEN RETURN C1_cmre_2; END IF;
+    IF i = 2 THEN RETURN C2_cmre_2; END IF;
+    RETURN CX_cmre_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_7; END IF;
+    IF i = 1 THEN RETURN C1_cca1_7; END IF;
+    IF i = 2 THEN RETURN C2_cca1_7; END IF;
+    RETURN CX_cca1_7;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_3; END IF;
+    IF i = 1 THEN RETURN C1_cmre_3; END IF;
+    IF i = 2 THEN RETURN C2_cmre_3; END IF;
+    RETURN CX_cmre_3;
+  END;
+--
+-- 
+  FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN 0; END IF;
+    IF i = C1_scl1 THEN RETURN 1; END IF;
+    IF i = C2_scl1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN 0; END IF;
+    IF i = C1_scl2 THEN RETURN 1; END IF;
+    IF i = C2_scl2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN 0; END IF;
+    IF i = C1_scl3 THEN RETURN 1; END IF;
+    IF i = C2_scl3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN 0; END IF;
+    IF i = C1_scl4 THEN RETURN 1; END IF;
+    IF i = C2_scl4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN 0; END IF;
+    IF i = C1_scre_1 THEN RETURN 1; END IF;
+    IF i = C2_scre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN 0; END IF;
+    IF i = C1_csa1_1 THEN RETURN 1; END IF;
+    IF i = C2_csa1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN 0; END IF;
+    IF i = C1_csa1_2 THEN RETURN 1; END IF;
+    IF i = C2_csa1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN 0; END IF;
+    IF i = C1_csa1_3 THEN RETURN 1; END IF;
+    IF i = C2_csa1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN 0; END IF;
+    IF i = C1_csa1_4 THEN RETURN 1; END IF;
+    IF i = C2_csa1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN 0; END IF;
+    IF i = C1_csa2_1 THEN RETURN 1; END IF;
+    IF i = C2_csa2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN 0; END IF;
+    IF i = C1_csa3_1 THEN RETURN 1; END IF;
+    IF i = C2_csa3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN 0; END IF;
+    IF i = C1_csa4_1 THEN RETURN 1; END IF;
+    IF i = C2_csa4_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN 0; END IF;
+    IF i = C1_cca1_1 THEN RETURN 1; END IF;
+    IF i = C2_cca1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN 0; END IF;
+    IF i = C1_cca1_2 THEN RETURN 1; END IF;
+    IF i = C2_cca1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN 0; END IF;
+    IF i = C1_cca1_3 THEN RETURN 1; END IF;
+    IF i = C2_cca1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN 0; END IF;
+    IF i = C1_cca1_4 THEN RETURN 1; END IF;
+    IF i = C2_cca1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN 0; END IF;
+    IF i = C1_cca2_1 THEN RETURN 1; END IF;
+    IF i = C2_cca2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN 0; END IF;
+    IF i = C1_cca2_2 THEN RETURN 1; END IF;
+    IF i = C2_cca2_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN 0; END IF;
+    IF i = C1_cca3_1 THEN RETURN 1; END IF;
+    IF i = C2_cca3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN 0; END IF;
+    IF i = C1_cca3_2 THEN RETURN 1; END IF;
+    IF i = C2_cca3_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN 0; END IF;
+    IF i = C1_cmre_1 THEN RETURN 1; END IF;
+    IF i = C2_cmre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN 0; END IF;
+    IF i = C1_cmre_2 THEN RETURN 1; END IF;
+    IF i = C2_cmre_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN 0; END IF;
+    IF i = C1_cca1_7 THEN RETURN 1; END IF;
+    IF i = C2_cca1_7 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN 0; END IF;
+    IF i = C1_cmre_3 THEN RETURN 1; END IF;
+    IF i = C2_cmre_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  
+  FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
+    IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
+    IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : TIME ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
+    IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
+    IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
+    IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
+    IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
+    IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
+    IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
+    IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
+    IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
+    IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
+    IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
+    IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
+    IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
+    IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
+    IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
+    IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
+    IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
+    IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
+    IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
+    IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
+    IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
+    IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
+    IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
+    IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
+    IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
+    IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
+    IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
+    IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
+    IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
+    IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
+    IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
+    IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
+    IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
+    IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
+    IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
+    IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
+    IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
+    IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
+    IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
+    IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
+    IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
+    IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
+    IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
+    IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
+    IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
+    IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
+    IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  
+END c03s03b00x00p03n04i00517pkg;
+
+USE   work.c03s03b00x00p03n04i00517pkg.ALL;
+ENTITY c03s03b00x00p03n04i00517ent IS
+END c03s03b00x00p03n04i00517ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00517arch OF c03s03b00x00p03n04i00517ent IS
+--
+--          Access type declarations
+--
+  TYPE at_scre_1 IS ACCESS t_scre_1 ;
+  TYPE at_cca1_1 IS ACCESS t_cca1_1 ;
+  TYPE at_cca1_2 IS ACCESS t_cca1_2 ;
+  TYPE at_cca1_3 IS ACCESS t_cca1_3 ;
+  TYPE at_cca1_4 IS ACCESS t_cca1_4 ;
+  TYPE at_cmre_1 IS ACCESS t_cmre_1 ;
+  TYPE at_cmre_2 IS ACCESS t_cmre_2 ;
+  TYPE at_cca1_7 IS ACCESS t_cca1_7 ;
+  TYPE at_cmre_3 IS ACCESS t_cmre_3 ;
+--
+--
+BEGIN
+  TESTING: PROCESS
+--
+--          ACCESS VARIABLE declarations
+--
+    VARIABLE AV0_scre_1 : at_scre_1 ;
+    VARIABLE AV2_scre_1 : at_scre_1 ;
+    VARIABLE AV0_cca1_1 : at_cca1_1 ;
+    VARIABLE AV2_cca1_1 : at_cca1_1 ;
+    VARIABLE AV0_cca1_2 : at_cca1_2 ;
+    VARIABLE AV2_cca1_2 : at_cca1_2 ;
+    VARIABLE AV0_cca1_3 : at_cca1_3 ;
+    VARIABLE AV2_cca1_3 : at_cca1_3 ;
+    VARIABLE AV0_cca1_4 : at_cca1_4 ;
+    VARIABLE AV2_cca1_4 : at_cca1_4 ;
+    VARIABLE AV0_cmre_1 : at_cmre_1 ;
+    VARIABLE AV2_cmre_1 : at_cmre_1 ;
+    VARIABLE AV0_cmre_2 : at_cmre_2 ;
+    VARIABLE AV2_cmre_2 : at_cmre_2 ;
+    VARIABLE AV0_cca1_7 : at_cca1_7 ;
+    VARIABLE AV2_cca1_7 : at_cca1_7 ;
+    VARIABLE AV0_cmre_3 : at_cmre_3 ;
+    VARIABLE AV2_cmre_3 : at_cmre_3 ;
+--
+--
+  BEGIN
+--
+--          Allocation of access values
+--
+    AV0_scre_1 := NEW t_scre_1 ;
+    AV0_cca1_1 := NEW t_cca1_1 ;
+    AV0_cca1_2 := NEW t_cca1_2 ;
+    AV0_cca1_3 := NEW t_cca1_3 ;
+    AV0_cca1_4 := NEW t_cca1_4 ;
+    AV0_cmre_1 := NEW t_cmre_1 ;
+    AV0_cmre_2 := NEW t_cmre_2 ;
+    AV0_cca1_7 := NEW t_cca1_7 ;
+    AV0_cmre_3 := NEW t_cmre_3 ;
+---
+    AV2_scre_1 := NEW t_scre_1 ' ( C2_scre_1 ) ;
+    AV2_cca1_1 := NEW t_cca1_1 ' ( C2_cca1_1 ) ;
+    AV2_cca1_2 := NEW t_cca1_2 ' ( C2_cca1_2 ) ;
+    AV2_cca1_3 := NEW t_cca1_3 ' ( C2_cca1_3 ) ;
+    AV2_cca1_4 := NEW t_cca1_4 ' ( C2_cca1_4 ) ;
+    AV2_cmre_1 := NEW t_cmre_1 ' ( C2_cmre_1 ) ;
+    AV2_cmre_2 := NEW t_cmre_2 ' ( C2_cmre_2 ) ;
+    AV2_cca1_7 := NEW t_cca1_7 ' ( C2_cca1_7 ) ;
+    AV2_cmre_3 := NEW t_cmre_3 ' ( C2_cmre_3 ) ;
+--
+--
+    ASSERT AV0_scre_1.all = C0_scre_1  
+      REPORT "Improper initialization of AV0_scre_1" SEVERITY FAILURE;
+    ASSERT AV2_scre_1.all = C2_scre_1  
+      REPORT "Improper initialization of AV2_scre_1" SEVERITY FAILURE;
+    ASSERT AV0_cca1_1.all = C0_cca1_1  
+      REPORT "Improper initialization of AV0_cca1_1" SEVERITY FAILURE;
+    ASSERT AV2_cca1_1.all = C2_cca1_1  
+      REPORT "Improper initialization of AV2_cca1_1" SEVERITY FAILURE;
+    ASSERT AV0_cca1_2.all = C0_cca1_2  
+      REPORT "Improper initialization of AV0_cca1_2" SEVERITY FAILURE;
+    ASSERT AV2_cca1_2.all = C2_cca1_2  
+      REPORT "Improper initialization of AV2_cca1_2" SEVERITY FAILURE;
+    ASSERT AV0_cca1_3.all = C0_cca1_3  
+      REPORT "Improper initialization of AV0_cca1_3" SEVERITY FAILURE;
+    ASSERT AV2_cca1_3.all = C2_cca1_3  
+      REPORT "Improper initialization of AV2_cca1_3" SEVERITY FAILURE;
+    ASSERT AV0_cca1_4.all = C0_cca1_4  
+      REPORT "Improper initialization of AV0_cca1_4" SEVERITY FAILURE;
+    ASSERT AV2_cca1_4.all = C2_cca1_4  
+      REPORT "Improper initialization of AV2_cca1_4" SEVERITY FAILURE;
+    ASSERT AV0_cmre_1.all = C0_cmre_1  
+      REPORT "Improper initialization of AV0_cmre_1" SEVERITY FAILURE;
+    ASSERT AV2_cmre_1.all = C2_cmre_1  
+      REPORT "Improper initialization of AV2_cmre_1" SEVERITY FAILURE;
+    ASSERT AV0_cmre_2.all = C0_cmre_2  
+      REPORT "Improper initialization of AV0_cmre_2" SEVERITY FAILURE;
+    ASSERT AV2_cmre_2.all = C2_cmre_2  
+      REPORT "Improper initialization of AV2_cmre_2" SEVERITY FAILURE;
+    ASSERT AV0_cca1_7.all = C0_cca1_7  
+      REPORT "Improper initialization of AV0_cca1_7" SEVERITY FAILURE;
+    ASSERT AV2_cca1_7.all = C2_cca1_7  
+      REPORT "Improper initialization of AV2_cca1_7" SEVERITY FAILURE;
+    ASSERT AV0_cmre_3.all = C0_cmre_3  
+      REPORT "Improper initialization of AV0_cmre_3" SEVERITY FAILURE;
+    ASSERT AV2_cmre_3.all = C2_cmre_3  
+      REPORT "Improper initialization of AV2_cmre_3" SEVERITY FAILURE;
+--
+--
+    assert NOT( ( AV0_scre_1.all = C0_scre_1 ) 
+                and ( AV2_scre_1.all = C2_scre_1 ) 
+                and ( AV0_cca1_1.all = C0_cca1_1 ) 
+                and ( AV2_cca1_1.all = C2_cca1_1 ) 
+                and ( AV0_cca1_2.all = C0_cca1_2 ) 
+                and ( AV2_cca1_2.all = C2_cca1_2 ) 
+                and ( AV0_cca1_3.all = C0_cca1_3 ) 
+                and ( AV2_cca1_3.all = C2_cca1_3 ) 
+                and ( AV0_cca1_4.all = C0_cca1_4 ) 
+                and ( AV2_cca1_4.all = C2_cca1_4 ) 
+                and ( AV0_cmre_1.all = C0_cmre_1 ) 
+                and ( AV2_cmre_1.all = C2_cmre_1 ) 
+                and ( AV0_cmre_2.all = C0_cmre_2 ) 
+                and ( AV2_cmre_2.all = C2_cmre_2 ) 
+                and ( AV0_cca1_7.all = C0_cca1_7 ) 
+                and ( AV2_cca1_7.all = C2_cca1_7 ) 
+                and ( AV0_cmre_3.all = C0_cmre_3 ) 
+                and ( AV2_cmre_3.all = C2_cmre_3 )) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00517"
+      severity NOTE;
+    assert (    ( AV0_scre_1.all = C0_scre_1 ) 
+                and ( AV2_scre_1.all = C2_scre_1 ) 
+                and ( AV0_cca1_1.all = C0_cca1_1 ) 
+                and ( AV2_cca1_1.all = C2_cca1_1 ) 
+                and ( AV0_cca1_2.all = C0_cca1_2 ) 
+                and ( AV2_cca1_2.all = C2_cca1_2 ) 
+                and ( AV0_cca1_3.all = C0_cca1_3 ) 
+                and ( AV2_cca1_3.all = C2_cca1_3 ) 
+                and ( AV0_cca1_4.all = C0_cca1_4 ) 
+                and ( AV2_cca1_4.all = C2_cca1_4 ) 
+                and ( AV0_cmre_1.all = C0_cmre_1 ) 
+                and ( AV2_cmre_1.all = C2_cmre_1 ) 
+                and ( AV0_cmre_2.all = C0_cmre_2 ) 
+                and ( AV2_cmre_2.all = C2_cmre_2 ) 
+                and ( AV0_cca1_7.all = C0_cca1_7 ) 
+                and ( AV2_cca1_7.all = C2_cca1_7 ) 
+                and ( AV0_cmre_3.all = C0_cmre_3 ) 
+                and ( AV2_cmre_3.all = C2_cmre_3 )) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00517 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00517arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc519.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc519.vhd
new file mode 100644
index 0000000..2427b94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc519.vhd
@@ -0,0 +1,699 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc519.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c03s03b00x00p03n01i00519pkg is
+----------------------------------USING ONLY WHITE MATTER---------------------------------
+------------------------------------------------------------------------------------------
+---ACCESS TYPE FROM STANDARD PACKAGE
+
+  type boolean_ptr    is access boolean ;              --simple boolean type
+  type bit_ptr    is access bit ;                  --simple bit type
+  type char_ptr    is access character;             --simple character type
+  type severity_level_ptr    is access severity_level;--simple severity type
+  type integer_ptr    is access integer;               --simple integer type
+  type real_ptr    is access real;                  --simple real type
+  type time_ptr    is access time;                  --simple time type
+  type natural_ptr    is access natural;               --simple natural type
+  type positive_ptr    is access positive;              --simple positive type
+  type string_ptr    is access string;                --simple string type
+  type bit_vector_ptr    is access bit_vector;            --simple bit_vector type
+
+------------------------------------------------------------------------------------------
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+-------------------------------------------------------------------------------------------
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st    is  real_vector(0 to 15);
+  subtype time_vector_st    is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+  
+-------------------------------------------------------------------------------------------
+-------------------------------------------------------------------------------------------
+  
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+  
+-------------------------------------------------------------------------------------------
+  
+--CONSTRAINED ARRAY OF ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vectorofvector    is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector    is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector    is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector    is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+  
+-------------------------------------------------------------------------------------------
+  
+--UNCONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type s2boolean_vector    is array (natural range <>,natural range <>) of boolean;
+  type s2bit_vector       is array (natural range <>,natural range <>) of bit;
+  type s2char_vector       is array (natural range <>,natural range <>) of character;
+  type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
+  type s2integer_vector    is array (natural range <>,natural range <>) of integer;
+  type s2real_vector       is array (natural range <>,natural range <>) of real;
+  type s2time_vector       is array (natural range <>,natural range <>) of time;
+  type s2natural_vector    is array (natural range <>,natural range <>) of natural;
+  type s2positive_vector    is array (natural range <>,natural range <>) of positive;
+  
+-------------------------------------------------------------------------------------------
+  
+--CONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type column    is range 1 to 64;
+  type row    is range 1 to 1024;
+  type s2boolean_cons_vector    is array (row,column) of boolean;
+  type s2bit_cons_vector    is array (row,column) of bit;
+  type s2char_cons_vector    is array (row,column) of character;
+  type s2severity_level_cons_vector    is array (row,column) of severity_level;
+  type s2integer_cons_vector    is array (row,column) of integer;
+  type s2real_cons_vector    is array (row,column) of real;
+  type s2time_cons_vector    is array (row,column) of time;
+  type s2natural_cons_vector    is array (row,column) of natural;
+  type s2positive_cons_vector    is array (row,column) of positive;
+
+-------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS FROM STANDARD PACKAGE
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  
+-------------------------------------------------------------------------------------------
+
+--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+-------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+-------------------------------------------------------------------------------------------
+
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS
+  
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+  
+-------------------------------------------------------------------------------------------
+
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS OF ARRAY
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+--------------------------------------------------------------------------------------------
+
+  type record_of_ptr is record
+                          a:boolean_ptr ;                                     --simple boolean type
+                          b:bit_ptr;                                        --simple bit type
+                          c:char_ptr;                                       --simple character type
+                          e:severity_level_ptr;                        --simple severity type
+                          f:integer_ptr;                                      --simple integer type
+                          g:real_ptr ;                                 --simple real type
+                          h:time_ptr;                                       --simple time type
+                          i:natural_ptr;                                  --simple natural type
+                          j:positive_ptr;                                    --simple positive type
+                          k:string_ptr;                                   --simple string type
+                          l:bit_vector_ptr;                                --simple bit_vector type
+                        end record;
+  
+--------------------------------------------------------------------------------------------
+
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              h: record_of_ptr;
+                              i: record_array_st;
+                            end record;
+  
+--------------------------------------------------------------------------------------------
+--ACCESS TYPES FOR ABOVE
+--------------------------------------------------------------------------------------------
+  
+  type boolean_vector_ptr       is access boolean_vector;
+  type severity_level_vector_ptr    is access severity_level_vector;
+  type integer_vector_ptr       is access integer_vector;
+  type real_vector_ptr       is access real_vector;
+  type time_vector_ptr       is access time_vector;
+  type natural_vector_ptr       is access natural_vector;
+  type positive_vector_ptr       is access positive_vector;
+--------------------------------------------------------------------------------------------
+  type boolean_cons_vector_ptr    is access boolean_cons_vector;
+  type severity_level_cons_vector_ptr    is access severity_level_cons_vector;
+  type integer_cons_vector_ptr    is access integer_cons_vector;
+  type real_cons_vector_ptr       is access real_cons_vector;
+  type time_cons_vector_ptr       is access time_cons_vector;
+  type natural_cons_vector_ptr    is access natural_cons_vector;
+  type positive_cons_vector_ptr    is access positive_cons_vector;
+--------------------------------------------------------------------------------------------
+  type boolean_cons_vectorofvector_ptr is access boolean_cons_vectorofvector;
+  type sev_lvl_cons_vecofvec_ptr    is access severity_level_cons_vectorofvector;
+  type integer_cons_vectorofvector_ptr is access integer_cons_vectorofvector;
+  type real_cons_vectorofvector_ptr    is access real_cons_vectorofvector;
+  type time_cons_vectorofvector_ptr    is access time_cons_vectorofvector;
+  type natural_cons_vectorofvector_ptr is access natural_cons_vectorofvector;
+  type posi_cons_vecofvec_ptr       is access positive_cons_vectorofvector;
+--------------------------------------------------------------------------------------------
+  type s2boolean_vector_ptr       is access boolean_vector;
+  type s2bit_vector_ptr       is access s2bit_vector;
+  type s2char_vector_ptr       is access s2char_vector;
+  type s2severity_level_vector_ptr    is access s2severity_level_vector;
+  type s2integer_vector_ptr       is access s2integer_vector;
+  type s2real_vector_ptr       is access s2real_vector;
+  type s2time_vector_ptr       is access s2time_vector;
+  type s2positive_vector_ptr       is access s2positive_vector;
+--------------------------------------------------------------------------------------------
+  type s2boolean_cons_vector_ptr    is access s2boolean_cons_vector;
+  type s2bit_cons_vector_ptr       is access s2bit_cons_vector;
+  type s2char_cons_vector_ptr       is access s2char_cons_vector;
+  type s2sev_lvl_cons_vec_ptr       is access s2severity_level_cons_vector;
+  type s2integer_cons_vector_ptr    is access s2integer_cons_vector;
+  type s2real_cons_vector_ptr       is access s2real_cons_vector;
+  type s2time_cons_vector_ptr       is access s2time_cons_vector;
+  type s2natural_cons_vector_ptr    is access natural_cons_vector;
+  type s2positive_cons_vector_ptr    is access s2positive_cons_vector;
+--------------------------------------------------------------------------------------------
+  type record_std_package_ptr    is access record_std_package;
+  type record_cons_array_ptr       is access record_cons_array;
+  type record_2cons_array_ptr    is access record_2cons_array;
+  type record_cons_arrayofarray_ptr    is access record_cons_arrayofarray;
+  type record_of_ptr_ptr       is access record_of_ptr;
+  type record_of_records_ptr       is access record_of_records;
+  
+--------------------------------------------------------------------------------------------
+  
+--------------------USING PARTIAL GRAY & PARTIAL WHITE MATTER-------------------------------
+  
+  
+  type four_value is ('Z','0','1','X');                                    --enumerated type
+  type four_value_map is array(four_value) of boolean;
+  subtype binary is four_value range '0' to '1';
+  type four_value_vector is array (natural range <>) of four_value;              --unconstraint array of
+  type byte is array(0 to 7) of bit;
+  subtype word is bit_vector(0 to  15);                                    --constrained array
+  function resolution(i:in four_value_vector) return four_value;           --bus resolution
+  subtype four_value_state is resolution four_value;                       --function type   
+  type state_vector is array (natural range <>) of four_value_state;             --unconstraint array of
+  constant size :integer := 63;
+  type primary_memory is array(0 to size) of word;                        --array of an array
+  type primary_memory_module is                                             --record with field
+    record                                                                  --as an array
+      enable:binary;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;           --array of a complex record
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  subtype delay is integer range 1 to 10;
+  
+  type four_value_ptr       is access four_value;
+  type four_value_map_ptr    is access four_value_map;
+  type binary_ptr       is access binary;
+  type four_value_vector_ptr    is access four_value_vector;            --ennumerated type
+  type byte_ptr       is access byte;
+  type word_ptr       is access word;
+  type four_value_state_ptr    is access four_value_state;
+  type state_vector_ptr    is access state_vector;                 --type returned by resolu.
+  type primary_memory_ptr    is access primary_memory;
+  type whole_memory_ptr    is access whole_memory;
+  type current_ptr       is access current;
+  type resistance_ptr       is access resistance;
+  type delay_ptr       is access delay;
+  
+-----------------------------------------------------------------------------------------
+end c03s03b00x00p03n01i00519pkg;
+
+package body c03s03b00x00p03n01i00519pkg is
+  function resolution(i:in four_value_vector) return four_value is
+    variable temp :four_value := 'Z';
+  begin
+    return temp;
+  end;
+end c03s03b00x00p03n01i00519pkg;
+
+use work.c03s03b00x00p03n01i00519pkg.all;
+ENTITY c03s03b00x00p03n01i00519ent IS
+END c03s03b00x00p03n01i00519ent;
+
+ARCHITECTURE c03s03b00x00p03n01i00519arch OF c03s03b00x00p03n01i00519ent IS
+BEGIN
+  TESTING: PROCESS
+    variable var1 : boolean_ptr ;
+    variable var2 : bit_ptr ;
+    variable var3 : char_ptr ;
+    variable var4 : severity_level_ptr ;
+    variable var5 : integer_ptr ;
+    variable var6 : real_ptr ;
+    variable var7 : time_ptr ;
+    variable var8 : natural_ptr ;
+    variable var9 : positive_ptr ;
+    variable var10 : string_ptr ;
+    variable var11 : bit_vector_ptr ;
+    variable var12 : boolean_vector_ptr ;
+    variable var13 : severity_level_vector_ptr ;
+    variable var14 : integer_vector_ptr ;
+    variable var15 : real_vector_ptr ;
+    variable var16 : time_vector_ptr ;
+    variable var17 : natural_vector_ptr ;
+    variable var18 : positive_vector_ptr ;
+    variable var19 : boolean_cons_vector_ptr ;
+    variable var20 : severity_level_cons_vector_ptr ;
+    variable var21 : integer_cons_vector_ptr ;
+    variable var22 : real_cons_vector_ptr ;
+    variable var23 : time_cons_vector_ptr ;
+    variable var24 : natural_cons_vector_ptr ;
+    variable var25 : positive_cons_vector_ptr ;
+    variable var26 : boolean_cons_vectorofvector_ptr ;
+    variable var27 : sev_lvl_cons_vecofvec_ptr ;
+    variable var28 : integer_cons_vectorofvector_ptr ;
+    variable var29 : real_cons_vectorofvector_ptr ;
+    variable var30 : time_cons_vectorofvector_ptr ;
+    variable var31 : natural_cons_vectorofvector_ptr ;
+    variable var32 : posi_cons_vecofvec_ptr ;
+    variable var33 : s2boolean_vector_ptr ;
+    variable var34 : s2bit_vector_ptr ;
+    variable var35 : s2char_vector_ptr ;
+    variable var36 : s2severity_level_vector_ptr ;
+    variable var37 : s2integer_vector_ptr ;
+    variable var38 : s2real_vector_ptr ;
+    variable var39 : s2time_vector_ptr ;
+    variable var40 : s2positive_vector_ptr ;
+    variable var41 : s2boolean_cons_vector_ptr ;
+    variable var42 : s2bit_cons_vector_ptr ;
+    variable var43 : s2char_cons_vector_ptr ;
+    variable var44 : s2sev_lvl_cons_vec_ptr ;
+    variable var45 : s2integer_cons_vector_ptr ;
+    variable var46 : s2real_cons_vector_ptr ;
+    variable var47 : s2time_cons_vector_ptr ;
+    variable var48 : s2natural_cons_vector_ptr ;
+    variable var49 : s2positive_cons_vector_ptr ;
+    variable var50 : record_std_package_ptr ;
+    variable var51 : record_cons_array_ptr ;
+    variable var52 : record_2cons_array_ptr ;
+    variable var53 : record_cons_arrayofarray_ptr ;
+    variable var54 : record_of_ptr_ptr ;
+    variable var55 : record_of_records_ptr ;
+    variable var56 : four_value_ptr ;
+    variable var57 : four_value_map_ptr ;
+    variable var58 : binary_ptr ;
+    variable var59 : four_value_vector_ptr ;
+    variable var60 : byte_ptr ;
+    variable var61 : word_ptr ;
+    variable var62 : four_value_state_ptr ;
+    variable var63 : state_vector_ptr ;
+    variable var64 : primary_memory_ptr ;
+    variable var65 : whole_memory_ptr ;
+    variable var66 : current_ptr ;
+    variable var67 : resistance_ptr ;
+    variable var68 : delay_ptr ;
+  BEGIN
+    assert (var1 = null)
+      report "var1 has not been set to null." severity FAILURE ;
+    assert (var2 = null)
+      report "var2 has not been set to null." severity FAILURE ;
+    assert (var3 = null)
+      report "var3 has not been set to null." severity FAILURE ;
+    assert (var4 = null)
+      report "var4 has not been set to null." severity FAILURE ;
+    assert (var5 = null)
+      report "var5 has not been set to null." severity FAILURE ;
+    assert (var6 = null)
+      report "var6 has not been set to null." severity FAILURE ;
+    assert (var7 = null)
+      report "var7 has not been set to null." severity FAILURE ;
+    assert (var8 = null)
+      report "var8 has not been set to null." severity FAILURE ;
+    assert (var9 = null)
+      report "var9 has not been set to null." severity FAILURE ;
+    assert (var10 = null)
+      report "var10 has not been set to null." severity FAILURE ;
+    assert (var11 = null)
+      report "var11 has not been set to null." severity FAILURE ;
+    assert (var12 = null)
+      report "var12 has not been set to null." severity FAILURE ;
+    assert (var13 = null)
+      report "var13 has not been set to null." severity FAILURE ;
+    assert (var14 = null)
+      report "var14 has not been set to null." severity FAILURE ;
+    assert (var15 = null)
+      report "var15 has not been set to null." severity FAILURE ;
+    assert (var16 = null)
+      report "var16 has not been set to null." severity FAILURE ;
+    assert (var17 = null)
+      report "var17 has not been set to null." severity FAILURE ;
+    assert (var18 = null)
+      report "var18 has not been set to null." severity FAILURE ;
+    assert (var19 = null)
+      report "var19 has not been set to null." severity FAILURE ;
+    assert (var20 = null)
+      report "var20 has not been set to null." severity FAILURE ;
+    assert (var21 = null)
+      report "var21 has not been set to null." severity FAILURE ;
+    assert (var22 = null)
+      report "var22 has not been set to null." severity FAILURE ;
+    assert (var23 = null)
+      report "var23 has not been set to null." severity FAILURE ;
+    assert (var24 = null)
+      report "var24 has not been set to null." severity FAILURE ;
+    assert (var25 = null)
+      report "var25 has not been set to null." severity FAILURE ;
+    assert (var26 = null)
+      report "var26 has not been set to null." severity FAILURE ;
+    assert (var27 = null)
+      report "var27 has not been set to null." severity FAILURE ;
+    assert (var28 = null)
+      report "var28 has not been set to null." severity FAILURE ;
+    assert (var29 = null)
+      report "var29 has not been set to null." severity FAILURE ;
+    assert (var30 = null)
+      report "var30 has not been set to null." severity FAILURE ;
+    assert (var31 = null)
+      report "var31 has not been set to null." severity FAILURE ;
+    assert (var32 = null)
+      report "var32 has not been set to null." severity FAILURE ;
+    assert (var33 = null)
+      report "var33 has not been set to null." severity FAILURE ;
+    assert (var34 = null)
+      report "var34 has not been set to null." severity FAILURE ;
+    assert (var35 = null)
+      report "var35 has not been set to null." severity FAILURE ;
+    assert (var36 = null)
+      report "var36 has not been set to null." severity FAILURE ;
+    assert (var37 = null)
+      report "var37 has not been set to null." severity FAILURE ;
+    assert (var38 = null)
+      report "var38 has not been set to null." severity FAILURE ;
+    assert (var39 = null)
+      report "var39 has not been set to null." severity FAILURE ;
+    assert (var40 = null)
+      report "var40 has not been set to null." severity FAILURE ;
+    assert (var41 = null)
+      report "var41 has not been set to null." severity FAILURE ;
+    assert (var42 = null)
+      report "var42 has not been set to null." severity FAILURE ;
+    assert (var43 = null)
+      report "var43 has not been set to null." severity FAILURE ;
+    assert (var44 = null)
+      report "var44 has not been set to null." severity FAILURE ;
+    assert (var45 = null)
+      report "var45 has not been set to null." severity FAILURE ;
+    assert (var46 = null)
+      report "var46 has not been set to null." severity FAILURE ;
+    assert (var47 = null)
+      report "var47 has not been set to null." severity FAILURE ;
+    assert (var48 = null)
+      report "var48 has not been set to null." severity FAILURE ;
+    assert (var49 = null)
+      report "var49 has not been set to null." severity FAILURE ;
+    assert (var50 = null)
+      report "var50 has not been set to null." severity FAILURE ;
+    assert (var51 = null)
+      report "var51 has not been set to null." severity FAILURE ;
+    assert (var52 = null)
+      report "var52 has not been set to null." severity FAILURE ;
+    assert (var53 = null)
+      report "var53 has not been set to null." severity FAILURE ;
+    assert (var54 = null)
+      report "var54 has not been set to null." severity FAILURE ;
+    assert (var55 = null)
+      report "var55 has not been set to null." severity FAILURE ;
+    assert (var56 = null)
+      report "var56 has not been set to null." severity FAILURE ;
+    assert (var57 = null)
+      report "var57 has not been set to null." severity FAILURE ;
+    assert (var58 = null)
+      report "var58 has not been set to null." severity FAILURE ;
+    assert (var59 = null)
+      report "var59 has not been set to null." severity FAILURE ;
+    assert (var60 = null)
+      report "var60 has not been set to null." severity FAILURE ;
+    assert (var61 = null)
+      report "var61 has not been set to null." severity FAILURE ;
+    assert (var62 = null)
+      report "var62 has not been set to null." severity FAILURE ;
+    assert (var63 = null)
+      report "var63 has not been set to null." severity FAILURE ;
+    assert (var64 = null)
+      report "var64 has not been set to null." severity FAILURE ;
+    assert (var65 = null)
+      report "var65 has not been set to null." severity FAILURE ;
+    assert (var66 = null)
+      report "var66 has not been set to null." severity FAILURE ;
+    assert (var67 = null)
+      report "var67 has not been set to null." severity FAILURE ;
+    assert (var68 = null)
+      report "var68 has not been set to null." severity FAILURE ;
+    assert   NOT((var1 = null)
+                 and (var2 = null)
+                 and (var3 = null)
+                 and (var4 = null)
+                 and (var5 = null)
+                 and (var6 = null)
+                 and (var7 = null)
+                 and (var8 = null)
+                 and (var9 = null)
+                 and (var10 = null)
+                 and (var11 = null)
+                 and (var12 = null)
+                 and (var13 = null)
+                 and (var14 = null)
+                 and (var15 = null)
+                 and (var16 = null)
+                 and (var17 = null)
+                 and (var18 = null)
+                 and (var19 = null)
+                 and (var20 = null)
+                 and (var21 = null)
+                 and (var22 = null)
+                 and (var23 = null)
+                 and (var24 = null)
+                 and (var25 = null)
+                 and (var26 = null)
+                 and (var27 = null)
+                 and (var28 = null)
+                 and (var29 = null)
+                 and (var30 = null)
+                 and (var31 = null)
+                 and (var32 = null)
+                 and (var33 = null)
+                 and (var34 = null)
+                 and (var35 = null)
+                 and (var36 = null)
+                 and (var37 = null)
+                 and (var38 = null)
+                 and (var39 = null)
+                 and (var40 = null)
+                 and (var41 = null)
+                 and (var42 = null)
+                 and (var43 = null)
+                 and (var44 = null)
+                 and (var45 = null)
+                 and (var46 = null)
+                 and (var47 = null)
+                 and (var48 = null)
+                 and (var49 = null)
+                 and (var50 = null)
+                 and (var51 = null)
+                 and (var52 = null)
+                 and (var53 = null)
+                 and (var54 = null)
+                 and (var55 = null)
+                 and (var56 = null)
+                 and (var57 = null)
+                 and (var58 = null)
+                 and (var59 = null)
+                 and (var60 = null)
+                 and (var61 = null)
+                 and (var62 = null)
+                 and (var63 = null)
+                 and (var64 = null)
+                 and (var65 = null)
+                 and (var66 = null)
+                 and (var67 = null)
+                 and (var68 = null))
+      report "***PASSED TEST: c03s03b00x00p03n01i00519"
+      severity NOTE;
+    assert      ((var1 = null)
+                 and (var2 = null)
+                 and (var3 = null)
+                 and (var4 = null)
+                 and (var5 = null)
+                 and (var6 = null)
+                 and (var7 = null)
+                 and (var8 = null)
+                 and (var9 = null)
+                 and (var10 = null)
+                 and (var11 = null)
+                 and (var12 = null)
+                 and (var13 = null)
+                 and (var14 = null)
+                 and (var15 = null)
+                 and (var16 = null)
+                 and (var17 = null)
+                 and (var18 = null)
+                 and (var19 = null)
+                 and (var20 = null)
+                 and (var21 = null)
+                 and (var22 = null)
+                 and (var23 = null)
+                 and (var24 = null)
+                 and (var25 = null)
+                 and (var26 = null)
+                 and (var27 = null)
+                 and (var28 = null)
+                 and (var29 = null)
+                 and (var30 = null)
+                 and (var31 = null)
+                 and (var32 = null)
+                 and (var33 = null)
+                 and (var34 = null)
+                 and (var35 = null)
+                 and (var36 = null)
+                 and (var37 = null)
+                 and (var38 = null)
+                 and (var39 = null)
+                 and (var40 = null)
+                 and (var41 = null)
+                 and (var42 = null)
+                 and (var43 = null)
+                 and (var44 = null)
+                 and (var45 = null)
+                 and (var46 = null)
+                 and (var47 = null)
+                 and (var48 = null)
+                 and (var49 = null)
+                 and (var50 = null)
+                 and (var51 = null)
+                 and (var52 = null)
+                 and (var53 = null)
+                 and (var54 = null)
+                 and (var55 = null)
+                 and (var56 = null)
+                 and (var57 = null)
+                 and (var58 = null)
+                 and (var59 = null)
+                 and (var60 = null)
+                 and (var61 = null)
+                 and (var62 = null)
+                 and (var63 = null)
+                 and (var64 = null)
+                 and (var65 = null)
+                 and (var66 = null)
+                 and (var67 = null)
+                 and (var68 = null))
+      report "***FAILED TEST: c03s03b00x00p03n01i00519 - The null value of an access type is the default initial value of the type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n01i00519arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc52.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc52.vhd
new file mode 100644
index 0000000..9fd174f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc52.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc52.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b01x01p04n01i00052pkg is
+  constant test: integer;
+end c04s03b01x01p04n01i00052pkg;
+
+package body c04s03b01x01p04n01i00052pkg is
+  constant test, test2: integer := 10; -- No_failure_here
+end c04s03b01x01p04n01i00052pkg;
+
+
+use work.c04s03b01x01p04n01i00052pkg.all;
+ENTITY c04s03b01x01p04n01i00052ent IS
+END c04s03b01x01p04n01i00052ent;
+
+ARCHITECTURE c04s03b01x01p04n01i00052arch OF c04s03b01x01p04n01i00052ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( test = 10 ) 
+      report "***PASSED TEST: c04s03b01x01p04n01i00052"
+      severity NOTE;
+    assert ( test = 10 ) 
+      report "***FAILED TEST: c04s03b01x01p04n01i00052 - A deferred constant declaration appear in a package declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p04n01i00052arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc520.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc520.vhd
new file mode 100644
index 0000000..cdfa796
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc520.vhd
@@ -0,0 +1,1366 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc520.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c03s03b00x00p03n04i00520pkg IS
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     8;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)        
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Scalar type for subelements
+--
+  SUBTYPE st_scl1 IS CHARACTER                              ;
+  SUBTYPE st_scl3 IS INTEGER   RANGE   1   TO   INTEGER'HIGH;
+  SUBTYPE st_scl4 IS REAL      RANGE 0.0   TO         1024.0;
+  
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Records of scalars
+--
+  TYPE t_scre_1 IS RECORD
+                     left   :  st_scl1;
+                     second :  TIME;
+                     third  :  st_scl3;
+                     right  :  st_scl4;
+                   END RECORD;
+--
+--          Unconstrained arrays of scalars
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
+  
+  TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
+                          st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+--
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
+  
+  SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 ,                         -- ( i2, i1 ) of CHAR
+                                st_ind1 );
+  SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 ,                         -- ( i3, i2, i1) of CHAR
+                                st_ind2 ,
+                                st_ind1 );
+  SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 ,                         -- ( i4, i3, i2, i1 ) of CHAR
+                                st_ind3 ,
+                                st_ind2 ,
+                                st_ind1 );
+--
+--
+--          constrained arrays of composites
+--
+  TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1;          -- ( i1 ) is RECORD of scalar
+  TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1;          --             ( i2 )( i1 ) is CHAR
+  TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2;          --       ( i3 )( i2 )( i1 ) is CHAR
+  TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3;          -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
+  
+  TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1;          --       ( i3 )( i2,   i1 ) is CHAR
+  TYPE t_cca2_2 IS ARRAY (st_ind4,                       -- ( i4,   i3 )( i2,   i1 ) of CHAR
+                          st_ind3) OF t_csa2_1;
+  TYPE t_cca3_1 IS ARRAY (st_ind4,                       -- ( i4,   i3,   i2 )( i1 ) of CHAR
+                          st_ind3,
+                          st_ind2) OF t_csa1_1;
+  TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1;          -- ( i4 )( i3,   i2,   i1 ) is CHAR
+--
+--          Records of composites
+--
+  TYPE t_cmre_1 IS RECORD
+                     left   :  t_csa1_1;                                   -- .fN(i1) is CHAR
+                     second :  t_scre_1;                                   -- .fN.fN
+                   END RECORD;
+
+  TYPE t_cmre_2 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_csa1_1;                               --        .fN(i1) is CHAR        
+                   END RECORD;
+--
+--          Mixed Records/arrays
+--
+  TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2;          --    (i3).fN(i1) is CHAR        
+  TYPE t_cmre_3 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_cca1_7;                               -- .fN(i3).fN(i1) is CHAR        
+                   END RECORD;
+  
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+  TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
+  TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
+  TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
+  TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
+  TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
+  TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
+  TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
+  TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
+  TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
+  TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
+  TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
+  TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
+  TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
+  TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
+  TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
+--
+--          Declaration of Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
+--
+--          Resolved SUBTYPE declaration
+--
+  SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
+  SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
+  SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
+  SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
+  SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
+  SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
+  SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
+  SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
+  SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
+  SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
+  SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
+  SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
+  SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
+  SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
+  SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
+  SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
+  SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
+  SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
+  SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
+  SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
+--
+--          Functions declarations for multi-dimensional comosite values
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
+  
+-- -------------------------------------------------------------------------------------------
+--      Data values for Composite Types
+-- -------------------------------------------------------------------------------------------
+  CONSTANT CX_scl1 : st_scl1 := 'X' ;
+  CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
+  CONSTANT C1_scl1 : st_scl1 := 'A' ;
+  CONSTANT C2_scl1 : st_scl1 := 'Z' ;
+  
+  CONSTANT CX_scl2 : TIME := 99 fs ;
+  CONSTANT C0_scl2 : TIME := TIME'LEFT ;
+  CONSTANT C1_scl2 : TIME := 0 fs;
+  CONSTANT C2_scl2 : TIME := 2 ns;
+  
+  CONSTANT CX_scl3 : st_scl3 :=  15 ;
+  CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
+  CONSTANT C1_scl3 : st_scl3 :=   6 ;
+  CONSTANT C2_scl3 : st_scl3 :=   8 ;
+  
+  CONSTANT CX_scl4 : st_scl4 := 99.9 ;
+  CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
+  CONSTANT C1_scl4 : st_scl4 :=  1.0 ;
+  CONSTANT C2_scl4 : st_scl4 :=  2.1 ;
+  
+  CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
+  CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
+  CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
+  CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
+  
+  CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
+  CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
+  CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
+  CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
+                                     OTHERS                      =>C0_scl1);
+  
+  CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
+  CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
+  CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
+  CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
+                                     OTHERS                      =>C0_scl2);
+  
+  CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
+  CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
+  CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
+  CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
+                                     OTHERS                      =>C0_scl3);
+  
+  CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
+  CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
+  CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
+  CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
+                                     OTHERS                      =>C0_scl4);
+--
+  CONSTANT CX_csa2_1 : t_csa2_1 ;
+  CONSTANT C0_csa2_1 : t_csa2_1 ;
+  CONSTANT C1_csa2_1 : t_csa2_1 ;
+  CONSTANT C2_csa2_1 : t_csa2_1 ;
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 ;
+  CONSTANT C0_csa3_1 : t_csa3_1 ;
+  CONSTANT C1_csa3_1 : t_csa3_1 ;
+  CONSTANT C2_csa3_1 : t_csa3_1 ;
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 ;
+  CONSTANT C0_csa4_1 : t_csa4_1 ;
+  CONSTANT C1_csa4_1 : t_csa4_1 ;
+  CONSTANT C2_csa4_1 : t_csa4_1 ;
+--
+  CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
+  CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
+  CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
+  CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
+                                     C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 ); 
+  CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 ); 
+  CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
+  CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
+  CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
+  CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 ); 
+  CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
+  CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
+  CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
+  CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 ); 
+  CONSTANT CX_cca2_1 : t_cca2_1 ;
+  CONSTANT C0_cca2_1 : t_cca2_1 ;
+  CONSTANT C1_cca2_1 : t_cca2_1 ;
+  CONSTANT C2_cca2_1 : t_cca2_1 ;
+--
+  CONSTANT CX_cca2_2 : t_cca2_2 ;
+  CONSTANT C0_cca2_2 : t_cca2_2 ;
+  CONSTANT C1_cca2_2 : t_cca2_2 ;
+  CONSTANT C2_cca2_2 : t_cca2_2 ;
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 ;
+  CONSTANT C0_cca3_1 : t_cca3_1 ;
+  CONSTANT C1_cca3_1 : t_cca3_1 ;
+  CONSTANT C2_cca3_1 : t_cca3_1 ;
+--
+  CONSTANT CX_cca3_2 : t_cca3_2 ;
+  CONSTANT C0_cca3_2 : t_cca3_2 ;
+  CONSTANT C1_cca3_2 : t_cca3_2 ;
+  CONSTANT C2_cca3_2 : t_cca3_2 ;
+  
+  CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
+  CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
+  CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
+  CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
+  
+  CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
+  
+  CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
+  CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
+  CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
+  CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 ); 
+  CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
+  CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
+  CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
+  CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
+  
+-- --------------------------------------------------------------------------------------------
+--      Functions for mapping from integer test values to/from values of the Test types
+-- --------------------------------------------------------------------------------------------
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
+  
+  FUNCTION val_i ( i : st_scl1 )  RETURN INTEGER;
+  FUNCTION val_i ( i : TIME )     RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl3 )  RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl4 )  RETURN INTEGER;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
+  
+  FUNCTION val_s ( i : st_scl1 )  RETURN STRING;
+  FUNCTION val_s ( i : TIME )     RETURN STRING;
+  FUNCTION val_s ( i : st_scl3 )  RETURN STRING;
+  FUNCTION val_s ( i : st_scl4 )  RETURN STRING;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
+  
+END;
+
+PACKAGE BODY c03s03b00x00p03n04i00520pkg IS
+  
+  CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
+  CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
+  CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
+  CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 ); 
+  CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
+  CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
+  CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
+  CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
+  CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
+  CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
+  CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
+  
+  CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
+  CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
+  CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
+  CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 ); 
+--
+-- Functions to provide values for multi-dimensional composites
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
+    VARIABLE res : t_csa2_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
+    VARIABLE res : t_csa3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
+    VARIABLE res : t_csa4_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          FOR l IN res'RANGE(4) LOOP
+            res(i,j,k,l) := v0;
+          END LOOP;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
+    VARIABLE res : t_cca2_2;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
+    VARIABLE res : t_cca3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+--
+--          Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_scre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa4_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_7;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+-- 
+-- 
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl1; END IF;
+    IF i = 1 THEN RETURN C1_scl1; END IF;
+    IF i = 2 THEN RETURN C2_scl1; END IF;
+    RETURN CX_scl1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl2; END IF;
+    IF i = 1 THEN RETURN C1_scl2; END IF;
+    IF i = 2 THEN RETURN C2_scl2; END IF;
+    RETURN CX_scl2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl3; END IF;
+    IF i = 1 THEN RETURN C1_scl3; END IF;
+    IF i = 2 THEN RETURN C2_scl3; END IF;
+    RETURN CX_scl3;
+  END;
+
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl4; END IF;
+    IF i = 1 THEN RETURN C1_scl4; END IF;
+    IF i = 2 THEN RETURN C2_scl4; END IF;
+    RETURN CX_scl4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scre_1; END IF;
+    IF i = 1 THEN RETURN C1_scre_1; END IF;
+    IF i = 2 THEN RETURN C2_scre_1; END IF;
+    RETURN CX_scre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_1; END IF;
+    IF i = 1 THEN RETURN C1_csa1_1; END IF;
+    IF i = 2 THEN RETURN C2_csa1_1; END IF;
+    RETURN CX_csa1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_2; END IF;
+    IF i = 1 THEN RETURN C1_csa1_2; END IF;
+    IF i = 2 THEN RETURN C2_csa1_2; END IF;
+    RETURN CX_csa1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_3; END IF;
+    IF i = 1 THEN RETURN C1_csa1_3; END IF;
+    IF i = 2 THEN RETURN C2_csa1_3; END IF;
+    RETURN CX_csa1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_4; END IF;
+    IF i = 1 THEN RETURN C1_csa1_4; END IF;
+    IF i = 2 THEN RETURN C2_csa1_4; END IF;
+    RETURN CX_csa1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa2_1; END IF;
+    IF i = 1 THEN RETURN C1_csa2_1; END IF;
+    IF i = 2 THEN RETURN C2_csa2_1; END IF;
+    RETURN CX_csa2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa3_1; END IF;
+    IF i = 1 THEN RETURN C1_csa3_1; END IF;
+    IF i = 2 THEN RETURN C2_csa3_1; END IF;
+    RETURN CX_csa3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa4_1; END IF;
+    IF i = 1 THEN RETURN C1_csa4_1; END IF;
+    IF i = 2 THEN RETURN C2_csa4_1; END IF;
+    RETURN CX_csa4_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_1; END IF;
+    IF i = 1 THEN RETURN C1_cca1_1; END IF;
+    IF i = 2 THEN RETURN C2_cca1_1; END IF;
+    RETURN CX_cca1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_2; END IF;
+    IF i = 1 THEN RETURN C1_cca1_2; END IF;
+    IF i = 2 THEN RETURN C2_cca1_2; END IF;
+    RETURN CX_cca1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_3; END IF;
+    IF i = 1 THEN RETURN C1_cca1_3; END IF;
+    IF i = 2 THEN RETURN C2_cca1_3; END IF;
+    RETURN CX_cca1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_4; END IF;
+    IF i = 1 THEN RETURN C1_cca1_4; END IF;
+    IF i = 2 THEN RETURN C2_cca1_4; END IF;
+    RETURN CX_cca1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_1; END IF;
+    IF i = 1 THEN RETURN C1_cca2_1; END IF;
+    IF i = 2 THEN RETURN C2_cca2_1; END IF;
+    RETURN CX_cca2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_2; END IF;
+    IF i = 1 THEN RETURN C1_cca2_2; END IF;
+    IF i = 2 THEN RETURN C2_cca2_2; END IF;
+    RETURN CX_cca2_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_1; END IF;
+    IF i = 1 THEN RETURN C1_cca3_1; END IF;
+    IF i = 2 THEN RETURN C2_cca3_1; END IF;
+    RETURN CX_cca3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_2; END IF;
+    IF i = 1 THEN RETURN C1_cca3_2; END IF;
+    IF i = 2 THEN RETURN C2_cca3_2; END IF;
+    RETURN CX_cca3_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_1; END IF;
+    IF i = 1 THEN RETURN C1_cmre_1; END IF;
+    IF i = 2 THEN RETURN C2_cmre_1; END IF;
+    RETURN CX_cmre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_2; END IF;
+    IF i = 1 THEN RETURN C1_cmre_2; END IF;
+    IF i = 2 THEN RETURN C2_cmre_2; END IF;
+    RETURN CX_cmre_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_7; END IF;
+    IF i = 1 THEN RETURN C1_cca1_7; END IF;
+    IF i = 2 THEN RETURN C2_cca1_7; END IF;
+    RETURN CX_cca1_7;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_3; END IF;
+    IF i = 1 THEN RETURN C1_cmre_3; END IF;
+    IF i = 2 THEN RETURN C2_cmre_3; END IF;
+    RETURN CX_cmre_3;
+  END;
+--
+-- 
+  FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN 0; END IF;
+    IF i = C1_scl1 THEN RETURN 1; END IF;
+    IF i = C2_scl1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN 0; END IF;
+    IF i = C1_scl2 THEN RETURN 1; END IF;
+    IF i = C2_scl2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN 0; END IF;
+    IF i = C1_scl3 THEN RETURN 1; END IF;
+    IF i = C2_scl3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN 0; END IF;
+    IF i = C1_scl4 THEN RETURN 1; END IF;
+    IF i = C2_scl4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN 0; END IF;
+    IF i = C1_scre_1 THEN RETURN 1; END IF;
+    IF i = C2_scre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN 0; END IF;
+    IF i = C1_csa1_1 THEN RETURN 1; END IF;
+    IF i = C2_csa1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN 0; END IF;
+    IF i = C1_csa1_2 THEN RETURN 1; END IF;
+    IF i = C2_csa1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN 0; END IF;
+    IF i = C1_csa1_3 THEN RETURN 1; END IF;
+    IF i = C2_csa1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN 0; END IF;
+    IF i = C1_csa1_4 THEN RETURN 1; END IF;
+    IF i = C2_csa1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN 0; END IF;
+    IF i = C1_csa2_1 THEN RETURN 1; END IF;
+    IF i = C2_csa2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN 0; END IF;
+    IF i = C1_csa3_1 THEN RETURN 1; END IF;
+    IF i = C2_csa3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN 0; END IF;
+    IF i = C1_csa4_1 THEN RETURN 1; END IF;
+    IF i = C2_csa4_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN 0; END IF;
+    IF i = C1_cca1_1 THEN RETURN 1; END IF;
+    IF i = C2_cca1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN 0; END IF;
+    IF i = C1_cca1_2 THEN RETURN 1; END IF;
+    IF i = C2_cca1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN 0; END IF;
+    IF i = C1_cca1_3 THEN RETURN 1; END IF;
+    IF i = C2_cca1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN 0; END IF;
+    IF i = C1_cca1_4 THEN RETURN 1; END IF;
+    IF i = C2_cca1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN 0; END IF;
+    IF i = C1_cca2_1 THEN RETURN 1; END IF;
+    IF i = C2_cca2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN 0; END IF;
+    IF i = C1_cca2_2 THEN RETURN 1; END IF;
+    IF i = C2_cca2_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN 0; END IF;
+    IF i = C1_cca3_1 THEN RETURN 1; END IF;
+    IF i = C2_cca3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN 0; END IF;
+    IF i = C1_cca3_2 THEN RETURN 1; END IF;
+    IF i = C2_cca3_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN 0; END IF;
+    IF i = C1_cmre_1 THEN RETURN 1; END IF;
+    IF i = C2_cmre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN 0; END IF;
+    IF i = C1_cmre_2 THEN RETURN 1; END IF;
+    IF i = C2_cmre_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN 0; END IF;
+    IF i = C1_cca1_7 THEN RETURN 1; END IF;
+    IF i = C2_cca1_7 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN 0; END IF;
+    IF i = C1_cmre_3 THEN RETURN 1; END IF;
+    IF i = C2_cmre_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  
+  FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
+    IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
+    IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : TIME ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
+    IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
+    IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
+    IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
+    IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
+    IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
+    IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
+    IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
+    IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
+    IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
+    IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
+    IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
+    IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
+    IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
+    IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
+    IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
+    IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
+    IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
+    IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
+    IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
+    IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
+    IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
+    IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
+    IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
+    IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
+    IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
+    IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
+    IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
+    IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
+    IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
+    IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
+    IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
+    IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
+    IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
+    IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
+    IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
+    IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
+    IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
+    IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
+    IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
+    IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
+    IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
+    IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
+    IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
+    IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
+    IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
+    IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  
+END c03s03b00x00p03n04i00520pkg;
+
+USE   work.c03s03b00x00p03n04i00520pkg.ALL;ENTITY c03s03b00x00p03n04i00520ent IS
+                                                                                      END c03s03b00x00p03n04i00520ent;
+
+                                                                                      ARCHITECTURE c03s03b00x00p03n04i00520arch OF c03s03b00x00p03n04i00520ent IS
+--
+--          Access type declarations
+--
+                                                                                        TYPE at_usa1_1 IS ACCESS t_usa1_1 ;
+                                                                                        TYPE at_usa1_2 IS ACCESS t_usa1_2 ;
+                                                                                        TYPE at_usa1_3 IS ACCESS t_usa1_3 ;
+                                                                                        TYPE at_usa1_4 IS ACCESS t_usa1_4 ;
+                                                                                        TYPE at_csa1_1 IS ACCESS t_csa1_1 ;
+                                                                                        TYPE at_csa1_2 IS ACCESS t_csa1_2 ;
+                                                                                        TYPE at_csa1_3 IS ACCESS t_csa1_3 ;
+                                                                                        TYPE at_csa1_4 IS ACCESS t_csa1_4 ;
+--
+--
+                                                                                      BEGIN
+                                                                                        TESTING: PROCESS
+--
+--          ACCESS VARIABLE declarations
+--
+                                                                                          VARIABLE AV0_usa1_1 : at_usa1_1 ;
+                                                                                          VARIABLE AV2_usa1_1 : at_usa1_1 ;
+                                                                                          VARIABLE AV0_usa1_2 : at_usa1_2 ;
+                                                                                          VARIABLE AV2_usa1_2 : at_usa1_2 ;
+                                                                                          VARIABLE AV0_usa1_3 : at_usa1_3 ;
+                                                                                          VARIABLE AV2_usa1_3 : at_usa1_3 ;
+                                                                                          VARIABLE AV0_usa1_4 : at_usa1_4 ;
+                                                                                          VARIABLE AV2_usa1_4 : at_usa1_4 ;
+                                                                                          VARIABLE AV0_csa1_1 : at_csa1_1 ;
+                                                                                          VARIABLE AV2_csa1_1 : at_csa1_1 ;
+                                                                                          VARIABLE AV0_csa1_2 : at_csa1_2 ;
+                                                                                          VARIABLE AV2_csa1_2 : at_csa1_2 ;
+                                                                                          VARIABLE AV0_csa1_3 : at_csa1_3 ;
+                                                                                          VARIABLE AV2_csa1_3 : at_csa1_3 ;
+                                                                                          VARIABLE AV0_csa1_4 : at_csa1_4 ;
+                                                                                          VARIABLE AV2_csa1_4 : at_csa1_4 ;
+--
+--
+                                                                                        BEGIN
+--
+--          Allocation of access values
+--
+                                                                                          AV0_usa1_1 := NEW t_usa1_1 (st_ind1 ) ;
+                                                                                          AV0_usa1_2 := NEW t_usa1_2 (st_ind2 ) ;
+                                                                                          AV0_usa1_3 := NEW t_usa1_3 (st_ind3 ) ;
+                                                                                          AV0_usa1_4 := NEW t_usa1_4 (st_ind4 ) ;
+                                                                                          AV0_csa1_1 := NEW t_csa1_1 ;
+                                                                                          AV0_csa1_2 := NEW t_csa1_2 ;
+                                                                                          AV0_csa1_3 := NEW t_csa1_3 ;
+                                                                                          AV0_csa1_4 := NEW t_csa1_4 ;
+---
+                                                                                          AV2_usa1_1 := NEW t_usa1_1 ' ( C2_csa1_1 ) ;
+                                                                                          AV2_usa1_2 := NEW t_usa1_2 ' ( C2_csa1_2 ) ;
+                                                                                          AV2_usa1_3 := NEW t_usa1_3 ' ( C2_csa1_3 ) ;
+                                                                                          AV2_usa1_4 := NEW t_usa1_4 ' ( C2_csa1_4 ) ;
+                                                                                          AV2_csa1_1 := NEW t_csa1_1 ' ( C2_csa1_1 ) ;
+                                                                                          AV2_csa1_2 := NEW t_csa1_2 ' ( C2_csa1_2 ) ;
+                                                                                          AV2_csa1_3 := NEW t_csa1_3 ' ( C2_csa1_3 ) ;
+                                                                                          AV2_csa1_4 := NEW t_csa1_4 ' ( C2_csa1_4 ) ;
+--
+--
+                                                                                          ASSERT AV0_usa1_1.all = C0_csa1_1  
+                                                                                            REPORT "Improper initialization of AV0_usa1_1" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_usa1_1.all = C2_csa1_1  
+                                                                                            REPORT "Improper initialization of AV2_usa1_1" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_usa1_2.all = C0_csa1_2  
+                                                                                            REPORT "Improper initialization of AV0_usa1_2" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_usa1_2.all = C2_csa1_2  
+                                                                                            REPORT "Improper initialization of AV2_usa1_2" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_usa1_3.all = C0_csa1_3  
+                                                                                            REPORT "Improper initialization of AV0_usa1_3" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_usa1_3.all = C2_csa1_3  
+                                                                                            REPORT "Improper initialization of AV2_usa1_3" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_usa1_4.all = C0_csa1_4  
+                                                                                            REPORT "Improper initialization of AV0_usa1_4" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_usa1_4.all = C2_csa1_4  
+                                                                                            REPORT "Improper initialization of AV2_usa1_4" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_csa1_1.all = C0_csa1_1  
+                                                                                            REPORT "Improper initialization of AV0_csa1_1" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_csa1_1.all = C2_csa1_1  
+                                                                                            REPORT "Improper initialization of AV2_csa1_1" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_csa1_2.all = C0_csa1_2  
+                                                                                            REPORT "Improper initialization of AV0_csa1_2" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_csa1_2.all = C2_csa1_2  
+                                                                                            REPORT "Improper initialization of AV2_csa1_2" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_csa1_3.all = C0_csa1_3  
+                                                                                            REPORT "Improper initialization of AV0_csa1_3" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_csa1_3.all = C2_csa1_3  
+                                                                                            REPORT "Improper initialization of AV2_csa1_3" SEVERITY FAILURE;
+                                                                                          ASSERT AV0_csa1_4.all = C0_csa1_4  
+                                                                                            REPORT "Improper initialization of AV0_csa1_4" SEVERITY FAILURE;
+                                                                                          ASSERT AV2_csa1_4.all = C2_csa1_4  
+                                                                                            REPORT "Improper initialization of AV2_csa1_4" SEVERITY FAILURE;
+--
+--
+                                                                                          assert NOT( ( AV0_usa1_1.all = C0_csa1_1 ) 
+                                                                                                      and ( AV2_usa1_1.all = C2_csa1_1 ) 
+                                                                                                      and ( AV0_usa1_2.all = C0_csa1_2 ) 
+                                                                                                      and ( AV2_usa1_2.all = C2_csa1_2 ) 
+                                                                                                      and ( AV0_usa1_3.all = C0_csa1_3 ) 
+                                                                                                      and ( AV2_usa1_3.all = C2_csa1_3 ) 
+                                                                                                      and ( AV0_usa1_4.all = C0_csa1_4 ) 
+                                                                                                      and ( AV2_usa1_4.all = C2_csa1_4 ) 
+                                                                                                      and ( AV0_csa1_1.all = C0_csa1_1 ) 
+                                                                                                      and ( AV2_csa1_1.all = C2_csa1_1 ) 
+                                                                                                      and ( AV0_csa1_2.all = C0_csa1_2 ) 
+                                                                                                      and ( AV2_csa1_2.all = C2_csa1_2 ) 
+                                                                                                      and ( AV0_csa1_3.all = C0_csa1_3 ) 
+                                                                                                      and ( AV2_csa1_3.all = C2_csa1_3 ) 
+                                                                                                      and ( AV0_csa1_4.all = C0_csa1_4 ) 
+                                                                                                      and ( AV2_csa1_4.all = C2_csa1_4 )) 
+                                                                                            report "***PASSED TEST: c03s03b00x00p03n04i00520"
+                                                                                            severity NOTE;
+                                                                                          assert    (   ( AV0_usa1_1.all = C0_csa1_1 ) 
+                                                                                                        and ( AV2_usa1_1.all = C2_csa1_1 ) 
+                                                                                                        and ( AV0_usa1_2.all = C0_csa1_2 ) 
+                                                                                                        and ( AV2_usa1_2.all = C2_csa1_2 ) 
+                                                                                                        and ( AV0_usa1_3.all = C0_csa1_3 ) 
+                                                                                                        and ( AV2_usa1_3.all = C2_csa1_3 ) 
+                                                                                                        and ( AV0_usa1_4.all = C0_csa1_4 ) 
+                                                                                                        and ( AV2_usa1_4.all = C2_csa1_4 ) 
+                                                                                                        and ( AV0_csa1_1.all = C0_csa1_1 ) 
+                                                                                                        and ( AV2_csa1_1.all = C2_csa1_1 ) 
+                                                                                                        and ( AV0_csa1_2.all = C0_csa1_2 ) 
+                                                                                                        and ( AV2_csa1_2.all = C2_csa1_2 ) 
+                                                                                                        and ( AV0_csa1_3.all = C0_csa1_3 ) 
+                                                                                                        and ( AV2_csa1_3.all = C2_csa1_3 ) 
+                                                                                                        and ( AV0_csa1_4.all = C0_csa1_4 ) 
+                                                                                                        and ( AV2_csa1_4.all = C2_csa1_4 )) 
+                                                                                            report "***FAILED TEST: c03s03b00x00p03n04i00520 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
+                                                                                            severity ERROR;
+                                                                                          wait;
+                                                                                        END PROCESS TESTING;
+
+                                                                                      END c03s03b00x00p03n04i00520arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc521.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc521.vhd
new file mode 100644
index 0000000..323baad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc521.vhd
@@ -0,0 +1,1373 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc521.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c03s03b00x00p03n04i00521pkg IS
+--
+--          Index types for array declarations
+--
+  SUBTYPE st_ind1 IS INTEGER   RANGE   1   TO     8;     -- index from 1 (POSITIVE)
+  SUBTYPE st_ind2 IS INTEGER   RANGE   0   TO     3;     -- index from 0 (NATURAL)        
+  SUBTYPE st_ind3 IS CHARACTER RANGE 'a'   TO   'd';     -- non-INTEGER index
+  SUBTYPE st_ind4 IS INTEGER   RANGE   0 DOWNTO  -3;     -- descending range
+--
+--          Scalar type for subelements
+--
+  SUBTYPE st_scl1 IS CHARACTER                              ;
+  SUBTYPE st_scl3 IS INTEGER   RANGE   1   TO   INTEGER'HIGH;
+  SUBTYPE st_scl4 IS REAL      RANGE 0.0   TO         1024.0;
+  
+-- -----------------------------------------------------------------------------------------
+--      Composite type declarations
+-- -----------------------------------------------------------------------------------------
+--
+--          Records of scalars
+--
+  TYPE t_scre_1 IS RECORD
+                     left   :  st_scl1;
+                     second :  TIME;
+                     third  :  st_scl3;
+                     right  :  st_scl4;
+                   END RECORD;
+--
+--          Unconstrained arrays of scalars
+--
+  TYPE t_usa1_1 IS ARRAY (st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa1_2 IS ARRAY (st_ind2 RANGE <>) OF TIME;
+  TYPE t_usa1_3 IS ARRAY (st_ind3 RANGE <>) OF st_scl3;
+  TYPE t_usa1_4 IS ARRAY (st_ind4 RANGE <>) OF st_scl4;
+  
+  TYPE t_usa2_1 IS ARRAY (st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa3_1 IS ARRAY (st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+  TYPE t_usa4_1 IS ARRAY (st_ind4 RANGE <>,
+                          st_ind3 RANGE <>,
+                          st_ind2 RANGE <>,
+                          st_ind1 RANGE <>) OF st_scl1;
+--
+--
+--          Constrained arrays of scalars (make compatable with unconstrained types
+--
+  SUBTYPE t_csa1_1 IS t_usa1_1 (st_ind1 );
+  SUBTYPE t_csa1_2 IS t_usa1_2 (st_ind2 );
+  SUBTYPE t_csa1_3 IS t_usa1_3 (st_ind3 );
+  SUBTYPE t_csa1_4 IS t_usa1_4 (st_ind4 );
+  
+  SUBTYPE t_csa2_1 IS t_usa2_1 (st_ind2 ,                         -- ( i2, i1 ) of CHAR
+                                st_ind1 );
+  SUBTYPE t_csa3_1 IS t_usa3_1 (st_ind3 ,                         -- ( i3, i2, i1) of CHAR
+                                st_ind2 ,
+                                st_ind1 );
+  SUBTYPE t_csa4_1 IS t_usa4_1 (st_ind4 ,                         -- ( i4, i3, i2, i1 ) of CHAR
+                                st_ind3 ,
+                                st_ind2 ,
+                                st_ind1 );
+--
+--
+--          constrained arrays of composites
+--
+  TYPE t_cca1_1 IS ARRAY (st_ind1) OF t_scre_1;          -- ( i1 ) is RECORD of scalar
+  TYPE t_cca1_2 IS ARRAY (st_ind2) OF t_csa1_1;          --             ( i2 )( i1 ) is CHAR
+  TYPE t_cca1_3 IS ARRAY (st_ind3) OF t_cca1_2;          --       ( i3 )( i2 )( i1 ) is CHAR
+  TYPE t_cca1_4 IS ARRAY (st_ind4) OF t_cca1_3;          -- ( i4 )( i3 )( i2 )( i1 ) is CHAR
+  
+  TYPE t_cca2_1 IS ARRAY (st_ind3) OF t_csa2_1;          --       ( i3 )( i2,   i1 ) is CHAR
+  TYPE t_cca2_2 IS ARRAY (st_ind4,                       -- ( i4,   i3 )( i2,   i1 ) of CHAR
+                          st_ind3) OF t_csa2_1;
+  TYPE t_cca3_1 IS ARRAY (st_ind4,                       -- ( i4,   i3,   i2 )( i1 ) of CHAR
+                          st_ind3,
+                          st_ind2) OF t_csa1_1;
+  TYPE t_cca3_2 IS ARRAY (st_ind4) OF t_csa3_1;          -- ( i4 )( i3,   i2,   i1 ) is CHAR
+--
+--          Records of composites
+--
+  TYPE t_cmre_1 IS RECORD
+                     left   :  t_csa1_1;                                   -- .fN(i1) is CHAR
+                     second :  t_scre_1;                                   -- .fN.fN
+                   END RECORD;
+
+  TYPE t_cmre_2 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_csa1_1;                               --        .fN(i1) is CHAR        
+                   END RECORD;
+--
+--          Mixed Records/arrays
+--
+  TYPE t_cca1_7 IS ARRAY (st_ind3) OF t_cmre_2;          --    (i3).fN(i1) is CHAR        
+  TYPE t_cmre_3 IS RECORD
+                     left   ,
+                       second ,
+                       third  ,
+                       right  :  t_cca1_7;                               -- .fN(i3).fN(i1) is CHAR        
+                   END RECORD;
+  
+--
+--          TYPE declarations for resolution function (Constrained types only)
+--
+  TYPE t_scre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_scre_1;
+  TYPE t_csa1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_1;
+  TYPE t_csa1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_2;
+  TYPE t_csa1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_3;
+  TYPE t_csa1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa1_4;
+  TYPE t_csa2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa2_1;
+  TYPE t_csa3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa3_1;
+  TYPE t_csa4_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_csa4_1;
+  TYPE t_cca1_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_1;
+  TYPE t_cca1_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_2;
+  TYPE t_cca1_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_3;
+  TYPE t_cca1_4_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_4;
+  TYPE t_cca2_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_1;
+  TYPE t_cca2_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca2_2;
+  TYPE t_cca3_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_1;
+  TYPE t_cca3_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca3_2;
+  TYPE t_cmre_1_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_1;
+  TYPE t_cmre_2_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_2;
+  TYPE t_cca1_7_vct IS ARRAY (POSITIVE RANGE <>) OF t_cca1_7;
+  TYPE t_cmre_3_vct IS ARRAY (POSITIVE RANGE <>) OF t_cmre_3;
+--
+--          Declaration of Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1;
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2;
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3;
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4;
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1;
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1;
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1;
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1;
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2;
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3;
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4;
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1;
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2;
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1;
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2;
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1;
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2;
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7;
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3;
+--
+--          Resolved SUBTYPE declaration
+--
+  SUBTYPE rst_scre_1 IS rf_scre_1 t_scre_1 ;
+  SUBTYPE rst_csa1_1 IS rf_csa1_1 t_csa1_1 ;
+  SUBTYPE rst_csa1_2 IS rf_csa1_2 t_csa1_2 ;
+  SUBTYPE rst_csa1_3 IS rf_csa1_3 t_csa1_3 ;
+  SUBTYPE rst_csa1_4 IS rf_csa1_4 t_csa1_4 ;
+  SUBTYPE rst_csa2_1 IS rf_csa2_1 t_csa2_1 ;
+  SUBTYPE rst_csa3_1 IS rf_csa3_1 t_csa3_1 ;
+  SUBTYPE rst_csa4_1 IS rf_csa4_1 t_csa4_1 ;
+  SUBTYPE rst_cca1_1 IS rf_cca1_1 t_cca1_1 ;
+  SUBTYPE rst_cca1_2 IS rf_cca1_2 t_cca1_2 ;
+  SUBTYPE rst_cca1_3 IS rf_cca1_3 t_cca1_3 ;
+  SUBTYPE rst_cca1_4 IS rf_cca1_4 t_cca1_4 ;
+  SUBTYPE rst_cca2_1 IS rf_cca2_1 t_cca2_1 ;
+  SUBTYPE rst_cca2_2 IS rf_cca2_2 t_cca2_2 ;
+  SUBTYPE rst_cca3_1 IS rf_cca3_1 t_cca3_1 ;
+  SUBTYPE rst_cca3_2 IS rf_cca3_2 t_cca3_2 ;
+  SUBTYPE rst_cmre_1 IS rf_cmre_1 t_cmre_1 ;
+  SUBTYPE rst_cmre_2 IS rf_cmre_2 t_cmre_2 ;
+  SUBTYPE rst_cca1_7 IS rf_cca1_7 t_cca1_7 ;
+  SUBTYPE rst_cmre_3 IS rf_cmre_3 t_cmre_3 ;
+--
+--          Functions declarations for multi-dimensional comosite values
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 ;
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 ;
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 ;
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 ;
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 ;
+  
+-- -------------------------------------------------------------------------------------------
+--      Data values for Composite Types
+-- -------------------------------------------------------------------------------------------
+  CONSTANT CX_scl1 : st_scl1 := 'X' ;
+  CONSTANT C0_scl1 : st_scl1 := st_scl1'LEFT ;
+  CONSTANT C1_scl1 : st_scl1 := 'A' ;
+  CONSTANT C2_scl1 : st_scl1 := 'Z' ;
+  
+  CONSTANT CX_scl2 : TIME := 99 fs ;
+  CONSTANT C0_scl2 : TIME := TIME'LEFT ;
+  CONSTANT C1_scl2 : TIME := 0 fs;
+  CONSTANT C2_scl2 : TIME := 2 ns;
+  
+  CONSTANT CX_scl3 : st_scl3 :=  15 ;
+  CONSTANT C0_scl3 : st_scl3 := st_scl3'LEFT ;
+  CONSTANT C1_scl3 : st_scl3 :=   6 ;
+  CONSTANT C2_scl3 : st_scl3 :=   8 ;
+  
+  CONSTANT CX_scl4 : st_scl4 := 99.9 ;
+  CONSTANT C0_scl4 : st_scl4 := st_scl4'LEFT ;
+  CONSTANT C1_scl4 : st_scl4 :=  1.0 ;
+  CONSTANT C2_scl4 : st_scl4 :=  2.1 ;
+  
+  CONSTANT CX_scre_1 : t_scre_1 := ( CX_scl1, CX_scl2, CX_scl3, CX_scl4 );
+  CONSTANT C0_scre_1 : t_scre_1 := ( C0_scl1, C0_scl2, C0_scl3, C0_scl4 );
+  CONSTANT C1_scre_1 : t_scre_1 := ( C1_scl1, C1_scl2, C1_scl3, C1_scl4 );
+  CONSTANT C2_scre_1 : t_scre_1 := ( C2_scl1, C0_scl2, C0_scl3, C2_scl4 );
+  
+  CONSTANT CX_csa1_1 : t_csa1_1 := ( OTHERS=>CX_scl1);
+  CONSTANT C0_csa1_1 : t_csa1_1 := ( OTHERS=>C0_scl1);
+  CONSTANT C1_csa1_1 : t_csa1_1 := ( OTHERS=>C1_scl1);
+  CONSTANT C2_csa1_1 : t_csa1_1 := ( t_csa1_1'LEFT|t_csa1_1'RIGHT=>C2_scl1,
+                                     OTHERS                      =>C0_scl1);
+  
+  CONSTANT CX_csa1_2 : t_csa1_2 := ( OTHERS=>CX_scl2);
+  CONSTANT C0_csa1_2 : t_csa1_2 := ( OTHERS=>C0_scl2);
+  CONSTANT C1_csa1_2 : t_csa1_2 := ( OTHERS=>C1_scl2);
+  CONSTANT C2_csa1_2 : t_csa1_2 := ( t_csa1_2'LEFT|t_csa1_2'RIGHT=>C2_scl2,
+                                     OTHERS                      =>C0_scl2);
+  
+  CONSTANT CX_csa1_3 : t_csa1_3 := ( OTHERS=>CX_scl3);
+  CONSTANT C0_csa1_3 : t_csa1_3 := ( OTHERS=>C0_scl3);
+  CONSTANT C1_csa1_3 : t_csa1_3 := ( OTHERS=>C1_scl3);
+  CONSTANT C2_csa1_3 : t_csa1_3 := ( t_csa1_3'LEFT|t_csa1_3'RIGHT=>C2_scl3,
+                                     OTHERS                      =>C0_scl3);
+  
+  CONSTANT CX_csa1_4 : t_csa1_4 := ( OTHERS=>CX_scl4);
+  CONSTANT C0_csa1_4 : t_csa1_4 := ( OTHERS=>C0_scl4);
+  CONSTANT C1_csa1_4 : t_csa1_4 := ( OTHERS=>C1_scl4);
+  CONSTANT C2_csa1_4 : t_csa1_4 := ( t_csa1_4'LEFT|t_csa1_4'RIGHT=>C2_scl4,
+                                     OTHERS                      =>C0_scl4);
+--
+  CONSTANT CX_csa2_1 : t_csa2_1 ;
+  CONSTANT C0_csa2_1 : t_csa2_1 ;
+  CONSTANT C1_csa2_1 : t_csa2_1 ;
+  CONSTANT C2_csa2_1 : t_csa2_1 ;
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 ;
+  CONSTANT C0_csa3_1 : t_csa3_1 ;
+  CONSTANT C1_csa3_1 : t_csa3_1 ;
+  CONSTANT C2_csa3_1 : t_csa3_1 ;
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 ;
+  CONSTANT C0_csa4_1 : t_csa4_1 ;
+  CONSTANT C1_csa4_1 : t_csa4_1 ;
+  CONSTANT C2_csa4_1 : t_csa4_1 ;
+--
+  CONSTANT CX_cca1_1 : t_cca1_1 := ( OTHERS=>CX_scre_1 );
+  CONSTANT C0_cca1_1 : t_cca1_1 := ( OTHERS=>C0_scre_1 );
+  CONSTANT C1_cca1_1 : t_cca1_1 := ( OTHERS=>C1_scre_1 );
+  CONSTANT C2_cca1_1 : t_cca1_1 := ( C2_scre_1, C0_scre_1, C0_scre_1, C0_scre_1,
+                                     C0_scre_1, C0_scre_1, C0_scre_1, C2_scre_1 ); 
+  CONSTANT CX_cca1_2 : t_cca1_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cca1_2 : t_cca1_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cca1_2 : t_cca1_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cca1_2 : t_cca1_2 := ( C2_csa1_1, C0_csa1_1, C0_csa1_1, C2_csa1_1 ); 
+  CONSTANT CX_cca1_3 : t_cca1_3 := ( OTHERS=>CX_cca1_2 );
+  CONSTANT C0_cca1_3 : t_cca1_3 := ( OTHERS=>C0_cca1_2 );
+  CONSTANT C1_cca1_3 : t_cca1_3 := ( OTHERS=>C1_cca1_2 );
+  CONSTANT C2_cca1_3 : t_cca1_3 := ( C2_cca1_2, C0_cca1_2, C0_cca1_2, C2_cca1_2 ); 
+  CONSTANT CX_cca1_4 : t_cca1_4 := ( OTHERS=>CX_cca1_3 );
+  CONSTANT C0_cca1_4 : t_cca1_4 := ( OTHERS=>C0_cca1_3 );
+  CONSTANT C1_cca1_4 : t_cca1_4 := ( OTHERS=>C1_cca1_3 );
+  CONSTANT C2_cca1_4 : t_cca1_4 := ( C2_cca1_3, C0_cca1_3, C0_cca1_3, C2_cca1_3 ); 
+  CONSTANT CX_cca2_1 : t_cca2_1 ;
+  CONSTANT C0_cca2_1 : t_cca2_1 ;
+  CONSTANT C1_cca2_1 : t_cca2_1 ;
+  CONSTANT C2_cca2_1 : t_cca2_1 ;
+--
+  CONSTANT CX_cca2_2 : t_cca2_2 ;
+  CONSTANT C0_cca2_2 : t_cca2_2 ;
+  CONSTANT C1_cca2_2 : t_cca2_2 ;
+  CONSTANT C2_cca2_2 : t_cca2_2 ;
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 ;
+  CONSTANT C0_cca3_1 : t_cca3_1 ;
+  CONSTANT C1_cca3_1 : t_cca3_1 ;
+  CONSTANT C2_cca3_1 : t_cca3_1 ;
+--
+  CONSTANT CX_cca3_2 : t_cca3_2 ;
+  CONSTANT C0_cca3_2 : t_cca3_2 ;
+  CONSTANT C1_cca3_2 : t_cca3_2 ;
+  CONSTANT C2_cca3_2 : t_cca3_2 ;
+  
+  CONSTANT CX_cmre_1 : t_cmre_1 := ( CX_csa1_1, CX_scre_1 );
+  CONSTANT C0_cmre_1 : t_cmre_1 := ( C0_csa1_1, C0_scre_1 );
+  CONSTANT C1_cmre_1 : t_cmre_1 := ( C1_csa1_1, C1_scre_1 );
+  CONSTANT C2_cmre_1 : t_cmre_1 := ( C2_csa1_1, C0_scre_1 );
+  
+  CONSTANT CX_cmre_2 : t_cmre_2 := ( OTHERS=>CX_csa1_1 );
+  CONSTANT C0_cmre_2 : t_cmre_2 := ( OTHERS=>C0_csa1_1 );
+  CONSTANT C1_cmre_2 : t_cmre_2 := ( OTHERS=>C1_csa1_1 );
+  CONSTANT C2_cmre_2 : t_cmre_2 := ( left|right=>C2_csa1_1, OTHERS=>C0_csa1_1 );
+  
+  CONSTANT CX_cca1_7 : t_cca1_7 := ( OTHERS=>CX_cmre_2 );
+  CONSTANT C0_cca1_7 : t_cca1_7 := ( OTHERS=>C0_cmre_2 );
+  CONSTANT C1_cca1_7 : t_cca1_7 := ( OTHERS=>C1_cmre_2 );
+  CONSTANT C2_cca1_7 : t_cca1_7 := ( C2_cmre_2, C0_cmre_2, C0_cmre_2, C2_cmre_2 ); 
+  CONSTANT CX_cmre_3 : t_cmre_3 := ( OTHERS=>CX_cca1_7 );
+  CONSTANT C0_cmre_3 : t_cmre_3 := ( OTHERS=>C0_cca1_7 );
+  CONSTANT C1_cmre_3 : t_cmre_3 := ( OTHERS=>C1_cca1_7 );
+  CONSTANT C2_cmre_3 : t_cmre_3 := ( left|right=>C2_cca1_7, OTHERS=>C0_cca1_7 );
+  
+-- --------------------------------------------------------------------------------------------
+--      Functions for mapping from integer test values to/from values of the Test types
+-- --------------------------------------------------------------------------------------------
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3;
+  
+  FUNCTION val_i ( i : st_scl1 )  RETURN INTEGER;
+  FUNCTION val_i ( i : TIME )     RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl3 )  RETURN INTEGER;
+  FUNCTION val_i ( i : st_scl4 )  RETURN INTEGER;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER;
+  
+  FUNCTION val_s ( i : st_scl1 )  RETURN STRING;
+  FUNCTION val_s ( i : TIME )     RETURN STRING;
+  FUNCTION val_s ( i : st_scl3 )  RETURN STRING;
+  FUNCTION val_s ( i : st_scl4 )  RETURN STRING;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING;
+  
+END;
+
+PACKAGE BODY c03s03b00x00p03n04i00521pkg IS
+  
+  CONSTANT CX_csa2_1 : t_csa2_1 := F_csa2_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa2_1 : t_csa2_1 := F_csa2_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa2_1 : t_csa2_1 := F_csa2_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa3_1 : t_csa3_1 := F_csa3_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa3_1 : t_csa3_1 := F_csa3_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa3_1 : t_csa3_1 := F_csa3_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_csa4_1 : t_csa4_1 := F_csa4_1 ( CX_scl1, CX_scl1 );
+  CONSTANT C0_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C0_scl1 );
+  CONSTANT C1_csa4_1 : t_csa4_1 := F_csa4_1 ( C1_scl1, C1_scl1 );
+  CONSTANT C2_csa4_1 : t_csa4_1 := F_csa4_1 ( C0_scl1, C2_scl1 );
+  
+  CONSTANT CX_cca2_1 : t_cca2_1 := ( OTHERS=>CX_csa2_1 );
+  CONSTANT C0_cca2_1 : t_cca2_1 := ( OTHERS=>C0_csa2_1 );
+  CONSTANT C1_cca2_1 : t_cca2_1 := ( OTHERS=>C1_csa2_1 );
+  CONSTANT C2_cca2_1 : t_cca2_1 := ( C2_csa2_1, C0_csa2_1, C0_csa2_1, C2_csa2_1 ); 
+  CONSTANT CX_cca2_2 : t_cca2_2 := F_cca2_2 ( CX_csa2_1, CX_csa2_1 );
+  CONSTANT C0_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C0_csa2_1 );
+  CONSTANT C1_cca2_2 : t_cca2_2 := F_cca2_2 ( C1_csa2_1, C1_csa2_1 );
+  CONSTANT C2_cca2_2 : t_cca2_2 := F_cca2_2 ( C0_csa2_1, C2_csa2_1 );
+  
+  CONSTANT CX_cca3_1 : t_cca3_1 := F_cca3_1 ( CX_csa1_1, CX_csa1_1 );
+  CONSTANT C0_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C0_csa1_1 );
+  CONSTANT C1_cca3_1 : t_cca3_1 := F_cca3_1 ( C1_csa1_1, C1_csa1_1 );
+  CONSTANT C2_cca3_1 : t_cca3_1 := F_cca3_1 ( C0_csa1_1, C2_csa1_1 );
+  
+  CONSTANT CX_cca3_2 : t_cca3_2 := ( OTHERS=>CX_csa3_1 );
+  CONSTANT C0_cca3_2 : t_cca3_2 := ( OTHERS=>C0_csa3_1 );
+  CONSTANT C1_cca3_2 : t_cca3_2 := ( OTHERS=>C1_csa3_1 );
+  CONSTANT C2_cca3_2 : t_cca3_2 := ( C2_csa3_1, C0_csa3_1, C0_csa3_1, C2_csa3_1 ); 
+--
+-- Functions to provide values for multi-dimensional composites
+--
+  FUNCTION F_csa2_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa2_1 IS
+    VARIABLE res : t_csa2_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa3_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa3_1 IS
+    VARIABLE res : t_csa3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_csa4_1 ( v0,v2 : IN st_scl1 ) RETURN t_csa4_1 IS
+    VARIABLE res : t_csa4_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          FOR l IN res'RANGE(4) LOOP
+            res(i,j,k,l) := v0;
+          END LOOP;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'left (4)) := v2;
+    res(res'left (1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'left (3),res'right(4)) := v2;
+    res(res'left (1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'left (2),res'right(3),res'right(4)) := v2;
+    res(res'left (1),res'right(2),res'right(3),res'right(4)) := v2;
+    res(res'right(1),res'right(2),res'right(3),res'right(4)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca2_2 ( v0,v2 : IN t_csa2_1 ) RETURN t_cca2_2 IS
+    VARIABLE res : t_cca2_2;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        res(i,j) := v0;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2)) := v2;
+    res(res'left (1),res'right(2)) := v2;
+    res(res'right(1),res'left (2)) := v2;
+    res(res'right(1),res'right(2)) := v2;
+    RETURN res;
+  END;
+  
+  FUNCTION F_cca3_1 ( v0,v2 : IN t_csa1_1 ) RETURN t_cca3_1 IS
+    VARIABLE res : t_cca3_1;
+  BEGIN
+    FOR i IN res'RANGE(1) LOOP
+      FOR j IN res'RANGE(2) LOOP
+        FOR k IN res'RANGE(3) LOOP
+          res(i,j,k) := v0;
+        END LOOP;
+      END LOOP;
+    END LOOP;
+    res(res'left (1),res'left (2),res'left (3)) := v2;
+    res(res'right(1),res'left (2),res'left (3)) := v2;
+    res(res'left (1),res'right(2),res'left (3)) := v2;
+    res(res'right(1),res'right(2),res'left (3)) := v2;
+    res(res'left (1),res'left (2),res'right(3)) := v2;
+    res(res'right(1),res'left (2),res'right(3)) := v2;
+    res(res'left (1),res'right(2),res'right(3)) := v2;
+    res(res'right(1),res'right(2),res'right(3)) := v2;
+    RETURN res;
+  END;
+  
+--
+--          Resolution Functions
+--
+  FUNCTION rf_scre_1 ( v: t_scre_1_vct ) RETURN t_scre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_scre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_1 ( v: t_csa1_1_vct ) RETURN t_csa1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  FUNCTION rf_csa1_2 ( v: t_csa1_2_vct ) RETURN t_csa1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_3 ( v: t_csa1_3_vct ) RETURN t_csa1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa1_4 ( v: t_csa1_4_vct ) RETURN t_csa1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa2_1 ( v: t_csa2_1_vct ) RETURN t_csa2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa3_1 ( v: t_csa3_1_vct ) RETURN t_csa3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_csa4_1 ( v: t_csa4_1_vct ) RETURN t_csa4_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_csa4_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_1 ( v: t_cca1_1_vct ) RETURN t_cca1_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cca1_2 ( v: t_cca1_2_vct ) RETURN t_cca1_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_3 ( v: t_cca1_3_vct ) RETURN t_cca1_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_4 ( v: t_cca1_4_vct ) RETURN t_cca1_4 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_4;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_1 ( v: t_cca2_1_vct ) RETURN t_cca2_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca2_2 ( v: t_cca2_2_vct ) RETURN t_cca2_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca2_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_1 ( v: t_cca3_1_vct ) RETURN t_cca3_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca3_2 ( v: t_cca3_2_vct ) RETURN t_cca3_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca3_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+
+  FUNCTION rf_cmre_1 ( v: t_cmre_1_vct ) RETURN t_cmre_1 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_1;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_2 ( v: t_cmre_2_vct ) RETURN t_cmre_2 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_2;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cca1_7 ( v: t_cca1_7_vct ) RETURN t_cca1_7 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cca1_7;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+  
+  FUNCTION rf_cmre_3 ( v: t_cmre_3_vct ) RETURN t_cmre_3 IS
+  BEGIN
+    IF v'LENGTH=0
+    THEN RETURN CX_cmre_3;
+    ELSE RETURN v(1);
+    END IF;
+  END;
+-- 
+-- 
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl1; END IF;
+    IF i = 1 THEN RETURN C1_scl1; END IF;
+    IF i = 2 THEN RETURN C2_scl1; END IF;
+    RETURN CX_scl1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN TIME IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl2; END IF;
+    IF i = 1 THEN RETURN C1_scl2; END IF;
+    IF i = 2 THEN RETURN C2_scl2; END IF;
+    RETURN CX_scl2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl3; END IF;
+    IF i = 1 THEN RETURN C1_scl3; END IF;
+    IF i = 2 THEN RETURN C2_scl3; END IF;
+    RETURN CX_scl3;
+  END;
+
+  FUNCTION val_t ( i : INTEGER ) RETURN st_scl4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scl4; END IF;
+    IF i = 1 THEN RETURN C1_scl4; END IF;
+    IF i = 2 THEN RETURN C2_scl4; END IF;
+    RETURN CX_scl4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_scre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_scre_1; END IF;
+    IF i = 1 THEN RETURN C1_scre_1; END IF;
+    IF i = 2 THEN RETURN C2_scre_1; END IF;
+    RETURN CX_scre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_1; END IF;
+    IF i = 1 THEN RETURN C1_csa1_1; END IF;
+    IF i = 2 THEN RETURN C2_csa1_1; END IF;
+    RETURN CX_csa1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_2; END IF;
+    IF i = 1 THEN RETURN C1_csa1_2; END IF;
+    IF i = 2 THEN RETURN C2_csa1_2; END IF;
+    RETURN CX_csa1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_3; END IF;
+    IF i = 1 THEN RETURN C1_csa1_3; END IF;
+    IF i = 2 THEN RETURN C2_csa1_3; END IF;
+    RETURN CX_csa1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa1_4; END IF;
+    IF i = 1 THEN RETURN C1_csa1_4; END IF;
+    IF i = 2 THEN RETURN C2_csa1_4; END IF;
+    RETURN CX_csa1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa2_1; END IF;
+    IF i = 1 THEN RETURN C1_csa2_1; END IF;
+    IF i = 2 THEN RETURN C2_csa2_1; END IF;
+    RETURN CX_csa2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa3_1; END IF;
+    IF i = 1 THEN RETURN C1_csa3_1; END IF;
+    IF i = 2 THEN RETURN C2_csa3_1; END IF;
+    RETURN CX_csa3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_csa4_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_csa4_1; END IF;
+    IF i = 1 THEN RETURN C1_csa4_1; END IF;
+    IF i = 2 THEN RETURN C2_csa4_1; END IF;
+    RETURN CX_csa4_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_1; END IF;
+    IF i = 1 THEN RETURN C1_cca1_1; END IF;
+    IF i = 2 THEN RETURN C2_cca1_1; END IF;
+    RETURN CX_cca1_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_2; END IF;
+    IF i = 1 THEN RETURN C1_cca1_2; END IF;
+    IF i = 2 THEN RETURN C2_cca1_2; END IF;
+    RETURN CX_cca1_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_3; END IF;
+    IF i = 1 THEN RETURN C1_cca1_3; END IF;
+    IF i = 2 THEN RETURN C2_cca1_3; END IF;
+    RETURN CX_cca1_3;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_4 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_4; END IF;
+    IF i = 1 THEN RETURN C1_cca1_4; END IF;
+    IF i = 2 THEN RETURN C2_cca1_4; END IF;
+    RETURN CX_cca1_4;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_1; END IF;
+    IF i = 1 THEN RETURN C1_cca2_1; END IF;
+    IF i = 2 THEN RETURN C2_cca2_1; END IF;
+    RETURN CX_cca2_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca2_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca2_2; END IF;
+    IF i = 1 THEN RETURN C1_cca2_2; END IF;
+    IF i = 2 THEN RETURN C2_cca2_2; END IF;
+    RETURN CX_cca2_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_1; END IF;
+    IF i = 1 THEN RETURN C1_cca3_1; END IF;
+    IF i = 2 THEN RETURN C2_cca3_1; END IF;
+    RETURN CX_cca3_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca3_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca3_2; END IF;
+    IF i = 1 THEN RETURN C1_cca3_2; END IF;
+    IF i = 2 THEN RETURN C2_cca3_2; END IF;
+    RETURN CX_cca3_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_1 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_1; END IF;
+    IF i = 1 THEN RETURN C1_cmre_1; END IF;
+    IF i = 2 THEN RETURN C2_cmre_1; END IF;
+    RETURN CX_cmre_1;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_2 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_2; END IF;
+    IF i = 1 THEN RETURN C1_cmre_2; END IF;
+    IF i = 2 THEN RETURN C2_cmre_2; END IF;
+    RETURN CX_cmre_2;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cca1_7 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cca1_7; END IF;
+    IF i = 1 THEN RETURN C1_cca1_7; END IF;
+    IF i = 2 THEN RETURN C2_cca1_7; END IF;
+    RETURN CX_cca1_7;
+  END;
+  FUNCTION val_t ( i : INTEGER ) RETURN t_cmre_3 IS
+  BEGIN
+    IF i = 0 THEN RETURN C0_cmre_3; END IF;
+    IF i = 1 THEN RETURN C1_cmre_3; END IF;
+    IF i = 2 THEN RETURN C2_cmre_3; END IF;
+    RETURN CX_cmre_3;
+  END;
+--
+-- 
+  FUNCTION val_i ( i : st_scl1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN 0; END IF;
+    IF i = C1_scl1 THEN RETURN 1; END IF;
+    IF i = C2_scl1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : TIME ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN 0; END IF;
+    IF i = C1_scl2 THEN RETURN 1; END IF;
+    IF i = C2_scl2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN 0; END IF;
+    IF i = C1_scl3 THEN RETURN 1; END IF;
+    IF i = C2_scl3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : st_scl4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN 0; END IF;
+    IF i = C1_scl4 THEN RETURN 1; END IF;
+    IF i = C2_scl4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_scre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN 0; END IF;
+    IF i = C1_scre_1 THEN RETURN 1; END IF;
+    IF i = C2_scre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN 0; END IF;
+    IF i = C1_csa1_1 THEN RETURN 1; END IF;
+    IF i = C2_csa1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN 0; END IF;
+    IF i = C1_csa1_2 THEN RETURN 1; END IF;
+    IF i = C2_csa1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN 0; END IF;
+    IF i = C1_csa1_3 THEN RETURN 1; END IF;
+    IF i = C2_csa1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN 0; END IF;
+    IF i = C1_csa1_4 THEN RETURN 1; END IF;
+    IF i = C2_csa1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN 0; END IF;
+    IF i = C1_csa2_1 THEN RETURN 1; END IF;
+    IF i = C2_csa2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN 0; END IF;
+    IF i = C1_csa3_1 THEN RETURN 1; END IF;
+    IF i = C2_csa3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_csa4_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN 0; END IF;
+    IF i = C1_csa4_1 THEN RETURN 1; END IF;
+    IF i = C2_csa4_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN 0; END IF;
+    IF i = C1_cca1_1 THEN RETURN 1; END IF;
+    IF i = C2_cca1_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN 0; END IF;
+    IF i = C1_cca1_2 THEN RETURN 1; END IF;
+    IF i = C2_cca1_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN 0; END IF;
+    IF i = C1_cca1_3 THEN RETURN 1; END IF;
+    IF i = C2_cca1_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_4 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN 0; END IF;
+    IF i = C1_cca1_4 THEN RETURN 1; END IF;
+    IF i = C2_cca1_4 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN 0; END IF;
+    IF i = C1_cca2_1 THEN RETURN 1; END IF;
+    IF i = C2_cca2_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca2_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN 0; END IF;
+    IF i = C1_cca2_2 THEN RETURN 1; END IF;
+    IF i = C2_cca2_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN 0; END IF;
+    IF i = C1_cca3_1 THEN RETURN 1; END IF;
+    IF i = C2_cca3_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca3_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN 0; END IF;
+    IF i = C1_cca3_2 THEN RETURN 1; END IF;
+    IF i = C2_cca3_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_1 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN 0; END IF;
+    IF i = C1_cmre_1 THEN RETURN 1; END IF;
+    IF i = C2_cmre_1 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_2 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN 0; END IF;
+    IF i = C1_cmre_2 THEN RETURN 1; END IF;
+    IF i = C2_cmre_2 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cca1_7 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN 0; END IF;
+    IF i = C1_cca1_7 THEN RETURN 1; END IF;
+    IF i = C2_cca1_7 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  FUNCTION val_i ( i : t_cmre_3 ) RETURN INTEGER IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN 0; END IF;
+    IF i = C1_cmre_3 THEN RETURN 1; END IF;
+    IF i = C2_cmre_3 THEN RETURN 2; END IF;
+    RETURN -1;
+  END;
+  
+  FUNCTION val_s ( i : st_scl1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl1 THEN RETURN "C0_scl1"; END IF;
+    IF i = C1_scl1 THEN RETURN "C1_scl1"; END IF;
+    IF i = C2_scl1 THEN RETURN "C2_scl1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : TIME ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl2 THEN RETURN "C0_scl2"; END IF;
+    IF i = C1_scl2 THEN RETURN "C1_scl2"; END IF;
+    IF i = C2_scl2 THEN RETURN "C2_scl2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl3 THEN RETURN "C0_scl3"; END IF;
+    IF i = C1_scl3 THEN RETURN "C1_scl3"; END IF;
+    IF i = C2_scl3 THEN RETURN "C2_scl3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : st_scl4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scl4 THEN RETURN "C0_scl4"; END IF;
+    IF i = C1_scl4 THEN RETURN "C1_scl4"; END IF;
+    IF i = C2_scl4 THEN RETURN "C2_scl4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_scre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_scre_1 THEN RETURN "C0_scre_1"; END IF;
+    IF i = C1_scre_1 THEN RETURN "C1_scre_1"; END IF;
+    IF i = C2_scre_1 THEN RETURN "C2_scre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_1 THEN RETURN "C0_csa1_1"; END IF;
+    IF i = C1_csa1_1 THEN RETURN "C1_csa1_1"; END IF;
+    IF i = C2_csa1_1 THEN RETURN "C2_csa1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_2 THEN RETURN "C0_csa1_2"; END IF;
+    IF i = C1_csa1_2 THEN RETURN "C1_csa1_2"; END IF;
+    IF i = C2_csa1_2 THEN RETURN "C2_csa1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_3 THEN RETURN "C0_csa1_3"; END IF;
+    IF i = C1_csa1_3 THEN RETURN "C1_csa1_3"; END IF;
+    IF i = C2_csa1_3 THEN RETURN "C2_csa1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa1_4 THEN RETURN "C0_csa1_4"; END IF;
+    IF i = C1_csa1_4 THEN RETURN "C1_csa1_4"; END IF;
+    IF i = C2_csa1_4 THEN RETURN "C2_csa1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa2_1 THEN RETURN "C0_csa2_1"; END IF;
+    IF i = C1_csa2_1 THEN RETURN "C1_csa2_1"; END IF;
+    IF i = C2_csa2_1 THEN RETURN "C2_csa2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa3_1 THEN RETURN "C0_csa3_1"; END IF;
+    IF i = C1_csa3_1 THEN RETURN "C1_csa3_1"; END IF;
+    IF i = C2_csa3_1 THEN RETURN "C2_csa3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_csa4_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_csa4_1 THEN RETURN "C0_csa4_1"; END IF;
+    IF i = C1_csa4_1 THEN RETURN "C1_csa4_1"; END IF;
+    IF i = C2_csa4_1 THEN RETURN "C2_csa4_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_1 THEN RETURN "C0_cca1_1"; END IF;
+    IF i = C1_cca1_1 THEN RETURN "C1_cca1_1"; END IF;
+    IF i = C2_cca1_1 THEN RETURN "C2_cca1_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_2 THEN RETURN "C0_cca1_2"; END IF;
+    IF i = C1_cca1_2 THEN RETURN "C1_cca1_2"; END IF;
+    IF i = C2_cca1_2 THEN RETURN "C2_cca1_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_3 THEN RETURN "C0_cca1_3"; END IF;
+    IF i = C1_cca1_3 THEN RETURN "C1_cca1_3"; END IF;
+    IF i = C2_cca1_3 THEN RETURN "C2_cca1_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_4 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_4 THEN RETURN "C0_cca1_4"; END IF;
+    IF i = C1_cca1_4 THEN RETURN "C1_cca1_4"; END IF;
+    IF i = C2_cca1_4 THEN RETURN "C2_cca1_4"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_1 THEN RETURN "C0_cca2_1"; END IF;
+    IF i = C1_cca2_1 THEN RETURN "C1_cca2_1"; END IF;
+    IF i = C2_cca2_1 THEN RETURN "C2_cca2_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca2_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca2_2 THEN RETURN "C0_cca2_2"; END IF;
+    IF i = C1_cca2_2 THEN RETURN "C1_cca2_2"; END IF;
+    IF i = C2_cca2_2 THEN RETURN "C2_cca2_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_1 THEN RETURN "C0_cca3_1"; END IF;
+    IF i = C1_cca3_1 THEN RETURN "C1_cca3_1"; END IF;
+    IF i = C2_cca3_1 THEN RETURN "C2_cca3_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca3_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca3_2 THEN RETURN "C0_cca3_2"; END IF;
+    IF i = C1_cca3_2 THEN RETURN "C1_cca3_2"; END IF;
+    IF i = C2_cca3_2 THEN RETURN "C2_cca3_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_1 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_1 THEN RETURN "C0_cmre_1"; END IF;
+    IF i = C1_cmre_1 THEN RETURN "C1_cmre_1"; END IF;
+    IF i = C2_cmre_1 THEN RETURN "C2_cmre_1"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_2 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_2 THEN RETURN "C0_cmre_2"; END IF;
+    IF i = C1_cmre_2 THEN RETURN "C1_cmre_2"; END IF;
+    IF i = C2_cmre_2 THEN RETURN "C2_cmre_2"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cca1_7 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cca1_7 THEN RETURN "C0_cca1_7"; END IF;
+    IF i = C1_cca1_7 THEN RETURN "C1_cca1_7"; END IF;
+    IF i = C2_cca1_7 THEN RETURN "C2_cca1_7"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  FUNCTION val_s ( i : t_cmre_3 ) RETURN STRING IS
+  BEGIN
+    IF i = C0_cmre_3 THEN RETURN "C0_cmre_3"; END IF;
+    IF i = C1_cmre_3 THEN RETURN "C1_cmre_3"; END IF;
+    IF i = C2_cmre_3 THEN RETURN "C2_cmre_3"; END IF;
+    RETURN "UNKNOWN";
+  END;
+  
+END c03s03b00x00p03n04i00521pkg;
+
+USE   work.c03s03b00x00p03n04i00521pkg.ALL;
+ENTITY c03s03b00x00p03n04i00521ent IS
+END c03s03b00x00p03n04i00521ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00521arch OF c03s03b00x00p03n04i00521ent IS
+--
+--          Access type declarations
+--
+  TYPE at_usa2_1 IS ACCESS t_usa2_1 ;
+  TYPE at_usa3_1 IS ACCESS t_usa3_1 ;
+  TYPE at_usa4_1 IS ACCESS t_usa4_1 ;
+  TYPE at_csa2_1 IS ACCESS t_csa2_1 ;
+  TYPE at_csa3_1 IS ACCESS t_csa3_1 ;
+  TYPE at_csa4_1 IS ACCESS t_csa4_1 ;
+  TYPE at_cca2_1 IS ACCESS t_cca2_1 ;
+  TYPE at_cca2_2 IS ACCESS t_cca2_2 ;
+  TYPE at_cca3_1 IS ACCESS t_cca3_1 ;
+  TYPE at_cca3_2 IS ACCESS t_cca3_2 ;
+--
+--
+BEGIN
+  TESTING: PROCESS
+--
+--          ACCESS VARIABLE declarations
+--
+    VARIABLE AV0_usa2_1 : at_usa2_1 ;
+    VARIABLE AV2_usa2_1 : at_usa2_1 ;
+    VARIABLE AV0_usa3_1 : at_usa3_1 ;
+    VARIABLE AV2_usa3_1 : at_usa3_1 ;
+    VARIABLE AV0_usa4_1 : at_usa4_1 ;
+    VARIABLE AV2_usa4_1 : at_usa4_1 ;
+    VARIABLE AV0_csa2_1 : at_csa2_1 ;
+    VARIABLE AV2_csa2_1 : at_csa2_1 ;
+    VARIABLE AV0_csa3_1 : at_csa3_1 ;
+    VARIABLE AV2_csa3_1 : at_csa3_1 ;
+    VARIABLE AV0_csa4_1 : at_csa4_1 ;
+    VARIABLE AV2_csa4_1 : at_csa4_1 ;
+    VARIABLE AV0_cca2_1 : at_cca2_1 ;
+    VARIABLE AV2_cca2_1 : at_cca2_1 ;
+    VARIABLE AV0_cca2_2 : at_cca2_2 ;
+    VARIABLE AV2_cca2_2 : at_cca2_2 ;
+    VARIABLE AV0_cca3_1 : at_cca3_1 ;
+    VARIABLE AV2_cca3_1 : at_cca3_1 ;
+    VARIABLE AV0_cca3_2 : at_cca3_2 ;
+    VARIABLE AV2_cca3_2 : at_cca3_2 ;
+--
+--
+  BEGIN
+--
+--          Allocation of access values
+--
+    AV0_usa2_1 := NEW t_usa2_1 (                  st_ind2, st_ind1 ) ;
+    AV0_usa3_1 := NEW t_usa3_1 (         st_ind3, st_ind2, st_ind1 ) ;
+    AV0_usa4_1 := NEW t_usa4_1 (st_ind4, st_ind3, st_ind2, st_ind1 ) ;
+    AV0_csa2_1 := NEW t_csa2_1 ;
+    AV0_csa3_1 := NEW t_csa3_1 ;
+    AV0_csa4_1 := NEW t_csa4_1 ;
+    AV0_cca2_1 := NEW t_cca2_1 ;
+    AV0_cca2_2 := NEW t_cca2_2 ;
+    AV0_cca3_1 := NEW t_cca3_1 ;
+    AV0_cca3_2 := NEW t_cca3_2 ;
+---
+    AV2_usa2_1 := NEW t_usa2_1 ' ( C2_csa2_1 ) ;
+    AV2_usa3_1 := NEW t_usa3_1 ' ( C2_csa3_1 ) ;
+    AV2_usa4_1 := NEW t_usa4_1 ' ( C2_csa4_1 ) ;
+    AV2_csa2_1 := NEW t_csa2_1 ' ( C2_csa2_1 ) ;
+    AV2_csa3_1 := NEW t_csa3_1 ' ( C2_csa3_1 ) ;
+    AV2_csa4_1 := NEW t_csa4_1 ' ( C2_csa4_1 ) ;
+    AV2_cca2_1 := NEW t_cca2_1 ' ( C2_cca2_1 ) ;
+    AV2_cca2_2 := NEW t_cca2_2 ' ( C2_cca2_2 ) ;
+    AV2_cca3_1 := NEW t_cca3_1 ' ( C2_cca3_1 ) ;
+    AV2_cca3_2 := NEW t_cca3_2 ' ( C2_cca3_2 ) ;
+--
+--
+    ASSERT AV0_usa2_1.all = C0_csa2_1  
+      REPORT "Improper initialization of AV0_usa2_1" SEVERITY FAILURE;
+    ASSERT AV2_usa2_1.all = C2_csa2_1  
+      REPORT "Improper initialization of AV2_usa2_1" SEVERITY FAILURE;
+    ASSERT AV0_usa3_1.all = C0_csa3_1  
+      REPORT "Improper initialization of AV0_usa3_1" SEVERITY FAILURE;
+    ASSERT AV2_usa3_1.all = C2_csa3_1  
+      REPORT "Improper initialization of AV2_usa3_1" SEVERITY FAILURE;
+    ASSERT AV0_usa4_1.all = C0_csa4_1  
+      REPORT "Improper initialization of AV0_usa4_1" SEVERITY FAILURE;
+    ASSERT AV2_usa4_1.all = C2_csa4_1  
+      REPORT "Improper initialization of AV2_usa4_1" SEVERITY FAILURE;
+    ASSERT AV0_csa2_1.all = C0_csa2_1  
+      REPORT "Improper initialization of AV0_csa2_1" SEVERITY FAILURE;
+    ASSERT AV2_csa2_1.all = C2_csa2_1  
+      REPORT "Improper initialization of AV2_csa2_1" SEVERITY FAILURE;
+    ASSERT AV0_csa3_1.all = C0_csa3_1  
+      REPORT "Improper initialization of AV0_csa3_1" SEVERITY FAILURE;
+    ASSERT AV2_csa3_1.all = C2_csa3_1  
+      REPORT "Improper initialization of AV2_csa3_1" SEVERITY FAILURE;
+    ASSERT AV0_csa4_1.all = C0_csa4_1  
+      REPORT "Improper initialization of AV0_csa4_1" SEVERITY FAILURE;
+    ASSERT AV2_csa4_1.all = C2_csa4_1  
+      REPORT "Improper initialization of AV2_csa4_1" SEVERITY FAILURE;
+    ASSERT AV0_cca2_1.all = C0_cca2_1  
+      REPORT "Improper initialization of AV0_cca2_1" SEVERITY FAILURE;
+    ASSERT AV2_cca2_1.all = C2_cca2_1  
+      REPORT "Improper initialization of AV2_cca2_1" SEVERITY FAILURE;
+    ASSERT AV0_cca2_2.all = C0_cca2_2  
+      REPORT "Improper initialization of AV0_cca2_2" SEVERITY FAILURE;
+    ASSERT AV2_cca2_2.all = C2_cca2_2  
+      REPORT "Improper initialization of AV2_cca2_2" SEVERITY FAILURE;
+    ASSERT AV0_cca3_1.all = C0_cca3_1  
+      REPORT "Improper initialization of AV0_cca3_1" SEVERITY FAILURE;
+    ASSERT AV2_cca3_1.all = C2_cca3_1  
+      REPORT "Improper initialization of AV2_cca3_1" SEVERITY FAILURE;
+    ASSERT AV0_cca3_2.all = C0_cca3_2  
+      REPORT "Improper initialization of AV0_cca3_2" SEVERITY FAILURE;
+    ASSERT AV2_cca3_2.all = C2_cca3_2  
+      REPORT "Improper initialization of AV2_cca3_2" SEVERITY FAILURE;
+--
+--
+    assert NOT( ( AV0_usa2_1.all = C0_csa2_1 ) 
+                and ( AV2_usa2_1.all = C2_csa2_1 ) 
+                and ( AV0_usa3_1.all = C0_csa3_1 ) 
+                and ( AV2_usa3_1.all = C2_csa3_1 ) 
+                and ( AV0_usa4_1.all = C0_csa4_1 ) 
+                and ( AV2_usa4_1.all = C2_csa4_1 ) 
+                and ( AV0_csa2_1.all = C0_csa2_1 ) 
+                and ( AV2_csa2_1.all = C2_csa2_1 ) 
+                and ( AV0_csa3_1.all = C0_csa3_1 ) 
+                and ( AV2_csa3_1.all = C2_csa3_1 )) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00521"
+      severity NOTE;
+    assert  (   ( AV0_usa2_1.all = C0_csa2_1 ) 
+                and ( AV2_usa2_1.all = C2_csa2_1 ) 
+                and ( AV0_usa3_1.all = C0_csa3_1 ) 
+                and ( AV2_usa3_1.all = C2_csa3_1 ) 
+                and ( AV0_usa4_1.all = C0_csa4_1 ) 
+                and ( AV2_usa4_1.all = C2_csa4_1 ) 
+                and ( AV0_csa2_1.all = C0_csa2_1 ) 
+                and ( AV2_csa2_1.all = C2_csa2_1 ) 
+                and ( AV0_csa3_1.all = C0_csa3_1 ) 
+                and ( AV2_csa3_1.all = C2_csa3_1 )) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00521 - Each access value designates an object of the subtype defined by the subtype indication of the access type definition."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00521arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc522.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc522.vhd
new file mode 100644
index 0000000..1226d5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc522.vhd
@@ -0,0 +1,217 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc522.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n01i00522ent IS
+END c03s03b00x00p03n01i00522ent;
+
+ARCHITECTURE c03s03b00x00p03n01i00522arch OF c03s03b00x00p03n01i00522ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare access types and access objects everywhere.
+    -- Enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    type    AC1 is access SWITCH_LEVEL;
+
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    type    AC2 is access LOGIC_SWITCH;
+
+    -- Access types.
+    type    AC3 is access AC2;
+
+    -- array types.  Constrained.
+    type WORD   is array(0 to 31) of BIT;
+    type    AC4 is access WORD;
+
+    -- record types.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    type AC5 is access DATE;
+
+    -- INTEGER types.
+    type AC6 is access INTEGER;
+    
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    type AC7 is access POSITIVE;
+    
+    -- Physical types.
+    type AC8 is access TIME;
+    
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+    type AC10 is access DISTANCE;
+    
+    -- floating point types.
+    type AC11 is access REAL;
+    
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    type AC12 is access POSITIVE_R;
+    -- Predefined enumerated types.
+    type AC13 is access BIT;
+    
+    type AC14 is access SEVERITY_LEVEL;
+    
+    type AC15 is access BOOLEAN;
+    
+    type AC16 is access CHARACTER;
+    
+    -- Other predefined types.
+    type AC17 is access NATURAL;
+    
+    type AC18 is access STRING;
+    
+    type AC19 is access BIT_VECTOR;
+    
+    type MEMORY is array(0 to 64) of WORD;
+    type AC20 is access MEMORY;
+    
+    -- Declare all the variables.
+    variable VAR1 : AC1;
+    variable VAR2 : AC2;
+    variable VAR3 : AC3;
+    variable VAR4 : AC4;
+    variable VAR5 : AC5;
+    variable VAR6 : AC6;
+    variable VAR7 : AC7;
+    variable VAR8 : AC8;
+    variable VAR10: AC10;
+    variable VAR11: AC11;
+    variable VAR12: AC12;
+    variable VAR13: AC13;
+    variable VAR14: AC14;
+    variable VAR15: AC15;
+    variable VAR16: AC16;
+    variable VAR17: AC17;
+    variable VAR18: AC18;
+    variable VAR19: AC19;
+    variable VAR20: AC20;
+  BEGIN
+    -- Assert that all variables are initially NULL.
+    assert (VAR1 = null)
+      report "VAR1 has not been set to NULL.";
+    assert (VAR2 = null)
+      report "VAR2 has not been set to NULL.";
+    assert (VAR3 = null)
+      report "VAR3 has not been set to NULL.";
+    assert (VAR4 = null)
+      report "VAR4 has not been set to NULL.";
+    assert (VAR5 = null)
+      report "VAR5 has not been set to NULL.";
+    assert (VAR6 = null)
+      report "VAR6 has not been set to NULL.";
+    assert (VAR7 = null)
+      report "VAR7 has not been set to NULL.";
+    assert (VAR8 = null)
+      report "VAR8 has not been set to NULL.";
+    assert (VAR10 = null)
+      report "VAR10 has not been set to NULL.";
+    assert (VAR11 = null)
+      report "VAR11 has not been set to NULL.";
+    assert (VAR12 = null)
+      report "VAR12 has not been set to NULL.";
+    assert (VAR13 = null)
+      report "VAR13 has not been set to NULL.";
+    assert (VAR14 = null)
+      report "VAR14 has not been set to NULL.";
+    assert (VAR15 = null)
+      report "VAR15 has not been set to NULL.";
+    assert (VAR16 = null)
+      report "VAR16 has not been set to NULL.";
+    assert (VAR17 = null)
+      report "VAR17 has not been set to NULL.";
+    assert (VAR18 = null)
+      report "VAR18 has not been set to NULL.";
+    assert (VAR19 = null)
+      report "VAR19 has not been set to NULL.";
+    assert (VAR20 = null)
+      report "VAR20 has not been set to NULL.";
+    assert   NOT(      (VAR1 = null)
+                       and (VAR2 = null)
+                       and (VAR3 = null)
+                       and (VAR4 = null)
+                       and (VAR5 = null)
+                       and (VAR6 = null)
+                       and (VAR7 = null)
+                       and (VAR8 = null)
+                       and (VAR10 = null)
+                       and (VAR11 = null)
+                       and (VAR12 = null)
+                       and (VAR13 = null)
+                       and (VAR14 = null)
+                       and (VAR15 = null)
+                       and (VAR16 = null)
+                       and (VAR17 = null)
+                       and (VAR18 = null)
+                       and (VAR19 = null)
+                       and (VAR20 = null))
+      report "***PASSED TEST: c03s03b00x00p03n01i00522"
+      severity NOTE;
+    assert   (      (VAR1 = null)
+                    and (VAR2 = null)
+                    and (VAR3 = null)
+                    and (VAR4 = null)
+                    and (VAR5 = null)
+                    and (VAR6 = null)
+                    and (VAR7 = null)
+                    and (VAR8 = null)
+                    and (VAR10 = null)
+                    and (VAR11 = null)
+                    and (VAR12 = null)
+                    and (VAR13 = null)
+                    and (VAR14 = null)
+                    and (VAR15 = null)
+                    and (VAR16 = null)
+                    and (VAR17 = null)
+                    and (VAR18 = null)
+                    and (VAR19 = null)
+                    and (VAR20 = null))
+      report "***FAILED TEST: c03s03b00x00p03n01i00522 - The null value of an access type is the default initial value of the type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n01i00522arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc523.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc523.vhd
new file mode 100644
index 0000000..3f4d14d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc523.vhd
@@ -0,0 +1,127 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc523.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c03s03b00x00p03n03i00523pkg is
+  type udf_int       is range -500 to 500;
+  type udf_real       is range -2000.0 to 2000.0;
+  type udf_int_ptr    is access udf_int;
+  type udf_real_ptr    is access udf_real;
+end c03s03b00x00p03n03i00523pkg;
+
+use work.c03s03b00x00p03n03i00523pkg.all;
+
+ENTITY c03s03b00x00p03n03i00523ent IS
+END c03s03b00x00p03n03i00523ent;
+
+ARCHITECTURE c03s03b00x00p03n03i00523arch OF c03s03b00x00p03n03i00523ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype int_ptr is udf_int_ptr;
+    
+    variable v_int_ptr1: int_ptr    := new udf_int'(365);
+    variable v_int_ptr2: int_ptr;
+    variable v_int_ptr3: int_ptr    := v_int_ptr1;
+    variable v_int_ptr4: int_ptr    := new udf_int'(-365);
+    
+    subtype real_ptr is udf_real_ptr;
+    
+    variable v_real_ptr1: real_ptr    := new udf_real'(365.12);
+    variable v_real_ptr2: real_ptr;
+    variable v_real_ptr3: real_ptr    := v_real_ptr1;
+    variable v_real_ptr4: real_ptr    := new udf_real'(-365.12);
+    constant epislon: udf_real    := 0.00001;
+
+  BEGIN
+
+    assert v_int_ptr1.all    = 365;
+    assert v_int_ptr2    = null;
+    assert v_int_ptr3.all    = 365;
+    assert v_int_ptr4.all    = -365;
+    
+    v_int_ptr2 := new udf_int'(100);
+    
+    assert v_int_ptr2.all    = 100;
+    
+    assert (v_int_ptr1.all + v_int_ptr3.all) = 730;
+    assert (v_int_ptr2.all + v_int_ptr3.all) = 465;
+    assert (v_int_ptr1.all + v_int_ptr4.all) = 0;
+    assert (v_int_ptr1.all - v_int_ptr3.all) = 0;
+    assert (v_int_ptr3.all * v_int_ptr1.all) = 133225;
+    assert (v_int_ptr3.all / v_int_ptr1.all) = 1;
+
+    assert v_real_ptr1.all    = 365.12;
+    assert v_real_ptr2    = null;
+    assert v_real_ptr3.all    = 365.12;
+    assert v_real_ptr4.all    = -365.12;
+    
+    v_real_ptr2 := new udf_real'(100.0);
+    
+    assert v_real_ptr2.all    = 100.0;
+    
+    assert (v_real_ptr1.all + v_real_ptr3.all - 730.24 < epislon);
+    assert (v_real_ptr1.all + v_real_ptr2.all - 465.12 < epislon);
+    assert (v_real_ptr1.all + v_real_ptr4.all < epislon);
+    assert (v_real_ptr1.all - v_real_ptr3.all < epislon);
+    assert (v_real_ptr1.all * v_real_ptr3.all - 133312.6144 < epislon);
+    assert (v_real_ptr1.all / v_real_ptr3.all - 1.0 < epislon);
+
+    assert NOT(((v_int_ptr1.all + v_int_ptr3.all) = 730)   and
+               (  (v_int_ptr2.all + v_int_ptr3.all) = 465)   and
+               (  (v_int_ptr1.all + v_int_ptr4.all) = 0)   and
+               (  (v_int_ptr1.all - v_int_ptr3.all) = 0)   and
+               (  (v_int_ptr3.all * v_int_ptr1.all) = 133225)   and
+               (  (v_int_ptr3.all / v_int_ptr1.all) = 1)   and
+               (  (v_real_ptr1.all + v_real_ptr3.all - 730.24 < epislon))   and
+               (  (v_real_ptr1.all + v_real_ptr2.all - 465.12 < epislon))   and
+               (  (v_real_ptr1.all + v_real_ptr4.all < epislon))      and
+               (  (v_real_ptr1.all - v_real_ptr3.all < epislon))      and
+               (  (v_real_ptr1.all * v_real_ptr3.all - 133312.6144 < epislon))and
+               (  (v_real_ptr1.all / v_real_ptr3.all - 1.0 < epislon)))   
+      report "***PASSED TEST: c03s03b00x00p03n03i00523"
+      severity NOTE;
+    assert   (( (v_int_ptr1.all + v_int_ptr3.all) = 730)   and
+              (  (v_int_ptr2.all + v_int_ptr3.all) = 465)   and
+              (  (v_int_ptr1.all + v_int_ptr4.all) = 0)   and
+              (  (v_int_ptr1.all - v_int_ptr3.all) = 0)   and
+              (  (v_int_ptr3.all * v_int_ptr1.all) = 133225)   and
+              (  (v_int_ptr3.all / v_int_ptr1.all) = 1)   and
+              (  (v_real_ptr1.all + v_real_ptr3.all - 730.24 < epislon))   and
+              (  (v_real_ptr1.all + v_real_ptr2.all - 465.12 < epislon))   and
+              (  (v_real_ptr1.all + v_real_ptr4.all < epislon))      and
+              (  (v_real_ptr1.all - v_real_ptr3.all < epislon))      and
+              (  (v_real_ptr1.all * v_real_ptr3.all - 133312.6144 < epislon))and
+              (  (v_real_ptr1.all / v_real_ptr3.all - 1.0 < epislon)))   
+      report "***FAILED TEST: c03s03b00x00p03n03i00523 - User defined integer and floating point types to test for user defined integer and floating point using as base for access type failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n03i00523arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc524.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc524.vhd
new file mode 100644
index 0000000..15fc8fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc524.vhd
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc524.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00524ent IS
+END c03s03b00x00p03n04i00524ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00524arch OF c03s03b00x00p03n04i00524ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type integer_ptr is access integer;
+    variable v_integer_ptr1: integer_ptr := new integer'(365);
+    variable v_integer_ptr2: integer_ptr;
+    variable v_integer_ptr3: integer_ptr := v_integer_ptr1;
+
+
+    type int is range -500 to 500;
+    type int_ptr is access int;
+    variable v_int_ptr1: int_ptr := new int'(365);
+    variable v_int_ptr2: int_ptr;
+    variable v_int_ptr3: int_ptr := v_int_ptr1;
+    variable v_int_ptr4: int_ptr := new int'(-365);
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_integer_ptr1.all = 365;
+    if (v_integer_ptr1.all = 365) then
+      Oktest := OKtest + 1;
+    end if;
+    assert v_integer_ptr2     = null;
+    if (v_integer_ptr2     = null) then
+      Oktest := OKtest + 1;
+    end if;
+    assert v_integer_ptr3.all = 365;
+    if (v_integer_ptr3.all = 365) then
+      Oktest := OKtest + 1;
+    end if;
+
+    assert (v_integer_ptr1.all + v_integer_ptr3.all) = 730;
+    if ((v_integer_ptr1.all + v_integer_ptr3.all) = 730) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_integer_ptr1.all - v_integer_ptr3.all) = 0;
+    if ((v_integer_ptr1.all - v_integer_ptr3.all) = 0) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_integer_ptr3.all * v_integer_ptr1.all) = 133225;
+    if ((v_integer_ptr3.all * v_integer_ptr1.all) = 133225) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_integer_ptr3.all / v_integer_ptr1.all) = 1;
+    if ((v_integer_ptr3.all / v_integer_ptr1.all) = 1) then
+      Oktest := OKtest + 1;
+    end if;
+
+    deallocate(v_integer_ptr2);
+    deallocate(v_integer_ptr1);
+
+    assert v_int_ptr1.all = 365;
+    if (v_int_ptr1.all = 365) then
+      Oktest := OKtest + 1;
+    end if;
+    assert v_int_ptr2 = null;
+    if (v_int_ptr2 = null) then
+      Oktest := OKtest + 1;
+    end if;
+    assert v_int_ptr3.all = 365;
+    if (v_int_ptr3.all = 365) then
+      Oktest := OKtest + 1;
+    end if;
+    assert v_int_ptr4.all = -365;
+    if (v_int_ptr4.all = -365) then
+      Oktest := OKtest + 1;
+    end if;
+
+    v_int_ptr2 := new int'(100);
+
+    assert v_int_ptr2.all = 100;
+    if (v_int_ptr2.all = 100) then
+      Oktest := OKtest + 1;
+    end if;
+
+    assert (v_int_ptr1.all + v_int_ptr3.all) = 730;
+    if ((v_int_ptr1.all + v_int_ptr3.all) = 730) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_int_ptr2.all + v_int_ptr3.all) = 465;
+    if ((v_int_ptr2.all + v_int_ptr3.all) = 465) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_int_ptr1.all + v_int_ptr4.all) = 0;
+    if ((v_int_ptr1.all + v_int_ptr4.all) = 0) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_int_ptr1.all - v_int_ptr3.all) = 0;
+    if ((v_int_ptr1.all - v_int_ptr3.all) = 0) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_int_ptr3.all * v_int_ptr1.all) = 133225;
+    if ((v_int_ptr3.all * v_int_ptr1.all) = 133225) then
+      Oktest := OKtest + 1;
+    end if;
+    assert (v_int_ptr3.all / v_int_ptr1.all) = 1;
+    if ((v_int_ptr3.all / v_int_ptr1.all) = 1) then
+      Oktest := OKtest + 1;
+    end if;
+
+    assert NOT(OKtest = 18) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00524"
+      severity NOTE;
+    assert (OKtest = 18) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00524 - Integer type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00524arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc525.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc525.vhd
new file mode 100644
index 0000000..86ea8c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc525.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc525.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00525ent IS
+END c03s03b00x00p03n04i00525ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00525arch OF c03s03b00x00p03n04i00525ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type bit_ptr is access bit;
+    variable v_bit_ptr1: bit_ptr := new bit'('1');
+    variable v_bit_ptr2: bit_ptr;
+    variable v_bit_ptr3: bit_ptr := v_bit_ptr1;
+    variable v_bit_ptr4: bit_ptr := new bit'('0');
+    variable v_bit_ptr5: bit_ptr := v_bit_ptr4;
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_bit_ptr1.all = '1';
+    if (v_bit_ptr1.all = '1') then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_bit_ptr2 = null;
+    if (v_bit_ptr2 = null) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_bit_ptr3.all = '1';
+    if (v_bit_ptr3.all = '1') then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_bit_ptr4.all = '0';
+    if (v_bit_ptr4.all = '0') then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_bit_ptr5.all = '0';
+    if (v_bit_ptr5.all = '0') then
+      OKtest := OKtest + 1;
+    end if;
+
+    v_bit_ptr2 := new bit'('0');
+
+    assert v_bit_ptr2.all = '0';
+    if (v_bit_ptr2.all = '0') then
+      OKtest := OKtest + 1;
+    end if;
+
+    assert (v_bit_ptr1.all & v_bit_ptr3.all) = "11";
+    if ((v_bit_ptr1.all & v_bit_ptr3.all) = "11") then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_bit_ptr3.all & v_bit_ptr5.all) = "10";
+    if ((v_bit_ptr3.all & v_bit_ptr5.all) = "10") then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_bit_ptr3.all & v_bit_ptr2.all) = "10";
+    if ((v_bit_ptr3.all & v_bit_ptr2.all) = "10") then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_bit_ptr3.all > v_bit_ptr5.all) = true;
+    if ((v_bit_ptr3.all > v_bit_ptr5.all) = true) then
+      OKtest := OKtest + 1;
+    end if;
+
+    deallocate(v_bit_ptr1);
+    deallocate(v_bit_ptr2);
+    deallocate(v_bit_ptr4);
+
+    assert NOT(OKtest = 10) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00525" 
+      severity NOTE;
+    assert (OKtest = 10) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00525 - Bit type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00525arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc526.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc526.vhd
new file mode 100644
index 0000000..2f81a82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc526.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc526.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00526ent IS
+END c03s03b00x00p03n04i00526ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00526arch OF c03s03b00x00p03n04i00526ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type beta is range 1000 downto 0
+      units
+        b1;
+        b2  =  5 b1;
+        b3  =  7 b2;
+        b4  =  1 b3;
+      end units;
+
+    type phys_ptr is access beta;
+    variable v_phys_ptr1: phys_ptr := new beta'(6 b1);
+    variable v_phys_ptr2: phys_ptr;
+    variable v_phys_ptr3: phys_ptr := v_phys_ptr1;
+    variable v_phys_ptr4: phys_ptr := new beta'(1 b3);
+    variable v_phys_ptr5: phys_ptr := v_phys_ptr4;
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_phys_ptr1.all = 6 b1;
+    if (v_phys_ptr1.all = 6 b1) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_phys_ptr2 = null;
+    if (v_phys_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_phys_ptr3.all = 6 b1;
+    if (v_phys_ptr3.all = 6 b1) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_phys_ptr4.all = 1 b3;
+    if (v_phys_ptr4.all = 1 b3) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_phys_ptr5.all = b4;
+    if (v_phys_ptr5.all = b4) then
+      OKtest := Oktest + 1;
+    end if;
+
+    v_phys_ptr2 := new beta'(7 b2);
+
+    assert v_phys_ptr2.all = b3;
+    if (v_phys_ptr2.all = b3) then
+      OKtest := Oktest + 1;
+    end if;
+
+    assert (40 * v_phys_ptr3.all / 6 = 1 b2 + 1 b4);
+    if (40 * v_phys_ptr3.all / 6 = 1 b2 + 1 b4) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_phys_ptr5.all = 1 b2 + 6 b2);
+    if (v_phys_ptr5.all = 1 b2 + 6 b2) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_phys_ptr5.all = v_phys_ptr2.all - 5 * 7 b1 + 1 b4);
+    if (v_phys_ptr5.all = v_phys_ptr2.all - 5 * 7 b1 + 1 b4) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_phys_ptr5.all > v_phys_ptr1.all) = true;
+    if ((v_phys_ptr5.all > v_phys_ptr1.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+
+    deallocate(v_phys_ptr1);
+    deallocate(v_phys_ptr2);
+    deallocate(v_phys_ptr4);
+
+    assert NOT(OKtest = 10) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00526" 
+      severity NOTE;
+    assert (OKtest = 10) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00526 - Physical type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00526arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc527.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc527.vhd
new file mode 100644
index 0000000..9dd0f8b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc527.vhd
@@ -0,0 +1,128 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc527.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00527ent IS
+END c03s03b00x00p03n04i00527ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00527arch OF c03s03b00x00p03n04i00527ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    -- first index constraint method
+    type bv_ptr is access bit_vector(0 to 7);
+    variable v_bv_ptr1: bv_ptr    := new bit_vector'("00000001");
+    variable v_bv_ptr2: bv_ptr;
+    variable v_bv_ptr3: bv_ptr    := v_bv_ptr1;
+    
+    
+    -- second index constraint method
+    subtype tbus is bit_vector(1 to 8);
+    type bus_ptr is access tbus;
+    variable v_bv_ptr4: bus_ptr    := new tbus'("10000000");
+    
+    
+    -- third index constraint method
+    type bus_ptr2 is access bit_vector;
+    variable v_bv_ptr5: bus_ptr2    := new bit_vector'("1111");
+    variable v_bv_ptr6: bus_ptr2    := new bit_vector(1 to 4);
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_bv_ptr1.all = "00000001";
+    if (v_bv_ptr1.all = "00000001") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bv_ptr2 = null;
+    if (v_bv_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bv_ptr3.all = "00000001";
+    if (v_bv_ptr3.all = "00000001") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bv_ptr4.all = "10000000";
+    if (v_bv_ptr4.all = "10000000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bv_ptr5.all = "1111";
+    if (v_bv_ptr5.all = "1111") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bv_ptr6.all = "0000";
+    if (v_bv_ptr6.all = "0000") then
+      OKtest := Oktest + 1;
+    end if;
+    
+    v_bv_ptr2 := new bit_vector'("00110011");
+    
+    assert v_bv_ptr2.all = "00110011";
+    if (v_bv_ptr6.all = "0000") then
+      OKtest := Oktest + 1;
+    end if;
+    
+    assert (v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001";
+    if ((v_bv_ptr1.all & v_bv_ptr3.all) = "0000000100000001") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011";
+    if ((v_bv_ptr1.all & v_bv_ptr2.all) = "0000000100110011") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bv_ptr5.all & v_bv_ptr6.all) = "11110000";
+    if ((v_bv_ptr5.all & v_bv_ptr6.all) = "11110000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001";
+    if ((v_bv_ptr5.all & v_bv_ptr1.all) = "111100000001") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bv_ptr6.all /= v_bv_ptr5.all) = true;
+    if ((v_bv_ptr6.all /= v_bv_ptr5.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    deallocate(v_bv_ptr1);
+    deallocate(v_bv_ptr2);
+    deallocate(v_bv_ptr4);
+    deallocate(v_bv_ptr5);
+    deallocate(v_bv_ptr6);
+
+    assert NOT(OKtest = 12) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00527" 
+      severity NOTE;
+    assert (OKtest = 12) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00527 - Bit Vector type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00527arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc528.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc528.vhd
new file mode 100644
index 0000000..1bb64fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc528.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc528.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00528ent IS
+END c03s03b00x00p03n04i00528ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00528arch OF c03s03b00x00p03n04i00528ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type char_ptr is access character;
+
+    variable v_char_ptr1: char_ptr := new character'('a');
+    variable v_char_ptr2: char_ptr;
+    variable v_char_ptr3: char_ptr := v_char_ptr1;
+    variable v_char_ptr4: char_ptr := new character'('|');
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_char_ptr1.all = 'a';
+    if (v_char_ptr1.all = 'a') then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_char_ptr2 = null;
+    if (v_char_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_char_ptr3.all = 'a';
+    if (v_char_ptr3.all = 'a') then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_char_ptr4.all = '|';
+    if (v_char_ptr4.all = '|') then
+      OKtest := Oktest + 1;
+    end if;
+
+    v_char_ptr2 := new character'('K');
+
+    assert v_char_ptr2.all = 'K';
+    if (v_char_ptr2.all = 'K') then
+      OKtest := Oktest + 1;
+    end if;
+
+    assert (v_char_ptr1.all & v_char_ptr3.all) = "aa";
+    if ((v_char_ptr1.all & v_char_ptr3.all) = "aa") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_char_ptr1.all & v_char_ptr2.all) = "aK";
+    if ((v_char_ptr1.all & v_char_ptr2.all) = "aK") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_char_ptr1.all & v_char_ptr4.all) = "a|";
+    if ((v_char_ptr1.all & v_char_ptr4.all) = "a|") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_char_ptr1.all /= v_char_ptr4.all) = true;
+    if ((v_char_ptr1.all /= v_char_ptr4.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+
+    deallocate(v_char_ptr1);
+    deallocate(v_char_ptr2);
+    deallocate(v_char_ptr4);
+
+    assert NOT(OKtest = 9) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00528" 
+      severity NOTE;
+    assert (OKtest = 9) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00528 - Character type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00528arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc529.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc529.vhd
new file mode 100644
index 0000000..e642312
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc529.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc529.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00529ent IS
+END c03s03b00x00p03n04i00529ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00529arch OF c03s03b00x00p03n04i00529ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type string_ptr is access string(1 to 8);
+
+    variable v_string_ptr1: string_ptr := new string'("abcd0123");
+    variable v_string_ptr2: string_ptr;
+    variable v_string_ptr3: string_ptr := v_string_ptr1;
+    variable v_string_ptr4: string_ptr := new string'("=>*/&^!)");
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_string_ptr1(1 to 8) = "abcd0123";
+    if (v_string_ptr1(1 to 8) = "abcd0123") then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_string_ptr2 = null;
+    if (v_string_ptr2 = null) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_string_ptr3(1 to 8) = "abcd0123";
+    if (v_string_ptr3(1 to 8) = "abcd0123") then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_string_ptr3(2 to 7) = "bcd012";
+    if (v_string_ptr3(2 to 7) = "bcd012") then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_string_ptr3(6) = '1';
+    if (v_string_ptr3(6) = '1') then
+      OKtest := OKtest + 1;
+    end if;
+
+    v_string_ptr2 := new string'("ABCD----");
+    
+    assert v_string_ptr2(6) = '-';
+    if (v_string_ptr3(6) = '1') then
+      OKtest := OKtest + 1;
+    end if;
+    
+    assert (v_string_ptr1(1 to 8) & v_string_ptr4(1 to 8)) = "abcd0123=>*/&^!)";        
+    if ((v_string_ptr1(1 to 8) & v_string_ptr4(1 to 8)) = "abcd0123=>*/&^!)") then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_string_ptr1(1 to 8) & v_string_ptr2(1 to 8)) = "abcd0123ABCD----";        
+    if ((v_string_ptr1(1 to 8) & v_string_ptr2(1 to 8)) = "abcd0123ABCD----") then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_string_ptr1(1 to 8) /= v_string_ptr4(1 to 8)) = true;
+    if ((v_string_ptr1(1 to 8) /= v_string_ptr4(1 to 8)) = true) then
+      OKtest := OKtest + 1;
+    end if;
+    assert (v_string_ptr1(1) /= v_string_ptr1(2)) = true;
+    if ((v_string_ptr1(1) /= v_string_ptr1(2)) = true) then
+      OKtest := OKtest + 1;
+    end if;
+    
+    deallocate(v_string_ptr1);
+    deallocate(v_string_ptr2);
+    deallocate(v_string_ptr4);
+
+    assert NOT(OKtest = 10) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00529" 
+      severity NOTE;
+    assert (OKtest = 10) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00529 - String type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00529arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc53.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc53.vhd
new file mode 100644
index 0000000..4d61dbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc53.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc53.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b01x01p04n03i00053pkg is
+  constant C1 : Bit ;
+  constant C2 : Integer ;
+end c04s03b01x01p04n03i00053pkg;
+
+package body c04s03b01x01p04n03i00053pkg is
+  constant C1 : Bit    := '1';
+  constant C2 : Integer    := 20;
+end c04s03b01x01p04n03i00053pkg;  -- Failure_here
+
+
+use work.c04s03b01x01p04n03i00053pkg.all;
+ENTITY c04s03b01x01p04n03i00053ent IS
+END c04s03b01x01p04n03i00053ent;
+
+ARCHITECTURE c04s03b01x01p04n03i00053arch OF c04s03b01x01p04n03i00053ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( C1 = '1' and C2 = 20 ) 
+      report "***PASSED TEST:c04s03b01x01p04n03i00053" 
+      severity NOTE;
+    assert ( C1 = '1' and C2 = 20 ) 
+      report "***FAILED TEST: c04s03b01x01p04n03i00053 - Full constant declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p04n03i00053arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc530.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc530.vhd
new file mode 100644
index 0000000..f6afe5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc530.vhd
@@ -0,0 +1,307 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc530.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00530ent IS
+END c03s03b00x00p03n04i00530ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00530arch OF c03s03b00x00p03n04i00530ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type small is
+      record
+        bt : bit;
+        bv : bit_vector (11 downto 0);
+        r  : real range 0.0 to real'high;
+        bb : boolean;
+        i  : integer range 1 to 20;
+      end record;
+    type color    is (red, green, blue);
+    type two_d    is array (color, 1 to 3) of bit;
+    type smar    is array (1 to 3) of small;
+    
+    type record_ptr is access small;
+    type smar_ptr    is access smar;
+    type two_d_ptr    is access two_d;
+
+    variable v_record_ptr1: record_ptr := new small'(bt => '1',
+                                                     bv => "010101010101",
+                                                     r  => 0.1234,
+                                                     bb => true,
+                                                     i  => 20);
+    variable v_record_ptr2: record_ptr;
+    variable v_record_ptr3: record_ptr := v_record_ptr1;
+    variable v_record_ptr4: record_ptr := new small'(bt => '0',
+                                                     bv => "010101010101",
+                                                     r  => 0.9999,
+                                                     bb => false,
+                                                     i  => 1);
+    
+    variable v_smar_ptr1: smar_ptr := new smar'(others => (bt => '1',
+                                                           bv => "010101010101",
+                                                           r  => 0.1234,
+                                                           bb => true,
+                                                           i  => 20));
+    variable v_smar_ptr2: smar_ptr;
+    variable v_smar_ptr3: smar_ptr := v_smar_ptr1;
+    variable v_smar_ptr4: smar_ptr := new smar'(1 => (bt => '1',
+                                                      bv => "010101010101",
+                                                      r  => 0.1234,
+                                                      bb => true,
+                                                      i  => 20),
+                                                others => (bt => '0',
+                                                           bv => "010101010101",
+                                                           r  => 0.9999,
+                                                           bb => false,
+                                                           i  => 1));
+    
+    variable v_two_d_ptr1: two_d_ptr := new two_d'(others => (others => '1'));
+    variable v_two_d_ptr2: two_d_ptr;
+    variable v_two_d_ptr3: two_d_ptr := v_two_d_ptr1;
+    variable v_two_d_ptr4: two_d_ptr := new two_d'(red   => "111",
+                                                   green => "000",
+                                                   blue  => "101");
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+
+    assert v_record_ptr1.bt = '1';
+    if (v_record_ptr1.bt = '1') then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_record_ptr1.bv = "010101010101";
+    if (v_record_ptr1.bv = "010101010101") then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_record_ptr1.r = 0.1234;
+    if (v_record_ptr1.r = 0.1234) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_record_ptr1.bb = true;
+    if (v_record_ptr1.bb = true) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_record_ptr1.i = 20;
+    if (v_record_ptr1.i = 20) then
+      OKtest := OKtest + 1;
+    end if;
+    assert v_record_ptr2 = null;
+    if (v_record_ptr2 = null) then
+      OKtest := OKtest + 1;
+    end if;
+    
+    v_record_ptr2 := new small'(bt => '0',
+                                bv => "010101010101",
+                                r  => 0.1234,
+                                bb => true,
+                                i  => 10);
+    
+    assert v_record_ptr2.bt = '0';
+    if (v_record_ptr2.bt = '0') then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr2.bv = "010101010101";
+    if (v_record_ptr2.bv = "010101010101") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr2.r = 0.1234;
+    if (v_record_ptr2.r = 0.1234) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr2.bb = true;
+    if (v_record_ptr2.bb = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr2.i = 10;
+    if (v_record_ptr2.i = 10) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr2 /= null;
+    if (v_record_ptr2 /= null) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    assert v_record_ptr1.all = v_record_ptr3.all;
+    if (v_record_ptr1.all = v_record_ptr3.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_record_ptr1.all /= v_record_ptr4.all;
+    if (v_record_ptr1.all /= v_record_ptr4.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_record_ptr1.bt & v_record_ptr4.bt) = "10";
+    if ((v_record_ptr1.bt & v_record_ptr4.bt) = "10") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_record_ptr1.i - v_record_ptr4.i) = 19;
+    if ((v_record_ptr1.i - v_record_ptr4.i) = 19) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    deallocate(v_record_ptr1);
+    deallocate(v_record_ptr2);
+    deallocate(v_record_ptr4);
+    
+    assert v_smar_ptr1(1).bt = '1';
+    if (v_smar_ptr1(1).bt = '1') then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1).bv = "010101010101";
+    if (v_smar_ptr1(1).bv = "010101010101") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1).r = 0.1234;
+    if (v_smar_ptr1(1).r = 0.1234) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1).bb = true;
+    if (v_smar_ptr1(1).bb = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1).i = 20;
+    if (v_smar_ptr1(1).i = 20) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2 = null;
+    if (v_smar_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    v_smar_ptr2 := new smar'(others => (bt => '1',
+                                        bv => "010101010101",
+                                        r  => 0.1234,
+                                        bb => true,
+                                        i  => 10));
+    
+    assert v_smar_ptr2(1).bt = '1';
+    if (v_smar_ptr2(1).bt = '1') then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2(1).bv = "010101010101";
+    if (v_smar_ptr2(1).bv = "010101010101") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2(1).r = 0.1234;
+    if (v_smar_ptr2(1).r = 0.1234) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2(1).bb = true;
+    if (v_smar_ptr2(1).bb = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2(1).i = 10;
+    if (v_smar_ptr2(1).i = 10) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr2 /= null;
+    if (v_smar_ptr2 /= null) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    assert v_smar_ptr1.all = v_smar_ptr3.all;
+    if (v_smar_ptr1.all = v_smar_ptr3.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1) /= v_smar_ptr4(2);
+    if (v_smar_ptr1(1) /= v_smar_ptr4(2)) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_smar_ptr1(1) = v_smar_ptr4(1);
+    if (v_smar_ptr1(1) = v_smar_ptr4(1)) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_smar_ptr1(1).bt & v_smar_ptr4(1).bt) = "11";
+    if ((v_smar_ptr1(1).bt & v_smar_ptr4(1).bt) = "11") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_smar_ptr1(1).i - v_smar_ptr4(1).i) = 0;
+    if ((v_smar_ptr1(1).i - v_smar_ptr4(1).i) = 0) then
+      OKtest := Oktest + 1;
+    end if;
+
+    deallocate(v_smar_ptr1);
+    deallocate(v_smar_ptr2);
+    deallocate(v_smar_ptr4);
+    
+    assert v_two_d_ptr1.all = v_two_d_ptr3.all;
+    if (v_two_d_ptr1.all = v_two_d_ptr3.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_two_d_ptr1.all /= v_two_d_ptr4.all;
+    if (v_two_d_ptr1.all /= v_two_d_ptr4.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_two_d_ptr2 = null;
+    if (v_two_d_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_two_d_ptr3(blue, 2) = '1';
+    if (v_two_d_ptr3(blue, 2) = '1') then
+      OKtest := Oktest + 1;
+    end if;
+    
+    v_two_d_ptr2 := new two_d'(red   => "111",
+                               green => "000",
+                               blue  => "101");
+    
+    assert v_two_d_ptr2.all = v_two_d_ptr4.all;
+    if (v_two_d_ptr2.all = v_two_d_ptr4.all) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_two_d_ptr2 /= null;
+    if (v_two_d_ptr2 /= null) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    assert (v_two_d_ptr1(red, 1) & v_two_d_ptr4(blue, 2)) = "10";
+    if ((v_two_d_ptr1(red, 1) & v_two_d_ptr4(blue, 2)) = "10") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_two_d_ptr1(red, 1) /= v_two_d_ptr4(blue,2));
+    if ((v_two_d_ptr1(red, 1) /= v_two_d_ptr4(blue,2))) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    deallocate(v_two_d_ptr1);
+    deallocate(v_two_d_ptr2);
+    deallocate(v_two_d_ptr4);
+
+    assert NOT(OKtest = 41) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00530" 
+      severity NOTE;
+    assert (OKtest = 41) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00530 - Composite type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00530arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc531.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc531.vhd
new file mode 100644
index 0000000..77d7a61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc531.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc531.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n04i00531ent IS
+END c03s03b00x00p03n04i00531ent;
+
+ARCHITECTURE c03s03b00x00p03n04i00531arch OF c03s03b00x00p03n04i00531ent IS
+
+BEGIN
+  TESTING : PROCESS
+
+    type bool_ptr is access boolean;
+    variable v_bool_ptr1: bool_ptr := new boolean'(true);
+    variable v_bool_ptr2: bool_ptr;
+    variable v_bool_ptr3: bool_ptr := v_bool_ptr1;
+    variable v_bool_ptr4: bool_ptr := new boolean'(false);
+    variable v_bool_ptr5: bool_ptr := v_bool_ptr4;
+
+    variable OKtest : integer := 0;
+
+  BEGIN
+    assert v_bool_ptr1.all = true;
+    if (v_bool_ptr1.all = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bool_ptr2 = null;
+    if (v_bool_ptr2 = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bool_ptr3.all = true;
+    if (v_bool_ptr3.all = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bool_ptr4.all = false;
+    if (v_bool_ptr4.all = false) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_bool_ptr5.all = false;
+    if (v_bool_ptr5.all = false) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    v_bool_ptr2 := new boolean'(true);
+    
+    assert v_bool_ptr2.all = true;
+    if (v_bool_ptr2.all = true) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    assert (v_bool_ptr1.all and v_bool_ptr5.all) = false;
+    if ((v_bool_ptr1.all and v_bool_ptr5.all) = false) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bool_ptr1.all and v_bool_ptr2.all) = true;
+    if ((v_bool_ptr1.all and v_bool_ptr2.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bool_ptr3.all or v_bool_ptr5.all) = true;
+    if ((v_bool_ptr3.all or v_bool_ptr5.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_bool_ptr3.all > v_bool_ptr5.all) = true;
+    if ((v_bool_ptr3.all > v_bool_ptr5.all) = true) then
+      OKtest := Oktest + 1;
+    end if;
+    assert (not v_bool_ptr3.all) = false;
+    if ((not v_bool_ptr3.all) = false) then
+      OKtest := Oktest + 1;
+    end if;
+    
+    deallocate(v_bool_ptr1);
+    deallocate(v_bool_ptr2);
+    deallocate(v_bool_ptr4);
+
+    assert NOT(OKtest = 11) 
+      report "***PASSED TEST: c03s03b00x00p03n04i00531" 
+      severity NOTE;
+    assert (OKtest = 11) 
+      report "***FAILED TEST: c03s03b00x00p03n04i00531 - Boolean type using as base for access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n04i00531arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc534.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc534.vhd
new file mode 100644
index 0000000..126f325
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc534.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc534.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p04n02i00534ent IS
+END c03s03b00x00p04n02i00534ent;
+
+ARCHITECTURE c03s03b00x00p04n02i00534arch OF c03s03b00x00p04n02i00534ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- The access type we will use.
+    type ACT  is access BIT;
+
+    -- Declare a variable of this type.  Initialize it.
+    variable VAR : ACT := NEW BIT'( '0' );
+  BEGIN
+    -- Attempt to assign a value to it.
+    VAR.all := '1';
+    assert NOT( VAR.all = '1' )
+      report "***PASSED TEST: c03s03b00x00p04n02i00534"
+      severity NOTE;
+    assert ( VAR.all = '1' )
+      report "***FAILED TEST: c03s03b00x00p04n02i00534 - Object designated by an access value is always an object of class variable test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p04n02i00534arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc535.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc535.vhd
new file mode 100644
index 0000000..d310731
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc535.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc535.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p05n01i00535ent IS
+END c03s03b00x00p05n01i00535ent;
+
+ARCHITECTURE c03s03b00x00p05n01i00535arch OF c03s03b00x00p05n01i00535ent IS
+  type b is access BIT_VECTOR(0 to 10);   -- Success_here
+BEGIN
+  TESTING: PROCESS
+    variable k : b; 
+  BEGIN
+    assert NOT(k=null)
+      report "***PASSED TEST: c03s03b00x00p05n01i00535"
+      severity NOTE;
+    assert ( k=null )
+      report "***FAILED TEST: c03s03b00x00p05n01i00535 - The only form of constraint that is allowed after the name of an access type in a subtype indication is an index constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p05n01i00535arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc537.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc537.vhd
new file mode 100644
index 0000000..696aa53
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc537.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc537.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p05n02i00537ent IS
+END c03s03b00x00p05n02i00537ent;
+
+ARCHITECTURE c03s03b00x00p05n02i00537arch OF c03s03b00x00p05n02i00537ent IS
+  type ARR is access BIT_VECTOR ;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : ARR := null ;
+    variable V2 : ARR(0 to 3) := new BIT_VECTOR'("1111") ; -- no_failure_here
+  BEGIN
+    V1 := V2;
+    assert NOT(V1(0 to 3)="1111")
+      report "***PASSED TEST: c03s03b00x00p05n02i00537"
+      severity NOTE;
+    assert (V1(0 to 3)="1111")
+      report "***FAILED TEST: c03s03b00x00p05n02i00537 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p05n02i00537arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc538.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc538.vhd
new file mode 100644
index 0000000..38da705
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc538.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc538.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p05n02i00538ent IS
+END c03s03b00x00p05n02i00538ent;
+
+ARCHITECTURE c03s03b00x00p05n02i00538arch OF c03s03b00x00p05n02i00538ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype byte is bit_vector (7 downto 0);
+    type byte_mem is array (0 to 15) of byte;
+
+    type ar_bv_ptr is access byte_mem;
+    variable v_ar_bv_ptr1: ar_bv_ptr := new byte_mem'(0 => "10000000",
+                                                      1 => "00000001",
+                                                      others => "00000000");
+    variable v_ar_bv_ptr2: ar_bv_ptr;
+    variable v_ar_bv_ptr3: ar_bv_ptr := v_ar_bv_ptr1;
+    variable   OKtest : integer := 0;
+  BEGIN
+    assert v_ar_bv_ptr1(1)    = "00000001";
+    if (v_ar_bv_ptr1(1)  = "00000001") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_ar_bv_ptr2    = null;
+    if (v_ar_bv_ptr2     = null) then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_ar_bv_ptr3(0)    = "10000000";
+    if (v_ar_bv_ptr3(0)  = "10000000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_ar_bv_ptr3(15) = "00000000";
+    if (v_ar_bv_ptr3(15) = "00000000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert v_ar_bv_ptr3(1)(0)    = '1';        -- (7 downto 0)
+    if (v_ar_bv_ptr3(1)(0)       = '1') then
+      OKtest := Oktest + 1;
+    end if;
+
+    v_ar_bv_ptr2 := new byte_mem'(0 => "10000000",
+                                  1 => "00000001",
+                                  others => "00000000");
+
+    assert v_ar_bv_ptr2(0)(7) = '1';        -- (7 downto 0)
+    if (v_ar_bv_ptr2(0)(7) = '1') then
+      OKtest := Oktest + 1;
+    end if;
+
+    assert (v_ar_bv_ptr1(1) & v_ar_bv_ptr3(7)) = "0000000100000000";
+    if ((v_ar_bv_ptr1(1) & v_ar_bv_ptr3(7)) = "0000000100000000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_ar_bv_ptr3(1) & v_ar_bv_ptr2(0)) = "0000000110000000";
+    if ((v_ar_bv_ptr3(1) & v_ar_bv_ptr2(0)) = "0000000110000000") then
+      OKtest := Oktest + 1;
+    end if;
+    assert (v_ar_bv_ptr1(1) /= v_ar_bv_ptr3(0)) = true;
+    if ((v_ar_bv_ptr1(1) /= v_ar_bv_ptr3(0)) = true) then
+      OKtest := Oktest + 1;
+    end if;
+
+    assert NOT(OKtest = 9)
+      report "***PASSED TEST: c03s03b00x00p05n02i00538" 
+      severity NOTE;
+    assert (OKtest = 9)
+      report "***FAILED TEST: c03s03b00x00p05n02i00538 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p05n02i00538arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc539.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc539.vhd
new file mode 100644
index 0000000..b90a4c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc539.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc539.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b01x00p01n02i00539ent IS
+END c03s03b01x00p01n02i00539ent;
+
+ARCHITECTURE c03s03b01x00p01n02i00539arch OF c03s03b01x00p01n02i00539ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type a;
+    type a is access a;
+
+    variable k : a;
+  BEGIN
+    assert NOT( k=null )
+      report "***PASSED TEST: c03s03b01x00p01n02i00539"
+      severity NOTE;
+    assert ( k=null)
+      report "***FAILED TEST: c03s03b01x00p01n02i00539 - The type of an element of the designated type can be another access type, or even the same access type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b01x00p01n02i00539arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc54.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc54.vhd
new file mode 100644
index 0000000..66639b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc54.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc54.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b01x01p04n01i00054pkg is
+  constant DC : STRING;               -- unconstrainted deferred constant
+end c04s03b01x01p04n01i00054pkg;
+
+package body c04s03b01x01p04n01i00054pkg is
+  constant DC : STRING := "Hello";    -- constant completion
+end c04s03b01x01p04n01i00054pkg;
+
+
+use work.c04s03b01x01p04n01i00054pkg.all;
+ENTITY c04s03b01x01p04n01i00054ent IS
+END c04s03b01x01p04n01i00054ent;
+
+ARCHITECTURE c04s03b01x01p04n01i00054arch OF c04s03b01x01p04n01i00054ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( DC'LENGTH = 5 and DC(1) = 'H' and DC(5) = 'o' )
+      report "***PASSED TEST:c04s03b01x01p04n01i00054"
+      severity NOTE;
+    assert ( DC'LENGTH = 5 and DC(1) = 'H' and DC(5) = 'o' )
+      report "***FAILED TEST:c04s03b01x01p04n01i00054 - A deferred constant declaration appear in a package declaration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p04n01i00054arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc541.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc541.vhd
new file mode 100644
index 0000000..2db7fda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc541.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc541.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b02x00p06n01i00541ent IS
+END c03s03b02x00p06n01i00541ent;
+
+ARCHITECTURE c03s03b02x00p06n01i00541arch OF c03s03b02x00p06n01i00541ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    type    AC1 is access SWITCH_LEVEL;
+
+    -- Declare a variable.
+    variable VAR : AC1;
+  BEGIN
+    -- Perform the test.
+    assert( VAR = NULL );
+    DEALLOCATE( VAR );
+    assert NOT( VAR = NULL )
+      report "***PASSED TEST: c03s03b02x00p06n01i00541"
+      severity NOTE;
+    assert ( VAR = NULL )
+      report "***FAILED TEST: c03s03b02x00p06n01i00541 - DEALLOCATE operation test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b02x00p06n01i00541arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc542.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc542.vhd
new file mode 100644
index 0000000..eb780e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc542.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc542.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b02x00p06n01i00542ent IS
+END c03s03b02x00p06n01i00542ent;
+
+ARCHITECTURE c03s03b02x00p06n01i00542arch OF c03s03b02x00p06n01i00542ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type int_ptr is access integer;
+    variable var1: int_ptr := new integer;
+  BEGIN
+    var1:= null;
+    Deallocate(var1);
+    assert NOT(var1 = null) 
+      report "***PASSED TEST: c03s03b02x00p06n01i00542"
+      severity NOTE;
+    assert (var1 = null) 
+      report "***FAILED TEST: c03s03b02x00p06n01i00542 - DEALLOCATE operation test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b02x00p06n01i00542arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc544.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc544.vhd
new file mode 100644
index 0000000..96519ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc544.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc544.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n01i00544ent IS
+END c03s04b00x00p03n01i00544ent;
+
+ARCHITECTURE c03s04b00x00p03n01i00544arch OF c03s04b00x00p03n01i00544ent IS
+  type L is                           -- constrained array decl
+    array (1 to 1023, 31 downto 0) of Bit;
+
+  type M is                           -- record type decl
+    record
+      A: Integer;
+      B: L;
+    end record;
+
+  type O is                           -- file decl
+    file of M;  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c03s04b00x00p03n01i00544"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n01i00544arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc545.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc545.vhd
new file mode 100644
index 0000000..871982b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc545.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc545.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n01i00545ent IS
+END c03s04b00x00p03n01i00545ent;
+
+ARCHITECTURE c03s04b00x00p03n01i00545arch OF c03s04b00x00p03n01i00545ent IS
+  type TM is                             -- unconstrained array decl
+    array (Integer range <>) of Integer;     -- No_failure_here
+
+  type FT is                             -- file decl
+    file of TM;                              -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c03s04b00x00p03n01i00545"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n01i00545arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc546.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc546.vhd
new file mode 100644
index 0000000..4d08111
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc546.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc546.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n01i00546ent IS
+END c03s04b00x00p03n01i00546ent;
+
+ARCHITECTURE c03s04b00x00p03n01i00546arch OF c03s04b00x00p03n01i00546ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    type    FT1 is file of SWITCH_LEVEL;
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    type    FT2 is file of SWITCH_LEVEL;
+
+    -- array types.  Unconstrained.
+    type MEMORY is array(INTEGER range <>) of BIT;
+    type    FT3 is file of MEMORY;
+
+    -- array types.  Constrained.
+    type WORD   is array(0 to 31) of BIT;
+    type    FT4 is file of WORD;
+
+    -- record types.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    type FT5 is file of DATE;
+    
+    -- INTEGER types.
+    type FT6 is file of INTEGER;
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    type FT7 is file of POSITIVE;
+    
+    -- Physical types.
+    type FT8 is file of TIME;
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+    type FT10 is file of DISTANCE;
+    
+    -- floating point types.
+    type FT11 is file of REAL;
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    type FT12 is file of POSITIVE_R;
+
+    -- Predefined enumerated types.
+    type FT13 is file of BIT;
+    type FT14 is file of SEVERITY_LEVEL;
+    type FT15 is file of BOOLEAN;
+    type FT16 is file of CHARACTER;
+    
+    -- Other predefined types.
+    type FT17 is file of NATURAL;
+    type FT18 is file of STRING;
+    type FT19 is file of BIT_VECTOR;
+
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c03s04b00x00p03n01i00546"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n01i00546arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc554.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc554.vhd
new file mode 100644
index 0000000..6df12c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc554.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc554.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:28 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:25 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00554ent IS
+END c03s04b01x00p01n01i00554ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00554arch OF c03s04b01x00p01n01i00554ent IS
+  type boolean_file is file of boolean;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_file open read_mode is "iofile.10";
+    variable  v : boolean;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= true) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00554"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00554 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00554arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc555.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc555.vhd
new file mode 100644
index 0000000..ebe086c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc555.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc555.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:28 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:25 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00555ent IS
+END c03s04b01x00p01n01i00555ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00555arch OF c03s04b01x00p01n01i00555ent IS
+  type boolean_file is file of boolean;
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_file open write_mode is "iofile.10";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,true);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00555 - The output file will be verified by test s010202.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00555arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc556.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc556.vhd
new file mode 100644
index 0000000..f18ef73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc556.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc556.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:29 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:26 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00556ent IS
+END c03s04b01x00p01n01i00556ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00556arch OF c03s04b01x00p01n01i00556ent IS
+  type natural_vector  is array (natural range <>) of natural;
+  type natural_vector_file is file of natural_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_vector_file open write_mode is "iofile.25";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(1,2,3,4));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00556 - The output file will be verified by test s010234.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00556arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc557.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc557.vhd
new file mode 100644
index 0000000..04f9146
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc557.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc557.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:29 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:26 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00557ent IS
+END c03s04b01x00p01n01i00557ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00557arch OF c03s04b01x00p01n01i00557ent IS
+  type bit_file is file of bit;
+BEGIN
+  TESTING: PROCESS
+    file filein : bit_file open write_mode is "iofile.08";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,'1');
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00557 - The output file will be verified by test s010204.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00557arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc558.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc558.vhd
new file mode 100644
index 0000000..2c85c1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc558.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc558.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:30 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:27 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00558ent IS
+END c03s04b01x00p01n01i00558ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00558arch OF c03s04b01x00p01n01i00558ent IS
+  type bit_file is file of bit;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : bit_file open read_mode is "iofile.08";
+    variable  v : bit;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= '1') then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00558"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00558 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00558arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc559.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc559.vhd
new file mode 100644
index 0000000..a3b2076
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc559.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc559.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:30 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:27 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00559ent IS
+END c03s04b01x00p01n01i00559ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00559arch OF c03s04b01x00p01n01i00559ent IS
+  type natural_vector      is array (natural range <>) of natural;
+  type natural_vector_file is file of natural_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : natural_vector_file open read_mode is "iofile.25";
+    variable  v    : natural_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= (1,2,3,4)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00559"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00559 - File reading operation (natural_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00559arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc56.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc56.vhd
new file mode 100644
index 0000000..b76d638
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc56.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc56.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p05n01i00056ent IS
+END c04s03b01x01p05n01i00056ent;
+
+ARCHITECTURE c04s03b01x01p05n01i00056arch OF c04s03b01x01p05n01i00056ent IS
+  procedure PRO (constant C1 : in BIT := '1') is  --- No_failure_here
+  begin
+    assert NOT( C1= '1' )
+      report "***PASSED TEST:c04s03b01x01p05n01i00056"
+      severity NOTE;
+    assert ( C1= '1' )
+      report "***FAILED TEST: c04s03b01x01p05n01i00056 - The formal parameters of subprogram are of mode in may be constant."
+      severity ERROR;
+  end;
+BEGIN
+  PRO;
+END c04s03b01x01p05n01i00056arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc560.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc560.vhd
new file mode 100644
index 0000000..d2eaa84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc560.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc560.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:31 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:27 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00560ent IS
+END c03s04b01x00p01n01i00560ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00560arch OF c03s04b01x00p01n01i00560ent IS
+  type character_file is file of character;
+BEGIN
+  TESTING: PROCESS
+    file filein : character_file open write_mode is "iofile.16";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,'s');
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00560 - The output file will be verified by test s010206.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00560arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc561.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc561.vhd
new file mode 100644
index 0000000..41284d7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc561.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc561.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:31 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:28 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00561ent IS
+END c03s04b01x00p01n01i00561ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00561arch OF c03s04b01x00p01n01i00561ent IS
+  type character_file is file of character;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : character_file open read_mode is "iofile.16";
+    variable  v : character;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= 's') then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00561"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00561 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00561arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc562.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc562.vhd
new file mode 100644
index 0000000..1ff7ae4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc562.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc562.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:31 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:28 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:04 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00562ent IS
+END c03s04b01x00p01n01i00562ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00562arch OF c03s04b01x00p01n01i00562ent IS
+  type integer_cons_vector  is array (15 downto 0) of integer;
+  type integer_cons_vector_file is file of integer_cons_vector;
+  constant C19 : integer_cons_vector := (others => 3);
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_cons_vector_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00562 - The output file will be verified by test s010242.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00562arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc563.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc563.vhd
new file mode 100644
index 0000000..2f1acc8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc563.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc563.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:32 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:29 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:04 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00563ent IS
+END c03s04b01x00p01n01i00563ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00563arch OF c03s04b01x00p01n01i00563ent IS
+  type severity_level_file is file of severity_level;
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_file open write_mode is "iofile.17";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,note);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00563 - The output file will be verified by test s010208.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00563arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc564.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc564.vhd
new file mode 100644
index 0000000..2c7693c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc564.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc564.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:32 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:29 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:04 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00564ent IS
+END c03s04b01x00p01n01i00564ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00564arch OF c03s04b01x00p01n01i00564ent IS
+  type severity_level_file is file of severity_level;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_file open read_mode is "iofile.17";
+    variable  v : severity_level;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= note) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00564"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00564 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00564arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc565.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc565.vhd
new file mode 100644
index 0000000..ace2c51
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc565.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc565.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:32 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:30 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:04 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00565ent IS
+END c03s04b01x00p01n01i00565ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00565arch OF c03s04b01x00p01n01i00565ent IS
+  type positive_vector  is array (positive range <>) of positive;
+  type positive_vector_file is file of positive_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_vector_file open write_mode is "iofile.25";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(1,2,3,4));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00565 - The output file will be verified by test s010236.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00565arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc566.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc566.vhd
new file mode 100644
index 0000000..a5eec4e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc566.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc566.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:33 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:30 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00566ent IS
+END c03s04b01x00p01n01i00566ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00566arch OF c03s04b01x00p01n01i00566ent IS
+  type integer_file is file of integer;
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_file open write_mode is "iofile.18";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,3);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00566 - The output file will be verified by test s010210.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00566arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc567.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc567.vhd
new file mode 100644
index 0000000..e7e300b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc567.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc567.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:33 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:30 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00567ent IS
+END c03s04b01x00p01n01i00567ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00567arch OF c03s04b01x00p01n01i00567ent IS
+  type integer_file is file of integer;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_file open read_mode is "iofile.18";
+    variable  v : integer;
+  BEGIN
+    for i in 1 to 100 loop
+      assert (endfile(filein) = false) 
+        report"end of file reached before expected"
+        severity error;
+      read(filein,v);
+      if (v /= 3) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 50 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00567"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00567 - Implicitly declared procedure READ test failed. It may cause by procedure WRITE failed also."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00567arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc568.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc568.vhd
new file mode 100644
index 0000000..7ed7af4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc568.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc568.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:33 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:31 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00568ent IS
+END c03s04b01x00p01n01i00568ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00568arch OF c03s04b01x00p01n01i00568ent IS
+  type positive_vector      is array (natural range <>) of positive;
+  type positive_vector_file is file of positive_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : positive_vector_file open read_mode is "iofile.25";
+    variable  v    : positive_vector(0 to 3);
+    variable  len   : positive;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= (1,2,3,4)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00568"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00568 - File reading operation (positive_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00568arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc569.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc569.vhd
new file mode 100644
index 0000000..fd9c5ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc569.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc569.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:33 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:31 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00569ent IS
+END c03s04b01x00p01n01i00569ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00569arch OF c03s04b01x00p01n01i00569ent IS
+  type real_file is file of real;
+BEGIN
+  TESTING: PROCESS
+    file filein : real_file open write_mode is "iofile.19";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,3.0);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00569 - The output file will be verified by test s010212.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00569arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc570.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc570.vhd
new file mode 100644
index 0000000..d1af4cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc570.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc570.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:34 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:32 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00570ent IS
+END c03s04b01x00p01n01i00570ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00570arch OF c03s04b01x00p01n01i00570ent IS
+  type real_file is file of real;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : real_file open read_mode is "iofile.19";
+    variable  v : real;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= 3.0) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00570"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00570 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00570arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc571.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc571.vhd
new file mode 100644
index 0000000..65e1454
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc571.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc571.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:34 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:32 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00571ent IS
+END c03s04b01x00p01n01i00571ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00571arch OF c03s04b01x00p01n01i00571ent IS
+  type integer_cons_vector      is array (15 downto 0) of integer;
+  type integer_cons_vector_file is file of integer_cons_vector;
+  constant C19 : integer_cons_vector := (others => 3);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : integer_cons_vector_file open read_mode is "iofile.30";
+    variable  v    : integer_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00571"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00571 - File reading operation (integer_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00571arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc572.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc572.vhd
new file mode 100644
index 0000000..0346705
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc572.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc572.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:34 1996  --
+--                 ****************************               --
+
+
+--major mess!
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:33 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00572ent IS
+END c03s04b01x00p01n01i00572ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00572arch OF c03s04b01x00p01n01i00572ent IS
+  type time_file is file of time;
+BEGIN
+  TESTING: PROCESS
+    file filein : time_file open write_mode is "iofile.20";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,3 ns);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: ENTITY c03s04b01x00p01n01i00572"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+  
+
+
+end c03s04b01x00p01n01i00572arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc573.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc573.vhd
new file mode 100644
index 0000000..8546c76
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc573.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc573.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:34 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:33 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00573ent IS
+END c03s04b01x00p01n01i00573ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00573arch OF c03s04b01x00p01n01i00573ent IS
+  type time_file is file of time;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : time_file open read_mode is "iofile.20";
+    variable  v : time;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= 3 ns) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00573"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00573 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00573arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc574.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc574.vhd
new file mode 100644
index 0000000..eedfb34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc574.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc574.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:34 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:34 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:07 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00574ent IS
+END c03s04b01x00p01n01i00574ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00574arch OF c03s04b01x00p01n01i00574ent IS
+  type boolean_cons_vector  is array (15 downto 0) of boolean;
+  type boolean_cons_vector_file is file of boolean_cons_vector;
+  constant C19 : boolean_cons_vector := (others => true);
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_cons_vector_file open write_mode is "iofile.28";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00574 - The output file will be verified by test s010238.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00574arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc575.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc575.vhd
new file mode 100644
index 0000000..f674ff2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc575.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc575.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:35 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:34 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:07 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00575ent IS
+END c03s04b01x00p01n01i00575ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00575arch OF c03s04b01x00p01n01i00575ent IS
+  type natural_file is file of natural;
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_file open write_mode is "iofile.18";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,3);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00575 - The output file will be verified by test s010216.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00575arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc576.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc576.vhd
new file mode 100644
index 0000000..1c9c6a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc576.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc576.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:35 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:35 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:07 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00576ent IS
+END c03s04b01x00p01n01i00576ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00576arch OF c03s04b01x00p01n01i00576ent IS
+  type natural_file is file of natural;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_file open read_mode is "iofile.18";
+    variable  v : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= 3 ) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00576"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00576 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00576arch;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc577.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc577.vhd
new file mode 100644
index 0000000..40059c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc577.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc577.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:35 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:48 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:12 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00577ent IS
+END c03s04b01x00p01n01i00577ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00577arch OF c03s04b01x00p01n01i00577ent IS
+  type boolean_cons_vector      is array (15 downto 0) of boolean;
+  type boolean_cons_vector_file is file of boolean_cons_vector;
+  constant C19 : boolean_cons_vector := (others => true);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : boolean_cons_vector_file open read_mode is "iofile.28";
+    variable  v    : boolean_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00577"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00577 - File reading operation (boolean_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00577arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc578.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc578.vhd
new file mode 100644
index 0000000..c78b5cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc578.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc578.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:35 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:49 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:13 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00578ent IS
+END c03s04b01x00p01n01i00578ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00578arch OF c03s04b01x00p01n01i00578ent IS
+  type positive_file is file of positive;
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_file open write_mode is "iofile.18";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,3);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00578 - The output file will be verified by test s010218.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00578arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc579.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc579.vhd
new file mode 100644
index 0000000..3dd7799
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc579.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc579.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:36 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:49 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:13 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00579ent IS
+END c03s04b01x00p01n01i00579ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00579arch OF c03s04b01x00p01n01i00579ent IS
+  type positive_file is file of positive;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_file open read_mode is "iofile.18";
+    variable  v : positive;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= 3 ) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00579"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00579 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00579arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc580.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc580.vhd
new file mode 100644
index 0000000..08ae432
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc580.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc580.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:36 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00580ent IS
+END c03s04b01x00p01n01i00580ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00580arch OF c03s04b01x00p01n01i00580ent IS
+  constant C1 : boolean    := true;
+  type boolean_vector       is array (natural range <>) of boolean;
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  type boolean_vector_st_file    is file of boolean_vector_st;
+  constant C27 : boolean_vector_st := (others => C1);
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_vector_st_file open write_mode is "iofile.28";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00580 - The output file will be verified by test s010256.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00580arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc581.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc581.vhd
new file mode 100644
index 0000000..8a93ecf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc581.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc581.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:36 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00581ent IS
+END c03s04b01x00p01n01i00581ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00581arch OF c03s04b01x00p01n01i00581ent IS
+  type string_file is file of string;
+BEGIN
+  TESTING: PROCESS
+    file filein : string_file open write_mode is "iofile.21";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,"shishir");
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00581 - The output file will be verified by test s010220.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00581arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc582.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc582.vhd
new file mode 100644
index 0000000..2242c7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc582.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc582.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:36 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:50 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:14 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00582ent IS
+END c03s04b01x00p01n01i00582ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00582arch OF c03s04b01x00p01n01i00582ent IS
+  type string_file is file of string;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : string_file open read_mode is "iofile.21";
+    variable  v    : string(1 to 7);
+    variable  len    : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 7) report "wrong length passed during read operation";
+      if (v /= "shishir" or len /= 7) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00582"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00582 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00582arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc583.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc583.vhd
new file mode 100644
index 0000000..a9f3e73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc583.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc583.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:37 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00583ent IS
+END c03s04b01x00p01n01i00583ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00583arch OF c03s04b01x00p01n01i00583ent IS
+  type severity_level_cons_vector  is array (15 downto 0) of severity_level;
+  type severity_level_cons_vector_file is file of severity_level_cons_vector;
+  constant C19 : severity_level_cons_vector := (others => note);
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_cons_vector_file open write_mode is "iofile.29";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00583 - The output file will be verified by test s010240.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00583arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc584.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc584.vhd
new file mode 100644
index 0000000..278c124
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc584.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc584.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:37 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:51 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:14 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00584ent IS
+END c03s04b01x00p01n01i00584ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00584arch OF c03s04b01x00p01n01i00584ent IS
+  type bit_vector_file is file of bit_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : bit_vector_file open write_mode is "iofile.22";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,B"0011");
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00584 - The output file will be verified by test s010222.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00584arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc585.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc585.vhd
new file mode 100644
index 0000000..5355724
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc585.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc585.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:37 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:51 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:14 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00585ent IS
+END c03s04b01x00p01n01i00585ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00585arch OF c03s04b01x00p01n01i00585ent IS
+  type bit_vector_file is file of bit_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : bit_vector_file open read_mode is "iofile.22";
+    variable  v    : bit_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= B"0011") then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00585"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00585 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00585arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc586.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc586.vhd
new file mode 100644
index 0000000..bc85add
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc586.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc586.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:38 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:52 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:15 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00586ent IS
+END c03s04b01x00p01n01i00586ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00586arch OF c03s04b01x00p01n01i00586ent IS
+  type real_cons_vector  is array (15 downto 0) of real;
+  type real_cons_vector_file is file of real_cons_vector;
+  constant C19 : real_cons_vector := (others => 3.0);
+BEGIN
+  TESTING: PROCESS
+    file filein : real_cons_vector_file open write_mode is "iofile.31";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00586 - The output file will be verified by test s010244.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00586arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc587.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc587.vhd
new file mode 100644
index 0000000..658a610
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc587.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc587.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:38 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00587ent IS
+END c03s04b01x00p01n01i00587ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00587arch OF c03s04b01x00p01n01i00587ent IS
+  type boolean_vector       is array (natural range <>) of boolean;
+  type boolean_vector_file is file of boolean_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_vector_file open write_mode is "iofile.23";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(true,false));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00587 - The output file will be verified by test s010224.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00587arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc588.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc588.vhd
new file mode 100644
index 0000000..6d22054
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc588.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc588.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:38 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:53 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:15 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00588ent IS
+END c03s04b01x00p01n01i00588ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00588arch OF c03s04b01x00p01n01i00588ent IS
+  type boolean_vector      is array (natural range <>) of boolean;
+  type boolean_vector_file is file of boolean_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : boolean_vector_file open read_mode is "iofile.23";
+    variable  v    : boolean_vector(0 to 1);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 2) report "wrong length passed during read operation";
+      if (v /= (true,false)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00588"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00588 - File reading operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00588arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc589.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc589.vhd
new file mode 100644
index 0000000..e52cf75
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc589.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc589.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:38 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:53 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:15 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00589ent IS
+END c03s04b01x00p01n01i00589ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00589arch OF c03s04b01x00p01n01i00589ent IS
+  type real_cons_vector      is array (15 downto 0) of real;
+  type real_cons_vector_file is file of real_cons_vector;
+  constant C19 : real_cons_vector := (others => 3.0);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : real_cons_vector_file open read_mode is "iofile.31";
+    variable  v    : real_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00589"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00589 - File reading operation (real_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00589arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc590.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc590.vhd
new file mode 100644
index 0000000..408ddc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc590.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc590.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:38 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00590ent IS
+END c03s04b01x00p01n01i00590ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00590arch OF c03s04b01x00p01n01i00590ent IS
+  type severity_level_vector  is array (natural range <>) of severity_level;
+  type severity_level_vector_file is file of severity_level_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_vector_file open write_mode is "iofile.24";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(note,error));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00590 - The output file will be verified by test s010226.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00590arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc591.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc591.vhd
new file mode 100644
index 0000000..f03720b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc591.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc591.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:39 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:54 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:16 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00591ent IS
+END c03s04b01x00p01n01i00591ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00591arch OF c03s04b01x00p01n01i00591ent IS
+  type severity_level_vector      is array (natural range <>) of severity_level;
+  type severity_level_vector_file is file of severity_level_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : severity_level_vector_file open read_mode is "iofile.24";
+    variable  v    : severity_level_vector(0 to 1);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 2) report "wrong length passed during read operation";
+      if (v /= (note,error)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00591"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00591 - File reading operation (severity_level_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00591arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc592.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc592.vhd
new file mode 100644
index 0000000..40f416e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc592.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc592.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:39 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:55 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:16 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00592ent IS
+END c03s04b01x00p01n01i00592ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00592arch OF c03s04b01x00p01n01i00592ent IS
+  type severity_level_cons_vector      is array (15 downto 0) of severity_level;
+  type severity_level_cons_vector_file is file of severity_level_cons_vector;
+  constant C19 : severity_level_cons_vector := (others => note);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : severity_level_cons_vector_file open read_mode is "iofile.29";
+    variable  v    : severity_level_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00592"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00592 - File reading operation (severity_level_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00592arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc593.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc593.vhd
new file mode 100644
index 0000000..3e3ce84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc593.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc593.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:39 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00593ent IS
+END c03s04b01x00p01n01i00593ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00593arch OF c03s04b01x00p01n01i00593ent IS
+  type integer_vector  is array (natural range <>) of integer;
+  type integer_vector_file is file of integer_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_vector_file open write_mode is "iofile.25";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(1,2,3,4));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00593 - The output file will be verified by test s010228.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00593arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc594.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc594.vhd
new file mode 100644
index 0000000..b00c1f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc594.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc594.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:39 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:56 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:17 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00594ent IS
+END c03s04b01x00p01n01i00594ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00594arch OF c03s04b01x00p01n01i00594ent IS
+  type integer_vector      is array (natural range <>) of integer;
+  type integer_vector_file is file of integer_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : integer_vector_file open read_mode is "iofile.25";
+    variable  v    : integer_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= (1,2,3,4)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00594"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00594 - File reading operation (integer_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00594arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc595.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc595.vhd
new file mode 100644
index 0000000..843cfaa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc595.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc595.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:39 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:56 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:17 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00595ent IS
+END c03s04b01x00p01n01i00595ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00595arch OF c03s04b01x00p01n01i00595ent IS
+  constant C1 : boolean   := true;
+  type boolean_vector             is array (natural range <>) of boolean;
+  subtype boolean_vector_st       is boolean_vector(0 to 15);
+  type boolean_vector_st_file    is file of boolean_vector_st;
+  constant C27 : boolean_vector_st := (others => C1);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : boolean_vector_st_file open read_mode is "iofile.28";
+    variable  v    : boolean_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00595"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00595 - File reading operation (boolean_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00595arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc596.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc596.vhd
new file mode 100644
index 0000000..dd26cad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc596.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc596.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:40 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00596ent IS
+END c03s04b01x00p01n01i00596ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00596arch OF c03s04b01x00p01n01i00596ent IS
+  type real_vector  is array (natural range <>) of real;
+  type real_vector_file is file of real_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : real_vector_file open write_mode is "iofile.26";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(1.0,2.0,3.0,4.0));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00596 - The output file will be verified by test s010230.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00596arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc597.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc597.vhd
new file mode 100644
index 0000000..5cb59fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc597.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc597.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:40 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:57 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:18 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00597ent IS
+END c03s04b01x00p01n01i00597ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00597arch OF c03s04b01x00p01n01i00597ent IS
+  type real_vector      is array (natural range <>) of real;
+  type real_vector_file is file of real_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : real_vector_file open read_mode is "iofile.26";
+    variable  v    : real_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= (1.0,2.0,3.0,4.0)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00597"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00597 - File reading operation (real_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00597arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc598.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc598.vhd
new file mode 100644
index 0000000..ce9920a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc598.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc598.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:40 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00598ent IS
+END c03s04b01x00p01n01i00598ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00598arch OF c03s04b01x00p01n01i00598ent IS
+  type time_cons_vector  is array (15 downto 0) of time;
+  type time_cons_vector_file is file of time_cons_vector;
+  constant C19 : time_cons_vector := (others => 3 ns);
+BEGIN
+  TESTING: PROCESS
+    file filein : time_cons_vector_file open write_mode is "iofile.32";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00598 - The output file will be verified by test s010246.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00598arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc599.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc599.vhd
new file mode 100644
index 0000000..a8e923e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc599.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc599.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:40 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00599ent IS
+END c03s04b01x00p01n01i00599ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00599arch OF c03s04b01x00p01n01i00599ent IS
+  type time_vector  is array (natural range <>) of time;
+  type time_vector_file is file of time_vector;
+BEGIN
+  TESTING: PROCESS
+    file filein : time_vector_file open write_mode is "iofile.27";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,(1 ns,2 ns,3 ns,4 ns));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00599 - The output file will be verified by test s010232.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00599arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc600.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc600.vhd
new file mode 100644
index 0000000..2deafd9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc600.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc600.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:40 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:58 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:18 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00600ent IS
+END c03s04b01x00p01n01i00600ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00600arch OF c03s04b01x00p01n01i00600ent IS
+  type time_vector      is array (natural range <>) of time;
+  type time_vector_file is file of time_vector;
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : time_vector_file open read_mode is "iofile.27";
+    variable  v    : time_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= (1 ns,2 ns,3 ns,4 ns)) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00600"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00600 - File reading operation (time_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00600arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc601.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc601.vhd
new file mode 100644
index 0000000..8da71e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc601.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc601.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:41 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:25:58 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:19 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00601ent IS
+END c03s04b01x00p01n01i00601ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00601arch OF c03s04b01x00p01n01i00601ent IS
+  type time_cons_vector      is array (15 downto 0) of time;
+  type time_cons_vector_file is file of time_cons_vector;
+  constant C19 : time_cons_vector := (others => 3 ns);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : time_cons_vector_file open read_mode is "iofile.32";
+    variable  v    : time_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00601"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00601 - File reading operation (time_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00601arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc602.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc602.vhd
new file mode 100644
index 0000000..e549a25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc602.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc602.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:41 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00602ent IS
+END c03s04b01x00p01n01i00602ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00602arch OF c03s04b01x00p01n01i00602ent IS
+  constant C4 : time    := 3 ns;
+  type    time_vector    is array (natural range <>) of time;
+  subtype time_vector_st    is time_vector(0 to 15);
+  type    time_vector_st_file    is file of time_vector_st;
+  constant C27 : time_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : time_vector_st_file open write_mode is "iofile.32";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00602 - The output file will be verified by test s010264.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00602arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc603.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc603.vhd
new file mode 100644
index 0000000..5c70ba0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc603.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc603.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:41 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00603ent IS
+END c03s04b01x00p01n01i00603ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00603arch OF c03s04b01x00p01n01i00603ent IS
+  type natural_cons_vector  is array (15 downto 0) of natural;
+  type natural_cons_vector_file is file of natural_cons_vector;
+  constant C19 : natural_cons_vector := (others => 3);
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_cons_vector_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00603 - The output file will be verified by test s010248.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00603arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc604.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc604.vhd
new file mode 100644
index 0000000..bae2fc3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc604.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc604.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:41 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:00 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:19 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00604ent IS
+END c03s04b01x00p01n01i00604ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00604arch OF c03s04b01x00p01n01i00604ent IS
+  type natural_cons_vector      is array (15 downto 0) of natural;
+  type natural_cons_vector_file is file of natural_cons_vector;
+  constant C19 : natural_cons_vector := (others => 3);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : natural_cons_vector_file open read_mode is "iofile.30";
+    variable  v    : natural_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00604"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00604 - File reading operation (natural_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00604arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc605.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc605.vhd
new file mode 100644
index 0000000..aeeabef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc605.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc605.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:41 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00605ent IS
+END c03s04b01x00p01n01i00605ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00605arch OF c03s04b01x00p01n01i00605ent IS
+  constant C4 : severity_level    := note;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  subtype severity_level_vector_st is severity_level_vector(0 to 15);
+  type severity_level_vector_st_file    is file of severity_level_vector_st;
+  constant C27 : severity_level_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_vector_st_file open write_mode is "iofile.29";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00605 - The output file will be verified by test s010258.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00605arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc606.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc606.vhd
new file mode 100644
index 0000000..4bffe74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc606.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc606.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:42 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00606ent IS
+END c03s04b01x00p01n01i00606ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00606arch OF c03s04b01x00p01n01i00606ent IS
+  type positive_cons_vector  is array (15 downto 0) of positive;
+  type positive_cons_vector_file is file of positive_cons_vector;
+  constant C19 : positive_cons_vector := (others => 3);
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_cons_vector_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00606 - The output file will be verified by test s010250.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00606arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc607.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc607.vhd
new file mode 100644
index 0000000..50a1d4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc607.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc607.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:42 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:01 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:20 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00607ent IS
+END c03s04b01x00p01n01i00607ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00607arch OF c03s04b01x00p01n01i00607ent IS
+  type positive_cons_vector      is array (15 downto 0) of positive;
+  type positive_cons_vector_file is file of positive_cons_vector;
+  constant C19 : positive_cons_vector := (others => 3);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : positive_cons_vector_file open read_mode is "iofile.30";
+    variable  v    : positive_cons_vector;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00607"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00607 - File reading operation (positive_cons_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00607arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc608.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc608.vhd
new file mode 100644
index 0000000..275bae5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc608.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc608.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:42 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:01 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:20 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00608ent IS
+END c03s04b01x00p01n01i00608ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00608arch OF c03s04b01x00p01n01i00608ent IS
+  constant C4 : severity_level    := note;
+  type severity_level_vector      is array (natural range <>) of severity_level;
+  subtype severity_level_vector_st is severity_level_vector(0 to 15);
+  type severity_level_vector_st_file      is file of severity_level_vector_st;
+  constant C27 : severity_level_vector_st := (others => C4);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : severity_level_vector_st_file open read_mode is "iofile.29";
+    variable  v    : severity_level_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00608"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00608 - File reading operation (severity_level_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00608arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc609.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc609.vhd
new file mode 100644
index 0000000..bfd7a2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc609.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc609.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:42 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00609ent IS
+END c03s04b01x00p01n01i00609ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00609arch OF c03s04b01x00p01n01i00609ent IS
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c: character;
+                               d: severity_level;
+                               e: integer;
+                               f: real;
+                               g: time;
+                               h: natural;
+                               i: positive;
+                             end record;
+  type record_std_package_file is file of record_std_package;
+  constant C19 : record_std_package := (true,'1','s',note,3,3.0,3 ns,3,3); 
+BEGIN
+  TESTING: PROCESS
+    file filein : record_std_package_file open write_mode is "iofile.33";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C19);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00609 - The output file will be verified by test s010252.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00609arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc610.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc610.vhd
new file mode 100644
index 0000000..4aa6586
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc610.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc610.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:43 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:02 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:21 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00610ent IS
+END c03s04b01x00p01n01i00610ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00610arch OF c03s04b01x00p01n01i00610ent IS
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c: character;
+                               d: severity_level;
+                               e: integer;
+                               f: real;
+                               g: time;
+                               h: natural;
+                               i: positive;
+                             end record;
+  type record_std_package_file is file of record_std_package;
+  constant C19 : record_std_package := (true,'1','s',note,3,3.0,3 ns,3,3);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : record_std_package_file open read_mode is "iofile.33";
+    variable  v    : record_std_package;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C19) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00610"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00610 - File reading operation (record_std_package file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00610arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc611.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc611.vhd
new file mode 100644
index 0000000..bfaa7e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc611.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc611.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:43 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:03 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:21 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00611ent IS
+END c03s04b01x00p01n01i00611ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00611arch OF c03s04b01x00p01n01i00611ent IS
+  constant C4 : time   := 3 ns;
+  type    time_vector        is array (natural range <>) of time;
+  subtype time_vector_st       is time_vector(0 to 15);
+  type    time_vector_st_file     is file of time_vector_st;
+  constant    C27    : time_vector_st := (others => C4);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : time_vector_st_file open read_mode is "iofile.32";
+    variable  v    : time_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00611"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00611 - File reading operation (time_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00611arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc612.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc612.vhd
new file mode 100644
index 0000000..8777ef9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc612.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc612.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:43 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00612ent IS
+END c03s04b01x00p01n01i00612ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00612arch OF c03s04b01x00p01n01i00612ent IS
+  constant C1 : boolean    := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 3;
+  constant C9 : positive    := 3;
+  type boolean_cons_vector is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector is array (15 downto 0) of integer;
+  type real_cons_vector is array (15 downto 0) of real;
+  type time_cons_vector is array (15 downto 0) of time;
+  type natural_cons_vector is array (15 downto 0) of natural;
+  type positive_cons_vector is array (15 downto 0) of positive;
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector    := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  type record_cons_array_file is file of record_cons_array;
+  constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+BEGIN
+  TESTING: PROCESS
+    file filein : record_cons_array_file open write_mode is "iofile.34";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00612 - The output file will be verified by test s010254.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00612arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc613.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc613.vhd
new file mode 100644
index 0000000..155b42f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc613.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc613.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:43 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:03 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:22 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00613ent IS
+END c03s04b01x00p01n01i00613ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00613arch OF c03s04b01x00p01n01i00613ent IS
+  constant C1 : boolean   := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer   := 3;
+  constant C6 : real      := 3.0;
+  constant C7 : time      := 3 ns;
+  constant C8 : natural   := 3;
+  constant C9 : positive  := 3;
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+  constant C19 : boolean_cons_vector      := (others => C1);
+  constant C20 : severity_level_cons_vector       := (others => C4);
+  constant C21 : integer_cons_vector      := (others => C5);
+  constant C22 : real_cons_vector         := (others => C6);
+  constant C23 : time_cons_vector         := (others => C7);
+  constant C24 : natural_cons_vector      := (others => C8);
+  constant C25 : positive_cons_vector     := (others => C9);
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  type record_cons_array_file is file of record_cons_array;
+  constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : record_cons_array_file open read_mode is "iofile.34";
+    variable  v    : record_cons_array;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00613"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00613 - File reading operation (record_cons_array file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00613arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc614.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc614.vhd
new file mode 100644
index 0000000..f09bcec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc614.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc614.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:43 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00614ent IS
+END c03s04b01x00p01n01i00614ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00614arch OF c03s04b01x00p01n01i00614ent IS
+  constant    C4 : integer    := 3;
+  type       integer_vector       is array (natural range <>) of integer;
+  subtype    integer_vector_st    is integer_vector(0 to 15);
+  type       integer_vector_st_file    is file of integer_vector_st;
+  constant    C27 : integer_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_vector_st_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00614 - The output file will be verified by test s010260.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00614arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc615.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc615.vhd
new file mode 100644
index 0000000..6bc03b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc615.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc615.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:44 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:04 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:22 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00615ent IS
+END c03s04b01x00p01n01i00615ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00615arch OF c03s04b01x00p01n01i00615ent IS
+  constant C4 : integer   := 3;
+  type integer_vector     is array (natural range <>) of integer;
+  subtype integer_vector_st is integer_vector(0 to 15);
+  type integer_vector_st_file     is file of integer_vector_st;
+  constant C27 : integer_vector_st := (others => C4);
+  signal    k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : integer_vector_st_file open read_mode is "iofile.30";
+    variable  v    : integer_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00615"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00615 - File reading operation (integer_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00615arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc616.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc616.vhd
new file mode 100644
index 0000000..41f378d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc616.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc616.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:44 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00616ent IS
+END c03s04b01x00p01n01i00616ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00616arch OF c03s04b01x00p01n01i00616ent IS
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  type record_array_st_file is file of record_array_st;
+
+  constant C1 : boolean    := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 3;
+  constant C9 : positive    := 3;
+
+  constant C28 : boolean_vector_st    :=(others => C1);
+  constant C29 : severity_level_vector_st   :=(others => C4);
+  constant C30 : integer_vector_st   :=(others => C5);
+  constant C31 : real_vector_st      :=(others => C6);
+  constant C32 : time_vector_st      :=(others => C7);
+  constant C33 : natural_vector_st   :=(others => C8);
+  constant C34 : positive_vector_st   :=(others => C9);
+
+  constant C35 : record_array_st    := (C28,C29,C30,C31,C32,C33,C34);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : record_array_st_file open write_mode is "iofile.34";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C35);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00616 - The output file will be verified by test s010270.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00616arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc617.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc617.vhd
new file mode 100644
index 0000000..3be4b58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc617.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc617.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:44 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00617ent IS
+END c03s04b01x00p01n01i00617ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00617arch OF c03s04b01x00p01n01i00617ent IS
+  constant C4 : real    := 3.0;
+  type    real_vector    is array (natural range <>) of real;
+  subtype real_vector_st is real_vector(0 to 15);
+  type    real_vector_st_file    is file of real_vector_st;
+  constant C27 : real_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : real_vector_st_file open write_mode is "iofile.31";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00617 - The output file will be verified by test s010262.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00617arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc618.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc618.vhd
new file mode 100644
index 0000000..27e282e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc618.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc618.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:44 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:06 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:23 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00618ent IS
+END c03s04b01x00p01n01i00618ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00618arch OF c03s04b01x00p01n01i00618ent IS
+  constant    C4    : real   := 3.0;
+  type    real_vector        is array (natural range <>) of real;
+  subtype real_vector_st       is real_vector(0 to 15);
+  type    real_vector_st_file     is file of real_vector_st;
+  constant    C27    : real_vector_st := (others => C4);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : real_vector_st_file open read_mode is "iofile.31";
+    variable  v    : real_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00618"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00618 - File reading operation (real_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00618arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc619.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc619.vhd
new file mode 100644
index 0000000..37580c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc619.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc619.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:44 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00619ent IS
+END c03s04b01x00p01n01i00619ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00619arch OF c03s04b01x00p01n01i00619ent IS
+  constant C4 : natural    := 3 ;
+  type    natural_vector       is array (natural range <>) of natural;
+  subtype natural_vector_st    is natural_vector(0 to 15);
+  type    natural_vector_st_file    is file of natural_vector_st;
+  constant C27 : natural_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_vector_st_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00619 - The output file will be verified by test s010266.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00619arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc620.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc620.vhd
new file mode 100644
index 0000000..e2bc086
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc620.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc620.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:45 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:06 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:24 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00620ent IS
+END c03s04b01x00p01n01i00620ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00620arch OF c03s04b01x00p01n01i00620ent IS
+  constant C4 : natural   := 3 ;
+  type    natural_vector        is array (natural range <>) of natural;
+  subtype natural_vector_st    is natural_vector(0 to 15);
+  type    natural_vector_st_file  is file of natural_vector_st;
+  constant    C27    : natural_vector_st := (others => C4);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : natural_vector_st_file open read_mode is "iofile.30";
+    variable  v    : natural_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00620"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00620 - File reading operation (natural_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00620arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc621.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc621.vhd
new file mode 100644
index 0000000..02c858a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc621.vhd
@@ -0,0 +1,121 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc621.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:45 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:07 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:24 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00621ent IS
+END c03s04b01x00p01n01i00621ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00621arch OF c03s04b01x00p01n01i00621ent IS
+  type boolean_vector     is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector     is array (natural range <>) of integer;
+  type real_vector        is array (natural range <>) of real;
+  type time_vector        is array (natural range <>) of time;
+  type natural_vector     is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  
+  subtype boolean_vector_st       is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st          is  real_vector(0 to 15);
+  subtype time_vector_st          is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st      is  positive_vector(0 to 15);
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  type record_array_st_file is file of record_array_st;
+  
+  constant C1 : boolean   := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer   := 3;
+  constant C6 : real      := 3.0;
+  constant C7 : time      := 3 ns;
+  constant C8 : natural   := 3;
+  constant C9 : positive  := 3;
+  
+  constant C28 : boolean_vector_st        :=(others => C1);
+  constant C29 : severity_level_vector_st :=(others => C4);
+  constant C30 : integer_vector_st        :=(others => C5);
+  constant C31 : real_vector_st           :=(others => C6);
+  constant C32 : time_vector_st           :=(others => C7);
+  constant C33 : natural_vector_st        :=(others => C8);
+  constant C34 : positive_vector_st       :=(others => C9);
+  
+  constant C35 : record_array_st  := (C28,C29,C30,C31,C32,C33,C34);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : record_array_st_file open read_mode is "iofile.34";
+    variable  v    : record_array_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C35) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00621"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00621 - File reading operation (record_array_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00621arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc622.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc622.vhd
new file mode 100644
index 0000000..241256b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc622.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc622.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:45 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00622ent IS
+END c03s04b01x00p01n01i00622ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00622arch OF c03s04b01x00p01n01i00622ent IS
+  constant C4 : positive    := 3 ;
+  type    positive_vector       is array (natural range <>) of positive;
+  subtype positive_vector_st       is positive_vector(0 to 15);
+  type    positive_vector_st_file    is file of positive_vector_st;
+  constant C27 : positive_vector_st := (others => C4);
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_vector_st_file open write_mode is "iofile.30";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C27);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00622 - The output file will be verified by test s010268.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00622arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc623.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc623.vhd
new file mode 100644
index 0000000..048936d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc623.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc623.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:45 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:08 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:24 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00623ent IS
+END c03s04b01x00p01n01i00623ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00623arch OF c03s04b01x00p01n01i00623ent IS
+  constant C4 : positive   := 3 ;
+  type    positive_vector        is array (natural range <>) of positive;
+  subtype positive_vector_st    is positive_vector(0 to 15);
+  type    positive_vector_st_file is file of positive_vector_st;
+  constant    C27    : positive_vector_st := (others => C4);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : positive_vector_st_file open read_mode is "iofile.30";
+    variable  v    : positive_vector_st;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C27) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00623"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00623 - File reading operation (positive_vector_st file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00623arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc624.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc624.vhd
new file mode 100644
index 0000000..18e6641
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc624.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc624.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:45 1996  --
+--                 ****************************               --
+
+
+
+
+ENTITY c03s04b01x00p01n01i00624ent IS
+END c03s04b01x00p01n01i00624ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00624arch OF c03s04b01x00p01n01i00624ent IS
+
+  type    four_value    is ('Z','0','1','X');
+  type    four_value_file is file of four_value;
+  constant C38 : four_value := 'X';
+
+BEGIN
+  TESTING: PROCESS
+    file filein : four_value_file open write_mode is "iofile.36";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00624 - The output file will be verified by test s010274.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00624arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc625.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc625.vhd
new file mode 100644
index 0000000..4f17c28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc625.vhd
@@ -0,0 +1,164 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc625.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:46 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00625ent IS
+END c03s04b01x00p01n01i00625ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00625arch OF c03s04b01x00p01n01i00625ent IS
+
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st    is  real_vector(0 to 15);
+  subtype time_vector_st    is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+  
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              i: record_array_st;
+                            end record;
+
+  type record_of_records_file is file of record_of_records;
+
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 3;
+  constant C9 : positive := 3;
+
+  constant C10 : string := "shishir";
+  constant C11 : bit_vector := B"0011";
+  constant C12 : boolean_vector := (true,false);
+  constant C13 : severity_level_vector := (note,error);
+  constant C14 : integer_vector := (1,2,3,4);
+  constant C15 : real_vector := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector := (1,2,3,4);
+  constant C18 : positive_vector := (1,2,3,4);
+
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+
+  constant C26 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+
+  constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+
+  constant C28 : boolean_vector_st :=(others => C1);
+  constant C29 : severity_level_vector_st:= (others => C4);
+  constant C30 : integer_vector_st:=(others => C5);
+  constant C31 : real_vector_st:=(others => C6);
+  constant C32 : time_vector_st:=(others => C7);
+  constant C33 : natural_vector_st:=(others => C8);
+  constant C34 : positive_vector_st:=(others => C9);
+
+  constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
+
+  constant C37 : record_of_records := (C26,C27,C35);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : record_of_records_file open write_mode is "iofile.35";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C37);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00625 - The output file will be verified by test s010272.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00625arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc626.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc626.vhd
new file mode 100644
index 0000000..946e5ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc626.vhd
@@ -0,0 +1,184 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc626.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:46 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:09 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:25 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00626ent IS
+END c03s04b01x00p01n01i00626ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00626arch OF c03s04b01x00p01n01i00626ent IS
+  type boolean_vector  is array (natural range <>) of boolean;
+  type severity_level_vector   is array (natural range <>) of severity_level;
+  type integer_vector  is array (natural range <>) of integer;
+  type real_vector     is array (natural range <>) of real;
+  type time_vector     is array (natural range <>) of time;
+  type natural_vector  is array (natural range <>) of natural;
+  type positive_vector         is array (natural range <>) of positive;
+  
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st     is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st   is  positive_vector(0 to 15);
+
+  type boolean_cons_vector     is array (15 downto 0) of boolean;
+  type severity_level_cons_vector      is array (15 downto 0) of severity_level;
+  type integer_cons_vector     is array (15 downto 0) of integer;
+  type real_cons_vector        is array (15 downto 0) of real;
+  type time_cons_vector        is array (15 downto 0) of time;
+  type natural_cons_vector     is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              i: record_array_st;
+                            end record;
+  
+  type record_of_records_file is file of record_of_records;
+  
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 3;
+  constant C9 : positive := 3;
+  
+  constant C10 : string := "shishir";
+  constant C11 : bit_vector := B"0011";
+  constant C12 : boolean_vector := (true,false);
+  constant C13 : severity_level_vector := (note,error);
+  constant C14 : integer_vector := (1,2,3,4);
+  constant C15 : real_vector := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector := (1,2,3,4);
+  constant C18 : positive_vector := (1,2,3,4);
+  
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  
+  constant C26 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  
+  constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  
+  constant C28 : boolean_vector_st :=(others => C1);
+  constant C29 : severity_level_vector_st:= (others => C4);
+  constant C30 : integer_vector_st:=(others => C5);
+  constant C31 : real_vector_st:=(others => C6);
+  constant C32 : time_vector_st:=(others => C7);
+  constant C33 : natural_vector_st:=(others => C8);
+  constant C34 : positive_vector_st:=(others => C9);
+  
+  constant C35 : record_array_st := (C28,C29,C30,C31,C32,C33,C34);
+  
+  constant C37 : record_of_records := (C26,C27,C35);
+  signal       k    : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : record_of_records_file open read_mode is "iofile.35";
+    variable  v    : record_of_records;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C37) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00626"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00626 - File reading operation (record_of_records file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00626arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc627.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc627.vhd
new file mode 100644
index 0000000..eba7a2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc627.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc627.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:46 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:09 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:25 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00627ent IS
+END c03s04b01x00p01n01i00627ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00627arch OF c03s04b01x00p01n01i00627ent IS
+
+  type   four_value is ('Z','0','1','X');
+  type    four_value_file is file of four_value;
+  constant C38 : four_value := 'X';
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : four_value_file open read_mode is "iofile.36";
+    variable  v    : four_value;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00627"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00627 - File reading operation (four_value file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00627arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc628.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc628.vhd
new file mode 100644
index 0000000..7342217
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc628.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc628.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:46 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00628ent IS
+END c03s04b01x00p01n01i00628ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00628arch OF c03s04b01x00p01n01i00628ent IS
+
+  type   byte   is array(0 to 7) of bit;
+  type    byte_file    is file of byte;
+  constant C38 : byte := (others => '1');
+
+BEGIN
+  TESTING: PROCESS
+    file filein : byte_file open write_mode is "iofile.40";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00628 - The output file will be verified by test s010282.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00628arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc629.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc629.vhd
new file mode 100644
index 0000000..2df0930
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc629.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc629.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:47 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00629ent IS
+END c03s04b01x00p01n01i00629ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00629arch OF c03s04b01x00p01n01i00629ent IS
+
+  type    four_value    is ('Z','0','1','X');
+  type   four_value_map    is array (four_value) of boolean;
+  type    four_value_map_file is file of four_value_map;
+  constant C38 : four_value_map := (true,true,true,true);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : four_value_map_file open write_mode is "iofile.37";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00629 - The output file will be verified by test s010276.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00629arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc63.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc63.vhd
new file mode 100644
index 0000000..08e68c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc63.vhd
@@ -0,0 +1,580 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc63.vhd,v 1.2 2001-10-26 16:29:57 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p01n01i00063ent IS
+END c04s03b01x02p01n01i00063ent;
+
+ARCHITECTURE c04s03b01x02p01n01i00063arch OF c04s03b01x02p01n01i00063ent IS
+--
+--
+--          Declaration of composite types
+--           - array types and subtypes
+--
+  TYPE    ut_chary    IS ARRAY (CHARACTER RANGE <>) OF INTEGER;      -- unconstrained array type    
+  TYPE    ct_word     IS ARRAY (0 TO 15)            OF BIT;          -- constrained array type
+
+  SUBTYPE ust_subchary IS ut_chary;                                  -- unconstrained array subtype
+  SUBTYPE cst_str10    IS STRING    ( 1  TO 10 );                    -- constrained array subtype
+  SUBTYPE cst_digit    IS ut_chary  ('0' TO '9');                    -- constrained array subtype
+--
+--          Declaration of composite types
+--           - records types and subtypes
+--
+  TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+  TYPE rt_date IS
+    RECORD
+      day   : INTEGER RANGE 0 TO 31;
+      month : month_name;
+      year  : INTEGER RANGE 0 TO 4000;
+    END RECORD;
+--
+  SUBTYPE rst_date IS rt_date;
+  
+----------------------------------------------------------------------------------------------------------
+--
+--          SIGNAL declarations
+--
+  
+  SIGNAL     STRING_con_0 :     STRING (1 TO 7);
+  SIGNAL     STRING_con_1 :     STRING (1 TO 7) := "sailing";
+  SIGNAL     STRING_con_2 :     STRING (1 TO 7) := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
+  
+  SIGNAL BIT_VECTOR_con_0 : BIT_VECTOR (0 TO 7);
+  SIGNAL BIT_VECTOR_con_1 : BIT_VECTOR (0 TO 7) := B"10101110";
+  SIGNAL BIT_VECTOR_con_2 : BIT_VECTOR (0 TO 7) := ( '1', '0', '1', '0', '1', '1', '1', '0');
+  
+  SIGNAL   ut_chary_con_0 :   ut_chary (NUL TO ENQ);
+  SIGNAL   ut_chary_con_1 :   ut_chary (NUL TO ENQ) := ( 1, 2, 3, 9, 8, 7);
+  
+  SIGNAL    ct_word_con_0 :    ct_word;
+  SIGNAL    ct_word_con_1 :    ct_word := ( '1', '1', '1', '1', '1', '1', '1', '1',
+                                            '1', '1', '1', '1', '1', '1', '1', '1');
+  
+  SIGNAL  cst_str10_con_0 :  cst_str10;
+  SIGNAL  cst_str10_con_1 :  cst_str10 := "abcdefghij";
+  SIGNAL  cst_str10_con_2 :  cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');
+  
+  SIGNAL  cst_digit_con_0 :  cst_digit;
+  SIGNAL  cst_digit_con_1 :  cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
+  
+  SIGNAL    rt_date_con_0 :    rt_date;
+  SIGNAL    rt_date_con_1 :    rt_date := (1, Jan, 1989);
+  
+  SIGNAL   rst_date_con_0 :   rst_date;
+  SIGNAL   rst_date_con_1 :   rst_date := (1, Apr, 2000);
+
+----------------------------------------------------------------------------------------------------------
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+--
+    ASSERT STRING_con_0(1) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(2) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(3) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(4) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(5) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(6) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(7) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT BIT_VECTOR_con_0(0) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(1) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(2) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(3) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(4) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(5) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(6) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(7) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
+
+    ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ut_chary_con_0(NUL) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(SOH) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(STX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(ETX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(EOT) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(ENQ) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ut_chary_con_1(NUL) = 1 REPORT "ut_chary_con_1('a') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(SOH) = 2 REPORT "ut_chary_con_1('b') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(STX) = 3 REPORT "ut_chary_con_1('c') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(ETX) = 9 REPORT "ut_chary_con_1('d') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(EOT) = 8 REPORT "ut_chary_con_1('e') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(ENQ) = 7 REPORT "ut_chary_con_1('f') not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ct_word_con_0(0) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(1) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(2) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(3) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(4) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(5) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(6) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(7) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(8) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(9) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(10) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(11) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(12) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(13) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(14) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(15) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ct_word_con_1(0) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(1) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(2) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(3) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(4) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(5) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(6) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(7) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(8) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(9) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(10) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(11) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(12) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(13) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(14) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(15) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_str10_con_0(1) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(2) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(3) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(4) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(5) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(6) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(7) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(8) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(9) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(10) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+
+    ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_digit_con_0('0') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('1') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('2') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('3') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('4') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('5') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('6') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('7') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('8') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('9') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+
+    ASSERT cst_digit_con_1('0') = 0 REPORT "cst_digit_con_1('0') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('1') = 1 REPORT "cst_digit_con_1('1') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('2') = 2 REPORT "cst_digit_con_1('2') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('3') = 3 REPORT "cst_digit_con_1('3') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('4') = 4 REPORT "cst_digit_con_1('4') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('5') = 5 REPORT "cst_digit_con_1('5') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('6') = 6 REPORT "cst_digit_con_1('6') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('7') = 7 REPORT "cst_digit_con_1('7') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('8') = 8 REPORT "cst_digit_con_1('8') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('9') = 9 REPORT "cst_digit_con_1('9') not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT  rt_date_con_0.day   = 0    REPORT " rt_date_con_0.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_0.month = Jan  REPORT " rt_date_con_0.month not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_0.year  = 0    REPORT " rt_date_con_0.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT  rt_date_con_1.day   = 1    REPORT " rt_date_con_1.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_1.month = Jan  REPORT " rt_date_con_1.month not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_1.year  = 1989 REPORT " rt_date_con_1.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_con_0.day   = 0    REPORT "rst_date_con_0.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_0.month = Jan  REPORT "rst_date_con_0.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_0.year  = 0    REPORT "rst_date_con_0.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_con_1.day   = 1    REPORT "rst_date_con_1.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_1.month = Apr  REPORT "rst_date_con_1.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_1.year  = 2000 REPORT "rst_date_con_1.year  not properly intialized" SEVERITY FAILURE;
+
+-------------------------------------------------------------------------------------------------------------
+
+    assert NOT(   STRING_con_0(1) = NUL       and 
+                  STRING_con_0(2) = NUL       and 
+                  STRING_con_0(3) = NUL       and 
+                  STRING_con_0(4) = NUL       and 
+                  STRING_con_0(5) = NUL       and 
+                  STRING_con_0(6) = NUL       and 
+                  STRING_con_0(7) = NUL       and 
+                  STRING_con_1(1) = 's'       and 
+                  STRING_con_1(2) = 'a'       and 
+                  STRING_con_1(3) = 'i'       and 
+                  STRING_con_1(4) = 'l'       and 
+                  STRING_con_1(5) = 'i'       and 
+                  STRING_con_1(6) = 'n'       and 
+                  STRING_con_1(7) = 'g'       and 
+                  STRING_con_2(1) = 's'       and 
+                  STRING_con_2(2) = 'a'       and 
+                  STRING_con_2(3) = 'i'       and 
+                  STRING_con_2(4) = 'l'       and 
+                  STRING_con_2(5) = 'i'       and 
+                  STRING_con_2(6) = 'n'       and 
+                  STRING_con_2(7) = 'g'       and 
+                  BIT_VECTOR_con_0(0) = '0'    and 
+                  BIT_VECTOR_con_0(1) = '0'    and 
+                  BIT_VECTOR_con_0(2) = '0'    and 
+                  BIT_VECTOR_con_0(3) = '0'    and 
+                  BIT_VECTOR_con_0(4) = '0'    and 
+                  BIT_VECTOR_con_0(5) = '0'    and 
+                  BIT_VECTOR_con_0(6) = '0'    and 
+                  BIT_VECTOR_con_0(7) = '0'    and 
+                  BIT_VECTOR_con_1(0) = '1'    and 
+                  BIT_VECTOR_con_1(1) = '0'    and 
+                  BIT_VECTOR_con_1(2) = '1'    and 
+                  BIT_VECTOR_con_1(3) = '0'    and 
+                  BIT_VECTOR_con_1(4) = '1'    and 
+                  BIT_VECTOR_con_1(5) = '1'    and 
+                  BIT_VECTOR_con_1(6) = '1'    and 
+                  BIT_VECTOR_con_1(7) = '0'    and 
+                  BIT_VECTOR_con_2(0) = '1'    and 
+                  BIT_VECTOR_con_2(1) = '0'    and 
+                  BIT_VECTOR_con_2(2) = '1'    and 
+                  BIT_VECTOR_con_2(3) = '0'    and 
+                  BIT_VECTOR_con_2(4) = '1'    and 
+                  BIT_VECTOR_con_2(5) = '1'    and 
+                  BIT_VECTOR_con_2(6) = '1'    and 
+                  BIT_VECTOR_con_2(7) = '0'    and 
+                  ut_chary_con_0(NUL) = INTEGER'LEFT and 
+                  ut_chary_con_0(SOH) = INTEGER'LEFT and 
+                  ut_chary_con_0(STX) = INTEGER'LEFT and 
+                  ut_chary_con_0(ETX) = INTEGER'LEFT and 
+                  ut_chary_con_0(EOT) = INTEGER'LEFT and 
+                  ut_chary_con_0(ENQ) = INTEGER'LEFT and 
+                  ut_chary_con_1(NUL) = 1    and 
+                  ut_chary_con_1(SOH) = 2    and 
+                  ut_chary_con_1(STX) = 3    and 
+                  ut_chary_con_1(ETX) = 9    and 
+                  ut_chary_con_1(EOT) = 8    and 
+                  ut_chary_con_1(ENQ) = 7    and 
+                  ct_word_con_0(0) = '0'       and 
+                  ct_word_con_0(1) = '0'       and 
+                  ct_word_con_0(2) = '0'       and 
+                  ct_word_con_0(3) = '0'       and 
+                  ct_word_con_0(4) = '0'       and 
+                  ct_word_con_0(5) = '0'       and 
+                  ct_word_con_0(6) = '0'       and 
+                  ct_word_con_0(7) = '0'       and 
+                  ct_word_con_0(8) = '0'       and 
+                  ct_word_con_0(9) = '0'       and 
+                  ct_word_con_0(10) = '0'    and 
+                  ct_word_con_0(11) = '0'    and 
+                  ct_word_con_0(12) = '0'    and 
+                  ct_word_con_0(13) = '0'    and 
+                  ct_word_con_0(14) = '0'    and 
+                  ct_word_con_0(15) = '0'    and 
+                  ct_word_con_1(0) = '1'       and 
+                  ct_word_con_1(1) = '1'       and 
+                  ct_word_con_1(2) = '1'       and 
+                  ct_word_con_1(3) = '1'       and 
+                  ct_word_con_1(4) = '1'       and 
+                  ct_word_con_1(5) = '1'       and 
+                  ct_word_con_1(6) = '1'       and 
+                  ct_word_con_1(7) = '1'       and 
+                  ct_word_con_1(8) = '1'       and 
+                  ct_word_con_1(9) = '1'       and 
+                  ct_word_con_1(10) = '1'    and 
+                  ct_word_con_1(11) = '1'    and 
+                  ct_word_con_1(12) = '1'    and 
+                  ct_word_con_1(13) = '1'    and 
+                  ct_word_con_1(14) = '1'    and 
+                  ct_word_con_1(15) = '1'    and 
+                  cst_str10_con_0(1) = NUL    and 
+                  cst_str10_con_0(2) = NUL    and 
+                  cst_str10_con_0(3) = NUL    and 
+                  cst_str10_con_0(4) = NUL    and 
+                  cst_str10_con_0(5) = NUL    and 
+                  cst_str10_con_0(6) = NUL    and 
+                  cst_str10_con_0(7) = NUL    and 
+                  cst_str10_con_0(8) = NUL    and 
+                  cst_str10_con_0(9) = NUL    and 
+                  cst_str10_con_0(10) = NUL    and 
+                  cst_str10_con_1(1) = 'a'    and
+                  cst_str10_con_1(2) = 'b'    and
+                  cst_str10_con_1(3) = 'c'    and
+                  cst_str10_con_1(4) = 'd'    and
+                  cst_str10_con_1(5) = 'e'    and
+                  cst_str10_con_1(6) = 'f'    and
+                  cst_str10_con_1(7) = 'g'    and
+                  cst_str10_con_1(8) = 'h'    and
+                  cst_str10_con_1(9) = 'i'    and
+                  cst_str10_con_1(10)= 'j'    and
+                  cst_str10_con_2(1) = 'a'    and
+                  cst_str10_con_2(2) = 'b'    and
+                  cst_str10_con_2(3) = 'c'    and
+                  cst_str10_con_2(4) = 'd'    and
+                  cst_str10_con_2(5) = 'e'    and
+                  cst_str10_con_2(6) = 'f'    and
+                  cst_str10_con_2(7) = 'g'    and
+                  cst_str10_con_2(8) = 'h'    and
+                  cst_str10_con_2(9) = 'i'    and
+                  cst_str10_con_2(10)= 'j'    and
+                  cst_digit_con_0('0') = INTEGER'LEFT    and
+                  cst_digit_con_0('1') = INTEGER'LEFT    and
+                  cst_digit_con_0('2') = INTEGER'LEFT    and
+                  cst_digit_con_0('3') = INTEGER'LEFT    and
+                  cst_digit_con_0('4') = INTEGER'LEFT    and
+                  cst_digit_con_0('5') = INTEGER'LEFT    and
+                  cst_digit_con_0('6') = INTEGER'LEFT    and
+                  cst_digit_con_0('7') = INTEGER'LEFT    and
+                  cst_digit_con_0('8') = INTEGER'LEFT    and
+                  cst_digit_con_0('9') = INTEGER'LEFT    and
+                  cst_digit_con_1('0') = 0    and
+                  cst_digit_con_1('1') = 1    and
+                  cst_digit_con_1('2') = 2    and
+                  cst_digit_con_1('3') = 3    and
+                  cst_digit_con_1('4') = 4    and
+                  cst_digit_con_1('5') = 5    and
+                  cst_digit_con_1('6') = 6    and
+                  cst_digit_con_1('7') = 7    and
+                  cst_digit_con_1('8') = 8    and
+                  cst_digit_con_1('9') = 9    and
+                  rt_date_con_0.day   = 0       and
+                  rt_date_con_0.month = Jan     and
+                  rt_date_con_0.year  = 0       and
+                  rt_date_con_1.day   = 1       and
+                  rt_date_con_1.month = Jan     and
+                  rt_date_con_1.year  = 1989    and
+                  rst_date_con_0.day   = 0       and
+                  rst_date_con_0.month = Jan     and
+                  rst_date_con_0.year  = 0       and
+                  rst_date_con_1.day   = 1       and
+                  rst_date_con_1.month = Apr     and
+                  rst_date_con_1.year  = 2000    )
+      report "***PASSED TEST: /src/ch04/sc03/sb01/ss02/p001/s010101.vhd"
+      severity NOTE;
+    assert (   STRING_con_0(1) = NUL       and 
+               STRING_con_0(2) = NUL       and 
+               STRING_con_0(3) = NUL       and 
+               STRING_con_0(4) = NUL       and 
+               STRING_con_0(5) = NUL       and 
+               STRING_con_0(6) = NUL       and 
+               STRING_con_0(7) = NUL       and 
+               STRING_con_1(1) = 's'       and 
+               STRING_con_1(2) = 'a'       and 
+               STRING_con_1(3) = 'i'       and 
+               STRING_con_1(4) = 'l'       and 
+               STRING_con_1(5) = 'i'       and 
+               STRING_con_1(6) = 'n'       and 
+               STRING_con_1(7) = 'g'       and 
+               STRING_con_2(1) = 's'       and 
+               STRING_con_2(2) = 'a'       and 
+               STRING_con_2(3) = 'i'       and 
+               STRING_con_2(4) = 'l'       and 
+               STRING_con_2(5) = 'i'       and 
+               STRING_con_2(6) = 'n'       and 
+               STRING_con_2(7) = 'g'       and 
+               BIT_VECTOR_con_0(0) = '0'    and 
+               BIT_VECTOR_con_0(1) = '0'    and 
+               BIT_VECTOR_con_0(2) = '0'    and 
+               BIT_VECTOR_con_0(3) = '0'    and 
+               BIT_VECTOR_con_0(4) = '0'    and 
+               BIT_VECTOR_con_0(5) = '0'    and 
+               BIT_VECTOR_con_0(6) = '0'    and 
+               BIT_VECTOR_con_0(7) = '0'    and 
+               BIT_VECTOR_con_1(0) = '1'    and 
+               BIT_VECTOR_con_1(1) = '0'    and 
+               BIT_VECTOR_con_1(2) = '1'    and 
+               BIT_VECTOR_con_1(3) = '0'    and 
+               BIT_VECTOR_con_1(4) = '1'    and 
+               BIT_VECTOR_con_1(5) = '1'    and 
+               BIT_VECTOR_con_1(6) = '1'    and 
+               BIT_VECTOR_con_1(7) = '0'    and 
+               BIT_VECTOR_con_2(0) = '1'    and 
+               BIT_VECTOR_con_2(1) = '0'    and 
+               BIT_VECTOR_con_2(2) = '1'    and 
+               BIT_VECTOR_con_2(3) = '0'    and 
+               BIT_VECTOR_con_2(4) = '1'    and 
+               BIT_VECTOR_con_2(5) = '1'    and 
+               BIT_VECTOR_con_2(6) = '1'    and 
+               BIT_VECTOR_con_2(7) = '0'    and 
+               ut_chary_con_0(NUL) = INTEGER'LEFT and 
+               ut_chary_con_0(SOH) = INTEGER'LEFT and 
+               ut_chary_con_0(STX) = INTEGER'LEFT and 
+               ut_chary_con_0(ETX) = INTEGER'LEFT and 
+               ut_chary_con_0(EOT) = INTEGER'LEFT and 
+               ut_chary_con_0(ENQ) = INTEGER'LEFT and 
+               ut_chary_con_1(NUL) = 1    and 
+               ut_chary_con_1(SOH) = 2    and 
+               ut_chary_con_1(STX) = 3    and 
+               ut_chary_con_1(ETX) = 9    and 
+               ut_chary_con_1(EOT) = 8    and 
+               ut_chary_con_1(ENQ) = 7    and 
+               ct_word_con_0(0) = '0'       and 
+               ct_word_con_0(1) = '0'       and 
+               ct_word_con_0(2) = '0'       and 
+               ct_word_con_0(3) = '0'       and 
+               ct_word_con_0(4) = '0'       and 
+               ct_word_con_0(5) = '0'       and 
+               ct_word_con_0(6) = '0'       and 
+               ct_word_con_0(7) = '0'       and 
+               ct_word_con_0(8) = '0'       and 
+               ct_word_con_0(9) = '0'       and 
+               ct_word_con_0(10) = '0'    and 
+               ct_word_con_0(11) = '0'    and 
+               ct_word_con_0(12) = '0'    and 
+               ct_word_con_0(13) = '0'    and 
+               ct_word_con_0(14) = '0'    and 
+               ct_word_con_0(15) = '0'    and 
+               ct_word_con_1(0) = '1'       and 
+               ct_word_con_1(1) = '1'       and 
+               ct_word_con_1(2) = '1'       and 
+               ct_word_con_1(3) = '1'       and 
+               ct_word_con_1(4) = '1'       and 
+               ct_word_con_1(5) = '1'       and 
+               ct_word_con_1(6) = '1'       and 
+               ct_word_con_1(7) = '1'       and 
+               ct_word_con_1(8) = '1'       and 
+               ct_word_con_1(9) = '1'       and 
+               ct_word_con_1(10) = '1'    and 
+               ct_word_con_1(11) = '1'    and 
+               ct_word_con_1(12) = '1'    and 
+               ct_word_con_1(13) = '1'    and 
+               ct_word_con_1(14) = '1'    and 
+               ct_word_con_1(15) = '1'    and 
+               cst_str10_con_0(1) = NUL    and 
+               cst_str10_con_0(2) = NUL    and 
+               cst_str10_con_0(3) = NUL    and 
+               cst_str10_con_0(4) = NUL    and 
+               cst_str10_con_0(5) = NUL    and 
+               cst_str10_con_0(6) = NUL    and 
+               cst_str10_con_0(7) = NUL    and 
+               cst_str10_con_0(8) = NUL    and 
+               cst_str10_con_0(9) = NUL    and 
+               cst_str10_con_0(10) = NUL    and 
+               cst_str10_con_1(1) = 'a'    and
+               cst_str10_con_1(2) = 'b'    and
+               cst_str10_con_1(3) = 'c'    and
+               cst_str10_con_1(4) = 'd'    and
+               cst_str10_con_1(5) = 'e'    and
+               cst_str10_con_1(6) = 'f'    and
+               cst_str10_con_1(7) = 'g'    and
+               cst_str10_con_1(8) = 'h'    and
+               cst_str10_con_1(9) = 'i'    and
+               cst_str10_con_1(10)= 'j'    and
+               cst_str10_con_2(1) = 'a'    and
+               cst_str10_con_2(2) = 'b'    and
+               cst_str10_con_2(3) = 'c'    and
+               cst_str10_con_2(4) = 'd'    and
+               cst_str10_con_2(5) = 'e'    and
+               cst_str10_con_2(6) = 'f'    and
+               cst_str10_con_2(7) = 'g'    and
+               cst_str10_con_2(8) = 'h'    and
+               cst_str10_con_2(9) = 'i'    and
+               cst_str10_con_2(10)= 'j'    and
+               cst_digit_con_0('0') = INTEGER'LEFT    and
+               cst_digit_con_0('1') = INTEGER'LEFT    and
+               cst_digit_con_0('2') = INTEGER'LEFT    and
+               cst_digit_con_0('3') = INTEGER'LEFT    and
+               cst_digit_con_0('4') = INTEGER'LEFT    and
+               cst_digit_con_0('5') = INTEGER'LEFT    and
+               cst_digit_con_0('6') = INTEGER'LEFT    and
+               cst_digit_con_0('7') = INTEGER'LEFT    and
+               cst_digit_con_0('8') = INTEGER'LEFT    and
+               cst_digit_con_0('9') = INTEGER'LEFT    and
+               cst_digit_con_1('0') = 0    and
+               cst_digit_con_1('1') = 1    and
+               cst_digit_con_1('2') = 2    and
+               cst_digit_con_1('3') = 3    and
+               cst_digit_con_1('4') = 4    and
+               cst_digit_con_1('5') = 5    and
+               cst_digit_con_1('6') = 6    and
+               cst_digit_con_1('7') = 7    and
+               cst_digit_con_1('8') = 8    and
+               cst_digit_con_1('9') = 9    and
+               rt_date_con_0.day   = 0       and
+               rt_date_con_0.month = Jan     and
+               rt_date_con_0.year  = 0       and
+               rt_date_con_1.day   = 1       and
+               rt_date_con_1.month = Jan     and
+               rt_date_con_1.year  = 1989    and
+               rst_date_con_0.day   = 0       and
+               rst_date_con_0.month = Jan     and
+               rst_date_con_0.year  = 0       and
+               rst_date_con_1.day   = 1       and
+               rst_date_con_1.month = Apr     and
+               rst_date_con_1.year  = 2000    )
+      report "***FAILED TEST: c04s03b01x02p01n01i00063 - A signal declared a signal of the specified type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p01n01i00063arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc630.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc630.vhd
new file mode 100644
index 0000000..3e29762
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc630.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc630.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:47 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:11 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:26 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00630ent IS
+END c03s04b01x00p01n01i00630ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00630arch OF c03s04b01x00p01n01i00630ent IS
+
+  type   four_value is ('Z','0','1','X');
+  type   four_value_map is array (four_value) of boolean;
+  type    four_value_map_file is file of four_value_map;
+  constant C38 : four_value_map := (true,true,true,true);
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : four_value_map_file open read_mode is "iofile.37";
+    variable  v    : four_value_map;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00630"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00630 - File reading operation (four_value_map file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00630arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc631.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc631.vhd
new file mode 100644
index 0000000..2034913
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc631.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc631.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:48 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:11 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:26 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00631ent IS
+END c03s04b01x00p01n01i00631ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00631arch OF c03s04b01x00p01n01i00631ent IS
+
+  type   byte       is array (0 to 7) of bit;
+  type    byte_file    is file of byte;
+  constant C38 : byte := (others => '1');
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : byte_file open read_mode is "iofile.40";
+    variable  v    : byte;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00631"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00631 - File reading operation (byte file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00631arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc632.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc632.vhd
new file mode 100644
index 0000000..705fa6f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc632.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc632.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:48 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p01n01i00632ent IS
+END c03s04b01x00p01n01i00632ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00632arch OF c03s04b01x00p01n01i00632ent IS
+
+  type    four_value    is ('Z','0','1','X');
+  subtype   binary       is four_value range '0' to '1';
+  type    binary_file    is file of binary;
+  constant C38 : binary    := '0';
+
+BEGIN
+  TESTING: PROCESS
+    file filein : binary_file open write_mode is "iofile.38";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00632 - The output file will be verified by test s010278.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00632arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc633.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc633.vhd
new file mode 100644
index 0000000..f0e6f49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc633.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc633.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:48 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:12 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:27 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00633ent IS
+END c03s04b01x00p01n01i00633ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00633arch OF c03s04b01x00p01n01i00633ent IS
+
+  type   four_value    is ('Z','0','1','X');
+  subtype   binary       is four_value range '0' to '1';
+  type    binary_file    is file of binary;
+  constant C38 : binary := '0';
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : binary_file open read_mode is "iofile.38";
+    variable  v    : binary;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00633"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00633 - File reading operation (binary file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00633arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc634.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc634.vhd
new file mode 100644
index 0000000..25f86f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc634.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc634.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:48 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00634ent IS
+END c03s04b01x00p01n01i00634ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00634arch OF c03s04b01x00p01n01i00634ent IS
+
+  type      four_value    is ('Z','0','1','X');
+  subtype      binary      is four_value range '0' to '1';
+  subtype      word      is bit_vector(0 to 15);
+  constant   size      : integer := 7;
+  type      primary_memory   is array(0 to size) of word;
+
+  type    primary_memory_module is
+    record
+      enable      : binary;
+      memory_number   : primary_memory;
+    end record;
+
+  type    primary_memory_module_file    is file of primary_memory_module;
+
+  constant C38 : word          := (others => '1');
+  constant C44 : primary_memory       := (others => C38);
+  constant C45 : primary_memory_module    := ('1',C44);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : primary_memory_module_file open write_mode is "iofile.43";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C45);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00634 - The output file will be verified by test s010288.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00634arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc635.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc635.vhd
new file mode 100644
index 0000000..ecc8e7e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc635.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc635.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:49 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00635ent IS
+END c03s04b01x00p01n01i00635ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00635arch OF c03s04b01x00p01n01i00635ent IS
+
+  type    four_value    is ('Z','0','1','X');
+  type   four_value_vector    is array (natural range <>) of four_value;
+  type    four_value_vector_file    is file of four_value_vector;
+  constant C38 : four_value_vector    := ('1','0','1','0');
+
+BEGIN
+  TESTING: PROCESS
+    file filein : four_value_vector_file open write_mode is "iofile.39";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00635 - The output file will be verified by test s010280.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00635arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc636.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc636.vhd
new file mode 100644
index 0000000..2c129f7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc636.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc636.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:49 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:13 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:28 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00636ent IS
+END c03s04b01x00p01n01i00636ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00636arch OF c03s04b01x00p01n01i00636ent IS
+
+  type   four_value    is ('Z','0','1','X');
+  type   four_value_vector    is array (natural range <>) of four_value;
+  type    four_value_vector_file    is file of four_value_vector;
+  constant C38 : four_value_vector := ('1','0','1','0');
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : four_value_vector_file open read_mode is "iofile.39";
+    variable  v    : four_value_vector(0 to 3);
+    variable  len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 4) report "wrong length passed during read operation";
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00636"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00636 - File reading operation (four_value_vector file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00636arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc637.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc637.vhd
new file mode 100644
index 0000000..aa0643d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc637.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc637.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:50 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00637ent IS
+END c03s04b01x00p01n01i00637ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00637arch OF c03s04b01x00p01n01i00637ent IS
+
+  subtype      word   is bit_vector(0 to 15);
+  type    word_file    is file of word;
+  constant C38 : word := (others => '1');
+
+BEGIN
+  TESTING: PROCESS
+    file filein : word_file open write_mode is "iofile.41";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C38);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00637 - The output file will be verified by test s010284.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00637arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc638.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc638.vhd
new file mode 100644
index 0000000..e53ae92
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc638.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc638.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:50 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:14 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:28 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00638ent IS
+END c03s04b01x00p01n01i00638ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00638arch OF c03s04b01x00p01n01i00638ent IS
+
+  subtype   word       is bit_vector(0 to 15);
+  type    word_file    is file of word;
+  constant C38 : word := (others => '1');
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : word_file open read_mode is "iofile.41";
+    variable  v    : word;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C38) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00638"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00638 - File reading operation (word file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00638arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc639.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc639.vhd
new file mode 100644
index 0000000..55c9c4d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc639.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc639.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:51 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:14 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:28 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00639ent IS
+END c03s04b01x00p01n01i00639ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00639arch OF c03s04b01x00p01n01i00639ent IS
+
+  type            four_value    is ('Z','0','1','X');
+  subtype         binary          is four_value range '0' to '1';
+  subtype      word       is bit_vector(0 to 15);
+  constant   size      : integer := 7;
+  type       primary_memory  is array(0 to size) of word;
+
+  type    primary_memory_module is
+    record
+      enable          : binary;
+      memory_number   : primary_memory;
+    end record;
+
+  type       primary_memory_module_file     is file of primary_memory_module;
+
+  constant C38 : word          := (others => '1');
+  constant C44 : primary_memory       := (others => C38);
+  constant C45 : primary_memory_module    := ('1',C44);
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : primary_memory_module_file open read_mode is "iofile.43";
+    variable  v    : primary_memory_module;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C45) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00639"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00639 - File reading operation (primary_memory_module file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00639arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc64.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc64.vhd
new file mode 100644
index 0000000..2e30878
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc64.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc64.vhd,v 1.2 2001-10-26 16:29:58 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p02n01i00064ent IS
+END c04s03b01x02p02n01i00064ent;
+
+ARCHITECTURE c04s03b01x02p02n01i00064arch OF c04s03b01x02p02n01i00064ent IS
+  signal C1 : Boolean      := TRUE;          -- No_failure_here
+  signal C2 : bit          := '1';          -- No_failure_here
+  signal C3 : integer      := 12345;          -- No_failure_here
+  signal C4 : positive     := 54321;          -- No_failure_here
+  signal C5 : natural      := 12121;          -- No_failure_here
+  signal C6 : real         := 1.345;          -- No_failure_here
+  signal C7 : character    := 'N';          -- No_failure_here
+  signal C8 : time         := 100 ns;          -- No_failure_here
+  signal C9 : String    (1 to 8)    := "AAAAAAAA";  -- No_failure_here
+  signal C10 : bit_vector(0 to 7)    := "11111111";  -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(    C1   = TRUE   and
+                   C2   = '1'   and
+                   C3   = 12345   and
+                   C4   = 54321   and
+                   C5   = 12121   and
+                   C6   = 1.345   and
+                   C7   = 'N'   and
+                   C8   = 100 ns   and
+                   C9   = "AAAAAAAA"   and
+                   C10   = "11111111"   ) 
+      report "***PASSED TEST:c04s03b01x02p02n01i00064"
+      severity NOTE;
+    assert (    C1   = TRUE   and
+                C2   = '1'   and
+                C3   = 12345   and
+                C4   = 54321   and
+                C5   = 12121   and
+                C6   = 1.345   and
+                C7   = 'N'   and
+                C8   = 100 ns   and
+                C9   = "AAAAAAAA"   and
+                C10   = "11111111"   ) 
+      report "***FAILED TEST: c04s03b01x02p02n01i00064 - Syntactic test for signal assignment failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p02n01i00064arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc640.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc640.vhd
new file mode 100644
index 0000000..a0a8a35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc640.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc640.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:51 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00640ent IS
+END c03s04b01x00p01n01i00640ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00640arch OF c03s04b01x00p01n01i00640ent IS
+
+  subtype      word   is bit_vector(0 to 15);
+  constant   size   : integer := 7;
+  type   primary_memory   is array(0 to size) of word;
+  type    primary_memory_file    is file of primary_memory;
+  constant C38 : word := (others => '1');
+  constant C44 : primary_memory := (others => C38);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : primary_memory_file open write_mode is "iofile.42";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C44);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00640 - The output file will be verified by test s010286.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00640arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc641.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc641.vhd
new file mode 100644
index 0000000..bef8906
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc641.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc641.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:51 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:15 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:29 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00641ent IS
+END c03s04b01x00p01n01i00641ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00641arch OF c03s04b01x00p01n01i00641ent IS
+
+  subtype   word       is bit_vector(0 to 15);
+  constant   size   : integer := 7;
+  type    primary_memory  is array(0 to size) of word;
+  type    primary_memory_file     is file of primary_memory;
+  constant C38 : word := (others => '1');
+  constant C44 : primary_memory := (others => C38);
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : primary_memory_file open read_mode is "iofile.42";
+    variable  v    : primary_memory;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C44) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00641"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00641 - File reading operation (primary_memory file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00641arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc642.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc642.vhd
new file mode 100644
index 0000000..76291b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc642.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc642.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:52 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00642ent IS
+END c03s04b01x00p01n01i00642ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00642arch OF c03s04b01x00p01n01i00642ent IS
+
+  type      four_value    is ('Z','0','1','X');
+  subtype      binary      is four_value range '0' to '1';
+  subtype      word      is bit_vector(0 to 15);
+  constant   size      : integer := 7;
+  type      primary_memory   is array(0 to size) of word;
+
+  type    primary_memory_module is
+    record
+      enable      : binary;
+      memory_number   : primary_memory;
+    end record;
+  
+  type   whole_memory   is array (0 to size) of primary_memory_module;
+
+  type    whole_memory_file    is file of whole_memory;
+
+  constant C38 : word          := (others => '1');
+  constant C44 : primary_memory       := (others => C38);
+  constant C45 : primary_memory_module    := ('1',C44);
+  constant C46 : whole_memory      := (others => C45);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : whole_memory_file open write_mode is "iofile.44";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C46);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00642 - The output file will be verified by test s010290.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00642arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc643.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc643.vhd
new file mode 100644
index 0000000..9e1e40e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc643.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc643.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:52 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00643ent IS
+END c03s04b01x00p01n01i00643ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00643arch OF c03s04b01x00p01n01i00643ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       boolean_vector    is array (natural range <>) of boolean;
+  subtype    boolean_vector_range is boolean_vector(hi_to_low_range);
+
+  constant   C1 : boolean         := true;
+  constant   C2 : boolean_vector_range    := (others => C1);
+
+  type       boolean_vector_range_file is file of boolean_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : boolean_vector_range_file open write_mode is "iofile.46";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C2);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00643 - The output file will be verified by test s010298.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00643arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc644.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc644.vhd
new file mode 100644
index 0000000..7665345
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc644.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc644.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:52 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:16 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:30 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00644ent IS
+END c03s04b01x00p01n01i00644ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00644arch OF c03s04b01x00p01n01i00644ent IS
+
+  type            four_value    is ('Z','0','1','X');
+  subtype         binary          is four_value range '0' to '1';
+  subtype      word       is bit_vector(0 to 15);
+  constant   size      : integer := 7;
+  type       primary_memory  is array(0 to size) of word;
+
+  type    primary_memory_module is
+    record
+      enable          : binary;
+      memory_number   : primary_memory;
+    end record;
+
+  type    whole_memory    is array (0 to size) of primary_memory_module;
+
+  type      whole_memory_file     is file of whole_memory;
+
+  constant C38 : word          := (others => '1');
+  constant C44 : primary_memory       := (others => C38);
+  constant C45 : primary_memory_module    := ('1',C44);
+  constant C46 : whole_memory             := (others => C45);
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : whole_memory_file open read_mode is "iofile.44";
+    variable  v    : whole_memory;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C46) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00644"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00644 - File reading operation (whole_memory_file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00644arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc645.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc645.vhd
new file mode 100644
index 0000000..b65dba2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc645.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc645.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:52 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:17 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:30 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00645ent IS
+END c03s04b01x00p01n01i00645ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00645arch OF c03s04b01x00p01n01i00645ent IS
+  
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            boolean_vector  is array (natural range <>) of boolean;
+  subtype         boolean_vector_range is boolean_vector(hi_to_low_range);
+  
+  constant        C1 : boolean                    := true;
+  constant        C2 : boolean_vector_range       := (others => C1);
+  
+  type            boolean_vector_range_file is file of boolean_vector_range;
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : boolean_vector_range_file open read_mode is "iofile.46";
+    variable  v    : boolean_vector_range;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C2) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00645"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00645 - File reading operation (boolean_vector_range_file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00645arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc646.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc646.vhd
new file mode 100644
index 0000000..3e9c7c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc646.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+ENTITY c03s04b01x00p01n01i00646ent IS
+END c03s04b01x00p01n01i00646ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00646arch OF c03s04b01x00p01n01i00646ent IS
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+
+  type current_file is file of current;
+
+  constant C47 : current := 1 A;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : current_file open write_mode is "iofile.62";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C47);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00646 - The output file will be verified by test s010292.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00646arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc647.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc647.vhd
new file mode 100644
index 0000000..6e47b87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc647.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+ENTITY c03s04b01x00p01n01i00647ent IS
+END c03s04b01x00p01n01i00647ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00647arch OF c03s04b01x00p01n01i00647ent IS
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+
+  type current_file is file of current;
+  constant C47 : current := 1 A;
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : current_file open read_mode is "iofile.62";
+    variable  v    : current;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C47) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00647"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00647 - File reading operation (current_file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00647arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc648.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc648.vhd
new file mode 100644
index 0000000..fee7575
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc648.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc648.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:53 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00648ent IS
+END c03s04b01x00p01n01i00648ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00648arch OF c03s04b01x00p01n01i00648ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       severity_level_vector       is array (natural range <>) of severity_level;
+  subtype    severity_level_vector_range    is severity_level_vector(hi_to_low_range);
+  constant   C1 : severity_level_vector_range := (others => note);
+
+  type       severity_level_vector_range_file is file of severity_level_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_vector_range_file open write_mode is "iofile.01";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00648 - The output file will be verified by test s010102.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00648arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc649.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc649.vhd
new file mode 100644
index 0000000..85657a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc649.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+ENTITY c03s04b01x00p01n01i00649ent IS
+END c03s04b01x00p01n01i00649ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00649arch OF c03s04b01x00p01n01i00649ent IS
+
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm    = 1000 uOhm;
+      Ohm    = 1000 mOhm;
+      KOhm     = 1000 Ohm;
+    end units;
+
+  type resistance_file is file of resistance;
+
+  constant C47 : resistance := 1 Ohm;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : resistance_file open write_mode is "iofile.63";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C47);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00649 - The output file will be verified by test s010294.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00649arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc650.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc650.vhd
new file mode 100644
index 0000000..1d1ea35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc650.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+ENTITY c03s04b01x00p01n01i00650ent IS
+END c03s04b01x00p01n01i00650ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00650arch OF c03s04b01x00p01n01i00650ent IS
+
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm    = 1000 uOhm;
+      Ohm    = 1000 mOhm;
+      KOhm     = 1000 Ohm;
+    end units;
+
+  type resistance_file is file of resistance;
+  constant C47 : resistance := 1 Ohm;
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : resistance_file open read_mode is "iofile.63";
+    variable  v    : resistance;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C47) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00650"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00650 - File reading operation (resistance_file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00650arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc651.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc651.vhd
new file mode 100644
index 0000000..e62058f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc651.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc651.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:54 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:19 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:32 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00651ent IS
+END c03s04b01x00p01n01i00651ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00651arch OF c03s04b01x00p01n01i00651ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            severity_level_vector is array (natural range <>) of severity_level;       
+  subtype         severity_level_vector_range is severity_level_vector(hi_to_low_range);     
+  constant        C1 : severity_level_vector_range := (others => note);
+  
+  type            severity_level_vector_range_file is file of severity_level_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : severity_level_vector_range_file open read_mode is "iofile.01";
+    variable   v : severity_level_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00651"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00651 - File reading of severity_level_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00651arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc652.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc652.vhd
new file mode 100644
index 0000000..c8d538e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc652.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc652.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:54 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00652ent IS
+END c03s04b01x00p01n01i00652ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00652arch OF c03s04b01x00p01n01i00652ent IS
+
+  subtype   delay   is integer range 1 to 10;
+
+  type    delay_file is file of delay;
+
+  constant C47 : delay := 2;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : delay_file open write_mode is "iofile.45";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein, C47);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00652 - The output file will be verified by test s010296.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00652arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc653.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc653.vhd
new file mode 100644
index 0000000..e3366fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc653.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc653.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:54 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:20 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:33 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00653ent IS
+END c03s04b01x00p01n01i00653ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00653arch OF c03s04b01x00p01n01i00653ent IS
+
+  subtype   delay   is integer range 1 to 10;
+  
+  type    delay_file is file of delay;
+  constant C47 : delay := 2;
+
+  signal       k    : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : delay_file open read_mode is "iofile.45";
+    variable  v    : delay;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C47) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00653"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00653 - File reading operation (delay_file type) failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00653arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc654.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc654.vhd
new file mode 100644
index 0000000..6d1d0fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc654.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc654.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:54 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00654ent IS
+END c03s04b01x00p01n01i00654ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00654arch OF c03s04b01x00p01n01i00654ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       integer_vector is array (natural range <>) of integer;
+  subtype    integer_vector_range is integer_vector(hi_to_low_range);
+  constant   C1 : integer_vector_range := (others => 3);
+
+  type       integer_vector_range_file is file of integer_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_vector_range_file open write_mode is "iofile.03";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00654 - The output file will be verified by test s010104.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00654arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc655.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc655.vhd
new file mode 100644
index 0000000..ef01182
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc655.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc655.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:55 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:21 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:33 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00655ent IS
+END c03s04b01x00p01n01i00655ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00655arch OF c03s04b01x00p01n01i00655ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            integer_vector is array (natural range <>) of integer;       
+  subtype         integer_vector_range is integer_vector(hi_to_low_range);     
+  constant        C1 : integer_vector_range := (others => 3);
+  
+  type            integer_vector_range_file is file of integer_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : integer_vector_range_file open read_mode is "iofile.03";
+    variable   v : integer_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00655"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00655 - File reading of integer_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00655arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc656.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc656.vhd
new file mode 100644
index 0000000..9a61767
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc656.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc656.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:55 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00656ent IS
+END c03s04b01x00p01n01i00656ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00656arch OF c03s04b01x00p01n01i00656ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       real_vector is array (natural range <>) of real;
+  subtype    real_vector_range is real_vector(hi_to_low_range);
+  constant   C1 : real_vector_range := (others => 3.0);
+
+  type       real_vector_range_file is file of real_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : real_vector_range_file open write_mode is "iofile.05";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00656 - The output file will be verified by test s010106.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00656arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc657.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc657.vhd
new file mode 100644
index 0000000..3999acf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc657.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc657.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:55 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:22 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:34 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00657ent IS
+END c03s04b01x00p01n01i00657ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00657arch OF c03s04b01x00p01n01i00657ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            real_vector is array (natural range <>) of real;       
+  subtype         real_vector_range is real_vector(hi_to_low_range);     
+  constant        C1 : real_vector_range := (others => 3.0);
+  
+  type            real_vector_range_file is file of real_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : real_vector_range_file open read_mode is "iofile.05";
+    variable   v : real_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00657"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00657 - File reading of real_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00657arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc658.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc658.vhd
new file mode 100644
index 0000000..50a9894
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc658.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc658.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:55 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00658ent IS
+END c03s04b01x00p01n01i00658ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00658arch OF c03s04b01x00p01n01i00658ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       time_vector is array (natural range <>) of time;
+  subtype    time_vector_range is time_vector(hi_to_low_range);
+  constant   C1 : time_vector_range := (others => 3 ns);
+
+  type       time_vector_range_file is file of time_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : time_vector_range_file open write_mode is "iofile.07";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00658 - The output file will be verified by test s010108.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00658arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc659.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc659.vhd
new file mode 100644
index 0000000..d00b1e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc659.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc659.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:55 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:23 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:34 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00659ent IS
+END c03s04b01x00p01n01i00659ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00659arch OF c03s04b01x00p01n01i00659ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            time_vector is array (natural range <>) of time;       
+  subtype         time_vector_range is time_vector(hi_to_low_range);     
+  constant        C1 : time_vector_range := (others => 3 ns);
+  
+  type            time_vector_range_file is file of time_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : time_vector_range_file open read_mode is "iofile.07";
+    variable   v : time_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00659"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00659 - File reading of time_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00659arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc66.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc66.vhd
new file mode 100644
index 0000000..c06b86a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc66.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc66.vhd,v 1.2 2001-10-26 16:29:58 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p07n01i00066ent IS
+END c04s03b01x02p07n01i00066ent;
+
+ARCHITECTURE c04s03b01x02p07n01i00066arch OF c04s03b01x02p07n01i00066ent IS
+  signal C1 : Boolean   := true;  -- No_failure_here
+  signal C2 : bit       := '0';   -- No_failure_here
+  signal C3 : integer   := 123;   -- No_failure_here
+  signal C4 : positive  := 34;    -- No_failure_here
+  signal C5 : natural   := 12;    -- No_failure_here
+  signal C6 : real      := 1.20;  -- No_failure_here
+  signal C7 : character := 'C';   -- No_failure_here
+  signal C8 : time      := 0 ns;  -- No_failure_here
+  signal INDEX : INTEGER range 0 to 99 := 0; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(    C1   = true   and
+                   C2   = '0'   and
+                   C3   = 123   and
+                   C4   = 34   and
+                   C5   = 12   and
+                   C6   = 1.20   and
+                   C7   = 'C'   and
+                   C8   = 0 ns   and
+                   INDEX   = 0   )
+      report "***PASSED TEST: c04s03b01x02p07n01i00066"
+      severity NOTE;
+    assert (    C1   = true   and
+                C2   = '0'   and
+                C3   = 123   and
+                C4   = 34   and
+                C5   = 12   and
+                C6   = 1.20   and
+                C7   = 'C'   and
+                C8   = 0 ns   and
+                INDEX   = 0   )
+      report "***FAILED TEST: c04s03b01x02p07n01i00066 - Signal expression must be as the same type as the signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p07n01i00066arch;
+
+
+
+
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc660.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc660.vhd
new file mode 100644
index 0000000..1378b7e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc660.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc660.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:56 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00660ent IS
+END c03s04b01x00p01n01i00660ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00660arch OF c03s04b01x00p01n01i00660ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       natural_vector is array (natural range <>) of natural;
+  subtype    natural_vector_range is natural_vector(hi_to_low_range);
+  constant   C1 : natural_vector_range := (others => 3);
+
+  type       natural_vector_range_file is file of natural_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_vector_range_file open write_mode is "iofile.03";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00660 - The output file will be verified by test s010110.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00660arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc661.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc661.vhd
new file mode 100644
index 0000000..de13b12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc661.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc661.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:56 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:24 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:35 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00661ent IS
+END c03s04b01x00p01n01i00661ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00661arch OF c03s04b01x00p01n01i00661ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            natural_vector is array (natural range <>) of natural;       
+  subtype         natural_vector_range is natural_vector(hi_to_low_range);     
+  constant        C1 : natural_vector_range := (others => 3);
+  
+  type            natural_vector_range_file is file of natural_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : natural_vector_range_file open read_mode is "iofile.03";
+    variable   v : natural_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00661"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00661 - File reading of natural_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00661arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc662.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc662.vhd
new file mode 100644
index 0000000..f263220
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc662.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc662.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:56 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00662ent IS
+END c03s04b01x00p01n01i00662ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00662arch OF c03s04b01x00p01n01i00662ent IS
+
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 7;
+  subtype    hi_to_low_range is integer range low_number to hi_number;
+
+  type       positive_vector is array (natural range <>) of positive;
+  subtype    positive_vector_range is positive_vector(hi_to_low_range);
+  constant   C1 : positive_vector_range := (others => 3);
+
+  type       positive_vector_range_file is file of positive_vector_range;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_vector_range_file open write_mode is "iofile.03";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C1);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00662 - The output file will be verified by test s010112.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00662arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc663.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc663.vhd
new file mode 100644
index 0000000..53242ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc663.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc663.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:56 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:25 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:35 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00663ent IS
+END c03s04b01x00p01n01i00663ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00663arch OF c03s04b01x00p01n01i00663ent IS
+
+  constant        low_number      : integer := 0;
+  constant        hi_number       : integer := 7;
+  subtype         hi_to_low_range is integer range low_number to hi_number;
+  
+  type            positive_vector is array (natural range <>) of positive;       
+  subtype         positive_vector_range is positive_vector(hi_to_low_range);     
+  constant        C1 : positive_vector_range := (others => 3);
+  
+  type            positive_vector_range_file is file of positive_vector_range;
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein : positive_vector_range_file open read_mode is "iofile.03";
+    variable   v : positive_vector_range := C1;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v);
+      if (v /= C1) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00663"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00663 - File reading of positive_vector_range_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00663arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc664.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc664.vhd
new file mode 100644
index 0000000..1e66d8e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc664.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc664.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:57 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00664ent IS
+END c03s04b01x00p01n01i00664ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00664arch OF c03s04b01x00p01n01i00664ent IS
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type    array_rec_std       is array (integer range <>) of record_std_package;
+  type    array_rec_std_file    is file of array_rec_std;
+
+  constant   C26 : record_std_package    := (true,'1','s',note,3,3.0,3 ns,3,3);
+  constant   C57 : array_rec_std(0 to 7)    := (others => C26);
+
+BEGIN
+  TESTING: PROCESS
+    file filein : array_rec_std_file open write_mode is "iofile.11";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C57);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00664 - The output file will be verified by test s010114.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00664arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc665.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc665.vhd
new file mode 100644
index 0000000..07d5594
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc665.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc665.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:57 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:25 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:36 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00665ent IS
+END c03s04b01x00p01n01i00665ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00665arch OF c03s04b01x00p01n01i00665ent IS
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  type    array_rec_std           is array (integer range <>) of record_std_package;
+  type    array_rec_std_file      is file of array_rec_std;
+  
+  constant        C26 : record_std_package        := (true,'1','s',note,3,3.0,3 ns,3,3);     
+  constant        C57 : array_rec_std(0 to 7)     := (others => C26);
+
+  signal     k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    file filein    : array_rec_std_file open read_mode is "iofile.11";
+    variable   v    : array_rec_std(0 to 7);
+    variable   len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 8) report "wrong length passed during read operation";
+      if (v /= C57) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00665"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00665 - File reading of array_rec_std_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00665arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc666.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc666.vhd
new file mode 100644
index 0000000..b4d524c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc666.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc666.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:57 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00666ent IS
+END c03s04b01x00p01n01i00666ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00666arch OF c03s04b01x00p01n01i00666ent IS
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+
+  constant C1 : boolean    := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 3;
+  constant C9 : positive    := 3;
+
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+
+  constant C27 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+
+  constant C58 : array_rec_cons (0 to 7)    := (others => C27);
+
+  type    array_rec_cons_file    is file of array_rec_cons;
+
+BEGIN
+  TESTING: PROCESS
+    file filein : array_rec_cons_file open write_mode is "iofile.13";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C58);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00666 - The output file will be verified by test s010116.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00666arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc667.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc667.vhd
new file mode 100644
index 0000000..6f49dff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc667.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc667.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:57 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:26 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:36 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00667ent IS
+END c03s04b01x00p01n01i00667ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00667arch OF c03s04b01x00p01n01i00667ent IS
+
+  type boolean_cons_vector        is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector        is array (15 downto 0) of integer;
+  type real_cons_vector           is array (15 downto 0) of real;
+  type time_cons_vector           is array (15 downto 0) of time;
+  type natural_cons_vector        is array (15 downto 0) of natural;
+  type positive_cons_vector       is array (15 downto 0) of positive;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  
+  constant C1 : boolean   := true;
+  constant C4 : severity_level    := note;
+  constant C5 : integer   := 3;
+  constant C6 : real      := 3.0;
+  constant C7 : time      := 3 ns;
+  constant C8 : natural   := 3;
+  constant C9 : positive  := 3;
+  
+  constant C19 : boolean_cons_vector      := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector      := (others => C5);
+  constant C22 : real_cons_vector         := (others => C6);
+  constant C23 : time_cons_vector         := (others => C7);
+  constant C24 : natural_cons_vector      := (others => C8);
+  constant C25 : positive_cons_vector     := (others => C9);
+  
+  constant C27 : record_cons_array        := (C19,C20,C21,C22,C23,C24,C25);
+  
+  constant C58 : array_rec_cons (0 to 7)  := (others => C27);
+  
+  type    array_rec_cons_file     is file of array_rec_cons;
+
+  signal     k : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : array_rec_cons_file open read_mode is "iofile.13";
+    variable   v    : array_rec_cons(0 to 7);
+    variable   len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 8) report "wrong length passed during read operation";
+      if (v /= C58) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00667"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00667 - File reading of array_rec_cons_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00667arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc668.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc668.vhd
new file mode 100644
index 0000000..f0b47d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc668.vhd
@@ -0,0 +1,160 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc668.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:57 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00668ent IS
+END c03s04b01x00p01n01i00668ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00668arch OF c03s04b01x00p01n01i00668ent IS
+
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector       is array (15 downto 0) of real;
+  type time_cons_vector       is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              i: record_array_st;
+                            end record;
+
+  type    array_rec_rec       is array (integer range <>) of record_of_records;
+  type    array_rec_rec_file    is file of array_rec_rec;
+
+  constant C1 : boolean       := true;
+  constant C2 : bit       := '1';
+  constant C3 : character    := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer       := 3;
+  constant C6 : real       := 3.0;
+  constant C7 : time       := 3 ns;
+  constant C8 : natural       := 3;
+  constant C9 : positive       := 3;
+  constant C10 : string       := "shishir";
+  constant C11 : bit_vector       := B"0011";
+  constant C12 : boolean_vector       := (true,false);
+  constant C13 : severity_level_vector    := (note,error);
+  constant C14 : integer_vector       := (1,2,3,4);
+  constant C15 : real_vector       := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector       := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector       := (1,2,3,4);
+  constant C18 : positive_vector       := (1,2,3,4);
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    := (others => C7);
+  constant C24 : natural_cons_vector    := (others => C8);
+  constant C25 : positive_cons_vector    := (others => C9);
+  constant C26 : record_std_package    := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C27 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+  constant C28 : boolean_vector_st    := (others => C1);
+  constant C29 : severity_level_vector_st   := (others => C4);
+  constant C30 : integer_vector_st   := (others => C5);
+  constant C31 : real_vector_st      := (others => C6);
+  constant C32 : time_vector_st      := (others => C7);
+  constant C33 : natural_vector_st   := (others => C8);
+  constant C34 : positive_vector_st   := (others => C9);
+  constant C35 : record_array_st       := (C28,C29,C30,C31,C32,C33,C34);
+
+  constant C37 : record_of_records    := (C26,C27,C35);
+
+  constant C59: array_rec_rec(0 to 7)    :=(others => C37);
+BEGIN
+  TESTING: PROCESS
+    file filein : array_rec_rec_file open write_mode is "iofile.15";
+  BEGIN
+    for i in 1 to 100 loop
+      write(filein,C59);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p01n01i00668 - The output file will be verified by test s010118.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00668arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc669.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc669.vhd
new file mode 100644
index 0000000..8b6fba0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc669.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc669.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:58 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:27 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:37 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p01n01i00669ent IS
+END c03s04b01x00p01n01i00669ent;
+
+ARCHITECTURE c03s04b01x00p01n01i00669arch OF c03s04b01x00p01n01i00669ent IS
+
+  type boolean_vector     is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector     is array (natural range <>) of integer;
+  type real_vector        is array (natural range <>) of real;
+  type time_vector        is array (natural range <>) of time;
+  type natural_vector     is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  
+  subtype boolean_vector_st       is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st          is  real_vector(0 to 15);
+  subtype time_vector_st          is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st      is  positive_vector(0 to 15);
+  
+  type boolean_cons_vector        is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector        is array (15 downto 0) of integer;
+  type real_cons_vector           is array (15 downto 0) of real;
+  type time_cons_vector           is array (15 downto 0) of time;
+  type natural_cons_vector        is array (15 downto 0) of natural;
+  type positive_cons_vector       is array (15 downto 0) of positive;
+  
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              i: record_array_st;
+                            end record;
+  
+  type    array_rec_rec           is array (integer range <>) of record_of_records;
+  type    array_rec_rec_file      is file of array_rec_rec;
+  
+  constant C1 : boolean           := true;
+  constant C2 : bit               := '1';
+  constant C3 : character         := 's';
+  constant C4 : severity_level    := note;
+  constant C5 : integer           := 3;
+  constant C6 : real              := 3.0;
+  constant C7 : time              := 3 ns;
+  constant C8 : natural           := 3;
+  constant C9 : positive          := 3;
+  constant C10 : string           := "shishir";
+  constant C11 : bit_vector               := B"0011";
+  constant C12 : boolean_vector           := (true,false);
+  constant C13 : severity_level_vector    := (note,error);
+  constant C14 : integer_vector           := (1,2,3,4);
+  constant C15 : real_vector              := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector              := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector           := (1,2,3,4);
+  constant C18 : positive_vector          := (1,2,3,4);
+  constant C19 : boolean_cons_vector      := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector      := (others => C5);
+  constant C22 : real_cons_vector         := (others => C6);
+  constant C23 : time_cons_vector         := (others => C7);
+  constant C24 : natural_cons_vector      := (others => C8);
+  constant C25 : positive_cons_vector     := (others => C9);
+  constant C26 : record_std_package       := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C27 : record_cons_array        := (C19,C20,C21,C22,C23,C24,C25);
+  constant C28 : boolean_vector_st        := (others => C1);
+  constant C29 : severity_level_vector_st := (others => C4);
+  constant C30 : integer_vector_st        := (others => C5);
+  constant C31 : real_vector_st           := (others => C6);
+  constant C32 : time_vector_st           := (others => C7);
+  constant C33 : natural_vector_st        := (others => C8);
+  constant C34 : positive_vector_st       := (others => C9);
+  constant C35 : record_array_st          := (C28,C29,C30,C31,C32,C33,C34);
+  
+  constant C37 : record_of_records        := (C26,C27,C35);
+  
+  constant C59: array_rec_rec(0 to 7)     :=(others => C37);
+
+  signal     k : integer := 0;
+
+BEGIN
+  TESTING: PROCESS
+    file filein    : array_rec_rec_file open read_mode is "iofile.15";
+    variable   v    : array_rec_rec(0 to 7);
+    variable   len   : natural;
+  BEGIN
+    for i in 1 to 100 loop
+      assert(endfile(filein) = false) report"end of file reached before expected";
+      read(filein,v,len);
+      assert(len = 8) report "wrong length passed during read operation";
+      if (v /= C59) then
+        k <= 1;
+      end if;
+    end loop;
+    wait for 1 ns;
+    assert NOT(k = 0)
+      report "***PASSED TEST: c03s04b01x00p01n01i00669"
+      severity NOTE;
+    assert (k = 0)
+      report "***FAILED TEST: c03s04b01x00p01n01i00669 - File reading of array_rec_rec_file operation failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p01n01i00669arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc670.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc670.vhd
new file mode 100644
index 0000000..adb3cd0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc670.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc670.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:58 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00670ent IS
+END c03s04b01x00p23n01i00670ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00670arch OF c03s04b01x00p23n01i00670ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type       SWITCH_LEVEL is ('0', '1', 'X');
+    type       FT is file of SWITCH_LEVEL;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.48";
+
+    -- Declare a variable.
+    constant CON : SWITCH_LEVEL := '1';
+    variable VAR : SWITCH_LEVEL := CON;
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00670 - The output file will tested by test file s010404.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00670arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc671.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc671.vhd
new file mode 100644
index 0000000..59fcee3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc671.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc671.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:58 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00671ent IS
+END c03s04b01x00p23n01i00671ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00671arch OF c03s04b01x00p23n01i00671ent IS
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    type FT is file of DATE;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.51";
+
+    -- Declare a variable.
+    constant CON : DATE := (1,1,1);
+    variable VAR : DATE := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00671 - The output file will tested by test file s010410.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00671arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc672.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc672.vhd
new file mode 100644
index 0000000..b65a2e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc672.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc672.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:58 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:29 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:38 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00672ent IS
+END c03s04b01x00p23n01i00672ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00672arch OF c03s04b01x00p23n01i00672ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type       SWITCH_LEVEL is ('0', '1', 'X');
+    type       FT is file of SWITCH_LEVEL;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.48";
+    
+    -- Declare a variable into which we will read.
+    constant CON : SWITCH_LEVEL := '1';
+    variable VAR : SWITCH_LEVEL ;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00672"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00672 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00672arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc673.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc673.vhd
new file mode 100644
index 0000000..8137829
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc673.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc673.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:59 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:29 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:38 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00673ent IS
+END c03s04b01x00p23n01i00673ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00673arch OF c03s04b01x00p23n01i00673ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    type FT is file of DATE;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.51";
+    
+    -- Declare a variable into which we will read.
+    constant CON : DATE := ( 1,1,1 );
+    variable VAR : DATE;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00673"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00673 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00673arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc674.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc674.vhd
new file mode 100644
index 0000000..8301784
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc674.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc674.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:59 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00674ent IS
+END c03s04b01x00p23n01i00674ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00674arch OF c03s04b01x00p23n01i00674ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type SWITCH_LEVEL is ( '0', '1', 'Z' );
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    type    FT is file of LOGIC_SWITCH;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.49";
+
+    -- Declare a variable.
+    constant CON : LOGIC_SWITCH := '1';
+    variable VAR : LOGIC_SWITCH := CON;
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00674 - The output file will tested by test file s010406.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00674arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc675.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc675.vhd
new file mode 100644
index 0000000..0c6dbeb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc675.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc675.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:59 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:30 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:38 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00675ent IS
+END c03s04b01x00p23n01i00675ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00675arch OF c03s04b01x00p23n01i00675ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type SWITCH_LEVEL is ( '0', '1', 'Z' );
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    type    FT is file of LOGIC_SWITCH;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.49";
+    
+    -- Declare a variable into which we will read.
+    constant CON : LOGIC_SWITCH := '1';
+    variable VAR : LOGIC_SWITCH ;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00675"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00675 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00675arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc676.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc676.vhd
new file mode 100644
index 0000000..de22af7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc676.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc676.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:59 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00676ent IS
+END c03s04b01x00p23n01i00676ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00676arch OF c03s04b01x00p23n01i00676ent IS
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    type FT is file of POSITIVE_R;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.54";
+
+    -- Declare a variable.
+    constant CON : POSITIVE_R := 1.0;
+    variable VAR : POSITIVE_R := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00676 - The output file will tested by test file s010422.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00676arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc677.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc677.vhd
new file mode 100644
index 0000000..5f12a7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc677.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc677.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:37:59 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00677ent IS
+END c03s04b01x00p23n01i00677ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00677arch OF c03s04b01x00p23n01i00677ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type WORD   is array(0 to 31) of BIT;
+    type    FT is file of WORD;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.50";
+
+    -- Declare a variable.
+    constant CON : WORD := B"11111111111111111111111111111111";
+    variable VAR : WORD := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00677 - The output file will tested by test file s010408.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00677arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc678.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc678.vhd
new file mode 100644
index 0000000..8c47c52
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc678.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc678.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:00 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:31 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:39 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00678ent IS
+END c03s04b01x00p23n01i00678ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00678arch OF c03s04b01x00p23n01i00678ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type WORD   is array(0 to 31) of BIT;
+    type    FT is file of WORD;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.50";
+    
+    -- Declare a variable into which we will read.
+    constant CON : WORD := B"11111111111111111111111111111111";
+    variable VAR : WORD;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00678"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00678 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00678arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc679.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc679.vhd
new file mode 100644
index 0000000..e93b2e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc679.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc679.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:00 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00679ent IS
+END c03s04b01x00p23n01i00679ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00679arch OF c03s04b01x00p23n01i00679ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of INTEGER;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.08";
+
+    -- Declare a variable.
+    constant CON : INTEGER := 1;
+    variable VAR : INTEGER := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00679 - The output file will tested by test file s010412.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00679arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc68.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc68.vhd
new file mode 100644
index 0000000..cae1740
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc68.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc68.vhd,v 1.2 2001-10-26 16:29:58 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p07n04i00068ent IS
+END c04s03b01x02p07n04i00068ent;
+
+ARCHITECTURE c04s03b01x02p07n04i00068arch OF c04s03b01x02p07n04i00068ent IS
+  signal S1 : Integer := (10 *2 *4 +9 -3);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT( S1 = 86 )
+      report "***PASSED TEST: c04s03b01x02p07n04i00068"
+      severity NOTE;
+    assert ( S1 = 86 )
+      report "***FAILED TEST: c04s03b01x02p07n04i00068 - The value of the default expression is the default value of the signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p07n04i00068arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc680.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc680.vhd
new file mode 100644
index 0000000..92708f0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc680.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc680.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:00 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:32 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:40 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00680ent IS
+END c03s04b01x00p23n01i00680ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00680arch OF c03s04b01x00p23n01i00680ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of INTEGER;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.08";
+    
+    -- Declare a variable into which we will read.
+    constant CON : INTEGER := 1;
+    variable VAR : INTEGER;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00680"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00680 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00680arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc681.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc681.vhd
new file mode 100644
index 0000000..2527301
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc681.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc681.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:01 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00681ent IS
+END c03s04b01x00p23n01i00681ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00681arch OF c03s04b01x00p23n01i00681ent IS
+
+  type FT is file of INTEGER;
+BEGIN
+  TESTING: PROCESS
+    file S1: FT open write_mode is "iofile.47";   
+  BEGIN
+    WRITE(S1,3);
+    WRITE(S1,2);
+    WRITE(S1,1);
+    wait for 10 ns;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00681 - The output file will tested by test file s010402.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00681arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc682.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc682.vhd
new file mode 100644
index 0000000..3664b1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc682.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc682.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:01 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:33 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:40 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00682ent IS
+END c03s04b01x00p23n01i00682ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00682arch OF c03s04b01x00p23n01i00682ent IS
+  type FT is file of INTEGER;
+BEGIN
+  TESTING: PROCESS
+    variable i3, i2, i1: INTEGER;
+    file S1: FT open read_mode is "iofile.47";
+  BEGIN
+    wait for 10 ns;
+    READ(S1,i3);
+    READ(S1,i2);
+    READ(S1,i1);
+    wait for 10 ns;
+    assert NOT( (i3 = 3) and (i2 = 2) and (i1 = 1) )
+      report "***PASSED TEST: c03s04b01x00p23n01i00682"
+      severity NOTE;
+    assert ( (i3 = 3) and (i2 = 2) and (i1 = 1) )
+      report "***FAILED TEST: c03s04b01x00p23n01i00682 - Procedure READ retrieves the next value from a file."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00682arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc683.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc683.vhd
new file mode 100644
index 0000000..38632f5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc683.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc683.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:01 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:33 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:40 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00683ent IS
+END c03s04b01x00p23n01i00683ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00683arch OF c03s04b01x00p23n01i00683ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    type FT is file of POSITIVE_R;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.54";
+    
+    -- Declare a variable into which we will read.
+    constant CON : POSITIVE_R := 1.0;
+    variable VAR : POSITIVE_R;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00683"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00683 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00683arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc684.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc684.vhd
new file mode 100644
index 0000000..b8ce797
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc684.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc684.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00684ent IS
+END c03s04b01x00p23n01i00684ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00684arch OF c03s04b01x00p23n01i00684ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    type FT is file of POSITIVE;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.08";
+
+    -- Declare a variable.
+    constant CON : POSITIVE := 1;
+    variable VAR : POSITIVE := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00684 - The output file will tested by test file s010414.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00684arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc685.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc685.vhd
new file mode 100644
index 0000000..5cba64d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc685.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc685.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:02 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:34 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:41 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00685ent IS
+END c03s04b01x00p23n01i00685ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00685arch OF c03s04b01x00p23n01i00685ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    type FT is file of POSITIVE;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.08";
+    
+    -- Declare a variable into which we will read.
+    constant CON : POSITIVE := 1;
+    variable VAR : POSITIVE;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00685"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00685 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00685arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc686.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc686.vhd
new file mode 100644
index 0000000..237ac8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc686.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc686.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:02 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00686ent IS
+END c03s04b01x00p23n01i00686ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00686arch OF c03s04b01x00p23n01i00686ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of BOOLEAN;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.10";
+
+    -- Declare a variable.
+    constant CON : BOOLEAN := TRUE;
+    variable VAR : BOOLEAN := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00686 - The output file will tested by test file s010428.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00686arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc687.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc687.vhd
new file mode 100644
index 0000000..3a02212
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc687.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc687.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00687ent IS
+END c03s04b01x00p23n01i00687ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00687arch OF c03s04b01x00p23n01i00687ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of TIME;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.52";
+
+    -- Declare a variable.
+    constant CON : TIME := 1 ns;
+    variable VAR : TIME := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00687 - The output file will tested by test file s010416.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00687arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc688.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc688.vhd
new file mode 100644
index 0000000..33c1810
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc688.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc688.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:03 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:35 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:42 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00688ent IS
+END c03s04b01x00p23n01i00688ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00688arch OF c03s04b01x00p23n01i00688ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of TIME;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.52";
+    
+    -- Declare a variable into which we will read.
+    constant CON : TIME := 1 ns;
+    variable VAR : TIME;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00688"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00688 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00688arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc689.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc689.vhd
new file mode 100644
index 0000000..0ab97a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc689.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc689.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00689ent IS
+END c03s04b01x00p23n01i00689ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00689arch OF c03s04b01x00p23n01i00689ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of BIT;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.08";
+
+    -- Declare a variable.
+    constant CON : BIT := '1';
+    variable VAR : BIT := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00689 - The output file will tested by test file s010424.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00689arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc69.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc69.vhd
new file mode 100644
index 0000000..08ccfeb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc69.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc69.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p07n05i00069ent IS
+END c04s03b01x02p07n05i00069ent;
+
+ARCHITECTURE c04s03b01x02p07n05i00069arch OF c04s03b01x02p07n05i00069ent IS
+  signal S1 : BIT_VECTOR(0 to 3) := ("0101" and "0101");
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(    S1(0)   = '0'   and
+                   S1(1)   = '1'   and
+                   S1(2)   = '0'   and
+                   S1(3)   = '1'   )
+      report "***PASSED TEST: c04s03b01x02p07n05i00069"
+      severity NOTE;
+    assert (    S1(0)   = '0'   and
+                S1(1)   = '1'   and
+                S1(2)   = '0'   and
+                S1(3)   = '1'   )
+      report "***FAILED TEST: c04s03b01x02p07n05i00069 - Each subelement of the value of the composite subtype is the default value of the corresponding subelement of the signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p07n05i00069arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc690.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc690.vhd
new file mode 100644
index 0000000..2b93ec7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc690.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc690.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:03 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00690ent IS
+END c03s04b01x00p23n01i00690ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00690arch OF c03s04b01x00p23n01i00690ent IS
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+    type FilT is file of DISTANCE;
+
+    -- Declare the actual file to write.
+    file FILEV : FilT open write_mode is "iofile.53";
+
+    -- Declare a variable.
+    constant CON : DISTANCE := 1 nm;
+    variable VAR : DISTANCE := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00690 - The output file will tested by test file s010418.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00690arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc691.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc691.vhd
new file mode 100644
index 0000000..678a323
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc691.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc691.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:04 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:37 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:42 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00691ent IS
+END c03s04b01x00p23n01i00691ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00691arch OF c03s04b01x00p23n01i00691ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+    type FilT is file of DISTANCE;
+    
+    -- Declare the actual file to read.
+    file FILEV : FilT open read_mode is "iofile.53";
+    
+    -- Declare a variable into which we will read.
+    constant CON : DISTANCE := 1 nm;
+    variable VAR : DISTANCE;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00691"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00691 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00691arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc692.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc692.vhd
new file mode 100644
index 0000000..4aac090
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc692.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc692.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:04 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:38 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:43 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00692ent IS
+END c03s04b01x00p23n01i00692ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00692arch OF c03s04b01x00p23n01i00692ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of BIT;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.08";
+    
+    -- Declare a variable into which we will read.
+    constant CON : BIT := '1';
+    variable VAR : BIT;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00692"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00692 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00692arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc693.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc693.vhd
new file mode 100644
index 0000000..783df55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc693.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc693.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:04 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:38 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:43 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00693ent IS
+END c03s04b01x00p23n01i00693ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00693arch OF c03s04b01x00p23n01i00693ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of REAL;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.54";
+    
+    -- Declare a variable into which we will read.
+    constant CON : REAL := 1.0;
+    variable VAR : REAL;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00693"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00693 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00693arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc694.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc694.vhd
new file mode 100644
index 0000000..063545c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc694.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc694.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00694ent IS
+END c03s04b01x00p23n01i00694ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00694arch OF c03s04b01x00p23n01i00694ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of REAL;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.54";
+
+    -- Declare a variable.
+    constant CON : REAL := 1.0;
+    variable VAR : REAL := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00694 - The output file will tested by test file s010420.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00694arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc695.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc695.vhd
new file mode 100644
index 0000000..0701828
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc695.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc695.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:05 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:39 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:43 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00695ent IS
+END c03s04b01x00p23n01i00695ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00695arch OF c03s04b01x00p23n01i00695ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of BOOLEAN;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.10";
+    
+    -- Declare a variable into which we will read.
+    constant CON : BOOLEAN := TRUE;
+    variable VAR : BOOLEAN;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00695"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00695 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00695arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc696.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc696.vhd
new file mode 100644
index 0000000..9bb52ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc696.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc696.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:05 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:39 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:44 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00696ent IS
+END c03s04b01x00p23n01i00696ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00696arch OF c03s04b01x00p23n01i00696ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of SEVERITY_LEVEL;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.55";
+    
+    -- Declare a variable into which we will read.
+    constant CON : SEVERITY_LEVEL := WARNING;
+    variable VAR : SEVERITY_LEVEL;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00696"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00696 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00696arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc697.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc697.vhd
new file mode 100644
index 0000000..5a0760e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc697.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc697.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:05 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00697ent IS
+END c03s04b01x00p23n01i00697ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00697arch OF c03s04b01x00p23n01i00697ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of SEVERITY_LEVEL;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.55";
+
+    -- Declare a variable.
+    constant CON : SEVERITY_LEVEL := WARNING;
+    variable VAR : SEVERITY_LEVEL := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00697 - The output file will tested by test file s010426.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00697arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc698.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc698.vhd
new file mode 100644
index 0000000..f796267
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc698.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc698.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00698ent IS
+END c03s04b01x00p23n01i00698ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00698arch OF c03s04b01x00p23n01i00698ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of CHARACTER;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.08";
+
+    -- Declare a variable.
+    constant CON : CHARACTER := '1';
+    variable VAR : CHARACTER := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00698 - The output file will tested by test file s010430.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00698arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc699.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc699.vhd
new file mode 100644
index 0000000..8afad7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc699.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc699.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:06 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:40 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:44 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00699ent IS
+END c03s04b01x00p23n01i00699ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00699arch OF c03s04b01x00p23n01i00699ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of CHARACTER;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.08";
+    
+    -- Declare a variable into which we will read.
+    constant CON : CHARACTER := '1';
+    variable VAR : CHARACTER;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00699"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00699 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00699arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc70.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc70.vhd
new file mode 100644
index 0000000..5723753
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc70.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc70.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p08n02i00070ent IS
+END c04s03b01x02p08n02i00070ent;
+
+ARCHITECTURE c04s03b01x02p08n02i00070arch OF c04s03b01x02p08n02i00070ent IS
+  type    A is array (1 to 10) of integer;
+  subtype    B is integer range a'range;
+  signal    c :  b;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT( c=1 )
+      report "***PASSED TEST:c04s03b01x02p08n02i00070"
+      severity NOTE;
+    assert ( c=1 )
+      report "***FAILED TEST:c04s03b01x02p08n02i00070 - Implicit default value test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p08n02i00070arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc700.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc700.vhd
new file mode 100644
index 0000000..9c26e42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc700.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc700.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:06 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00700ent IS
+END c03s04b01x00p23n01i00700ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00700arch OF c03s04b01x00p23n01i00700ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of NATURAL;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.08";
+
+    -- Declare a variable.
+    constant CON : NATURAL := 1;
+    variable VAR : NATURAL := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00700 - The output file will tested by test file s010432.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00700arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc701.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc701.vhd
new file mode 100644
index 0000000..7622968
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc701.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc701.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:07 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:41 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:45 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00701ent IS
+END c03s04b01x00p23n01i00701ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00701arch OF c03s04b01x00p23n01i00701ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    type FT is file of NATURAL;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.08";
+    
+    -- Declare a variable into which we will read.
+    constant CON : NATURAL := 1;
+    variable VAR : NATURAL;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00701"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00701 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00701arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc702.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc702.vhd
new file mode 100644
index 0000000..a5a0d9d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc702.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc702.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:07 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00702ent IS
+END c03s04b01x00p23n01i00702ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00702arch OF c03s04b01x00p23n01i00702ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    subtype STRING12 is STRING( 1 to 12 );
+    type FT is file of STRING12;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.56";
+
+    -- Declare a variable.
+    constant CON : STRING12 := "hello, world";
+    variable VAR : STRING12 := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00702 - The output file will tested by test file s010434.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00702arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc703.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc703.vhd
new file mode 100644
index 0000000..2e1ea8e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc703.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc703.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:07 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:42 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:45 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00703ent IS
+END c03s04b01x00p23n01i00703ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00703arch OF c03s04b01x00p23n01i00703ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    subtype STRING12 is STRING( 1 to 12 );
+    type FT is file of STRING12;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.56";
+    
+    -- Declare a variable into which we will read.
+    constant CON : STRING12 := "hello, world";
+    variable VAR : STRING12;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00703"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00703 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00703arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc704.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc704.vhd
new file mode 100644
index 0000000..80b6267
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc704.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc704.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:07 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00704ent IS
+END c03s04b01x00p23n01i00704ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00704arch OF c03s04b01x00p23n01i00704ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    subtype BIT_VECTOR5 is BIT_VECTOR( 1 to 5 );
+    type FT is file of BIT_VECTOR5;
+
+    -- Declare the actual file to write.
+    file FILEV : FT open write_mode is "iofile.57";
+
+    -- Declare a variable.
+    constant CON : BIT_VECTOR5 := B"10101";
+    variable VAR : BIT_VECTOR5 := CON;
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00704 - The output file will tested by test file s010436.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00704arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc705.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc705.vhd
new file mode 100644
index 0000000..a648909
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc705.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc705.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:08 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:43 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:46 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00705ent IS
+END c03s04b01x00p23n01i00705ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00705arch OF c03s04b01x00p23n01i00705ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the type and the file.
+    subtype BIT_VECTOR5 is BIT_VECTOR( 1 to 5 );
+    type FT is file of BIT_VECTOR5;
+    
+    -- Declare the actual file to read.
+    file FILEV : FT open read_mode is "iofile.57";
+    
+    -- Declare a variable into which we will read.
+    constant CON : BIT_VECTOR5 := B"10101";
+    variable VAR : BIT_VECTOR5;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00705"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00705 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00705arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc706.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc706.vhd
new file mode 100644
index 0000000..6c67dab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc706.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc706.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:08 1996  --
+--                 ****************************               --
+
+
+
+package c03s04b01x00p23n01i00706pkg is
+
+  type Waveform_element is record
+                             Value:     Bit;
+                             At:        Time;
+                           end record;
+  
+  type Signal_history is file of Waveform_element;
+
+end c03s04b01x00p23n01i00706pkg;
+
+use work.c03s04b01x00p23n01i00706pkg.all;
+ENTITY c03s04b01x00p23n01i00706ent IS
+END c03s04b01x00p23n01i00706ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00706arch OF c03s04b01x00p23n01i00706ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV : Signal_history open write_mode is "iofile.58";
+
+    -- Declare a variable.
+    variable VAR : Waveform_element    := ('1',10 ns);
+
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 100 loop
+      WRITE( FILEV,VAR );
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00706 - The output file will tested by test file s010438.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00706arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc707.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc707.vhd
new file mode 100644
index 0000000..3274e47
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc707.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc707.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:08 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:44 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:46 1996  --
+--                 ****************************               --
+
+
+package c03s04b01x00p23n01i00707pkg is
+
+  type Waveform_element is record
+                             Value:     Bit;
+                             At:        Time;
+                           end record;
+  
+  type Signal_history is file of Waveform_element;
+
+end c03s04b01x00p23n01i00707pkg;
+
+use work.c03s04b01x00p23n01i00707pkg.all;
+ENTITY c03s04b01x00p23n01i00707ent IS
+END c03s04b01x00p23n01i00707ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00707arch OF c03s04b01x00p23n01i00707ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to read.
+    file FILEV : Signal_history open read_mode is "iofile.58";
+    
+    -- Declare a variable into which we will read.
+    constant con : Waveform_element := ('1',10 ns);
+    variable VAR : Waveform_element;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to 100 loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if (VAR /= CON) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00707"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00707 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00707arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc708.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc708.vhd
new file mode 100644
index 0000000..39cd65a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc708.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc708.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:08 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00708ent IS
+END c03s04b01x00p23n01i00708ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00708arch OF c03s04b01x00p23n01i00708ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  -- Types...;
+  subtype STR16 is STRING (1 to StringLength);
+  type t1 is record
+               number:      NATURAL;
+               string:      STR16;
+             end record;
+
+  type string_table is array (1 to NumOfStrings) of STR16;
+  
+  -- Objects...
+  constant string_array: string_table :=
+    ( "This is string 1"
+      ,"__Hello  World__"
+      ,"This is string " & "3"
+      ,"_Bird is a word_"
+      ,"_Goodbye (ciao)_"
+      );
+
+  type ft1 is file of t1;
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV : ft1 open write_mode is "iofile.59";
+
+    -- Declare a variable.
+    variable VAR : t1;
+  BEGIN
+    -- Write out the file.
+    for I in 1 to NumOfStrings  loop
+      VAR.number := i;
+      VAR.string := string_array(i);
+      write(FILEV, VAR);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00708 - The output file will tested by test file s010440.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00708arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc709.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc709.vhd
new file mode 100644
index 0000000..b5f0d39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc709.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc709.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:09 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:45 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:47 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p23n01i00709ent IS
+END c03s04b01x00p23n01i00709ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00709arch OF c03s04b01x00p23n01i00709ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  -- Types...;
+  subtype STR16 is STRING (1 to StringLength);
+  type t1 is record
+               number:      NATURAL;
+               string:      STR16;
+             end record;
+  type string_table is array (1 to NumOfStrings) of STR16;
+
+  -- Objects...
+  constant string_array: string_table :=
+    ( "This is string 1"
+      ,"__Hello  World__"
+      ,"This is string " & "3"
+      ,"_Bird is a word_"
+      ,"_Goodbye (ciao)_"
+      );
+
+  type ft1 is file of t1;
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to read.
+    file FILEV : ft1 open read_mode is "iofile.59";
+    
+    -- Declare a variable into which we will read.
+    variable VAR : t1;
+    variable k   : integer      := 0;   
+  BEGIN
+    -- Read in the file.
+    for I in 1 to NumofStrings loop
+      if (ENDFILE( FILEV ) /= FALSE) then
+        k := 1;
+      end if;
+      assert( (ENDFILE( FILEV ) = FALSE) )
+        report "Hit the end of file too soon.";
+      READ( FILEV,VAR );
+      if ((VAR.number /= i) or (VAR.string /= string_array(i))) then
+        k := 1;
+      end if;
+    end loop;
+    
+    -- Verify that we are at the end.
+    if (ENDFILE( FILEV ) /= TRUE) then
+      k := 1;
+    end if;
+    assert( ENDFILE( FILEV ) = TRUE )
+      report "Have not reached end of file yet."
+      severity ERROR;   
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00709"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00709 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00709arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc710.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc710.vhd
new file mode 100644
index 0000000..e94f66f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc710.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc710.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:09 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00710ent IS
+END c03s04b01x00p23n01i00710ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00710arch OF c03s04b01x00p23n01i00710ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  type t2 is array(1 to 5) of INTEGER;
+  type t3 is array(INTEGER range <>) of t2;
+  
+  -- Objects...
+  constant integer_array: t3(1 to 8) :=
+    ( (0, 1, 2, 3, 4),    (2, 4, 6, 8, 10),
+      (-2, -1, 0, 1, 2),    (13, 2, -45, 6, 1),
+      (1, 4, 16, 64, 256),    (1, 4, 9, 16, 25),
+      (1, 2, 4, 8, 16),    (5, 4, 3, 2, 1) );
+
+  type    ft3 is file of t3;
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV : ft3 open write_mode is "iofile.60";
+
+    -- Declare a variable.
+    variable VAR : t3(3 downto 0);
+  BEGIN
+    -- Write out the file.
+    for I in 1 to 2  loop
+      VAR := integer_array((i-1)*4+1 to i*4);
+      write(FILEV, VAR);
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p23n01i00710 - The output file will tested by test file s010442.vhd"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00710arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc711.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc711.vhd
new file mode 100644
index 0000000..7a15d8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc711.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc711.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:09 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p23n01i00711ent IS
+END c03s04b01x00p23n01i00711ent;
+
+ARCHITECTURE c03s04b01x00p23n01i00711arch OF c03s04b01x00p23n01i00711ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  -- Types...;
+  type t2 is array(1 to 5) of INTEGER;
+  type t3 is array(INTEGER range <>) of t2;
+  type ft3 is file of t3;
+
+  -- Objects...
+  constant integer_array: t3(1 to 8) :=
+    ( (0, 1, 2, 3, 4),    (2, 4, 6, 8, 10),
+      (-2, -1, 0, 1, 2),    (13, 2, -45, 6, 1),
+      (1, 4, 16, 64, 256),    (1, 4, 9, 16, 25),
+      (1, 2, 4, 8, 16),    (5, 4, 3, 2, 1) );
+
+
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to read.
+    file FILEV : ft3 open read_mode is "iofile.60";
+    
+    -- Declare a variable into which we will read.
+    variable VAR    : t3(3 downto 0);
+    variable k      : integer   := 0;   
+    variable count    : integer;
+    variable length   : integer;
+  BEGIN
+    -- Read in the file.
+    count := 1;
+    while not endfile(FILEV) loop
+      read(FILEV, VAR, length);
+      assert length = 4
+        report "Wrong length returned from READ"
+        severity ERROR;
+      if (length /= 4) then
+        k := 1;
+      end if;
+      assert VAR(1 to length) = integer_array((count-1)*4+1 to count*4)
+        report "Read of array of integer arrays failed."
+        severity ERROR;
+      if (VAR(1 to length) /= integer_array((count-1)*4+1 to count*4)) then
+        k := 1;
+      end if;
+      count := count + 1;
+    end loop;
+
+    assert NOT( k = 0 )
+      report "***PASSED TEST: c03s04b01x00p23n01i00711"
+      severity NOTE;
+    assert( k = 0 )
+      report "***FAILED TEST: c03s04b01x00p23n01i00711 - The variables don't equal the constants." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p23n01i00711arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc712.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc712.vhd
new file mode 100644
index 0000000..20218cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc712.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc712.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:09 1996  --
+--                 ****************************               --
+
+
+
+ENTITY c03s04b01x00p24n01i00712ent IS
+END c03s04b01x00p24n01i00712ent;
+
+ARCHITECTURE c03s04b01x00p24n01i00712arch OF c03s04b01x00p24n01i00712ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  -- Types...;
+  subtype STR16 is STRING (1 to StringLength);
+  type string_table is array (1 to NumOfStrings) of STR16;
+
+  -- Objects...
+  constant string_array: string_table :=
+    ( "This is string 1"
+      ,"__Hello  World__"
+      ,"This is string " & "3"
+      ,"_Bird is a word_"
+      ,"_Goodbye (ciao)_"
+      );
+
+  type ft3 is file of STRING;
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV : ft3 open write_mode is "iofile.01";
+  BEGIN
+    for i in 1 to NumOfStrings loop
+      write(FILEV, string_array(i));
+    end loop;
+    assert FALSE
+      report "***PASSED TEST: c03s04b01x00p24n01i00712 - This test should produce an output file iofile.01 and tested by s010102.vhd."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p24n01i00712arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc713.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc713.vhd
new file mode 100644
index 0000000..dab5fe5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc713.vhd
@@ -0,0 +1,103 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc713.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
+-- $Revision: 1.3 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:38:09 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:26:46 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:36:48 1996  --
+--                 ****************************               --
+
+
+ENTITY c03s04b01x00p24n01i00713ent IS
+END c03s04b01x00p24n01i00713ent;
+
+ARCHITECTURE c03s04b01x00p24n01i00713arch OF c03s04b01x00p24n01i00713ent IS
+  -- Some constants...
+  constant StringLength: INTEGER := 16;
+  constant NumOfStrings: INTEGER := 5;
+  
+  -- Types...;
+  subtype STR16 is STRING (1 to StringLength);
+  type string_table is array (1 to NumOfStrings) of STR16;
+
+  -- Objects...
+  constant string_array: string_table :=
+    (  "This is string 1"
+       ,"__Hello  World__"
+       ,"This is string " & "3"
+       ,"_Bird is a word_"
+       ,"_Goodbye (ciao)_"
+       );
+
+  type ft3 is file of STRING;
+BEGIN
+  TESTING: PROCESS
+    -- Declare the actual file to write.
+    file FILEV : ft3 open read_mode is "iofile.02";
+    variable length   : INTEGER;
+    variable str   : STR16;
+    variable count    : integer := 0;
+    variable ok   : integer := 1;
+  BEGIN
+    count := 1;
+    while not endfile(FILEV) loop
+      read(FILEV, str, length);
+      if (length /= 16) then
+        ok := 0;
+      end if;
+      if (str /= string_array(count)) then
+        ok := 0;
+      end if;
+      assert str = string_array(count)
+        report "'string' is incorrect"
+        severity ERROR;
+      count := count + 1;
+    end loop;
+    assert NOT(ok = 1)
+      report "***PASSED TEST: c03s04b01x00p24n01i00713" 
+      severity NOTE;
+    assert (ok = 1)
+      report "***FAILED TEST: c03s04b01x00p24n01i00713 - READ operation for unconstrained array type test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b01x00p24n01i00713arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc717.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc717.vhd
new file mode 100644
index 0000000..b529fe7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc717.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc717.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b00x00p02n01i00717ent IS
+begin
+  assert false
+    report "First entity NOT overwritten -- test FAILS."
+    severity note ;
+END c01s01b00x00p02n01i00717ent;
+
+
+-- legal. identifier has already been defined - this causes the
+--        first entity to be over-written.
+ENTITY c01s01b00x00p02n01i00717ent IS                         -- second use of name
+begin
+  assert false
+    report "First entity overwritten -- test passes."
+    severity note ;
+END c01s01b00x00p02n01i00717ent;
+
+ARCHITECTURE c01s01b00x00p02n01i00717arch OF c01s01b00x00p02n01i00717ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b00x00p02n01i00717 - This test needs manual check." 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b00x00p02n01i00717arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc719.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc719.vhd
new file mode 100644
index 0000000..9185d9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc719.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc719.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b00x00p04n01i00719ent IS
+BEGIN
+END;            -- No_Failure_Here
+
+ENTITY c01s01b00x00p04n01i00719ent IS
+END c01s01b00x00p04n01i00719ent;
+
+ARCHITECTURE c01s01b00x00p04n01i00719arch OF c01s01b00x00p04n01i00719ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s01b00x00p04n01i00719"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b00x00p04n01i00719arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc731.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc731.vhd
new file mode 100644
index 0000000..a602d07
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc731.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc731.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p04n01i00731ent IS
+  -- A basic entity with a port
+  port ( signal s : bit);
+END c01s01b01x00p04n01i00731ent;
+
+ARCHITECTURE c01s01b01x00p04n01i00731arch OF c01s01b01x00p04n01i00731ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x00p04n01i00731"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p04n01i00731arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc740.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc740.vhd
new file mode 100644
index 0000000..a4fe42e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc740.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc740.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p04n02i00740pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural  
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer; 
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  constant C1 : boolean := true; 
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note; 
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant C10 : string := "shishir";
+  constant C11 : bit_vector := B"0011";
+  constant C12 : boolean_vector := (true,false); 
+  constant C13 : severity_level_vector := (note,error);
+  constant C14 : integer_vector := (1,2,3,4); 
+  constant C15 : real_vector := (1.0,2.0,3.0,4.0); 
+  constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector := (1,2,3,4);
+  constant C18 : positive_vector := (1,2,3,4);
+
+end c01s01b01x01p04n02i00740pkg;
+
+use work.c01s01b01x01p04n02i00740pkg.all;
+ENTITY c01s01b01x01p04n02i00740ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    Cgen1 : boolean := true;
+    Cgen2 : bit := '1';
+    Cgen3 : character := 's';
+    Cgen4 : severity_level := note;
+    Cgen5 : integer := 3;
+    Cgen6 : real := 3.0;
+    Cgen7 : time := 3 ns;
+    Cgen8 : natural := 1;
+    Cgen9 : positive := 1;
+    Cgen10 : string := "shishir";
+    Cgen11 : bit_vector := B"0011";
+    Cgen12 : boolean_vector := (true,false);
+    Cgen13 : severity_level_vector := (note,error);
+    Cgne14 : integer_vector := (1,2,3,4);
+    Cgen15 : real_vector := (1.0,2.0,3.0,4.0);
+    Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+    Cgen17 : natural_vector := (1,2,3,4);
+    Cgen18 : positive_vector := (1,2,3,4));
+END c01s01b01x01p04n02i00740ent;
+
+ARCHITECTURE c01s01b01x01p04n02i00740arch OF c01s01b01x01p04n02i00740ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    variable Vgen1 : boolean := true;
+    variable Vgen2 : bit := '1';
+    variable Vgen3 : character := 's';
+    variable Vgen4 : severity_level := note;
+    variable Vgen5 : integer := 3;
+    variable Vgen6 : real := 3.0;
+    variable Vgen7 : time := 3 ns;
+    variable Vgen8 : natural := 1;
+    variable Vgen9 : positive := 1;
+    variable Vgen10 : string (one to seven):= "shishir";
+    variable Vgen11 : bit_vector(zero to three) := B"0011";
+    variable Vgen12 : boolean_vector(zero to one) := (true,false);
+    variable Vgen13 : severity_level_vector(zero to one) := (note,error);
+    variable Vgen14 : integer_vector(zero to three) := (1,2,3,4);
+    variable Vgen15 : real_vector(zero to three) := (1.0,2.0,3.0,4.0);
+    variable Vgen16 : time_vector(zero to three) := (1 ns, 2 ns, 3 ns, 4 ns);
+    variable Vgen17 : natural_vector(zero to three) := (1,2,3,4);
+    variable Vgen18 : positive_vector(zero to three) := (1,2,3,4);
+
+  BEGIN
+    assert Vgen1 = C1 report "Initializing variable with generic Vgen1 does not work" severity error;
+    assert Vgen2 = C2 report "Initializing variable with generic Vgen2 does not work" severity error;
+    assert Vgen3 = C3 report "Initializing variable with generic Vgen3 does not work" severity error;
+    assert Vgen4 = C4 report "Initializing variable with generic Vgen4 does not work" severity error;
+    assert Vgen5 = C5 report "Initializing variable with generic Vgen5 does not work" severity error;
+    assert Vgen6 = C6 report "Initializing variable with generic Vgen6 does not work" severity error;
+    assert Vgen7 = C7 report "Initializing variable with generic Vgen7 does not work" severity error;
+    assert Vgen8 = C8 report "Initializing variable with generic Vgen8 does not work" severity error;
+    assert Vgen9 = C9 report "Initializing variable with generic Vgen9 does not work" severity error;
+    assert Vgen10 = C10 report "Initializing variable with generic Vgen10 does not work" severity error;
+    assert Vgen11 = C11 report "Initializing variable with generic Vgen11 does not work" severity error;
+    assert Vgen12 = C12 report "Initializing variable with generic Vgen12 does not work" severity error;
+    assert Vgen13 = C13 report "Initializing variable with generic Vgen13 does not work" severity error;
+    assert Vgen14 = C14 report "Initializing variable with generic Vgen14 does not work" severity error;
+    assert Vgen15 = C15 report "Initializing variable with generic Vgen15 does not work" severity error;
+    assert Vgen16 = C16 report "Initializing variable with generic Vgen16 does not work" severity error;
+    assert Vgen17 = C17 report "Initializing variable with generic Vgen17 does not work" severity error;
+    assert Vgen18 = C18 report "Initializing variable with generic Vgen18 does not work" severity error;
+    assert NOT( 
+      Vgen1 = C1    and
+      Vgen2 = C2    and
+      Vgen3 = C3    and
+      Vgen4 = C4    and
+      Vgen5 = C5    and
+      Vgen6 = C6    and
+      Vgen7 = C7    and
+      Vgen8 = C8    and
+      Vgen9 = C9    and
+      Vgen10 = C10    and
+      Vgen11 = C11    and
+      Vgen12 = C12    and
+      Vgen13 = C13    and
+      Vgen14 = C14    and
+      Vgen15 = C15    and
+      Vgen16 = C16    and
+      Vgen17 = C17    and
+      Vgen18 = C18    )
+      report "***PASSED TEST: c01s01b01x01p04n02i00740"
+      severity NOTE;
+    assert ( 
+      Vgen1 = C1    and
+      Vgen2 = C2    and
+      Vgen3 = C3    and
+      Vgen4 = C4    and
+      Vgen5 = C5    and
+      Vgen6 = C6    and
+      Vgen7 = C7    and
+      Vgen8 = C8    and
+      Vgen9 = C9    and
+      Vgen10 = C10    and
+      Vgen11 = C11    and
+      Vgen12 = C12    and
+      Vgen13 = C13    and
+      Vgen14 = C14    and
+      Vgen15 = C15    and
+      Vgen16 = C16    and
+      Vgen17 = C17    and
+      Vgen18 = C18    )
+      report "***FAILED TEST: c01s01b01x01p04n02i00740 - Initializing variable with generic does not work."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p04n02i00740arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc741.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc741.vhd
new file mode 100644
index 0000000..f6cb9da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc741.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc741.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s01b01x01p04n01i00741ent_a is
+  generic (
+    constant gc1 : in integer;
+    constant gc2 : in real;
+    constant gc3 : in boolean
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x01p04n01i00741ent_a;
+
+architecture c01s01b01x01p04n01i00741arch_a of c01s01b01x01p04n01i00741ent_a is
+begin
+  p0: process
+  begin
+    wait for 1 ns;
+    if (gc1 = 5) AND (gc2 = 0.1234) AND (gc3) then
+      assert FALSE 
+        report "***PASSED TEST: c01s01b01x01p04n01i00741"
+        severity NOTE;
+    else
+      assert FALSE
+        report "***FAILED TEST: c01s01b01x01p04n01i00741 - Simple generic association in component instantiation failed."
+        severity ERROR;
+    end if;
+    wait;
+  end process;
+end c01s01b01x01p04n01i00741arch_a;
+
+
+ENTITY c01s01b01x01p04n01i00741ent IS
+  generic ( constant gen_con : integer := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x01p04n01i00741ent;
+
+ARCHITECTURE c01s01b01x01p04n01i00741arch OF c01s01b01x01p04n01i00741ent IS
+  constant    c1 : integer    := 33;
+  constant    c2 : real    := 1.23557;
+  constant    c3 : boolean    := FALSE;
+  signal       s1 : integer;
+  signal       s2 : integer;
+  signal       s3 : integer;
+
+  component comp1
+    generic (
+      constant dgc1 : integer;
+      constant dgc2 : real;
+      constant dgc3 : boolean
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+  
+  for u1 : comp1 use
+    entity work.c01s01b01x01p04n01i00741ent_a(c01s01b01x01p04n01i00741arch_a)
+    generic map (dgc1, dgc2, dgc3)
+    port map ( dcent1, dcent2 );
+
+BEGIN
+  
+  u1 : comp1
+    generic map (5, 0.1234, TRUE)
+    port map (ee1,ee2);
+
+END c01s01b01x01p04n01i00741arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc742.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc742.vhd
new file mode 100644
index 0000000..17c1be2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc742.vhd
@@ -0,0 +1,131 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc742.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p04n01i00742pkg is
+  type arrtype is array (1 to 5) of integer;
+  type rectype is record
+-- 'a',33,0.1234,TRUE
+                    ch : character;
+                    int : integer;
+                    re : real;
+                    bo : boolean;
+                  end record;
+end c01s01b01x01p04n01i00742pkg;
+
+use work.c01s01b01x01p04n01i00742pkg.all;
+entity c01s01b01x01p04n01i00742ent_a is
+  generic (
+    constant gc1 : arrtype;
+    constant gc2 : rectype;
+    constant gc3 : boolean
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x01p04n01i00742ent_a;
+
+architecture c01s01b01x01p04n01i00742arch_a of c01s01b01x01p04n01i00742ent_a is
+begin
+  p0: process
+  begin
+    wait for 1 ns;
+    if (gc1=(1,2,3,4,5)) AND (gc2.ch='a') AND (gc2.int=33) AND (gc2.re=0.1234) AND (gc2.bo)  AND (gc3) then
+      assert FALSE 
+        report "***PASSED TEST: c01s01b01x01p04n01i00742"
+        severity NOTE;
+    else
+      assert FALSE
+        report "***FAILED TEST: c01s01b01x01p04n01i00742 - Generic association with type conversion in component instantiation failed." 
+        severity ERROR;
+    end if;
+    wait;
+  end process;
+end c01s01b01x01p04n01i00742arch_a;
+
+use work.c01s01b01x01p04n01i00742pkg.all;
+ENTITY c01s01b01x01p04n01i00742ent IS
+  generic ( constant gen_con : integer := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x01p04n01i00742ent;
+
+ARCHITECTURE c01s01b01x01p04n01i00742arch OF c01s01b01x01p04n01i00742ent IS
+  signal       s1 : integer;
+  signal       s2 : integer;
+  signal       s3 : integer;
+
+  component comp1
+    generic (
+      constant dgc1 : arrtype;
+      constant dgc2 : rectype;
+      constant dgc3 : boolean
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+  
+  for u1 : comp1 use
+    entity work.c01s01b01x01p04n01i00742ent_a(c01s01b01x01p04n01i00742arch_a)
+    generic map (dgc1, dgc2, dgc3)
+    port map ( dcent1, dcent2 );
+
+  function BoolToArr(bin : boolean) return arrtype is
+  begin
+    if bin then
+      return (1,2,3,4,5);
+    else
+      return (9,8,7,6,5);
+    end if;
+  end;
+  
+  function IntegerToRec(iin : integer) return rectype is
+  begin
+    return ('a',33,0.1234,TRUE);
+  end;
+  
+  function BitToBool(bin : bit) return boolean is
+  begin
+    if (bin = '1') then
+      return TRUE;
+    else
+      return FALSE;
+    end if;
+  end;
+
+BEGIN
+  
+  u1 : comp1
+    generic map (BoolToArr(TRUE), IntegerToRec(1234), BitToBool('1'))
+    port map (ee1,ee2);
+
+END c01s01b01x01p04n01i00742arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc743.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc743.vhd
new file mode 100644
index 0000000..840378a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc743.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc743.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p04n01i00743pkg is
+  type arrtype is array (1 to 5) of bit;
+  constant defcon1 : bit;
+  constant defcon2 : integer;
+  constant defcon3 : arrtype;
+  constant defcon4 : boolean;
+  component comp1
+    generic (
+      constant dgc1 : bit := defcon1;
+      constant dgc2 : integer := defcon2;
+      constant dgc3 : arrtype := defcon3;
+      constant dgc4 : boolean := defcon4
+      );
+    port ( signal dcent1 : inout bit := dgc1;
+           signal dcent2 : inout integer := dgc2;
+           signal dcent3 : inout arrtype := dgc3;
+           signal dcent4 : inout boolean := dgc4
+           );
+  end component;
+end c01s01b01x01p04n01i00743pkg;
+
+package body c01s01b01x01p04n01i00743pkg is
+  constant defcon1 : bit := '1';
+  constant defcon2 : integer := 113;
+  constant defcon3 : arrtype := ('1','0','1','0','1');
+  constant defcon4 : boolean := TRUE;
+end c01s01b01x01p04n01i00743pkg;
+
+use work.c01s01b01x01p04n01i00743pkg.all;
+entity c01s01b01x01p04n01i00743ent_a is
+  generic (
+    constant gc1 : bit;
+    constant gc2 : integer;
+    constant gc3 : arrtype;
+    constant gc4 : boolean
+    );
+  port (       signal cent1 : inout bit;
+               signal cent2 : inout integer;
+               signal cent3 : inout arrtype;
+               signal cent4 : inout boolean
+               );
+end c01s01b01x01p04n01i00743ent_a;
+
+architecture c01s01b01x01p04n01i00743arch_a of c01s01b01x01p04n01i00743ent_a is
+begin
+  p0: process
+  begin
+    wait for 1 ns;
+    if (gc1='1') and (gc2=113) and (gc3=('1','0','1','0','1')) and (gc4) then
+      assert FALSE 
+        report "***PASSED TEST: c01s01b01x01p04n01i00743"
+        severity NOTE;
+    else
+      assert FALSE
+        report "***FAILED TEST: c01s01b01x01p04n01i00743 - Generic default to deferred constants." 
+        severity ERROR;
+    end if;
+    wait;
+  end process;
+end c01s01b01x01p04n01i00743arch_a;
+
+use work.c01s01b01x01p04n01i00743pkg.all;
+ENTITY c01s01b01x01p04n01i00743ent IS
+  generic    (    constant gen_con : integer := 1334 );
+  port    (    signal ee1 : inout boolean := TRUE;
+               signal ee2 : inout bit;
+               signal ee3 : inout integer;
+               signal ee4 : inout arrtype
+               );
+END c01s01b01x01p04n01i00743ent;
+
+ARCHITECTURE c01s01b01x01p04n01i00743arch OF c01s01b01x01p04n01i00743ent IS
+  for u1 : comp1 use
+    entity work.c01s01b01x01p04n01i00743ent_a(c01s01b01x01p04n01i00743arch_a)
+    generic map ( dgc1, dgc2, dgc3, dgc4 )
+    port map ( dcent1, dcent2, dcent3, dcent4 );
+BEGIN
+
+  u1 : comp1; 
+
+END c01s01b01x01p04n01i00743arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc744.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc744.vhd
new file mode 100644
index 0000000..e47c7da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc744.vhd
@@ -0,0 +1,170 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc744.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00744pkg is
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c: character;
+                               d: severity_level;
+                               e: integer;
+                               f: real;
+                               g: time;
+                               h: natural;
+                               i: positive;
+                               j: string(1 to 7);
+                               k: bit_vector(0 to 3);
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+
+end c01s01b01x01p05n02i00744pkg;
+
+use work.c01s01b01x01p05n02i00744pkg.all;
+ENTITY c01s01b01x01p05n02i00744ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "shishir";
+    C11 : bit_vector    := B"0011"
+    );
+  port(
+    S1 : inout boolean_vector      (zero to fifteen);
+    S2 : inout severity_level_vector   (zero to fifteen);
+    S3 : inout integer_vector      (zero to fifteen);
+    S4 : inout real_vector         (zero to fifteen);
+    S5 : inout time_vector       (zero to fifteen);
+    S6 : inout natural_vector      (zero to fifteen);
+    S7 : inout positive_vector      (zero to fifteen);
+    S48: inout array_rec_std      (zero to seven)
+    );
+END c01s01b01x01p05n02i00744ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00744arch OF c01s01b01x01p05n02i00744ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable   k : integer := 0;
+  BEGIN
+    for i in S1'range loop
+      S1(i) <= C1;
+    end loop;
+    for i in S2'range loop
+      S2(i) <= C4;
+    end loop;
+    for i in S3'range loop
+      S3(i) <= C5;
+    end loop;
+    for i in S4'range loop
+      S4(i) <= C6;
+    end loop;
+    for i in S5'range loop
+      S5(i) <= C7;
+    end loop;
+    for i in S6'range loop
+      S6(i) <= C8;
+    end loop;
+    for i in S7'range loop
+      S7(i) <= C9;
+    end loop;
+    for i in S48'range loop
+      S48(i) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+    end loop;
+    wait for 10 ns;
+    for i in zero to 7 loop
+      if (S1(i) /= true) then
+        k := 1;
+      end if;
+      assert S1(i) = true report " boolean_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S2(i) /= note) then
+        k := 1;
+      end if;
+      assert S2(i) = note report " severity_level_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S3(i) /= 3) then
+        k := 1;
+      end if;
+      assert S3(i) = 3 report " integer_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S4(i) /= 3.0) then
+        k := 1;
+      end if;
+      assert S4(i) = 3.0 report " real_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S5(i) /= 3 ns) then
+        k := 1;
+      end if;
+      assert S5(i) = 3 ns report " time_vector (zero to fifteen) error in the left generic value" severity  error;
+      if (S6(i) /= 1) then
+        k := 1;
+      end if;
+      assert S6(i) = 1 report " natural_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S7(i) /= 1) then
+        k := 1;
+      end if;
+      assert S7(i) = 1 report " positive_vector(zero to fifteen) error in the left generic value" severity  error;
+      if (S48(i) /= (true,'1','s',note,3,3.0,3 ns,1,1,"shishir","0011")) then
+        k := 1;
+      end if;
+      assert S48(i) = (true,'1','s',note,3,3.0,3 ns,1,1,"shishir","0011") report " array_rec_std(zero to seven) error in the left generic value" severity  error;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c01s01b01x01p05n02i00744"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c01s01b01x01p05n02i00744 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00744arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc745.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc745.vhd
new file mode 100644
index 0000000..771b627
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc745.vhd
@@ -0,0 +1,250 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc745.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00745pkg is
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c: character;
+                               d: severity_level;
+                               e: integer;
+                               f: real;
+                               g: time;
+                               h: natural;
+                               i: positive;
+                               j: string(1 to 7);
+                               k: bit_vector(0 to 3);
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+
+  function F1(inp : boolean_vector)    return boolean ;
+  function F2(inp : bit_vector)    return bit ;
+  function F3(inp : string)       return character ;
+  function F4(inp : severity_level_vector)    return severity_level ;
+  function F5(inp : integer_vector)    return integer ;
+  function F6(inp : real_vector)    return real ;
+  function F7(inp : time_vector)    return time ;
+  function F8(inp : natural_vector)    return natural ;
+  function F9(inp : positive_vector)    return positive ;
+  function F10(inp : array_rec_std)    return record_std_package ;
+
+end c01s01b01x01p05n02i00745pkg;
+
+package body c01s01b01x01p05n02i00745pkg is
+  function F1(inp : boolean_vector) return boolean is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = true) report"wrong initialization of S1" severity error;
+    end loop;
+    return false;
+  end F1;
+  function F2(inp : bit_vector) return bit is
+  begin
+    for i in 0 to 3 loop
+      assert(inp(i) = '0') report"wrong initialization of S2" severity error;
+    end loop;
+    return '0';
+  end F2;
+  function F3(inp : string) return character is
+  begin
+    for i in 1 to 7 loop
+      assert(inp(i) = 's') report"wrong initialization of S3" severity error;
+    end loop;
+    return 'h';
+  end F3;
+  function F4(inp : severity_level_vector) return severity_level is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = note) report"wrong initialization of S4" severity error;
+    end loop;
+    return error;
+  end F4;
+  function F5(inp : integer_vector) return integer is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3) report"wrong initialization of S5" severity error;
+    end loop;
+    return 6;
+  end F5;
+  function F6(inp : real_vector) return real is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
+    end loop;
+    return 6.0;
+  end F6;
+  function F7(inp : time_vector) return time is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
+    end loop;
+    return 6 ns;
+  end F7;
+  function F8(inp : natural_vector) return natural is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S8" severity error;
+    end loop;
+    return 6;
+  end F8;
+  function F9(inp : positive_vector) return positive is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S9" severity error;
+    end loop;
+    return 6;
+  end F9;
+  function F10(inp : array_rec_std) return record_std_package is
+  begin
+    for i in 0 to 7 loop
+      assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
+    end loop;
+    return (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
+  end F10;
+end c01s01b01x01p05n02i00745pkg;
+
+
+use work.c01s01b01x01p05n02i00745pkg.all;
+ENTITY c01s01b01x01p05n02i00745ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "sssssss";
+    C11 : bit_vector    := B"0000";
+    C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
+    );
+  port(
+    S1 : boolean_vector(zero to fifteen)    := (others => C1);
+    S2 : severity_level_vector(zero to fifteen)    := (others => C4);
+    S3 : integer_vector(zero to fifteen)   := (others => C5);
+    S4 : real_vector(zero to fifteen)   := (others => C6);
+    S5 : time_vector (zero to fifteen)   := (others => C7);
+    S6 : natural_vector(zero to fifteen)   := (others => C8);
+    S7 : positive_vector(zero to fifteen)   := (others => C9);
+    S8 : string(one to seven)      := C10;
+    S9 : bit_vector(zero to three)      := C11;
+    S48: array_rec_std(zero to seven)   := (others => C48)
+    );
+END c01s01b01x01p05n02i00745ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00745arch OF c01s01b01x01p05n02i00745ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    variable var1 : boolean;
+    variable var4 : severity_level;
+    variable var5 : integer;
+    variable var6 : real;
+    variable var7 : time;
+    variable var8 : natural;
+    variable var9 : positive;
+    variable var2 : bit;
+    variable var3 : character;
+    variable var48: record_std_package;
+
+  BEGIN
+    var1 := F1(S1);
+    var2 := F2(S9);
+    var3 := F3(S8);
+    var4 := F4(S2);
+    var5 := F5(S3);
+    var6 := F6(S4);
+    var7 := F7(S5);
+    var8 := F8(S6);
+    var9 := F9(S7);
+    var48 := F10(S48);
+    wait for 1 ns;
+
+    assert(var1 = false) report "wrong assignment in the function F1" severity error;
+    assert(var2 = '0') report "wrong assignment in the function F2" severity error;
+    assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
+    assert(var4 = error) report "wrong assignment in the function F4" severity error;
+    assert(var5 = 6) report "wrong assignment in the function F5" severity error;
+    assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
+    assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
+    assert(var8 = 6) report "wrong assignment in the function F8" severity error;
+    assert(var9 = 6) report "wrong assignment in the function F9" severity error;
+    assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
+
+    assert NOT(    var1    = F1(S1)   and
+                   var2    = F2(S9)   and
+                   var3    = F3(S8)   and
+                   var4    = F4(S2)   and
+                   var5    = F5(S3)   and
+                   var6    = F6(S4)   and
+                   var7    = F7(S5)   and
+                   var8    = F8(S6)   and
+                   var9    = F9(S7)   and
+                   var48    = F10(S48)   )
+      report "***PASSED TEST: c01s01b01x01p05n02i00745"
+      severity NOTE;
+    assert (    var1    = F1(S1)   and
+                var2    = F2(S9)   and
+                var3    = F3(S8)   and
+                var4    = F4(S2)   and
+                var5    = F5(S3)   and
+                var6    = F6(S4)   and
+                var7    = F7(S5)   and
+                var8    = F8(S6)   and
+                var9    = F9(S7)   and
+                var48    = F10(S48)   )
+      report "***FAILED TEST: c01s01b01x01p05n02i00745 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00745arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc746.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc746.vhd
new file mode 100644
index 0000000..07ed72d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc746.vhd
@@ -0,0 +1,249 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc746.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00746pkg is
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(1 to 7);
+                               k:bit_vector(0 to 3);
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+
+  function F1(inp : boolean_vector(0 to 15))    return boolean ;
+  function F2(inp : bit_vector(0 to 3))    return bit ;
+  function F3(inp : string(1 to 7))       return character ;
+  function F4(inp : severity_level_vector(0 to 15))    return severity_level ;
+  function F5(inp : integer_vector(0 to 15))    return integer ;
+  function F6(inp : real_vector(0 to 15))    return real ;
+  function F7(inp : time_vector(0 to 15))    return time ;
+  function F8(inp : natural_vector(0 to 15))    return natural ;
+  function F9(inp : positive_vector(0 to 15)) return positive ;
+  function F10(inp: array_rec_std(0 to 7))    return record_std_package ;
+
+end c01s01b01x01p05n02i00746pkg;
+
+package body c01s01b01x01p05n02i00746pkg is
+  function F1(inp : boolean_vector(0 to 15)) return boolean is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = true) report"wrong initialization of S1" severity error;
+    end loop;
+    return false;
+  end F1;
+  function F2(inp : bit_vector(0 to 3)) return bit is
+  begin
+    for i in 0 to 3 loop
+      assert(inp(i) = '0') report"wrong initialization of S2" severity error;
+    end loop;
+    return '0';
+  end F2;
+  function F3(inp : string(1 to 7)) return character is
+  begin
+    for i in 1 to 7 loop
+      assert(inp(i) = 's') report"wrong initialization of S3" severity error;
+    end loop;
+    return 'h';
+  end F3;
+  function F4(inp : severity_level_vector(0 to 15)) return severity_level is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = note) report"wrong initialization of S4" severity error;
+    end loop;
+    return error;
+  end F4;
+  function F5(inp : integer_vector(0 to 15)) return integer is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3) report"wrong initialization of S5" severity error;
+    end loop;
+    return 6;
+  end F5;
+  function F6(inp : real_vector(0 to 15)) return real is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
+    end loop;
+    return 6.0;
+  end F6;
+  function F7(inp : time_vector(0 to 15)) return time is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
+    end loop;
+    return 6 ns;
+  end F7;
+  function F8(inp : natural_vector(0 to 15)) return natural is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S8" severity error;
+    end loop;
+    return 6;
+  end F8;
+  function F9(inp : positive_vector(0 to 15)) return positive is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S9" severity error;
+    end loop;
+    return 6;
+  end F9;
+  function F10(inp : array_rec_std(0 to 7)) return record_std_package is
+  begin
+    for i in 0 to 7 loop
+      assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
+    end loop;
+    return (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
+  end F10;
+end c01s01b01x01p05n02i00746pkg;
+
+use work.c01s01b01x01p05n02i00746pkg.all;
+ENTITY c01s01b01x01p05n02i00746ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "sssssss";
+    C11 : bit_vector    := B"0000";
+    C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
+    );
+  port(
+    S1 : boolean_vector(zero to fifteen)    := (others => C1);
+    S2 : severity_level_vector(zero to fifteen)    := (others => C4);
+    S3 : integer_vector(zero to fifteen)   := (others => C5);
+    S4 : real_vector(zero to fifteen)   := (others => C6);
+    S5 : time_vector (zero to fifteen)   := (others => C7);
+    S6 : natural_vector(zero to fifteen)   := (others => C8);
+    S7 : positive_vector(zero to fifteen)   := (others => C9);
+    S8 : string(one to seven)      := C10;
+    S9 : bit_vector(zero to three)      := C11;
+    S48: array_rec_std(zero to seven)   := (others => C48)
+    );
+END c01s01b01x01p05n02i00746ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00746arch OF c01s01b01x01p05n02i00746ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    variable var1 : boolean;
+    variable var4 : severity_level;
+    variable var5 : integer;
+    variable var6 : real;
+    variable var7 : time;
+    variable var8 : natural;
+    variable var9 : positive;
+    variable var2 : bit;
+    variable var3 : character;
+    variable var48: record_std_package;
+
+  BEGIN
+    var1 := F1(S1);
+    var2 := F2(S9);
+    var3 := F3(S8);
+    var4 := F4(S2);
+    var5 := F5(S3);
+    var6 := F6(S4);
+    var7 := F7(S5);
+    var8 := F8(S6);
+    var9 := F9(S7);
+    var48 := F10(S48);
+    wait for 1 ns;
+
+    assert(var1 = false) report "wrong assignment in the function F1" severity error;
+    assert(var2 = '0') report "wrong assignment in the function F2" severity error;
+    assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
+    assert(var4 = error) report "wrong assignment in the function F4" severity error;
+    assert(var5 = 6) report "wrong assignment in the function F5" severity error;
+    assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
+    assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
+    assert(var8 = 6) report "wrong assignment in the function F8" severity error;
+    assert(var9 = 6) report "wrong assignment in the function F9" severity error;
+    assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
+
+    assert NOT(    var1    = F1(S1)   and
+                   var2    = F2(S9)   and
+                   var3    = F3(S8)   and
+                   var4    = F4(S2)   and
+                   var5    = F5(S3)   and
+                   var6    = F6(S4)   and
+                   var7    = F7(S5)   and
+                   var8    = F8(S6)   and
+                   var9    = F9(S7)   and
+                   var48    = F10(S48)   )
+      report "***PASSED TEST: c01s01b01x01p05n02i00746"
+      severity NOTE;
+    assert (    var1    = F1(S1)   and
+                var2    = F2(S9)   and
+                var3    = F3(S8)   and
+                var4    = F4(S2)   and
+                var5    = F5(S3)   and
+                var6    = F6(S4)   and
+                var7    = F7(S5)   and
+                var8    = F8(S6)   and
+                var9    = F9(S7)   and
+                var48    = F10(S48)   )
+      report "***FAILED TEST: c01s01b01x01p05n02i00746 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00746arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc747.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc747.vhd
new file mode 100644
index 0000000..3ff5063
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc747.vhd
@@ -0,0 +1,249 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc747.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00747pkg is
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(1 to 7);
+                               k:bit_vector(0 to 3);
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+
+  procedure P1(inp : boolean_vector;ot:out boolean) ;
+  procedure P2(inp : bit_vector;ot:out bit) ;
+  procedure P3(inp : string; ot:out character);
+  procedure P4(inp : severity_level_vector;ot:out severity_level);
+  procedure P5(inp : integer_vector; ot:out integer) ;
+  procedure P6(inp : real_vector; ot:out real) ;
+  procedure P7(inp : time_vector; ot:out time) ;
+  procedure P8(inp : natural_vector;ot:out natural) ;
+  procedure P9(inp : positive_vector;ot:out positive) ;
+  procedure P10(inp : array_rec_std;ot:out record_std_package) ;
+
+end c01s01b01x01p05n02i00747pkg;
+
+package body c01s01b01x01p05n02i00747pkg is
+  procedure P1(inp : boolean_vector;ot:out boolean) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = true) report"wrong initialization of S1" severity error;
+    end loop;
+    ot :=  false;
+  end P1;
+  procedure P2(inp : bit_vector;ot:out bit) is
+  begin
+    for i in 0 to 3 loop
+      assert(inp(i) = '0') report"wrong initialization of S2" severity error;
+    end loop;
+    ot :=  '0';
+  end P2;
+  procedure P3(inp : string; ot:out character) is
+  begin
+    for i in 1 to 7 loop
+      assert(inp(i) = 's') report"wrong initialization of S3" severity error;
+    end loop;
+    ot :=  'h';
+  end P3;
+  procedure P4(inp : severity_level_vector;ot:out severity_level) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = note) report"wrong initialization of S4" severity error;
+    end loop;
+    ot :=  error;
+  end P4;
+  procedure P5(inp : integer_vector; ot:out integer) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3) report"wrong initialization of S5" severity error;
+    end loop;
+    ot :=  6;
+  end P5;
+  procedure P6(inp : real_vector; ot:out real) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
+    end loop;
+    ot :=  6.0;
+  end P6;
+  procedure P7(inp : time_vector; ot:out time) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
+    end loop;
+    ot :=  6 ns;
+  end P7;
+  procedure P8(inp : natural_vector;ot:out natural) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S8" severity error;
+    end loop;
+    ot :=  6;
+  end P8;
+  procedure P9(inp : positive_vector;ot:out positive) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S9" severity error;
+    end loop;
+    ot :=  6;
+  end P9;
+  procedure P10(inp : array_rec_std;ot:out record_std_package) is
+  begin
+    for i in 0 to 7 loop
+      assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
+    end loop;
+    ot :=  (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
+  end P10;
+end c01s01b01x01p05n02i00747pkg;
+
+use work.c01s01b01x01p05n02i00747pkg.all;
+ENTITY c01s01b01x01p05n02i00747ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "sssssss";
+    C11 : bit_vector    := B"0000";
+    C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
+    );
+  port(
+    S1 : boolean_vector(zero to fifteen)    := (others => C1);
+    S2 : severity_level_vector(zero to fifteen)    := (others => C4);
+    S3 : integer_vector(zero to fifteen)   := (others => C5);
+    S4 : real_vector(zero to fifteen)   := (others => C6);
+    S5 : time_vector (zero to fifteen)   := (others => C7);
+    S6 : natural_vector(zero to fifteen)   := (others => C8);
+    S7 : positive_vector(zero to fifteen)   := (others => C9);
+    S8 : string(one to seven)      := C10;
+    S9 : bit_vector(zero to three)      := C11;
+    S48: array_rec_std(zero to seven)   := (others => C48)
+    );
+END c01s01b01x01p05n02i00747ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00747arch OF c01s01b01x01p05n02i00747ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    variable var1 : boolean;
+    variable var4 : severity_level;
+    variable var5 : integer;
+    variable var6 : real;
+    variable var7 : time;
+    variable var8 : natural;
+    variable var9 : positive;
+    variable var2 : bit;
+    variable var3 : character;
+    variable var48: record_std_package;
+
+  BEGIN
+    P1(S1,var1);
+    P2(S9,var2);
+    P3(S8,var3);
+    P4(S2,var4);
+    P5(S3,var5);
+    P6(S4,var6);
+    P7(S5,var7);
+    P8(S6,var8);
+    P9(S7,var9);
+    P10(S48,var48);
+    wait for 1 ns;
+
+    assert(var1 = false) report "wrong assignment in the function F1" severity error;
+    assert(var2 = '0') report "wrong assignment in the function F2" severity error;
+    assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
+    assert(var4 = error) report "wrong assignment in the function F4" severity error;
+    assert(var5 = 6) report "wrong assignment in the function F5" severity error;
+    assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
+    assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
+    assert(var8 = 6) report "wrong assignment in the function F8" severity error;
+    assert(var9 = 6) report "wrong assignment in the function F9" severity error;
+    assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
+
+    assert NOT(    var1    = false      and
+                   var2    = '0'      and
+                   var3    = 'h'      and
+                   var4    = error      and
+                   var5    = 6      and
+                   var6    = 6.0      and
+                   var7    = 6 ns      and
+                   var8    = 6      and
+                   var9    = 6      and
+                   var48    = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")   )
+      report "***PASSED TEST: c01s01b01x01p05n02i00747"
+      severity NOTE;
+    assert (    var1    = false      and
+                var2    = '0'      and
+                var3    = 'h'      and
+                var4    = error      and
+                var5    = 6      and
+                var6    = 6.0      and
+                var7    = 6 ns      and
+                var8    = 6      and
+                var9    = 6      and
+                var48    = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")   )
+      report "***FAILED TEST: c01s01b01x01p05n02i00747 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00747arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc748.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc748.vhd
new file mode 100644
index 0000000..44247a3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc748.vhd
@@ -0,0 +1,247 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc748.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00748pkg is
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(1 to 7);
+                               k:bit_vector(0 to 3);
+                             end record;
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+
+  procedure P1(inp : boolean_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out boolean_vector) ;
+  procedure P2(inp : bit_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out bit_vector) ;
+  procedure P3(inp : string; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out string);
+  procedure P4(inp : severity_level_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out severity_level_vector);
+  procedure P5(inp : integer_vector; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out integer_vector) ;
+  procedure P6(inp : real_vector; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out real_vector) ;
+  procedure P7(inp : time_vector; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out time_vector) ;
+  procedure P8(inp : natural_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out natural_vector) ;
+  procedure P9(inp : positive_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out positive_vector) ;
+  procedure P10(inp : array_rec_std; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out array_rec_std) ;
+end c01s01b01x01p05n02i00748pkg;
+
+package body c01s01b01x01p05n02i00748pkg is
+  procedure P1(inp : boolean_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out boolean_vector) is
+  begin 
+    for i in 0 to 15 loop
+      assert(inp(i) = true) report"wrong initialization of S1" severity error;
+    end loop;
+    ot := inp;
+  end P1;   
+  procedure P2(inp : bit_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out bit_vector) is
+  begin
+    for i in 0 to 3 loop
+      assert(inp(i) = '0') report"wrong initialization of S2" severity error;
+    end loop;
+    ot := inp;
+  end P2;
+  procedure P3(inp : string; a:integer; b:integer; c:integer; d:integer; e:integer; ot:out string) is
+  begin
+    for i in 1 to 7 loop
+      assert(inp(i) = 's') report"wrong initialization of S3" severity error;
+    end loop;
+    ot := inp;
+  end P3;
+  procedure P4(inp : severity_level_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out severity_level_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = note) report"wrong initialization of S4" severity error;
+    end loop;
+    ot := inp;
+  end P4;
+  procedure P5(inp : integer_vector;  a:integer; b:integer; c:integer; d:integer; e:integer;ot:out integer_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3) report"wrong initialization of S5" severity error;
+    end loop;
+    ot := inp;
+  end P5;
+  procedure P6(inp : real_vector;  a:integer; b:integer; c:integer; d:integer; e:integer;ot:out real_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
+    end loop;
+    ot := inp;
+  end P6;
+  procedure P7(inp : time_vector;  a:integer; b:integer; c:integer; d:integer; e:integer;ot:out time_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
+    end loop;
+    ot := inp;
+  end P7;
+  procedure P8(inp : natural_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out natural_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S8" severity error;
+    end loop;
+    ot :=  inp;
+  end P8;
+  procedure P9(inp : positive_vector; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out positive_vector) is
+  begin
+    for i in 0 to 15 loop
+      assert(inp(i) = 1) report"wrong initialization of S9" severity error;
+    end loop;
+    ot := inp;
+  end P9;
+  procedure P10(inp : array_rec_std; a:integer; b:integer; c:integer; d:integer; e:integer;ot:out array_rec_std) is
+  begin
+    for i in 0 to 7 loop
+      assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
+    end loop;
+    ot :=  inp;
+  end P10;
+end c01s01b01x01p05n02i00748pkg;
+
+use work.c01s01b01x01p05n02i00748pkg.all;
+ENTITY c01s01b01x01p05n02i00748ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "sssssss";
+    C11 : bit_vector    := B"0000";
+    C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
+    );
+  port(
+    S1 : boolean_vector(zero to fifteen)    := (others => C1);
+    S2 : severity_level_vector(zero to fifteen)    := (others => C4);
+    S3 : integer_vector(zero to fifteen)   := (others => C5);
+    S4 : real_vector(zero to fifteen)   := (others => C6);
+    S5 : time_vector (zero to fifteen)   := (others => C7);
+    S6 : natural_vector(zero to fifteen)   := (others => C8);
+    S7 : positive_vector(zero to fifteen)   := (others => C9);
+    S8 : string(one to seven)      := C10;
+    S9 : bit_vector(zero to three)      := C11;
+    S48: array_rec_std(zero to seven)   := (others => C48)
+    );
+END c01s01b01x01p05n02i00748ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00748arch OF c01s01b01x01p05n02i00748ent IS
+BEGIN
+  TESTING: PROCESS
+
+    variable var1 : boolean_vector(zero to fifteen);
+    variable var4 : severity_level_vector(zero to fifteen);
+    variable var5 : integer_vector(zero to fifteen);
+    variable var6 : real_vector(zero to fifteen);
+    variable var7 : time_vector(zero to fifteen);
+    variable var8 : natural_vector(zero to fifteen);
+    variable var9 : positive_vector(zero to fifteen);
+    variable var2 : bit_vector(zero to three);
+    variable var3 : string(one to seven);
+    variable var48: array_rec_std(zero to seven);
+
+  BEGIN
+    P1(S1,zero,one,three,seven,fifteen,var1);
+    P2(S9,zero,one,three,seven,fifteen,var2);
+    P3(S8,zero,one,three,seven,fifteen,var3);
+    P4(S2,zero,one,three,seven,fifteen,var4);
+    P5(S3,zero,one,three,seven,fifteen,var5);
+    P6(S4,zero,one,three,seven,fifteen,var6);
+    P7(S5,zero,one,three,seven,fifteen,var7);
+    P8(S6,zero,one,three,seven,fifteen,var8);
+    P9(S7,zero,one,three,seven,fifteen,var9);
+    P10(S48,zero,one,three,seven,fifteen,var48);
+    wait for 1 ns;
+
+    assert(var1(0) = true)    report"wrong assignment of S1" severity error;
+    assert(var2(0) = '0')    report"wrong assignment of S2" severity error;
+    assert(var3(1) = 's')    report"wrong assignment of S3" severity error;
+    assert(var4(0) = note)    report"wrong assignment of S4" severity error;
+    assert(var5(0) = 3)    report"wrong assignment of S5" severity error;
+    assert(var6(0) = 3.0)    report"wrong assignment of S6" severity error;
+    assert(var7(0) = 3 ns)    report"wrong assignment of S7" severity error;
+    assert(var8(0) = 1)    report"wrong assignment of S8" severity error;
+    assert(var9(0) = 1)    report"wrong assignment of S9" severity error;
+    assert(var48(0) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000"))    report"wrong assignment of S10" severity error;
+
+    assert NOT(    (var1(0) = true)   and
+                   (var2(0) = '0')    and
+                   (var3(1) = 's')    and
+                   (var4(0) = note)    and
+                   (var5(0) = 3)       and
+                   (var6(0) = 3.0)    and
+                   (var7(0) = 3 ns)    and
+                   (var8(0) = 1)       and
+                   (var9(0) = 1)       and
+                   (var48(0) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) )
+      report "***PASSED TEST: c01s01b01x01p05n02i00748"
+      severity NOTE;
+    assert (    (var1(0) = true)   and
+                (var2(0) = '0')    and
+                (var3(1) = 's')    and
+                (var4(0) = note)    and
+                (var5(0) = 3)       and
+                (var6(0) = 3.0)    and
+                (var7(0) = 3 ns)    and
+                (var8(0) = 1)       and
+                (var9(0) = 1)       and
+                (var48(0) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) )
+      report "***FAILED TEST: c01s01b01x01p05n02i00748 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00748arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc749.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc749.vhd
new file mode 100644
index 0000000..099d1fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc749.vhd
@@ -0,0 +1,527 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc749.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00749ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean    := true;
+    C2 : bit       := '1';
+    C3 : character    := 's';
+    C4 : severity_level:= note;
+    C5 : integer    := 3;
+    C6 : real       := 3.0;
+    C7 : time       := 3 ns;
+    C8 : natural    := 1;
+    C9 : positive    := 1;
+    C10 : string    := "shishir";
+    C11 : bit_vector    := B"0011"
+    );
+END c01s01b01x01p05n02i00749ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00749arch OF c01s01b01x01p05n02i00749ent IS
+  subtype hi_to_low_range    is integer range zero to seven;
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  subtype boolean_vector_st    is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st    is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st    is  integer_vector(zero to fifteen);
+  subtype real_vector_st    is  real_vector(zero to fifteen);
+  subtype time_vector_st    is  time_vector(zero to fifteen);
+  subtype natural_vector_st    is  natural_vector(zero to fifteen);
+  subtype positive_vector_st    is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector    is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector    is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector    is array (fifteen downto zero) of integer;
+  type real_cons_vector    is array (fifteen downto zero) of real;
+  type time_cons_vector    is array (fifteen downto zero) of time;
+  type natural_cons_vector    is array (fifteen downto zero) of natural;
+  type positive_cons_vector    is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector    is array (zero to fifteen) of boolean_cons_vector;   
+  type severity_level_cons_vectorofvector    is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (zero to fifteen) of integer_cons_vector
+    ;
+  type real_cons_vectorofvector    is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector    is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (zero to fifteen) of natural_cons_vector;   
+  type positive_cons_vectorofvector    is array (zero to fifteen) of positive_cons_vector;
+  
+  type record_std_package is record
+                               a:boolean;
+                               b:bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range    is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range    is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range    is integer_vector(hi_to_low_range);
+  subtype real_vector_range       is real_vector(hi_to_low_range);
+  subtype time_vector_range       is time_vector(hi_to_low_range);
+  subtype natural_vector_range    is natural_vector(hi_to_low_range);
+  subtype positive_vector_range    is positive_vector(hi_to_low_range);
+
+  type array_rec_std    is array (integer range <>) of record_std_package;
+  type array_rec_cons    is array (integer range <>) of record_cons_array;
+  type array_rec_rec    is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st    is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st    is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st    is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+  
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                            --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  type primary_memory_module is                                           --record with field
+    record                                                                  --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;         --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12 : boolean_vector    := (C1,false);
+  constant C13 : severity_level_vector    := (C4,error);
+  constant C14 : integer_vector    := (one,two,three,four);
+  constant C15 : real_vector    := (1.0,2.0,C6,4.0);
+  constant C16 : time_vector    := (1 ns, 2 ns,C7, 4 ns);
+  constant C17 : natural_vector    := (one,2,3,4);
+  constant C18 : positive_vector    := (one,2,3,4);
+  constant C19 : boolean_cons_vector    := (others => C1);
+  constant C20 : severity_level_cons_vector    := (others => C4);
+  constant C21 : integer_cons_vector    := (others => C5);
+  constant C22 : real_cons_vector    := (others => C6);
+  constant C23 : time_cons_vector    :=  (others => C7);
+  constant C24 : natural_cons_vector    :=  (others => C8);
+  constant C25 : positive_cons_vector    :=  (others => C9);
+  constant C26 : boolean_cons_vectorofvector    := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector    :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector    := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector    := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector    := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector    := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector    := (others => (others => C9));
+  constant C50 : record_std_package    := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51 : record_cons_array    := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 : severity_level_vector_st   := (others => C4);
+  constant C72 : integer_vector_st:=(others => C5);
+  constant C73 : real_vector_st   :=(others => C6);
+  constant C74 : time_vector_st   :=(others => C7);
+  constant C75 : natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  constant C77 : record_array_st    := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a :record_array_st    := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b: record_array_new   := (C70,C71,C72,C73,C74,C75,C76);
+  constant C55 : record_of_records:= (C50,C51,C53,C77,C54b);
+  constant C60 : byte       := (others => '0');
+  constant C61 : word       := (others =>'0' );
+  constant C64 : primary_memory    := (others => C61);
+  constant C65 : primary_memory_module    := ('1',C64);
+  constant C66 : whole_memory    := (others => C65);
+  constant C67 : current       := 1 A;
+  constant C68 : resistance    := 1 Ohm;
+  constant C69 : delay       := 2;
+  constant C78: boolean_vector_range    := (others => C1);
+  constant C79: severity_level_vector_range    := (others => C4) ;
+  constant C80: integer_vector_range    :=(others => C5) ;
+  constant C81: real_vector_range    :=(others => C6);
+  constant C82: time_vector_range    :=(others => C7);
+  constant C83: natural_vector_range    :=(others => C8);
+  constant C84: positive_vector_range    :=(others => C9);
+  constant C85: array_rec_std(0 to 7)    :=(others => C50)  ;
+  constant C86: array_rec_cons (0 to 7)    :=(others => C51);
+  constant C88: array_rec_rec(0 to 7)    :=(others => C55);
+  constant C102: record_of_arr_of_record   := (C85,C86,C88);
+
+  signal V1    : boolean_vector(zero to fifteen) ;
+  signal V2    : severity_level_vector(zero to fifteen);
+  signal V3    : integer_vector(zero to fifteen) ;
+  signal V4    : real_vector(zero to fifteen) ;
+  signal V5    : time_vector (zero to fifteen);
+  signal V6    : natural_vector(zero to fifteen);
+  signal V7    : positive_vector(zero to fifteen);
+  signal V8    : boolean_cons_vector;
+  signal V9    : severity_level_cons_vector ;
+  signal V10    : integer_cons_vector;
+  signal V11    : real_cons_vector;
+  signal V12    : time_cons_vector ;
+  signal V13    : natural_cons_vector ;
+  signal V14    : positive_cons_vector ;
+  signal V15    : boolean_cons_vectorofvector ;
+  signal V16    : severity_level_cons_vectorofvector;
+  signal V17    : integer_cons_vectorofvector;
+  signal V18    : real_cons_vectorofvector;
+  signal V19    : time_cons_vectorofvector;
+  signal V20    : natural_cons_vectorofvector;
+  signal V21    : positive_cons_vectorofvector;
+  signal V22    : record_std_package;
+  signal V23    : record_cons_array ;
+  signal V24    : record_cons_arrayofarray ;
+  signal V25    : boolean_vector_st ;
+  signal V26    : severity_level_vector_st ;
+  signal V27    : integer_vector_st ;
+  signal V28    : real_vector_st ;
+  signal V29    : time_vector_st ;
+  signal V30    : natural_vector_st ;
+  signal V31    : positive_vector_st ;
+  signal V32    : record_array_st ;
+  signal V33    : record_array_st ;
+  signal V34   : record_array_new ;
+  signal V35    : record_of_records ;
+  signal V36    : byte ;
+  signal V37    : word ;
+  signal V41   : boolean_vector_range ;
+  signal V42   : severity_level_vector_range  ;
+  signal V43   : integer_vector_range  ;
+  signal V44   : real_vector_range ;
+  signal V45   : time_vector_range  ;
+  signal V46   : natural_vector_range  ;
+  signal V47   : positive_vector_range  ;
+  signal V48   : array_rec_std(zero to seven) ;
+  signal V49   : array_rec_cons(zero to seven) ;
+  signal V50   : array_rec_rec(zero to seven) ;
+  signal V51   : record_of_arr_of_record ;
+
+BEGIN
+  V1     <= (zero to fifteen => C1);
+  V2     <= (zero to fifteen => C4);
+  V3     <= (zero to fifteen => C5);
+  V4     <= (zero to fifteen => C6);
+  V5     <= (zero to fifteen => C7);
+  V6     <= (zero to fifteen => C8);
+  V7     <= (zero to fifteen => C9);
+  V8     <= C19;
+  V9     <= C20;
+  V10     <= C21;
+  V11     <= C22;
+  V12     <= C23;
+  V13     <= C24;
+  V14     <= C25;
+  V15     <= C26;
+  V16     <= C27;
+  V17     <= C28;
+  V18     <= C29;
+  V19     <= C30;
+  V20     <= C31;
+  V21     <= C32;
+  V22     <= C50;
+  V23     <= C51;
+  V24     <= C53;
+  V25     <= C70;
+  V26     <= C71;
+  V27     <= C72;
+  V28     <= C73;
+  V29     <= C74;
+  V30     <= C75;
+  V31     <= C76;
+  V32     <= C54a;
+  V33     <= C54a;
+  V34    <= C54b;
+  V35     <= C55;
+  V36     <= C60;
+  V37     <= C61;
+  V41    <= C78;
+  V42    <= C79;
+  V43    <= C80;
+  V44    <= C81;
+  V45    <= C82;
+  V46    <= C83;
+  V47    <= C84;
+  V48    <= C85;
+  V49    <= C86;
+  V50    <= C88;
+  V51    <= C102;
+
+  TESTING: PROCESS
+  BEGIN
+
+    wait for 1 ns;
+
+    assert (V1(0) = C1)    report " error in initializing S1" severity error;
+    assert (V2(0) = C4)    report " error in initializing S2" severity error;
+    assert (V3(0) = C5)    report " error in initializing S3" severity error;
+    assert (V4(0) = C6)    report " error in initializing S4" severity error;
+    assert (V5(0) = C7)    report " error in initializing S5" severity error;
+    assert (V6(0) = C8)    report " error in initializing S6" severity error;
+    assert (V7(0) = C9)    report " error in initializing S7" severity error;
+    assert V8 = C19    report " error in initializing S8" severity error;
+    assert V9 = C20    report " error in initializing S9" severity error;
+    assert V10 = C21    report " error in initializing S10" severity error;
+    assert V11 = C22    report " error in initializing S11" severity error;
+    assert V12 = C23    report " error in initializing S12" severity error;
+    assert V13 = C24    report " error in initializing S13" severity error;
+    assert V14 = C25    report " error in initializing S14" severity error;
+    assert V15 = C26    report " error in initializing S15" severity error;
+    assert V16 = C27    report " error in initializing S16" severity error;
+    assert V17 = C28    report " error in initializing S17" severity error;
+    assert V18 = C29    report " error in initializing S18" severity error;
+    assert V19 = C30    report " error in initializing S19" severity error;
+    assert V20 = C31    report " error in initializing S20" severity error;
+    assert V21 = C32    report " error in initializing S21" severity error;
+    assert V22 = C50    report " error in initializing S22" severity error;
+    assert V23 = C51    report " error in initializing S23" severity error;
+    assert V24 = C53     report " error in initializing S24" severity error;
+    assert V25 = C70     report " error in initializing S25" severity error;
+    assert V26 = C71    report " error in initializing S26" severity error;
+    assert V27 = C72    report " error in initializing S27" severity error;
+    assert V28 = C73    report " error in initializing S28" severity error;
+    assert V29 = C74    report " error in initializing S29" severity error;
+    assert V30 = C75    report " error in initializing S30" severity error;
+    assert V31 = C76    report " error in initializing S31" severity error;
+    assert V32 = C54a    report " error in initializing S32" severity error;
+    assert V33 = C54a    report " error in initializing S33" severity error;
+    assert V34= C54b    report " error in initializing S34" severity error;
+    assert V35 = C55    report " error in initializing S35" severity error;
+    assert V36 = C60    report " error in initializing S36" severity error;
+    assert V37 = C61    report " error in initializing S37" severity error;
+    assert V41= C78    report " error in initializing S41" severity error;
+    assert V42= C79    report " error in initializing S42" severity error;
+    assert V43= C80    report " error in initializing S43" severity error;
+    assert V44= C81     report " error in initializing S44" severity error;
+    assert V45= C82    report " error in initializing S45" severity error;
+    assert V46= C83    report " error in initializing S46" severity error;
+    assert V47= C84    report " error in initializing S47" severity error;
+    assert V48= C85    report " error in initializing S48" severity error;
+    assert V49= C86    report " error in initializing S49" severity error;
+    assert V50= C88    report " error in initializing S50" severity error;
+    assert V51= C102    report " error in initializing S51" severity error;
+
+    assert NOT(    (V1(0) = C1)    and 
+                   (V2(0) = C4)    and 
+                   (V3(0) = C5)    and 
+                   (V4(0) = C6)    and 
+                   (V5(0) = C7)    and 
+                   (V6(0) = C8)    and 
+                   (V7(0) = C9)    and 
+                   V8 = C19    and 
+                   V9 = C20    and 
+                   V10 = C21    and 
+                   V11 = C22    and 
+                   V12 = C23    and 
+                   V13 = C24    and 
+                   V14 = C25    and 
+                   V15 = C26    and 
+                   V16 = C27    and 
+                   V17 = C28    and 
+                   V18 = C29    and 
+                   V19 = C30    and 
+                   V20 = C31    and 
+                   V21 = C32    and
+                   V22 = C50    and
+                   V23 = C51    and
+                   V24 = C53     and
+                   V25 = C70     and
+                   V26 = C71    and
+                   V27 = C72    and
+                   V28 = C73    and
+                   V29 = C74    and
+                   V30 = C75    and
+                   V31 = C76    and
+                   V32 = C54a    and
+                   V33 = C54a    and
+                   V34= C54b    and
+                   V35 = C55    and
+                   V36 = C60    and
+                   V37 = C61    and
+                   V41= C78    and
+                   V42= C79    and
+                   V43= C80    and
+                   V44= C81     and
+                   V45= C82    and
+                   V46= C83    and 
+                   V47= C84    and 
+                   V48= C85    and 
+                   V49= C86    and 
+                   V50= C88    and 
+                   V51= C102    )   
+      report "***PASSED TEST: c01s01b01x01p05n02i00749"
+      severity NOTE;
+    assert (    (V1(0) = C1)    and 
+                (V2(0) = C4)    and 
+                (V3(0) = C5)    and 
+                (V4(0) = C6)    and 
+                (V5(0) = C7)    and 
+                (V6(0) = C8)    and 
+                (V7(0) = C9)    and 
+                V8 = C19    and 
+                V9 = C20    and 
+                V10 = C21    and 
+                V11 = C22    and 
+                V12 = C23    and 
+                V13 = C24    and 
+                V14 = C25    and 
+                V15 = C26    and 
+                V16 = C27    and 
+                V17 = C28    and 
+                V18 = C29    and 
+                V19 = C30    and 
+                V20 = C31    and 
+                V21 = C32    and
+                V22 = C50    and
+                V23 = C51    and
+                V24 = C53     and
+                V25 = C70     and
+                V26 = C71    and
+                V27 = C72    and
+                V28 = C73    and
+                V29 = C74    and
+                V30 = C75    and
+                V31 = C76    and
+                V32 = C54a    and
+                V33 = C54a    and
+                V34= C54b    and
+                V35 = C55    and
+                V36 = C60    and
+                V37 = C61    and
+                V41= C78    and
+                V42= C79    and
+                V43= C80    and
+                V44= C81     and
+                V45= C82    and
+                V46= C83    and 
+                V47= C84    and 
+                V48= C85    and 
+                V49= C86    and 
+                V50= C88    and 
+                V51= C102    )   
+      report "***FAILED TEST: c01s01b01x01p05n02i00749 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00749arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc750.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc750.vhd
new file mode 100644
index 0000000..9afa1d2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc750.vhd
@@ -0,0 +1,479 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc750.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00750ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive :=1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00750ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00750arch OF c01s01b01x01p05n02i00750ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;   
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
+    ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;   
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+  
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                            --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  type primary_memory_module is                                           --record with field
+    record                                                                  --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;         --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12 : boolean_vector := (C1,false);
+  constant C13 : severity_level_vector := (C4,error);
+  constant C14 : integer_vector := (one,two,three,four);
+  constant C15 : real_vector := (1.0,2.0,C6,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17 : natural_vector := (one,2,3,4);
+  constant C18 : positive_vector := (one,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 :  severity_level_vector_st:= (others => C4);
+  constant C72 :  integer_vector_st:=(others => C5);
+  constant C73 :  real_vector_st:=(others => C6);
+  constant C74 :  time_vector_st:=(others => C7);
+  constant C75 :  natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60 : byte := (others => '0');
+  constant C61 : word := (others =>'0' );
+  constant C64 : primary_memory := (others => C61);
+  constant C65 : primary_memory_module := ('1',C64);
+  constant C66 : whole_memory := (others => C65);
+  constant C67 : current := 1 A;
+  constant C68 : resistance := 1 Ohm;
+  constant C69 : delay := 2;
+  constant C78: boolean_vector_range := (others => C1);
+  constant C79: severity_level_vector_range := (others => C4) ;
+  constant C80: integer_vector_range :=(others => C5) ;
+  constant C81: real_vector_range :=(others => C6);
+  constant C82: time_vector_range :=(others => C7);
+  constant C83: natural_vector_range :=(others => C8);
+  constant C84: positive_vector_range :=(others => C9);
+  constant C85: array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86: array_rec_cons (0 to 7) :=(others => C51);
+  constant C88: array_rec_rec(0 to 7) :=(others => C55);
+  constant C102: record_of_arr_of_record:= (C85,C86,C88);
+
+  signal V1    : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
+  signal V2    : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
+  signal V3    : integer_vector(zero to fifteen) := (zero to fifteen => C5);
+  signal V4    : real_vector(zero to fifteen)    := (zero to fifteen => C6);
+  signal V5    : time_vector (zero to fifteen)   := (zero to fifteen => C7);
+  signal V6    : natural_vector(zero to fifteen):= (zero to fifteen => C8);
+  signal V7    : positive_vector(zero to fifteen):= (zero to fifteen => C9);
+  signal V8    : boolean_cons_vector:= C19;
+  signal V9    : severity_level_cons_vector:= C20;
+  signal V10    : integer_cons_vector:= C21;
+  signal V11    : real_cons_vector:= C22;
+  signal V12    : time_cons_vector:= C23;
+  signal V13    : natural_cons_vector := C24;
+  signal V14    : positive_cons_vector := C25;
+  signal V15    : boolean_cons_vectorofvector := C26;
+  signal V16    : severity_level_cons_vectorofvector:= C27;
+  signal V17    : integer_cons_vectorofvector:= C28;
+  signal V18    : real_cons_vectorofvector:= C29;
+  signal V19    : time_cons_vectorofvector:= C30;
+  signal V20    : natural_cons_vectorofvector:= C31;
+  signal V21    : positive_cons_vectorofvector:= C32;
+  signal V22    : record_std_package:= C50;
+  signal V23    : record_cons_array := C51;
+  signal V24    : record_cons_arrayofarray := C53 ;
+  signal V25    : boolean_vector_st := C70 ;
+  signal V26    : severity_level_vector_st:= C71;
+  signal V27    : integer_vector_st := C72;
+  signal V28    : real_vector_st := C73;
+  signal V29    : time_vector_st := C74;
+  signal V30    : natural_vector_st := C75;
+  signal V31    : positive_vector_st := C76;
+  signal V32    : record_array_st := C54a;
+  signal V33    : record_array_st := C54a;
+  signal V34   : record_array_new:= C54b;
+  signal V35    : record_of_records := C55;
+  signal V36    : byte    := C60;
+  signal V37    : word    := C61;
+  signal V41   : boolean_vector_range    := C78;
+  signal V42   : severity_level_vector_range := C79;
+  signal V43   : integer_vector_range  := C80;
+  signal V44   : real_vector_range:= C81 ;
+  signal V45   : time_vector_range  := C82;
+  signal V46   : natural_vector_range  := C83;
+  signal V47   : positive_vector_range  := C84;
+  signal V48   : array_rec_std(zero to seven)    := C85;
+  signal V49   : array_rec_cons(zero to seven) := C86;
+  signal V50   : array_rec_rec(zero to seven)    := C88;
+  signal V51   : record_of_arr_of_record    := C102;
+
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+
+    wait for 1 ns;
+
+    assert (V1(0) = C1)    report " error in initializing S1" severity error;
+    assert (V2(0) = C4)    report " error in initializing S2" severity error;
+    assert (V3(0) = C5)    report " error in initializing S3" severity error;
+    assert (V4(0) = C6)    report " error in initializing S4" severity error;
+    assert (V5(0) = C7)    report " error in initializing S5" severity error;
+    assert (V6(0) = C8)    report " error in initializing S6" severity error;
+    assert (V7(0) = C9)    report " error in initializing S7" severity error;
+    assert V8 = C19    report " error in initializing S8" severity error;
+    assert V9 = C20    report " error in initializing S9" severity error;
+    assert V10 = C21    report " error in initializing S10" severity error;
+    assert V11 = C22    report " error in initializing S11" severity error;
+    assert V12 = C23    report " error in initializing S12" severity error;
+    assert V13 = C24    report " error in initializing S13" severity error;
+    assert V14 = C25    report " error in initializing S14" severity error;
+    assert V15 = C26    report " error in initializing S15" severity error;
+    assert V16 = C27    report " error in initializing S16" severity error;
+    assert V17 = C28    report " error in initializing S17" severity error;
+    assert V18 = C29    report " error in initializing S18" severity error;
+    assert V19 = C30    report " error in initializing S19" severity error;
+    assert V20 = C31    report " error in initializing S20" severity error;
+    assert V21 = C32    report " error in initializing S21" severity error;
+    assert V22 = C50    report " error in initializing S22" severity error;
+    assert V23 = C51    report " error in initializing S23" severity error;
+    assert V24 = C53     report " error in initializing S24" severity error;
+    assert V25 = C70     report " error in initializing S25" severity error;
+    assert V26 = C71    report " error in initializing S26" severity error;
+    assert V27 = C72    report " error in initializing S27" severity error;
+    assert V28 = C73    report " error in initializing S28" severity error;
+    assert V29 = C74    report " error in initializing S29" severity error;
+    assert V30 = C75    report " error in initializing S30" severity error;
+    assert V31 = C76    report " error in initializing S31" severity error;
+    assert V32 = C54a    report " error in initializing S32" severity error;
+    assert V33 = C54a    report " error in initializing S33" severity error;
+    assert V34= C54b    report " error in initializing S34" severity error;
+    assert V35 = C55    report " error in initializing S35" severity error;
+    assert V36 = C60    report " error in initializing S36" severity error;
+    assert V37 = C61    report " error in initializing S37" severity error;
+    assert V41= C78    report " error in initializing S41" severity error;
+    assert V42= C79    report " error in initializing S42" severity error;
+    assert V43= C80    report " error in initializing S43" severity error;
+    assert V44= C81     report " error in initializing S44" severity error;
+    assert V45= C82    report " error in initializing S45" severity error;
+    assert V46= C83    report " error in initializing S46" severity error;
+    assert V47= C84    report " error in initializing S47" severity error;
+    assert V48= C85    report " error in initializing S48" severity error;
+    assert V49= C86    report " error in initializing S49" severity error;
+    assert V50= C88    report " error in initializing S50" severity error;
+    assert V51= C102    report " error in initializing S51" severity error;
+
+    assert NOT(    (V1(0) = C1)    and 
+                   (V2(0) = C4)    and 
+                   (V3(0) = C5)    and 
+                   (V4(0) = C6)    and 
+                   (V5(0) = C7)    and 
+                   (V6(0) = C8)    and 
+                   (V7(0) = C9)    and 
+                   V8 = C19    and 
+                   V9 = C20    and 
+                   V10 = C21    and 
+                   V11 = C22    and 
+                   V12 = C23    and 
+                   V13 = C24    and 
+                   V14 = C25    and 
+                   V15 = C26    and 
+                   V16 = C27    and 
+                   V17 = C28    and 
+                   V18 = C29    and 
+                   V19 = C30    and 
+                   V20 = C31    and 
+                   V21 = C32    and 
+                   V22 = C50    and 
+                   V23 = C51    and 
+                   V24 = C53     and 
+                   V25 = C70     and 
+                   V26 = C71    and 
+                   V27 = C72    and 
+                   V28 = C73    and 
+                   V29 = C74    and 
+                   V30 = C75    and 
+                   V31 = C76    and 
+                   V32 = C54a    and 
+                   V33 = C54a    and 
+                   V34= C54b    and 
+                   V35 = C55    and 
+                   V36 = C60    and 
+                   V37 = C61    and 
+                   V41= C78    and 
+                   V42= C79    and 
+                   V43= C80    and 
+                   V44= C81     and 
+                   V45= C82    and 
+                   V46= C83    and 
+                   V47= C84    and 
+                   V48= C85    and 
+                   V49= C86    and 
+                   V50= C88    and 
+                   V51= C102    ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00750"
+      severity NOTE;
+    assert (    (V1(0) = C1)    and 
+                (V2(0) = C4)    and 
+                (V3(0) = C5)    and 
+                (V4(0) = C6)    and 
+                (V5(0) = C7)    and 
+                (V6(0) = C8)    and 
+                (V7(0) = C9)    and 
+                V8 = C19    and 
+                V9 = C20    and 
+                V10 = C21    and 
+                V11 = C22    and 
+                V12 = C23    and 
+                V13 = C24    and 
+                V14 = C25    and 
+                V15 = C26    and 
+                V16 = C27    and 
+                V17 = C28    and 
+                V18 = C29    and 
+                V19 = C30    and 
+                V20 = C31    and 
+                V21 = C32    and 
+                V22 = C50    and 
+                V23 = C51    and 
+                V24 = C53     and 
+                V25 = C70     and 
+                V26 = C71    and 
+                V27 = C72    and 
+                V28 = C73    and 
+                V29 = C74    and 
+                V30 = C75    and 
+                V31 = C76    and 
+                V32 = C54a    and 
+                V33 = C54a    and 
+                V34= C54b    and 
+                V35 = C55    and 
+                V36 = C60    and 
+                V37 = C61    and 
+                V41= C78    and 
+                V42= C79    and 
+                V43= C80    and 
+                V44= C81     and 
+                V45= C82    and 
+                V46= C83    and 
+                V47= C84    and 
+                V48= C85    and 
+                V49= C86    and 
+                V50= C88    and 
+                V51= C102    ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00750 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00750arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc751.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc751.vhd
new file mode 100644
index 0000000..e3f8134
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc751.vhd
@@ -0,0 +1,526 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc751.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00751ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00751ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00751arch OF c01s01b01x01p05n02i00751ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;   
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
+    ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;   
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+  
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                            --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  type primary_memory_module is                                           --record with field
+    record                                                                  --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;         --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12 : boolean_vector := (C1,false);
+  constant C13 : severity_level_vector := (C4,error);
+  constant C14 : integer_vector := (one,two,three,four);
+  constant C15 : real_vector := (1.0,2.0,C6,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17 : natural_vector := (one,2,3,4);
+  constant C18 : positive_vector := (one,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 :  severity_level_vector_st:= (others => C4);
+  constant C72 :  integer_vector_st:=(others => C5);
+  constant C73 :  real_vector_st:=(others => C6);
+  constant C74 :  time_vector_st:=(others => C7);
+  constant C75 :  natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60 : byte := (others => '0');
+  constant C61 : word := (others =>'0' );
+  constant C64 : primary_memory := (others => C61);
+  constant C65 : primary_memory_module := ('1',C64);
+  constant C66 : whole_memory := (others => C65);
+  constant C67 : current := 1 A;
+  constant C68 : resistance := 1 Ohm;
+  constant C69 : delay := 2;
+  constant C78: boolean_vector_range := (others => C1);
+  constant C79: severity_level_vector_range := (others => C4) ;
+  constant C80: integer_vector_range :=(others => C5) ;
+  constant C81: real_vector_range :=(others => C6);
+  constant C82: time_vector_range :=(others => C7);
+  constant C83: natural_vector_range :=(others => C8);
+  constant C84: positive_vector_range :=(others => C9);
+  constant C85: array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86: array_rec_cons (0 to 7) :=(others => C51);
+  constant C88: array_rec_rec(0 to 7) :=(others => C55);
+  constant C102: record_of_arr_of_record:= (C85,C86,C88);
+
+BEGIN
+
+  TESTING: PROCESS
+    variable V1    : boolean_vector(zero to fifteen) ;
+    variable V2    : severity_level_vector(zero to fifteen);
+    variable V3    : integer_vector(zero to fifteen) ;
+    variable V4    : real_vector(zero to fifteen) ;
+    variable V5    : time_vector (zero to fifteen);
+    variable V6    : natural_vector(zero to fifteen);
+    variable V7    : positive_vector(zero to fifteen);
+    variable V8    : boolean_cons_vector;
+    variable V9    : severity_level_cons_vector ;
+    variable V10    : integer_cons_vector;
+    variable V11    : real_cons_vector;
+    variable V12    : time_cons_vector ;
+    variable V13    : natural_cons_vector ;
+    variable V14    : positive_cons_vector ;
+    variable V15    : boolean_cons_vectorofvector ;
+    variable V16    : severity_level_cons_vectorofvector;
+    variable V17    : integer_cons_vectorofvector;
+    variable V18    : real_cons_vectorofvector;
+    variable V19    : time_cons_vectorofvector;
+    variable V20    : natural_cons_vectorofvector;
+    variable V21    : positive_cons_vectorofvector;
+    variable V22    : record_std_package;
+    variable V23    : record_cons_array ;
+    variable V24    : record_cons_arrayofarray ;
+    variable V25    : boolean_vector_st ;
+    variable V26    : severity_level_vector_st ;
+    variable V27    : integer_vector_st ;
+    variable V28    : real_vector_st ;
+    variable V29    : time_vector_st ;
+    variable V30    : natural_vector_st ;
+    variable V31    : positive_vector_st ;
+    variable V32    : record_array_st ;
+    variable V33    : record_array_st ;
+    variable V34   : record_array_new ;
+    variable V35    : record_of_records ;
+    variable V36    : byte ;
+    variable V37    : word ;
+    variable V41   : boolean_vector_range ;
+    variable V42   : severity_level_vector_range  ;
+    variable V43   : integer_vector_range  ;
+    variable V44   : real_vector_range ;
+    variable V45   : time_vector_range  ;
+    variable V46   : natural_vector_range  ;
+    variable V47   : positive_vector_range  ;
+    variable V48   : array_rec_std(zero to seven) ;
+    variable V49   : array_rec_cons(zero to seven) ;
+    variable V50   : array_rec_rec(zero to seven) ;
+    variable V51   : record_of_arr_of_record ;
+
+  BEGIN
+
+    V1     := (zero to fifteen => C1);
+    V2     := (zero to fifteen => C4);
+    V3     := (zero to fifteen => C5);
+    V4     := (zero to fifteen => C6);
+    V5     := (zero to fifteen => C7);
+    V6     := (zero to fifteen => C8);
+    V7     := (zero to fifteen => C9);
+    V8     := C19;
+    V9     := C20;
+    V10     := C21;
+    V11     := C22;
+    V12     := C23;
+    V13     := C24;
+    V14     := C25;
+    V15     := C26;
+    V16     := C27;
+    V17     := C28;
+    V18     := C29;
+    V19     := C30;
+    V20     := C31;
+    V21     := C32;
+    V22     := C50;
+    V23     := C51;
+    V24     := C53;
+    V25     := C70;
+    V26     := C71;
+    V27     := C72;
+    V28     := C73;
+    V29     := C74;
+    V30     := C75;
+    V31     := C76;
+    V32     := C54a;
+    V33     := C54a;
+    V34    := C54b;
+    V35     := C55;
+    V36     := C60;
+    V37     := C61;
+    V41    := C78;
+    V42    := C79;
+    V43    := C80;
+    V44    := C81;
+    V45    := C82;
+    V46    := C83;
+    V47    := C84;
+    V48    := C85;
+    V49    := C86;
+    V50    := C88;
+    V51    := C102;
+
+    assert (V1(0) = C1)    report " error in initializing S1" severity error;
+    assert (V2(0) = C4)    report " error in initializing S2" severity error;
+    assert (V3(0) = C5)    report " error in initializing S3" severity error;
+    assert (V4(0) = C6)    report " error in initializing S4" severity error;
+    assert (V5(0) = C7)    report " error in initializing S5" severity error;
+    assert (V6(0) = C8)    report " error in initializing S6" severity error;
+    assert (V7(0) = C9)    report " error in initializing S7" severity error;
+    assert V8 = C19    report " error in initializing S8" severity error;
+    assert V9 = C20    report " error in initializing S9" severity error;
+    assert V10 = C21    report " error in initializing S10" severity error;
+    assert V11 = C22    report " error in initializing S11" severity error;
+    assert V12 = C23    report " error in initializing S12" severity error;
+    assert V13 = C24    report " error in initializing S13" severity error;
+    assert V14 = C25    report " error in initializing S14" severity error;
+    assert V15 = C26    report " error in initializing S15" severity error;
+    assert V16 = C27    report " error in initializing S16" severity error;
+    assert V17 = C28    report " error in initializing S17" severity error;
+    assert V18 = C29    report " error in initializing S18" severity error;
+    assert V19 = C30    report " error in initializing S19" severity error;
+    assert V20 = C31    report " error in initializing S20" severity error;
+    assert V21 = C32    report " error in initializing S21" severity error;
+    assert V22 = C50    report " error in initializing S22" severity error;
+    assert V23 = C51    report " error in initializing S23" severity error;
+    assert V24 = C53     report " error in initializing S24" severity error;
+    assert V25 = C70     report " error in initializing S25" severity error;
+    assert V26 = C71    report " error in initializing S26" severity error;
+    assert V27 = C72    report " error in initializing S27" severity error;
+    assert V28 = C73    report " error in initializing S28" severity error;
+    assert V29 = C74    report " error in initializing S29" severity error;
+    assert V30 = C75    report " error in initializing S30" severity error;
+    assert V31 = C76    report " error in initializing S31" severity error;
+    assert V32 = C54a    report " error in initializing S32" severity error;
+    assert V33 = C54a    report " error in initializing S33" severity error;
+    assert V34= C54b    report " error in initializing S34" severity error;
+    assert V35 = C55    report " error in initializing S35" severity error;
+    assert V36 = C60    report " error in initializing S36" severity error;
+    assert V37 = C61    report " error in initializing S37" severity error;
+    assert V41= C78    report " error in initializing S41" severity error;
+    assert V42= C79    report " error in initializing S42" severity error;
+    assert V43= C80    report " error in initializing S43" severity error;
+    assert V44= C81     report " error in initializing S44" severity error;
+    assert V45= C82    report " error in initializing S45" severity error;
+    assert V46= C83    report " error in initializing S46" severity error;
+    assert V47= C84    report " error in initializing S47" severity error;
+    assert V48= C85    report " error in initializing S48" severity error;
+    assert V49= C86    report " error in initializing S49" severity error;
+    assert V50= C88    report " error in initializing S50" severity error;
+    assert V51= C102    report " error in initializing S51" severity error;
+
+    assert NOT(    (V1(0) = C1)    and 
+                   (V2(0) = C4)    and 
+                   (V3(0) = C5)    and 
+                   (V4(0) = C6)    and 
+                   (V5(0) = C7)    and 
+                   (V6(0) = C8)    and 
+                   (V7(0) = C9)    and 
+                   V8 = C19    and 
+                   V9 = C20    and 
+                   V10 = C21    and 
+                   V11 = C22    and 
+                   V12 = C23    and 
+                   V13 = C24    and 
+                   V14 = C25    and 
+                   V15 = C26    and 
+                   V16 = C27    and 
+                   V17 = C28    and 
+                   V18 = C29    and 
+                   V19 = C30    and 
+                   V20 = C31    and 
+                   V21 = C32    and 
+                   V22 = C50    and 
+                   V23 = C51    and 
+                   V24 = C53     and 
+                   V25 = C70     and 
+                   V26 = C71    and 
+                   V27 = C72    and 
+                   V28 = C73    and 
+                   V29 = C74    and 
+                   V30 = C75    and 
+                   V31 = C76    and 
+                   V32 = C54a    and 
+                   V33 = C54a    and 
+                   V34= C54b    and 
+                   V35 = C55    and 
+                   V36 = C60    and 
+                   V37 = C61    and 
+                   V41= C78    and 
+                   V42= C79    and 
+                   V43= C80    and 
+                   V44= C81     and 
+                   V45= C82    and 
+                   V46= C83    and 
+                   V47= C84    and 
+                   V48= C85    and 
+                   V49= C86    and 
+                   V50= C88    and 
+                   V51= C102    ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00751"
+      severity NOTE;
+    assert (    (V1(0) = C1)    and 
+                (V2(0) = C4)    and 
+                (V3(0) = C5)    and 
+                (V4(0) = C6)    and 
+                (V5(0) = C7)    and 
+                (V6(0) = C8)    and 
+                (V7(0) = C9)    and 
+                V8 = C19    and 
+                V9 = C20    and 
+                V10 = C21    and 
+                V11 = C22    and 
+                V12 = C23    and 
+                V13 = C24    and 
+                V14 = C25    and 
+                V15 = C26    and 
+                V16 = C27    and 
+                V17 = C28    and 
+                V18 = C29    and 
+                V19 = C30    and 
+                V20 = C31    and 
+                V21 = C32    and 
+                V22 = C50    and 
+                V23 = C51    and 
+                V24 = C53     and 
+                V25 = C70     and 
+                V26 = C71    and 
+                V27 = C72    and 
+                V28 = C73    and 
+                V29 = C74    and 
+                V30 = C75    and 
+                V31 = C76    and 
+                V32 = C54a    and 
+                V33 = C54a    and 
+                V34= C54b    and 
+                V35 = C55    and 
+                V36 = C60    and 
+                V37 = C61    and 
+                V41= C78    and 
+                V42= C79    and 
+                V43= C80    and 
+                V44= C81     and 
+                V45= C82    and 
+                V46= C83    and 
+                V47= C84    and 
+                V48= C85    and 
+                V49= C86    and 
+                V50= C88    and 
+                V51= C102    ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00751 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00751arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc752.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc752.vhd
new file mode 100644
index 0000000..8d5ddb1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc752.vhd
@@ -0,0 +1,476 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc752.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00752ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00752ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00752arch OF c01s01b01x01p05n02i00752ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;   
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
+    ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;   
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+  
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                            --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  type primary_memory_module is                                           --record with field
+    record                                                                  --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;         --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12 : boolean_vector := (C1,false);
+  constant C13 : severity_level_vector := (C4,error);
+  constant C14 : integer_vector := (one,two,three,four);
+  constant C15 : real_vector := (1.0,2.0,C6,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17 : natural_vector := (one,2,3,4);
+  constant C18 : positive_vector := (one,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 :  severity_level_vector_st:= (others => C4);
+  constant C72 :  integer_vector_st:=(others => C5);
+  constant C73 :  real_vector_st:=(others => C6);
+  constant C74 :  time_vector_st:=(others => C7);
+  constant C75 :  natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60 : byte := (others => '0');
+  constant C61 : word := (others =>'0' );
+  constant C64 : primary_memory := (others => C61);
+  constant C65 : primary_memory_module := ('1',C64);
+  constant C66 : whole_memory := (others => C65);
+  constant C67 : current := 1 A;
+  constant C68 : resistance := 1 Ohm;
+  constant C69 : delay := 2;
+  constant C78: boolean_vector_range := (others => C1);
+  constant C79: severity_level_vector_range := (others => C4) ;
+  constant C80: integer_vector_range :=(others => C5) ;
+  constant C81: real_vector_range :=(others => C6);
+  constant C82: time_vector_range :=(others => C7);
+  constant C83: natural_vector_range :=(others => C8);
+  constant C84: positive_vector_range :=(others => C9);
+  constant C85: array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86: array_rec_cons (0 to 7) :=(others => C51);
+  constant C88: array_rec_rec(0 to 7) :=(others => C55);
+  constant C102: record_of_arr_of_record:= (C85,C86,C88);
+
+BEGIN
+
+  TESTING: PROCESS
+    variable V1    : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
+    variable V2    : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
+    variable V3    : integer_vector(zero to fifteen) := (zero to fifteen => C5);
+    variable V4    : real_vector(zero to fifteen)    := (zero to fifteen => C6);
+    variable V5    : time_vector (zero to fifteen)   := (zero to fifteen => C7);
+    variable V6    : natural_vector(zero to fifteen):= (zero to fifteen => C8);
+    variable V7    : positive_vector(zero to fifteen):= (zero to fifteen => C9);
+    variable V8    : boolean_cons_vector:= C19;
+    variable V9    : severity_level_cons_vector := C20;
+    variable V10    : integer_cons_vector:= C21;
+    variable V11    : real_cons_vector:= C22;
+    variable V12    : time_cons_vector := C23;
+    variable V13    : natural_cons_vector := C24;
+    variable V14    : positive_cons_vector := C25;
+    variable V15    : boolean_cons_vectorofvector := C26;
+    variable V16    : severity_level_cons_vectorofvector:= C27;
+    variable V17    : integer_cons_vectorofvector:= C28;
+    variable V18    : real_cons_vectorofvector:= C29;
+    variable V19    : time_cons_vectorofvector:= C30;
+    variable V20    : natural_cons_vectorofvector:= C31;
+    variable V21    : positive_cons_vectorofvector:= C32;
+    variable V22    : record_std_package:= C50;
+    variable V23    : record_cons_array := C51;
+    variable V24    : record_cons_arrayofarray := C53 ;
+    variable V25    : boolean_vector_st:= C70 ;
+    variable V26    :  severity_level_vector_st := C71;
+    variable V27    :  integer_vector_st:= C72;
+    variable V28    :  real_vector_st := C73;
+    variable V29    :  time_vector_st := C74;
+    variable V30    :  natural_vector_st:= C75;
+    variable V31    : positive_vector_st := C76;
+    variable V32    : record_array_st := C54a;
+    variable V33    : record_array_st := C54a;
+    variable V34   : record_array_new:= C54b;
+    variable V35    : record_of_records := C55;
+    variable V36    : byte    := C60;
+    variable V37    : word    := C61;
+    variable V41   : boolean_vector_range    := C78;
+    variable V42   : severity_level_vector_range     := C79;
+    variable V43   : integer_vector_range  := C80;
+    variable V44   : real_vector_range:= C81 ;
+    variable V45   : time_vector_range := C82;
+    variable V46   : natural_vector_range    := C83;
+    variable V47   : positive_vector_range  := C84;
+    variable V48   : array_rec_std(zero to seven)    := C85;
+    variable V49   : array_rec_cons(zero to seven) := C86;
+    variable V50   : array_rec_rec(zero to seven)    := C88;
+    variable V51   : record_of_arr_of_record    := C102;
+  BEGIN
+
+    assert (V1(0) = C1)    report " error in initializing S1" severity error;
+    assert (V2(0) = C4)    report " error in initializing S2" severity error;
+    assert (V3(0) = C5)    report " error in initializing S3" severity error;
+    assert (V4(0) = C6)    report " error in initializing S4" severity error;
+    assert (V5(0) = C7)    report " error in initializing S5" severity error;
+    assert (V6(0) = C8)    report " error in initializing S6" severity error;
+    assert (V7(0) = C9)    report " error in initializing S7" severity error;
+    assert V8 = C19    report " error in initializing S8" severity error;
+    assert V9 = C20    report " error in initializing S9" severity error;
+    assert V10 = C21    report " error in initializing S10" severity error;
+    assert V11 = C22    report " error in initializing S11" severity error;
+    assert V12 = C23    report " error in initializing S12" severity error;
+    assert V13 = C24    report " error in initializing S13" severity error;
+    assert V14 = C25    report " error in initializing S14" severity error;
+    assert V15 = C26    report " error in initializing S15" severity error;
+    assert V16 = C27    report " error in initializing S16" severity error;
+    assert V17 = C28    report " error in initializing S17" severity error;
+    assert V18 = C29    report " error in initializing S18" severity error;
+    assert V19 = C30    report " error in initializing S19" severity error;
+    assert V20 = C31    report " error in initializing S20" severity error;
+    assert V21 = C32    report " error in initializing S21" severity error;
+    assert V22 = C50    report " error in initializing S22" severity error;
+    assert V23 = C51    report " error in initializing S23" severity error;
+    assert V24 = C53     report " error in initializing S24" severity error;
+    assert V25 = C70     report " error in initializing S25" severity error;
+    assert V26 = C71    report " error in initializing S26" severity error;
+    assert V27 = C72    report " error in initializing S27" severity error;
+    assert V28 = C73    report " error in initializing S28" severity error;
+    assert V29 = C74    report " error in initializing S29" severity error;
+    assert V30 = C75    report " error in initializing S30" severity error;
+    assert V31 = C76    report " error in initializing S31" severity error;
+    assert V32 = C54a    report " error in initializing S32" severity error;
+    assert V33 = C54a    report " error in initializing S33" severity error;
+    assert V34 = C54b    report " error in initializing S34" severity error;
+    assert V35 = C55    report " error in initializing S35" severity error;
+    assert V36 = C60    report " error in initializing S36" severity error;
+    assert V37 = C61    report " error in initializing S37" severity error;
+    assert V41= C78    report " error in initializing S41" severity error;
+    assert V42= C79    report " error in initializing S42" severity error;
+    assert V43= C80    report " error in initializing S43" severity error;
+    assert V44= C81     report " error in initializing S44" severity error;
+    assert V45= C82    report " error in initializing S45" severity error;
+    assert V46= C83    report " error in initializing S46" severity error;
+    assert V47= C84    report " error in initializing S47" severity error;
+    assert V48= C85    report " error in initializing S48" severity error;
+    assert V49= C86    report " error in initializing S49" severity error;
+    assert V50= C88    report " error in initializing S50" severity error;
+    assert V51= C102    report " error in initializing S51" severity error;
+
+    assert NOT(    (V1(0) = C1)    and 
+                   (V2(0) = C4)    and 
+                   (V3(0) = C5)    and 
+                   (V4(0) = C6)    and 
+                   (V5(0) = C7)    and 
+                   (V6(0) = C8)    and 
+                   (V7(0) = C9)    and 
+                   V8 = C19    and 
+                   V9 = C20    and 
+                   V10 = C21    and 
+                   V11 = C22    and 
+                   V12 = C23    and 
+                   V13 = C24    and 
+                   V14 = C25    and 
+                   V15 = C26    and 
+                   V16 = C27    and 
+                   V17 = C28    and 
+                   V18 = C29    and 
+                   V19 = C30    and 
+                   V20 = C31    and 
+                   V21 = C32    and 
+                   V22 = C50    and 
+                   V23 = C51    and 
+                   V24 = C53     and 
+                   V25 = C70     and 
+                   V26 = C71    and 
+                   V27 = C72    and 
+                   V28 = C73    and 
+                   V29 = C74    and 
+                   V30 = C75    and 
+                   V31 = C76    and 
+                   V32 = C54a    and 
+                   V33 = C54a    and 
+                   V34= C54b    and 
+                   V35 = C55    and 
+                   V36 = C60    and 
+                   V37 = C61    and 
+                   V41= C78    and 
+                   V42= C79    and 
+                   V43= C80    and 
+                   V44= C81     and 
+                   V45= C82    and 
+                   V46= C83    and 
+                   V47= C84    and 
+                   V48= C85    and 
+                   V49= C86    and 
+                   V50= C88    and 
+                   V51= C102    ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00752"
+      severity NOTE;
+    assert (    (V1(0) = C1)    and 
+                (V2(0) = C4)    and 
+                (V3(0) = C5)    and 
+                (V4(0) = C6)    and 
+                (V5(0) = C7)    and 
+                (V6(0) = C8)    and 
+                (V7(0) = C9)    and 
+                V8 = C19    and 
+                V9 = C20    and 
+                V10 = C21    and 
+                V11 = C22    and 
+                V12 = C23    and 
+                V13 = C24    and 
+                V14 = C25    and 
+                V15 = C26    and 
+                V16 = C27    and 
+                V17 = C28    and 
+                V18 = C29    and 
+                V19 = C30    and 
+                V20 = C31    and 
+                V21 = C32    and 
+                V22 = C50    and 
+                V23 = C51    and 
+                V24 = C53     and 
+                V25 = C70     and 
+                V26 = C71    and 
+                V27 = C72    and 
+                V28 = C73    and 
+                V29 = C74    and 
+                V30 = C75    and 
+                V31 = C76    and 
+                V32 = C54a    and 
+                V33 = C54a    and 
+                V34= C54b    and 
+                V35 = C55    and 
+                V36 = C60    and 
+                V37 = C61    and 
+                V41= C78    and 
+                V42= C79    and 
+                V43= C80    and 
+                V44= C81     and 
+                V45= C82    and 
+                V46= C83    and 
+                V47= C84    and 
+                V48= C85    and 
+                V49= C86    and 
+                V50= C88    and 
+                V51= C102    ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00752 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00752arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc753.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc753.vhd
new file mode 100644
index 0000000..5877e63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc753.vhd
@@ -0,0 +1,370 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc753.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00753pkg is
+  subtype hi_to_low_range    is integer range 0 to 7;
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is integer_vector(0 to 15);
+  subtype real_vector_st    is real_vector(0 to 15);
+  subtype time_vector_st    is time_vector(0 to 15);
+  subtype natural_vector_st    is natural_vector(0 to 15);
+  subtype positive_vector_st    is positive_vector(0 to 15);
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+  type boolean_cons_vectorofvector    is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector    is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector    is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector    is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(1 to 7);
+                               k:bit_vector(0 to 3);
+                             end record;
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  type record_array_new is record
+                             a:boolean_vector(0 to 15);
+                             b:severity_level_vector(0 to 15);
+                             c:integer_vector(0 to 15);
+                             d:real_vector(0 to 15);
+                             e:time_vector(0 to 15);
+                             f:natural_vector(0 to 15);
+                             g:positive_vector(0 to 15);
+                           end record;
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(0 to 7);
+                                    b: array_rec_cons(0 to 7);
+                                    c: array_rec_rec(0 to 7);
+                                  end record;
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(0 to 7) of bit;
+  
+  subtype word is bit_vector(0 to 15);                                 --constrained array
+  
+  constant size :integer := 7;
+  
+  type primary_memory is array(0 to size) of word;                     --array of an array
+  
+  type primary_memory_module is                                       --record with field
+    record                                                               --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;     --array of a complex record
+  subtype delay is integer range 1 to 10;
+  
+end c01s01b01x01p05n02i00753pkg;
+
+
+use work.c01s01b01x01p05n02i00753pkg.all;
+ENTITY c01s01b01x01p05n02i00753ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+  port(
+    S1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
+    S2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
+    S3 : integer_vector(zero to fifteen):= (zero to fifteen => C5);
+    S4 : real_vector(zero to fifteen):= (zero to fifteen => C6);
+    S5 : time_vector (zero to fifteen):= (zero to fifteen => C7);
+    S6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
+    S7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
+    S8 : boolean_cons_vector:= (zero to fifteen => C1);
+    S9 : severity_level_cons_vector := (zero to fifteen => C4);
+    S10 : integer_cons_vector:= (zero to fifteen => C5);
+    S11 : real_cons_vector:= (zero to fifteen => C6);
+    S12 : time_cons_vector := (zero to fifteen => C7);
+    S13 : natural_cons_vector := (zero to fifteen => C8);
+    S14 : positive_cons_vector := (zero to fifteen => C9);
+    S15 : boolean_cons_vectorofvector:= (zero to fifteen =>(others=> C1));
+    S16 : severity_level_cons_vectorofvector := (zero to fifteen =>(others=> C4));
+    S17 : integer_cons_vectorofvector := (zero to fifteen =>(others=> C5));
+    S18 : real_cons_vectorofvector := (zero to fifteen =>(others=> C6));
+    S19 : time_cons_vectorofvector := (zero to fifteen =>(others=> C7));
+    S20 : natural_cons_vectorofvector := (zero to fifteen =>(others=> C8));
+    S21 : positive_cons_vectorofvector := (zero to fifteen =>(others=> C9));
+    S22 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+    S25 : boolean_vector_st := (zero to fifteen => C1);
+    S26 : severity_level_vector_st:= (zero to fifteen => C4);
+    S27 : integer_vector_st:= (zero to fifteen => C5);
+    S28 : real_vector_st:= (zero to fifteen => C6);
+    S29 : time_vector_st:= (zero to fifteen => C7);
+    S30 : natural_vector_st:= (zero to fifteen => C8);
+    S31 : positive_vector_st:= (zero to fifteen => C9)
+    );
+END c01s01b01x01p05n02i00753ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00753arch OF c01s01b01x01p05n02i00753ent IS
+
+BEGIN
+  assert (S1(0) = C1) report " error in initializing S1" severity error;
+  assert (S2(0) = C4) report " error in initializing S2" severity error;
+  assert (S3(0) = C5) report " error in initializing S3" severity error;
+  assert (S4(0) = C6) report " error in initializing S4" severity error;
+  assert (S5(0) = C7) report " error in initializing S5" severity error;
+  assert (S6(0) = C8) report " error in initializing S6" severity error;
+  assert (S7(0) = C9) report " error in initializing S7" severity error;
+  assert (S8(0) = C1) report " error in initializing S8" severity error;
+  assert (S9(0) = C4) report " error in initializing S9" severity error;
+  assert (S10(0) = C5) report " error in initializing S10" severity error;
+  assert (S11(0) = C6) report " error in initializing S11" severity error;
+  assert (S12(0) = C7) report " error in initializing S12" severity error;
+  assert (S13(0) = C8) report " error in initializing S13" severity error;
+  assert (S14(0) = C9) report " error in initializing S14" severity error;
+  assert (S15(0)(0) = C1) report " error in initializing S15" severity error;
+  assert (S16(0)(0) = C4) report " error in initializing S16" severity error;
+  assert (S17(0)(0) = C5) report " error in initializing S17" severity error;
+  assert (S18(0)(0) = C6) report " error in initializing S18" severity error;
+  assert (S19(0)(0) = C7) report " error in initializing S19" severity error;
+  assert (S20(0)(0) = C8) report " error in initializing S20" severity error;
+  assert (S21(0)(0) = C9) report " error in initializing S21" severity error;
+  assert (S22.a = C1) report " error in initializing S21" severity error;
+  assert (S22.b = C2) report " error in initializing S21" severity error;
+  assert (S22.c = C3) report " error in initializing S21" severity error;
+  assert (S22.d = C4) report " error in initializing S21" severity error;
+  assert (S22.e = C5) report " error in initializing S21" severity error;
+  assert (S22.f = C6) report " error in initializing S21" severity error;
+  assert (S22.g = C7) report " error in initializing S21" severity error;
+  assert (S22.h = C8) report " error in initializing S21" severity error;
+  assert (S22.i = C9) report " error in initializing S21" severity error;
+  assert (S22.j = C10) report " error in initializing S21" severity error;
+  assert (S22.k = C11) report " error in initializing S21" severity error;
+  assert (S25(0) = C1) report " error in initializing S25" severity error;
+  assert (S26(0) = C4) report " error in initializing S26" severity error;
+  assert (S27(0) = C5) report " error in initializing S27" severity error;
+  assert (S28(0) = C6) report " error in initializing S28" severity error;
+  assert (S29(0) = C7) report " error in initializing S29" severity error;
+  assert (S30(0) = C8) report " error in initializing S30" severity error;
+  assert (S31(0) = C9) report " error in initializing S31" severity error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(    (S1(0) = C1)    and 
+                   (S2(0) = C4)    and 
+                   (S3(0) = C5)    and 
+                   (S4(0) = C6)    and 
+                   (S5(0) = C7)    and 
+                   (S6(0) = C8)    and 
+                   (S7(0) = C9)    and 
+                   (S8(0) = C1)    and 
+                   (S9(0) = C4)    and 
+                   (S10(0) = C5)    and 
+                   (S11(0) = C6)    and 
+                   (S12(0) = C7)    and 
+                   (S13(0) = C8)    and 
+                   (S14(0) = C9)    and 
+                   (S15(0)(0) = C1) and 
+                   (S16(0)(0) = C4) and 
+                   (S17(0)(0) = C5) and 
+                   (S18(0)(0) = C6) and 
+                   (S19(0)(0) = C7) and 
+                   (S20(0)(0) = C8) and 
+                   (S21(0)(0) = C9) and 
+                   (S22.a = C1)    and 
+                   (S22.b = C2)    and 
+                   (S22.c = C3)    and 
+                   (S22.d = C4)    and 
+                   (S22.e = C5)    and 
+                   (S22.f = C6)    and 
+                   (S22.g = C7)    and 
+                   (S22.h = C8)    and 
+                   (S22.i = C9)    and 
+                   (S22.j = C10)    and 
+                   (S22.k = C11)    and 
+                   (S25(0) = C1)    and 
+                   (S26(0) = C4)    and 
+                   (S27(0) = C5)    and 
+                   (S28(0) = C6)    and 
+                   (S29(0) = C7)    and 
+                   (S30(0) = C8)    and 
+                   (S31(0) = C9)    ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00753"
+      severity NOTE;
+    assert (    (S1(0) = C1)    and 
+                (S2(0) = C4)    and 
+                (S3(0) = C5)    and 
+                (S4(0) = C6)    and 
+                (S5(0) = C7)    and 
+                (S6(0) = C8)    and 
+                (S7(0) = C9)    and 
+                (S8(0) = C1)    and 
+                (S9(0) = C4)    and 
+                (S10(0) = C5)    and 
+                (S11(0) = C6)    and 
+                (S12(0) = C7)    and 
+                (S13(0) = C8)    and 
+                (S14(0) = C9)    and 
+                (S15(0)(0) = C1) and 
+                (S16(0)(0) = C4) and 
+                (S17(0)(0) = C5) and 
+                (S18(0)(0) = C6) and 
+                (S19(0)(0) = C7) and 
+                (S20(0)(0) = C8) and 
+                (S21(0)(0) = C9) and 
+                (S22.a = C1)    and 
+                (S22.b = C2)    and 
+                (S22.c = C3)    and 
+                (S22.d = C4)    and 
+                (S22.e = C5)    and 
+                (S22.f = C6)    and 
+                (S22.g = C7)    and 
+                (S22.h = C8)    and 
+                (S22.i = C9)    and 
+                (S22.j = C10)    and 
+                (S22.k = C11)    and 
+                (S25(0) = C1)    and 
+                (S26(0) = C4)    and 
+                (S27(0) = C5)    and 
+                (S28(0) = C6)    and 
+                (S29(0) = C7)    and 
+                (S30(0) = C8)    and 
+                (S31(0) = C9)    ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00753 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00753arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc754.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc754.vhd
new file mode 100644
index 0000000..5cb4386
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc754.vhd
@@ -0,0 +1,1025 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc754.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00754pkg is
+  subtype hi_to_low_range    is integer range 0 to 7;
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer;
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+  subtype boolean_vector_st    is boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st    is  integer_vector(0 to 15);
+  subtype real_vector_st    is  real_vector(0 to 15);
+  subtype time_vector_st    is  time_vector(0 to 15);
+  subtype natural_vector_st    is  natural_vector(0 to 15);
+  subtype positive_vector_st    is  positive_vector(0 to 15);
+  type boolean_cons_vector    is array (15 downto 0) of boolean;
+  type severity_level_cons_vector    is array (15 downto 0) of severity_level;
+  type integer_cons_vector    is array (15 downto 0) of integer;
+  type real_cons_vector    is array (15 downto 0) of real;
+  type time_cons_vector    is array (15 downto 0) of time;
+  type natural_cons_vector    is array (15 downto 0) of natural;
+  type positive_cons_vector    is array (15 downto 0) of positive;
+  type boolean_cons_vectorofvector       is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector    is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector    is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector    is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector    is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector    is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector    is array (0 to 15) of positive_cons_vector;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(1 to 7);
+                               k:bit_vector(0 to 3);
+                             end record;
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  type record_array_new is record
+                             a:boolean_vector(0 to 15);
+                             b:severity_level_vector(0 to 15);
+                             c:integer_vector(0 to 15);
+                             d:real_vector(0 to 15);
+                             e:time_vector(0 to 15);
+                             f:natural_vector(0 to 15);
+                             g:positive_vector(0 to 15);
+                           end record;
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  subtype boolean_vector_range    is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range    is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range    is integer_vector(hi_to_low_range);
+  subtype real_vector_range       is real_vector(hi_to_low_range);
+  subtype time_vector_range       is time_vector(hi_to_low_range);
+  subtype natural_vector_range    is natural_vector(hi_to_low_range);
+  subtype positive_vector_range    is positive_vector(hi_to_low_range);
+  type array_rec_std       is array (integer range <>) of record_std_package;
+  type array_rec_cons       is array (integer range <>) of record_cons_array;
+  type array_rec_rec       is array (integer range <>) of record_of_records;
+  subtype array_rec_std_st    is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st    is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st    is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(0 to 7);
+                                    b: array_rec_cons(0 to 7);
+                                    c: array_rec_rec(0 to 7);
+                                  end record;
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(0 to 7) of bit;
+  
+  subtype word is bit_vector(0 to 15);                                 --constrained array
+  
+  constant size :integer := 7;
+  
+  type primary_memory is array(0 to size) of word;                     --array of an array
+  
+  type primary_memory_module is                                       --record with field
+    record                                                               --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;     --array of a complex record
+  subtype delay is integer range 1 to 10;
+  
+  constant C1    : boolean := true;
+  constant C2    : bit := '1';
+  constant C3    : character := 's';
+  constant C4    : severity_level := note;
+  constant C5    : integer := 3;
+  constant C6    : real := 3.0;
+  constant C7    : time := 3 ns;
+  constant C8    : natural := 1;
+  constant C9    : positive := 1;
+  constant C10    : string := "shishir";
+  constant C11    : bit_vector := B"0011";
+  constant C12    : boolean_vector := (C1,false);
+  constant C13    : severity_level_vector := (C4,error);
+  constant C14    : integer_vector := (1,2,3,4);
+  constant C15    : real_vector := (1.0,2.0,C6,4.0);
+  constant C16    : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17    : natural_vector := (1,2,3,4);
+  constant C18    : positive_vector := (1,2,3,4);
+  constant C19    : boolean_cons_vector := (others => C1);
+  constant C20    : severity_level_cons_vector := (others => C4);
+  constant C21    : integer_cons_vector := (others => C5);
+  constant C22    : real_cons_vector := (others => C6);
+  constant C23    : time_cons_vector :=  (others => C7);
+  constant C24    : natural_cons_vector :=  (others => C8);
+  constant C25    : positive_cons_vector :=  (others => C9);
+  constant C26    : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27    : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28    : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29    : real_cons_vectorofvector := (others => (others => C6));
+  constant C30    : time_cons_vectorofvector := (others => (others => C7));
+  constant C31    : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32    : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50    : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51    : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53    : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70    : boolean_vector_st :=(others => C1);
+  constant C71    : severity_level_vector_st:= (others => C4);
+  constant C72    : integer_vector_st:=(others => C5);
+  constant C73    : real_vector_st:=(others => C6);
+  constant C74    : time_vector_st:=(others => C7);
+  constant C75    : natural_vector_st:=(others => C8);
+  constant C76    : positive_vector_st:=(others => C9);
+  constant C77    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b   : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55    : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60    : byte := (others => '0');
+  constant C61    : word := (others =>'0' );
+  constant C64    : primary_memory := (others => C61);
+  constant C65    : primary_memory_module := ('1',C64);
+  constant C66    : whole_memory := (others => C65);
+  constant C67    : current := 1 A;
+  constant C68    : resistance := 1 Ohm;
+  constant C69    : delay := 2;
+  constant C78   : boolean_vector_range := (others => C1);
+  constant C79   : severity_level_vector_range := (others => C4) ;
+  constant C80   : integer_vector_range :=(others => C5) ;
+  constant C81   : real_vector_range :=(others => C6);
+  constant C82   : time_vector_range :=(others => C7);
+  constant C83   : natural_vector_range :=(others => C8);
+  constant C84   : positive_vector_range :=(others => C9);
+  constant C85   : array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86   : array_rec_cons (0 to 7) :=(others => C51);
+  constant C88   : array_rec_rec(0 to 7) :=(others => C55);
+  constant C102   : record_of_arr_of_record:= (C85,C86,C88);
+
+end c01s01b01x01p05n02i00754pkg;
+
+
+use work.c01s01b01x01p05n02i00754pkg.all;
+ENTITY c01s01b01x01p05n02i00754ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+  port(
+    S1    : boolean_vector(zero to fifteen);
+    S2    : severity_level_vector(zero to fifteen);
+    S3    : integer_vector(zero to fifteen);
+    S4    : real_vector(zero to fifteen);
+    S5    : time_vector (zero to fifteen);
+    S6    : natural_vector(zero to fifteen);
+    S7    : positive_vector(zero to fifteen);
+    S8    : boolean_cons_vector;
+    S9    : severity_level_cons_vector ;
+    S10    : integer_cons_vector;
+    S11    : real_cons_vector;
+    S12    : time_cons_vector ;
+    S13    : natural_cons_vector ;
+    S14    : positive_cons_vector ;
+    S15    : boolean_cons_vectorofvector;
+    S16    : severity_level_cons_vectorofvector;
+    S17    : integer_cons_vectorofvector;
+    S18    : real_cons_vectorofvector;
+    S19    : time_cons_vectorofvector;
+    S20    : natural_cons_vectorofvector;
+    S21    : positive_cons_vectorofvector;
+    S22    : record_std_package;
+    S23    : record_cons_array;
+    S24    : record_cons_arrayofarray ;
+    S25    : boolean_vector_st;
+    S26    : severity_level_vector_st;
+    S27    : integer_vector_st;
+    S28    : real_vector_st;
+    S29    : time_vector_st;
+    S30    : natural_vector_st;
+    S31    : positive_vector_st;
+    S32    : record_array_st;
+    S33    : record_array_st;
+    S34   : record_array_new;
+    S35    : record_of_records;
+    S36    : byte;
+    S37    : word;
+    S38    : current_vector(zero to three);
+    S39    : resistance_vector(zero to three);
+    S40    : delay;
+    S41   : boolean_vector_range;
+    S42   : severity_level_vector_range ;
+    S43   : integer_vector_range ;
+    S44   : real_vector_range ;
+    S45   : time_vector_range ;
+    S46   : natural_vector_range ;
+    S47   : positive_vector_range ;
+    S48   : array_rec_std(zero to seven);
+    S49   : array_rec_cons(zero to seven);
+    S50   : array_rec_rec(zero to seven);
+    S51   : record_of_arr_of_record
+    );
+END c01s01b01x01p05n02i00754ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00754arch OF c01s01b01x01p05n02i00754ent IS
+
+BEGIN
+  assert (S1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity  error;
+  assert (S6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S8'left = 15) report " boolean_cons_vector error in the left generic value" severity  error;
+  assert (S9'left = 15) report " severity_level_cons_vector  error in the left generic value" severity  error;
+  assert (S10'left = 15) report " integer_cons_vector error in the left generic value" severity  error;
+  assert (S11'left = 15) report " real_cons_vector error in the left generic value" severity  error;
+  assert (S12'left = 15) report " time_cons_vector  error in the left generic value" severity  error;
+  assert (S13'left = 15) report " natural_cons_vector  error in the left generic value" severity  error;
+  assert (S14'left = 15) report " positive_cons_vector  error in the left generic value" severity  error;
+  assert (S15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S22.j'left = 1) report " record_std_package error in the left generic value" severity  error;
+  assert (S22.k'left = 0) report " record_std_package error in the left generic value" severity  error;
+  assert (S23.a'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.b'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.c'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.d'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.e'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.f'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.g'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S24.a'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.b'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.c'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.d'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.e'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.f'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.g'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S25'left = 0) report " boolean_vector_st error in the left generic value" severity  error;
+  assert (S26'left = 0) report "  severity_level_vector_st error in the left generic value" severity  error;
+  assert (S27'left = 0) report "  integer_vector_st error in the left generic value" severity  error;
+  assert (S28'left = 0) report "  real_vector_st error in the left generic value" severity  error;
+  assert (S29'left = 0) report "  time_vector_st error in the left generic value" severity  error;
+  assert (S30'left = 0) report "  natural_vector_st error in the left generic value" severity  error;
+  assert (S31'left = 0) report " positive_vector_st error in the left generic value" severity  error;
+  assert (S32.a'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.b'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.c'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.d'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.e'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.f'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.g'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S34.a'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.b'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.c'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.d'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.e'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.f'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.g'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S36'left = 0) report " byte error in the left generic value" severity  error;
+  assert (S37'left = 0) report " word error in the left generic value" severity  error;
+  assert (S38'left = 0) report " current_vector(zero to three) error in the left generic value" severity  error;
+  assert (S39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity  error;
+--assert (S40'left = 1) report " delay error in the left generic value" severity  error;
+  assert (S41'left = 0) report " boolean_vector_range error in the left generic value" severity  error;
+  assert (S42'left = 0) report " severity_level_vector_range  error in the left generic value" severity  error;
+  assert (S43'left = 0) report " integer_vector_range  error in the left generic value" severity  error;
+  assert (S44'left = 0) report " real_vector_range  error in the left generic value" severity  error;
+  assert (S45'left = 0) report " time_vector_range  error in the left generic value" severity  error;
+  assert (S46'left = 0) report " natural_vector_range  error in the left generic value" severity  error;
+  assert (S47'left = 0) report " positive_vector_range  error in the left generic value" severity  error;
+  assert (S48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity  error;
+  assert (S49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity  error;
+  assert (S50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity  error;
+  assert (S51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  assert (S51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  assert (S51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  
+  assert (S1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity  error;
+  assert (S6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S8'right = 0) report " boolean_cons_vector error in the right generic value" severity  error;
+  assert (S9'right = 0) report " severity_level_cons_vector  error in the right generic value" severity  error;
+  assert (S10'right = 0) report " integer_cons_vector error in the right generic value" severity  error;
+  assert (S11'right = 0) report " real_cons_vector error in the right generic value" severity  error;
+  assert (S12'right = 0) report " time_cons_vector  error in the right generic value" severity  error;
+  assert (S13'right = 0) report " natural_cons_vector  error in the right generic value" severity  error;
+  assert (S14'right = 0) report " positive_cons_vector  error in the right generic value" severity  error;
+  assert (S15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S22.j'right = 7) report " record_std_package error in the right generic value" severity  error;
+  assert (S22.k'right = 3) report " record_std_package error in the right generic value" severity  error;
+  assert (S23.a'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.b'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.c'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.d'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.e'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.f'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.g'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S24.a'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.b'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.c'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.d'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.e'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.f'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.g'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S25'right = 15) report " boolean_vector_st error in the right generic value" severity  error;
+  assert (S26'right = 15) report "  severity_level_vector_st error in the right generic value" severity  error;
+  assert (S27'right = 15) report "  integer_vector_st error in the right generic value" severity  error;
+  assert (S28'right = 15) report "  real_vector_st error in the right generic value" severity  error;
+  assert (S29'right = 15) report "  time_vector_st error in the right generic value" severity  error;
+  assert (S30'right = 15) report "  natural_vector_st error in the right generic value" severity  error;
+  assert (S31'right = 15) report " positive_vector_st error in the right generic value" severity  error;
+  assert (S32.a'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.b'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.c'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.d'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.e'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.f'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.g'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S34.a'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.b'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.c'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.d'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.e'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.f'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.g'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S36'right = 7) report " byte error in the right generic value" severity  error;
+  assert (S37'right = 15) report " word error in the right generic value" severity  error;
+  assert (S38'right = 3) report " current_vector(zero to three) error in the right generic value" severity  error;
+  assert (S39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity  error;
+--assert (S40'right = 1) report " delay error in the right generic value" severity  error;
+  assert (S41'right = 7) report " boolean_vector_range error in the right generic value" severity  error;
+  assert (S42'right = 7) report " severity_level_vector_range  error in the right generic value" severity  error;
+  assert (S43'right = 7) report " integer_vector_range  error in the right generic value" severity  error;
+  assert (S44'right = 7) report " real_vector_range  error in the right generic value" severity  error;
+  assert (S45'right = 7) report " time_vector_range  error in the right generic value" severity  error;
+  assert (S46'right = 7) report " natural_vector_range  error in the right generic value" severity  error;
+  assert (S47'right = 7) report " positive_vector_range  error in the right generic value" severity  error;
+  assert (S48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity  error;
+  assert (S49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity  error;
+  assert (S50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity  error;
+  assert (S51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity  error;
+  assert (S6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S8'length = 16) report " boolean_cons_vector error in the length generic value" severity  error;
+  assert (S9'length = 16) report " severity_level_cons_vector  error in the length generic value" severity  error;
+  assert (S10'length = 16) report " integer_cons_vector error in the length generic value" severity  error;
+  assert (S11'length = 16) report " real_cons_vector error in the length generic value" severity  error;
+  assert (S12'length = 16) report " time_cons_vector  error in the length generic value" severity  error;
+  assert (S13'length = 16) report " natural_cons_vector  error in the length generic value" severity  error;
+  assert (S14'length = 16) report " positive_cons_vector  error in the length generic value" severity  error;
+  assert (S15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S22.j'length = 7) report " record_std_package error in the length generic value" severity  error;
+  assert (S22.k'length = 4) report " record_std_package error in the length generic value" severity  error;
+  assert (S23.a'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.b'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.c'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.d'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.e'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.f'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.g'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S24.a'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.b'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.c'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.d'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.e'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.f'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.g'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S25'length = 16) report " boolean_vector_st error in the length generic value" severity  error;
+  assert (S26'length = 16) report "  severity_level_vector_st error in the length generic value" severity  error;
+  assert (S27'length = 16) report "  integer_vector_st error in the length generic value" severity  error;
+  assert (S28'length = 16) report "  real_vector_st error in the length generic value" severity  error;
+  assert (S29'length = 16) report "  time_vector_st error in the length generic value" severity  error;
+  assert (S30'length = 16) report "  natural_vector_st error in the length generic value" severity  error;
+  assert (S31'length = 16) report " positive_vector_st error in the length generic value" severity  error;
+  assert (S32.a'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.b'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.c'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.d'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.e'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.f'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.g'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S34.a'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.b'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.c'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.d'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.e'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.f'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.g'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S36'length = 8) report " byte error in the length generic value" severity  error;
+  assert (S37'length = 16) report " word error in the length generic value" severity  error;
+  assert (S38'length = 4) report " current_vector(zero to three) error in the length generic value" severity  error;
+  assert (S39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity  error;
+--assert (S40'length = 1) report " delay error in the length generic value" severity  error;
+  assert (S41'length = 8) report " boolean_vector_range error in the length generic value" severity  error;
+  assert (S42'length = 8) report " severity_level_vector_range  error in the length generic value" severity  error;
+  assert (S43'length = 8) report " integer_vector_range  error in the length generic value" severity  error;
+  assert (S44'length = 8) report " real_vector_range  error in the length generic value" severity  error;
+  assert (S45'length = 8) report " time_vector_range  error in the length generic value" severity  error;
+  assert (S46'length = 8) report " natural_vector_range  error in the length generic value" severity  error;
+  assert (S48'length = 8) report " positive_vector_range  error in the length generic value" severity  error;
+  assert (S48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity  error;
+  assert (S49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity  error;
+  assert (S50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity  error;
+  assert (S51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+  assert (S51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+  assert (S51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert   NOT(    (S1'left = 0)    and 
+                     (S2'left = 0)    and 
+                     (S3'left = 0)    and 
+                     (S4'left = 0)    and 
+                     (S5'left = 0)    and 
+                     (S6'left = 0)    and 
+                     (S7'left = 0)    and 
+                     (S8'left = 15) and 
+                     (S9'left = 15) and 
+                     (S10'left = 15) and 
+                     (S11'left = 15) and 
+                     (S12'left = 15) and 
+                     (S13'left = 15) and 
+                     (S14'left = 15) and 
+                     (S15'left = 0) and 
+                     (S16'left = 0) and 
+                     (S17'left = 0) and 
+                     (S18'left = 0) and 
+                     (S19'left = 0) and 
+                     (S20'left = 0) and 
+                     (S21'left = 0) and 
+                     (S22.j'left = 1) and 
+                     (S22.k'left = 0) and 
+                     (S23.a'left = 15) and 
+                     (S23.b'left = 15) and 
+                     (S23.c'left = 15) and 
+                     (S23.d'left = 15) and 
+                     (S23.e'left = 15) and 
+                     (S23.f'left = 15) and 
+                     (S23.g'left = 15) and 
+                     (S24.a'left = 0) and 
+                     (S24.b'left = 0) and 
+                     (S24.c'left = 0) and 
+                     (S24.d'left = 0) and 
+                     (S24.e'left = 0) and 
+                     (S24.f'left = 0) and 
+                     (S24.g'left = 0) and 
+                     (S25'left = 0) and 
+                     (S26'left = 0) and 
+                     (S27'left = 0) and 
+                     (S28'left = 0) and 
+                     (S29'left = 0) and 
+                     (S30'left = 0) and 
+                     (S31'left = 0) and 
+                     (S32.a'left = 0) and 
+                     (S32.b'left = 0) and 
+                     (S32.c'left = 0) and 
+                     (S32.d'left = 0) and 
+                     (S32.e'left = 0) and 
+                     (S32.f'left = 0) and 
+                     (S32.g'left = 0) and 
+                     (S34.a'left = 0) and 
+                     (S34.b'left = 0) and 
+                     (S34.c'left = 0) and 
+                     (S34.d'left = 0) and 
+                     (S34.e'left = 0) and 
+                     (S34.f'left = 0) and 
+                     (S34.g'left = 0) and 
+                     (S36'left = 0) and 
+                     (S37'left = 0) and 
+                     (S38'left = 0) and 
+                     (S39'left = 0) and 
+--          (S40'left = 1) and 
+                     (S42'left = 0) and 
+                     (S43'left = 0) and 
+                     (S44'left = 0) and 
+                     (S45'left = 0) and 
+                     (S46'left = 0) and 
+                     (S47'left = 0) and 
+                     (S48'left = 0) and 
+                     (S49'left = 0) and 
+                     (S50'left = 0) and 
+                     (S51.a'left = 0) and 
+                     (S51.b'left = 0) and 
+                     (S51.c'left = 0) and 
+                     (S1'right = 15) and 
+                     (S2'right = 15) and 
+                     (S3'right = 15) and 
+                     (S4'right = 15) and 
+                     (S5'right = 15) and 
+                     (S6'right = 15) and 
+                     (S7'right = 15) and 
+                     (S8'right = 0) and 
+                     (S9'right = 0) and 
+                     (S10'right = 0)and 
+                     (S11'right = 0) and 
+                     (S12'right = 0) and 
+                     (S13'right = 0) and 
+                     (S14'right = 0) and 
+                     (S15'right = 15) and 
+                     (S16'right = 15) and 
+                     (S17'right = 15) and 
+                     (S18'right = 15) and 
+                     (S19'right = 15) and 
+                     (S20'right = 15) and 
+                     (S21'right = 15) and 
+                     (S22.j'right = 7) and 
+                     (S22.k'right = 3) and 
+                     (S23.a'right = 0) and 
+                     (S23.b'right = 0) and 
+                     (S23.c'right = 0) and 
+                     (S23.d'right = 0) and 
+                     (S23.e'right = 0) and 
+                     (S23.f'right = 0) and 
+                     (S23.g'right = 0) and 
+                     (S24.a'right = 15) and 
+                     (S24.b'right = 15) and 
+                     (S24.c'right = 15) and 
+                     (S24.d'right = 15) and 
+                     (S24.e'right = 15) and 
+                     (S24.f'right = 15) and 
+                     (S24.g'right = 15) and 
+                     (S25'right = 15) and 
+                     (S26'right = 15) and 
+                     (S27'right = 15) and 
+                     (S28'right = 15) and 
+                     (S29'right = 15) and 
+                     (S30'right = 15) and 
+                     (S31'right = 15) and 
+                     (S32.a'right = 15) and 
+                     (S32.b'right = 15) and 
+                     (S32.c'right = 15) and 
+                     (S32.d'right = 15) and 
+                     (S32.e'right = 15) and 
+                     (S32.f'right = 15) and 
+                     (S32.g'right = 15) and 
+                     (S34.a'right = 15) and 
+                     (S34.b'right = 15) and 
+                     (S34.c'right = 15) and 
+                     (S34.d'right = 15) and 
+                     (S34.e'right = 15) and 
+                     (S34.f'right = 15) and 
+                     (S34.g'right = 15) and 
+                     (S36'right = 7) and 
+                     (S37'right = 15) and  
+                     (S38'right = 3) and 
+                     (S39'right = 3) and 
+--          (S40'right = 1) and 
+                     (S41'right = 7) and 
+                     (S42'right = 7) and 
+                     (S43'right = 7) and 
+                     (S44'right = 7) and 
+                     (S45'right = 7) and 
+                     (S46'right = 7) and 
+                     (S47'right = 7) and 
+                     (S48'right = 7) and 
+                     (S49'right = 7) and 
+                     (S50'right = 7) and 
+                     (S51.a'right = 7) and 
+                     (S51.b'right = 7) and 
+                     (S51.c'right = 7) and 
+                     (S1'length = 16) and 
+                     (S2'length = 16) and 
+                     (S3'length = 16) and 
+                     (S4'length = 16) and 
+                     (S5'length = 16) and 
+                     (S6'length = 16) and 
+                     (S7'length = 16) and 
+                     (S8'length = 16) and 
+                     (S9'length = 16) and 
+                     (S10'length = 16) and 
+                     (S11'length = 16) and 
+                     (S12'length = 16) and 
+                     (S13'length = 16) and 
+                     (S14'length = 16) and 
+                     (S15'length = 16) and 
+                     (S16'length = 16) and 
+                     (S17'length = 16) and 
+                     (S18'length = 16) and 
+                     (S19'length = 16) and 
+                     (S20'length = 16) and 
+                     (S21'length = 16) and 
+                     (S22.j'length = 7)and 
+                     (S22.k'length = 4) and 
+                     (S23.a'length = 16) and 
+                     (S23.b'length = 16) and 
+                     (S23.c'length = 16) and 
+                     (S23.d'length = 16) and 
+                     (S23.e'length = 16) and 
+                     (S23.f'length = 16) and 
+                     (S23.g'length = 16) and 
+                     (S24.a'length = 16) and 
+                     (S24.b'length = 16) and 
+                     (S24.c'length = 16) and 
+                     (S24.d'length = 16) and 
+                     (S24.e'length = 16) and 
+                     (S24.f'length = 16) and 
+                     (S24.g'length = 16) and 
+                     (S25'length = 16) and 
+                     (S26'length = 16) and 
+                     (S27'length = 16) and 
+                     (S28'length = 16) and 
+                     (S29'length = 16) and 
+                     (S30'length = 16) and 
+                     (S31'length = 16) and 
+                     (S32.a'length = 16) and 
+                     (S32.b'length = 16) and 
+                     (S32.c'length = 16) and 
+                     (S32.d'length = 16) and 
+                     (S32.e'length = 16) and 
+                     (S32.f'length = 16) and 
+                     (S32.g'length = 16) and 
+                     (S34.a'length = 16) and 
+                     (S34.b'length = 16) and 
+                     (S34.c'length = 16) and 
+                     (S34.d'length = 16) and 
+                     (S34.e'length = 16) and 
+                     (S34.f'length = 16) and 
+                     (S34.g'length = 16) and 
+                     (S36'length = 8) and 
+                     (S37'length = 16) and 
+                     (S38'length = 4) and 
+                     (S39'length = 4) and 
+--          (S40'length = 1) and 
+                     (S41'length = 8) and 
+                     (S42'length = 8) and 
+                     (S43'length = 8) and 
+                     (S44'length = 8) and 
+                     (S45'length = 8) and 
+                     (S46'length = 8) and 
+                     (S48'length = 8) and 
+                     (S48'length = 8) and 
+                     (S49'length = 8) and 
+                     (S50'length = 8) and 
+                     (S51.a'length = 8) and 
+                     (S51.b'length = 8) and 
+                     (S51.c'length = 8) ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00754"
+      severity NOTE;
+    assert   ((S1'left = 0)    and 
+              (S2'left = 0)    and 
+              (S3'left = 0)    and 
+              (S4'left = 0)    and 
+              (S5'left = 0)    and 
+              (S6'left = 0)    and 
+              (S7'left = 0)    and 
+              (S8'left = 15) and 
+              (S9'left = 15) and 
+              (S10'left = 15) and 
+              (S11'left = 15) and 
+              (S12'left = 15) and 
+              (S13'left = 15) and 
+              (S14'left = 15) and 
+              (S15'left = 0) and 
+              (S16'left = 0) and 
+              (S17'left = 0) and 
+              (S18'left = 0) and 
+              (S19'left = 0) and 
+              (S20'left = 0) and 
+              (S21'left = 0) and 
+              (S22.j'left = 1) and 
+              (S22.k'left = 0) and 
+              (S23.a'left = 15) and 
+              (S23.b'left = 15) and 
+              (S23.c'left = 15) and 
+              (S23.d'left = 15) and 
+              (S23.e'left = 15) and 
+              (S23.f'left = 15) and 
+              (S23.g'left = 15) and 
+              (S24.a'left = 0) and 
+              (S24.b'left = 0) and 
+              (S24.c'left = 0) and 
+              (S24.d'left = 0) and 
+              (S24.e'left = 0) and 
+              (S24.f'left = 0) and 
+              (S24.g'left = 0) and 
+              (S25'left = 0) and 
+              (S26'left = 0) and 
+              (S27'left = 0) and 
+              (S28'left = 0) and 
+              (S29'left = 0) and 
+              (S30'left = 0) and 
+              (S31'left = 0) and 
+              (S32.a'left = 0) and 
+              (S32.b'left = 0) and 
+              (S32.c'left = 0) and 
+              (S32.d'left = 0) and 
+              (S32.e'left = 0) and 
+              (S32.f'left = 0) and 
+              (S32.g'left = 0) and 
+              (S34.a'left = 0) and 
+              (S34.b'left = 0) and 
+              (S34.c'left = 0) and 
+              (S34.d'left = 0) and 
+              (S34.e'left = 0) and 
+              (S34.f'left = 0) and 
+              (S34.g'left = 0) and 
+              (S36'left = 0) and 
+              (S37'left = 0) and 
+              (S38'left = 0) and 
+              (S39'left = 0) and 
+--          (S40'left = 1) and 
+              (S42'left = 0) and 
+              (S43'left = 0) and 
+              (S44'left = 0) and 
+              (S45'left = 0) and 
+              (S46'left = 0) and 
+              (S47'left = 0) and 
+              (S48'left = 0) and 
+              (S49'left = 0) and 
+              (S50'left = 0) and 
+              (S51.a'left = 0) and 
+              (S51.b'left = 0) and 
+              (S51.c'left = 0) and 
+              (S1'right = 15) and 
+              (S2'right = 15) and 
+              (S3'right = 15) and 
+              (S4'right = 15) and 
+              (S5'right = 15) and 
+              (S6'right = 15) and 
+              (S7'right = 15) and 
+              (S8'right = 0) and 
+              (S9'right = 0) and 
+              (S10'right = 0)and 
+              (S11'right = 0) and 
+              (S12'right = 0) and 
+              (S13'right = 0) and 
+              (S14'right = 0) and 
+              (S15'right = 15) and 
+              (S16'right = 15) and 
+              (S17'right = 15) and 
+              (S18'right = 15) and 
+              (S19'right = 15) and 
+              (S20'right = 15) and 
+              (S21'right = 15) and 
+              (S22.j'right = 7) and 
+              (S22.k'right = 3) and 
+              (S23.a'right = 0) and 
+              (S23.b'right = 0) and 
+              (S23.c'right = 0) and 
+              (S23.d'right = 0) and 
+              (S23.e'right = 0) and 
+              (S23.f'right = 0) and 
+              (S23.g'right = 0) and 
+              (S24.a'right = 15) and 
+              (S24.b'right = 15) and 
+              (S24.c'right = 15) and 
+              (S24.d'right = 15) and 
+              (S24.e'right = 15) and 
+              (S24.f'right = 15) and 
+              (S24.g'right = 15) and 
+              (S25'right = 15) and 
+              (S26'right = 15) and 
+              (S27'right = 15) and 
+              (S28'right = 15) and 
+              (S29'right = 15) and 
+              (S30'right = 15) and 
+              (S31'right = 15) and 
+              (S32.a'right = 15) and 
+              (S32.b'right = 15) and 
+              (S32.c'right = 15) and 
+              (S32.d'right = 15) and 
+              (S32.e'right = 15) and 
+              (S32.f'right = 15) and 
+              (S32.g'right = 15) and 
+              (S34.a'right = 15) and 
+              (S34.b'right = 15) and 
+              (S34.c'right = 15) and 
+              (S34.d'right = 15) and 
+              (S34.e'right = 15) and 
+              (S34.f'right = 15) and 
+              (S34.g'right = 15) and 
+              (S36'right = 7) and 
+              (S37'right = 15) and  
+              (S38'right = 3) and 
+              (S39'right = 3) and 
+--          (S40'right = 1) and 
+              (S41'right = 7) and 
+              (S42'right = 7) and 
+              (S43'right = 7) and 
+              (S44'right = 7) and 
+              (S45'right = 7) and 
+              (S46'right = 7) and 
+              (S47'right = 7) and 
+              (S48'right = 7) and 
+              (S49'right = 7) and 
+              (S50'right = 7) and 
+              (S51.a'right = 7) and 
+              (S51.b'right = 7) and 
+              (S51.c'right = 7) and 
+              (S1'length = 16) and 
+              (S2'length = 16) and 
+              (S3'length = 16) and 
+              (S4'length = 16) and 
+              (S5'length = 16) and 
+              (S6'length = 16) and 
+              (S7'length = 16) and 
+              (S8'length = 16) and 
+              (S9'length = 16) and 
+              (S10'length = 16) and 
+              (S11'length = 16) and 
+              (S12'length = 16) and 
+              (S13'length = 16) and 
+              (S14'length = 16) and 
+              (S15'length = 16) and 
+              (S16'length = 16) and 
+              (S17'length = 16) and 
+              (S18'length = 16) and 
+              (S19'length = 16) and 
+              (S20'length = 16) and 
+              (S21'length = 16) and 
+              (S22.j'length = 7)and 
+              (S22.k'length = 4) and 
+              (S23.a'length = 16) and 
+              (S23.b'length = 16) and 
+              (S23.c'length = 16) and 
+              (S23.d'length = 16) and 
+              (S23.e'length = 16) and 
+              (S23.f'length = 16) and 
+              (S23.g'length = 16) and 
+              (S24.a'length = 16) and 
+              (S24.b'length = 16) and 
+              (S24.c'length = 16) and 
+              (S24.d'length = 16) and 
+              (S24.e'length = 16) and 
+              (S24.f'length = 16) and 
+              (S24.g'length = 16) and 
+              (S25'length = 16) and 
+              (S26'length = 16) and 
+              (S27'length = 16) and 
+              (S28'length = 16) and 
+              (S29'length = 16) and 
+              (S30'length = 16) and 
+              (S31'length = 16) and 
+              (S32.a'length = 16) and 
+              (S32.b'length = 16) and 
+              (S32.c'length = 16) and 
+              (S32.d'length = 16) and 
+              (S32.e'length = 16) and 
+              (S32.f'length = 16) and 
+              (S32.g'length = 16) and 
+              (S34.a'length = 16) and 
+              (S34.b'length = 16) and 
+              (S34.c'length = 16) and 
+              (S34.d'length = 16) and 
+              (S34.e'length = 16) and 
+              (S34.f'length = 16) and 
+              (S34.g'length = 16) and 
+              (S36'length = 8) and 
+              (S37'length = 16) and 
+              (S38'length = 4) and 
+              (S39'length = 4) and 
+--          (S40'length = 1) and 
+              (S41'length = 8) and 
+              (S42'length = 8) and 
+              (S43'length = 8) and 
+              (S44'length = 8) and 
+              (S45'length = 8) and 
+              (S46'length = 8) and 
+              (S48'length = 8) and 
+              (S48'length = 8) and 
+              (S49'length = 8) and 
+              (S50'length = 8) and 
+              (S51.a'length = 8) and 
+              (S51.b'length = 8) and 
+              (S51.c'length = 8) ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00754 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00754arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc755.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc755.vhd
new file mode 100644
index 0000000..5079776
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc755.vhd
@@ -0,0 +1,1018 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc755.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00755ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00755ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00755arch OF c01s01b01x01p05n02i00755ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector; 
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+  
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                                 --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  
+  type primary_memory_module is                                       --record with field
+    record                                                               --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;     --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12    : boolean_vector := (C1,false);
+  constant C13    : severity_level_vector := (C4,error);
+  constant C14    : integer_vector := (one,two,three,four);
+  constant C15    : real_vector := (1.0,2.0,C6,4.0);
+  constant C16    : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17    : natural_vector := (one,2,3,4);
+  constant C18    : positive_vector := (one,2,3,4);
+  constant C19    : boolean_cons_vector := (others => C1);
+  constant C20    : severity_level_cons_vector := (others => C4);
+  constant C21    : integer_cons_vector := (others => C5);
+  constant C22    : real_cons_vector := (others => C6);
+  constant C23    : time_cons_vector :=  (others => C7);
+  constant C24    : natural_cons_vector :=  (others => C8);
+  constant C25    : positive_cons_vector :=  (others => C9);
+  constant C26    : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27    : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28    : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29    : real_cons_vectorofvector := (others => (others => C6));
+  constant C30    : time_cons_vectorofvector := (others => (others => C7));
+  constant C31    : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32    : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50    : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51    : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53    : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70    : boolean_vector_st :=(others => C1);
+  constant C71    : severity_level_vector_st:= (others => C4);
+  constant C72    : integer_vector_st:=(others => C5);
+  constant C73    : real_vector_st:=(others => C6);
+  constant C74    : time_vector_st:=(others => C7);
+  constant C75    : natural_vector_st:=(others => C8);
+  constant C76    : positive_vector_st:=(others => C9);
+  constant C77    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b   : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55    : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60    : byte := (others => '0');
+  constant C61    : word := (others =>'0' );
+  constant C64    : primary_memory := (others => C61);
+  constant C65    : primary_memory_module := ('1',C64);
+  constant C66    : whole_memory := (others => C65);
+  constant C67    : current := 1 A;
+  constant C68    : resistance := 1 Ohm;
+  constant C69    : delay := 2;
+  constant C78   : boolean_vector_range := (others => C1);
+  constant C79   : severity_level_vector_range := (others => C4) ;
+  constant C80   : integer_vector_range :=(others => C5) ;
+  constant C81   : real_vector_range :=(others => C6);
+  constant C82   : time_vector_range :=(others => C7);
+  constant C83   : natural_vector_range :=(others => C8);
+  constant C84   : positive_vector_range :=(others => C9);
+  constant C85   : array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86   : array_rec_cons (0 to 7) :=(others => C51);
+  constant C88   : array_rec_rec(0 to 7) :=(others => C55);
+  constant C102   : record_of_arr_of_record:= (C85,C86,C88);
+  
+  signal S1    : boolean_vector(zero to fifteen);
+  signal S2    : severity_level_vector(zero to fifteen);
+  signal S3    : integer_vector(zero to fifteen);
+  signal S4    : real_vector(zero to fifteen);
+  signal S5    : time_vector (zero to fifteen);
+  signal S6    : natural_vector(zero to fifteen);
+  signal S7    : positive_vector(zero to fifteen);
+  signal S8    : boolean_cons_vector;
+  signal S9    : severity_level_cons_vector ;
+  signal S10    : integer_cons_vector;
+  signal S11    : real_cons_vector;
+  signal S12    : time_cons_vector ;
+  signal S13    : natural_cons_vector ;
+  signal S14    : positive_cons_vector ;
+  signal S15    : boolean_cons_vectorofvector;
+  signal S16    : severity_level_cons_vectorofvector;
+  signal S17    : integer_cons_vectorofvector;
+  signal S18    : real_cons_vectorofvector;
+  signal S19    : time_cons_vectorofvector;
+  signal S20    : natural_cons_vectorofvector;
+  signal S21    : positive_cons_vectorofvector;
+  signal S22    : record_std_package;
+  signal S23    : record_cons_array;
+  signal S24    : record_cons_arrayofarray ;
+  signal S25    : boolean_vector_st;
+  signal S26    : severity_level_vector_st;
+  signal S27    : integer_vector_st;
+  signal S28    : real_vector_st;
+  signal S29    : time_vector_st;
+  signal S30    : natural_vector_st;
+  signal S31    : positive_vector_st;
+  signal S32    : record_array_st;
+  signal S33    : record_array_st;
+  signal S34   : record_array_new;
+  signal S35    : record_of_records;
+  signal S36    : byte;
+  signal S37    : word;
+  signal S38    : current_vector(zero to three);
+  signal S39    : resistance_vector(zero to three);
+  signal S40    : delay;
+  signal S41   : boolean_vector_range;
+  signal S42   : severity_level_vector_range ;
+  signal S43   : integer_vector_range ;
+  signal S44   : real_vector_range ;
+  signal S45   : time_vector_range ;
+  signal S46   : natural_vector_range ;
+  signal S47   : positive_vector_range ;
+  signal S48   : array_rec_std(zero to seven);
+  signal S49   : array_rec_cons(zero to seven);
+  signal S50   : array_rec_rec(zero to seven);
+  signal S51   : record_of_arr_of_record;
+
+BEGIN
+  assert (S1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity  error;
+  assert (S6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity  error;
+  assert (S8'left = 15) report " boolean_cons_vector error in the left generic value" severity  error;
+  assert (S9'left = 15) report " severity_level_cons_vector  error in the left generic value" severity  error;
+  assert (S10'left = 15) report " integer_cons_vector error in the left generic value" severity  error;
+  assert (S11'left = 15) report " real_cons_vector error in the left generic value" severity  error;
+  assert (S12'left = 15) report " time_cons_vector  error in the left generic value" severity  error;
+  assert (S13'left = 15) report " natural_cons_vector  error in the left generic value" severity  error;
+  assert (S14'left = 15) report " positive_cons_vector  error in the left generic value" severity  error;
+  assert (S15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity  error;
+  assert (S22.j'left = 1) report " record_std_package error in the left generic value" severity  error;
+  assert (S22.k'left = 0) report " record_std_package error in the left generic value" severity  error;
+  assert (S23.a'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.b'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.c'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.d'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.e'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.f'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S23.g'left = 15) report " record_cons_array error in the left generic value" severity  error;
+  assert (S24.a'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.b'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.c'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.d'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.e'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.f'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S24.g'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+  assert (S25'left = 0) report " boolean_vector_st error in the left generic value" severity  error;
+  assert (S26'left = 0) report "  severity_level_vector_st error in the left generic value" severity  error;
+  assert (S27'left = 0) report "  integer_vector_st error in the left generic value" severity  error;
+  assert (S28'left = 0) report "  real_vector_st error in the left generic value" severity  error;
+  assert (S29'left = 0) report "  time_vector_st error in the left generic value" severity  error;
+  assert (S30'left = 0) report "  natural_vector_st error in the left generic value" severity  error;
+  assert (S31'left = 0) report " positive_vector_st error in the left generic value" severity  error;
+  assert (S32.a'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.b'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.c'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.d'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.e'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.f'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S32.g'left = 0) report " record_array_st error in the left generic value" severity  error;
+  assert (S34.a'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.b'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.c'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.d'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.e'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.f'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S34.g'left = 0) report " record_array_new error in the left generic value" severity  error;
+  assert (S36'left = 0) report " byte error in the left generic value" severity  error;
+  assert (S37'left = 0) report " word error in the left generic value" severity  error;
+  assert (S38'left = 0) report " current_vector(zero to three) error in the left generic value" severity  error;
+  assert (S39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity  error;
+--assert (S40'left = 1) report " delay error in the left generic value" severity  error;
+  assert (S41'left = 0) report " boolean_vector_range error in the left generic value" severity  error;
+  assert (S42'left = 0) report " severity_level_vector_range  error in the left generic value" severity  error;
+  assert (S43'left = 0) report " integer_vector_range  error in the left generic value" severity  error;
+  assert (S44'left = 0) report " real_vector_range  error in the left generic value" severity  error;
+  assert (S45'left = 0) report " time_vector_range  error in the left generic value" severity  error;
+  assert (S46'left = 0) report " natural_vector_range  error in the left generic value" severity  error;
+  assert (S47'left = 0) report " positive_vector_range  error in the left generic value" severity  error;
+  assert (S48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity  error;
+  assert (S49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity  error;
+  assert (S50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity  error;
+  assert (S51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  assert (S51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  assert (S51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+  
+  assert (S1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity  error;
+  assert (S6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity  error;
+  assert (S8'right = 0) report " boolean_cons_vector error in the right generic value" severity  error;
+  assert (S9'right = 0) report " severity_level_cons_vector  error in the right generic value" severity  error;
+  assert (S10'right = 0) report " integer_cons_vector error in the right generic value" severity  error;
+  assert (S11'right = 0) report " real_cons_vector error in the right generic value" severity  error;
+  assert (S12'right = 0) report " time_cons_vector  error in the right generic value" severity  error;
+  assert (S13'right = 0) report " natural_cons_vector  error in the right generic value" severity  error;
+  assert (S14'right = 0) report " positive_cons_vector  error in the right generic value" severity  error;
+  assert (S15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity  error;
+  assert (S22.j'right = 7) report " record_std_package error in the right generic value" severity  error;
+  assert (S22.k'right = 3) report " record_std_package error in the right generic value" severity  error;
+  assert (S23.a'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.b'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.c'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.d'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.e'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.f'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S23.g'right = 0) report " record_cons_array error in the right generic value" severity  error;
+  assert (S24.a'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.b'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.c'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.d'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.e'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.f'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S24.g'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+  assert (S25'right = 15) report " boolean_vector_st error in the right generic value" severity  error;
+  assert (S26'right = 15) report "  severity_level_vector_st error in the right generic value" severity  error;
+  assert (S27'right = 15) report "  integer_vector_st error in the right generic value" severity  error;
+  assert (S28'right = 15) report "  real_vector_st error in the right generic value" severity  error;
+  assert (S29'right = 15) report "  time_vector_st error in the right generic value" severity  error;
+  assert (S30'right = 15) report "  natural_vector_st error in the right generic value" severity  error;
+  assert (S31'right = 15) report " positive_vector_st error in the right generic value" severity  error;
+  assert (S32.a'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.b'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.c'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.d'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.e'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.f'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S32.g'right = 15) report " record_array_st error in the right generic value" severity  error;
+  assert (S34.a'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.b'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.c'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.d'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.e'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.f'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S34.g'right = 15) report " record_array_new error in the right generic value" severity  error;
+  assert (S36'right = 7) report " byte error in the right generic value" severity  error;
+  assert (S37'right = 15) report " word error in the right generic value" severity  error;
+  assert (S38'right = 3) report " current_vector(zero to three) error in the right generic value" severity  error;
+  assert (S39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity  error;
+--assert (S40'right = 1) report " delay error in the right generic value" severity  error;
+  assert (S41'right = 7) report " boolean_vector_range error in the right generic value" severity  error;
+  assert (S42'right = 7) report " severity_level_vector_range  error in the right generic value" severity  error;
+  assert (S43'right = 7) report " integer_vector_range  error in the right generic value" severity  error;
+  assert (S44'right = 7) report " real_vector_range  error in the right generic value" severity  error;
+  assert (S45'right = 7) report " time_vector_range  error in the right generic value" severity  error;
+  assert (S46'right = 7) report " natural_vector_range  error in the right generic value" severity  error;
+  assert (S47'right = 7) report " positive_vector_range  error in the right generic value" severity  error;
+  assert (S48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity  error;
+  assert (S49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity  error;
+  assert (S50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity  error;
+  assert (S51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+  assert (S1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity  error;
+  assert (S6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity  error;
+  assert (S8'length = 16) report " boolean_cons_vector error in the length generic value" severity  error;
+  assert (S9'length = 16) report " severity_level_cons_vector  error in the length generic value" severity  error;
+  assert (S10'length = 16) report " integer_cons_vector error in the length generic value" severity  error;
+  assert (S11'length = 16) report " real_cons_vector error in the length generic value" severity  error;
+  assert (S12'length = 16) report " time_cons_vector  error in the length generic value" severity  error;
+  assert (S13'length = 16) report " natural_cons_vector  error in the length generic value" severity  error;
+  assert (S14'length = 16) report " positive_cons_vector  error in the length generic value" severity  error;
+  assert (S15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity  error;
+  assert (S22.j'length = 7) report " record_std_package error in the length generic value" severity  error;
+  assert (S22.k'length = 4) report " record_std_package error in the length generic value" severity  error;
+  assert (S23.a'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.b'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.c'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.d'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.e'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.f'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S23.g'length = 16) report " record_cons_array error in the length generic value" severity  error;
+  assert (S24.a'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.b'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.c'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.d'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.e'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.f'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S24.g'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+  assert (S25'length = 16) report " boolean_vector_st error in the length generic value" severity  error;
+  assert (S26'length = 16) report "  severity_level_vector_st error in the length generic value" severity  error;
+  assert (S27'length = 16) report "  integer_vector_st error in the length generic value" severity  error;
+  assert (S28'length = 16) report "  real_vector_st error in the length generic value" severity  error;
+  assert (S29'length = 16) report "  time_vector_st error in the length generic value" severity  error;
+  assert (S30'length = 16) report "  natural_vector_st error in the length generic value" severity  error;
+  assert (S31'length = 16) report " positive_vector_st error in the length generic value" severity  error;
+  assert (S32.a'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.b'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.c'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.d'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.e'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.f'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S32.g'length = 16) report " record_array_st error in the length generic value" severity  error;
+  assert (S34.a'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.b'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.c'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.d'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.e'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.f'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S34.g'length = 16) report " record_array_new error in the length generic value" severity  error;
+  assert (S36'length = 8) report " byte error in the length generic value" severity  error;
+  assert (S37'length = 16) report " word error in the length generic value" severity  error;
+  assert (S38'length = 4) report " current_vector(zero to three) error in the length generic value" severity  error;
+  assert (S39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity  error;
+--assert (S40'length = 1) report " delay error in the length generic value" severity  error;
+  assert (S41'length = 8) report " boolean_vector_range error in the length generic value" severity  error;
+  assert (S42'length = 8) report " severity_level_vector_range  error in the length generic value" severity  error;
+  assert (S43'length = 8) report " integer_vector_range  error in the length generic value" severity  error;
+  assert (S44'length = 8) report " real_vector_range  error in the length generic value" severity  error;
+  assert (S45'length = 8) report " time_vector_range  error in the length generic value" severity  error;
+  assert (S46'length = 8) report " natural_vector_range  error in the length generic value" severity  error;
+  assert (S48'length = 8) report " positive_vector_range  error in the length generic value" severity  error;
+  assert (S48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity  error;
+  assert (S49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity  error;
+  assert (S50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity  error;
+  assert (S51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+  assert (S51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+  assert (S51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert   NOT(    (S1'left = 0)    and 
+                     (S2'left = 0)    and 
+                     (S3'left = 0)    and 
+                     (S4'left = 0)    and 
+                     (S5'left = 0)    and 
+                     (S6'left = 0)    and 
+                     (S7'left = 0)    and 
+                     (S8'left = 15) and 
+                     (S9'left = 15) and 
+                     (S10'left = 15) and 
+                     (S11'left = 15) and 
+                     (S12'left = 15) and 
+                     (S13'left = 15) and 
+                     (S14'left = 15) and 
+                     (S15'left = 0) and 
+                     (S16'left = 0) and 
+                     (S17'left = 0) and 
+                     (S18'left = 0) and 
+                     (S19'left = 0) and 
+                     (S20'left = 0) and 
+                     (S21'left = 0) and 
+                     (S22.j'left = 1) and 
+                     (S22.k'left = 0) and 
+                     (S23.a'left = 15) and 
+                     (S23.b'left = 15) and 
+                     (S23.c'left = 15) and 
+                     (S23.d'left = 15) and 
+                     (S23.e'left = 15) and 
+                     (S23.f'left = 15) and 
+                     (S23.g'left = 15) and 
+                     (S24.a'left = 0) and 
+                     (S24.b'left = 0) and 
+                     (S24.c'left = 0) and 
+                     (S24.d'left = 0) and 
+                     (S24.e'left = 0) and 
+                     (S24.f'left = 0) and 
+                     (S24.g'left = 0) and 
+                     (S25'left = 0) and 
+                     (S26'left = 0) and 
+                     (S27'left = 0) and 
+                     (S28'left = 0) and 
+                     (S29'left = 0) and 
+                     (S30'left = 0) and 
+                     (S31'left = 0) and 
+                     (S32.a'left = 0) and 
+                     (S32.b'left = 0) and 
+                     (S32.c'left = 0) and 
+                     (S32.d'left = 0) and 
+                     (S32.e'left = 0) and 
+                     (S32.f'left = 0) and 
+                     (S32.g'left = 0) and 
+                     (S34.a'left = 0) and 
+                     (S34.b'left = 0) and 
+                     (S34.c'left = 0) and 
+                     (S34.d'left = 0) and 
+                     (S34.e'left = 0) and 
+                     (S34.f'left = 0) and 
+                     (S34.g'left = 0) and 
+                     (S36'left = 0) and 
+                     (S37'left = 0) and 
+                     (S38'left = 0) and 
+                     (S39'left = 0) and 
+--          (S40'left = 1) and 
+                     (S42'left = 0) and 
+                     (S43'left = 0) and 
+                     (S44'left = 0) and 
+                     (S45'left = 0) and 
+                     (S46'left = 0) and 
+                     (S47'left = 0) and 
+                     (S48'left = 0) and 
+                     (S49'left = 0) and 
+                     (S50'left = 0) and 
+                     (S51.a'left = 0) and 
+                     (S51.b'left = 0) and 
+                     (S51.c'left = 0) and 
+                     (S1'right = 15) and 
+                     (S2'right = 15) and 
+                     (S3'right = 15) and 
+                     (S4'right = 15) and 
+                     (S5'right = 15) and 
+                     (S6'right = 15) and 
+                     (S7'right = 15) and 
+                     (S8'right = 0) and 
+                     (S9'right = 0) and 
+                     (S10'right = 0)and 
+                     (S11'right = 0) and 
+                     (S12'right = 0) and 
+                     (S13'right = 0) and 
+                     (S14'right = 0) and 
+                     (S15'right = 15) and 
+                     (S16'right = 15) and 
+                     (S17'right = 15) and 
+                     (S18'right = 15) and 
+                     (S19'right = 15) and 
+                     (S20'right = 15) and 
+                     (S21'right = 15) and 
+                     (S22.j'right = 7) and 
+                     (S22.k'right = 3) and 
+                     (S23.a'right = 0) and 
+                     (S23.b'right = 0) and 
+                     (S23.c'right = 0) and 
+                     (S23.d'right = 0) and 
+                     (S23.e'right = 0) and 
+                     (S23.f'right = 0) and 
+                     (S23.g'right = 0) and 
+                     (S24.a'right = 15) and 
+                     (S24.b'right = 15) and 
+                     (S24.c'right = 15) and 
+                     (S24.d'right = 15) and 
+                     (S24.e'right = 15) and 
+                     (S24.f'right = 15) and 
+                     (S24.g'right = 15) and 
+                     (S25'right = 15) and 
+                     (S26'right = 15) and 
+                     (S27'right = 15) and 
+                     (S28'right = 15) and 
+                     (S29'right = 15) and 
+                     (S30'right = 15) and 
+                     (S31'right = 15) and 
+                     (S32.a'right = 15) and 
+                     (S32.b'right = 15) and 
+                     (S32.c'right = 15) and 
+                     (S32.d'right = 15) and 
+                     (S32.e'right = 15) and 
+                     (S32.f'right = 15) and 
+                     (S32.g'right = 15) and 
+                     (S34.a'right = 15) and 
+                     (S34.b'right = 15) and 
+                     (S34.c'right = 15) and 
+                     (S34.d'right = 15) and 
+                     (S34.e'right = 15) and 
+                     (S34.f'right = 15) and 
+                     (S34.g'right = 15) and 
+                     (S36'right = 7) and 
+                     (S37'right = 15) and  
+                     (S38'right = 3) and 
+                     (S39'right = 3) and 
+--          (S40'right = 1) and 
+                     (S41'right = 7) and 
+                     (S42'right = 7) and 
+                     (S43'right = 7) and 
+                     (S44'right = 7) and 
+                     (S45'right = 7) and 
+                     (S46'right = 7) and 
+                     (S47'right = 7) and 
+                     (S48'right = 7) and 
+                     (S49'right = 7) and 
+                     (S50'right = 7) and 
+                     (S51.a'right = 7) and 
+                     (S51.b'right = 7) and 
+                     (S51.c'right = 7) and 
+                     (S1'length = 16) and 
+                     (S2'length = 16) and 
+                     (S3'length = 16) and 
+                     (S4'length = 16) and 
+                     (S5'length = 16) and 
+                     (S6'length = 16) and 
+                     (S7'length = 16) and 
+                     (S8'length = 16) and 
+                     (S9'length = 16) and 
+                     (S10'length = 16) and 
+                     (S11'length = 16) and 
+                     (S12'length = 16) and 
+                     (S13'length = 16) and 
+                     (S14'length = 16) and 
+                     (S15'length = 16) and 
+                     (S16'length = 16) and 
+                     (S17'length = 16) and 
+                     (S18'length = 16) and 
+                     (S19'length = 16) and 
+                     (S20'length = 16) and 
+                     (S21'length = 16) and 
+                     (S22.j'length = 7)and 
+                     (S22.k'length = 4) and 
+                     (S23.a'length = 16) and 
+                     (S23.b'length = 16) and 
+                     (S23.c'length = 16) and 
+                     (S23.d'length = 16) and 
+                     (S23.e'length = 16) and 
+                     (S23.f'length = 16) and 
+                     (S23.g'length = 16) and 
+                     (S24.a'length = 16) and 
+                     (S24.b'length = 16) and 
+                     (S24.c'length = 16) and 
+                     (S24.d'length = 16) and 
+                     (S24.e'length = 16) and 
+                     (S24.f'length = 16) and 
+                     (S24.g'length = 16) and 
+                     (S25'length = 16) and 
+                     (S26'length = 16) and 
+                     (S27'length = 16) and 
+                     (S28'length = 16) and 
+                     (S29'length = 16) and 
+                     (S30'length = 16) and 
+                     (S31'length = 16) and 
+                     (S32.a'length = 16) and 
+                     (S32.b'length = 16) and 
+                     (S32.c'length = 16) and 
+                     (S32.d'length = 16) and 
+                     (S32.e'length = 16) and 
+                     (S32.f'length = 16) and 
+                     (S32.g'length = 16) and 
+                     (S34.a'length = 16) and 
+                     (S34.b'length = 16) and 
+                     (S34.c'length = 16) and 
+                     (S34.d'length = 16) and 
+                     (S34.e'length = 16) and 
+                     (S34.f'length = 16) and 
+                     (S34.g'length = 16) and 
+                     (S36'length = 8) and 
+                     (S37'length = 16) and 
+                     (S38'length = 4) and 
+                     (S39'length = 4) and 
+--          (S40'length = 1) and 
+                     (S41'length = 8) and 
+                     (S42'length = 8) and 
+                     (S43'length = 8) and 
+                     (S44'length = 8) and 
+                     (S45'length = 8) and 
+                     (S46'length = 8) and 
+                     (S48'length = 8) and 
+                     (S48'length = 8) and 
+                     (S49'length = 8) and 
+                     (S50'length = 8) and 
+                     (S51.a'length = 8) and 
+                     (S51.b'length = 8) and 
+                     (S51.c'length = 8) ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00755"
+      severity NOTE;
+    assert   ((S1'left = 0)    and 
+              (S2'left = 0)    and 
+              (S3'left = 0)    and 
+              (S4'left = 0)    and 
+              (S5'left = 0)    and 
+              (S6'left = 0)    and 
+              (S7'left = 0)    and 
+              (S8'left = 15) and 
+              (S9'left = 15) and 
+              (S10'left = 15) and 
+              (S11'left = 15) and 
+              (S12'left = 15) and 
+              (S13'left = 15) and 
+              (S14'left = 15) and 
+              (S15'left = 0) and 
+              (S16'left = 0) and 
+              (S17'left = 0) and 
+              (S18'left = 0) and 
+              (S19'left = 0) and 
+              (S20'left = 0) and 
+              (S21'left = 0) and 
+              (S22.j'left = 1) and 
+              (S22.k'left = 0) and 
+              (S23.a'left = 15) and 
+              (S23.b'left = 15) and 
+              (S23.c'left = 15) and 
+              (S23.d'left = 15) and 
+              (S23.e'left = 15) and 
+              (S23.f'left = 15) and 
+              (S23.g'left = 15) and 
+              (S24.a'left = 0) and 
+              (S24.b'left = 0) and 
+              (S24.c'left = 0) and 
+              (S24.d'left = 0) and 
+              (S24.e'left = 0) and 
+              (S24.f'left = 0) and 
+              (S24.g'left = 0) and 
+              (S25'left = 0) and 
+              (S26'left = 0) and 
+              (S27'left = 0) and 
+              (S28'left = 0) and 
+              (S29'left = 0) and 
+              (S30'left = 0) and 
+              (S31'left = 0) and 
+              (S32.a'left = 0) and 
+              (S32.b'left = 0) and 
+              (S32.c'left = 0) and 
+              (S32.d'left = 0) and 
+              (S32.e'left = 0) and 
+              (S32.f'left = 0) and 
+              (S32.g'left = 0) and 
+              (S34.a'left = 0) and 
+              (S34.b'left = 0) and 
+              (S34.c'left = 0) and 
+              (S34.d'left = 0) and 
+              (S34.e'left = 0) and 
+              (S34.f'left = 0) and 
+              (S34.g'left = 0) and 
+              (S36'left = 0) and 
+              (S37'left = 0) and 
+              (S38'left = 0) and 
+              (S39'left = 0) and 
+--          (S40'left = 1) and 
+              (S42'left = 0) and 
+              (S43'left = 0) and 
+              (S44'left = 0) and 
+              (S45'left = 0) and 
+              (S46'left = 0) and 
+              (S47'left = 0) and 
+              (S48'left = 0) and 
+              (S49'left = 0) and 
+              (S50'left = 0) and 
+              (S51.a'left = 0) and 
+              (S51.b'left = 0) and 
+              (S51.c'left = 0) and 
+              (S1'right = 15) and 
+              (S2'right = 15) and 
+              (S3'right = 15) and 
+              (S4'right = 15) and 
+              (S5'right = 15) and 
+              (S6'right = 15) and 
+              (S7'right = 15) and 
+              (S8'right = 0) and 
+              (S9'right = 0) and 
+              (S10'right = 0)and 
+              (S11'right = 0) and 
+              (S12'right = 0) and 
+              (S13'right = 0) and 
+              (S14'right = 0) and 
+              (S15'right = 15) and 
+              (S16'right = 15) and 
+              (S17'right = 15) and 
+              (S18'right = 15) and 
+              (S19'right = 15) and 
+              (S20'right = 15) and 
+              (S21'right = 15) and 
+              (S22.j'right = 7) and 
+              (S22.k'right = 3) and 
+              (S23.a'right = 0) and 
+              (S23.b'right = 0) and 
+              (S23.c'right = 0) and 
+              (S23.d'right = 0) and 
+              (S23.e'right = 0) and 
+              (S23.f'right = 0) and 
+              (S23.g'right = 0) and 
+              (S24.a'right = 15) and 
+              (S24.b'right = 15) and 
+              (S24.c'right = 15) and 
+              (S24.d'right = 15) and 
+              (S24.e'right = 15) and 
+              (S24.f'right = 15) and 
+              (S24.g'right = 15) and 
+              (S25'right = 15) and 
+              (S26'right = 15) and 
+              (S27'right = 15) and 
+              (S28'right = 15) and 
+              (S29'right = 15) and 
+              (S30'right = 15) and 
+              (S31'right = 15) and 
+              (S32.a'right = 15) and 
+              (S32.b'right = 15) and 
+              (S32.c'right = 15) and 
+              (S32.d'right = 15) and 
+              (S32.e'right = 15) and 
+              (S32.f'right = 15) and 
+              (S32.g'right = 15) and 
+              (S34.a'right = 15) and 
+              (S34.b'right = 15) and 
+              (S34.c'right = 15) and 
+              (S34.d'right = 15) and 
+              (S34.e'right = 15) and 
+              (S34.f'right = 15) and 
+              (S34.g'right = 15) and 
+              (S36'right = 7) and 
+              (S37'right = 15) and  
+              (S38'right = 3) and 
+              (S39'right = 3) and 
+--          (S40'right = 1) and 
+              (S41'right = 7) and 
+              (S42'right = 7) and 
+              (S43'right = 7) and 
+              (S44'right = 7) and 
+              (S45'right = 7) and 
+              (S46'right = 7) and 
+              (S47'right = 7) and 
+              (S48'right = 7) and 
+              (S49'right = 7) and 
+              (S50'right = 7) and 
+              (S51.a'right = 7) and 
+              (S51.b'right = 7) and 
+              (S51.c'right = 7) and 
+              (S1'length = 16) and 
+              (S2'length = 16) and 
+              (S3'length = 16) and 
+              (S4'length = 16) and 
+              (S5'length = 16) and 
+              (S6'length = 16) and 
+              (S7'length = 16) and 
+              (S8'length = 16) and 
+              (S9'length = 16) and 
+              (S10'length = 16) and 
+              (S11'length = 16) and 
+              (S12'length = 16) and 
+              (S13'length = 16) and 
+              (S14'length = 16) and 
+              (S15'length = 16) and 
+              (S16'length = 16) and 
+              (S17'length = 16) and 
+              (S18'length = 16) and 
+              (S19'length = 16) and 
+              (S20'length = 16) and 
+              (S21'length = 16) and 
+              (S22.j'length = 7)and 
+              (S22.k'length = 4) and 
+              (S23.a'length = 16) and 
+              (S23.b'length = 16) and 
+              (S23.c'length = 16) and 
+              (S23.d'length = 16) and 
+              (S23.e'length = 16) and 
+              (S23.f'length = 16) and 
+              (S23.g'length = 16) and 
+              (S24.a'length = 16) and 
+              (S24.b'length = 16) and 
+              (S24.c'length = 16) and 
+              (S24.d'length = 16) and 
+              (S24.e'length = 16) and 
+              (S24.f'length = 16) and 
+              (S24.g'length = 16) and 
+              (S25'length = 16) and 
+              (S26'length = 16) and 
+              (S27'length = 16) and 
+              (S28'length = 16) and 
+              (S29'length = 16) and 
+              (S30'length = 16) and 
+              (S31'length = 16) and 
+              (S32.a'length = 16) and 
+              (S32.b'length = 16) and 
+              (S32.c'length = 16) and 
+              (S32.d'length = 16) and 
+              (S32.e'length = 16) and 
+              (S32.f'length = 16) and 
+              (S32.g'length = 16) and 
+              (S34.a'length = 16) and 
+              (S34.b'length = 16) and 
+              (S34.c'length = 16) and 
+              (S34.d'length = 16) and 
+              (S34.e'length = 16) and 
+              (S34.f'length = 16) and 
+              (S34.g'length = 16) and 
+              (S36'length = 8) and 
+              (S37'length = 16) and 
+              (S38'length = 4) and 
+              (S39'length = 4) and 
+--          (S40'length = 1) and 
+              (S41'length = 8) and 
+              (S42'length = 8) and 
+              (S43'length = 8) and 
+              (S44'length = 8) and 
+              (S45'length = 8) and 
+              (S46'length = 8) and 
+              (S48'length = 8) and 
+              (S48'length = 8) and 
+              (S49'length = 8) and 
+              (S50'length = 8) and 
+              (S51.a'length = 8) and 
+              (S51.b'length = 8) and 
+              (S51.c'length = 8) ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00755 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00755arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc756.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc756.vhd
new file mode 100644
index 0000000..c3c199c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc756.vhd
@@ -0,0 +1,1018 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc756.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00756ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00756ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00756arch OF c01s01b01x01p05n02i00756ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector; 
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+  
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_rec(zero to seven);
+                                  end record;
+
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+  
+  type byte is array(zero to seven) of bit;
+  
+  subtype word is bit_vector(zero to fifteen);                                 --constrained array
+  
+  constant size :integer := seven;
+  
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  
+  type primary_memory_module is                                       --record with field
+    record                                                               --as an array
+      enable:bit;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;     --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  constant C12    : boolean_vector := (C1,false);
+  constant C13    : severity_level_vector := (C4,error);
+  constant C14    : integer_vector := (one,two,three,four);
+  constant C15    : real_vector := (1.0,2.0,C6,4.0);
+  constant C16    : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant C17    : natural_vector := (one,2,3,4);
+  constant C18    : positive_vector := (one,2,3,4);
+  constant C19    : boolean_cons_vector := (others => C1);
+  constant C20    : severity_level_cons_vector := (others => C4);
+  constant C21    : integer_cons_vector := (others => C5);
+  constant C22    : real_cons_vector := (others => C6);
+  constant C23    : time_cons_vector :=  (others => C7);
+  constant C24    : natural_cons_vector :=  (others => C8);
+  constant C25    : positive_cons_vector :=  (others => C9);
+  constant C26    : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27    : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28    : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29    : real_cons_vectorofvector := (others => (others => C6));
+  constant C30    : time_cons_vectorofvector := (others => (others => C7));
+  constant C31    : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32    : positive_cons_vectorofvector := (others => (others => C9));
+  constant C50    : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
+  constant C51    : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C53    : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+  constant C70    : boolean_vector_st :=(others => C1);
+  constant C71    : severity_level_vector_st:= (others => C4);
+  constant C72    : integer_vector_st:=(others => C5);
+  constant C73    : real_vector_st:=(others => C6);
+  constant C74    : time_vector_st:=(others => C7);
+  constant C75    : natural_vector_st:=(others => C8);
+  constant C76    : positive_vector_st:=(others => C9);
+  constant C77    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54a    : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+  constant C54b   : record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
+  constant C55    : record_of_records := (C50,C51,C53,C77,C54b);
+  constant C60    : byte := (others => '0');
+  constant C61    : word := (others =>'0' );
+  constant C64    : primary_memory := (others => C61);
+  constant C65    : primary_memory_module := ('1',C64);
+  constant C66    : whole_memory := (others => C65);
+  constant C67    : current := 1 A;
+  constant C68    : resistance := 1 Ohm;
+  constant C69    : delay := 2;
+  constant C78   : boolean_vector_range := (others => C1);
+  constant C79   : severity_level_vector_range := (others => C4) ;
+  constant C80   : integer_vector_range :=(others => C5) ;
+  constant C81   : real_vector_range :=(others => C6);
+  constant C82   : time_vector_range :=(others => C7);
+  constant C83   : natural_vector_range :=(others => C8);
+  constant C84   : positive_vector_range :=(others => C9);
+  constant C85   : array_rec_std(0 to 7) :=(others => C50)  ;
+  constant C86   : array_rec_cons (0 to 7) :=(others => C51);
+  constant C88   : array_rec_rec(0 to 7) :=(others => C55);
+  constant C102   : record_of_arr_of_record:= (C85,C86,C88);
+  
+BEGIN
+  TESTING: PROCESS
+    variable V1    : boolean_vector(zero to fifteen);
+    variable V2    : severity_level_vector(zero to fifteen);
+    variable V3    : integer_vector(zero to fifteen);
+    variable V4    : real_vector(zero to fifteen);
+    variable V5    : time_vector (zero to fifteen);
+    variable V6    : natural_vector(zero to fifteen);
+    variable V7    : positive_vector(zero to fifteen);
+    variable V8    : boolean_cons_vector;
+    variable V9    : severity_level_cons_vector ;
+    variable V10    : integer_cons_vector;
+    variable V11    : real_cons_vector;
+    variable V12    : time_cons_vector ;
+    variable V13    : natural_cons_vector ;
+    variable V14    : positive_cons_vector ;
+    variable V15    : boolean_cons_vectorofvector;
+    variable V16    : severity_level_cons_vectorofvector;
+    variable V17    : integer_cons_vectorofvector;
+    variable V18    : real_cons_vectorofvector;
+    variable V19    : time_cons_vectorofvector;
+    variable V20    : natural_cons_vectorofvector;
+    variable V21    : positive_cons_vectorofvector;
+    variable V22    : record_std_package;
+    variable V23    : record_cons_array;
+    variable V24    : record_cons_arrayofarray ;
+    variable V25    : boolean_vector_st;
+    variable V26    : severity_level_vector_st;
+    variable V27    : integer_vector_st;
+    variable V28    : real_vector_st;
+    variable V29    : time_vector_st;
+    variable V30    : natural_vector_st;
+    variable V31    : positive_vector_st;
+    variable V32    : record_array_st;
+    variable V33    : record_array_st;
+    variable V34   : record_array_new;
+    variable V35    : record_of_records;
+    variable V36    : byte;
+    variable V37    : word;
+    variable V38    : current_vector(zero to three);
+    variable V39    : resistance_vector(zero to three);
+    variable V40    : delay;
+    variable V41   : boolean_vector_range;
+    variable V42   : severity_level_vector_range ;
+    variable V43   : integer_vector_range ;
+    variable V44   : real_vector_range ;
+    variable V45   : time_vector_range ;
+    variable V46   : natural_vector_range ;
+    variable V47   : positive_vector_range ;
+    variable V48   : array_rec_std(zero to seven);
+    variable V49   : array_rec_cons(zero to seven);
+    variable V50   : array_rec_rec(zero to seven);
+    variable V51   : record_of_arr_of_record;
+
+  BEGIN
+    assert (V1'left = 0) report " boolean_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V2'left = 0) report " severity_level_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V3'left = 0) report " integer_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V4'left = 0) report " real_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V5'left = 0) report " time_vector (zero to fifteen) error in the left generic value" severity  error;
+    assert (V6'left = 0) report " natural_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V7'left = 0) report " positive_vector(zero to fifteen) error in the left generic value" severity  error;
+    assert (V8'left = 15) report " boolean_cons_vector error in the left generic value" severity  error;
+    assert (V9'left = 15) report " severity_level_cons_vector  error in the left generic value" severity  error;
+    assert (V10'left = 15) report " integer_cons_vector error in the left generic value" severity  error;
+    assert (V11'left = 15) report " real_cons_vector error in the left generic value" severity  error;
+    assert (V12'left = 15) report " time_cons_vector  error in the left generic value" severity  error;
+    assert (V13'left = 15) report " natural_cons_vector  error in the left generic value" severity  error;
+    assert (V14'left = 15) report " positive_cons_vector  error in the left generic value" severity  error;
+    assert (V15'left = 0) report " boolean_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V16'left = 0) report " severity_level_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V17'left = 0) report " integer_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V18'left = 0) report " real_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V19'left = 0) report " time_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V20'left = 0) report " natural_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V21'left = 0) report " positive_cons_vectorofvector error in the left generic value" severity  error;
+    assert (V22.j'left = 1) report " record_std_package error in the left generic value" severity  error;
+    assert (V22.k'left = 0) report " record_std_package error in the left generic value" severity  error;
+    assert (V23.a'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.b'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.c'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.d'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.e'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.f'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V23.g'left = 15) report " record_cons_array error in the left generic value" severity  error;
+    assert (V24.a'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.b'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.c'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.d'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.e'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.f'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V24.g'left = 0) report " record_cons_arrayofarray  error in the left generic value" severity  error;
+    assert (V25'left = 0) report " boolean_vector_st error in the left generic value" severity  error;
+    assert (V26'left = 0) report "  severity_level_vector_st error in the left generic value" severity  error;
+    assert (V27'left = 0) report "  integer_vector_st error in the left generic value" severity  error;
+    assert (V28'left = 0) report "  real_vector_st error in the left generic value" severity  error;
+    assert (V29'left = 0) report "  time_vector_st error in the left generic value" severity  error;
+    assert (V30'left = 0) report "  natural_vector_st error in the left generic value" severity  error;
+    assert (V31'left = 0) report " positive_vector_st error in the left generic value" severity  error;
+    assert (V32.a'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.b'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.c'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.d'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.e'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.f'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V32.g'left = 0) report " record_array_st error in the left generic value" severity  error;
+    assert (V34.a'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.b'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.c'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.d'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.e'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.f'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V34.g'left = 0) report " record_array_new error in the left generic value" severity  error;
+    assert (V36'left = 0) report " byte error in the left generic value" severity  error;
+    assert (V37'left = 0) report " word error in the left generic value" severity  error;
+    assert (V38'left = 0) report " current_vector(zero to three) error in the left generic value" severity  error;
+    assert (V39'left = 0) report " resistance_vector(zero to three) error in the left generic value" severity  error;
+--assert (V40'left = 1) report " delay error in the left generic value" severity  error;
+    assert (V41'left = 0) report " boolean_vector_range error in the left generic value" severity  error;
+    assert (V42'left = 0) report " severity_level_vector_range  error in the left generic value" severity  error;
+    assert (V43'left = 0) report " integer_vector_range  error in the left generic value" severity  error;
+    assert (V44'left = 0) report " real_vector_range  error in the left generic value" severity  error;
+    assert (V45'left = 0) report " time_vector_range  error in the left generic value" severity  error;
+    assert (V46'left = 0) report " natural_vector_range  error in the left generic value" severity  error;
+    assert (V47'left = 0) report " positive_vector_range  error in the left generic value" severity  error;
+    assert (V48'left = 0) report " array_rec_std(zero to seven) error in the left generic value" severity  error;
+    assert (V49'left = 0) report " array_rec_cons(zero to seven) error in the left generic value" severity  error;
+    assert (V50'left = 0) report " array_rec_rec(zero to seven) error in the left generic value" severity  error;
+    assert (V51.a'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+    assert (V51.b'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+    assert (V51.c'left = 0) report " record_of_arr_of_record error in the left generic value" severity  error;
+    
+    assert (V1'right = 15) report " boolean_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V2'right = 15) report " severity_level_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V3'right = 15) report " integer_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V4'right = 15) report " real_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V5'right = 15) report " time_vector (zero to fifteen) error in the right generic value" severity  error;
+    assert (V6'right = 15) report " natural_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V7'right = 15) report " positive_vector(zero to fifteen) error in the right generic value" severity  error;
+    assert (V8'right = 0) report " boolean_cons_vector error in the right generic value" severity  error;
+    assert (V9'right = 0) report " severity_level_cons_vector  error in the right generic value" severity  error;
+    assert (V10'right = 0) report " integer_cons_vector error in the right generic value" severity  error;
+    assert (V11'right = 0) report " real_cons_vector error in the right generic value" severity  error;
+    assert (V12'right = 0) report " time_cons_vector  error in the right generic value" severity  error;
+    assert (V13'right = 0) report " natural_cons_vector  error in the right generic value" severity  error;
+    assert (V14'right = 0) report " positive_cons_vector  error in the right generic value" severity  error;
+    assert (V15'right = 15) report " boolean_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V16'right = 15) report " severity_level_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V17'right = 15) report " integer_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V18'right = 15) report " real_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V19'right = 15) report " time_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V20'right = 15) report " natural_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V21'right = 15) report " positive_cons_vectorofvector error in the right generic value" severity  error;
+    assert (V22.j'right = 7) report " record_std_package error in the right generic value" severity  error;
+    assert (V22.k'right = 3) report " record_std_package error in the right generic value" severity  error;
+    assert (V23.a'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.b'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.c'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.d'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.e'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.f'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V23.g'right = 0) report " record_cons_array error in the right generic value" severity  error;
+    assert (V24.a'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.b'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.c'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.d'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.e'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.f'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V24.g'right = 15) report " record_cons_arrayofarray  error in the right generic value" severity  error;
+    assert (V25'right = 15) report " boolean_vector_st error in the right generic value" severity  error;
+    assert (V26'right = 15) report "  severity_level_vector_st error in the right generic value" severity  error;
+    assert (V27'right = 15) report "  integer_vector_st error in the right generic value" severity  error;
+    assert (V28'right = 15) report "  real_vector_st error in the right generic value" severity  error;
+    assert (V29'right = 15) report "  time_vector_st error in the right generic value" severity  error;
+    assert (V30'right = 15) report "  natural_vector_st error in the right generic value" severity  error;
+    assert (V31'right = 15) report " positive_vector_st error in the right generic value" severity  error;
+    assert (V32.a'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.b'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.c'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.d'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.e'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.f'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V32.g'right = 15) report " record_array_st error in the right generic value" severity  error;
+    assert (V34.a'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.b'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.c'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.d'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.e'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.f'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V34.g'right = 15) report " record_array_new error in the right generic value" severity  error;
+    assert (V36'right = 7) report " byte error in the right generic value" severity  error;
+    assert (V37'right = 15) report " word error in the right generic value" severity  error;
+    assert (V38'right = 3) report " current_vector(zero to three) error in the right generic value" severity  error;
+    assert (V39'right = 3) report " resistance_vector(zero to three) error in the right generic value" severity  error;
+--assert (V40'right = 1) report " delay error in the right generic value" severity  error;
+    assert (V41'right = 7) report " boolean_vector_range error in the right generic value" severity  error;
+    assert (V42'right = 7) report " severity_level_vector_range  error in the right generic value" severity  error;
+    assert (V43'right = 7) report " integer_vector_range  error in the right generic value" severity  error;
+    assert (V44'right = 7) report " real_vector_range  error in the right generic value" severity  error;
+    assert (V45'right = 7) report " time_vector_range  error in the right generic value" severity  error;
+    assert (V46'right = 7) report " natural_vector_range  error in the right generic value" severity  error;
+    assert (V47'right = 7) report " positive_vector_range  error in the right generic value" severity  error;
+    assert (V48'right = 7) report " array_rec_std(zero to seven) error in the right generic value" severity  error;
+    assert (V49'right = 7) report " array_rec_cons(zero to seven) error in the right generic value" severity  error;
+    assert (V50'right = 7) report " array_rec_rec(zero to seven) error in the right generic value" severity  error;
+    assert (V51.a'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+    assert (V51.b'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+    assert (V51.c'right = 7) report " record_of_arr_of_record error in the right generic value" severity  error;
+    assert (V1'length = 16) report " boolean_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V2'length = 16) report " severity_level_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V3'length = 16) report " integer_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V4'length = 16) report " real_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V5'length = 16) report " time_vector (zero to fifteen) error in the length generic value" severity  error;
+    assert (V6'length = 16) report " natural_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V7'length = 16) report " positive_vector(zero to fifteen) error in the length generic value" severity  error;
+    assert (V8'length = 16) report " boolean_cons_vector error in the length generic value" severity  error;
+    assert (V9'length = 16) report " severity_level_cons_vector  error in the length generic value" severity  error;
+    assert (V10'length = 16) report " integer_cons_vector error in the length generic value" severity  error;
+    assert (V11'length = 16) report " real_cons_vector error in the length generic value" severity  error;
+    assert (V12'length = 16) report " time_cons_vector  error in the length generic value" severity  error;
+    assert (V13'length = 16) report " natural_cons_vector  error in the length generic value" severity  error;
+    assert (V14'length = 16) report " positive_cons_vector  error in the length generic value" severity  error;
+    assert (V15'length = 16) report " boolean_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V16'length = 16) report " severity_level_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V17'length = 16) report " integer_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V18'length = 16) report " real_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V19'length = 16) report " time_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V20'length = 16) report " natural_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V21'length = 16) report " positive_cons_vectorofvector error in the length generic value" severity  error;
+    assert (V22.j'length = 7) report " record_std_package error in the length generic value" severity  error;
+    assert (V22.k'length = 4) report " record_std_package error in the length generic value" severity  error;
+    assert (V23.a'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.b'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.c'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.d'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.e'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.f'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V23.g'length = 16) report " record_cons_array error in the length generic value" severity  error;
+    assert (V24.a'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.b'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.c'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.d'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.e'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.f'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V24.g'length = 16) report " record_cons_arrayofarray  error in the length generic value" severity  error;
+    assert (V25'length = 16) report " boolean_vector_st error in the length generic value" severity  error;
+    assert (V26'length = 16) report "  severity_level_vector_st error in the length generic value" severity  error;
+    assert (V27'length = 16) report "  integer_vector_st error in the length generic value" severity  error;
+    assert (V28'length = 16) report "  real_vector_st error in the length generic value" severity  error;
+    assert (V29'length = 16) report "  time_vector_st error in the length generic value" severity  error;
+    assert (V30'length = 16) report "  natural_vector_st error in the length generic value" severity  error;
+    assert (V31'length = 16) report " positive_vector_st error in the length generic value" severity  error;
+    assert (V32.a'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.b'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.c'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.d'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.e'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.f'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V32.g'length = 16) report " record_array_st error in the length generic value" severity  error;
+    assert (V34.a'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.b'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.c'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.d'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.e'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.f'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V34.g'length = 16) report " record_array_new error in the length generic value" severity  error;
+    assert (V36'length = 8) report " byte error in the length generic value" severity  error;
+    assert (V37'length = 16) report " word error in the length generic value" severity  error;
+    assert (V38'length = 4) report " current_vector(zero to three) error in the length generic value" severity  error;
+    assert (V39'length = 4) report " resistance_vector(zero to three) error in the length generic value" severity  error;
+--assert (V40'length = 1) report " delay error in the length generic value" severity  error;
+    assert (V41'length = 8) report " boolean_vector_range error in the length generic value" severity  error;
+    assert (V42'length = 8) report " severity_level_vector_range  error in the length generic value" severity  error;
+    assert (V43'length = 8) report " integer_vector_range  error in the length generic value" severity  error;
+    assert (V44'length = 8) report " real_vector_range  error in the length generic value" severity  error;
+    assert (V45'length = 8) report " time_vector_range  error in the length generic value" severity  error;
+    assert (V46'length = 8) report " natural_vector_range  error in the length generic value" severity  error;
+    assert (V48'length = 8) report " positive_vector_range  error in the length generic value" severity  error;
+    assert (V48'length = 8) report " array_rec_std(zero to seven) error in the length generic value" severity  error;
+    assert (V49'length = 8) report " array_rec_cons(zero to seven) error in the length generic value" severity  error;
+    assert (V50'length = 8) report " array_rec_rec(zero to seven) error in the length generic value" severity  error;
+    assert (V51.a'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+    assert (V51.b'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+    assert (V51.c'length = 8) report " record_of_arr_of_record error in the length generic value" severity  error;
+
+
+    assert   NOT(    (V1'left = 0)    and 
+                     (V2'left = 0)    and 
+                     (V3'left = 0)    and 
+                     (V4'left = 0)    and 
+                     (V5'left = 0)    and 
+                     (V6'left = 0)    and 
+                     (V7'left = 0)    and 
+                     (V8'left = 15) and 
+                     (V9'left = 15) and 
+                     (V10'left = 15) and 
+                     (V11'left = 15) and 
+                     (V12'left = 15) and 
+                     (V13'left = 15) and 
+                     (V14'left = 15) and 
+                     (V15'left = 0) and 
+                     (V16'left = 0) and 
+                     (V17'left = 0) and 
+                     (V18'left = 0) and 
+                     (V19'left = 0) and 
+                     (V20'left = 0) and 
+                     (V21'left = 0) and 
+                     (V22.j'left = 1) and 
+                     (V22.k'left = 0) and 
+                     (V23.a'left = 15) and 
+                     (V23.b'left = 15) and 
+                     (V23.c'left = 15) and 
+                     (V23.d'left = 15) and 
+                     (V23.e'left = 15) and 
+                     (V23.f'left = 15) and 
+                     (V23.g'left = 15) and 
+                     (V24.a'left = 0) and 
+                     (V24.b'left = 0) and 
+                     (V24.c'left = 0) and 
+                     (V24.d'left = 0) and 
+                     (V24.e'left = 0) and 
+                     (V24.f'left = 0) and 
+                     (V24.g'left = 0) and 
+                     (V25'left = 0) and 
+                     (V26'left = 0) and 
+                     (V27'left = 0) and 
+                     (V28'left = 0) and 
+                     (V29'left = 0) and 
+                     (V30'left = 0) and 
+                     (V31'left = 0) and 
+                     (V32.a'left = 0) and 
+                     (V32.b'left = 0) and 
+                     (V32.c'left = 0) and 
+                     (V32.d'left = 0) and 
+                     (V32.e'left = 0) and 
+                     (V32.f'left = 0) and 
+                     (V32.g'left = 0) and 
+                     (V34.a'left = 0) and 
+                     (V34.b'left = 0) and 
+                     (V34.c'left = 0) and 
+                     (V34.d'left = 0) and 
+                     (V34.e'left = 0) and 
+                     (V34.f'left = 0) and 
+                     (V34.g'left = 0) and 
+                     (V36'left = 0) and 
+                     (V37'left = 0) and 
+                     (V38'left = 0) and 
+                     (V39'left = 0) and 
+--          (V40'left = 1) and 
+                     (V42'left = 0) and 
+                     (V43'left = 0) and 
+                     (V44'left = 0) and 
+                     (V45'left = 0) and 
+                     (V46'left = 0) and 
+                     (V47'left = 0) and 
+                     (V48'left = 0) and 
+                     (V49'left = 0) and 
+                     (V50'left = 0) and 
+                     (V51.a'left = 0) and 
+                     (V51.b'left = 0) and 
+                     (V51.c'left = 0) and 
+                     (V1'right = 15) and 
+                     (V2'right = 15) and 
+                     (V3'right = 15) and 
+                     (V4'right = 15) and 
+                     (V5'right = 15) and 
+                     (V6'right = 15) and 
+                     (V7'right = 15) and 
+                     (V8'right = 0) and 
+                     (V9'right = 0) and 
+                     (V10'right = 0)and 
+                     (V11'right = 0) and 
+                     (V12'right = 0) and 
+                     (V13'right = 0) and 
+                     (V14'right = 0) and 
+                     (V15'right = 15) and 
+                     (V16'right = 15) and 
+                     (V17'right = 15) and 
+                     (V18'right = 15) and 
+                     (V19'right = 15) and 
+                     (V20'right = 15) and 
+                     (V21'right = 15) and 
+                     (V22.j'right = 7) and 
+                     (V22.k'right = 3) and 
+                     (V23.a'right = 0) and 
+                     (V23.b'right = 0) and 
+                     (V23.c'right = 0) and 
+                     (V23.d'right = 0) and 
+                     (V23.e'right = 0) and 
+                     (V23.f'right = 0) and 
+                     (V23.g'right = 0) and 
+                     (V24.a'right = 15) and 
+                     (V24.b'right = 15) and 
+                     (V24.c'right = 15) and 
+                     (V24.d'right = 15) and 
+                     (V24.e'right = 15) and 
+                     (V24.f'right = 15) and 
+                     (V24.g'right = 15) and 
+                     (V25'right = 15) and 
+                     (V26'right = 15) and 
+                     (V27'right = 15) and 
+                     (V28'right = 15) and 
+                     (V29'right = 15) and 
+                     (V30'right = 15) and 
+                     (V31'right = 15) and 
+                     (V32.a'right = 15) and 
+                     (V32.b'right = 15) and 
+                     (V32.c'right = 15) and 
+                     (V32.d'right = 15) and 
+                     (V32.e'right = 15) and 
+                     (V32.f'right = 15) and 
+                     (V32.g'right = 15) and 
+                     (V34.a'right = 15) and 
+                     (V34.b'right = 15) and 
+                     (V34.c'right = 15) and 
+                     (V34.d'right = 15) and 
+                     (V34.e'right = 15) and 
+                     (V34.f'right = 15) and 
+                     (V34.g'right = 15) and 
+                     (V36'right = 7) and 
+                     (V37'right = 15) and  
+                     (V38'right = 3) and 
+                     (V39'right = 3) and 
+--          (V40'right = 1) and 
+                     (V41'right = 7) and 
+                     (V42'right = 7) and 
+                     (V43'right = 7) and 
+                     (V44'right = 7) and 
+                     (V45'right = 7) and 
+                     (V46'right = 7) and 
+                     (V47'right = 7) and 
+                     (V48'right = 7) and 
+                     (V49'right = 7) and 
+                     (V50'right = 7) and 
+                     (V51.a'right = 7) and 
+                     (V51.b'right = 7) and 
+                     (V51.c'right = 7) and 
+                     (V1'length = 16) and 
+                     (V2'length = 16) and 
+                     (V3'length = 16) and 
+                     (V4'length = 16) and 
+                     (V5'length = 16) and 
+                     (V6'length = 16) and 
+                     (V7'length = 16) and 
+                     (V8'length = 16) and 
+                     (V9'length = 16) and 
+                     (V10'length = 16) and 
+                     (V11'length = 16) and 
+                     (V12'length = 16) and 
+                     (V13'length = 16) and 
+                     (V14'length = 16) and 
+                     (V15'length = 16) and 
+                     (V16'length = 16) and 
+                     (V17'length = 16) and 
+                     (V18'length = 16) and 
+                     (V19'length = 16) and 
+                     (V20'length = 16) and 
+                     (V21'length = 16) and 
+                     (V22.j'length = 7)and 
+                     (V22.k'length = 4) and 
+                     (V23.a'length = 16) and 
+                     (V23.b'length = 16) and 
+                     (V23.c'length = 16) and 
+                     (V23.d'length = 16) and 
+                     (V23.e'length = 16) and 
+                     (V23.f'length = 16) and 
+                     (V23.g'length = 16) and 
+                     (V24.a'length = 16) and 
+                     (V24.b'length = 16) and 
+                     (V24.c'length = 16) and 
+                     (V24.d'length = 16) and 
+                     (V24.e'length = 16) and 
+                     (V24.f'length = 16) and 
+                     (V24.g'length = 16) and 
+                     (V25'length = 16) and 
+                     (V26'length = 16) and 
+                     (V27'length = 16) and 
+                     (V28'length = 16) and 
+                     (V29'length = 16) and 
+                     (V30'length = 16) and 
+                     (V31'length = 16) and 
+                     (V32.a'length = 16) and 
+                     (V32.b'length = 16) and 
+                     (V32.c'length = 16) and 
+                     (V32.d'length = 16) and 
+                     (V32.e'length = 16) and 
+                     (V32.f'length = 16) and 
+                     (V32.g'length = 16) and 
+                     (V34.a'length = 16) and 
+                     (V34.b'length = 16) and 
+                     (V34.c'length = 16) and 
+                     (V34.d'length = 16) and 
+                     (V34.e'length = 16) and 
+                     (V34.f'length = 16) and 
+                     (V34.g'length = 16) and 
+                     (V36'length = 8) and 
+                     (V37'length = 16) and 
+                     (V38'length = 4) and 
+                     (V39'length = 4) and 
+--          (V40'length = 1) and 
+                     (V41'length = 8) and 
+                     (V42'length = 8) and 
+                     (V43'length = 8) and 
+                     (V44'length = 8) and 
+                     (V45'length = 8) and 
+                     (V46'length = 8) and 
+                     (V48'length = 8) and 
+                     (V48'length = 8) and 
+                     (V49'length = 8) and 
+                     (V50'length = 8) and 
+                     (V51.a'length = 8) and 
+                     (V51.b'length = 8) and 
+                     (V51.c'length = 8) ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00756"
+      severity NOTE;
+    assert   ((V1'left = 0)    and 
+              (V2'left = 0)    and 
+              (V3'left = 0)    and 
+              (V4'left = 0)    and 
+              (V5'left = 0)    and 
+              (V6'left = 0)    and 
+              (V7'left = 0)    and 
+              (V8'left = 15) and 
+              (V9'left = 15) and 
+              (V10'left = 15) and 
+              (V11'left = 15) and 
+              (V12'left = 15) and 
+              (V13'left = 15) and 
+              (V14'left = 15) and 
+              (V15'left = 0) and 
+              (V16'left = 0) and 
+              (V17'left = 0) and 
+              (V18'left = 0) and 
+              (V19'left = 0) and 
+              (V20'left = 0) and 
+              (V21'left = 0) and 
+              (V22.j'left = 1) and 
+              (V22.k'left = 0) and 
+              (V23.a'left = 15) and 
+              (V23.b'left = 15) and 
+              (V23.c'left = 15) and 
+              (V23.d'left = 15) and 
+              (V23.e'left = 15) and 
+              (V23.f'left = 15) and 
+              (V23.g'left = 15) and 
+              (V24.a'left = 0) and 
+              (V24.b'left = 0) and 
+              (V24.c'left = 0) and 
+              (V24.d'left = 0) and 
+              (V24.e'left = 0) and 
+              (V24.f'left = 0) and 
+              (V24.g'left = 0) and 
+              (V25'left = 0) and 
+              (V26'left = 0) and 
+              (V27'left = 0) and 
+              (V28'left = 0) and 
+              (V29'left = 0) and 
+              (V30'left = 0) and 
+              (V31'left = 0) and 
+              (V32.a'left = 0) and 
+              (V32.b'left = 0) and 
+              (V32.c'left = 0) and 
+              (V32.d'left = 0) and 
+              (V32.e'left = 0) and 
+              (V32.f'left = 0) and 
+              (V32.g'left = 0) and 
+              (V34.a'left = 0) and 
+              (V34.b'left = 0) and 
+              (V34.c'left = 0) and 
+              (V34.d'left = 0) and 
+              (V34.e'left = 0) and 
+              (V34.f'left = 0) and 
+              (V34.g'left = 0) and 
+              (V36'left = 0) and 
+              (V37'left = 0) and 
+              (V38'left = 0) and 
+              (V39'left = 0) and 
+--          (V40'left = 1) and 
+              (V42'left = 0) and 
+              (V43'left = 0) and 
+              (V44'left = 0) and 
+              (V45'left = 0) and 
+              (V46'left = 0) and 
+              (V47'left = 0) and 
+              (V48'left = 0) and 
+              (V49'left = 0) and 
+              (V50'left = 0) and 
+              (V51.a'left = 0) and 
+              (V51.b'left = 0) and 
+              (V51.c'left = 0) and 
+              (V1'right = 15) and 
+              (V2'right = 15) and 
+              (V3'right = 15) and 
+              (V4'right = 15) and 
+              (V5'right = 15) and 
+              (V6'right = 15) and 
+              (V7'right = 15) and 
+              (V8'right = 0) and 
+              (V9'right = 0) and 
+              (V10'right = 0)and 
+              (V11'right = 0) and 
+              (V12'right = 0) and 
+              (V13'right = 0) and 
+              (V14'right = 0) and 
+              (V15'right = 15) and 
+              (V16'right = 15) and 
+              (V17'right = 15) and 
+              (V18'right = 15) and 
+              (V19'right = 15) and 
+              (V20'right = 15) and 
+              (V21'right = 15) and 
+              (V22.j'right = 7) and 
+              (V22.k'right = 3) and 
+              (V23.a'right = 0) and 
+              (V23.b'right = 0) and 
+              (V23.c'right = 0) and 
+              (V23.d'right = 0) and 
+              (V23.e'right = 0) and 
+              (V23.f'right = 0) and 
+              (V23.g'right = 0) and 
+              (V24.a'right = 15) and 
+              (V24.b'right = 15) and 
+              (V24.c'right = 15) and 
+              (V24.d'right = 15) and 
+              (V24.e'right = 15) and 
+              (V24.f'right = 15) and 
+              (V24.g'right = 15) and 
+              (V25'right = 15) and 
+              (V26'right = 15) and 
+              (V27'right = 15) and 
+              (V28'right = 15) and 
+              (V29'right = 15) and 
+              (V30'right = 15) and 
+              (V31'right = 15) and 
+              (V32.a'right = 15) and 
+              (V32.b'right = 15) and 
+              (V32.c'right = 15) and 
+              (V32.d'right = 15) and 
+              (V32.e'right = 15) and 
+              (V32.f'right = 15) and 
+              (V32.g'right = 15) and 
+              (V34.a'right = 15) and 
+              (V34.b'right = 15) and 
+              (V34.c'right = 15) and 
+              (V34.d'right = 15) and 
+              (V34.e'right = 15) and 
+              (V34.f'right = 15) and 
+              (V34.g'right = 15) and 
+              (V36'right = 7) and 
+              (V37'right = 15) and  
+              (V38'right = 3) and 
+              (V39'right = 3) and 
+--          (V40'right = 1) and 
+              (V41'right = 7) and 
+              (V42'right = 7) and 
+              (V43'right = 7) and 
+              (V44'right = 7) and 
+              (V45'right = 7) and 
+              (V46'right = 7) and 
+              (V47'right = 7) and 
+              (V48'right = 7) and 
+              (V49'right = 7) and 
+              (V50'right = 7) and 
+              (V51.a'right = 7) and 
+              (V51.b'right = 7) and 
+              (V51.c'right = 7) and 
+              (V1'length = 16) and 
+              (V2'length = 16) and 
+              (V3'length = 16) and 
+              (V4'length = 16) and 
+              (V5'length = 16) and 
+              (V6'length = 16) and 
+              (V7'length = 16) and 
+              (V8'length = 16) and 
+              (V9'length = 16) and 
+              (V10'length = 16) and 
+              (V11'length = 16) and 
+              (V12'length = 16) and 
+              (V13'length = 16) and 
+              (V14'length = 16) and 
+              (V15'length = 16) and 
+              (V16'length = 16) and 
+              (V17'length = 16) and 
+              (V18'length = 16) and 
+              (V19'length = 16) and 
+              (V20'length = 16) and 
+              (V21'length = 16) and 
+              (V22.j'length = 7)and 
+              (V22.k'length = 4) and 
+              (V23.a'length = 16) and 
+              (V23.b'length = 16) and 
+              (V23.c'length = 16) and 
+              (V23.d'length = 16) and 
+              (V23.e'length = 16) and 
+              (V23.f'length = 16) and 
+              (V23.g'length = 16) and 
+              (V24.a'length = 16) and 
+              (V24.b'length = 16) and 
+              (V24.c'length = 16) and 
+              (V24.d'length = 16) and 
+              (V24.e'length = 16) and 
+              (V24.f'length = 16) and 
+              (V24.g'length = 16) and 
+              (V25'length = 16) and 
+              (V26'length = 16) and 
+              (V27'length = 16) and 
+              (V28'length = 16) and 
+              (V29'length = 16) and 
+              (V30'length = 16) and 
+              (V31'length = 16) and 
+              (V32.a'length = 16) and 
+              (V32.b'length = 16) and 
+              (V32.c'length = 16) and 
+              (V32.d'length = 16) and 
+              (V32.e'length = 16) and 
+              (V32.f'length = 16) and 
+              (V32.g'length = 16) and 
+              (V34.a'length = 16) and 
+              (V34.b'length = 16) and 
+              (V34.c'length = 16) and 
+              (V34.d'length = 16) and 
+              (V34.e'length = 16) and 
+              (V34.f'length = 16) and 
+              (V34.g'length = 16) and 
+              (V36'length = 8) and 
+              (V37'length = 16) and 
+              (V38'length = 4) and 
+              (V39'length = 4) and 
+--          (V40'length = 1) and 
+              (V41'length = 8) and 
+              (V42'length = 8) and 
+              (V43'length = 8) and 
+              (V44'length = 8) and 
+              (V45'length = 8) and 
+              (V46'length = 8) and 
+              (V48'length = 8) and 
+              (V48'length = 8) and 
+              (V49'length = 8) and 
+              (V50'length = 8) and 
+              (V51.a'length = 8) and 
+              (V51.b'length = 8) and 
+              (V51.c'length = 8) ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00756 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00756arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc757.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc757.vhd
new file mode 100644
index 0000000..eb76c0c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc757.vhd
@@ -0,0 +1,382 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc757.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p05n02i00757ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    C1 : boolean := true;
+    C2 : bit := '1';
+    C3 : character := 's';
+    C4 : severity_level := note;
+    C5 : integer := 3;
+    C6 : real := 3.0;
+    C7 : time := 3 ns;
+    C8 : natural := 1;
+    C9 : positive := 1;
+    C10 : string := "shishir";
+    C11 : bit_vector := B"0011"
+    );
+END c01s01b01x01p05n02i00757ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00757arch OF c01s01b01x01p05n02i00757ent IS
+  subtype hi_to_low_range is integer range zero to seven;
+
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  subtype boolean_vector_st is boolean_vector(zero to fifteen);
+  subtype severity_level_vector_st is  severity_level_vector(zero to fifteen);
+  subtype integer_vector_st is  integer_vector(zero to fifteen);
+  subtype real_vector_st is  real_vector(zero to fifteen);
+  subtype time_vector_st is  time_vector(zero to fifteen);
+  subtype natural_vector_st is  natural_vector(zero to fifteen);
+  subtype positive_vector_st is  positive_vector(zero to fifteen);
+
+  type boolean_cons_vector is array (fifteen downto zero) of boolean;
+  type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
+  type integer_cons_vector is array (fifteen downto zero) of integer;
+  type real_cons_vector is array (fifteen downto zero) of real;
+  type time_cons_vector is array (fifteen downto zero) of time;
+  type natural_cons_vector is array (fifteen downto zero) of natural;
+  type positive_cons_vector is array (fifteen downto zero) of positive;
+  
+  type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector ;
+  type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
+  type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
+  type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
+  type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector; 
+  subtype column is integer range one to two;
+  subtype row is integer range one to eight;
+  type s2boolean_cons_vector is array (row,column) of boolean;
+  type s2bit_cons_vector is array (row,column) of bit;
+  type s2char_cons_vector is array (row,column) of character;
+  type s2severity_level_cons_vector is array (row,column) of severity_level;
+  type s2integer_cons_vector is array (row,column) of integer;
+  type s2real_cons_vector is array (row,column) of real;
+  type s2time_cons_vector is array (row,column) of time;
+  type s2natural_cons_vector is array (row,column) of natural;
+  type s2positive_cons_vector is array (row,column) of positive;
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                               j:string(one to seven);
+                               k:bit_vector(zero to three);
+                             end record;
+
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+  
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+  type record_array_new is record
+                             a:boolean_vector(zero to fifteen);
+                             b:severity_level_vector(zero to fifteen);
+                             c:integer_vector(zero to fifteen);
+                             d:real_vector(zero to fifteen);
+                             e:time_vector(zero to fifteen);
+                             f:natural_vector(zero to fifteen);
+                             g:positive_vector(zero to fifteen);
+                           end record;
+  
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              i: record_array_st;
+                              j: record_array_new;
+                            end record;
+  subtype boolean_vector_range is boolean_vector(hi_to_low_range);
+  subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
+  subtype integer_vector_range is integer_vector(hi_to_low_range);
+  subtype real_vector_range is real_vector(hi_to_low_range);
+  subtype time_vector_range is time_vector(hi_to_low_range);
+  subtype natural_vector_range is natural_vector(hi_to_low_range);
+  subtype positive_vector_range is positive_vector(hi_to_low_range);
+  
+  type array_rec_std is array (integer range <>) of record_std_package;
+  type array_rec_cons is array (integer range <>) of record_cons_array;
+  type array_rec_2cons is array (integer range <>) of record_2cons_array;
+  type array_rec_rec is array (integer range <>) of record_of_records;
+  
+  subtype array_rec_std_st is array_rec_std (hi_to_low_range);
+  subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
+  subtype array_rec_2cons_st is  array_rec_2cons (hi_to_low_range);
+  subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
+  
+  type record_of_arr_of_record is record
+                                    a: array_rec_std(zero to seven);
+                                    b: array_rec_cons(zero to seven);
+                                    c: array_rec_2cons(zero to seven);
+                                    d: array_rec_rec(zero to seven);
+                                  end record;
+  
+  type four_value is ('Z','0','1','X');                                 --enumerated type
+  type four_value_vector is array (natural range <>) of four_value;
+  subtype four_value_vector_range is four_value_vector(hi_to_low_range);
+  
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  
+  type current_vector is array (natural range <>) of current;
+  subtype current_vector_range is current_vector(hi_to_low_range);
+  
+  
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  
+  type resistance_vector is array (natural range <>) of resistance;
+  subtype resistance_vector_range is resistance_vector(hi_to_low_range);
+--   function resolution14(i:in four_value_vector) return four_value;        --bus resolution
+--   subtype four_value_state is resolution14 four_value;                    --function type
+  type four_value_map is array(four_value) of boolean;
+  subtype binary is four_value range '0' to '1';
+  type byte is array(zero to seven) of bit;
+  subtype word is bit_vector(zero to fifteen);                                 --constrained array
+  constant size :integer := seven;
+  type primary_memory is array(zero to size) of word;                     --array of an array
+  type primary_memory_module is                                       --record with field
+    record                                                               --as an array
+      enable:binary;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;     --array of a complex record
+  subtype delay is integer range one to 10;
+  
+  
+  constant     C12 : boolean_vector := (C1,false);
+  constant     C13 : severity_level_vector := (C4,error);
+  constant     C14 : integer_vector := (one,two,three,four);
+  constant     C15 : real_vector := (1.0,2.0,C6,4.0);
+  constant     C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
+  constant     C17 : natural_vector := (one,2,3,4);
+  constant     C18 : positive_vector := (one,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+  
+BEGIN
+  assert (hi_to_low_range'left = 0) report "generic for left bound of hi_to_low_range not working" severity failure;
+  assert (hi_to_low_range'right = 7) report "generic for right bound of hi_to_low_range not working" severity failure;
+  assert (row'left = 1) report "generic constrained for left bound of row not working" severity failure;
+  assert (row'right = 8) report "generic constrained for right bound of row not working" severity failure;
+  assert (column'left = 1) report "generic constrained for left bound of column not working" severity failure;
+  assert (column'right = 2) report "generic constrained for right bound of column not working" severity failure;
+  assert (boolean_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (severity_level_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (integer_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (real_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (time_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (natural_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (positive_cons_vector'left = 15) report "generic constrained for left bound of array not working" severity failure;
+  assert (boolean_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (severity_level_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (integer_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (real_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (time_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (natural_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert (positive_cons_vector'right = 0) report "generic constrained for right bound of array not working" severity failure;
+  assert  (boolean_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (severity_level_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (integer_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (real_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (time_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (natural_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (positive_cons_vectorofvector'left = 0) report "generic constrained for left bound of array not working" severity failure;
+  assert  (boolean_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (severity_level_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (integer_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (real_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (time_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (natural_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+  assert  (positive_cons_vectorofvector'right = 15) report "generic constrained for right bound of array not working" severity failure;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert    NOT(    (hi_to_low_range'left = 0) and 
+                      (hi_to_low_range'right = 7) and 
+                      (row'left = 1) and 
+                      (row'right = 8) and 
+                      (column'left = 1) and 
+                      (column'right = 2) and 
+                      (boolean_cons_vector'left = 15) and 
+                      (severity_level_cons_vector'left = 15)   and 
+                      (integer_cons_vector'left = 15) and 
+                      (real_cons_vector'left = 15)    and 
+                      (time_cons_vector'left = 15)    and 
+                      (natural_cons_vector'left = 15) and 
+                      (positive_cons_vector'left = 15) and 
+                      (boolean_cons_vector'right = 0) and 
+                      (severity_level_cons_vector'right = 0)   and 
+                      (integer_cons_vector'right = 0) and 
+                      (real_cons_vector'right = 0)    and 
+                      (time_cons_vector'right = 0)    and 
+                      (natural_cons_vector'right = 0) and 
+                      (positive_cons_vector'right = 0) and 
+                      (boolean_cons_vectorofvector'left = 0) and 
+                      (severity_level_cons_vectorofvector'left = 0) and 
+                      (integer_cons_vectorofvector'left = 0) and 
+                      (real_cons_vectorofvector'left = 0)    and 
+                      (time_cons_vectorofvector'left = 0)    and 
+                      (natural_cons_vectorofvector'left = 0) and 
+                      (positive_cons_vectorofvector'left = 0) and 
+                      (boolean_cons_vectorofvector'right = 15) and 
+                      (severity_level_cons_vectorofvector'right = 15) and 
+                      (integer_cons_vectorofvector'right = 15) and 
+                      (real_cons_vectorofvector'right = 15)    and 
+                      (time_cons_vectorofvector'right = 15)    and 
+                      (natural_cons_vectorofvector'right = 15) and 
+                      (positive_cons_vectorofvector'right = 15)    ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00757"
+      severity NOTE;
+    assert    (    (hi_to_low_range'left = 0) and 
+                   (hi_to_low_range'right = 7) and 
+                   (row'left = 1) and 
+                   (row'right = 8) and 
+                   (column'left = 1) and 
+                   (column'right = 2) and 
+                   (boolean_cons_vector'left = 15) and 
+                   (severity_level_cons_vector'left = 15)   and 
+                   (integer_cons_vector'left = 15) and 
+                   (real_cons_vector'left = 15)    and 
+                   (time_cons_vector'left = 15)    and 
+                   (natural_cons_vector'left = 15) and 
+                   (positive_cons_vector'left = 15) and 
+                   (boolean_cons_vector'right = 0) and 
+                   (severity_level_cons_vector'right = 0)   and 
+                   (integer_cons_vector'right = 0) and 
+                   (real_cons_vector'right = 0)    and 
+                   (time_cons_vector'right = 0)    and 
+                   (natural_cons_vector'right = 0) and 
+                   (positive_cons_vector'right = 0) and 
+                   (boolean_cons_vectorofvector'left = 0) and 
+                   (severity_level_cons_vectorofvector'left = 0) and 
+                   (integer_cons_vectorofvector'left = 0) and 
+                   (real_cons_vectorofvector'left = 0)    and 
+                   (time_cons_vectorofvector'left = 0)    and 
+                   (natural_cons_vectorofvector'left = 0) and 
+                   (positive_cons_vectorofvector'left = 0) and 
+                   (boolean_cons_vectorofvector'right = 15) and 
+                   (severity_level_cons_vectorofvector'right = 15) and 
+                   (integer_cons_vectorofvector'right = 15) and 
+                   (real_cons_vectorofvector'right = 15)    and 
+                   (time_cons_vectorofvector'right = 15)    and 
+                   (natural_cons_vectorofvector'right = 15) and 
+                   (positive_cons_vectorofvector'right = 15)    ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00757 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00757arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc759.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc759.vhd
new file mode 100644
index 0000000..b693afb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc759.vhd
@@ -0,0 +1,184 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc759.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00759pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural  
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer; 
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  constant C1    : boolean := true; 
+  constant C2    : bit := '1';
+  constant C3    : character := 's';
+  constant C4    : severity_level := note; 
+  constant C5    : integer := 3;
+  constant C6    : real := 3.0;
+  constant C7    : time := 3 ns;
+  constant C8    : natural := 1;
+  constant C9    : positive := 1;
+  constant C10    : string := "shishir";
+  constant C11    : bit_vector := B"0011";
+  constant C12    : boolean_vector := (true,false); 
+  constant C13    : severity_level_vector := (note,error);
+  constant C14    : integer_vector := (1,2,3,4); 
+  constant C15    : real_vector := (1.0,2.0,3.0,4.0); 
+  constant C16    : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17    : natural_vector := (1,2,3,4);
+  constant C18    : positive_vector := (1,2,3,4);
+
+end c01s01b01x01p05n02i00759pkg;
+
+
+use   work.c01s01b01x01p05n02i00759pkg.ALL;
+ENTITY c01s01b01x01p05n02i00759ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   :integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen10    : string := "shishir";
+    Cgen11    : bit_vector := B"0011";
+    Cgen12    : boolean_vector := (true,false);
+    Cgen13    : severity_level_vector := (note,error);
+    Cgen14    : integer_vector := (1,2,3,4);
+    Cgen15    : real_vector := (1.0,2.0,3.0,4.0);
+    Cgen16    : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+    Cgen17    : natural_vector := (1,2,3,4);
+    Cgen18    : positive_vector := (1,2,3,4) );
+END c01s01b01x01p05n02i00759ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00759arch OF c01s01b01x01p05n02i00759ent IS
+  constant Vgen1       : boolean := true;
+  constant Vgen2       : bit := '1';
+  constant Vgen3       : character := 's';
+  constant Vgen4       : severity_level := note;
+  constant Vgen5       : integer := 3;
+  constant Vgen6       : real := 3.0;
+  constant Vgen7       : time := 3 ns;
+  constant Vgen8       : natural := 1;
+  constant Vgen9       : positive := 1;
+  constant Vgen10    : string (one to seven):= "shishir";
+  constant Vgen11    : bit_vector(zero to three) := B"0011";
+  constant Vgen12    : boolean_vector(zero to one) := (true,false);
+  constant Vgen13    : severity_level_vector(zero to one) := (note,error);
+  constant Vgen14    : integer_vector(zero to three) := (1,2,3,4);
+  constant Vgen15    : real_vector(zero to three) := (1.0,2.0,3.0,4.0);
+  constant Vgen16    : time_vector(zero to three) := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant Vgen17    : natural_vector(zero to three) := (1,2,3,4);
+  constant Vgen18    : positive_vector(zero to three) := (1,2,3,4);
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen10 = C10 report "Initializing signal with generic Vgen10 does not work" severity error;
+  assert Vgen11 = C11 report "Initializing signal with generic Vgen11 does not work" severity error;
+  assert Vgen12 = C12 report "Initializing signal with generic Vgen12 does not work" severity error;
+  assert Vgen13 = C13 report "Initializing signal with generic Vgen13 does not work" severity error;
+  assert Vgen14 = C14 report "Initializing signal with generic Vgen14 does not work" severity error;
+  assert Vgen15 = C15 report "Initializing signal with generic Vgen15 does not work" severity error;
+  assert Vgen16 = C16 report "Initializing signal with generic Vgen16 does not work" severity error;
+  assert Vgen17 = C17 report "Initializing signal with generic Vgen17 does not work" severity error;
+  assert Vgen18 = C18 report "Initializing signal with generic Vgen18 does not work" severity error;
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen10 = C10 and 
+                    Vgen11 = C11 and 
+                    Vgen12 = C12 and 
+                    Vgen13 = C13 and 
+                    Vgen14 = C14 and 
+                    Vgen15 = C15 and 
+                    Vgen16 = C16 and 
+                    Vgen17 = C17 and 
+                    Vgen18 = C18 ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00759"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen10 = C10 and 
+                   Vgen11 = C11 and 
+                   Vgen12 = C12 and 
+                   Vgen13 = C13 and 
+                   Vgen14 = C14 and 
+                   Vgen15 = C15 and 
+                   Vgen16 = C16 and 
+                   Vgen17 = C17 and 
+                   Vgen18 = C18 ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00759 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00759arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc76.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc76.vhd
new file mode 100644
index 0000000..d5dffd2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc76.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc76.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p10n04i00076ent IS
+END c04s03b01x02p10n04i00076ent;
+
+ARCHITECTURE c04s03b01x02p10n04i00076arch OF c04s03b01x02p10n04i00076ent IS
+  function F (constant S : BIT_VECTOR) return bit;
+  function F (constant S : BIT_VECTOR) return bit is
+    variable res_bit : bit := bit'('0');
+  begin
+    for I in S'LOW to S'HIGH loop
+      if S(I) = bit'('1') then
+        res_bit := bit'('1');
+        exit;
+      end if;
+    end loop;
+    return res_bit;
+  end;
+  signal X : F bit;       -- X is a resolved signal.
+  signal P,Q : bit := '1';
+BEGIN
+  TESTING: PROCESS(P)
+  BEGIN
+    X <= P;
+  END PROCESS TESTING;
+
+  TESTING1: PROCESS(Q)
+  BEGIN
+    X <= Q;      --NO_Failure Here
+  END PROCESS TESTING1;
+
+  TEST: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert NOT(X='1') 
+      report "***PASSED TEST: c04s03b01x02p10n04i00076" 
+      severity NOTE;
+    assert (X='1') 
+      report "***FAILED TEST:c04s03b01x02p10n04i00076 - A signal with multiple source should be a resolved signal."
+      severity ERROR;
+    wait;
+  END PROCESS TEST;
+
+END c04s03b01x02p10n04i00076arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc760.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc760.vhd
new file mode 100644
index 0000000..0665348
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc760.vhd
@@ -0,0 +1,185 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc760.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00760pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+  constant C1    : boolean    := true; 
+  constant C2    : bit       := '1';
+  constant C3    : character    := 's';
+  constant C4    : severity_level:= note; 
+  constant C5    : integer    := 3;
+  constant C6    : real       := 3.0;
+  constant C7    : time       := 3 ns;
+  constant C8    : natural    := 1;
+  constant C9    : positive    := 1;
+  constant C10    : string    := "shishir";
+  constant C11    : bit_vector    := B"0011";
+  constant C12    : boolean_vector:= (true,false); 
+  constant C13    : severity_level_vector    := (note,error);
+  constant C14    : integer_vector:= (1,2,3,4); 
+  constant C15    : real_vector    := (1.0,2.0,3.0,4.0); 
+  constant C16    : time_vector    := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17    : natural_vector:= (1,2,3,4);
+  constant C18    : positive_vector:= (1,2,3,4);
+
+end c01s01b01x01p05n02i00760pkg;
+
+use   work.c01s01b01x01p05n02i00760pkg.ALL;
+ENTITY c01s01b01x01p05n02i00760ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   :integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen10    : string := "shishir";
+    Cgen11    : bit_vector := B"0011";
+    Cgen12    : boolean_vector := (true,false);
+    Cgen13    : severity_level_vector := (note,error);
+    Cgen14    : integer_vector := (1,2,3,4);
+    Cgen15    : real_vector := (1.0,2.0,3.0,4.0);
+    Cgen16    : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+    Cgen17    : natural_vector := (1,2,3,4);
+    Cgen18    : positive_vector := (1,2,3,4) 
+    );
+END c01s01b01x01p05n02i00760ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00760arch OF c01s01b01x01p05n02i00760ent IS
+  signal Vgen1    : boolean    := true;
+  signal Vgen2    : bit       := '1';
+  signal Vgen3    : character    := 's';
+  signal Vgen4    : severity_level:= note;
+  signal Vgen5    : integer    := 3;
+  signal Vgen6    : real       := 3.0;
+  signal Vgen7    : time       := 3 ns;
+  signal Vgen8    : natural    := 1;
+  signal Vgen9    : positive    := 1;
+  signal Vgen10    : string (one to seven)      := "shishir";
+  signal Vgen11    : bit_vector(zero to three)    := B"0011";
+  signal Vgen12    : boolean_vector(zero to one)    := (true,false);
+  signal Vgen13    : severity_level_vector(zero to one)    := (note,error);
+  signal Vgen14    : integer_vector(zero to three) := (1,2,3,4);
+  signal Vgen15    : real_vector(zero to three)    := (1.0,2.0,3.0,4.0);
+  signal Vgen16    : time_vector(zero to three)    := (1 ns, 2 ns, 3 ns, 4 ns);
+  signal Vgen17    : natural_vector(zero to three) := (1,2,3,4);
+  signal Vgen18    : positive_vector(zero to three) := (1,2,3,4);
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen10 = C10 report "Initializing signal with generic Vgen10 does not work" severity error;
+  assert Vgen11 = C11 report "Initializing signal with generic Vgen11 does not work" severity error;
+  assert Vgen12 = C12 report "Initializing signal with generic Vgen12 does not work" severity error;
+  assert Vgen13 = C13 report "Initializing signal with generic Vgen13 does not work" severity error;
+  assert Vgen14 = C14 report "Initializing signal with generic Vgen14 does not work" severity error;
+  assert Vgen15 = C15 report "Initializing signal with generic Vgen15 does not work" severity error;
+  assert Vgen16 = C16 report "Initializing signal with generic Vgen16 does not work" severity error;
+  assert Vgen17 = C17 report "Initializing signal with generic Vgen17 does not work" severity error;
+  assert Vgen18 = C18 report "Initializing signal with generic Vgen18 does not work" severity error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen10 = C10 and 
+                    Vgen11 = C11 and 
+                    Vgen12 = C12 and 
+                    Vgen13 = C13 and 
+                    Vgen14 = C14 and 
+                    Vgen15 = C15 and 
+                    Vgen16 = C16 and 
+                    Vgen17 = C17 and 
+                    Vgen18 = C18 ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00760"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen10 = C10 and 
+                   Vgen11 = C11 and 
+                   Vgen12 = C12 and 
+                   Vgen13 = C13 and 
+                   Vgen14 = C14 and 
+                   Vgen15 = C15 and 
+                   Vgen16 = C16 and 
+                   Vgen17 = C17 and 
+                   Vgen18 = C18 )
+      report "***FAILED TEST: c01s01b01x01p05n02i00760 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00760arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc761.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc761.vhd
new file mode 100644
index 0000000..9871cd0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc761.vhd
@@ -0,0 +1,184 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc761.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00761pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural  
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer; 
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st       is  boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st       is  positive_vector(0 to 15);
+
+  constant C1    : boolean    := true; 
+  constant C2    : bit       := '1';
+  constant C3    : character    := 's';
+  constant C4    : severity_level:= note; 
+  constant C5    : integer    := 3;
+  constant C6    : real       := 3.0;
+  constant C7    : time       := 3 ns;
+  constant C8    : natural    := 1;
+  constant C9    : positive    := 1;
+  constant C70    : boolean_vector_st       :=(others => C1);
+  constant C71    : severity_level_vector_st   :=(others => C4);
+  constant C72    : integer_vector_st      :=(others => C5);
+  constant C73    : real_vector_st      :=(others => C6);
+  constant C74    : time_vector_st      :=(others => C7);
+  constant C75    : natural_vector_st      :=(others => C8);
+  constant C76    : positive_vector_st      :=(others => C9);
+
+end c01s01b01x01p05n02i00761pkg;
+
+use   work.c01s01b01x01p05n02i00761pkg.ALL;
+ENTITY c01s01b01x01p05n02i00761ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   : integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen70  : boolean_vector_st       :=(others => true);
+    Cgen71  : severity_level_vector_st   :=(others => note);
+    Cgen72  : integer_vector_st      :=(others => 3);
+    Cgen73  : real_vector_st      :=(others => 3.0);
+    Cgen74  : time_vector_st      :=(others => 3 ns);
+    Cgen75  : natural_vector_st      :=(others => 1);
+    Cgen76  : positive_vector_st      :=(others => 1)
+    );
+  port(
+    Vgen1    : boolean    := true;
+    Vgen2    : bit       := '1';
+    Vgen3    : character    := 's';
+    Vgen4    : severity_level:= note;
+    Vgen5    : integer    := 3;
+    Vgen6    : real       := 3.0;
+    Vgen7    : time       := 3 ns;
+    Vgen8    : natural    := 1;
+    Vgen9    : positive    := 1;
+    Vgen70  : boolean_vector_st       :=(others => true);
+    Vgen71  : severity_level_vector_st   :=(others => note);
+    Vgen72  : integer_vector_st      :=(others => 3);
+    Vgen73  : real_vector_st      :=(others => 3.0);
+    Vgen74  : time_vector_st      :=(others => 3 ns);
+    Vgen75  : natural_vector_st      :=(others => 1);
+    Vgen76  : positive_vector_st      :=(others => 1)
+    );
+END c01s01b01x01p05n02i00761ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00761arch OF c01s01b01x01p05n02i00761ent IS
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
+  assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
+  assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
+  assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
+  assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
+  assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
+  assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen70 = C70 and
+                    Vgen71 = C71 and
+                    Vgen72 = C72 and
+                    Vgen73 = C73 and
+                    Vgen74 = C74 and
+                    Vgen75 = C75 and
+                    Vgen76 = C76 )
+      report "***PASSED TEST: c01s01b01x01p05n02i00761"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen70 = C70 and
+                   Vgen71 = C71 and
+                   Vgen72 = C72 and
+                   Vgen73 = C73 and
+                   Vgen74 = C74 and
+                   Vgen75 = C75 and
+                   Vgen76 = C76 )
+      report "***FAILED TEST: c01s01b01x01p05n02i00761 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00761arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc762.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc762.vhd
new file mode 100644
index 0000000..3fd73b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc762.vhd
@@ -0,0 +1,183 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc762.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00762pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural  
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer; 
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st       is  boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st       is  positive_vector(0 to 15);
+
+  constant C1    : boolean := true; 
+  constant C2    : bit := '1';
+  constant C3    : character := 's';
+  constant C4    : severity_level := note; 
+  constant C5    : integer := 3;
+  constant C6    : real := 3.0;
+  constant C7    : time := 3 ns;
+  constant C8    : natural := 1;
+  constant C9    : positive := 1;
+  constant C70    : boolean_vector_st       :=(others => C1);
+  constant C71    : severity_level_vector_st   :=(others => C4);
+  constant C72    : integer_vector_st      :=(others => C5);
+  constant C73    : real_vector_st      :=(others => C6);
+  constant C74    : time_vector_st      :=(others => C7);
+  constant C75    : natural_vector_st      :=(others => C8);
+  constant C76    : positive_vector_st      :=(others => C9);
+
+end c01s01b01x01p05n02i00762pkg;
+
+
+use   work.c01s01b01x01p05n02i00762pkg.ALL;
+ENTITY c01s01b01x01p05n02i00762ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   :integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen70  : boolean_vector_st       :=(others => true);
+    Cgen71  : severity_level_vector_st   :=(others => note);
+    Cgen72  : integer_vector_st      :=(others => 3);
+    Cgen73  : real_vector_st      :=(others => 3.0);
+    Cgen74  : time_vector_st      :=(others => 3 ns);
+    Cgen75  : natural_vector_st      :=(others => 1);
+    Cgen76  : positive_vector_st      :=(others => 1)
+    );
+END c01s01b01x01p05n02i00762ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00762arch OF c01s01b01x01p05n02i00762ent IS
+  constant Vgen1       : boolean := true;
+  constant Vgen2       : bit := '1';
+  constant Vgen3       : character := 's';
+  constant Vgen4       : severity_level := note;
+  constant Vgen5       : integer := 3;
+  constant Vgen6       : real := 3.0;
+  constant Vgen7       : time := 3 ns;
+  constant Vgen8       : natural := 1;
+  constant Vgen9       : positive := 1;
+  constant Vgen70         : boolean_vector_st       :=(others => Cgen1);
+  constant Vgen71         : severity_level_vector_st   :=(others => Cgen4);
+  constant Vgen72         : integer_vector_st      :=(others => Cgen5);
+  constant Vgen73         : real_vector_st      :=(others => Cgen6);
+  constant Vgen74         : time_vector_st      :=(others => Cgen7);
+  constant Vgen75         : natural_vector_st      :=(others => Cgen8);
+  constant Vgen76         : positive_vector_st      :=(others => Cgen9);
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
+  assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
+  assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
+  assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
+  assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
+  assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
+  assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen70 = C70 and
+                    Vgen71 = C71 and
+                    Vgen72 = C72 and
+                    Vgen73 = C73 and
+                    Vgen74 = C74 and
+                    Vgen75 = C75 and
+                    Vgen76 = C76 )
+      report "***PASSED TEST: c01s01b01x01p05n02i00762"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen70 = C70 and
+                   Vgen71 = C71 and
+                   Vgen72 = C72 and
+                   Vgen73 = C73 and
+                   Vgen74 = C74 and
+                   Vgen75 = C75 and
+                   Vgen76 = C76 )
+      report "***FAILED TEST: c01s01b01x01p05n02i00762 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00762arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc763.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc763.vhd
new file mode 100644
index 0000000..20a45e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc763.vhd
@@ -0,0 +1,183 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc763.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00763pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_vector    is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector    is array (natural range <>) of integer;
+  type real_vector    is array (natural range <>) of real;
+  type time_vector    is array (natural range <>) of time;
+  type natural_vector    is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st       is  boolean_vector(0 to 15);
+  subtype severity_level_vector_st    is  severity_level_vector(0 to 15);
+  subtype integer_vector_st       is  integer_vector(0 to 15);
+  subtype real_vector_st       is  real_vector(0 to 15);
+  subtype time_vector_st       is  time_vector(0 to 15);
+  subtype natural_vector_st       is  natural_vector(0 to 15);
+  subtype positive_vector_st       is  positive_vector(0 to 15);
+
+  constant C1    : boolean    := true; 
+  constant C2    : bit       := '1';
+  constant C3    : character    := 's';
+  constant C4    : severity_level:= note; 
+  constant C5    : integer    := 3;
+  constant C6    : real       := 3.0;
+  constant C7    : time       := 3 ns;
+  constant C8    : natural    := 1;
+  constant C9    : positive    := 1;
+  constant C70    : boolean_vector_st       :=(others => C1);
+  constant C71    : severity_level_vector_st   :=(others => C4);
+  constant C72    : integer_vector_st      :=(others => C5);
+  constant C73    : real_vector_st      :=(others => C6);
+  constant C74    : time_vector_st      :=(others => C7);
+  constant C75    : natural_vector_st      :=(others => C8);
+  constant C76    : positive_vector_st      :=(others => C9);
+
+end c01s01b01x01p05n02i00763pkg;
+
+use   work.c01s01b01x01p05n02i00763pkg.ALL;
+ENTITY c01s01b01x01p05n02i00763ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   :integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen70  : boolean_vector_st       :=(others => true);
+    Cgen71  : severity_level_vector_st   :=(others => note);
+    Cgen72  : integer_vector_st      :=(others => 3);
+    Cgen73  : real_vector_st      :=(others => 3.0);
+    Cgen74  : time_vector_st      :=(others => 3 ns);
+    Cgen75  : natural_vector_st      :=(others => 1);
+    Cgen76  : positive_vector_st      :=(others => 1)
+    );
+END c01s01b01x01p05n02i00763ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00763arch OF c01s01b01x01p05n02i00763ent IS
+  signal Vgen1    : boolean    := true;
+  signal Vgen2    : bit       := '1';
+  signal Vgen3    : character    := 's';
+  signal Vgen4    : severity_level:= note;
+  signal Vgen5    : integer    := 3;
+  signal Vgen6    : real       := 3.0;
+  signal Vgen7    : time       := 3 ns;
+  signal Vgen8    : natural    := 1;
+  signal Vgen9    : positive    := 1;
+  signal Vgen70   : boolean_vector_st       :=(others => Cgen1);
+  signal Vgen71   : severity_level_vector_st   :=(others => Cgen4);
+  signal Vgen72   : integer_vector_st      :=(others => Cgen5);
+  signal Vgen73   : real_vector_st      :=(others => Cgen6);
+  signal Vgen74   : time_vector_st      :=(others => Cgen7);
+  signal Vgen75   : natural_vector_st      :=(others => Cgen8);
+  signal Vgen76   : positive_vector_st      :=(others => Cgen9);
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen70 = C70 report "Initializing signal with generic Vgen70 does not work" severity error;
+  assert Vgen71 = C71 report "Initializing signal with generic Vgen71 does not work" severity error;
+  assert Vgen72 = C72 report "Initializing signal with generic Vgen72 does not work" severity error;
+  assert Vgen73 = C73 report "Initializing signal with generic Vgen73 does not work" severity error;
+  assert Vgen74 = C74 report "Initializing signal with generic Vgen74 does not work" severity error;
+  assert Vgen75 = C75 report "Initializing signal with generic Vgen75 does not work" severity error;
+  assert Vgen76 = C76 report "Initializing signal with generic Vgen76 does not work" severity error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen70 = C70 and
+                    Vgen71 = C71 and
+                    Vgen72 = C72 and
+                    Vgen73 = C73 and
+                    Vgen74 = C74 and
+                    Vgen75 = C75 and
+                    Vgen76 = C76 )
+      report "***PASSED TEST: c01s01b01x01p05n02i00763"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen70 = C70 and
+                   Vgen71 = C71 and
+                   Vgen72 = C72 and
+                   Vgen73 = C73 and
+                   Vgen74 = C74 and
+                   Vgen75 = C75 and
+                   Vgen76 = C76 )
+      report "***FAILED TEST: c01s01b01x01p05n02i00763 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00763arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc765.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc765.vhd
new file mode 100644
index 0000000..fa3a0ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc765.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc765.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p06n01i00765ent_a IS
+  port ( c1 : in  integer ;
+         c2 : out integer );
+END c01s01b01x02p06n01i00765ent_a;
+
+ARCHITECTURE c01s01b01x02p06n01i00765arch_a OF c01s01b01x02p06n01i00765ent_a IS
+
+BEGIN
+  c2   <=    c1;
+END c01s01b01x02p06n01i00765arch_a;
+
+
+ENTITY c01s01b01x02p06n01i00765ent IS
+  port ( p1 : in  integer ;
+         p2 : out integer );
+END c01s01b01x02p06n01i00765ent;
+
+ARCHITECTURE c01s01b01x02p06n01i00765arch OF c01s01b01x02p06n01i00765ent IS
+  component c01s01b01x02p06n01i00765ent_b
+    port (    c1 : in  integer ;
+              c2 : out integer );
+  end component;
+  for L : c01s01b01x02p06n01i00765ent_b use entity work.c01s01b01x02p06n01i00765ent_a(c01s01b01x02p06n01i00765arch_a);
+BEGIN
+  L: c01s01b01x02p06n01i00765ent_b
+    port map (p1, p2);    -- Success_here
+  -- The formal c1 is of mode in and
+  -- The corresponding actual p1 is of
+  -- mode in which is legal.
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s01b01x02p06n01i00765"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p06n01i00765arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc768.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc768.vhd
new file mode 100644
index 0000000..ad26eb2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc768.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc768.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p07n01i00768ent_a IS
+  port ( c1 : in    integer ;
+         c2 : out    integer );
+END c01s01b01x02p07n01i00768ent_a;
+
+ARCHITECTURE c01s01b01x02p07n01i00768arch_a OF c01s01b01x02p07n01i00768ent_a IS
+
+BEGIN
+  c2 <= c1;
+END c01s01b01x02p07n01i00768arch_a;
+
+
+
+ENTITY c01s01b01x02p07n01i00768ent IS
+  port ( p1 : in    integer ;
+         p2 : out    integer );
+END c01s01b01x02p07n01i00768ent;
+
+ARCHITECTURE c01s01b01x02p07n01i00768arch OF c01s01b01x02p07n01i00768ent IS
+  component c01s01b01x02p07n01i00768ent_b
+    port ( c1 : in integer ;
+           c2 : out integer );
+  end component;
+  for L : c01s01b01x02p07n01i00768ent_b use entity work.c01s01b01x02p07n01i00768ent_a(c01s01b01x02p07n01i00768arch_a);
+BEGIN
+  L : c01s01b01x02p07n01i00768ent_b port map (p1, p2);
+  -- Success_here
+    -- The formal c2 is of mode out .
+      -- The corresponding actual p2 is of
+        -- mode out which is legal
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p07n01i00768"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p07n01i00768arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc772.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc772.vhd
new file mode 100644
index 0000000..81b3350
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc772.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc772.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p08n01i00772ent_a IS
+  port ( C1 : inout    Bit ;
+         C2 : out    Bit );
+END c01s01b01x02p08n01i00772ent_a;
+
+ARCHITECTURE c01s01b01x02p08n01i00772arch_a OF c01s01b01x02p08n01i00772ent_a IS
+
+BEGIN
+  c2 <= c1;
+END c01s01b01x02p08n01i00772arch_a;
+
+
+
+ENTITY c01s01b01x02p08n01i00772ent IS
+  port ( P1 : inout    Bit ;
+         P2 : out    Bit );
+END c01s01b01x02p08n01i00772ent;
+
+ARCHITECTURE c01s01b01x02p08n01i00772arch OF c01s01b01x02p08n01i00772ent IS
+  component c01s01b01x02p08n01i00772ent_b
+    port ( C1 : inout    Bit ;
+           C2 : out    Bit );
+  end component ;
+  for L : c01s01b01x02p08n01i00772ent_b use entity work.c01s01b01x02p08n01i00772ent_a(c01s01b01x02p08n01i00772arch_a);
+BEGIN
+  L : c01s01b01x02p08n01i00772ent_b port map (p1, p2);
+  --Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p08n01i00772" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p08n01i00772arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc776.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc776.vhd
new file mode 100644
index 0000000..ff0c49f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc776.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc776.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p09n01i00776ent_a IS
+  port ( C1 : inout    Bit ;
+         C2 : buffer    Bit );
+END c01s01b01x02p09n01i00776ent_a;
+
+ARCHITECTURE c01s01b01x02p09n01i00776arch_a OF c01s01b01x02p09n01i00776ent_a IS
+
+BEGIN
+  c1 <= c2;
+END c01s01b01x02p09n01i00776arch_a;
+
+
+ENTITY c01s01b01x02p09n01i00776ent IS
+  port ( p1 : inout    Bit ;
+         p2 : buffer    Bit );
+END c01s01b01x02p09n01i00776ent;
+
+ARCHITECTURE c01s01b01x02p09n01i00776arch OF c01s01b01x02p09n01i00776ent IS
+  component c01s01b01x02p09n01i00776ent_b
+    port (    C1 : inout    Bit ;
+              C2 : buffer    Bit );
+  end component;
+  for L : c01s01b01x02p09n01i00776ent_b use entity work.c01s01b01x02p09n01i00776ent_a(c01s01b01x02p09n01i00776arch_a);
+BEGIN
+  L : c01s01b01x02p09n01i00776ent_b port map (p1, p2);
+  --Success here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p09n01i00776" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p09n01i00776arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc777.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc777.vhd
new file mode 100644
index 0000000..5841fcc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc777.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc777.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p10n01i00777ent_a IS
+  port      (A : linkage integer;
+             B : linkage integer;
+             C : linkage integer;
+             D : linkage integer);
+END c01s01b01x02p10n01i00777ent_a;
+
+ARCHITECTURE c01s01b01x02p10n01i00777arch_a OF c01s01b01x02p10n01i00777ent_a IS
+
+BEGIN
+  test : process
+  begin
+    wait;
+  end process test;
+END c01s01b01x02p10n01i00777arch_a;
+
+
+
+ENTITY c01s01b01x02p10n01i00777ent IS
+  port (X : linkage    integer;
+        Y : buffer    integer;
+        Z : inout    integer);
+END c01s01b01x02p10n01i00777ent;
+
+ARCHITECTURE c01s01b01x02p10n01i00777arch OF c01s01b01x02p10n01i00777ent IS
+  component c01s01b01x02p10n01i00777ent_b
+    port      (A : linkage integer;
+               B : linkage integer;
+               C : linkage integer;
+               D : linkage integer);
+  end component;
+  for L : c01s01b01x02p10n01i00777ent_b use entity work.c01s01b01x02p10n01i00777ent_a(c01s01b01x02p10n01i00777arch_a);
+
+  signal M : integer;
+
+BEGIN
+  L:c01s01b01x02p10n01i00777ent_b port map 
+    ( A => M,
+      B => X,
+      C => Y,
+      D => Z);
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p10n01i00777"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p10n01i00777arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc778.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc778.vhd
new file mode 100644
index 0000000..8891fa4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc778.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc778.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p10n01i00778ent_a IS
+  port (  c1 : linkage integer;
+          c2 : linkage integer;
+          c3 : linkage integer;
+          c4 : linkage integer;
+          c5 : linkage integer);
+END c01s01b01x02p10n01i00778ent_a;
+
+ARCHITECTURE c01s01b01x02p10n01i00778arch_a OF c01s01b01x02p10n01i00778ent_a IS
+
+BEGIN
+  test : process
+  begin
+    wait;
+  end process test;
+END c01s01b01x02p10n01i00778arch_a;
+
+
+
+ENTITY c01s01b01x02p10n01i00778ent IS
+  port (p1 : in      integer;
+        p2 : out     integer;
+        p3 : inout   integer;
+        p4 : buffer  integer;
+        p5 : linkage integer);
+END c01s01b01x02p10n01i00778ent;
+
+ARCHITECTURE c01s01b01x02p10n01i00778arch OF c01s01b01x02p10n01i00778ent IS
+  component c01s01b01x02p10n01i00778ent_b
+    port (  c1 : linkage integer;
+            c2 : linkage integer;
+            c3 : linkage integer;
+            c4 : linkage integer;
+            c5 : linkage integer);
+  end component;
+  for L : c01s01b01x02p10n01i00778ent_b use entity work.c01s01b01x02p10n01i00778ent_a(c01s01b01x02p10n01i00778arch_a);
+BEGIN
+  L: c01s01b01x02p10n01i00778ent_b port map (p1, p2, p3, p4, p5); -- Expect_Success
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p10n01i00778"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p10n01i00778arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc782.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc782.vhd
new file mode 100644
index 0000000..6e13a5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc782.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc782.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p12n04i00782ent_a IS
+  port (
+    C2 : inout      Bit;
+    C3 : linkage    Bit;
+    C4 : out        Bit;
+    C5 : Buffer     Bit
+    );
+END c01s01b01x02p12n04i00782ent_a;
+
+ARCHITECTURE c01s01b01x02p12n04i00782arch_a OF c01s01b01x02p12n04i00782ent_a IS
+BEGIN
+END c01s01b01x02p12n04i00782arch_a;
+
+
+
+ENTITY c01s01b01x02p12n04i00782ent IS
+  port (
+    A2 : inout      Bit;
+    A3 : linkage    Bit;
+    A4 : out        Bit;
+    A5 : Buffer     Bit
+    ) ;
+END c01s01b01x02p12n04i00782ent;
+
+ARCHITECTURE c01s01b01x02p12n04i00782arch OF c01s01b01x02p12n04i00782ent IS
+  component c01s01b01x02p12n04i00782ent_b
+    port (
+      C2 : inout      Bit;
+      C3 : linkage    Bit;
+      C4 : out        Bit;
+      C5 : Buffer     Bit
+      );
+  end component;
+  for L : c01s01b01x02p12n04i00782ent_b use entity work.c01s01b01x02p12n04i00782ent_a(c01s01b01x02p12n04i00782arch_a);
+BEGIN
+  L : c01s01b01x02p12n04i00782ent_b port map ( C2 => open, C3 => open, C4 => open, C5 => open );
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p12n04i00782"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p12n04i00782arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc784.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc784.vhd
new file mode 100644
index 0000000..a5ea38c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc784.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc784.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p12n04i00784ent_a IS
+  port (   C1 : in      bit_vector;
+           C2 : out     bit_vector;
+           C3 : inout   bit_vector;
+           C4 : buffer  bit_vector;
+           C5 : linkage bit_vector);
+END c01s01b01x02p12n04i00784ent_a;
+
+ARCHITECTURE c01s01b01x02p12n04i00784arch_a OF c01s01b01x02p12n04i00784ent_a IS
+BEGIN
+END c01s01b01x02p12n04i00784arch_a;
+
+
+
+ENTITY c01s01b01x02p12n04i00784ent IS
+  port (   P1 : in     bit_vector(15 downto 0);
+           P2 : out     bit_vector(15 downto 0);
+           P3 : inout     bit_vector(15 downto 0);
+           P4 : buffer     bit_vector(15 downto 0);
+           P5 : linkage     bit_vector(15 downto 0));
+END c01s01b01x02p12n04i00784ent;
+
+ARCHITECTURE c01s01b01x02p12n04i00784arch OF c01s01b01x02p12n04i00784ent IS
+  component c01s01b01x02p12n04i00784ent_b
+    port (   C1 : in      bit_vector;
+             C2 : out     bit_vector;
+             C3 : inout   bit_vector;
+             C4 : buffer  bit_vector;
+             C5 : linkage bit_vector);
+  end component;
+  for L : c01s01b01x02p12n04i00784ent_b use entity work.c01s01b01x02p12n04i00784ent_a(c01s01b01x02p12n04i00784arch_a);
+BEGIN
+  L : c01s01b01x02p12n04i00784ent_b 
+    port map (C1 => p1, C2 => p2, C3 => p3, C4 => p4, C5 => p5);
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s01b01x02p12n04i00784" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p12n04i00784arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc791.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc791.vhd
new file mode 100644
index 0000000..102cc10
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc791.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc791.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b02x00p03n01i00791ent_1 IS
+END  ;
+
+-- legal. with entity_simple_name
+ENTITY c01s01b02x00p03n01i00791ent_2 IS
+END c01s01b02x00p03n01i00791ent_2 ;
+
+-- legal. begin with no statements following
+ENTITY c01s01b02x00p03n01i00791ent_3 IS
+begin
+END c01s01b02x00p03n01i00791ent_3;
+
+-- legal. no space before semicolon
+ENTITY c01s01b02x00p03n01i00791ent_4 IS
+END c01s01b02x00p03n01i00791ent_4;
+
+-- legal. NEW line before semicolon
+ENTITY c01s01b02x00p03n01i00791ent_5 IS
+END c01s01b02x00p03n01i00791ent_5
+  ;
+
+--------------------------------
+ENTITY c01s01b02x00p03n01i00791ent IS
+END c01s01b02x00p03n01i00791ent;
+
+ARCHITECTURE c01s01b02x00p03n01i00791arch OF c01s01b02x00p03n01i00791ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s01b02x00p03n01i00791" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b02x00p03n01i00791arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc792.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc792.vhd
new file mode 100644
index 0000000..170d0a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc792.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc792.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b02x00p03n01i00792pkg is
+  constant k : integer := 5;
+  function wired_and (sig : bit_vector) return bit;
+end c01s01b02x00p03n01i00792pkg;
+
+package body c01s01b02x00p03n01i00792pkg is
+  function wired_and (sig : bit_vector) return bit is
+  begin
+    return '0';
+  end wired_and;
+end c01s01b02x00p03n01i00792pkg;
+
+
+ENTITY c01s01b02x00p03n01i00792ent_1 IS
+  GENERIC (CONSTANT a : bit);
+  ALIAS alias_identifier : bit IS a ;
+END    c01s01b02x00p03n01i00792ent_1 ;
+
+ENTITY c01s01b02x00p03n01i00792ent_2 IS
+  GENERIC (CONSTANT a : bit);
+  ATTRIBUTE my_name : integer;
+END    c01s01b02x00p03n01i00792ent_2 ;
+
+ENTITY c01s01b02x00p03n01i00792ent_4 IS
+  GENERIC (CONSTANT a : bit);
+  USE work.c01s01b02x00p03n01i00792pkg.ALL;
+END    c01s01b02x00p03n01i00792ent_4 ;
+
+use work.c01s01b02x00p03n01i00792pkg.all;
+ENTITY c01s01b02x00p03n01i00792ent_5 IS
+  port (signal a : in wired_and bit bus);
+  DISCONNECT a:bit AFTER 100 ns;
+END    c01s01b02x00p03n01i00792ent_5 ;
+
+--------------------------------
+ENTITY c01s01b02x00p03n01i00792ent IS
+END c01s01b02x00p03n01i00792ent;
+
+ARCHITECTURE c01s01b02x00p03n01i00792arch OF c01s01b02x00p03n01i00792ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s01b02x00p03n01i00792" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b02x00p03n01i00792arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc80.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc80.vhd
new file mode 100644
index 0000000..ce3c006
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc80.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc80.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p12n01i00080ent IS
+END c04s03b01x02p12n01i00080ent;
+
+ARCHITECTURE c04s03b01x02p12n01i00080arch OF c04s03b01x02p12n01i00080ent IS
+  type arrbit    is array (1 to 3) of bit;
+  type comp_vect    is array (positive range <>) of arrbit;
+  
+  function F(BB: comp_vect) return arrbit is
+  begin
+    return "111";
+  end;
+  
+  signal X : F arrbit ;
+  signal P : bit := '1';
+  signal Q : bit := '1';
+  signal R : bit := '1';
+BEGIN
+  TESTING: PROCESS(P,Q,R)
+  BEGIN
+    X(1) <= P;   -- No_failure_here
+    X(2) <= Q;   -- No_failure_here
+    X(3) <= R;   -- No_failure_here
+    assert NOT(X="111") 
+      report "***PASSED TEST: c04s03b01x02p12n01i00080"
+      severity NOTE;
+    assert (X="111") 
+      report "***FAILED TEST:c04s03b01x02p12n01i00080 - All of the subelements of the signal should have a driver in a process."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c04s03b01x02p12n01i00080arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc805.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc805.vhd
new file mode 100644
index 0000000..5755b1c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc805.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc805.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00805ent IS
+  port (CLK: in bit);
+begin
+  assert FALSE
+    report "The test of concurrent assertion statement in entity statement passed when you see this asssertion note."
+    severity note;
+  process
+  begin
+    wait;
+  end process;
+END c01s01b03x00p03n01i00805ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00805arch OF c01s01b03x00p03n01i00805ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s01b03x00p03n01i00805 - This test needs manual check to make sure that assertion notice appear."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00805arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc81.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc81.vhd
new file mode 100644
index 0000000..72e2e0f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc81.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc81.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p13n01i00081ent IS
+END c04s03b01x02p13n01i00081ent;
+
+ARCHITECTURE c04s03b01x02p13n01i00081arch OF c04s03b01x02p13n01i00081ent IS
+  signal S1 : Integer := 1;
+BEGIN
+  TESTING: PROCESS
+    variable T1 : TIME:= NOW;
+  BEGIN
+    assert NOT( S1 = 1 and T1 = NOW )
+      report "***PASSED TEST: c04s03b01x02p13n01i00081"
+      severity NOTE;
+    assert ( S1 = 1 and T1 = NOW )
+      report "***FAILED TEST:c04s03b01x02p13n01i00081 - Default value of the scalar signal is assumed at the start of the simulation."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p13n01i00081arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc817.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc817.vhd
new file mode 100644
index 0000000..fe41dac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc817.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc817.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b01x00p03n01i00817ent_a IS
+  port (A    : IN BIT);
+END c01s02b01x00p03n01i00817ent_a;
+
+ARCHITECTURE c01s02b01x00p03n01i00817arch_a OF c01s02b01x00p03n01i00817ent_a IS
+
+BEGIN
+  TEST : PROCESS
+  BEGIN
+    if A = '1' then 
+      null;
+    end if;
+    wait;
+  END PROCESS TEST;
+
+END c01s02b01x00p03n01i00817arch_a;
+
+
+package c01s02b01x00p03n01i00817pkg is
+  type BIT is ('0', '1');
+end c01s02b01x00p03n01i00817pkg;
+
+ENTITY c01s02b01x00p03n01i00817ent IS
+  port (A    : BIT;
+        B    : out BIT;
+        C, D    : Boolean) ;
+END c01s02b01x00p03n01i00817ent;
+
+ARCHITECTURE c01s02b01x00p03n01i00817arch OF c01s02b01x00p03n01i00817ent IS
+  
+  procedure P1 is
+  begin
+    return;
+  end P1;
+  
+  function F1 return BIT is
+  begin
+    return '0';
+  end F1;
+  
+  type    Q  is range 10.5 to 11.5;
+  subtype    R  is REAL;
+  constant    C1 : REAL := 1.39;
+  signal    S  : BIT;
+  component E2
+    port (A : in BIT);
+  end component;
+  for TEST : E2 use entity work.c01s02b01x00p03n01i00817ent_a(c01s02b01x00p03n01i00817arch_a);
+  use WORK.c01s02b01x00p03n01i00817pkg.all;
+
+BEGIN
+  TEST : E2 port map (S);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s02b01x00p03n01i00817"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b01x00p03n01i00817arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc82.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc82.vhd
new file mode 100644
index 0000000..1a997e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc82.vhd
@@ -0,0 +1,576 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc82.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p01n01i00082ent IS
+END c04s03b01x03p01n01i00082ent;
+
+ARCHITECTURE c04s03b01x03p01n01i00082arch OF c04s03b01x03p01n01i00082ent IS
+--
+--
+--          Declaration of composite types
+--           - array types and subtypes
+--
+  TYPE    ut_chary    IS ARRAY (CHARACTER RANGE <>) OF INTEGER;      -- unconstrained array type    
+  TYPE    ct_word     IS ARRAY (0 TO 15)            OF BIT;          -- constrained array type
+
+  SUBTYPE ust_subchary IS ut_chary;                                  -- unconstrained array subtype
+  SUBTYPE cst_str10    IS STRING    ( 1  TO 10 );                    -- constrained array subtype
+  SUBTYPE cst_digit    IS ut_chary  ('0' TO '9');                    -- constrained array subtype
+--
+--          Declaration of composite types
+--           - records types and subtypes
+--
+  TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+  TYPE rt_date IS
+    RECORD
+      day   : INTEGER RANGE 0 TO 31;
+      month : month_name;
+      year  : INTEGER RANGE 0 TO 4000;
+    END RECORD;
+--
+  SUBTYPE rst_date IS rt_date;
+  
+BEGIN
+  TESTING: PROCESS
+--
+--          VARIABLE declarations
+--
+    
+    VARIABLE     STRING_con_0 :     STRING (1 TO 7);
+    VARIABLE     STRING_con_1 :     STRING (1 TO 7) := "sailing";
+    VARIABLE     STRING_con_2 :     STRING (1 TO 7) := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
+    
+    VARIABLE BIT_VECTOR_con_0 : BIT_VECTOR (0 TO 7);
+    VARIABLE BIT_VECTOR_con_1 : BIT_VECTOR (0 TO 7) := B"10101110";
+    VARIABLE BIT_VECTOR_con_2 : BIT_VECTOR (0 TO 7) := ( '1', '0', '1', '0', '1', '1', '1', '0');
+    
+    VARIABLE   ut_chary_con_0 :   ut_chary (NUL TO ENQ);
+    VARIABLE   ut_chary_con_1 :   ut_chary (NUL TO ENQ) := ( 1, 2, 3, 9, 8, 7);
+    
+    VARIABLE    ct_word_con_0 :    ct_word;
+    VARIABLE    ct_word_con_1 :    ct_word := ( '1', '1', '1', '1', '1', '1', '1', '1',
+                                                '1', '1', '1', '1', '1', '1', '1', '1');
+    
+    VARIABLE  cst_str10_con_0 :  cst_str10;
+    VARIABLE  cst_str10_con_1 :  cst_str10 := "abcdefghij";
+    VARIABLE  cst_str10_con_2 :  cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j'); 
+    VARIABLE  cst_digit_con_0 :  cst_digit;
+    VARIABLE  cst_digit_con_1 :  cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
+    
+    VARIABLE    rt_date_con_0 :    rt_date;
+    VARIABLE    rt_date_con_1 :    rt_date := (1, Jan, 1989);
+    
+    VARIABLE   rst_date_con_0 :   rst_date;
+    VARIABLE   rst_date_con_1 :   rst_date := (1, Apr, 2000);
+    
+----------------------------------------------------------------------------------------------------------
+  BEGIN
+    ASSERT STRING_con_0(1) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(2) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(3) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(4) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(5) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(6) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_0(7) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT BIT_VECTOR_con_0(0) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(1) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(2) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(3) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(4) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(5) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(6) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_0(7) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
+
+    ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ut_chary_con_0(NUL) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(SOH) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(STX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(ETX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(EOT) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_0(ENQ) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ut_chary_con_1(NUL) = 1 REPORT "ut_chary_con_1('a') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(SOH) = 2 REPORT "ut_chary_con_1('b') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(STX) = 3 REPORT "ut_chary_con_1('c') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(ETX) = 9 REPORT "ut_chary_con_1('d') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(EOT) = 8 REPORT "ut_chary_con_1('e') not properly intialized" SEVERITY FAILURE;
+    ASSERT ut_chary_con_1(ENQ) = 7 REPORT "ut_chary_con_1('f') not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ct_word_con_0(0) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(1) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(2) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(3) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(4) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(5) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(6) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(7) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(8) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(9) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(10) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(11) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(12) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(13) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(14) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_0(15) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT ct_word_con_1(0) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(1) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(2) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(3) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(4) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(5) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(6) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(7) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(8) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(9) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(10) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(11) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(12) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(13) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(14) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    ASSERT ct_word_con_1(15) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_str10_con_0(1) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(2) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(3) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(4) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(5) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(6) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(7) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(8) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(9) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_0(10) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
+
+    ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
+
+    ASSERT cst_digit_con_0('0') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('1') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('2') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('3') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('4') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('5') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('6') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('7') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('8') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_0('9') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT cst_digit_con_1('0') = 0 REPORT "cst_digit_con_1('0') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('1') = 1 REPORT "cst_digit_con_1('1') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('2') = 2 REPORT "cst_digit_con_1('2') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('3') = 3 REPORT "cst_digit_con_1('3') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('4') = 4 REPORT "cst_digit_con_1('4') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('5') = 5 REPORT "cst_digit_con_1('5') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('6') = 6 REPORT "cst_digit_con_1('6') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('7') = 7 REPORT "cst_digit_con_1('7') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('8') = 8 REPORT "cst_digit_con_1('8') not properly intialized" SEVERITY FAILURE;
+    ASSERT cst_digit_con_1('9') = 9 REPORT "cst_digit_con_1('9') not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT  rt_date_con_0.day   = 0    REPORT " rt_date_con_0.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_0.month = Jan  REPORT " rt_date_con_0.month not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_0.year  = 0    REPORT " rt_date_con_0.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT  rt_date_con_1.day   = 1    REPORT " rt_date_con_1.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_1.month = Jan  REPORT " rt_date_con_1.month not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_con_1.year  = 1989 REPORT " rt_date_con_1.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_con_0.day   = 0    REPORT "rst_date_con_0.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_0.month = Jan  REPORT "rst_date_con_0.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_0.year  = 0    REPORT "rst_date_con_0.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_con_1.day   = 1    REPORT "rst_date_con_1.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_1.month = Apr  REPORT "rst_date_con_1.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_con_1.year  = 2000 REPORT "rst_date_con_1.year  not properly intialized" SEVERITY FAILURE;
+
+--------------------------------------------------------------------------------------------------------------
+
+    assert NOT(    STRING_con_0(1) = NUL      and 
+                   STRING_con_0(2) = NUL       and
+                   STRING_con_0(3) = NUL       and
+                   STRING_con_0(4) = NUL       and
+                   STRING_con_0(5) = NUL       and
+                   STRING_con_0(6) = NUL       and
+                   STRING_con_0(7) = NUL       and
+                   STRING_con_1(1) = 's'       and
+                   STRING_con_1(2) = 'a'       and
+                   STRING_con_1(3) = 'i'       and
+                   STRING_con_1(4) = 'l'       and
+                   STRING_con_1(5) = 'i'       and
+                   STRING_con_1(6) = 'n'       and
+                   STRING_con_1(7) = 'g'       and
+                   STRING_con_2(1) = 's'       and
+                   STRING_con_2(2) = 'a'       and
+                   STRING_con_2(3) = 'i'       and
+                   STRING_con_2(4) = 'l'       and
+                   STRING_con_2(5) = 'i'       and
+                   STRING_con_2(6) = 'n'       and
+                   STRING_con_2(7) = 'g'       and
+                   BIT_VECTOR_con_0(0) = '0'    and
+                   BIT_VECTOR_con_0(1) = '0'    and
+                   BIT_VECTOR_con_0(2) = '0'    and
+                   BIT_VECTOR_con_0(3) = '0'    and
+                   BIT_VECTOR_con_0(4) = '0'    and
+                   BIT_VECTOR_con_0(5) = '0'    and
+                   BIT_VECTOR_con_0(6) = '0'    and
+                   BIT_VECTOR_con_0(7) = '0'    and
+                   BIT_VECTOR_con_1(0) = '1'    and
+                   BIT_VECTOR_con_1(1) = '0'    and
+                   BIT_VECTOR_con_1(2) = '1'    and
+                   BIT_VECTOR_con_1(3) = '0'    and
+                   BIT_VECTOR_con_1(4) = '1'    and
+                   BIT_VECTOR_con_1(5) = '1'    and
+                   BIT_VECTOR_con_1(6) = '1'    and
+                   BIT_VECTOR_con_1(7) = '0'    and
+                   BIT_VECTOR_con_2(0) = '1'    and
+                   BIT_VECTOR_con_2(1) = '0'    and
+                   BIT_VECTOR_con_2(2) = '1'    and
+                   BIT_VECTOR_con_2(3) = '0'    and
+                   BIT_VECTOR_con_2(4) = '1'    and
+                   BIT_VECTOR_con_2(5) = '1'    and
+                   BIT_VECTOR_con_2(6) = '1'    and
+                   BIT_VECTOR_con_2(7) = '0'    and
+                   ut_chary_con_0(NUL) = INTEGER'LEFT    and
+                   ut_chary_con_0(SOH) = INTEGER'LEFT    and
+                   ut_chary_con_0(STX) = INTEGER'LEFT    and
+                   ut_chary_con_0(ETX) = INTEGER'LEFT    and
+                   ut_chary_con_0(EOT) = INTEGER'LEFT    and
+                   ut_chary_con_0(ENQ) = INTEGER'LEFT    and
+                   ut_chary_con_1(NUL) = 1    and
+                   ut_chary_con_1(SOH) = 2    and
+                   ut_chary_con_1(STX) = 3    and
+                   ut_chary_con_1(ETX) = 9    and
+                   ut_chary_con_1(EOT) = 8    and
+                   ut_chary_con_1(ENQ) = 7    and
+                   ct_word_con_0(0) = '0'       and
+                   ct_word_con_0(1) = '0'       and
+                   ct_word_con_0(2) = '0'       and
+                   ct_word_con_0(3) = '0'       and
+                   ct_word_con_0(4) = '0'       and
+                   ct_word_con_0(5) = '0'       and
+                   ct_word_con_0(6) = '0'       and
+                   ct_word_con_0(7) = '0'       and
+                   ct_word_con_0(8) = '0'       and
+                   ct_word_con_0(9) = '0'       and
+                   ct_word_con_0(10) = '0'    and
+                   ct_word_con_0(11) = '0'    and
+                   ct_word_con_0(12) = '0'    and
+                   ct_word_con_0(13) = '0'    and
+                   ct_word_con_0(14) = '0'    and
+                   ct_word_con_0(15) = '0'    and
+                   ct_word_con_1(0) = '1'       and
+                   ct_word_con_1(1) = '1'       and
+                   ct_word_con_1(2) = '1'       and
+                   ct_word_con_1(3) = '1'       and
+                   ct_word_con_1(4) = '1'       and
+                   ct_word_con_1(5) = '1'       and
+                   ct_word_con_1(6) = '1'       and
+                   ct_word_con_1(7) = '1'       and
+                   ct_word_con_1(8) = '1'       and
+                   ct_word_con_1(9) = '1'       and
+                   ct_word_con_1(10) = '1'    and
+                   ct_word_con_1(11) = '1'    and
+                   ct_word_con_1(12) = '1'    and
+                   ct_word_con_1(13) = '1'    and
+                   ct_word_con_1(14) = '1'    and
+                   ct_word_con_1(15) = '1'    and
+                   cst_str10_con_0(1) = NUL    and
+                   cst_str10_con_0(2) = NUL    and
+                   cst_str10_con_0(3) = NUL    and
+                   cst_str10_con_0(4) = NUL    and
+                   cst_str10_con_0(5) = NUL    and
+                   cst_str10_con_0(6) = NUL    and
+                   cst_str10_con_0(7) = NUL    and
+                   cst_str10_con_0(8) = NUL    and
+                   cst_str10_con_0(9) = NUL    and
+                   cst_str10_con_0(10) = NUL    and
+                   cst_str10_con_1(1) = 'a'    and
+                   cst_str10_con_1(2) = 'b'    and
+                   cst_str10_con_1(3) = 'c'    and
+                   cst_str10_con_1(4) = 'd'    and
+                   cst_str10_con_1(5) = 'e'    and
+                   cst_str10_con_1(6) = 'f'    and
+                   cst_str10_con_1(7) = 'g'    and
+                   cst_str10_con_1(8) = 'h'    and
+                   cst_str10_con_1(9) = 'i'    and
+                   cst_str10_con_1(10)= 'j'    and
+                   cst_str10_con_2(1) = 'a'    and
+                   cst_str10_con_2(2) = 'b'    and
+                   cst_str10_con_2(3) = 'c'    and
+                   cst_str10_con_2(4) = 'd'    and
+                   cst_str10_con_2(5) = 'e'    and
+                   cst_str10_con_2(6) = 'f'    and
+                   cst_str10_con_2(7) = 'g'    and
+                   cst_str10_con_2(8) = 'h'    and
+                   cst_str10_con_2(9) = 'i'    and
+                   cst_str10_con_2(10)= 'j'    and
+                   cst_digit_con_0('0') = INTEGER'LEFT    and
+                   cst_digit_con_0('1') = INTEGER'LEFT    and
+                   cst_digit_con_0('2') = INTEGER'LEFT    and
+                   cst_digit_con_0('3') = INTEGER'LEFT    and
+                   cst_digit_con_0('4') = INTEGER'LEFT    and
+                   cst_digit_con_0('5') = INTEGER'LEFT    and
+                   cst_digit_con_0('6') = INTEGER'LEFT    and
+                   cst_digit_con_0('7') = INTEGER'LEFT    and
+                   cst_digit_con_0('8') = INTEGER'LEFT    and
+                   cst_digit_con_0('9') = INTEGER'LEFT    and
+                   cst_digit_con_1('0') = 0    and
+                   cst_digit_con_1('1') = 1    and
+                   cst_digit_con_1('2') = 2    and
+                   cst_digit_con_1('3') = 3    and
+                   cst_digit_con_1('4') = 4    and
+                   cst_digit_con_1('5') = 5    and
+                   cst_digit_con_1('6') = 6    and
+                   cst_digit_con_1('7') = 7    and
+                   cst_digit_con_1('8') = 8    and
+                   cst_digit_con_1('9') = 9    and
+                   rt_date_con_0.day   = 0       and
+                   rt_date_con_0.month = Jan     and
+                   rt_date_con_0.year  = 0       and
+                   rt_date_con_1.day   = 1       and
+                   rt_date_con_1.month = Jan     and
+                   rt_date_con_1.year  = 1989    and
+                   rst_date_con_0.day   = 0       and
+                   rst_date_con_0.month = Jan     and
+                   rst_date_con_0.year  = 0       and
+                   rst_date_con_1.day   = 1       and
+                   rst_date_con_1.month = Apr     and
+                   rst_date_con_1.year  = 2000    )   
+      report "***PASSED TEST: /src/ch04/sc03/sb01/ss03/p001/s010101.vhd"
+      severity NOTE;
+    assert (       STRING_con_0(1) = NUL      and 
+                   STRING_con_0(2) = NUL       and
+                   STRING_con_0(3) = NUL       and
+                   STRING_con_0(4) = NUL       and
+                   STRING_con_0(5) = NUL       and
+                   STRING_con_0(6) = NUL       and
+                   STRING_con_0(7) = NUL       and
+                   STRING_con_1(1) = 's'       and
+                   STRING_con_1(2) = 'a'       and
+                   STRING_con_1(3) = 'i'       and
+                   STRING_con_1(4) = 'l'       and
+                   STRING_con_1(5) = 'i'       and
+                   STRING_con_1(6) = 'n'       and
+                   STRING_con_1(7) = 'g'       and
+                   STRING_con_2(1) = 's'       and
+                   STRING_con_2(2) = 'a'       and
+                   STRING_con_2(3) = 'i'       and
+                   STRING_con_2(4) = 'l'       and
+                   STRING_con_2(5) = 'i'       and
+                   STRING_con_2(6) = 'n'       and
+                   STRING_con_2(7) = 'g'       and
+                   BIT_VECTOR_con_0(0) = '0'    and
+                   BIT_VECTOR_con_0(1) = '0'    and
+                   BIT_VECTOR_con_0(2) = '0'    and
+                   BIT_VECTOR_con_0(3) = '0'    and
+                   BIT_VECTOR_con_0(4) = '0'    and
+                   BIT_VECTOR_con_0(5) = '0'    and
+                   BIT_VECTOR_con_0(6) = '0'    and
+                   BIT_VECTOR_con_0(7) = '0'    and
+                   BIT_VECTOR_con_1(0) = '1'    and
+                   BIT_VECTOR_con_1(1) = '0'    and
+                   BIT_VECTOR_con_1(2) = '1'    and
+                   BIT_VECTOR_con_1(3) = '0'    and
+                   BIT_VECTOR_con_1(4) = '1'    and
+                   BIT_VECTOR_con_1(5) = '1'    and
+                   BIT_VECTOR_con_1(6) = '1'    and
+                   BIT_VECTOR_con_1(7) = '0'    and
+                   BIT_VECTOR_con_2(0) = '1'    and
+                   BIT_VECTOR_con_2(1) = '0'    and
+                   BIT_VECTOR_con_2(2) = '1'    and
+                   BIT_VECTOR_con_2(3) = '0'    and
+                   BIT_VECTOR_con_2(4) = '1'    and
+                   BIT_VECTOR_con_2(5) = '1'    and
+                   BIT_VECTOR_con_2(6) = '1'    and
+                   BIT_VECTOR_con_2(7) = '0'    and
+                   ut_chary_con_0(NUL) = INTEGER'LEFT    and
+                   ut_chary_con_0(SOH) = INTEGER'LEFT    and
+                   ut_chary_con_0(STX) = INTEGER'LEFT    and
+                   ut_chary_con_0(ETX) = INTEGER'LEFT    and
+                   ut_chary_con_0(EOT) = INTEGER'LEFT    and
+                   ut_chary_con_0(ENQ) = INTEGER'LEFT    and
+                   ut_chary_con_1(NUL) = 1    and
+                   ut_chary_con_1(SOH) = 2    and
+                   ut_chary_con_1(STX) = 3    and
+                   ut_chary_con_1(ETX) = 9    and
+                   ut_chary_con_1(EOT) = 8    and
+                   ut_chary_con_1(ENQ) = 7    and
+                   ct_word_con_0(0) = '0'       and
+                   ct_word_con_0(1) = '0'       and
+                   ct_word_con_0(2) = '0'       and
+                   ct_word_con_0(3) = '0'       and
+                   ct_word_con_0(4) = '0'       and
+                   ct_word_con_0(5) = '0'       and
+                   ct_word_con_0(6) = '0'       and
+                   ct_word_con_0(7) = '0'       and
+                   ct_word_con_0(8) = '0'       and
+                   ct_word_con_0(9) = '0'       and
+                   ct_word_con_0(10) = '0'    and
+                   ct_word_con_0(11) = '0'    and
+                   ct_word_con_0(12) = '0'    and
+                   ct_word_con_0(13) = '0'    and
+                   ct_word_con_0(14) = '0'    and
+                   ct_word_con_0(15) = '0'    and
+                   ct_word_con_1(0) = '1'       and
+                   ct_word_con_1(1) = '1'       and
+                   ct_word_con_1(2) = '1'       and
+                   ct_word_con_1(3) = '1'       and
+                   ct_word_con_1(4) = '1'       and
+                   ct_word_con_1(5) = '1'       and
+                   ct_word_con_1(6) = '1'       and
+                   ct_word_con_1(7) = '1'       and
+                   ct_word_con_1(8) = '1'       and
+                   ct_word_con_1(9) = '1'       and
+                   ct_word_con_1(10) = '1'    and
+                   ct_word_con_1(11) = '1'    and
+                   ct_word_con_1(12) = '1'    and
+                   ct_word_con_1(13) = '1'    and
+                   ct_word_con_1(14) = '1'    and
+                   ct_word_con_1(15) = '1'    and
+                   cst_str10_con_0(1) = NUL    and
+                   cst_str10_con_0(2) = NUL    and
+                   cst_str10_con_0(3) = NUL    and
+                   cst_str10_con_0(4) = NUL    and
+                   cst_str10_con_0(5) = NUL    and
+                   cst_str10_con_0(6) = NUL    and
+                   cst_str10_con_0(7) = NUL    and
+                   cst_str10_con_0(8) = NUL    and
+                   cst_str10_con_0(9) = NUL    and
+                   cst_str10_con_0(10) = NUL    and
+                   cst_str10_con_1(1) = 'a'    and
+                   cst_str10_con_1(2) = 'b'    and
+                   cst_str10_con_1(3) = 'c'    and
+                   cst_str10_con_1(4) = 'd'    and
+                   cst_str10_con_1(5) = 'e'    and
+                   cst_str10_con_1(6) = 'f'    and
+                   cst_str10_con_1(7) = 'g'    and
+                   cst_str10_con_1(8) = 'h'    and
+                   cst_str10_con_1(9) = 'i'    and
+                   cst_str10_con_1(10)= 'j'    and
+                   cst_str10_con_2(1) = 'a'    and
+                   cst_str10_con_2(2) = 'b'    and
+                   cst_str10_con_2(3) = 'c'    and
+                   cst_str10_con_2(4) = 'd'    and
+                   cst_str10_con_2(5) = 'e'    and
+                   cst_str10_con_2(6) = 'f'    and
+                   cst_str10_con_2(7) = 'g'    and
+                   cst_str10_con_2(8) = 'h'    and
+                   cst_str10_con_2(9) = 'i'    and
+                   cst_str10_con_2(10)= 'j'    and
+                   cst_digit_con_0('0') = INTEGER'LEFT    and
+                   cst_digit_con_0('1') = INTEGER'LEFT    and
+                   cst_digit_con_0('2') = INTEGER'LEFT    and
+                   cst_digit_con_0('3') = INTEGER'LEFT    and
+                   cst_digit_con_0('4') = INTEGER'LEFT    and
+                   cst_digit_con_0('5') = INTEGER'LEFT    and
+                   cst_digit_con_0('6') = INTEGER'LEFT    and
+                   cst_digit_con_0('7') = INTEGER'LEFT    and
+                   cst_digit_con_0('8') = INTEGER'LEFT    and
+                   cst_digit_con_0('9') = INTEGER'LEFT    and
+                   cst_digit_con_1('0') = 0    and
+                   cst_digit_con_1('1') = 1    and
+                   cst_digit_con_1('2') = 2    and
+                   cst_digit_con_1('3') = 3    and
+                   cst_digit_con_1('4') = 4    and
+                   cst_digit_con_1('5') = 5    and
+                   cst_digit_con_1('6') = 6    and
+                   cst_digit_con_1('7') = 7    and
+                   cst_digit_con_1('8') = 8    and
+                   cst_digit_con_1('9') = 9    and
+                   rt_date_con_0.day   = 0       and
+                   rt_date_con_0.month = Jan     and
+                   rt_date_con_0.year  = 0       and
+                   rt_date_con_1.day   = 1       and
+                   rt_date_con_1.month = Jan     and
+                   rt_date_con_1.year  = 1989    and
+                   rst_date_con_0.day   = 0       and
+                   rst_date_con_0.month = Jan     and
+                   rst_date_con_0.year  = 0       and
+                   rst_date_con_1.day   = 1       and
+                   rst_date_con_1.month = Apr     and
+                   rst_date_con_1.year  = 2000    )   
+      report "***FAILED TEST: c04s03b01x03p01n01i00082 - A variable declaration declares a variable of the specified type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p01n01i00082arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc820.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc820.vhd
new file mode 100644
index 0000000..004ea89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc820.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc820.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b01x00p03n01i00820ent IS
+END c01s02b01x00p03n01i00820ent;
+
+ARCHITECTURE c01s02b01x00p03n01i00820arch_empty OF c01s02b01x00p03n01i00820ent IS
+
+BEGIN
+END c01s02b01x00p03n01i00820arch_empty;
+
+
+
+ARCHITECTURE c01s02b01x00p03n01i00820arch OF c01s02b01x00p03n01i00820ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s02b01x00p03n01i00820" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b01x00p03n01i00820arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc83.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc83.vhd
new file mode 100644
index 0000000..eafe359
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc83.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc83.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p02n01i00083ent IS
+END c04s03b01x03p02n01i00083ent;
+
+ARCHITECTURE c04s03b01x03p02n01i00083arch OF c04s03b01x03p02n01i00083ent IS
+  type x is (a, b, c, d);
+BEGIN
+  TESTING: PROCESS
+    variable x1 : x := a;            -- No_failure_here
+    variable x  : character := 'a';  -- No_failure_here
+    variable x2 : character := 'a';  -- No_failure_here
+  BEGIN
+    assert NOT( x1 = a and x = 'a' and x2 = 'a' )
+      report "***PASSED TEST:c04s03b01x03p02n01i00083"
+      severity NOTE;
+    assert ( x1 = a and x = 'a' and x2 = 'a' )
+      report "***FAILED TEST: c04s03b01x03p02n01i00083- Variable assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p02n01i00083arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc837.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc837.vhd
new file mode 100644
index 0000000..bf8f080
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc837.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc837.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p02n01i00837ent_a is 
+end c01s03b01x00p02n01i00837ent_a;
+
+architecture c01s03b01x00p02n01i00837arch_a of c01s03b01x00p02n01i00837ent_a is
+  signal S1 : INTEGER;
+begin
+  A2_BLK : block
+  begin
+    S1 <= 2 after 10 ns;
+  end block;
+
+  TESTING: PROCESS(S1)
+  BEGIN
+    if (now > 1 ns) then
+      assert NOT(S1 = 2) 
+        report "***PASSED TEST: c01s03b01x00p02n01i00837"
+        severity NOTE;
+      assert (S1 = 2) 
+        report "***FAILED TEST: c01s03b01x00p02n01i00837 - Configuration block syntactic error."
+        severity ERROR;
+    end if;
+  END PROCESS TESTING;
+
+end c01s03b01x00p02n01i00837arch_a;
+
+ENTITY c01s03b01x00p02n01i00837ent IS
+END c01s03b01x00p02n01i00837ent;
+
+ARCHITECTURE c01s03b01x00p02n01i00837arch OF c01s03b01x00p02n01i00837ent IS
+
+BEGIN
+
+  DBLK : block
+    component FOUR
+    end component;
+  begin
+    LS : FOUR ;
+  end block DBLK;
+
+END c01s03b01x00p02n01i00837arch;
+
+configuration c01s03b01x00p02n01i00837cfg of c01s03b01x00p02n01i00837ent  is
+  for c01s03b01x00p02n01i00837arch
+    for DBLK
+      for LS : FOUR use entity work.c01s03b01x00p02n01i00837ent_a(c01s03b01x00p02n01i00837arch_a);
+      end for;
+    end for;
+  end for;
+end c01s03b01x00p02n01i00837cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc84.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc84.vhd
new file mode 100644
index 0000000..bef10b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc84.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc84.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p02n01i00084ent IS
+END c04s03b01x03p02n01i00084ent;
+
+ARCHITECTURE c04s03b01x03p02n01i00084arch OF c04s03b01x03p02n01i00084ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x1 : bit ;                         -- No_failure_here
+    variable x2 : character ;                   -- No_failure_here
+    variable x3 : integer := 1000;                  -- No_failure_here
+    variable x4 : real := 1.001;                    -- No_failure_here
+    variable x5 : boolean ;                     -- No_failure_here
+    variable x6 : time  := 10 ns;                   -- No_failure_here
+    variable x7 : string(1 to 10) := "abcdefghij";    -- No_failure_here
+    variable x8 : bit_vector (10 downto 1);     -- No_failure_here
+  BEGIN
+    assert NOT(    x1 = '0'      and
+                   x2 = NUL      and
+                   x3 = 1000      and
+                   x4 = 1.001      and
+                   x5 = false      and
+                   x6 = 10 ns      and
+                   x7 = "abcdefghij"   and
+                   x8 = "0000000000"   ) 
+      report "***PASSED TEST:c04s03b01x03p02n01i00084"
+      severity NOTE;
+    assert (    x1 = '0'      and
+                x2 = NUL      and
+                x3 = 1000      and
+                x4 = 1.001      and
+                x5 = false      and
+                x6 = 10 ns      and
+                x7 = "abcdefghij"   and
+                x8 = "0000000000"   ) 
+      report "***FAILED TEST: c04s03b01x03p02n01i00084 - Variable assignment test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p02n01i00084arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc840.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc840.vhd
new file mode 100644
index 0000000..b6f310a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc840.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc840.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p03n01i00840ent_a is
+end c01s03b01x00p03n01i00840ent_a;
+
+architecture c01s03b01x00p03n01i00840arch_a of c01s03b01x00p03n01i00840ent_a is
+begin
+end c01s03b01x00p03n01i00840arch_a;
+
+ENTITY c01s03b01x00p03n01i00840ent IS
+END c01s03b01x00p03n01i00840ent;
+
+ARCHITECTURE c01s03b01x00p03n01i00840arch OF c01s03b01x00p03n01i00840ent IS
+
+BEGIN
+
+  AA_BLK : block
+    component FOUR
+    end component;
+  begin
+    LH : FOUR;
+    LR : FOUR;
+    aaa_blk: block
+    begin
+    end block;
+    L1: for I in 1 to 3 generate
+    end generate;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p03n01i00840"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p03n01i00840arch;
+
+configuration c01s03b01x00p03n01i00840cfg of c01s03b01x00p03n01i00840ent is
+  for c01s03b01x00p03n01i00840arch
+    for AA_BLK
+      for LH, LR : FOUR
+        use entity work.c01s03b01x00p03n01i00840ent_a(c01s03b01x00p03n01i00840arch_a);
+      end for;
+      for aaa_blk
+      end for;
+      for l1 (1 to 2)
+      end for;
+      for l1 (3)
+      end for;
+    end for;
+  end for;
+end c01s03b01x00p03n01i00840cfg;
+
+
+
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc842.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc842.vhd
new file mode 100644
index 0000000..35e3847
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc842.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc842.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p04n01i00842ent_a is
+end c01s03b01x00p04n01i00842ent_a;
+
+architecture c01s03b01x00p04n01i00842arch_a of c01s03b01x00p04n01i00842ent_a is
+begin
+end c01s03b01x00p04n01i00842arch_a;
+
+ENTITY c01s03b01x00p04n01i00842ent IS
+END c01s03b01x00p04n01i00842ent;
+
+ARCHITECTURE c01s03b01x00p04n01i00842arch OF c01s03b01x00p04n01i00842ent IS
+
+BEGIN
+  
+  AA_BLK : block
+    component FOUR
+    end component;
+  begin
+    LH : FOUR;
+    LR : FOUR;
+    aaa_blk: block
+    begin
+    end block;
+    L1: for I in 1 to 3 generate
+    end generate;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p04n01i00842"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p04n01i00842arch;
+
+configuration c01s03b01x00p04n01i00842cfg of c01s03b01x00p04n01i00842ent is
+  for c01s03b01x00p04n01i00842arch
+    for AA_BLK
+      for LH, LR : FOUR
+        use entity work.c01s03b01x00p04n01i00842ent_a(c01s03b01x00p04n01i00842arch_a);
+      end for;
+      for aaa_blk
+      end for;
+      for L1 (1 to 2)                 --- No_failure_here
+      end for;
+      for L1 (3)
+      end for;
+    end for;
+  end for;
+end c01s03b01x00p04n01i00842cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc843.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc843.vhd
new file mode 100644
index 0000000..75d0420
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc843.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc843.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p05n01i00843ent_a is 
+end c01s03b01x00p05n01i00843ent_a ;
+
+architecture c01s03b01x00p05n01i00843arch_a of c01s03b01x00p05n01i00843ent_a is
+begin
+  AC_BLK : block
+    signal B : BIT;
+  begin
+    B <= '1';
+  end block;
+end c01s03b01x00p05n01i00843arch_a;
+
+
+ENTITY c01s03b01x00p05n01i00843ent IS
+END c01s03b01x00p05n01i00843ent;
+
+ARCHITECTURE c01s03b01x00p05n01i00843arch OF c01s03b01x00p05n01i00843ent IS
+
+BEGIN
+  A_BLK : block
+    component C
+    end component;
+  begin
+    L1 : C;
+    L2 : C;
+    L3 : C;
+    L4 : C;
+    L5 : C;
+    L6 : C;
+    L7 : C;
+    L8 : C;
+    L9 : C;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p05n01i00843"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p05n01i00843arch;
+
+configuration c01s03b01x00p05n01i00843cfg of c01s03b01x00p05n01i00843ent is
+  for c01s03b01x00p05n01i00843arch
+    for A_BLK
+      for L1 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L2 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L3 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L4 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L5 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L6 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L7 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L8 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+      
+      for L9 : C
+        use entity work.c01s03b01x00p05n01i00843ent_a (c01s03b01x00p05n01i00843arch_a) ;
+      end for;
+    end for;
+  end for ;
+end c01s03b01x00p05n01i00843cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc844.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc844.vhd
new file mode 100644
index 0000000..eb2adca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc844.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc844.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p05n01i00844ent_a is 
+end c01s03b01x00p05n01i00844ent_a ;
+
+architecture c01s03b01x00p05n01i00844arch_a of c01s03b01x00p05n01i00844ent_a is
+begin
+  A1_BLK : block
+    signal S : INTEGER;
+  begin
+    S <= 1;
+  end block;
+end c01s03b01x00p05n01i00844arch_a;
+
+
+ENTITY c01s03b01x00p05n01i00844ent IS
+END c01s03b01x00p05n01i00844ent;
+
+architecture c01s03b01x00p05n01i00844arch of  c01s03b01x00p05n01i00844ent is
+BEGIN
+
+  AA_BLK : block
+    component FOUR
+    end component;
+  begin
+    LH : FOUR;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p05n01i00844"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p05n01i00844arch;
+
+configuration c01s03b01x00p05n01i00844cfg of c01s03b01x00p05n01i00844ent is
+  for c01s03b01x00p05n01i00844arch
+    for AA_BLK
+      for LH : FOUR
+        use
+          entity work.c01s03b01x00p05n01i00844ent_a(c01s03b01x00p05n01i00844arch_a);
+      end for;
+    end for;
+  end for ;
+end c01s03b01x00p05n01i00844cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc846.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc846.vhd
new file mode 100644
index 0000000..95e3d7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc846.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc846.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity and2g is
+end and2g;
+
+architecture behavior of and2g is
+begin
+end behavior;
+
+entity full_adder is
+end full_adder;
+
+architecture structural of full_adder is
+  component and2
+  end component;
+begin
+  C1: and2;
+end structural;
+
+ENTITY c01s03b01x00p08n01i00846ent IS
+END c01s03b01x00p08n01i00846ent;
+
+ARCHITECTURE c01s03b01x00p08n01i00846arch OF c01s03b01x00p08n01i00846ent IS
+  
+  component adder
+  end component;
+  
+BEGIN
+  A1 : adder;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p08n01i00846" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p08n01i00846arch;
+
+
+configuration c01s03b01x00p08n01i00846cfg of c01s03b01x00p08n01i00846ent is
+  for c01s03b01x00p08n01i00846arch
+    for A1: adder use                      -- component configuration
+                    entity work.full_adder(structural);
+                  
+                  for structural       -- no_failure_here
+                    for C1: and2 use
+                                   entity work.and2g(behavior);
+                    end for;
+                  end for;
+    end for;
+  end for;
+end c01s03b01x00p08n01i00846cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc849.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc849.vhd
new file mode 100644
index 0000000..1c9997e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc849.vhd
@@ -0,0 +1,291 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc849.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00849pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00849pkg_b;
+
+package body c01s03b01x00p12n01i00849pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00849pkg_b;
+
+use work.c01s03b01x00p12n01i00849pkg_b.all;
+package c01s03b01x00p12n01i00849pkg_a is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00849pkg_a;
+
+use work.c01s03b01x00p12n01i00849pkg_a.all;
+use work.c01s03b01x00p12n01i00849pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00849pkg_a.all;
+use work.c01s03b01x00p12n01i00849pkg_b.all;
+ENTITY c01s03b01x00p12n01i00849ent IS
+END c01s03b01x00p12n01i00849ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00849arch OF c01s03b01x00p12n01i00849ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00849"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00849 - Block configuration apply to implicit blocks generated by that generate statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00849arch;
+
+configuration c01s03b01x00p12n01i00849cfg of c01s03b01x00p12n01i00849ent is
+  for c01s03b01x00p12n01i00849arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc850.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc850.vhd
new file mode 100644
index 0000000..7bdcbe0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc850.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc850.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00850pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00850pkg_b;
+
+package body c01s03b01x00p12n01i00850pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00850pkg_b;
+
+use work.c01s03b01x00p12n01i00850pkg_b.all;
+package c01s03b01x00p12n01i00850pkg_a is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00850pkg_a;
+
+
+use work.c01s03b01x00p12n01i00850pkg_a.all;
+use work.c01s03b01x00p12n01i00850pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00850pkg_a.all;
+use work.c01s03b01x00p12n01i00850pkg_b.all;
+ENTITY c01s03b01x00p12n01i00850ent IS
+END c01s03b01x00p12n01i00850ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00850arch OF c01s03b01x00p12n01i00850ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00850"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00850 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00850arch;
+
+configuration c01s03b01x00p12n01i00850cfg of c01s03b01x00p12n01i00850ent is
+  for c01s03b01x00p12n01i00850arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(zero to three)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc852.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc852.vhd
new file mode 100644
index 0000000..ecae4e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc852.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc852.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00852pkg_2 is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00852pkg_2;
+
+package body c01s03b01x00p12n01i00852pkg_2 is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00852pkg_2;
+
+use work.c01s03b01x00p12n01i00852pkg_2.all;
+package c01s03b01x00p12n01i00852pkg is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal dumy : bit_vector(zero to three);
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00852pkg;
+
+use work.c01s03b01x00p12n01i00852pkg.all;
+use work.c01s03b01x00p12n01i00852pkg_2.all;
+entity c01s03b01x00p12n01i00852ent_a is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture c01s03b01x00p12n01i00852ent_a of c01s03b01x00p12n01i00852ent_a is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration c01s03b01x00p12n01i00852ent_abench of c01s03b01x00p12n01i00852ent_a is
+  for c01s03b01x00p12n01i00852ent_a
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00852pkg.all;
+use work.c01s03b01x00p12n01i00852pkg_2.all;
+ENTITY c01s03b01x00p12n01i00852ent IS
+END c01s03b01x00p12n01i00852ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00852arch OF c01s03b01x00p12n01i00852ent IS
+  component c01s03b01x00p12n01i00852ent_a
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component c01s03b01x00p12n01i00852ent_a
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : c01s03b01x00p12n01i00852ent_a
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:c01s03b01x00p12n01i00852ent_a
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00852"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00852 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00852arch;
+
+configuration c01s03b01x00p12n01i00852cfg of c01s03b01x00p12n01i00852ent is
+  for c01s03b01x00p12n01i00852arch
+    for K
+      for T5:c01s03b01x00p12n01i00852ent_a use configuration work.c01s03b01x00p12n01i00852ent_abench;
+      end for;
+      for G(dumy'range)
+        for T1:c01s03b01x00p12n01i00852ent_a
+          use configuration work.c01s03b01x00p12n01i00852ent_abench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc853.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc853.vhd
new file mode 100644
index 0000000..b471197
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc853.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc853.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00853pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00853pkg_b;
+
+package body c01s03b01x00p12n01i00853pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00853pkg_b;
+
+use work.c01s03b01x00p12n01i00853pkg_b.all;
+package c01s03b01x00p12n01i00853pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010";
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00853pkg_a;
+
+use work.c01s03b01x00p12n01i00853pkg_a.all;
+use work.c01s03b01x00p12n01i00853pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00853pkg_a.all;
+use work.c01s03b01x00p12n01i00853pkg_b.all;
+ENTITY c01s03b01x00p12n01i00853ent IS
+END c01s03b01x00p12n01i00853ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00853arch OF c01s03b01x00p12n01i00853ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00853"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00853 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00853arch;
+
+configuration c01s03b01x00p12n01i00853cfg of c01s03b01x00p12n01i00853ent is
+  for c01s03b01x00p12n01i00853arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(dumy'reverse_range)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc854.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc854.vhd
new file mode 100644
index 0000000..3744c5e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc854.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc854.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00854pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00854pkg_b;
+
+package body c01s03b01x00p12n01i00854pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00854pkg_b;
+
+use work.c01s03b01x00p12n01i00854pkg_b.all;
+package c01s03b01x00p12n01i00854pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010";
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00854pkg_a;
+
+use work.c01s03b01x00p12n01i00854pkg_a.all;
+use work.c01s03b01x00p12n01i00854pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00854pkg_a.all;
+use work.c01s03b01x00p12n01i00854pkg_b.all;
+ENTITY c01s03b01x00p12n01i00854ent IS
+END c01s03b01x00p12n01i00854ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00854arch OF c01s03b01x00p12n01i00854ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00854"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00854 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00854arch;
+
+configuration c01s03b01x00p12n01i00854cfg of c01s03b01x00p12n01i00854ent is
+  for c01s03b01x00p12n01i00854arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(dumy'reverse_range(1))
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc855.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc855.vhd
new file mode 100644
index 0000000..6c44d39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc855.vhd
@@ -0,0 +1,291 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc855.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00855pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00855pkg_b;
+
+package body c01s03b01x00p12n01i00855pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00855pkg_b;
+
+use work.c01s03b01x00p12n01i00855pkg_b.all;
+package c01s03b01x00p12n01i00855pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00855pkg_a;
+
+use work.c01s03b01x00p12n01i00855pkg_a.all;
+use work.c01s03b01x00p12n01i00855pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00855pkg_a.all;
+use work.c01s03b01x00p12n01i00855pkg_b.all;
+ENTITY c01s03b01x00p12n01i00855ent IS
+END c01s03b01x00p12n01i00855ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00855arch OF c01s03b01x00p12n01i00855ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00855"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00855 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00855arch;
+
+configuration c01s03b01x00p12n01i00855cfg of c01s03b01x00p12n01i00855ent is
+  for c01s03b01x00p12n01i00855arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(zero to 3)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc856.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc856.vhd
new file mode 100644
index 0000000..6bc98cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc856.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc856.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00856pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00856pkg_b;
+
+package body c01s03b01x00p12n01i00856pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00856pkg_b;
+
+use work.c01s03b01x00p12n01i00856pkg_b.all;
+package c01s03b01x00p12n01i00856pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010";
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00856pkg_a;
+
+use work.c01s03b01x00p12n01i00856pkg_a.all;
+use work.c01s03b01x00p12n01i00856pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00856pkg_a.all;
+use work.c01s03b01x00p12n01i00856pkg_b.all;
+ENTITY c01s03b01x00p12n01i00856ent IS
+END c01s03b01x00p12n01i00856ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00856arch OF c01s03b01x00p12n01i00856ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00856"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00856 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00856arch;
+
+configuration c01s03b01x00p12n01i00856cfg of c01s03b01x00p12n01i00856ent is
+  for c01s03b01x00p12n01i00856arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(hi_to_low_range)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc857.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc857.vhd
new file mode 100644
index 0000000..69353ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc857.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc857.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00857pkg_2 is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00857pkg_2;
+
+package body c01s03b01x00p12n01i00857pkg_2 is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00857pkg_2;
+
+use work.c01s03b01x00p12n01i00857pkg_2.all;
+package c01s03b01x00p12n01i00857pkg is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00857pkg;
+
+use work.c01s03b01x00p12n01i00857pkg.all;
+use work.c01s03b01x00p12n01i00857pkg_2.all;
+entity c01s03b01x00p12n01i00857ent_a is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture c01s03b01x00p12n01i00857ent_a of c01s03b01x00p12n01i00857ent_a is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration c01s03b01x00p12n01i00857ent_abench of c01s03b01x00p12n01i00857ent_a is
+  for c01s03b01x00p12n01i00857ent_a
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00857pkg.all;
+use work.c01s03b01x00p12n01i00857pkg_2.all;
+ENTITY c01s03b01x00p12n01i00857ent IS
+END c01s03b01x00p12n01i00857ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00857arch OF c01s03b01x00p12n01i00857ent IS
+  component c01s03b01x00p12n01i00857ent_a
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component c01s03b01x00p12n01i00857ent_a
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : c01s03b01x00p12n01i00857ent_a
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:c01s03b01x00p12n01i00857ent_a
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00857"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00857 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00857arch;
+
+configuration c01s03b01x00p12n01i00857cfg of c01s03b01x00p12n01i00857ent is
+  for c01s03b01x00p12n01i00857arch
+    for K
+      for T5:c01s03b01x00p12n01i00857ent_a use configuration work.c01s03b01x00p12n01i00857ent_abench;
+      end for;
+      for G(dumy'low to 3)
+        for T1:c01s03b01x00p12n01i00857ent_a
+          use configuration work.c01s03b01x00p12n01i00857ent_abench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc858.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc858.vhd
new file mode 100644
index 0000000..44bc00d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc858.vhd
@@ -0,0 +1,292 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc858.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00858pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00858pkg_b;
+
+package body c01s03b01x00p12n01i00858pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00858pkg_b;
+
+use work.c01s03b01x00p12n01i00858pkg_b.all;
+package c01s03b01x00p12n01i00858pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00858pkg_a;
+
+use work.c01s03b01x00p12n01i00858pkg_a.all;
+use work.c01s03b01x00p12n01i00858pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00858pkg_a.all;
+use work.c01s03b01x00p12n01i00858pkg_b.all;
+ENTITY c01s03b01x00p12n01i00858ent IS
+END c01s03b01x00p12n01i00858ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00858arch OF c01s03b01x00p12n01i00858ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00858"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00858 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00858arch;
+
+configuration c01s03b01x00p12n01i00858cfg of c01s03b01x00p12n01i00858ent is
+  for c01s03b01x00p12n01i00858arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(zero to dumy'high)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc859.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc859.vhd
new file mode 100644
index 0000000..78e1f4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc859.vhd
@@ -0,0 +1,296 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc859.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00859pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00859pkg_b;
+
+package body c01s03b01x00p12n01i00859pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00859pkg_b;
+
+use work.c01s03b01x00p12n01i00859pkg_b.all;
+package c01s03b01x00p12n01i00859pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to six) ;
+  signal Sin2 : boolean_vector(zero to six) ;
+  signal Sin4 : severity_level_vector(zero to six) ;
+  signal Sin5 : integer_vector(zero to six) ;
+  signal Sin6 : real_vector(zero to six) ;
+  signal Sin7 : time_vector(zero to six) ;
+  signal Sin8 : natural_vector(zero to six) ;
+  signal Sin9 : positive_vector(zero to six) ;
+  signal Sin10: array_rec_std(zero to six) ;
+end c01s03b01x00p12n01i00859pkg_a;
+
+use work.c01s03b01x00p12n01i00859pkg_a.all;
+use work.c01s03b01x00p12n01i00859pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00859pkg_a.all;
+use work.c01s03b01x00p12n01i00859pkg_b.all;
+ENTITY c01s03b01x00p12n01i00859ent IS
+END c01s03b01x00p12n01i00859ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00859arch OF c01s03b01x00p12n01i00859ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    Gif : if fifteen = 15 generate
+      T5 : test
+        port map
+        (
+          Sin2(4),Sin2(5),
+          Sin1(4),Sin1(5),
+          Sin4(4),Sin4(5),
+          Sin5(4),Sin5(5),
+          Sin6(4),Sin6(5),
+          Sin7(4),Sin7(5),
+          Sin8(4),Sin8(5),
+          Sin9(4),Sin9(5),
+          Sin10(4),Sin10(5)
+          );
+    end generate;
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00859"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00859 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00859arch;
+
+configuration cc01s03b01x00p12n01i00859cfg of c01s03b01x00p12n01i00859ent is
+  for c01s03b01x00p12n01i00859arch
+    for K
+      for GIF
+        for T5:test use configuration work.testbench;
+        end for;
+      end for;
+      for G(zero to dumy'high)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc86.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc86.vhd
new file mode 100644
index 0000000..b9706b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc86.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc86.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p05n02i00086ent IS
+END c04s03b01x03p05n02i00086ent;
+
+ARCHITECTURE c04s03b01x03p05n02i00086arch OF c04s03b01x03p05n02i00086ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type some_type is (Sunday,Monday,Tuesday,Wed,Thur,Fri);
+    variable X : some_type;    -- No_failure_here
+    -- no default value declared.
+  BEGIN
+
+    assert NOT( X=Sunday )
+      report "***PASSED TEST: c04s03b01x03p05n02i00086"
+      severity NOTE;
+    assert ( X=Sunday )
+      report "***FAILED TEST: c04s03b01x03p05n02i00086 - Variable default assignment failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p05n02i00086arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc860.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc860.vhd
new file mode 100644
index 0000000..f7abe68
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc860.vhd
@@ -0,0 +1,311 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc860.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00860pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00860pkg_b;
+
+package body c01s03b01x00p12n01i00860pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00860pkg_b;
+
+use work.c01s03b01x00p12n01i00860pkg_b.all;
+package c01s03b01x00p12n01i00860pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to six) ;
+  signal Sin2 : boolean_vector(zero to six) ;
+  signal Sin4 : severity_level_vector(zero to six) ;
+  signal Sin5 : integer_vector(zero to six) ;
+  signal Sin6 : real_vector(zero to six) ;
+  signal Sin7 : time_vector(zero to six) ;
+  signal Sin8 : natural_vector(zero to six) ;
+  signal Sin9 : positive_vector(zero to six) ;
+  signal Sin10: array_rec_std(zero to six) ;
+end c01s03b01x00p12n01i00860pkg_a;
+
+use work.c01s03b01x00p12n01i00860pkg_a.all;
+use work.c01s03b01x00p12n01i00860pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00860pkg_a.all;
+use work.c01s03b01x00p12n01i00860pkg_b.all;
+ENTITY c01s03b01x00p12n01i00860ent IS
+END c01s03b01x00p12n01i00860ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00860arch OF c01s03b01x00p12n01i00860ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    Gif : if fifteen = 15 generate
+      T5 : test
+        port map
+        (
+          Sin2(4),Sin2(5),
+          Sin1(4),Sin1(5),
+          Sin4(4),Sin4(5),
+          Sin5(4),Sin5(5),
+          Sin6(4),Sin6(5),
+          Sin7(4),Sin7(5),
+          Sin8(4),Sin8(5),
+          Sin9(4),Sin9(5),
+          Sin10(4),Sin10(5)
+          );
+    end generate;
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00860"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00860 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00860arch;
+
+configuration c01s03b01x00p12n01i00860cfg of c01s03b01x00p12n01i00860ent is
+  for c01s03b01x00p12n01i00860arch
+    for K
+      for GIF
+        for T5:test use configuration work.testbench;
+        end for;
+      end for;
+      for G(zero)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(one)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(two)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(three)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc861.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc861.vhd
new file mode 100644
index 0000000..50e31ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc861.vhd
@@ -0,0 +1,301 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc861.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00861pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00861pkg_b;
+
+package body c01s03b01x00p12n01i00861pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00861pkg_b;
+
+use work.c01s03b01x00p12n01i00861pkg_b.all;
+package c01s03b01x00p12n01i00861pkg_a is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to six) ;
+  signal Sin2 : boolean_vector(zero to six) ;
+  signal Sin4 : severity_level_vector(zero to six) ;
+  signal Sin5 : integer_vector(zero to six) ;
+  signal Sin6 : real_vector(zero to six) ;
+  signal Sin7 : time_vector(zero to six) ;
+  signal Sin8 : natural_vector(zero to six) ;
+  signal Sin9 : positive_vector(zero to six) ;
+  signal Sin10: array_rec_std(zero to six) ;
+end c01s03b01x00p12n01i00861pkg_a;
+
+use work.c01s03b01x00p12n01i00861pkg_a.all;
+use work.c01s03b01x00p12n01i00861pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00861pkg_a.all;
+use work.c01s03b01x00p12n01i00861pkg_b.all;
+ENTITY c01s03b01x00p12n01i00861ent IS
+END c01s03b01x00p12n01i00861ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00861arch OF c01s03b01x00p12n01i00861ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    Gif : if fifteen = 15 generate
+      T5 : test
+        port map
+        (
+          Sin2(4),Sin2(5),
+          Sin1(4),Sin1(5),
+          Sin4(4),Sin4(5),
+          Sin5(4),Sin5(5),
+          Sin6(4),Sin6(5),
+          Sin7(4),Sin7(5),
+          Sin8(4),Sin8(5),
+          Sin9(4),Sin9(5),
+          Sin10(4),Sin10(5)
+          );
+    end generate;
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00861"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00861 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00861arch;
+
+configuration c01s03b01x00p12n01i00861cfg of c01s03b01x00p12n01i00861ent is
+  for c01s03b01x00p12n01i00861arch
+    for K
+      for GIF
+        for T5:test use configuration work.testbench;
+        end for;
+      end for;
+      for G(zero to 1)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(2 to three)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc862.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc862.vhd
new file mode 100644
index 0000000..f6747d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc862.vhd
@@ -0,0 +1,302 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc862.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00862pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00862pkg_b;
+
+package body c01s03b01x00p12n01i00862pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00862pkg_b;
+
+use work.c01s03b01x00p12n01i00862pkg_b.all;
+package c01s03b01x00p12n01i00862pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant dumy : bit_vector(zero to three) := "1010" ;
+  signal Sin1 : bit_vector(zero to six) ;
+  signal Sin2 : boolean_vector(zero to six) ;
+  signal Sin4 : severity_level_vector(zero to six) ;
+  signal Sin5 : integer_vector(zero to six) ;
+  signal Sin6 : real_vector(zero to six) ;
+  signal Sin7 : time_vector(zero to six) ;
+  signal Sin8 : natural_vector(zero to six) ;
+  signal Sin9 : positive_vector(zero to six) ;
+  signal Sin10: array_rec_std(zero to six) ;
+end c01s03b01x00p12n01i00862pkg_a;
+
+use work.c01s03b01x00p12n01i00862pkg_a.all;
+use work.c01s03b01x00p12n01i00862pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00862pkg_a.all;
+use work.c01s03b01x00p12n01i00862pkg_b.all;
+
+ENTITY c01s03b01x00p12n01i00862ent IS
+END c01s03b01x00p12n01i00862ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00862arch OF c01s03b01x00p12n01i00862ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    Gif : if fifteen = 15 generate
+      T5 : test
+        port map
+        (
+          Sin2(4),Sin2(5),
+          Sin1(4),Sin1(5),
+          Sin4(4),Sin4(5),
+          Sin5(4),Sin5(5),
+          Sin6(4),Sin6(5),
+          Sin7(4),Sin7(5),
+          Sin8(4),Sin8(5),
+          Sin9(4),Sin9(5),
+          Sin10(4),Sin10(5)
+          );
+    end generate;
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00862"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00862 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00862arch;
+
+configuration c01s03b01x00p12n01i00862cfg of c01s03b01x00p12n01i00862ent is
+  for c01s03b01x00p12n01i00862arch
+    for K
+      for GIF
+        for T5:test use configuration work.testbench;
+        end for;
+      end for;
+      for G(dumy'low to 1)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(2 to dumy'high)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc863.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc863.vhd
new file mode 100644
index 0000000..23ede50
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc863.vhd
@@ -0,0 +1,296 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc863.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00863pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00863pkg_b;
+
+package body c01s03b01x00p12n01i00863pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00863pkg_b;
+
+use work.c01s03b01x00p12n01i00863pkg_b.all;
+package c01s03b01x00p12n01i00863pkg_a is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00863pkg_a;
+
+use work.c01s03b01x00p12n01i00863pkg_a.all;
+use work.c01s03b01x00p12n01i00863pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00863pkg_a.all;
+use work.c01s03b01x00p12n01i00863pkg_b.all;
+ENTITY c01s03b01x00p12n01i00863ent IS
+END c01s03b01x00p12n01i00863ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00863arch OF c01s03b01x00p12n01i00863ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00863"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00863 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00863arch;
+
+configuration c01s03b01x00p12n01i00863cfg of c01s03b01x00p12n01i00863ent is
+  for c01s03b01x00p12n01i00863arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(3)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(0 to 2)
+        for all:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc864.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc864.vhd
new file mode 100644
index 0000000..e01267a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc864.vhd
@@ -0,0 +1,273 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc864.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00864pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  signal dumy : bit_vector(0 to 3);
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00864pkg;
+
+use work.c01s03b01x00p12n01i00864pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00864pkg.all;
+ENTITY c01s03b01x00p12n01i00864ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+END c01s03b01x00p12n01i00864ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00864arch OF c01s03b01x00p12n01i00864ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00864"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00864 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00864arch;
+
+configuration c01s03b01x00p12n01i00864cfg of c01s03b01x00p12n01i00864ent is
+  for c01s03b01x00p12n01i00864arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(zero to three)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc866.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc866.vhd
new file mode 100644
index 0000000..12f6aff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc866.vhd
@@ -0,0 +1,288 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc866.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00866pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00866pkg;
+
+use work.c01s03b01x00p12n01i00866pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00866pkg.all;
+ENTITY c01s03b01x00p12n01i00866ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+END c01s03b01x00p12n01i00866ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00866arch OF c01s03b01x00p12n01i00866ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00866"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00866 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00866arch;
+
+configuration c01s03b01x00p12n01i00866cfg of c01s03b01x00p12n01i00866ent is
+  for c01s03b01x00p12n01i00866arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(one)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(3)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(dumy'low)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(2)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc867.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc867.vhd
new file mode 100644
index 0000000..921262d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc867.vhd
@@ -0,0 +1,284 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc867.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00867pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00867pkg;
+
+use work.c01s03b01x00p12n01i00867pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00867pkg.all;
+ENTITY c01s03b01x00p12n01i00867ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15;
+    dumb : bit_vector(0 to 3) := "1010");
+END c01s03b01x00p12n01i00867ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00867arch OF c01s03b01x00p12n01i00867ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00867"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00867 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00867arch;
+
+configuration c01s03b01x00p12n01i00867cfg of c01s03b01x00p12n01i00867ent is
+  for c01s03b01x00p12n01i00867arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(one)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(dumy'low)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(2 to dumy'high)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc868.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc868.vhd
new file mode 100644
index 0000000..50de97c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc868.vhd
@@ -0,0 +1,346 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc868.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00868pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00868pkg;
+
+use work.c01s03b01x00p12n01i00868pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00868pkg.all;
+entity test1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test1 of test1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration test1bench of test1 is
+  for test1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00868pkg.all;
+ENTITY c01s03b01x00p12n01i00868ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00868ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00868arch OF c01s03b01x00p12n01i00868ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test1
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test1
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00868"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00868 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00868arch;
+
+configuration c01s03b01x00p12n01i00868cfg of c01s03b01x00p12n01i00868ent is
+  for c01s03b01x00p12n01i00868arch
+    for K
+      for T5:test1 use configuration work.test1bench;
+      end for;
+      for G(0 to 3)
+        for all :test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc869.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc869.vhd
new file mode 100644
index 0000000..30ffda6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc869.vhd
@@ -0,0 +1,346 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc869.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00869pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00869pkg;
+
+use work.c01s03b01x00p12n01i00869pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00869pkg.all;
+entity test1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test1 of test1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration test1bench of test1 is
+  for test1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00869pkg.all;
+ENTITY c01s03b01x00p12n01i00869ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00869ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00869arch OF c01s03b01x00p12n01i00869ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test1
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test1
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00869"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00869 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00869arch;
+
+configuration c01s03b01x00p12n01i00869cfg of c01s03b01x00p12n01i00869ent is
+  for c01s03b01x00p12n01i00869arch
+    for K
+      for all:test1 use configuration work.test1bench;
+      end for;
+      for G(0 to 3)
+        for T1 :test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc87.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc87.vhd
new file mode 100644
index 0000000..36e634f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc87.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc87.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p05n02i00087ent IS
+END c04s03b01x03p05n02i00087ent;
+
+ARCHITECTURE c04s03b01x03p05n02i00087arch OF c04s03b01x03p05n02i00087ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type acc_type is access integer;
+    variable x : acc_type ;           -- No_failure_here
+  BEGIN
+
+    assert NOT( X=Null )
+      report "***PASSED TEST: c04s03b01x03p05n02i00087"
+      severity NOTE;
+    assert ( X=Null )
+      report "***FAILED TEST: c04s03b01x03p05n02i00087 - Variable default assignment failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p05n02i00087arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc870.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc870.vhd
new file mode 100644
index 0000000..6d8899d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc870.vhd
@@ -0,0 +1,346 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc870.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00870pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00870pkg;
+
+use work.c01s03b01x00p12n01i00870pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00870pkg.all;
+entity test1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test1 of test1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration test1bench of test1 is
+  for test1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00870pkg.all;
+ENTITY c01s03b01x00p12n01i00870ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00870ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00870arch OF c01s03b01x00p12n01i00870ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test1
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test1
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00870"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00870 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00870arch;
+
+configuration c01s03b01x00p12n01i00870cfg of c01s03b01x00p12n01i00870ent is
+  for c01s03b01x00p12n01i00870arch
+    for K
+      for others:test1 use configuration work.test1bench;
+      end for;
+      for G(0 to 3)
+        for all :test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc871.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc871.vhd
new file mode 100644
index 0000000..245600f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc871.vhd
@@ -0,0 +1,324 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc871.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00871pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00871pkg;
+
+use work.c01s03b01x00p12n01i00871pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00871pkg.all;
+entity test1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test1 of test1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration test1bench of test1 is
+  for test1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00871pkg.all;
+ENTITY c01s03b01x00p12n01i00871ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00871ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00871arch OF c01s03b01x00p12n01i00871ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00871"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00871 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00871arch;
+
+configuration c01s03b01x00p12n01i00871cfg of c01s03b01x00p12n01i00871ent is
+  for c01s03b01x00p12n01i00871arch
+    for K
+      for all:test use configuration work.test1bench;
+      end for;
+      for G(0 to 3)
+        for T1 :test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc872.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc872.vhd
new file mode 100644
index 0000000..b2aba52
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc872.vhd
@@ -0,0 +1,346 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc872.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00872pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  subtype dumy is integer range 0 to 3;
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00872pkg;
+
+use work.c01s03b01x00p12n01i00872pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00872pkg.all;
+entity test1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test1 of test1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration test1bench of test1 is
+  for test1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00872pkg.all;
+ENTITY c01s03b01x00p12n01i00872ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00872ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00872arch OF c01s03b01x00p12n01i00872ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test1
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test1
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00872"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00872 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00872arch;
+
+configuration c01s03b01x00p12n01i00872cfg of c01s03b01x00p12n01i00872ent is
+  for c01s03b01x00p12n01i00872arch
+    for K
+      for all:test1 use configuration work.test1bench;
+      end for;
+      for G(0 to 3)
+        for others :test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc873.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc873.vhd
new file mode 100644
index 0000000..1ed0a88
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc873.vhd
@@ -0,0 +1,324 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc873.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00873pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00873pkg;
+
+use work.c01s03b01x00p12n01i00873pkg.all;
+entity c01s03b01x00p12n01i00873ent_a is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture c01s03b01x00p12n01i00873ent_a of c01s03b01x00p12n01i00873ent_a is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration c01s03b01x00p12n01i00873ent_abench of c01s03b01x00p12n01i00873ent_a is
+  for c01s03b01x00p12n01i00873ent_a
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00873pkg.all;
+entity c01s03b01x00p12n01i00873ent_a1 is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture c01s03b01x00p12n01i00873ent_a1 of c01s03b01x00p12n01i00873ent_a1 is
+begin
+  sigout1 <= false;
+  sigout2 <= '0';
+  sigout4 <= error;
+  sigout5 <= 6;
+  sigout6 <= 6.0;
+  sigout7 <= 6 ns;
+  sigout8 <= 6;
+  sigout9 <= 6;
+  sigout10 <= (false,'0','h',error,6,6.0,6 ns,6,6);
+end;
+
+configuration c01s03b01x00p12n01i00873ent_a1bench of c01s03b01x00p12n01i00873ent_a1 is
+  for c01s03b01x00p12n01i00873ent_a1
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00873pkg.all;
+ENTITY c01s03b01x00p12n01i00873ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+  port(
+    dumy : inout bit_vector(zero to three));
+END c01s03b01x00p12n01i00873ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00873arch OF c01s03b01x00p12n01i00873ent IS
+  component c01s03b01x00p12n01i00873ent_a
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+
+  BEGIN
+    T5 : c01s03b01x00p12n01i00873ent_a
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:c01s03b01x00p12n01i00873ent_a
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+    variable dumb : bit_vector(zero to three);
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(4) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(4) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(4) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(4) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(4) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(4) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(4) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(4) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(4) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert Sin1(5) = '0' report "assignment of Sin1(5) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(5) = false report "assignment of Sin2(5) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(5) = error report "assignment of Sin4(5) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(5) = 6 report "assignment of Sin5(5) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(5) = 6.0 report "assignment of Sin6(5) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(5) = 6 ns report "assignment of Sin7(5) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(5) = 6 report "assignment of Sin8(5) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(5) = 6 report "assignment of Sin9(5) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(5) = (false,'0','h',error,6,6.0,6 ns,6,6) report "assignment of Sin15(5) to Sin15(4) is invalid through entity port" severity failure;
+    
+    assert NOT(    Sin1(0) = sin1(4)   and
+                   Sin2(0) = Sin2(4)   and
+                   Sin4(0) = Sin4(4)   and
+                   Sin5(0) = Sin5(4)   and
+                   Sin6(0) = Sin6(4)   and
+                   Sin7(0) = Sin7(4)   and
+                   Sin8(0) = Sin8(4)   and
+                   Sin9(0) = Sin9(4)   and
+                   Sin10(0)= Sin10(4)   and
+                   Sin1(5) = '0'      and
+                   Sin2(5) = FALSE      and
+                   Sin4(5) = error      and
+                   Sin5(5) = 6      and
+                   Sin6(5) = 6.0      and
+                   Sin7(5) = 6 ns      and
+                   Sin8(5) = 6      and
+                   Sin9(5) = 6      and
+                   Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***PASSED TEST: c01s03b01x00p12n01i00873"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(4)   and
+                Sin2(0) = Sin2(4)   and
+                Sin4(0) = Sin4(4)   and
+                Sin5(0) = Sin5(4)   and
+                Sin6(0) = Sin6(4)   and
+                Sin7(0) = Sin7(4)   and
+                Sin8(0) = Sin8(4)   and
+                Sin9(0) = Sin9(4)   and
+                Sin10(0)= Sin10(4)   and
+                Sin1(5) = '0'      and
+                Sin2(5) = FALSE      and
+                Sin4(5) = error      and
+                Sin5(5) = 6      and
+                Sin6(5) = 6.0      and
+                Sin7(5) = 6 ns      and
+                Sin8(5) = 6      and
+                Sin9(5) = 6      and
+                Sin10(5)=(False,'0','h',error,6,6.0,6 ns,6,6))
+      report "***FAILED TEST: c01s03b01x00p12n01i00873 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00873arch;
+
+configuration c01s03b01x00p12n01i00873cfg of c01s03b01x00p12n01i00873ent is
+  for c01s03b01x00p12n01i00873arch
+    for K
+      for others:c01s03b01x00p12n01i00873ent_a use configuration work.c01s03b01x00p12n01i00873ent_a1bench;
+      end for;
+      for G(0 to 3)
+        for T1 :c01s03b01x00p12n01i00873ent_a
+          use configuration work.c01s03b01x00p12n01i00873ent_abench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc874.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc874.vhd
new file mode 100644
index 0000000..55b568e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc874.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc874.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p17n02i00874ent_a is
+end c01s03b01x00p17n02i00874ent_a;
+
+architecture c01s03b01x00p17n02i00874arch_a of c01s03b01x00p17n02i00874ent_a is
+begin
+end c01s03b01x00p17n02i00874arch_a;
+
+entity c01s03b01x00p17n02i00874ent_b is
+end c01s03b01x00p17n02i00874ent_b;
+
+architecture c01s03b01x00p17n02i00874arch_b of c01s03b01x00p17n02i00874ent_b is
+  component c01s03b01x00p17n02i00874ent_a
+  end component;
+begin
+  C1: c01s03b01x00p17n02i00874ent_a;
+end c01s03b01x00p17n02i00874arch_b;
+
+ENTITY c01s03b01x00p17n02i00874ent IS
+END c01s03b01x00p17n02i00874ent;
+
+ARCHITECTURE c01s03b01x00p17n02i00874arch OF c01s03b01x00p17n02i00874ent IS
+
+  component adder
+  end component;
+  
+BEGIN
+  A1 : adder;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p17n02i00874"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p17n02i00874arch;
+
+configuration c01s03b01x00p17n02i00874cfg of c01s03b01x00p17n02i00874ent is
+  for c01s03b01x00p17n02i00874arch
+    for A1: adder use             -- component configuration
+                    entity work.c01s03b01x00p17n02i00874ent_b(c01s03b01x00p17n02i00874arch_b);
+                  
+                  for c01s03b01x00p17n02i00874arch_b          -- no_failure_here    block configuration
+                    -- implicit component configuration
+                  end for;           -- no_failure_here
+    end for;
+  end for;
+end c01s03b01x00p17n02i00874cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc876.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc876.vhd
new file mode 100644
index 0000000..501d040
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc876.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc876.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b02x00p02n01i00876ent_a  is
+  port (   ia, ib : bit;
+           oc, od : out bit) ;
+end c01s03b02x00p02n01i00876ent_a;
+
+architecture c01s03b02x00p02n01i00876arch_a of c01s03b02x00p02n01i00876ent_a is
+begin
+  A1_BLK : block
+    signal S : INTEGER;
+  begin
+    S <= 1;
+  end block;
+end c01s03b02x00p02n01i00876arch_a;
+
+
+ENTITY c01s03b02x00p02n01i00876ent IS
+  port (   P3 : out bit;
+           P4 : out bit) ;
+END c01s03b02x00p02n01i00876ent;
+
+ARCHITECTURE c01s03b02x00p02n01i00876arch OF c01s03b02x00p02n01i00876ent IS
+
+BEGIN
+  BB : block
+    signal S1 : bit;
+    signal S2 : bit;
+    component LOCAL port(   CI, I2  : in BIT;
+                            CO, RES :out BIT);
+    end component ;
+    
+    for all : LOCAL
+      use entity work.c01s03b02x00p02n01i00876ent_a (c01s03b02x00p02n01i00876arch_a)
+      port map (ia => CI, ib => I2, oc => CO, od => RES);
+  begin
+    L : LOCAL
+      port map (CI =>S1 , I2 =>S2 , CO=>P3 , RES =>P4 );
+    assert FALSE 
+      report "***PASSED TEST: c01s03b02x00p02n01i00876"
+      severity NOTE;
+  end block BB;
+
+END c01s03b02x00p02n01i00876arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc877.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc877.vhd
new file mode 100644
index 0000000..d7d2d0d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc877.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc877.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s03b02x00p02n01i00877ent IS
+END c01s03b02x00p02n01i00877ent;
+
+ARCHITECTURE c01s03b02x00p02n01i00877arch OF c01s03b02x00p02n01i00877ent IS
+
+BEGIN
+  BB : block
+
+    component LOCAL
+    end component;
+  begin
+    CIS : LOCAL;
+
+    assert FALSE 
+      report "***PASSED TEST: c01s03b02x00p02n01i00877"
+      severity NOTE;
+  end block BB;
+
+END c01s03b02x00p02n01i00877arch;
+
+configuration c01s03b02x00p02n01i00877cfg of c01s03b02x00p02n01i00877ent is
+  for  c01s03b02x00p02n01i00877arch
+    for BB
+      for CIS : LOCAL             -- Success_here
+      end for;
+    end for;
+  end for ;
+end c01s03b02x00p02n01i00877cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc878.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc878.vhd
new file mode 100644
index 0000000..aff9317
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc878.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc878.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s01b00x00p03n01i00878pkg is
+  constant UNIT_DELAY: TIME := 1 ns;
+end c10s01b00x00p03n01i00878pkg;
+
+-- a nand gate
+entity ENT1 is
+  port ( BITIN1, BITIN2 : in  BIT;
+         BITOUT: out BIT );
+end ENT1;
+
+use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
+architecture ARC1 of ENT1 is
+begin
+  BITOUT <= ( BITIN1 nand BITIN2 ) after UNIT_DELAY;
+end ARC1;
+
+configuration CON1 of ENT1 is
+  for ARC1
+  end for;
+end CON1;
+
+-- build an inverter from nand-nand logic
+entity ENT2 is
+  port ( GOING_IN: in BIT;
+         COMING_OUT: out BIT );
+end ENT2;
+
+architecture ARC2 of ENT2 is
+  component NAND_BOX
+    port ( IN1, IN2: in BIT; OUT1: out BIT );
+  end component;
+  signal STUCKAT_HIGH: BIT := '1';
+begin
+  NAND_COMP: NAND_BOX port map ( GOING_IN, STUCKAT_HIGH, COMING_OUT );
+end ARC2;
+
+use WORK.CON1;
+configuration CON2 of ENT2 is
+  for ARC2
+    for NAND_COMP: NAND_BOX
+      use configuration CON1
+        port map ( IN1, IN2, OUT1 );
+    end for;
+  end for;
+end CON2;
+
+-- declare a test bench
+ENTITY c10s01b00x00p03n01i00878ent IS
+END c10s01b00x00p03n01i00878ent;
+
+use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
+ARCHITECTURE c10s01b00x00p03n01i00878arch OF c10s01b00x00p03n01i00878ent IS
+  component INV
+    port ( ENTRA: in BIT; SALE: out BIT );
+  end component;
+  signal SIGIN, SIGOUT: BIT;
+BEGIN
+  INVERTER: INV port map ( SIGIN, SIGOUT );
+  TESTING: PROCESS
+    variable   k : integer := 0;
+  BEGIN
+    SIGIN <= '0';
+    wait for ( 2 * UNIT_DELAY );
+    if (SIGOUT /= '1') then
+      k := 1;
+    end if;
+    assert ( SIGOUT = '1' )
+      report "didn't invert low to high" severity FAILURE;
+    wait for ( 3 * UNIT_DELAY );
+    SIGIN <= '1';
+    wait for ( 2 * UNIT_DELAY );
+    if (SIGOUT /= '0') then
+      k := 1;
+    end if;
+    assert ( SIGOUT = '0' )
+      report "didn't invert high to low" severity FAILURE;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c10s01b00x00p03n01i00878"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c10s01b00x00p03n01i00878 - A declartive region is formed by the text of a configuration declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p03n01i00878arch;
+
+use WORK.CON2;
+configuration c10s01b00x00p03n01i00878cfg of c10s01b00x00p03n01i00878ent is
+  for c10s01b00x00p03n01i00878arch
+    for INVERTER: INV
+      use configuration CON2
+        port map ( ENTRA, SALE );
+    end for;
+  end for;
+end c10s01b00x00p03n01i00878cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc879.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc879.vhd
new file mode 100644
index 0000000..6c59318
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc879.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc879.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s01b00x00p04n01i00879pkg_a is
+  -- define a subtype to be used elsewhere
+  subtype EIGHTIES is INTEGER range 1980 to 1989;
+end c10s01b00x00p04n01i00879pkg_a;
+
+package c10s01b00x00p04n01i00879pkg_b is
+  use WORK.c10s01b00x00p04n01i00879pkg_a.EIGHTIES;
+  function INTO_EIGHTIES ( ARG: in INTEGER ) return EIGHTIES;
+end c10s01b00x00p04n01i00879pkg_b;
+
+package body c10s01b00x00p04n01i00879pkg_b is
+  -- map any integer into range 1980 : 1989 based on one's digit
+  function INTO_EIGHTIES ( ARG: in INTEGER ) return EIGHTIES is
+    variable RETVAL: EIGHTIES;
+  begin
+    RETVAL := ( ( abs ARG ) mod 10 ) + 1980;
+    return RETVAL;
+  end INTO_EIGHTIES;
+end c10s01b00x00p04n01i00879pkg_b;
+
+
+ENTITY c10s01b00x00p04n01i00879ent IS
+END c10s01b00x00p04n01i00879ent;
+
+use WORK.c10s01b00x00p04n01i00879pkg_a.all;
+use WORK.c10s01b00x00p04n01i00879pkg_b.all;
+ARCHITECTURE c10s01b00x00p04n01i00879arch OF c10s01b00x00p04n01i00879ent IS
+  signal THE_INPUT   : INTEGER;
+  signal THE_OUTPUT   : INTEGER;
+BEGIN
+  TESTING: PROCESS
+    variable   k : integer := 0;
+  BEGIN
+    for I in 120 to 149 loop
+      THE_INPUT    <= I;
+      THE_OUTPUT    <= INTO_EIGHTIES( I );
+      wait for 1 ns;
+      if ( THE_OUTPUT < 1980 or THE_OUTPUT > 1989 ) then
+        k := 1;
+      end if;
+      assert ( ( THE_OUTPUT >= 1980 ) and ( THE_OUTPUT <= 1989 ) )
+        report "output is out of range" 
+        severity FAILURE;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c10s01b00x00p04n01i00879"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c10s01b00x00p04n01i00879 - Declaration is formed by the subprogram declaration together with the corresponding subprogram body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p04n01i00879arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc88.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc88.vhd
new file mode 100644
index 0000000..674ab72
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc88.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc88.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p05n02i00088ent IS
+END c04s03b01x03p05n02i00088ent;
+
+ARCHITECTURE c04s03b01x03p05n02i00088arch OF c04s03b01x03p05n02i00088ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        a : bit;
+        b : character;
+        c : boolean;
+      end record;
+    variable x : rec_type ;
+  BEGIN
+
+    assert NOT( x.a = '0' and x.b = Nul and x.c = false ) 
+      report "***PASSED TEST:c04s03b01x03p05n02i00088"
+      severity NOTE;
+    assert ( x.a = '0' and x.b = Nul and x.c = false ) 
+      report "***FAILED TEST:c04s03b01x03p05n02i00088 - Variable default assignment failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x03p05n02i00088arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc880.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc880.vhd
new file mode 100644
index 0000000..a73930e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc880.vhd
@@ -0,0 +1,117 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc880.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s01b00x00p05n01i00880pkg_1 is
+  subtype LOWERCASE is CHARACTER range 'a' to 'z';
+end c10s01b00x00p05n01i00880pkg_1;
+
+use WORK.c10s01b00x00p05n01i00880pkg_1.LOWERCASE;
+package c10s01b00x00p05n01i00880pkg_2 is
+  function ISLOWER ( TESTCHAR: in CHARACTER ) return BOOLEAN;
+end c10s01b00x00p05n01i00880pkg_2;
+
+package body c10s01b00x00p05n01i00880pkg_2 is
+  function ISLOWER ( TESTCHAR: in CHARACTER ) return BOOLEAN is
+  begin
+    if ( ( TESTCHAR >= LOWERCASE'LOW ) and ( TESTCHAR <= LOWERCASE'HIGH )) then
+      return TRUE;
+    else
+      return FALSE;
+    end if;
+  end ISLOWER;
+end c10s01b00x00p05n01i00880pkg_2;
+
+ENTITY c10s01b00x00p05n01i00880ent IS
+END c10s01b00x00p05n01i00880ent;
+
+-- run through all values of character
+-- and post high if lowercase, low otherwise.  also, if is lowercase,
+-- place value on small_letter.
+use WORK.c10s01b00x00p05n01i00880pkg_1.LOWERCASE;
+use WORK.c10s01b00x00p05n01i00880pkg_2.all;
+ARCHITECTURE c10s01b00x00p05n01i00880arch OF c10s01b00x00p05n01i00880ent IS
+  signal LOWER_TRUTH : BIT := '0';
+  signal SMALL_LETTER: LOWERCASE;
+  signal TEST_LETTER : CHARACTER;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+
+    for CHAR_AT_HAND in CHARACTER'LOW to CHARACTER'HIGH loop
+      -- do the work
+      TEST_LETTER    <= CHAR_AT_HAND;
+      if ISLOWER( CHAR_AT_HAND ) then
+        LOWER_TRUTH    <= '1';
+        SMALL_LETTER    <= CHAR_AT_HAND;
+      else
+        LOWER_TRUTH    <= '0';
+      end if;
+      wait for 1 ns;
+      -- make sure it happened
+      if ( ( CHAR_AT_HAND >= LOWERCASE'LOW ) and ( CHAR_AT_HAND <= LOWERCASE'HIGH ) ) then
+        if (ISLOWER(CHAR_AT_HAND) = false) then
+          k := 1;
+        end if;
+        assert ( ISLOWER( CHAR_AT_HAND ) )
+          report "ISLOWER is wrong"
+          severity FAILURE;
+        if (LOWER_TRUTH /= '1') then
+          k := 1;
+        end if;
+        assert ( LOWER_TRUTH = '1' )
+          report "LOWER_TRUTH is wrong"
+          severity FAILURE;
+        if (CHAR_AT_HAND /= SMALL_LETTER) then
+          k := 1;
+        end if;
+        assert ( CHAR_AT_HAND = SMALL_LETTER )
+          report "SMALL_LETTER is wrong"
+          severity FAILURE;
+      else
+        if (LOWER_TRUTH /= '0') then
+          k := 1;
+        end if;
+        assert ( LOWER_TRUTH = '0' )
+          report "LOWER_TRUTH is wrong"
+          severity FAILURE;
+      end if;
+    end loop;
+
+    assert NOT( k=0 )
+      report "***PASSED TEST: c10s01b00x00p05n01i00880"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c10s01b00x00p05n01i00880 - A declaration region is formed by a package declaration together with the corresponding body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p05n01i00880arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc881.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc881.vhd
new file mode 100644
index 0000000..20d955f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc881.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc881.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s01b00x00p06n01i00881PKG is
+-- VAL1 is here a constant
+  constant VAL1 : INTEGER := 65;
+  type DBLINTREC is
+    record
+-- VAL1 is here a record element
+      VAL1  : INTEGER;
+      VAL2  : INTEGER;
+    end record;
+end c10s01b00x00p06n01i00881PKG;
+
+
+use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC;
+entity c10s01b00x00p06n01i00881ent_a is
+  port (
+    PS1: in  DBLINTREC;
+    PS2: out DBLINTREC
+    );
+end c10s01b00x00p06n01i00881ent_a;
+
+architecture c10s01b00x00p06n01i00881arch_a of c10s01b00x00p06n01i00881ent_a is
+begin
+  process
+  begin
+    PS2.VAL1 <= PS1.VAL1 + 1;
+    PS2.VAL2 <= PS1.VAL2 + 2;
+    wait;
+  end process;
+end c10s01b00x00p06n01i00881arch_a;
+
+use WORK.c10s01b00x00p06n01i00881PKG.DBLINTREC;
+use WORK.c10s01b00x00p06n01i00881ent_a;
+ENTITY c10s01b00x00p06n01i00881ent IS
+END c10s01b00x00p06n01i00881ent;
+
+ARCHITECTURE c10s01b00x00p06n01i00881arch OF c10s01b00x00p06n01i00881ent IS
+
+  component c10s01b00x00p06n01i00881ent_a
+    port ( PS1: in DBLINTREC; PS2: out DBLINTREC );
+  end component;
+  for A1: c10s01b00x00p06n01i00881ent_a
+    use entity work.c10s01b00x00p06n01i00881ent_a ( c10s01b00x00p06n01i00881arch_a );
+  signal S1: DBLINTREC := (3, 9);
+  signal S2: DBLINTREC := (0, 0);
+
+BEGIN
+  
+  A1: c10s01b00x00p06n01i00881ent_a port map ( S1, S2 );
+
+  TESTING: PROCESS
+  BEGIN
+
+    wait for 1 ns; -- let a time increment go by so init done
+    assert ( S2.VAL1 = 4 )
+      report "didn't add to record element S2.VAL1 correctly"
+      severity FAILURE;
+    assert ( S2.VAL2 = 11 )
+      report "didn't add to record element S2.VAL2 correctly"
+      severity FAILURE;
+
+    assert NOT( S2.VAL1 = 4 and S2.VAL2 =11 )
+      report "***PASSED TEST: c10s01b00x00p06n01i00881"
+      severity NOTE;
+    assert ( S2.VAL1 = 4 and S2.VAL2 =11 )
+      report "***FAILED TEST: c10s01b00x00p06n01i00881 - A declaratione region is formed by a record type declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p06n01i00881arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc883.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc883.vhd
new file mode 100644
index 0000000..573db95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc883.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc883.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s01b00x00p08n01i00883ent IS
+END c10s01b00x00p08n01i00883ent;
+
+ARCHITECTURE c10s01b00x00p08n01i00883arch OF c10s01b00x00p08n01i00883ent IS
+
+  signal S1   : INTEGER;
+  signal S2   : INTEGER;
+  signal GS1   : INTEGER;
+  signal GS2   : INTEGER;
+  signal PS1   : INTEGER;
+  signal PS2   : INTEGER;
+
+BEGIN
+
+  -- initialization block and process
+  ALIST1SUB:
+  block
+    generic (
+      GS1: INTEGER := 3;
+      GS2: INTEGER := 9
+      );
+    generic map ( 3, 9 );
+    port (
+      PS1: out INTEGER;
+      PS2: out INTEGER
+      );
+    port map ( S1, S2 );
+  begin
+    process
+    begin
+      PS1 <= GS1 + 1;
+      PS2 <= GS2 + 2;
+      wait;
+    end process; -- forever, initialization complete
+  end block ALIST1SUB;
+
+  -- verification process
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert NOT( S1=4 and S2=11 )
+      report "***PASSED TEST: c10s01b00x00p08n01i00883"
+      severity NOTE;
+    assert ( S1=4 and S2=11 )
+      report "***FAILED TEST: c10s01b00x00p08n01i00883 - A single declaration region is formed by the text of a block statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p08n01i00883arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc884.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc884.vhd
new file mode 100644
index 0000000..c46542f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc884.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc884.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s01b00x00p09n01i00884ent IS
+END c10s01b00x00p09n01i00884ent;
+
+ARCHITECTURE c10s01b00x00p09n01i00884arch OF c10s01b00x00p09n01i00884ent IS
+
+  constant GS1: INTEGER := 105;
+  constant GS2: INTEGER := 785;
+  signal PS1: INTEGER := 356;
+  signal PS2: INTEGER := 123;
+
+BEGIN
+  TESTING: PROCESS
+    constant GS1: INTEGER := 3;
+    constant GS2: INTEGER := 9;
+  BEGIN
+    PS1 <= GS1 + 1;
+    PS2 <= GS2 + 2;
+    wait on PS1, PS2;
+    assert NOT( PS1=4 and PS2=11 )
+      report "***PASSED TEST: c10s01b00x00p09n01i00884"
+      severity NOTE;
+    assert ( PS1=4 and PS2=11 )
+      report "***FAILED TEST: c10s01b00x00p09n01i00884 - A declaration region is formed by the text of a process statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p09n01i00884arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc885.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc885.vhd
new file mode 100644
index 0000000..9152a1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc885.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc885.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s01b00x00p10n01i00885ent IS
+END c10s01b00x00p10n01i00885ent;
+
+ARCHITECTURE c10s01b00x00p10n01i00885arch OF c10s01b00x00p10n01i00885ent IS
+  signal S: INTEGER := 356;
+BEGIN
+  TESTING: PROCESS
+    constant I: INTEGER := 105; -- loop parameter has same name
+    variable k: integer := 0;
+  BEGIN
+    -- assign process constant I to S
+    S <= I;
+    wait for 1 ns;
+    assert ( S = 105 )
+      report "constant not properly assigned to signal"
+      severity FAILURE;
+    -- loop parameter has same name as constant declared in process
+    for I in 1 to 5 loop
+      -- assign loop parameter I to S
+      S <= I;
+      wait for 1 ns;
+      if ((S<1) or (S>5)) then
+        k := 1;
+      end if;
+      assert ( ( S >= 1 ) and ( S <= 5 ) )
+        report "loop parameter not properly assigned to signal"
+        severity FAILURE;
+    end loop;
+    assert NOT( k=0 )
+      report "***PASSED TEST: c10s01b00x00p10n01i00885"
+      severity NOTE;
+    assert ( k=0 )
+      report "***FAILED TEST: c10s01b00x00p10n01i00885 - A declaration region is formed by the text of a loop statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p10n01i00885arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc886.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc886.vhd
new file mode 100644
index 0000000..d281808
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc886.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc886.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s01b00x00p11n01i00886pkg_a is
+  constant x : integer := 1;
+end c10s01b00x00p11n01i00886pkg_a;
+
+package c10s01b00x00p11n01i00886pkg_b is
+  constant x : integer := 1;
+end c10s01b00x00p11n01i00886pkg_b;
+
+
+entity c10s01b00x00p11n01i00886ent_a is
+  generic (    passed_value    : integer := 6; 
+               ignored_value    : integer := 0 );
+end c10s01b00x00p11n01i00886ent_a;
+
+architecture c10s01b00x00p11n01i00886arch_a of c10s01b00x00p11n01i00886ent_a is
+begin
+  TESTING:PROCESS
+  BEGIN
+    assert NOT( passed_value = 1)
+      report "***PASSED TEST: c10s01b00x00p11n01i00886"
+      severity NOTE;
+    assert ( passed_value = 1)
+      report "***FAILED TEST: c10s01b00x00p11n01i00886 - A block configuration test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s01b00x00p11n01i00886arch_a;
+
+configuration c10s01b00x00p11n01i00886cfg_a of c10s01b00x00p11n01i00886ent_a is
+  for c10s01b00x00p11n01i00886arch_a
+  end for;
+end c10s01b00x00p11n01i00886cfg_a;
+
+ENTITY c10s01b00x00p11n01i00886ent IS
+END c10s01b00x00p11n01i00886ent;
+
+ARCHITECTURE c10s01b00x00p11n01i00886arch OF c10s01b00x00p11n01i00886ent IS
+  component ic_socket
+    generic (dummy_value : integer := 2);
+  end component;
+BEGIN
+  instance : ic_socket;
+
+END c10s01b00x00p11n01i00886arch;
+
+configuration c10s01b00x00p11n01i00886cfg of c10s01b00x00p11n01i00886ent is
+  for c10s01b00x00p11n01i00886arch    -- block_specification
+    use work.c10s01b00x00p11n01i00886pkg_a.x;    -- creates a declarative item in this region
+    for instance : ic_socket use configuration work.c10s01b00x00p11n01i00886cfg_a
+                               generic map ( passed_value => x, ignored_value => dummy_value );
+    end for;
+  end for;
+end c10s01b00x00p11n01i00886cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc887.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc887.vhd
new file mode 100644
index 0000000..6ebb25c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc887.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc887.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p10n01i00887ent IS
+END c10s02b00x00p10n01i00887ent;
+
+ARCHITECTURE c10s02b00x00p10n01i00887arch OF c10s02b00x00p10n01i00887ent IS
+  function i_val ( a : integer ) return integer is
+  begin
+    return ( 2 * a );
+  end i_val;
+  signal i_sig : integer := 1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    i_sig <= i_val(i_sig) after 10 ns; -- declaration is visible.
+    wait for 11 ns;
+    assert NOT( i_sig = 2 )
+      report "***PASSED TEST: c10s02b00x00p10n01i00887"
+      severity NOTE;
+    assert ( i_sig = 2 )
+      report "***FAILED TEST: c10s02b00x00p10n01i00887 - The scope of the declaration extends to the end of the enclosing declaration when there is an absence of a separate subprogram declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p10n01i00887arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc888.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc888.vhd
new file mode 100644
index 0000000..d07c093
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc888.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc888.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p10n01i00888ent IS
+END c10s02b00x00p10n01i00888ent;
+
+ARCHITECTURE c10s02b00x00p10n01i00888arch OF c10s02b00x00p10n01i00888ent IS
+  procedure xyz ( a : integer; b : real ) is
+  begin
+    assert NOT( b = 2.0 * real(a) ) 
+      report "***PASSED TEST: c10s02b00x00p10n01i00888"
+      severity NOTE;
+    assert ( b = 2.0 * real(a) ) 
+      report "***FAILED TEST: c10s02b00x00p10n01i00888 - When in the absence of a separate subprogram declaration, the subprogram specification given in the subprogram body acts as the declaration." 
+      severity ERROR;
+  end xyz;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    xyz ( a => 20, b => 40.0 );
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p10n01i00888arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc889.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc889.vhd
new file mode 100644
index 0000000..5c84f60
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc889.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc889.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c10s02b00x00p12n01i00889pkg IS
+  CONSTANT zero : INTEGER := 0;
+END c10s02b00x00p12n01i00889pkg;
+
+
+USE WORK.c10s02b00x00p12n01i00889pkg.all;
+ENTITY c10s02b00x00p12n01i00889ent_a IS
+  GENERIC ( I : INTEGER );
+END c10s02b00x00p12n01i00889ent_a;
+
+
+ARCHITECTURE c10s02b00x00p12n01i00889arch_a OF c10s02b00x00p12n01i00889ent_a IS
+
+BEGIN
+  PROCESS
+  BEGIN
+    assert NOT( I=0 )
+      report "***PASSED TEST: c10s02b00x00p12n01i00889"
+      severity NOTE;
+    assert ( I=0 )
+      report "***FAILED TEST: c10s02b00x00p12n01i00889"
+      severity ERROR;
+    wait;
+  END PROCESS;
+END;
+
+USE WORK.c10s02b00x00p12n01i00889pkg.all;
+ENTITY c10s02b00x00p12n01i00889ent IS
+END c10s02b00x00p12n01i00889ent;
+
+ARCHITECTURE c10s02b00x00p12n01i00889arch OF c10s02b00x00p12n01i00889ent IS
+
+  COMPONENT c10s02b00x00p12n01i00889ent_a
+  END COMPONENT;
+
+BEGIN
+  comp1 : c10s02b00x00p12n01i00889ent_a;
+
+END c10s02b00x00p12n01i00889arch;
+
+
+CONFIGURATION c10s02b00x00p12n01i00889cfg OF c10s02b00x00p12n01i00889ent IS
+  FOR c10s02b00x00p12n01i00889arch
+    FOR comp1 : c10s02b00x00p12n01i00889ent_a
+      USE ENTITY WORK.c10s02b00x00p12n01i00889ent_a(c10s02b00x00p12n01i00889arch_a) GENERIC MAP ( zero );
+    END FOR;
+  END FOR;
+END c10s02b00x00p12n01i00889cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc890.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc890.vhd
new file mode 100644
index 0000000..45617db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc890.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc890.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c10s02b00x00p02n01i00890pkg is
+  function gimme_value return integer;
+end c10s02b00x00p02n01i00890pkg;
+
+package body c10s02b00x00p02n01i00890pkg is
+  constant x : integer := 10;    -- should not be visible outside
+  function gimme_value return integer is
+    constant x : integer := 0;    -- should only be visible inside
+  begin
+    return (x);
+  end;
+end c10s02b00x00p02n01i00890pkg;
+
+use work.c10s02b00x00p02n01i00890pkg.all;
+ENTITY c10s02b00x00p02n01i00890ent IS
+END c10s02b00x00p02n01i00890ent;
+
+ARCHITECTURE c10s02b00x00p02n01i00890arch OF c10s02b00x00p02n01i00890ent IS
+  constant   x : integer := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( gimme_value = 0 )
+      report "***PASSED TEST: c10s02b00x00p02n01i00890"
+      severity NOTE;
+    assert ( gimme_value = 0 )
+      report "***FAILED TEST: c10s02b00x00p02n01i00890 - A declaration in a subprogram extends only within the subprogram body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n01i00890arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc891.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc891.vhd
new file mode 100644
index 0000000..852d467
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc891.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc891.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p02n02i00891ent IS
+END c10s02b00x00p02n02i00891ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00891arch OF c10s02b00x00p02n02i00891ent IS
+  type rec_typ is RECORD
+                    -- immediate scope
+                    r,g,b : real;
+                  end record;
+BEGIN
+  TESTING: PROCESS
+    -- extended scope
+    variable electron_gun : rec_typ := ( 0.25, 0.5, 1.0 );
+  BEGIN
+    assert NOT(   electron_gun.r   = 0.25   and
+                  electron_gun.g   = 0.5   and
+                  electron_gun.b   = 1.0   ) 
+      report "***PASSED TEST: c10s02b00x00p02n02i00891"
+      severity NOTE;
+    assert (   electron_gun.r   = 0.25   and
+               electron_gun.g   = 0.5   and
+               electron_gun.b   = 1.0   ) 
+      report "***FAILED TEST: c10s02b00x00p02n02i00891 - The scope of the declaration that occurs immediately within a record type declaration extends beyond the immediate scope"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n02i00891arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc892.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc892.vhd
new file mode 100644
index 0000000..d1201f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc892.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc892.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c10s02b00x00p02n01i00892pkg is
+  function gimme_value return integer;
+end c10s02b00x00p02n01i00892pkg;
+
+package body c10s02b00x00p02n01i00892pkg is
+  constant x : integer := 0; -- should not be visible outside
+  function gimme_value return integer is
+  begin
+    return (x);
+  end;
+end c10s02b00x00p02n01i00892pkg;
+
+
+use work.c10s02b00x00p02n01i00892pkg.all;
+ENTITY c10s02b00x00p02n01i00892ent IS
+END c10s02b00x00p02n01i00892ent;
+
+ARCHITECTURE c10s02b00x00p02n01i00892arch OF c10s02b00x00p02n01i00892ent IS
+  constant   x : integer := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( gimme_value = 0 )
+      report "***PASSED TEST: c10s02b00x00p02n01i00892"
+      severity NOTE;
+    assert ( gimme_value = 0 )
+      report "***FAILED TEST: c10s02b00x00p02n01i00892 - A declaration body extends only within the package body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n01i00892arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc893.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc893.vhd
new file mode 100644
index 0000000..b187c55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc893.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc893.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p02n01i00893ent IS
+END c10s02b00x00p02n01i00893ent;
+
+ARCHITECTURE c10s02b00x00p02n01i00893arch OF c10s02b00x00p02n01i00893ent IS
+  constant   x : integer := 5;
+BEGIN
+  TESTING: PROCESS
+
+    constant x : integer := 10;    -- should not be visible outside
+    function gimme_value return integer is
+    begin
+      return (x);
+    end;
+
+  BEGIN
+    assert NOT( gimme_value = 10 )
+      report "***PASSED TEST: c10s02b00x00p02n01i00893"
+      severity NOTE;
+    assert ( gimme_value = 10 )
+      report "***FAILED TEST: c10s02b00x00p02n01i00893 - A declaration in a process extends only within the process body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n01i00893arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc894.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc894.vhd
new file mode 100644
index 0000000..4b9d1c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc894.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc894.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+Package c10s02b00x00p02n02i00894pkg is
+  -- immediate scope area
+  constant local : integer := 10;
+  function gimme_value return integer;
+end c10s02b00x00p02n02i00894pkg;
+
+Package body c10s02b00x00p02n02i00894pkg is
+  -- extended scope area
+  function gimme_value return integer is
+  begin
+    return (local);
+  end gimme_value;
+end c10s02b00x00p02n02i00894pkg;
+
+ENTITY c10s02b00x00p02n02i00894ent IS
+END c10s02b00x00p02n02i00894ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00894arch OF c10s02b00x00p02n02i00894ent IS
+  use work.c10s02b00x00p02n02i00894pkg.all;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( gimme_value = 10 )
+      report "***PASSED TEST: c10s02b00x00p02n02i00894"
+      severity NOTE;
+    assert ( gimme_value = 10 )
+      report "***FAILED TEST: c10s02b00x00p02n02i00894 - The scope of the declaration that occurs immediately within a package declaration extends beyond the immediate scope"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n02i00894arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc895.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc895.vhd
new file mode 100644
index 0000000..800054e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc895.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc895.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p02n02i00895ent IS
+  procedure xyz  ( a : integer; b : real );
+  procedure xyz ( a : integer; b : real ) is
+  begin
+    assert NOT( b = 2.0 * real(a) )   
+      report "***PASSED TEST: c10s02b00x00p02n02i00895"
+      severity NOTE;
+    assert ( b = 2.0 * real(a) )   
+      report "***FAILED TEST: c10s02b00x00p02n02i00895 - The scope of the declaration that occurs immediately within a formal parameter declaration extends beyond the immediate scope."
+      severity ERROR;
+  end xyz;
+END c10s02b00x00p02n02i00895ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00895arch OF c10s02b00x00p02n02i00895ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    xyz ( a => 20, b => 40.0 ); -- extended scope for the formals
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n02i00895arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc896.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc896.vhd
new file mode 100644
index 0000000..fae11c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc896.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc896.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p02n02i00896ent IS
+  generic ( x : integer := 2 );
+END c10s02b00x00p02n02i00896ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00896arch OF c10s02b00x00p02n02i00896ent IS
+
+BEGIN
+  -- extended use of declared generic.
+  assert NOT( x = 2 )
+    report "***PASSED TEST: c10s02b00x00p02n02i00896"
+    severity NOTE;
+  assert ( x = 2 )
+    report "***FAILED TEST: c10s02b00x00p02n02i00896 - The scope of the declaration that occurs immediately within a formal generic declaration extends beyond the immediate scope."
+    severity ERROR;
+
+END c10s02b00x00p02n02i00896arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc897.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc897.vhd
new file mode 100644
index 0000000..2dda296
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc897.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc897.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s02b00x00p02n02i00897ent IS
+  port ( x : integer := 2 );
+END c10s02b00x00p02n02i00897ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00897arch OF c10s02b00x00p02n02i00897ent IS
+
+BEGIN
+  -- extended use of declared generic.
+  assert NOT( x = 2 )
+    report "***PASSED TEST: c10s02b00x00p02n02i00897"
+    severity NOTE;
+  assert ( x = 2 )
+    report "***FAILED TEST: c10s02b00x00p02n02i00897 - The scope of the declaration that occurs immediately within a formal port declaration in an entity declaration extends beyond the immediate scope."
+    severity ERROR;
+
+END c10s02b00x00p02n02i00897arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc898.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc898.vhd
new file mode 100644
index 0000000..d95bdd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc898.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc898.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s02b00x00p02n02i00898ent_a is
+  generic ( g : integer := 1 );
+end c10s02b00x00p02n02i00898ent_a;
+
+architecture c10s02b00x00p02n02i00898arch_a of c10s02b00x00p02n02i00898ent_a is
+begin
+  assert NOT( g = 6 )
+    report "***PASSED TEST: c10s02b00x00p02n02i00898"
+    severity NOTE;
+  assert ( g = 6 )
+    report "***FAILED TEST: c10s02b00x00p02n02i00898 - Wrong generic value." 
+    severity ERROR;
+end c10s02b00x00p02n02i00898arch_a;
+
+
+ENTITY c10s02b00x00p02n02i00898ent IS
+END c10s02b00x00p02n02i00898ent;
+
+ARCHITECTURE c10s02b00x00p02n02i00898arch OF c10s02b00x00p02n02i00898ent IS
+  component ic_socket
+    generic ( g : integer := 5 ); -- locally declared
+  end component;
+  for instance : ic_socket use entity work.c10s02b00x00p02n02i00898ent_a(c10s02b00x00p02n02i00898arch_a);
+BEGIN
+  instance : ic_socket generic map ( 6 );
+  TESTING: PROCESS
+  BEGIN
+    wait;
+  END PROCESS TESTING;
+
+END c10s02b00x00p02n02i00898arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc90.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc90.vhd
new file mode 100644
index 0000000..bbf9afe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc90.vhd
@@ -0,0 +1,195 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc90.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p01n01i00090ent IS
+END c04s03b02x00p01n01i00090ent;
+
+ARCHITECTURE c04s03b02x00p01n01i00090arch OF c04s03b02x00p01n01i00090ent IS
+
+  Procedure Variable_params_of_subp (
+    VARIABLE  cp1  : in      Boolean        := FALSE;
+    VARIABLE  cp2  : in      Bit            := '0';
+    VARIABLE  cp3  : in      Character      := '$';
+    VARIABLE  cp4  : in      SEVERITY_LEVEL := FAILURE;
+    VARIABLE  cp5  : in      Integer        := 5 + 6 ;
+    VARIABLE  cp6  : in      Real           := 2.45 ;
+    VARIABLE  cp7  : in      TIME           := 0 fs;
+    VARIABLE  cp8  : in      Natural        := 10;
+    VARIABLE  cp9  : in      Positive       := 99;
+    --
+    VARIABLE  cp12 : out     Boolean        ;
+    VARIABLE  cp13 : out     Bit            ;
+    VARIABLE  cp14 : out     Character      ;
+    VARIABLE  cp15 : out     SEVERITY_LEVEL ;
+    VARIABLE  cp16 : out     Integer        ;
+    VARIABLE  cp17 : out     Real           ;
+    VARIABLE  cp18 : out     TIME           ;
+    VARIABLE  cp19 : out     Natural        ;
+    VARIABLE  cp20 : out     Positive       ;
+    --
+    VARIABLE  cp23 : inout   Boolean        ;
+    VARIABLE  cp24 : inout   Bit            ;
+    VARIABLE  cp25 : inout   Character      ;
+    VARIABLE  cp26 : inout   SEVERITY_LEVEL ;
+    VARIABLE  cp27 : inout   Integer        ;
+    VARIABLE  cp28 : inout   Real           ;
+    VARIABLE  cp29 : inout   TIME           ;
+    VARIABLE  cp30 : inout   Natural        ;
+    VARIABLE  cp31 : inout   Positive
+    ) is
+  begin
+    -- assign ins to outs
+    cp12 := cp1   ;
+    cp13 := cp2   ;
+    cp14 := cp3   ;
+    cp15 := cp4   ;
+    cp16 := cp5   ;
+    cp17 := cp6   ;
+    cp18 := cp7   ;
+    cp19 := cp8   ;
+    cp20 := cp9   ;
+    
+    -- assign ins to inouts
+    cp23 := cp1   ;
+    cp24 := cp2   ;
+    cp25 := cp3   ;
+    cp26 := cp4   ;
+    cp27 := cp5   ;
+    cp28 := cp6   ;
+    cp29 := cp7   ;
+    cp30 := cp8   ;
+    cp31 := cp9   ;
+    
+  end Variable_params_of_subp;
+  
+BEGIN
+  TESTING: PROCESS
+    VARIABLE    v1  :    Boolean        := false;
+    VARIABLE    v2  :    Bit            := '1';
+    VARIABLE    v3  :    Character      := '%';
+    VARIABLE    v4  :    SEVERITY_LEVEL := NOTE;
+    VARIABLE    v5  :    Integer        := 22121;
+    VARIABLE    v6  :    Real           := 2.545;
+    VARIABLE    v7  :    TIME           := 12 ns;
+    VARIABLE    v8  :    Natural        := 90;
+    VARIABLE    v9  :    Positive       := 101;
+    
+    VARIABLE    v12 :  Boolean        ;
+    VARIABLE    v13 :  Bit            ;
+    VARIABLE    v14 :  Character      ;
+    VARIABLE    v15 :  SEVERITY_LEVEL ;
+    VARIABLE    v16 :  Integer        ;
+    VARIABLE    v17 :  Real           ;
+    VARIABLE    v18 :  TIME           ;
+    VARIABLE    v19 :  Natural        ;
+    VARIABLE    v20 :  Positive       ;
+    
+    VARIABLE    v23 :  Boolean        ;
+    VARIABLE    v24 :  Bit            ;
+    VARIABLE    v25 :  Character      ;
+    VARIABLE    v26 :  SEVERITY_LEVEL ;
+    VARIABLE    v27 :  Integer        ;
+    VARIABLE    v28 :  Real           ;
+    VARIABLE    v29 :  TIME           ;
+    VARIABLE    v30 :  Natural        ;
+    VARIABLE    v31 :  Positive       ;
+
+  BEGIN
+
+    Variable_params_of_subp ( v1,v2,v3,v4,v5,v6,v7,v8,v9,
+                              v12,v13,v14,v15,v16,v17,v18,v19,v20,
+                              v23,v24,v25,v26,v27,v28,v29,v30,v31
+                              );
+
+    assert   v12 = v1 report "  v12 /= v1" severity failure;
+    assert   v13 = v2 report "  v13 /= v2" severity failure;
+    assert   v14 = v3 report "  v14 /= v3" severity failure;
+    assert   v15 = v4 report "  v15 /= v4" severity failure;
+    assert   v16 = v5 report "  v16 /= v5" severity failure;
+    assert   v17 = v6 report "  v17 /= v6" severity failure;
+    assert   v18 = v7 report "  v18 /= v7" severity failure;
+    assert   v19 = v8 report "  v19 /= v8" severity failure;
+    assert   v20 = v9 report "  v20 /= v9" severity failure;
+    
+    assert   v23 = v1 report "  v23 /= v1" severity failure;
+    assert   v24 = v2 report "  v24 /= v2" severity failure;
+    assert   v25 = v3 report "  v25 /= v3" severity failure;
+    assert   v26 = v4 report "  v26 /= v4" severity failure;
+    assert   v27 = v5 report "  v27 /= v5" severity failure;
+    assert   v28 = v6 report "  v28 /= v6" severity failure;
+    assert   v29 = v7 report "  v29 /= v7" severity failure;
+    assert   v30 = v8 report "  v30 /= v8" severity failure;
+    assert   v31 = v9 report "  v31 /= v9" severity failure;
+    WAIT for 1 ns;
+
+    assert NOT(       v12 = v1    and
+                      v13 = v2    and
+                      v14 = v3    and
+                      v15 = v4    and
+                      v16 = v5    and
+                      v17 = v6    and
+                      v18 = v7    and
+                      v19 = v8    and
+                      v20 = v9    and
+                      v23 = v1    and
+                      v24 = v2    and
+                      v25 = v3    and
+                      v26 = v4    and
+                      v27 = v5    and
+                      v28 = v6    and
+                      v29 = v7    and
+                      v30 = v8    and
+                      v31 = v9    )   
+      report "***PASSED TEST:c04s03b02x00p01n01i00090"
+      severity NOTE;
+    assert (            v12 = v1    and
+                        v13 = v2    and
+                        v14 = v3    and
+                        v15 = v4    and
+                        v16 = v5    and
+                        v17 = v6    and
+                        v18 = v7    and
+                        v19 = v8    and
+                        v20 = v9    and
+                        v23 = v1    and
+                        v24 = v2    and
+                        v25 = v3    and
+                        v26 = v4    and
+                        v27 = v5    and
+                        v28 = v6    and
+                        v29 = v7    and
+                        v30 = v8    and
+                        v31 = v9    )   
+      report "***FAILED TEST: c04s03b02x00p01n01i00090 - Variables as the interface objects that appear as variable parameters of subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p01n01i00090arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc900.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc900.vhd
new file mode 100644
index 0000000..5afadc7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc900.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc900.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p04n01i00900pkg_1 is
+  type MVL1 is (LOW,HIGH,RISING);
+  type MVL2 is (LOW,HIGH,RISING,FALLING,AMBIGUOUS);
+end c10s03b00x00p04n01i00900pkg_1;
+
+use work.c10s03b00x00p04n01i00900pkg_1.all;
+ENTITY c10s03b00x00p04n01i00900ent IS
+END c10s03b00x00p04n01i00900ent;
+
+ARCHITECTURE c10s03b00x00p04n01i00900arch OF c10s03b00x00p04n01i00900ent IS
+  signal S1 : MVL2;
+  signal S2 : MVL2;
+  signal S3 : MVL2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= LOW;           -- No_failure_here
+    S2 <= HIGH;        -- No_failure_here
+    S3 <= RISING;        -- No_failure_here
+    wait for 5 ns;
+    assert NOT(S1 = LOW and S2 = HIGH and S3 = RISING)
+      report "***PASSED TEST: c10s03b00x00p04n01i00900" 
+      severity NOTE;
+    assert (S1 = LOW and S2 = HIGH and S3 = RISING)
+      report "***FAILED TEST: c10s03b00x00p04n01i00900 - The occurence of the identifier is legal if and only if exactly one visible declaration is acceptable for the overloading rules in the given context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p04n01i00900arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc902.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc902.vhd
new file mode 100644
index 0000000..8f44c3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc902.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc902.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p05n01i00902ent IS
+  type work is (foo,bar); -- No_Failure_here
+END c10s03b00x00p05n01i00902ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00902arch OF c10s03b00x00p05n01i00902ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable var : work := foo;
+  BEGIN
+    wait for 5 ns;
+    assert NOT( var = foo )
+      report "***PASSED TEST: c10s03b00x00p05n01i00902"
+      severity NOTE;
+    assert ( var = foo )
+      report "***FAILED TEST: c10s03b00x00p05n01i00902 - The declaration should be visible in the architecture."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00902arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc91.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc91.vhd
new file mode 100644
index 0000000..00b9aae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc91.vhd
@@ -0,0 +1,300 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc91.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c04s03b02x00p01n01i00091pkg IS
+--
+--
+--          Declaration of composite types
+--           - array types and subtypes
+--
+  TYPE    ut_chary    IS ARRAY (CHARACTER RANGE <>) OF INTEGER;      --unconstrained array type
+
+  TYPE    ct_word     IS ARRAY (0 TO 15)            OF BIT;          --constrained array type
+
+  SUBTYPE ust_subchary IS ut_chary;                                  --unconstrained array subtype
+
+  SUBTYPE cst_str10    IS STRING    ( 1  TO 10 );                    --constrained array subtype
+
+  SUBTYPE cst_digit    IS ut_chary  ('0' TO '9');                    --constrained array subtype
+
+--
+--          Declaration of composite types
+--           - records types and subtypes
+--
+  TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+
+  TYPE rt_date IS
+    RECORD
+      day   : INTEGER RANGE 0 TO 31;
+      month : month_name;
+      year  : INTEGER RANGE 0 TO 4000;
+    END RECORD;
+--
+  SUBTYPE rst_date IS rt_date;
+
+END c04s03b02x00p01n01i00091pkg;
+
+
+USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
+ENTITY c04s03b02x00p01n01i00091ent_a IS
+  PORT (
+    SIGNAL     STRING_prt : IN     STRING (1 TO 7);
+    SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
+    SIGNAL   ut_chary_prt : IN   ut_chary (NUL TO ENQ);
+    SIGNAL    ct_word_prt : IN    ct_word;
+    SIGNAL  cst_str10_prt : IN  cst_str10;
+    SIGNAL  cst_digit_prt : IN  cst_digit;
+    SIGNAL    rt_date_prt : IN    rt_date;
+    SIGNAL   rst_date_prt : IN   rst_date
+    );
+END c04s03b02x00p01n01i00091ent_a;
+
+
+
+ARCHITECTURE c04s03b02x00p01n01i00091arch_a OF c04s03b02x00p01n01i00091ent_a IS
+
+BEGIN
+  PROCESS
+  BEGIN
+--
+    FOR I IN 1 TO 7
+    LOOP
+      ASSERT STRING_prt(I) = NUL REPORT "STRING_prt not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR I IN 0 TO 7
+    LOOP
+      ASSERT BIT_VECTOR_prt(I) = '0' REPORT "BIT_VECTOR_prt not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR I IN NUL TO ENQ
+    LOOP
+      ASSERT ut_chary_prt(I) = INTEGER'LEFT
+        REPORT "ut_chary_prt not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR I IN 0 TO 15
+    LOOP
+      ASSERT ct_word_prt(I) = '0' REPORT "ct_word_prt not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    FOR I IN 1 TO 10
+    LOOP
+      ASSERT cst_str10_prt(I) = NUL REPORT "cst_str10_prt not properly intialized" SEVERITY FAILURE;
+    END LOOP;
+    
+    FOR I IN '0' TO '9'
+    LOOP
+      ASSERT cst_digit_prt(I) = INTEGER'LEFT
+        REPORT "cst_digit_prt not properly intialized" SEVERITY FAILURE;      END LOOP;
+    
+    ASSERT  rt_date_prt.day   = 0    REPORT " rt_date_prt.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_prt.month = Jan  REPORT " rt_date_prt.month not properly intialized" SEVERITY FAILURE;
+    ASSERT  rt_date_prt.year  = 0    REPORT " rt_date_prt.year  not properly intialized" SEVERITY FAILURE;
+    
+    ASSERT rst_date_prt.day   = 0    REPORT "rst_date_prt.day   not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_prt.month = Jan  REPORT "rst_date_prt.month not properly intialized" SEVERITY FAILURE;
+    ASSERT rst_date_prt.year  = 0    REPORT "rst_date_prt.year  not properly intialized" SEVERITY FAILURE;
+    
+    
+    assert NOT(   STRING_prt(1)      = NUL   and
+                  STRING_prt(2)      = NUL   and   
+                  STRING_prt(3)      = NUL   and   
+                  STRING_prt(4)      = NUL   and   
+                  STRING_prt(5)      = NUL   and   
+                  STRING_prt(6)      = NUL   and   
+                  STRING_prt(7)      = NUL   and   
+                  BIT_VECTOR_prt(1)   = '0'   and
+                  BIT_VECTOR_prt(2)   = '0'   and
+                  BIT_VECTOR_prt(3)   = '0'   and
+                  BIT_VECTOR_prt(4)   = '0'   and
+                  BIT_VECTOR_prt(5)   = '0'   and
+                  BIT_VECTOR_prt(6)   = '0'   and
+                  BIT_VECTOR_prt(7)   = '0'   and
+                  ut_chary_prt(NUL)   = integer'left   and
+                  ut_chary_prt(SOH)   = integer'left   and
+                  ut_chary_prt(STX)   = integer'left   and
+                  ut_chary_prt(ETX)   = integer'left   and
+                  ut_chary_prt(EOT)   = integer'left   and
+                  ut_chary_prt(ENQ)   = integer'left   and
+                  ct_word_prt( 0)      = '0'   and
+                  ct_word_prt( 1)      = '0'   and
+                  ct_word_prt( 2)      = '0'   and
+                  ct_word_prt( 3)      = '0'   and
+                  ct_word_prt( 4)      = '0'   and
+                  ct_word_prt( 5)      = '0'   and
+                  ct_word_prt( 6)      = '0'   and
+                  ct_word_prt( 7)      = '0'   and
+                  ct_word_prt( 8)      = '0'   and
+                  ct_word_prt( 9)      = '0'   and
+                  ct_word_prt(10)      = '0'   and
+                  ct_word_prt(11)      = '0'   and
+                  ct_word_prt(12)      = '0'   and
+                  ct_word_prt(13)      = '0'   and
+                  ct_word_prt(14)      = '0'   and
+                  ct_word_prt(15)      = '0'   and
+                  cst_str10_prt( 1)   = NUL   and
+                  cst_str10_prt( 2)   = NUL   and
+                  cst_str10_prt( 3)   = NUL   and
+                  cst_str10_prt( 4)   = NUL   and
+                  cst_str10_prt( 5)   = NUL   and
+                  cst_str10_prt( 6)   = NUL   and
+                  cst_str10_prt( 7)   = NUL   and
+                  cst_str10_prt( 8)   = NUL   and
+                  cst_str10_prt( 9)   = NUL   and
+                  cst_str10_prt(10)   = NUL   and
+                  cst_digit_prt('0')   = integer'left   and
+                  cst_digit_prt('1')   = integer'left   and
+                  cst_digit_prt('2')   = integer'left   and
+                  cst_digit_prt('3')   = integer'left   and
+                  cst_digit_prt('4')   = integer'left   and
+                  cst_digit_prt('5')   = integer'left   and
+                  cst_digit_prt('6')   = integer'left   and
+                  cst_digit_prt('7')   = integer'left   and
+                  cst_digit_prt('8')   = integer'left   and
+                  cst_digit_prt('9')   = integer'left   and
+                  rt_date_prt.day      = 0   and
+                  rt_date_prt.month   = Jan   and
+                  rt_date_prt.year   = 0   and
+                  rst_date_prt.day   = 0   and
+                  rst_date_prt.month   = Jan   and
+                  rst_date_prt.year   = 0   )
+      report "***PASSED TEST: c04s03b02x00p01n01i00091"
+      severity NOTE;
+    assert (   STRING_prt(1)      = NUL   and
+               STRING_prt(2)      = NUL   and   
+               STRING_prt(3)      = NUL   and   
+               STRING_prt(4)      = NUL   and   
+               STRING_prt(5)      = NUL   and   
+               STRING_prt(6)      = NUL   and   
+               STRING_prt(7)      = NUL   and   
+               BIT_VECTOR_prt(1)   = '0'   and
+               BIT_VECTOR_prt(2)   = '0'   and
+               BIT_VECTOR_prt(3)   = '0'   and
+               BIT_VECTOR_prt(4)   = '0'   and
+               BIT_VECTOR_prt(5)   = '0'   and
+               BIT_VECTOR_prt(6)   = '0'   and
+               BIT_VECTOR_prt(7)   = '0'   and
+               ut_chary_prt(NUL)   = integer'left   and
+               ut_chary_prt(SOH)   = integer'left   and
+               ut_chary_prt(STX)   = integer'left   and
+               ut_chary_prt(ETX)   = integer'left   and
+               ut_chary_prt(EOT)   = integer'left   and
+               ut_chary_prt(ENQ)   = integer'left   and
+               ct_word_prt( 0)      = '0'   and
+               ct_word_prt( 1)      = '0'   and
+               ct_word_prt( 2)      = '0'   and
+               ct_word_prt( 3)      = '0'   and
+               ct_word_prt( 4)      = '0'   and
+               ct_word_prt( 5)      = '0'   and
+               ct_word_prt( 6)      = '0'   and
+               ct_word_prt( 7)      = '0'   and
+               ct_word_prt( 8)      = '0'   and
+               ct_word_prt( 9)      = '0'   and
+               ct_word_prt(10)      = '0'   and
+               ct_word_prt(11)      = '0'   and
+               ct_word_prt(12)      = '0'   and
+               ct_word_prt(13)      = '0'   and
+               ct_word_prt(14)      = '0'   and
+               ct_word_prt(15)      = '0'   and
+               cst_str10_prt( 1)   = NUL   and
+               cst_str10_prt( 2)   = NUL   and
+               cst_str10_prt( 3)   = NUL   and
+               cst_str10_prt( 4)   = NUL   and
+               cst_str10_prt( 5)   = NUL   and
+               cst_str10_prt( 6)   = NUL   and
+               cst_str10_prt( 7)   = NUL   and
+               cst_str10_prt( 8)   = NUL   and
+               cst_str10_prt( 9)   = NUL   and
+               cst_str10_prt(10)   = NUL   and
+               cst_digit_prt('0')   = integer'left   and
+               cst_digit_prt('1')   = integer'left   and
+               cst_digit_prt('2')   = integer'left   and
+               cst_digit_prt('3')   = integer'left   and
+               cst_digit_prt('4')   = integer'left   and
+               cst_digit_prt('5')   = integer'left   and
+               cst_digit_prt('6')   = integer'left   and
+               cst_digit_prt('7')   = integer'left   and
+               cst_digit_prt('8')   = integer'left   and
+               cst_digit_prt('9')   = integer'left   and
+               rt_date_prt.day      = 0   and
+               rt_date_prt.month   = Jan   and
+               rt_date_prt.year   = 0   and
+               rst_date_prt.day   = 0   and
+               rst_date_prt.month   = Jan   and
+               rst_date_prt.year   = 0   )
+      report "***FAILED TEST: c04s03b02x00p01n01i00091 - Variables as the interface objects that appear as variable parameters of subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS;
+
+END c04s03b02x00p01n01i00091arch_a;
+
+
+USE WORK.c04s03b02x00p01n01i00091pkg.ALL;
+ENTITY c04s03b02x00p01n01i00091ent IS
+END c04s03b02x00p01n01i00091ent;
+
+ARCHITECTURE c04s03b02x00p01n01i00091arch OF c04s03b02x00p01n01i00091ent IS
+  COMPONENT c04s03b02x00p01n01i00091ent_a
+    PORT (
+      SIGNAL     STRING_prt : IN     STRING (1 TO 7);
+      SIGNAL BIT_VECTOR_prt : IN BIT_VECTOR (0 TO 7);
+      SIGNAL   ut_chary_prt : IN   ut_chary (NUL TO ENQ);
+      SIGNAL    ct_word_prt : IN    ct_word;
+      SIGNAL  cst_str10_prt : IN  cst_str10;
+      SIGNAL  cst_digit_prt : IN  cst_digit;
+      SIGNAL    rt_date_prt : IN    rt_date;
+      SIGNAL   rst_date_prt : IN   rst_date
+      );
+  END COMPONENT;
+  for c : c04s03b02x00p01n01i00091ent_a use entity work.c04s03b02x00p01n01i00091ent_a(c04s03b02x00p01n01i00091arch_a);
+  
+  SIGNAL     STRING_prt :     STRING (1 TO 7);
+  SIGNAL BIT_VECTOR_prt : BIT_VECTOR (0 TO 7);
+  SIGNAL   ut_chary_prt :   ut_chary (NUL TO ENQ);
+  SIGNAL    ct_word_prt :    ct_word;
+  SIGNAL  cst_str10_prt :  cst_str10;
+  SIGNAL  cst_digit_prt :  cst_digit;
+  SIGNAL    rt_date_prt :    rt_date;
+  SIGNAL   rst_date_prt :   rst_date;
+  
+BEGIN
+  C : c04s03b02x00p01n01i00091ent_a
+    PORT MAP ( STRING_prt,
+               BIT_VECTOR_prt,
+               ut_chary_prt,
+               ct_word_prt,
+               cst_str10_prt,
+               cst_digit_prt,
+               rt_date_prt,
+               rst_date_prt );
+  
+
+END c04s03b02x00p01n01i00091arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc911.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc911.vhd
new file mode 100644
index 0000000..0c986d1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc911.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc911.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s03b00x00p07n01i00911ent_a is
+end c10s03b00x00p07n01i00911ent_a;
+
+architecture c10s03b00x00p07n01i00911arch_a of c10s03b00x00p07n01i00911ent_a is
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c10s03b00x00p07n01i00911"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+end c10s03b00x00p07n01i00911arch_a;
+
+
+ENTITY c10s03b00x00p07n01i00911ent IS
+END c10s03b00x00p07n01i00911ent;
+
+ARCHITECTURE c10s03b00x00p07n01i00911arch OF c10s03b00x00p07n01i00911ent IS
+  component device
+  end component;
+
+  -- selected use of configuration primary unit
+  for all : device use entity work.c10s03b00x00p07n01i00911ent_a(c10s03b00x00p07n01i00911arch_a);
+BEGIN
+  instance : device;
+END c10s03b00x00p07n01i00911arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc912.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc912.vhd
new file mode 100644
index 0000000..b4cec7c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc912.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc912.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p07n01i00912pkg is
+  constant x : integer := 2;
+end c10s03b00x00p07n01i00912pkg;
+
+ENTITY c10s03b00x00p07n01i00912ent IS
+END c10s03b00x00p07n01i00912ent;
+
+ARCHITECTURE c10s03b00x00p07n01i00912arch OF c10s03b00x00p07n01i00912ent IS
+  -- selected use of package element
+  use work.c10s03b00x00p07n01i00912pkg.x;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( x=2 )
+      report "***PASSED TEST: c10s03b00x00p07n01i00912"
+      severity NOTE;
+    assert ( x=2 )
+      report "***FAILED TEST: c10s03b00x00p07n01i00912 - A primary unit of a library can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p07n01i00912arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc913.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc913.vhd
new file mode 100644
index 0000000..65cde69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc913.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc913.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p07n01i00913pkg is
+  -- It is OK to define a type that overrides the name of a library
+  type work is (foo, bar);   -- No_failure_here
+end c10s03b00x00p07n01i00913pkg;
+
+use work.c10s03b00x00p07n01i00913pkg.all;
+ENTITY c10s03b00x00p07n01i00913ent IS
+END c10s03b00x00p07n01i00913ent;
+
+ARCHITECTURE c10s03b00x00p07n01i00913arch OF c10s03b00x00p07n01i00913ent IS
+
+BEGIN
+  TESTING : PROCESS
+    -- This succeeds in finding type "work" defined in package "c10s03b00x00p07n01i00913pkg"
+    -- in library "work"
+    variable doit : work.c10s03b00x00p07n01i00913pkg.work ;   -- No_failure_here
+  BEGIN
+    doit := foo;
+    wait for 5 ns;
+    assert NOT(doit = foo) 
+      report "***PASSED TEST: c10s03b00x00p07n01i00913"
+      severity NOTE;
+    assert (doit = foo) 
+      report "***FAILED TEST: c10s03b00x00p07n01i00913 - A declaration can be visible by selection for a primary unit contained in a library."
+      severity ERROR;
+    wait;
+  END PROCESS;
+
+END c10s03b00x00p07n01i00913arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc914.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc914.vhd
new file mode 100644
index 0000000..d55d618
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc914.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc914.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p07n01i00914pkg is
+  type c10s03b00x00p07n01i00914pkg is (a,b);
+end c10s03b00x00p07n01i00914pkg;
+
+use work.all;
+ENTITY c10s03b00x00p07n01i00914ent IS
+END c10s03b00x00p07n01i00914ent;
+
+ARCHITECTURE c10s03b00x00p07n01i00914arch OF c10s03b00x00p07n01i00914ent IS
+  signal S : c10s03b00x00p07n01i00914pkg.c10s03b00x00p07n01i00914pkg;
+BEGIN
+  TESTING: PROCESS
+    use work.c10s03b00x00p07n01i00914pkg.all;
+  BEGIN
+    S <= a after 5 ns;
+    wait for 10 ns;
+    assert NOT( S = a )
+      report "***PASSED TEST: c10s03b00x00p07n01i00914"
+      severity NOTE;
+    assert ( S = a )
+      report "***FAILED TEST: c10s03b00x00p07n01i00914 - A primary unit of a library can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p07n01i00914arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc915.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc915.vhd
new file mode 100644
index 0000000..6a3a283
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc915.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc915.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p08n01i00915ent IS
+END c10s03b00x00p08n01i00915ent;
+
+ARCHITECTURE c10s03b00x00p08n01i00915arch OF c10s03b00x00p08n01i00915ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c10s03b00x00p08n01i00915"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p08n01i00915arch;
+
+ARCHITECTURE c10s03b00x00p08n01i00915arch_a OF c10s03b00x00p08n01i00915ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c10s03b00x00p08n01i00915 - An architecture body of an entity can be visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p08n01i00915arch_a;
+
+configuration c10s03b00x00p08n01i00915cfg of c10s03b00x00p08n01i00915ent is
+  -- select the architecture you want.
+  for c10s03b00x00p08n01i00915arch
+  end for;
+end c10s03b00x00p08n01i00915cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc916.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc916.vhd
new file mode 100644
index 0000000..c572be2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc916.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc916.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p10n01i00916pkg is
+  constant x : integer := 2;
+end c10s03b00x00p10n01i00916pkg;
+
+ENTITY c10s03b00x00p10n01i00916ent IS
+END c10s03b00x00p10n01i00916ent;
+
+ARCHITECTURE c10s03b00x00p10n01i00916arch OF c10s03b00x00p10n01i00916ent IS
+
+  -- selected use of package element
+  use work.c10s03b00x00p10n01i00916pkg.x;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( x=2 )
+      report "***PASSED TEST: c10s03b00x00p10n01i00916"
+      severity NOTE;
+    assert ( x=2 )
+      report "***FAILED TEST: c10s03b00x00p10n01i00916 - A declaration ina package can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p10n01i00916arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc917.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc917.vhd
new file mode 100644
index 0000000..60e0ce3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc917.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc917.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c04s04b00x00p02n01i00917ent_a is
+  generic ( i_generic : integer; r_generic : real );
+end c04s04b00x00p02n01i00917ent_a;
+
+architecture c04s04b00x00p02n01i00917arch_a of c04s04b00x00p02n01i00917ent_a is
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert NOT( i_generic = 0 and r_generic = 15.0 )
+      report "***PASSED TEST: c04s04b00x00p02n01i00917"
+      severity NOTE;
+    assert ( i_generic = 0 and r_generic = 15.0 )
+      report "***FAILED TEST: c04s04b00x00p02n01i00917 - "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c04s04b00x00p02n01i00917arch_a;
+
+
+ENTITY c04s04b00x00p02n01i00917ent IS
+  subtype    register16    is bit_vector(15 downto 0);
+  constant    reg :    register16 := B"1001_0001_1010_1111";
+END c04s04b00x00p02n01i00917ent;
+
+ARCHITECTURE c04s04b00x00p02n01i00917arch OF c04s04b00x00p02n01i00917ent IS
+  component d
+    generic ( i_generic : integer := 1; r_generic : real := 2.0 );
+  end component;
+  for instance : d use entity work.c04s04b00x00p02n01i00917ent_a(c04s04b00x00p02n01i00917arch_a);
+BEGIN
+  instance : d generic map (reg'low, real(reg'high));
+  assert ( reg'low   = 0 )  report "reg'low   /= 0"  severity FAILURE;
+  assert ( reg'high  = 15 ) report "reg'high  /= 15" severity FAILURE;
+  assert ( reg'right = 0 )  report "reg'right /= 0"  severity FAILURE;
+  assert ( reg'left  = 15 ) report "reg'left  /= 15" severity FAILURE;
+
+END c04s04b00x00p02n01i00917arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc918.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc918.vhd
new file mode 100644
index 0000000..51c0cdc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc918.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc918.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p13n01i00918ent IS
+  procedure subprogram ( a : integer; b : real ) is
+  begin
+    assert ( b = real (a) ) report "not the same" severity FAILURE;
+    assert NOT( b = real(a) )
+      report "***PASSED TEST: c10s03b00x00p13n01i00918"
+      severity NOTE;
+    assert ( b = real(a) )
+      report "***FAILED TEST: c10s03b00x00p13n01i00918 - "
+      severity ERROR;
+  end subprogram;
+END c10s03b00x00p13n01i00918ent;
+
+ARCHITECTURE c10s03b00x00p13n01i00918arch OF c10s03b00x00p13n01i00918ent IS
+
+BEGIN
+  subprogram ( a => 10  , b => 10.0 );
+
+END c10s03b00x00p13n01i00918arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc919.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc919.vhd
new file mode 100644
index 0000000..8a35217
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc919.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc919.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s03b00x00p14n01i00919ent_a is
+  generic ( x : integer; y : real );
+end c10s03b00x00p14n01i00919ent_a;
+
+architecture c10s03b00x00p14n01i00919arch_a of c10s03b00x00p14n01i00919ent_a is
+begin
+  TESTING:PROCESS
+  BEGIN
+    assert NOT( real(x) = y )
+      report "***PASSED TEST: c10s03b00x00p14n01i00919"
+      severity NOTE;
+    assert ( real(x) = y )
+      report "***FAILED TEST: c10s03b00x00p14n01i00919 - The named associated local generics can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s03b00x00p14n01i00919arch_a;
+
+
+ENTITY c10s03b00x00p14n01i00919ent IS
+END c10s03b00x00p14n01i00919ent;
+
+ARCHITECTURE c10s03b00x00p14n01i00919arch OF c10s03b00x00p14n01i00919ent IS
+  component d
+    generic ( a : integer; b : real );
+  end component;
+BEGIN
+  instance : d generic map (a => 10, b => 10.0);
+
+END c10s03b00x00p14n01i00919arch;
+
+
+configuration c10s03b00x00p14n01i00919cfg of c10s03b00x00p14n01i00919ent is
+  for c10s03b00x00p14n01i00919arch
+    for instance : d
+      use entity work.c10s03b00x00p14n01i00919ent_a(c10s03b00x00p14n01i00919arch_a) generic map ( x => a, y => b);
+    end for;
+  end for;
+end c10s03b00x00p14n01i00919cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc920.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc920.vhd
new file mode 100644
index 0000000..f59dfaf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc920.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc920.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s03b00x00p15n01i00920ent_a is
+  port ( x : integer; y : real );
+end c10s03b00x00p15n01i00920ent_a;
+
+architecture c10s03b00x00p15n01i00920arch_a of c10s03b00x00p15n01i00920ent_a is
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert NOT( real(x) = y )
+      report "***PASSED TEST: c10s03b00x00p15n01i00920"
+      severity NOTE;
+    assert ( real(x) = y )
+      report "***FAILED TEST: c10s03b00x00p15n01i00920 - The named associated local ports can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s03b00x00p15n01i00920arch_a;
+
+ENTITY c10s03b00x00p15n01i00920ent IS
+END c10s03b00x00p15n01i00920ent;
+
+ARCHITECTURE c10s03b00x00p15n01i00920arch OF c10s03b00x00p15n01i00920ent IS
+  component d
+    port ( a : integer; b : real );
+  end component;
+  signal a : integer := 10;
+  signal b : real    := 10.0;
+BEGIN
+
+  instance : d port map ( a => a, b => b );
+
+END c10s03b00x00p15n01i00920arch;
+
+configuration c10s03b00x00p15n01i00920cfg of c10s03b00x00p15n01i00920ent is
+  for c10s03b00x00p15n01i00920arch
+    for instance : d
+      use entity work.c10s03b00x00p15n01i00920ent_a(c10s03b00x00p15n01i00920arch_a) port map ( x => a, y => b );
+    end for;
+  end for;
+end c10s03b00x00p15n01i00920cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc921.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc921.vhd
new file mode 100644
index 0000000..48ff8a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc921.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc921.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s03b00x00p16n01i00921ent_a is
+  generic ( x : integer; y : real );
+end c10s03b00x00p16n01i00921ent_a;
+
+architecture c10s03b00x00p16n01i00921arch_a of c10s03b00x00p16n01i00921ent_a is
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert NOT( real(x)=y )
+      report "***PASSED TEST: c10s03b00x00p16n01i00921"
+      severity NOTE;
+    assert ( real(x)=y )
+      report "***FAILED TEST: c10s03b00x00p16n01i00921 - Named associated formal generic can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s03b00x00p16n01i00921arch_a;
+
+ENTITY c10s03b00x00p16n01i00921ent IS
+END c10s03b00x00p16n01i00921ent;
+
+ARCHITECTURE c10s03b00x00p16n01i00921arch OF c10s03b00x00p16n01i00921ent IS
+  component d
+  end component;
+BEGIN
+  instance : d;
+
+END c10s03b00x00p16n01i00921arch;
+
+configuration c10s03b00x00p16n01i00921cfg of c10s03b00x00p16n01i00921ent is
+  for c10s03b00x00p16n01i00921arch
+    for instance : d
+      use entity work.c10s03b00x00p16n01i00921ent_a(c10s03b00x00p16n01i00921arch_a) generic map ( x => 10, y => 10.0 );
+    end for;
+  end for;
+end c10s03b00x00p16n01i00921cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc922.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc922.vhd
new file mode 100644
index 0000000..dc05393
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc922.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc922.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s03b00x00p17n01i00922ent_a is
+  port ( x : integer; y : real );
+end c10s03b00x00p17n01i00922ent_a;
+
+architecture c10s03b00x00p17n01i00922arch_a of c10s03b00x00p17n01i00922ent_a is
+begin
+  TESTING : PROCESS
+  BEGIN
+    assert NOT( real(x)=y )
+      report "***PASSED TEST: c10s03b00x00p17n01i00922"
+      severity NOTE;
+    assert ( real(x)=y )
+      report "***FAILED TEST: c10s03b00x00p17n01i00922 - Named formal ports can be made visible by selection."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s03b00x00p17n01i00922arch_a;
+
+ENTITY c10s03b00x00p17n01i00922ent IS
+END c10s03b00x00p17n01i00922ent;
+
+ARCHITECTURE c10s03b00x00p17n01i00922arch OF c10s03b00x00p17n01i00922ent IS
+  component d
+  end component;
+  signal a : integer := 10;
+  signal b : real    := 10.0;
+BEGIN
+  instance : d;
+
+END c10s03b00x00p17n01i00922arch;
+
+configuration c10s03b00x00p17n01i00922cfg of c10s03b00x00p17n01i00922ent is
+  for c10s03b00x00p17n01i00922arch
+    for instance : d
+      use entity work.c10s03b00x00p17n01i00922ent_a(c10s03b00x00p17n01i00922arch_a) port map ( x => a, y => b );
+    end for;
+  end for;
+end c10s03b00x00p17n01i00922cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc923.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc923.vhd
new file mode 100644
index 0000000..fc61724
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc923.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc923.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p19n01i00923ent IS
+  type primary is ( red, green, blue );
+END c10s03b00x00p19n01i00923ent;
+
+ARCHITECTURE c10s03b00x00p19n01i00923arch OF c10s03b00x00p19n01i00923ent IS
+
+  procedure xxx is
+    type    primary is ( red, green, blue );
+    constant x : c10s03b00x00p19n01i00923ent.primary := red;
+  begin
+    assert NOT( x=red )
+      report "***PASSED TEST: c10s03b00x00p19n01i00923"
+      severity NOTE;
+    assert ( x=red )
+      report "***FAILED TEST: c10s03b00x00p19n01i00923 - The declarations can be made visible by providing a prefix to the declaration to specify where it had been declared."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+END c10s03b00x00p19n01i00923arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc924.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc924.vhd
new file mode 100644
index 0000000..8b2c363
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc924.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc924.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p20n03i00924pkg is
+  type primary is ( red, green, blue );
+end c10s03b00x00p20n03i00924pkg;
+
+
+ENTITY c10s03b00x00p20n03i00924ent IS
+  type primary is ( yellow, pink, orange );
+END c10s03b00x00p20n03i00924ent;
+
+ARCHITECTURE c10s03b00x00p20n03i00924arch OF c10s03b00x00p20n03i00924ent IS
+  procedure xxx is
+    use    work.c10s03b00x00p20n03i00924pkg.all;
+    variable x : work.c10s03b00x00p20n03i00924pkg.primary;
+  begin
+    x := red;
+    assert NOT( x=red )
+      report "***PASSED TEST: c10s03b00x00p20n03i00924"
+      severity NOTE;
+    assert ( x=red )
+      report "***FAILED TEST: c10s03b00x00p20n03i00924 - A use clause can make a declaration visible and hide a local declaration."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+
+END c10s03b00x00p20n03i00924arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc925.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc925.vhd
new file mode 100644
index 0000000..97edf5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc925.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc925.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p22n01i00925ent IS
+END c10s03b00x00p22n01i00925ent;
+
+ARCHITECTURE c10s03b00x00p22n01i00925arch OF c10s03b00x00p22n01i00925ent IS
+  constant x : integer := 3;
+  procedure xxx is
+    constant x : integer := 5;
+    variable y : bit;
+  begin
+    if x > 3 then 
+      y := '1';
+    else 
+      y := '0';
+    end if;
+    assert NOT( y='1' )
+      report "***PASSED TEST: c10s03b00x00p22n01i00925"
+      severity NOTE;
+    assert ( y='1' )
+      report "***FAILED TEST: c10s03b00x00p22n01i00925 - Within the specification of a subprogram, every declaration with the same designator as the sybprogram is hidden."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+
+END c10s03b00x00p22n01i00925arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc926.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc926.vhd
new file mode 100644
index 0000000..86aa88b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc926.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc926.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p23n01i00926ent IS
+END c10s03b00x00p23n01i00926ent;
+
+ARCHITECTURE c10s03b00x00p23n01i00926arch OF c10s03b00x00p23n01i00926ent IS
+  type std_logic is ( 'X', '0', '1', 'W', 'L', 'H', 'Z' );
+  type std_logic_vector is array ( natural range <> ) of std_logic;
+
+  function "+" ( l,r : bit_vector ) return bit_vector is
+    variable lr : bit_vector ( 1 to l'length ) := l;
+    variable rr : bit_vector ( 1 to r'length ) := r;
+    variable result : bit_vector ( 1 to l'length );
+    variable carry : bit := '0';
+  begin
+    for i in l'length downto 1 loop
+      result(i) := lr(i) xor rr(i) xor carry;
+      carry := (lr(i) and rr(i)) or
+               (rr(i) and carry) or
+               (lr(i) and carry);
+    end loop;
+    return (result);
+  end;
+
+  -- homograph
+  function "+" ( l,r : std_logic_vector ) return std_logic_vector is
+  begin
+  end; 
+
+  signal a : bit_vector ( 15 downto 0 ) := B"0010001010100010";
+  signal b : bit_vector ( 15 downto 0 ) := B"0101111101011101";
+  signal s : bit_vector ( 15 downto 0 );
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    s <= (a + b) after 10 ns;
+    wait for 11 ns;
+    assert NOT( s = B"1000000111111111" )
+      report "***PASSED TEST: c10s03b00x00p23n01i00926"
+      severity NOTE;
+    assert ( s = B"1000000111111111" )
+      report "***FAILED TEST: c10s03b00x00p23n01i00926 - If one of the two declarations is the implicit declaration of a predefined operation, the predefined operation is laways hidden by teh other homograph."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p23n01i00926arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc927.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc927.vhd
new file mode 100644
index 0000000..00fb47c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc927.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc927.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p01n01i00927pkg is
+  type work is array(0 to 7) of BIT;
+end c10s04b00x00p01n01i00927pkg;
+
+use  work.c10s04b00x00p01n01i00927pkg.all;
+ENTITY c10s04b00x00p01n01i00927ent IS
+  port (P : in  bit);
+END c10s04b00x00p01n01i00927ent;
+
+ARCHITECTURE c10s04b00x00p01n01i00927arch OF c10s04b00x00p01n01i00927ent IS
+  use  work.c10s04b00x00p01n01i00927pkg;
+BEGIN
+  TESTING: PROCESS(P)
+    -- This succeeds because type work is defined in package c10s04b00x00p01n01i00927pkg,
+    -- there is no conflict with library "work"
+    variable doit : c10s04b00x00p01n01i00927pkg.work ;  -- No_failure_here
+  BEGIN
+    assert NOT(doit="00000000") 
+      report "***PASSED TEST: c10s04b00x00p01n01i00927"
+      severity NOTE;
+    assert (doit="00000000") 
+      report "***FAILED TEST: c10s04b00x00p01n01i00927 - Use clause do not make that declaration visible." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c10s04b00x00p01n01i00927arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc930.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc930.vhd
new file mode 100644
index 0000000..16e1548
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc930.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc930.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p03n01i00930pkg is
+  constant x : integer := 2;
+  constant y : real := 5.0;
+  subtype register16 is bit_vector(15 downto 0);
+  function "+" (l,r : bit_vector) return bit_vector;
+end c10s04b00x00p03n01i00930pkg;
+
+package body c10s04b00x00p03n01i00930pkg is
+  function "+" (l,r : bit_vector) return bit_vector is
+  begin
+    return (B"1111010100101010");
+  end;
+end c10s04b00x00p03n01i00930pkg;
+
+
+use work.c10s04b00x00p03n01i00930pkg."+";
+use work.c10s04b00x00p03n01i00930pkg.register16;
+ENTITY c10s04b00x00p03n01i00930ent IS
+END c10s04b00x00p03n01i00930ent;
+
+ARCHITECTURE c10s04b00x00p03n01i00930arch OF c10s04b00x00p03n01i00930ent IS
+  signal   i_sig  :  register16 := B"1010_1110_1010_0011";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    i_sig <= i_sig + i_sig after 10 ns;
+    wait for 11 ns;
+    assert NOT(i_sig = "1111010100101010")
+      report "***PASSED TEST: c10s04b00x00p03n01i00930"
+      severity NOTE;
+    assert (i_sig = "1111010100101010")
+      report "***FAILED TEST: c10s04b00x00p03n01i00930 - The operator is visible in the declaration region if the suffix of a selected name in a use clause is an operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s04b00x00p03n01i00930arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc931.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc931.vhd
new file mode 100644
index 0000000..eac447d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc931.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc931.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p03n01i00931pkg is
+  constant x : integer := 2;
+  constant y : real := 5.0;
+  subtype register16 is bit_vector(15 downto 0);
+end c10s04b00x00p03n01i00931pkg;
+
+
+use work.c10s04b00x00p03n01i00931pkg.x;
+ENTITY c10s04b00x00p03n01i00931ent IS
+END c10s04b00x00p03n01i00931ent;
+
+ARCHITECTURE c10s04b00x00p03n01i00931arch OF c10s04b00x00p03n01i00931ent IS
+  signal   i_sig  :  integer := x; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    i_sig <= i_sig + x after 10 ns;
+    wait for 11 ns;
+    assert NOT(i_sig = 4)
+      report "***PASSED TEST: c10s04b00x00p03n01i00931"
+      severity NOTE;
+    assert (i_sig = 4)
+      report "***FAILED TEST: c10s04b00x00p03n01i00931 - The identifier is visible in the declarative region if the suffix of a selected name in a use clause is a simple identifier." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s04b00x00p03n01i00931arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc932.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc932.vhd
new file mode 100644
index 0000000..11cf9e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc932.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc932.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p03n03i00932pkg is
+  subtype register16 is bit_vector(15 downto 0);
+  function "+" (l,r : bit_vector) return bit_vector;
+  function "-" (l,r : bit_vector) return bit_vector;
+end c10s04b00x00p03n03i00932pkg;
+
+package body c10s04b00x00p03n03i00932pkg is
+  function "+" (l,r : bit_vector) return bit_vector is
+  begin
+    return (B"1111010100101010");
+  end;
+  function "-" (l,r : bit_vector) return bit_vector is
+  begin
+    return (B"1111010100101010");
+  end;
+end c10s04b00x00p03n03i00932pkg;
+
+use work.c10s04b00x00p03n03i00932pkg.all;
+ENTITY c10s04b00x00p03n03i00932ent IS
+END c10s04b00x00p03n03i00932ent;
+
+ARCHITECTURE c10s04b00x00p03n03i00932arch OF c10s04b00x00p03n03i00932ent IS
+  signal i_sig : register16 := B"1010_1110_1010_0011";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    i_sig <= i_sig - i_sig + B"1111111100000000" after 10 ns;
+    wait for 20 ns;
+    assert NOT( i_sig = (B"1111010100101010") )
+      report "***PASSED TEST: c10s04b00x00p03n03i00932"
+      severity NOTE;
+    assert ( i_sig = (B"1111010100101010") )
+      report "***FAILED TEST: c10s04b00x00p03n03i00932 - All of the declarations of a package are visible within the declarative region if the suffix of a selected name in a use clause is the word 'all'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s04b00x00p03n03i00932arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc933.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc933.vhd
new file mode 100644
index 0000000..5017e86
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc933.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc933.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p04n01i00933pkg is
+  type    color is ( red, green, blue, yellow, orange, purple );
+  function    "+"    (l,r : bit_vector) return bit_vector;
+end c10s04b00x00p04n01i00933pkg;
+
+package body c10s04b00x00p04n01i00933pkg is
+  function "+" (l,r : bit_vector) return bit_vector is
+  begin
+    return (B"1111");
+  end;
+end c10s04b00x00p04n01i00933pkg;
+
+
+entity c10s04b00x00p04n01i00933ent_a is
+  generic ( x : bit_vector(3 downto 0));
+end c10s04b00x00p04n01i00933ent_a;
+
+architecture c10s04b00x00p04n01i00933arch_a of c10s04b00x00p04n01i00933ent_a is
+begin
+  TESTING: PROCESS
+  BEGIN
+    assert NOT( x=B"1111" )
+      report "***PASSED TEST: c10s04b00x00p04n01i00933"
+      severity NOTE;
+    assert ( x=B"1111" )
+      report "***FAILED TEST: c10s04b00x00p04n01i00933 - Items declared via a use clause are visible in the declarative region."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+end c10s04b00x00p04n01i00933arch_a;
+
+
+use work.c10s04b00x00p04n01i00933pkg.all;
+ENTITY c10s04b00x00p04n01i00933ent IS
+END c10s04b00x00p04n01i00933ent;
+
+ARCHITECTURE c10s04b00x00p04n01i00933arch OF c10s04b00x00p04n01i00933ent IS
+  constant c : bit_vector(3 downto 0) := B"1011";
+  component d
+  end component;
+BEGIN
+  instance : d;
+
+END c10s04b00x00p04n01i00933arch;
+
+configuration c10s04b00x00p04n01i00933cfg of c10s04b00x00p04n01i00933ent is
+  for c10s04b00x00p04n01i00933arch
+    -- declarations are visible here !
+    for instance : d
+      use entity work.c10s04b00x00p04n01i00933ent_a(c10s04b00x00p04n01i00933arch_a) generic map ( B"0100" + c );
+    end for;
+  end for;
+end c10s04b00x00p04n01i00933cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc934.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc934.vhd
new file mode 100644
index 0000000..ce639ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc934.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc934.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p04n01i00934pkg is
+  Type Weekdays is (Monday, Tuesday, Wednesday, Thursday, Friday);
+end c10s04b00x00p04n01i00934pkg;
+
+ENTITY c10s04b00x00p04n01i00934ent IS
+END c10s04b00x00p04n01i00934ent;
+
+use  WORK.c10s04b00x00p04n01i00934pkg.all;
+ARCHITECTURE c10s04b00x00p04n01i00934arch OF c10s04b00x00p04n01i00934ent IS
+  signal done : bit;
+  signal wkday :Weekdays;    -- No_failure_here
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    assert NOT(wkday = Monday) 
+      report "***PASSED TEST: c10s04b00x00p04n01i00934"
+      severity NOTE;
+    assert (wkday = Monday) 
+      report "***FAILED TEST: c10s04b00x00p04n01i00934 - Items declared via a use clause are visible in the declarative region."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s04b00x00p04n01i00934arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc935.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc935.vhd
new file mode 100644
index 0000000..3479c5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc935.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc935.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p06n01i00935pkg is
+  constant x : integer := 10;
+end c10s04b00x00p06n01i00935pkg;
+
+ENTITY c10s04b00x00p06n01i00935ent IS
+END c10s04b00x00p06n01i00935ent;
+
+ARCHITECTURE c10s04b00x00p06n01i00935arch OF c10s04b00x00p06n01i00935ent IS
+  procedure xxx is
+    constant x : integer := 5; -- homograph of x
+    -- here we place the declaration after the local homograph !
+    use work.c10s04b00x00p06n01i00935pkg.all;
+  begin
+    assert NOT( x=5 )
+      report "***PASSED TEST: c10s04b00x00p06n01i00935"
+      severity NOTE;
+    assert ( x=5 )
+      report "***FAILED TEST: c10s04b00x00p06n01i00935 - A potentially visible declaration is not visible within the immediate scope of a homograph."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+
+END c10s04b00x00p06n01i00935arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc936.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc936.vhd
new file mode 100644
index 0000000..7f8e9d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc936.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc936.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p06n01i00936pkg is
+  constant x : integer := 10;
+end c10s04b00x00p06n01i00936pkg;
+
+ENTITY c10s04b00x00p06n01i00936ent IS
+END c10s04b00x00p06n01i00936ent;
+
+ARCHITECTURE c10s04b00x00p06n01i00936arch OF c10s04b00x00p06n01i00936ent IS
+  use work.c10s04b00x00p06n01i00936pkg.all;
+  procedure xxx is
+    constant x : integer := 5; -- homograph of x
+  begin
+    assert NOT( x=5 )
+      report "***PASSED TEST: c10s04b00x00p06n01i00936"
+      severity NOTE;
+    assert ( x=5 )
+      report "***FAILED TEST: c10s04b00x00p06n01i00936 - A potentially visible declaration is not visible within the immediate scope of a homograph."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+
+END c10s04b00x00p06n01i00936arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc938.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc938.vhd
new file mode 100644
index 0000000..63954d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc938.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc938.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p07n01i00938pkg is
+  type color is ( red, white, green, blue );
+  constant x : color := green;
+end c10s04b00x00p07n01i00938pkg;
+
+ENTITY c10s04b00x00p07n01i00938ent IS
+END c10s04b00x00p07n01i00938ent;
+
+ARCHITECTURE c10s04b00x00p07n01i00938arch OF c10s04b00x00p07n01i00938ent IS
+  type    rgb is ( red, green, blue );
+  constant    x : rgb := red; -- homograph of x
+  use work.c10s04b00x00p07n01i00938pkg.all;
+  procedure xxx is
+  begin
+    -- takes the local x
+    assert (x = red) report "x /= red" severity FAILURE;
+    assert NOT( x=red )
+      report "***PASSED TEST: c10s04b00x00p07n01i00938"
+      severity NOTE;
+    assert ( x=red )
+      report "***FAILED TEST: c10s04b00x00p07n01i00938 - A oitentially visible declaration is made visible within the immediate scope of a homograph if the declaration is an enumeration literal."
+      severity ERROR;
+  end xxx;
+BEGIN
+  xxx;
+END c10s04b00x00p07n01i00938arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc940.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc940.vhd
new file mode 100644
index 0000000..24817e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc940.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc940.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s05b00x00p03n02i00940pkg1 is
+  function F1(B:in integer) return integer;
+end c10s05b00x00p03n02i00940pkg1;
+
+package body c10s05b00x00p03n02i00940pkg1 is
+  function  F1(B:in integer) return integer is
+  begin
+    return 1;
+  end;
+end c10s05b00x00p03n02i00940pkg1;
+
+
+package c10s05b00x00p03n02i00940pkg2 is
+  function F1(B:in bit) return boolean;
+end c10s05b00x00p03n02i00940pkg2;
+
+package body c10s05b00x00p03n02i00940pkg2 is
+  function  F1(B:in bit) return boolean is
+  begin
+    return false;
+  end;
+end c10s05b00x00p03n02i00940pkg2;
+
+use work.c10s05b00x00p03n02i00940pkg1.all, work.c10s05b00x00p03n02i00940pkg2.all;
+ENTITY c10s05b00x00p03n02i00940ent IS
+END c10s05b00x00p03n02i00940ent;
+
+ARCHITECTURE c10s05b00x00p03n02i00940arch OF c10s05b00x00p03n02i00940ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if (F1('1') = F1('0')) then  -- No_Failure_here
+      assert FALSE 
+        report "***PASSED TEST: c10s05b00x00p03n02i00940" 
+        severity NOTE;
+    else
+      assert FALSE 
+        report "***FAILED TEST: c10s05b00x00p03n02i00940 - A single interpretation of each constituent of the innermost complete context is not an error." 
+        severity ERROR;
+    end if;
+    wait;
+  END PROCESS TESTING;
+
+END c10s05b00x00p03n02i00940arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc942.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc942.vhd
new file mode 100644
index 0000000..d959db4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc942.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc942.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s05b00x00p05n01i00942ent IS
+END c10s05b00x00p05n01i00942ent;
+
+ARCHITECTURE c10s05b00x00p05n01i00942arch OF c10s05b00x00p05n01i00942ent IS
+  type three_state is ( '0','1','X');
+
+  function "and" (l,r : three_state) return three_state is
+  begin
+    if    (l = '0') or  (r = '0') then return('0');
+    elsif (l = '1') and (r = '1') then return('1');
+    else  return ('X');
+    end if;
+  end;
+
+BEGIN
+  TESTING:PROCESS
+  BEGIN
+    assert NOT( ('1' and 'X') = 'X' )
+      report "***PASSED TEST: c10s05b00x00p05n01i00942"
+      severity NOTE;
+    assert ( ('1' and 'X') = 'X' )
+      report "***FAILED TEST: c10s05b00x00p05n01i00942 - A name or expression have a certain type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s05b00x00p05n01i00942arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc943.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc943.vhd
new file mode 100644
index 0000000..a63f5cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc943.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc943.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p08n01i00943ent IS
+END c06s01b00x00p08n01i00943ent;
+
+ARCHITECTURE c06s01b00x00p08n01i00943arch OF c06s01b00x00p08n01i00943ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : BIT_VECTOR(0 to 5);     -- No_failure_here
+  BEGIN
+    assert NOT( V1="000000" )
+      report "***PASSED TEST: c06s01b00x00p08n01i00943"
+      severity NOTE;
+    assert ( V1="000000" )
+      report "***FAILED TEST: c06s01b00x00p08n01i00943 - The name must be a simple name, an operator symbol, a selected name, an indexed name, a slice name, or an attribute name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p08n01i00943arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc945.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc945.vhd
new file mode 100644
index 0000000..c68ed52
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc945.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc945.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p09n01i00945ent IS
+END c06s01b00x00p09n01i00945ent;
+
+ARCHITECTURE c06s01b00x00p09n01i00945arch OF c06s01b00x00p09n01i00945ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function "+" (a, b:in integer) return bit is
+      variable c: bit;
+      variable d: integer := 0;
+    begin
+      d := a + b + "+".d; -- function call can be used as a prefix.
+      if (d > 0) then
+        c := '0';
+      end if;
+      if (d < 0) then
+        c := '1';
+      end if;
+      return c; 
+    end;
+    variable k : bit;
+  BEGIN
+    k := "+"(1,2);
+    assert NOT(k='0') 
+      report "***PASSED TEST: c06s01b00x00p09n01i00945" 
+      severity NOTE;
+    assert (k='0') 
+      report "***FAILED TEST: c06s01b00x00p09n01i00945 - Prefix can only be a name or a function_call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p09n01i00945arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc951.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc951.vhd
new file mode 100644
index 0000000..500d0ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc951.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc951.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00951ent IS
+END c06s01b00x00p10n01i00951ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00951arch OF c06s01b00x00p10n01i00951ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type TWO is range 1 to 2;
+    type R1 is record
+                 X1: TWO;
+                 RE1: BOOLEAN;
+               end record;
+    type A1 is array (TWO) of R1;
+    variable V1: BOOLEAN;
+    variable V2: A1 ;
+  BEGIN
+    V1 := V2(1).RE1;
+    assert NOT(V1 = false) 
+      report "***PASSED TEST: c06s01b00x00p10n01i00951" 
+      severity NOTE;
+    assert (V1 = false) 
+      report "***FAILED TEST: c06s01b00x00p10n01i00951 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00951arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc952.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc952.vhd
new file mode 100644
index 0000000..d3d1a31
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc952.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc952.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00952ent IS
+END c06s01b00x00p10n01i00952ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00952arch OF c06s01b00x00p10n01i00952ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type TWO is range 1 to 2;
+    type R1 is record
+                 X1: TWO;
+                 RE1: BOOLEAN;
+               end record;
+    type A1  is array (TWO) of R1;
+    type A2  is array (TWO) of A1;
+    variable V1: BOOLEAN;
+    variable V3: A2 ;
+  BEGIN
+    V1 := V3(2)(1).RE1;
+    assert NOT(V1 = false) 
+      report "***PASSED TEST: c06s01b00x00p10n01i00952" 
+      severity NOTE;
+    assert (V1 = false) 
+      report "***FAILED TEST: c06s01b00x00p10n01i00952 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00952arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc953.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc953.vhd
new file mode 100644
index 0000000..39749a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc953.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc953.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00953ent IS
+END c06s01b00x00p10n01i00953ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00953arch OF c06s01b00x00p10n01i00953ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type TWO is range 1 to 2;
+    type R1 is record
+                 X1: TWO;
+                 RE1: BOOLEAN;
+               end record;
+    type A11 is array (TWO, TWO) of R1;
+    variable V1: BOOLEAN;
+    variable V4: A11;
+  BEGIN
+    V1 := V4(1,2).RE1;
+    assert NOT(V1 = false) 
+      report "***PASSED TEST: c06s01b00x00p10n01i00953" 
+      severity NOTE;
+    assert (V1 = false) 
+      report "***FAILED TEST: c06s01b00x00p10n01i00953 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00953arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc954.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc954.vhd
new file mode 100644
index 0000000..56823cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc954.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc954.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00954ent IS
+END c06s01b00x00p10n01i00954ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00954arch OF c06s01b00x00p10n01i00954ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type TWO is range 1 to 2;
+    type R1 is record
+                 X1: TWO;
+                 RE1: BOOLEAN;
+               end record;
+    type A1  is array (TWO) of R1;
+    type A22 is array (TWO, TWO) of A1;
+    variable V1: BOOLEAN;
+    variable V5: A22;
+  BEGIN
+    V1 := V5(1,2)(1).RE1;
+    assert NOT(V1 = false) 
+      report "***PASSED TEST: c06s01b00x00p10n01i00954" 
+      severity NOTE;
+    assert (V1 = false) 
+      report "***FAILED TEST: c06s01b00x00p10n01i00954 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00954arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc955.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc955.vhd
new file mode 100644
index 0000000..3e5a060
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc955.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc955.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n02i00955ent IS
+END c06s01b00x00p10n02i00955ent;
+
+ARCHITECTURE c06s01b00x00p10n02i00955arch OF c06s01b00x00p10n02i00955ent IS
+
+  signal PT : boolean;
+  subtype ONE is integer range 1 to 1;
+  type R1 is record
+               X1: ONE;
+               RE1: BOOLEAN;
+             end record;
+  function rr1(i : integer) return R1 is
+    variable vr : r1;
+  begin
+    return vr;
+  end rr1;
+  attribute AT1       : R1;
+  attribute AT1 of PT : signal is rr1(3);
+  type A1 is array (BOOLEAN) of BOOLEAN;
+BEGIN
+  TESTING: PROCESS
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := PT'AT1.RE1;
+    assert NOT( V1=FALSE )
+      report "***PASSED TEST: c06s01b00x00p10n02i00955"
+      severity NOTE;
+    assert ( V1=FALSE )
+      report "***FAILED TEST: c06s01b00x00p10n02i00955 - The prefix of a name is a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n02i00955arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc956.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc956.vhd
new file mode 100644
index 0000000..c38286d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc956.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc956.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n02i00956ent IS
+END c06s01b00x00p10n02i00956ent;
+
+ARCHITECTURE c06s01b00x00p10n02i00956arch OF c06s01b00x00p10n02i00956ent IS
+
+  signal PT : boolean;
+  subtype ONE is integer range 1 to 1;
+  type R1 is record
+               X1: ONE;
+               RE1: BOOLEAN;
+             end record;
+  function rr1(i : integer) return R1 is
+    variable vr : r1;
+  begin
+    return vr;
+  end rr1;
+  attribute AT1       : R1;
+  attribute AT1 of PT : signal is rr1(3);
+  type A1 is array (BOOLEAN) of BOOLEAN;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : BOOLEAN;
+    variable V2 : A1;
+  BEGIN
+    V1 := V2(PT'AT1.RE1);
+    assert NOT( V1=FALSE )
+      report "***PASSED TEST: c06s01b00x00p10n02i00956"
+      severity NOTE;
+    assert ( V1=FALSE )
+      report "***FAILED TEST: c06s01b00x00p10n02i00956 - The prefix of a name is a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n02i00956arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc958.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc958.vhd
new file mode 100644
index 0000000..9f7e9d8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc958.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc958.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p02n01i00958ent IS
+END c06s03b00x00p02n01i00958ent;
+
+ARCHITECTURE c06s03b00x00p02n01i00958arch OF c06s03b00x00p02n01i00958ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ONE is range 1 to 1;
+
+    type R0 is record X: ONE; RE: BOOLEAN; end record;            
+    type R1 is record X: ONE; RE: R0; end record;
+    type R2 is record X: ONE; RE: R1; end record;
+    type R3 is record X: ONE; RE: R2; end record;
+    type R4 is record X: ONE; RE: R3; end record;
+    type R5 is record X: ONE; RE: R4; end record;
+    type R6 is record X: ONE; RE: R5; end record;
+    type R7 is record X: ONE; RE: R6; end record;
+    type R8 is record X: ONE; RE: R7; end record;
+    type R9 is record X: ONE; RE: R8; end record;
+
+    variable V1: R9;
+  BEGIN
+    assert NOT(V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
+      report "***PASSED TEST: c06s03b00x00p02n01i00958"
+      severity NOTE;
+    assert (V1.RE.RE.RE.RE.RE.RE.RE.RE.RE.RE = false)
+      report "***FAILED TEST: c06s03b00x00p02n01i00958 - The selected name consists of a prefix, a dot (.), and a suffix."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p02n01i00958arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc962.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc962.vhd
new file mode 100644
index 0000000..ab758f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc962.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc962.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p03n01i00962ent IS
+END c06s03b00x00p03n01i00962ent;
+
+ARCHITECTURE c06s03b00x00p03n01i00962arch OF c06s03b00x00p03n01i00962ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T1 is record
+                 S1 : Bit ;
+                 S2 : Integer;
+               end record;
+    type T2 is record
+                 S11 : BIT ;
+                 S12 : T1 ;
+               end record;
+    variable V1 : T2 ;
+  BEGIN
+    V1.S12.S2 := 10 ;  -- No_Failure_here
+    wait for 10 ns;
+    assert NOT( V1.S12.S2 = 10 )
+      report "***PASSED TEST: c06s03b00x00p03n01i00962"
+      severity NOTE;
+    assert ( V1.S12.S2 = 10 )
+      report "***FAILED TEST: c06s03b00x00p03n01i00962 - The suffix of a selected name can be a simple name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p03n01i00962arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc964.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc964.vhd
new file mode 100644
index 0000000..70132d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc964.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc964.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p04n02i00964pkg is
+  type T1 is record
+               S1 : Bit ;
+               S2 : Integer;
+             end record;
+  type T2 is record
+               S11 : BIT ;
+               S12 : T1 ;
+             end record;
+end c06s03b00x00p04n02i00964pkg;
+
+use work.c06s03b00x00p04n02i00964pkg.all;
+
+ENTITY c06s03b00x00p04n02i00964ent IS
+END c06s03b00x00p04n02i00964ent;
+
+ARCHITECTURE c06s03b00x00p04n02i00964arch OF c06s03b00x00p04n02i00964ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T2 ;
+  BEGIN
+    V1.S12.S2 := 20 ;  -- No_Failure_here
+    wait for 10 ns;
+    assert NOT(V1.S12.S2 = 20)
+      report "***PASSED TEST: c06s03b00x00p04n02i00964"
+      severity NOTE;
+    assert (V1.S12.S2 = 20)
+      report "***FAILED TEST: c06s03b00x00p04n02i00964 - The selected name may be used to denote entities declared within a package."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p04n02i00964arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc965.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc965.vhd
new file mode 100644
index 0000000..a1faa30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc965.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc965.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p04n01i00965ent IS
+END c06s03b00x00p04n01i00965ent;
+
+ARCHITECTURE c06s03b00x00p04n01i00965arch OF c06s03b00x00p04n01i00965ent IS
+  type Rcd is record
+                RE1: BOOLEAN;
+              end record;
+BEGIN
+  TESTING: PROCESS
+    variable var : Rcd;
+  BEGIN
+    var.RE1 := TRUE;
+    wait for 5 ns;
+    assert NOT(var.RE1 = TRUE) 
+      report "***PASSED TEST: c06s03b00x00p04n01i00965"
+      severity NOTE;
+    assert (var.RE1 = TRUE) 
+      report "***FAILED TEST: c06s03b00x00p04n01i00965 - Selected name should be able to be used to denote an element of a record."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p04n01i00965arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc966.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc966.vhd
new file mode 100644
index 0000000..006b84a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc966.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc966.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p04n01i00966pkg is
+  constant   tPLH : TIME := 10 ns;
+  constant   tPHL : TIME := 12 ns;
+end c06s03b00x00p04n01i00966pkg;
+
+ENTITY c06s03b00x00p04n01i00966ent IS
+END c06s03b00x00p04n01i00966ent;
+
+ARCHITECTURE c06s03b00x00p04n01i00966arch OF c06s03b00x00p04n01i00966ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT(work.c06s03b00x00p04n01i00966pkg.tPLH = 10 ns and work.c06s03b00x00p04n01i00966pkg.tPHL = 12 ns)
+      report "***PASSED TEST: c06s03b00x00p04n01i00966" 
+      severity NOTE;
+    assert (work.c06s03b00x00p04n01i00966pkg.tPLH = 10 ns and work.c06s03b00x00p04n01i00966pkg.tPHL = 12 ns)
+      report "***FAILED TEST: c06s03b00x00p04n01i00966 - Selected name should be able to be used to denote a named entity whose declaration is contained within a package."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p04n01i00966arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc968.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc968.vhd
new file mode 100644
index 0000000..f3be44f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc968.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc968.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00968ent IS
+END c06s03b00x00p05n01i00968ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00968arch OF c06s03b00x00p05n01i00968ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        t : time;
+        u : character;
+        v : real;
+        w : severity_level;
+        x : bit;
+        y : integer;
+        z : boolean;
+      end record;
+    variable S1, S2 :rec_type;
+  BEGIN
+    S1.t := 10 ns;
+    S1.u := 'A';
+    S1.v := 1.2;
+    S1.w := ERROR;
+    S1.y := 12  ;
+    S1.x := '0' ;   -- legal.
+    S2   := S1  ;
+    assert NOT(S2.t=10 ns and S2.u='A' and S2.v=1.2 and S2.w=ERROR and S2.x='0' and S2.y=12 and S2.z=false) 
+      report "***PASSED TEST: c06s03b00x00p05n01i00968" 
+      severity NOTE;
+    assert (S2.t=10 ns and S2.u='A' and S2.v=1.2 and S2.w=ERROR and S2.x='0' and S2.y=12 and S2.z=false) 
+      report "***FAILED TEST: c06s03b00x00p05n01i00968 - Suffix should denote an element of a record object or value."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00968arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc969.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc969.vhd
new file mode 100644
index 0000000..795abf4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc969.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc969.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00969ent IS
+END c06s03b00x00p05n01i00969ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00969arch OF c06s03b00x00p05n01i00969ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        t : time;
+        u : character;
+        v : real;
+        w : severity_level;
+        x : bit;
+        y : integer;
+        z : boolean;
+      end record;
+    variable S1, S2 :rec_type;
+  BEGIN
+    S1.t := 11 ns;
+    S1.u := 'A';
+    S1.v := 2.1;
+    S1.w := NOTE;
+    S1.x := '0' ;   -- legal.
+    S1.y := 12  ;
+    S1.z := true;
+    S2.t := S1.t;
+    S2.u := S1.u;
+    S2.v := S1.v;
+    S2.w := S1.w;
+    S2.x := S1.x;
+    S2.y := S1.y;
+    S2.z := S1.z;
+    assert NOT(   
+      S1.t = 11 ns   and
+      S1.u = 'A'   and
+      S1.v = 2.1   and
+      S1.w = NOTE   and
+      S1.x = '0'    and
+      S1.y = 12     and
+      S1.z = true   and
+      S2.t = 11 ns   and
+      S2.u = 'A'   and
+      S2.v = 2.1   and
+      S2.w = NOTE   and
+      S2.x = '0'    and
+      S2.y = 12     and
+      S2.z = true   )
+      report "***PASSED TEST: c06s03b00x00p05n01i00969" 
+      severity NOTE;
+    assert (   
+      S1.t = 11 ns   and
+      S1.u = 'A'   and
+      S1.v = 2.1   and
+      S1.w = NOTE   and
+      S1.x = '0'    and
+      S1.y = 12     and
+      S1.z = true   and
+      S2.t = 11 ns   and
+      S2.u = 'A'   and
+      S2.v = 2.1   and
+      S2.w = NOTE   and
+      S2.x = '0'    and
+      S2.y = 12     and
+      S2.z = true   )
+      report "***FAILED TEST: c06s03b00x00p05n01i00969 - The prefix is not appropriate for the type of the object or value denoted by the suffix." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00969arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc973.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc973.vhd
new file mode 100644
index 0000000..a4348aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc973.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc973.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00973ent IS
+END c06s03b00x00p05n01i00973ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00973arch OF c06s03b00x00p05n01i00973ent IS
+  TYPE simple_record_2_type IS
+    RECORD
+      a2 : integer;
+      b2 : integer;
+    END RECORD;
+
+  TYPE array_of_records_type IS
+    ARRAY (20 TO 30) OF simple_record_2_type;
+
+  SIGNAL sr : array_of_records_type;
+BEGIN
+  TESTING: PROCESS
+    VARIABLE ar,br : array_of_records_type;
+
+    FUNCTION convert (ain : array_of_records_type) RETURN integer IS
+    BEGIN
+      RETURN (ain(25).b2);
+    END;
+  BEGIN
+    wait for 1 ns;
+    br(20).b2 := 8;
+    ar(30).b2 := br(20).b2;
+
+    ar(30).b2 := 8;
+    ar(20).a2 := ar(30).b2;
+
+    sr(30).b2 <= 8;
+    wait for 1 ns;
+    sr(20).a2 <= sr(30).b2;
+    wait for 1 ns;
+
+    ar(25).b2 := 3;
+    sr(25).b2 <= 3;
+    wait for 1 ns;
+    
+    assert NOT((ar(30).b2 = 8)   AND
+               (ar(20).a2 = 8)   AND
+               (sr(20).a2 = 8)   AND
+               (convert(ar) = 3) AND
+               (convert(sr) = 3)) 
+      report "***PASSED TEST: c06s03b00x00p05n01i00973" 
+      severity NOTE;
+    assert    ((ar(30).b2 = 8)   AND
+               (ar(20).a2 = 8)   AND
+               (sr(20).a2 = 8)   AND
+               (convert(ar) = 3) AND
+               (convert(sr) = 3)) 
+      report "***FAILED TEST: c06s03b00x00p05n01i00973 - The prefix fo the selected names can be an array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00973arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc98.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc98.vhd
new file mode 100644
index 0000000..6327a94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc98.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc98.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n02i00098ent_a IS
+  GENERIC ( gen_in : IN INTEGER );
+  PORT ( prt_in : IN INTEGER );
+  
+  ATTRIBUTE attr1 : INTEGER;
+  ATTRIBUTE attr1 OF gen_in : CONSTANT IS 100;
+  ATTRIBUTE attr1 OF prt_in : SIGNAL   IS 200;
+END c04s03b02x00p29n02i00098ent_a;
+
+ARCHITECTURE c04s03b02x00p29n02i00098arch_a OF c04s03b02x00p29n02i00098ent_a IS
+  
+BEGIN
+  PROCESS
+  BEGIN
+    ASSERT gen_in'attr1 = 100 REPORT "ERROR: Bad value for gen_in'attr1" SEVERITY FAILURE;
+    ASSERT prt_in'attr1 = 200 REPORT "ERROR: Bad value for prt_in'attr1" SEVERITY FAILURE;
+    assert NOT(gen_in'attr1 = 100 and prt_in'attr1 = 200) 
+      report "***PASSED TEST: c04s03b02x00p29n02i00098" 
+      severity NOTE;
+    assert (gen_in'attr1 = 100 and prt_in'attr1 = 200) 
+      report "***FAILED TEST: c04s03b02x00p29n02i00098 - Attribute reading fail."
+      severity ERROR;
+    wait;
+  END PROCESS;
+END c04s03b02x00p29n02i00098arch_a;
+
+
+
+ENTITY c04s03b02x00p29n02i00098ent IS
+END c04s03b02x00p29n02i00098ent;
+
+ARCHITECTURE c04s03b02x00p29n02i00098arch OF c04s03b02x00p29n02i00098ent IS
+  COMPONENT c04s03b02x00p29n02i00098ent_a
+    GENERIC ( gen_in : IN INTEGER );
+    PORT ( prt_in : IN INTEGER );
+  END COMPONENT;
+  FOR cmp1 : c04s03b02x00p29n02i00098ent_a USE ENTITY work.c04s03b02x00p29n02i00098ent_a(c04s03b02x00p29n02i00098arch_a); 
+  
+  SIGNAL s : INTEGER;
+BEGIN
+
+  cmp1 : c04s03b02x00p29n02i00098ent_a
+    GENERIC MAP ( 0 )
+    PORT MAP ( s );
+
+END c04s03b02x00p29n02i00098arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc983.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc983.vhd
new file mode 100644
index 0000000..000c157
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc983.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc983.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p06n01i00983ent IS
+END c06s03b00x00p06n01i00983ent;
+
+ARCHITECTURE c06s03b00x00p06n01i00983arch OF c06s03b00x00p06n01i00983ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T is
+      record
+        a:integer;
+        b:integer;
+      end record;
+    type A is access T;
+    variable B1, B2: A := new T'(0, 0);
+    variable C     : T;
+    function foo return integer is
+    begin 
+      return 120; 
+    end;
+    function foo return real is
+    begin 
+      return 12.0; 
+    end;
+  BEGIN
+    C      := B1.all;
+    B1.all := B2.all;
+    assert NOT( C.a=0 and C.b=0 )
+      report "***PASSED TEST: c06s03b00x00p06n01i00983"
+      severity NOTE;
+    assert ( C.a=0 and C.b=0 )
+      report "***FAILED TEST: c06s03b00x00p06n01i00983 - For a selected name that is used to denote the object designated by an access value, the suffix must be the reserved word all."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p06n01i00983arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc986.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc986.vhd
new file mode 100644
index 0000000..d155922
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc986.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc986.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p06n01i00986ent IS
+END c06s03b00x00p06n01i00986ent;
+
+ARCHITECTURE c06s03b00x00p06n01i00986arch OF c06s03b00x00p06n01i00986ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T1 is record
+                 S1 : BIT ;
+                 S2 : Integer;
+               end record;
+    type T2 is access T1;
+    variable V1 : T2 := new T1'('0',0) ;
+    variable V2 : T1;
+  BEGIN
+    V2 := V1.all ; -- No_Failure_here
+    wait for 10 ns;
+    assert NOT(V2.S1='0' and V2.S2=0) 
+      report "***PASSED TEST: c06s03b00x00p06n01i00986" 
+      severity NOTE;
+    assert (V2.S1='0' and V2.S2=0) 
+      report "***FAILED TEST: c06s03b00x00p06n01i00986 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p06n01i00986arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc987.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc987.vhd
new file mode 100644
index 0000000..429fed0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc987.vhd
@@ -0,0 +1,991 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc987.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p06n01i00987pkg is
+------------------------------------USING ONLY WHITE MATTER---------------------------------
+--------------------------------------------------------------------------------------------
+---ACCESS TYPE FROM STANDARD PACKAGE
+
+  type boolean_ptr is access boolean ;                                  --simple boolean type   
+  type bit_ptr is access bit ;                                          --simple bit type
+  type char_ptr is access character;                                    --simple character type
+  type severity_level_ptr is access severity_level;                     --simple severity type
+  type integer_ptr is access integer;                                   --simple integer type   
+  type real_ptr is access real;                                         --simple real type
+  type time_ptr is access time;                                         --simple time type
+  type natural_ptr is access natural;                                   --simple natural type
+  type positive_ptr is access positive;                                 --simple positive type
+  type string_ptr is access string;                                     --simple string type
+  type bit_vector_ptr is access bit_vector;                             --simple bit_vector type
+
+--------------------------------------------------------------------------------------------
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+---------------------------------------------------------------------------------------------
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st is  integer_vector(0 to 15);
+  subtype real_vector_st is  real_vector(0 to 15);
+  subtype time_vector_st is  time_vector(0 to 15);
+  subtype natural_vector_st is  natural_vector(0 to 15);
+  subtype positive_vector_st is  positive_vector(0 to 15);
+  
+---------------------------------------------------------------------------------------------
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vector is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector is array (15 downto 0) of integer;
+  type real_cons_vector is array (15 downto 0) of real;
+  type time_cons_vector is array (15 downto 0) of time;
+  type natural_cons_vector is array (15 downto 0) of natural;
+  type positive_cons_vector is array (15 downto 0) of positive;
+  
+---------------------------------------------------------------------------------------------
+  
+--CONSTRAINED ARRAY OF ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
+  
+---------------------------------------------------------------------------------------------
+
+--UNCONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type s2boolean_vector is array (natural range <>,natural range <>) of boolean;
+  type s2bit_vector is array (natural range<>,natural range <>) of bit;
+  type s2char_vector is array (natural range<>,natural range <>) of character;
+  type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
+  type s2integer_vector is array (natural range <>,natural range <>) of integer;
+  type s2real_vector is array (natural range <>,natural range <>) of real;
+  type s2time_vector is array (natural range <>,natural range <>) of time;
+  type s2natural_vector is array (natural range <>,natural range <>) of natural;
+  type s2positive_vector is array (natural range <>,natural range <>) of positive;
+  
+----------------------------------------------------------------------------------------------
+  
+--CONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type column is range 1 to 64;
+  type row is range 1 to 1024;
+  type s2boolean_cons_vector is array (row,column) of boolean;
+  type s2bit_cons_vector is array (row,column) of bit;
+  type s2char_cons_vector is array (row,column) of character;
+  type s2severity_level_cons_vector is array (row,column) of severity_level;
+  type s2integer_cons_vector is array (row,column) of integer;
+  type s2real_cons_vector is array (row,column) of real;
+  type s2time_cons_vector is array (row,column) of time;
+  type s2natural_cons_vector is array (row,column) of natural;
+  type s2positive_cons_vector is array (row,column) of positive;
+  
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS FROM STANDARD PACKAGE
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS AS UNCONSTRAINT ARRAYS
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+-----------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+-----------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS
+  
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS OF ARRAY
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+-----------------------------------------------------------------------------------------------
+  type record_of_ptr is record
+                          a:boolean_ptr ;                                   --simple boolean type
+                          b:bit_ptr;                                        --simple bit type
+                          c:char_ptr;                                       --simple character type
+                          e:severity_level_ptr;                        --simple severity type
+                          f:integer_ptr;                                    --simple integer type
+                          g:  real_ptr ;                                    --simple real type
+                          h:time_ptr;                                       --simple time type
+                          i: natural_ptr;                                   --simple natural type
+
+                          j:positive_ptr;                                   --simple positive type
+                          k: string_ptr;                                    --simple string type
+                          l: bit_vector_ptr;                                --simple bit_vector type
+                        end record;
+  
+  
+-----------------------------------------------------------------------------------------------
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              h: record_of_ptr;
+                              i: record_array_st;
+                            end record;
+  
+-----------------------------------------------------------------------------------------------
+--ACCESS TYPES FOR ABOVE
+-----------------------------------------------------------------------------------------------
+  
+  type boolean_vector_ptr is access boolean_vector;
+  type severity_level_vector_ptr is access severity_level_vector;
+  type integer_vector_ptr is access integer_vector;
+  type real_vector_ptr is access real_vector;
+  type time_vector_ptr is access time_vector;
+  type natural_vector_ptr is access natural_vector;
+  type positive_vector_ptr is access positive_vector;
+-----------------------------------------------------------------------------------------------
+  type boolean_vector_st_ptr is access boolean_vector_st;--(0 to 15);
+  type severity_level_vector_st_ptr is access  severity_level_vector_st;--(0 to 15);
+  type integer_vector_st_ptr is access  integer_vector_st;--(0 to 15);
+  type real_vector_st_ptr is access  real_vector_st;--(0 to 15);
+  type time_vector_st_ptr is access  time_vector_st;--(0 to 15);
+  type natural_vector_st_ptr is access  natural_vector_st;--(0 to 15);
+  type positive_vector_st_ptr is access  positive_vector_st;--(0 to 15);
+-----------------------------------------------------------------------------------------------
+  type boolean_cons_vector_ptr is access boolean_cons_vector;
+  type severity_level_cons_vector_ptr is access severity_level_cons_vector;
+  type integer_cons_vector_ptr is access  integer_cons_vector;
+  type real_cons_vector_ptr is access real_cons_vector;
+  type time_cons_vector_ptr is access time_cons_vector;
+  type natural_cons_vector_ptr is access natural_cons_vector;
+  type positive_cons_vector_ptr is access  positive_cons_vector;
+-----------------------------------------------------------------------------------------------
+  type boolean_cons_vectorofvector_ptr is access boolean_cons_vectorofvector;
+  type sev_lvl_cons_vecofvec_ptr is access severity_level_cons_vectorofvector;
+  type integer_cons_vectorofvector_ptr is access integer_cons_vectorofvector;
+  type real_cons_vectorofvector_ptr is access  real_cons_vectorofvector;
+  type time_cons_vectorofvector_ptr is access time_cons_vectorofvector;
+  type natural_cons_vectorofvector_ptr is access natural_cons_vectorofvector;
+  type posi_cons_vecofvec_ptr is access positive_cons_vectorofvector;
+-----------------------------------------------------------------------------------------------
+  type s2boolean_vector_ptr is access s2boolean_vector;
+  type s2bit_vector_ptr is access  s2bit_vector;
+  type s2char_vector_ptr is access s2char_vector;
+  type s2severity_level_vector_ptr is access s2severity_level_vector;
+  type s2integer_vector_ptr is access s2integer_vector;
+  type s2real_vector_ptr is access s2real_vector;
+  type s2time_vector_ptr is access  s2time_vector;
+  type s2positive_vector_ptr is access s2positive_vector;
+-----------------------------------------------------------------------------------------------
+  type s2boolean_cons_vector_ptr is access s2boolean_cons_vector;
+  type s2bit_cons_vector_ptr is access s2bit_cons_vector;
+  type s2char_cons_vector_ptr is access  s2char_cons_vector;
+  type s2sev_lvl_cons_vec_ptr is access s2severity_level_cons_vector;
+  type s2integer_cons_vector_ptr is access  s2integer_cons_vector;
+  type s2real_cons_vector_ptr is access  s2real_cons_vector;
+  type s2time_cons_vector_ptr is access  s2time_cons_vector;
+  type s2natural_cons_vector_ptr is access s2natural_cons_vector;
+  type s2positive_cons_vector_ptr is access s2positive_cons_vector;
+----------------------------------------------------------------------------------------------
+  type record_std_package_ptr is access record_std_package;
+  type record_cons_array_ptr is access  record_cons_array;
+  type record_2cons_array_ptr is access  record_2cons_array;
+  type record_cons_arrayofarray_ptr is access  record_cons_arrayofarray;
+  type record_of_ptr_ptr is access record_of_ptr;
+  type record_of_records_ptr is access record_of_records;
+  type record_array_st_ptr is access record_array_st;
+  
+-----------------------------------------------------------------------------------------------
+-------------------------USING PARTIAL GRAY & PARTIAL WHITE MATTER-----------------------------
+  
+  
+  
+  type four_value is ('Z','0','1','X');                                 --enumerated type
+  type four_value_map is array(four_value) of boolean;
+  subtype binary is four_value range '0' to '1';
+  type four_value_vector is array (natural range <>) of four_value;     --unconstraint array of
+  type byte is array(0 to 7) of bit;
+  subtype word is bit_vector(0 to  15);                                 --constrained array
+  function resolution(i:in four_value_vector) return four_value;        --bus resolution
+  subtype four_value_state is resolution four_value;                    --function type
+  type state_vector is array (natural range <>) of four_value_state;    --unconstraint array of
+  constant size :integer := 63;
+  type primary_memory is array(0 to size) of word;                      --array of an array
+  type primary_memory_module is                                         --record with field
+    record                                                                --as an array
+      enable:binary;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;       --array of a complex record
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  subtype delay is integer range 1 to 10;
+  
+  type four_value_ptr is access four_value;
+  type four_value_map_ptr is access four_value_map;
+  type binary_ptr is access binary;
+  type four_value_vector_ptr is access four_value_vector;               --ennumerated type
+  type byte_ptr is access byte;
+  type word_ptr is access word;
+  type four_value_state_ptr is access four_value_state;
+  type state_vector_ptr is access state_vector;                         --type returned by resolu.
+  type primary_memory_ptr is access primary_memory;
+  type primary_memory_module_ptr is access primary_memory_module;
+  type whole_memory_ptr is access whole_memory;
+  type current_ptr is access current;
+  type resistance_ptr is access resistance;
+  type delay_ptr is access delay;
+-------------------------------------------------------------------------------------------
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant C10 : string := "shishir";
+  constant C11 : bit_vector := B"0011";
+  constant C12 : boolean_vector := (true,false);
+  constant C13 : severity_level_vector := (note,error);
+  constant C14 : integer_vector := (1,2,3,4);
+  constant C15 : real_vector := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector := (1,2,3,4);
+  constant C18 : positive_vector := (1,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 :  severity_level_vector_st:= (others => C4);
+  constant C72 :  integer_vector_st:=(others => C5);
+  constant C73 :  real_vector_st:=(others => C6);
+  constant C74 :  time_vector_st:=(others => C7);
+  constant C75 :  natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  
+  
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+--constant C33 : s2boolean_vector := ((true,true),(false,false));
+--constant C34 : s2bit_vector := ((B"0011"),(B"1100"));
+--constant C35 : s2char_vector := (('s','h'),('i','s'));
+--constant C36 : s2severity_level_vector := ((note,error),(error,note));
+--constant C37 : s2integer_vector := ((1,2,3,4),(4,3,2,1));
+--constant C38 : s2real_vector := ((1.0,2.0,3.0,4.0),(4.0,3.0,2.0,1.0));
+--constant C39 : s2time_vector := ((1 ns, 2 ns, 3 ns, 4 ns),(1 ns, 2 ns, 3 ns, 4 ns));
+--constant C40 : s2positive_vector := ((1,2,3,4),(4,3,2,1));
+  constant C41 : s2boolean_cons_vector := (others =>(others => C1));
+  constant C42 : s2bit_cons_vector := (others => (others => C2));
+  constant C43 : s2char_cons_vector := (others =>(others => C3));
+  constant C44 : s2severity_level_cons_vector := (others => (others => C4));
+  constant C45 : s2integer_cons_vector := (others => (others => C5));
+  constant C46 : s2real_cons_vector := (others =>(others => C6));
+  constant C47 : s2time_cons_vector := (others =>(others => C7));
+  constant C48 : s2natural_cons_vector := (others =>(others => C8));
+  constant C49 : s2positive_cons_vector := (others => (others => C9));
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+--constant C54 : record_of_ptr := (NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
+--constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+--constant C55 : record_of_records := (C50,C51,C52,C53,C54,C54a);
+  constant C56 : four_value := 'Z';
+  constant C57 : four_value_map := (true,true,true,true);
+  constant C58 : binary := '0';
+  constant C59 : four_value_vector := ('1','0','1','0');
+  constant C60 : byte := (others => '0');
+  constant C61 : word := (others =>'0' );
+  constant C62 : four_value_state := 'Z';
+  constant C63 : state_vector := ('Z','Z','Z','Z');
+  constant C64 : primary_memory := (others => C61);
+  constant C65 : primary_memory_module := ('1',C64);
+  constant C66 : whole_memory := (others => C65);
+  constant C67 : current := 1 A;
+  constant C68 : resistance := 1 Ohm;
+  constant C69 : delay := 2;
+  
+end c06s03b00x00p06n01i00987pkg;
+
+package body c06s03b00x00p06n01i00987pkg is
+  function resolution(i:in four_value_vector) return four_value is
+    variable temp :four_value := 'Z';
+  begin
+    return temp;
+  end;
+end c06s03b00x00p06n01i00987pkg;
+
+use work.c06s03b00x00p06n01i00987pkg.all;
+
+ENTITY c06s03b00x00p06n01i00987ent IS
+END c06s03b00x00p06n01i00987ent;
+
+ARCHITECTURE c06s03b00x00p06n01i00987arch OF c06s03b00x00p06n01i00987ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable var1 : boolean_ptr ;
+    variable var2 : bit_ptr ;
+    variable var3 : char_ptr ;
+    variable var4 : severity_level_ptr ;
+    variable var5 : integer_ptr ;
+    variable var6 : real_ptr ;
+    variable var7 : time_ptr ;
+    variable var8 : natural_ptr ;
+    variable var9 : positive_ptr ;
+    variable var10 : string_ptr ;
+    variable var11 : bit_vector_ptr ;
+    variable var12 : boolean_vector_ptr ;
+    variable var13 : severity_level_vector_ptr ;
+    variable var14 : integer_vector_ptr ;
+    variable var15 : real_vector_ptr ;
+    variable var16 : time_vector_ptr ;
+    variable var17 : natural_vector_ptr ;
+    variable var18 : positive_vector_ptr ;
+    variable var19 : boolean_cons_vector_ptr ;
+    variable var20 : severity_level_cons_vector_ptr ;
+    variable var21 : integer_cons_vector_ptr ;
+    variable var22 : real_cons_vector_ptr ;
+    variable var23 : time_cons_vector_ptr ;
+    variable var24 : natural_cons_vector_ptr ;
+    variable var25 : positive_cons_vector_ptr ;
+    variable var26 : boolean_cons_vectorofvector_ptr ;
+    variable var27 : sev_lvl_cons_vecofvec_ptr ;
+    variable var28 : integer_cons_vectorofvector_ptr ;
+    variable var29 : real_cons_vectorofvector_ptr ;
+    variable var30 : time_cons_vectorofvector_ptr ;
+    variable var31 : natural_cons_vectorofvector_ptr ;
+    variable var32 : posi_cons_vecofvec_ptr ;
+-- variable var33 : s2boolean_vector_ptr ;
+-- variable var34 : s2bit_vector_ptr ;
+-- variable var35 : s2char_vector_ptr ;
+-- variable var36 : s2severity_level_vector_ptr ;
+-- variable var37 : s2integer_vector_ptr ;
+-- variable var38 : s2real_vector_ptr ;
+-- variable var39 : s2time_vector_ptr ;
+-- variable var40 : s2positive_vector_ptr ;
+    variable var41 : s2boolean_cons_vector_ptr ;
+    variable var42 : s2bit_cons_vector_ptr ;
+    variable var43 : s2char_cons_vector_ptr ;
+    variable var44 : s2sev_lvl_cons_vec_ptr ;
+    variable var45 : s2integer_cons_vector_ptr ;
+    variable var46 : s2real_cons_vector_ptr ;
+    variable var47 : s2time_cons_vector_ptr ;
+    variable var48 : s2natural_cons_vector_ptr ;
+    variable var49 : s2positive_cons_vector_ptr ;
+    variable var50 : record_std_package_ptr ;
+    variable var51 : record_cons_array_ptr ;
+    variable var52 : record_2cons_array_ptr ;
+    variable var53 : record_cons_arrayofarray_ptr ;
+    variable var54 : record_of_ptr_ptr ;
+    variable var54a : record_array_st_ptr;
+    variable var55 : record_of_records_ptr ;
+    variable var56 : four_value_ptr ;
+    variable var57 : four_value_map_ptr ;
+    variable var58 : binary_ptr ;
+    variable var59 : four_value_vector_ptr ;
+    variable var60 : byte_ptr ;
+    variable var61 : word_ptr ;
+    variable var62 : four_value_state_ptr ;
+    variable var63 : state_vector_ptr ;
+    variable var64 : primary_memory_ptr ;
+    variable var65 : primary_memory_module_ptr;
+    variable var66 : whole_memory_ptr ;
+    variable var67 : current_ptr ;
+    variable var68 : resistance_ptr ;
+    variable var69 : delay_ptr ;
+    variable var70 : boolean_vector_st_ptr;
+    variable var71 :  severity_level_vector_st_ptr;
+    variable var72 :  integer_vector_st_ptr;
+    variable var73 :  real_vector_st_ptr;
+    variable var74 :  time_vector_st_ptr;
+    variable var75 :  natural_vector_st_ptr;
+    variable var76 : positive_vector_st_ptr;
+    
+    variable vari1 : boolean;
+    variable vari2 : bit;
+    variable vari3 : character;
+    variable vari4 : severity_level;
+    variable vari5 : integer;
+    variable vari6 : real;
+    variable vari7 : time;
+    variable vari8 : natural;
+    variable vari9 : positive;
+    variable vari10 : string(1 to 7);
+    variable vari11 : bit_vector(0 to 3);
+    variable vari12 : boolean_vector(0 to 1);
+    variable vari13 : severity_level_vector(0 to 1);
+    variable vari14 : integer_vector(0 to 3);
+    variable vari15 : real_vector(0 to 3);
+    variable vari16 : time_vector(0 to 3);
+    variable vari17 : natural_vector(0 to 3);
+    variable vari18 : positive_vector(0 to 3);
+    variable vari19 : boolean_cons_vector;
+    variable vari20 : severity_level_cons_vector;
+    variable vari21 : integer_cons_vector;
+    variable vari22 : real_cons_vector;
+    variable vari23 : time_cons_vector;
+    variable vari24 : natural_cons_vector;
+    variable vari25 : positive_cons_vector;
+    variable vari26 : boolean_cons_vectorofvector;
+    variable vari27 : severity_level_cons_vectorofvector;
+    variable vari28 : integer_cons_vectorofvector;
+    variable vari29 : real_cons_vectorofvector;
+    variable vari30 : time_cons_vectorofvector;
+    variable vari31 : natural_cons_vectorofvector;
+    variable vari32 : positive_cons_vectorofvector;
+--variable vari33 : s2boolean_vector;
+--variable vari34 : s2bit_vector;
+--variable vari35 : s2char_vector;
+--variable vari36 : s2severity_level_vector;
+--variable vari37 : s2integer_vector;
+--variable vari38 : s2real_vector;
+--variable vari39 : s2time_vector;
+--variable vari40 : s2positive_vector;
+    variable vari41 : s2boolean_cons_vector;
+    variable vari42 : s2bit_cons_vector;
+    variable vari43 : s2char_cons_vector;
+    variable vari44 : s2severity_level_cons_vector;
+    variable vari45 : s2integer_cons_vector;
+    variable vari46 : s2real_cons_vector;
+    variable vari47 : s2time_cons_vector;
+    variable vari48 : s2natural_cons_vector;
+    variable vari49 : s2positive_cons_vector;
+    variable vari50 : record_std_package;
+    variable vari51 : record_cons_array;
+    variable vari52 : record_2cons_array;
+    variable vari53 : record_cons_arrayofarray;
+    variable vari54 : record_of_ptr;
+    variable vari55 : record_of_records;
+    variable vari56 : four_value;
+    variable vari57 : four_value_map;
+    variable vari58 : binary;
+    variable vari59 : four_value_vector(0 to 3);
+    variable vari60 : byte;
+    variable vari61 : word;
+    variable vari62 : four_value_state;
+    variable vari63 : state_vector(0 to 3);
+    variable vari64 : primary_memory;
+    variable vari65 : primary_memory_module;
+    variable vari66 : whole_memory;
+    variable vari67 : current;
+    variable vari68 : resistance;
+    variable vari69 : delay;
+    variable vari70 : boolean_vector_st;
+    variable vari71 : severity_level_vector_st;
+    variable vari72 : integer_vector_st;
+    variable vari73 : real_vector_st;
+    variable vari74 : time_vector_st;
+    variable vari75 : natural_vector_st;
+    variable vari76 : positive_vector_st;
+    variable vari54a : record_array_st;
+
+  BEGIN
+    var1 := NEW boolean '(C1);
+    var2 := NEW bit '(C2);
+    var3 := NEW character '(C3);
+    var4 := NEW severity_level '(C4);
+    var5 := NEW integer '(C5);
+    var6 := NEW real '(C6);
+    var7 := NEW time '(C7);
+    var8 := NEW natural '(C8);
+    var9 := NEW positive '(C9);
+    var10 := NEW string '(C10);
+    var11 := NEW bit_vector '(C11);
+    var12 := NEW boolean_vector '(C12);
+    var13 := NEW severity_level_vector '(C13);
+    var14 := NEW integer_vector '(C14);
+    var15 := NEW real_vector '(C15);
+    var16 := NEW time_vector '(C16);
+    var17 := NEW natural_vector '(C17);
+    var18 := NEW positive_vector '(C18);
+    var19 := NEW boolean_cons_vector '(C19);
+    var20 := NEW severity_level_cons_vector '(C20);
+    var21 := NEW integer_cons_vector '(C21);
+    var22 := NEW real_cons_vector '(C22);
+    var23 := NEW time_cons_vector '(C23);
+    var24 := NEW natural_cons_vector '(C24);
+    var25 := NEW positive_cons_vector '(C25);
+    var26 := NEW boolean_cons_vectorofvector '(C26);
+    var27 := NEW severity_level_cons_vectorofvector '(C27);
+    var28 := NEW integer_cons_vectorofvector '(C28);
+    var29 := NEW real_cons_vectorofvector '(C29);
+    var30 := NEW time_cons_vectorofvector '(C30);
+    var31 := NEW natural_cons_vectorofvector '(C31);
+    var32 := NEW positive_cons_vectorofvector '(C32);
+--var33 := NEW s2boolean_vector '(C33);
+--var34 := NEW s2bit_vector '(C34);
+--var35 := NEW s2char_vector '(C35);
+--var36 := NEW s2severity_level_vector '(C36);
+--var37 := NEW s2integer_vector '(C37);
+--var38 := NEW s2real_vector '(C38);
+--var39 := NEW s2time_vector '(C39);
+--var40 := NEW s2positive_vector '(C40);
+    var41 := NEW s2boolean_cons_vector '(C41);
+    var42 := NEW s2bit_cons_vector '(C42);
+    var43 := NEW s2char_cons_vector '(C43);
+    var44 := NEW s2severity_level_cons_vector '(C44);
+    var45 := NEW s2integer_cons_vector '(C45);
+    var46 := NEW s2real_cons_vector '(C46);
+    var47 := NEW s2time_cons_vector '(C47);
+    var48 := NEW s2natural_cons_vector '(C48);
+    var49 := NEW s2positive_cons_vector '(C49);
+    var50 := NEW record_std_package '(C50);
+    var51 := NEW record_cons_array '(C51);
+    var52 := NEW record_2cons_array '(C52);
+    var53 := NEW record_cons_arrayofarray '(C53);
+--var54 := NEW record_of_ptr '(C54);
+--var54a := NEW record_array_st '(C54a);
+--var55 := NEW record_of_records '(C55);
+    var56 := NEW four_value '(C56);
+    var57 := NEW four_value_map '(C57);
+    var58 := NEW binary '(C58);
+    var59 := NEW four_value_vector '(C59);
+    var60 := NEW byte '(C60);
+    var61 := NEW word '(C61);
+    var62 := NEW four_value_state '(C62);
+    var63 := NEW state_vector '(C63);
+    var64 := NEW primary_memory '(C64);
+    var65 := NEW primary_memory_module '(C65);
+    var66 := NEW whole_memory '(C66);
+    var67 := NEW current '(C67);
+    var68 := NEW resistance '(C68);
+    var69 := NEW delay '(C69);
+    var70 := NEW boolean_vector_st '(C70);
+    var71 := NEW severity_level_vector_st '(C71);
+    var72 := NEW integer_vector_st '(C72);
+    var73 := NEW real_vector_st '(C73);
+    var74 := NEW time_vector_st '(C74);
+    var75 := NEW natural_vector_st '(C75);
+    var76 := NEW positive_vector_st '(C76);
+    
+    vari1 := var1.all;
+    vari2 := var2.all;
+    vari3 := var3.all;
+    vari4 := var4.all;
+    vari5 := var5.all;
+    vari6 := var6.all;
+    vari7 := var7.all;
+    vari8 := var8.all;
+    vari9 := var9.all;
+    vari10 := var10.all;
+    vari11 := var11.all;
+    vari12 := var12.all;
+    vari13 := var13.all;
+    vari14 := var14.all;
+    vari15 := var15.all;
+    vari16 := var16.all;
+    vari17 := var17.all;
+    vari18 := var18.all;
+    vari19 := var19.all;
+    vari20 := var20.all;
+    vari21 := var21.all;
+    vari22 := var22.all;
+    vari23 := var23.all;
+    vari24 := var24.all;
+    vari25 := var25.all;
+    vari26 := var26.all;
+    vari27 := var27.all;
+    vari28 := var28.all;
+    vari29 := var29.all;
+    vari30 := var30.all;
+    vari31 := var31.all;
+    vari32 := var32.all;
+--vari33 := var33.all;
+--vari34 := var34.all;
+--vari35 := var35.all;
+--vari36 := var36.all;
+--vari37 := var37.all;
+--vari38 := var38.all;
+--vari39 := var39.all;
+--vari40 := var40.all;
+    vari41 := var41.all;
+    vari42 := var42.all;
+    vari43 := var43.all;
+    vari44 := var44.all;
+    vari45 := var45.all;
+    vari46 := var46.all;
+    vari47 := var47.all;
+    vari48 := var48.all;
+    vari49 := var49.all;
+    vari50 := var50.all;
+    vari51 := var51.all;
+    vari52 := var52.all;
+    vari53 := var53.all;
+--vari54 := var54.all;
+--vari55 := var55.all;
+    vari56 := var56.all;
+    vari57 := var57.all;
+    vari58 := var58.all;
+    vari59 := var59.all;
+    vari60 := var60.all;
+    vari61 := var61.all;
+    vari62 := var62.all;
+    vari63 := var63.all;
+    vari64 := var64.all;
+    vari65 := var65.all;
+    vari66 := var66.all;
+    vari67 := var67.all;
+    vari68 := var68.all;
+    vari69 := var69.all;
+    vari70 := var70.all;
+    vari71 := var71.all;
+    vari72 := var72.all;
+    vari73 := var73.all;
+    vari74 := var74.all;
+    vari75 := var75.all;
+    vari76 := var76.all;
+--vari54a := var54a.all;
+
+    ASSERT vari1= C1    report "Improper Assignment of vari1" SEVERITY FAILURE;
+    ASSERT vari2 = C2    report "Improper Assignment of vari2" SEVERITY FAILURE;
+    ASSERT vari3 = C3    report "Improper Assignment of vari3" SEVERITY FAILURE;
+    ASSERT vari4 = C4    report "Improper Assignment of vari4" SEVERITY FAILURE;
+    ASSERT vari5 = C5    report "Improper Assignment of vari5" SEVERITY FAILURE;
+    ASSERT vari6 = C6    report "Improper Assignment of vari6" SEVERITY FAILURE;
+    ASSERT vari7 = C7    report "Improper Assignment of vari7" SEVERITY FAILURE;
+    ASSERT vari8 = C8    report "Improper Assignment of vari8" SEVERITY FAILURE;
+    ASSERT vari9 = C9    report "Improper Assignment of vari9" SEVERITY FAILURE;
+    ASSERT vari10 = C10    report "Improper Assignment of vari10" SEVERITY FAILURE;
+    ASSERT vari11 = C11    report "Improper Assignment of vari11" SEVERITY FAILURE;
+    ASSERT vari12 = C12    report "Improper Assignment of vari12" SEVERITY FAILURE;
+    ASSERT vari13 = C13    report "Improper Assignment of vari13" SEVERITY FAILURE;
+    ASSERT vari14 = C14    report "Improper Assignment of vari14" SEVERITY FAILURE;
+    ASSERT vari15 = C15    report "Improper Assignment of vari15" SEVERITY FAILURE;
+    ASSERT vari16 = C16    report "Improper Assignment of vari16" SEVERITY FAILURE;
+    ASSERT vari17 = C17    report "Improper Assignment of vari17" SEVERITY FAILURE;
+    ASSERT vari18 = C18    report "Improper Assignment of vari18" SEVERITY FAILURE;
+    ASSERT vari19 = C19    report "Improper Assignment of vari19" SEVERITY FAILURE;
+    ASSERT vari20 = C20    report "Improper Assignment of vari20" SEVERITY FAILURE;
+    ASSERT vari21 = C21    report "Improper Assignment of vari21" SEVERITY FAILURE;
+    ASSERT vari22 = C22    report "Improper Assignment of vari22" SEVERITY FAILURE;
+    ASSERT vari23 = C23    report "Improper Assignment of vari23" SEVERITY FAILURE;
+    ASSERT vari24 = C24    report "Improper Assignment of vari24" SEVERITY FAILURE;
+    ASSERT vari25 = C25    report "Improper Assignment of vari25" SEVERITY FAILURE;
+    ASSERT vari26 = C26    report "Improper Assignment of vari26" SEVERITY FAILURE;
+    ASSERT vari27 = C27    report "Improper Assignment of vari27" SEVERITY FAILURE;
+    ASSERT vari28 = C28    report "Improper Assignment of vari28" SEVERITY FAILURE;
+    ASSERT vari29 = C29    report "Improper Assignment of vari29" SEVERITY FAILURE;
+    ASSERT vari30 = C30    report "Improper Assignment of vari30" SEVERITY FAILURE; 
+    ASSERT vari31 = C31    report "Improper Assignment of vari31" SEVERITY FAILURE; 
+    ASSERT vari32 = C32    report "Improper Assignment of vari32" SEVERITY FAILURE; 
+--ASSERT vari33 = C33    report "Improper Assignment of vari33" SEVERITY FAILURE; 
+--ASSERT vari34 = C34    report "Improper Assignment of vari34" SEVERITY FAILURE; 
+--ASSERT vari35 = C35    report "Improper Assignment of vari35" SEVERITY FAILURE; 
+--ASSERT vari36 = C36    report "Improper Assignment of vari36" SEVERITY FAILURE; 
+--ASSERT vari37 = C37    report "Improper Assignment of vari37" SEVERITY FAILURE; 
+--ASSERT vari38 = C38    report "Improper Assignment of vari38" SEVERITY FAILURE; 
+--ASSERT vari39 = C39    report "Improper Assignment of vari39" SEVERITY FAILURE; 
+--ASSERT vari40 = C40    report "Improper Assignment of vari40" SEVERITY FAILURE; 
+    ASSERT vari41 = C41    report "Improper Assignment of vari41" SEVERITY FAILURE; 
+    ASSERT vari42 = C42    report "Improper Assignment of vari42" SEVERITY FAILURE; 
+    ASSERT vari43 = C43    report "Improper Assignment of vari43" SEVERITY FAILURE; 
+    ASSERT vari44 = C44    report "Improper Assignment of vari44" SEVERITY FAILURE; 
+    ASSERT vari45 = C45    report "Improper Assignment of vari45" SEVERITY FAILURE; 
+    ASSERT vari46 = C46    report "Improper Assignment of vari46" SEVERITY FAILURE; 
+    ASSERT vari47 = C47    report "Improper Assignment of vari47" SEVERITY FAILURE; 
+    ASSERT vari48 = C48    report "Improper Assignment of vari48" SEVERITY FAILURE; 
+    ASSERT vari49 = C49    report "Improper Assignment of vari49" SEVERITY FAILURE;
+    ASSERT vari50 = C50    report "Improper Assignment of vari50" SEVERITY FAILURE;
+    ASSERT vari51 = C51    report "Improper Assignment of vari51" SEVERITY FAILURE;
+    ASSERT vari52 = C52    report "Improper Assignment of vari52" SEVERITY FAILURE;
+    ASSERT vari53 = C53    report "Improper Assignment of vari53" SEVERITY FAILURE;
+--ASSERT vari54 = C54    report "Improper Assignment of vari54" SEVERITY FAILURE;
+--ASSERT vari54a = C54a    report "Improper Assignment of vari54a" SEVERITY FAILURE;
+--ASSERT vari55 = C55    report "Improper Assignment of vari55" SEVERITY FAILURE;
+    ASSERT vari56 = C56    report "Improper Assignment of vari56" SEVERITY FAILURE;
+    ASSERT vari57 = C57    report "Improper Assignment of vari57" SEVERITY FAILURE;
+    ASSERT vari58 = C58    report "Improper Assignment of vari58" SEVERITY FAILURE;
+    ASSERT vari59 = C59    report "Improper Assignment of vari59" SEVERITY FAILURE;
+    ASSERT vari60 = C60    report "Improper Assignment of vari60" SEVERITY FAILURE;
+    ASSERT vari61 = C61    report "Improper Assignment of vari61" SEVERITY FAILURE;
+    ASSERT vari62 = C62    report "Improper Assignment of vari62" SEVERITY FAILURE;
+    ASSERT vari63 = C63    report "Improper Assignment of vari63" SEVERITY FAILURE;
+    ASSERT vari64 = C64    report "Improper Assignment of vari64" SEVERITY FAILURE;
+    ASSERT vari65 = C65    report "Improper Assignment of vari65" SEVERITY FAILURE;
+    ASSERT vari66 = C66    report "Improper Assignment of vari66" SEVERITY FAILURE;
+    ASSERT vari67 = C67    report "Improper Assignment of vari67" SEVERITY FAILURE;
+    ASSERT vari68 = C68    report "Improper Assignment of vari68" SEVERITY FAILURE;
+    ASSERT vari69 = C69    report "Improper Assignment of vari69" SEVERITY FAILURE;
+    ASSERT vari70 = C70    report "Improper Assignment of vari70" SEVERITY FAILURE;
+    ASSERT vari71 = C71    report "Improper Assignment of vari71" SEVERITY FAILURE;
+    ASSERT vari72 = C72    report "Improper Assignment of vari72" SEVERITY FAILURE;
+    ASSERT vari73 = C73    report "Improper Assignment of vari73" SEVERITY FAILURE;
+    ASSERT vari74 = C74    report "Improper Assignment of vari74" SEVERITY FAILURE;
+    ASSERT vari74 = C74    report "Improper Assignment of vari74" SEVERITY FAILURE;
+    ASSERT vari75 = C75    report "Improper Assignment of vari75" SEVERITY FAILURE;
+    ASSERT vari76 = C76    report "Improper Assignment of vari76" SEVERITY FAILURE;
+
+    assert NOT(   vari1 = C1    and 
+                  vari2 = C2    and 
+                  vari3 = C3    and 
+                  vari4 = C4    and 
+                  vari5 = C5    and 
+                  vari6 = C6    and 
+                  vari7 = C7    and 
+                  vari8 = C8    and 
+                  vari9 = C9    and 
+                  vari10 = C10    and 
+                  vari11 = C11    and 
+                  vari12 = C12    and 
+                  vari13 = C13    and 
+                  vari14 = C14    and 
+                  vari15 = C15    and 
+                  vari16 = C16    and 
+                  vari17 = C17    and 
+                  vari18 = C18    and 
+                  vari19 = C19    and 
+                  vari20 = C20    and 
+                  vari21 = C21    and 
+                  vari22 = C22    and 
+                  vari23 = C23    and 
+                  vari24 = C24    and 
+                  vari25 = C25    and 
+                  vari26 = C26    and 
+                  vari27 = C27    and 
+                  vari28 = C28    and 
+                  vari29 = C29    and 
+                  vari30 = C30    and 
+                  vari31 = C31    and 
+                  vari32 = C32    and 
+--      vari33 = C33    and 
+--      vari34 = C34    and 
+--      vari35 = C35    and 
+--      vari36 = C36    and 
+--      vari37 = C37    and 
+--      vari38 = C38    and 
+--      vari39 = C39    and 
+--      vari40 = C40    and 
+                  vari41 = C41    and 
+                  vari42 = C42    and 
+                  vari43 = C43    and 
+                  vari44 = C44    and 
+                  vari45 = C45    and 
+                  vari46 = C46    and 
+                  vari47 = C47    and 
+                  vari48 = C48    and 
+                  vari49 = C49    and 
+                  vari50 = C50    and 
+                  vari51 = C51    and 
+                  vari52 = C52    and 
+                  vari53 = C53    and 
+--      vari54 = C54    and 
+--      vari54a = C54a    and 
+--      vari55 = C55    and 
+                  vari56 = C56    and 
+                  vari57 = C57    and 
+                  vari58 = C58    and 
+                  vari59 = C59    and 
+                  vari60 = C60    and 
+                  vari61 = C61    and 
+                  vari62 = C62    and 
+                  vari63 = C63    and 
+                  vari64 = C64    and 
+                  vari65 = C65    and 
+                  vari66 = C66    and 
+                  vari67 = C67    and 
+                  vari68 = C68    and 
+                  vari69 = C69    and 
+                  vari70 = C70    and 
+                  vari71 = C71    and 
+                  vari72 = C72    and 
+                  vari73 = C73    and 
+                  vari74 = C74    and 
+                  vari75 = C75    and 
+                  vari76 = C76    ) 
+      report "***PASSED TEST: c06s03b00x00p06n01i00987" 
+      severity NOTE;
+    assert (   vari1 = C1    and 
+               vari2 = C2    and 
+               vari3 = C3    and 
+               vari4 = C4    and 
+               vari5 = C5    and 
+               vari6 = C6    and 
+               vari7 = C7    and 
+               vari8 = C8    and 
+               vari9 = C9    and 
+               vari10 = C10    and 
+               vari11 = C11    and 
+               vari12 = C12    and 
+               vari13 = C13    and 
+               vari14 = C14    and 
+               vari15 = C15    and 
+               vari16 = C16    and 
+               vari17 = C17    and 
+               vari18 = C18    and 
+               vari19 = C19    and 
+               vari20 = C20    and 
+               vari21 = C21    and 
+               vari22 = C22    and 
+               vari23 = C23    and 
+               vari24 = C24    and 
+               vari25 = C25    and 
+               vari26 = C26    and 
+               vari27 = C27    and 
+               vari28 = C28    and 
+               vari29 = C29    and 
+               vari30 = C30    and 
+               vari31 = C31    and 
+               vari32 = C32    and 
+--      vari33 = C33    and 
+--      vari34 = C34    and 
+--      vari35 = C35    and 
+--      vari36 = C36    and 
+--      vari37 = C37    and 
+--      vari38 = C38    and 
+--      vari39 = C39    and 
+--      vari40 = C40    and 
+               vari41 = C41    and 
+               vari42 = C42    and 
+               vari43 = C43    and 
+               vari44 = C44    and 
+               vari45 = C45    and 
+               vari46 = C46    and 
+               vari47 = C47    and 
+               vari48 = C48    and 
+               vari49 = C49    and 
+               vari50 = C50    and 
+               vari51 = C51    and 
+               vari52 = C52    and 
+               vari53 = C53    and 
+--      vari54 = C54    and 
+--      vari54a = C54a    and 
+--      vari55 = C55    and 
+               vari56 = C56    and 
+               vari57 = C57    and 
+               vari58 = C58    and 
+               vari59 = C59    and 
+               vari60 = C60    and 
+               vari61 = C61    and 
+               vari62 = C62    and 
+               vari63 = C63    and 
+               vari64 = C64    and 
+               vari65 = C65    and 
+               vari66 = C66    and 
+               vari67 = C67    and 
+               vari68 = C68    and 
+               vari69 = C69    and 
+               vari70 = C70    and 
+               vari71 = C71    and 
+               vari72 = C72    and 
+               vari73 = C73    and 
+               vari74 = C74    and 
+               vari75 = C75    and 
+               vari76 = C76    ) 
+      report "***FAILED TEST: c06s03b00x00p06n01i00987 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p06n01i00987arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc988.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc988.vhd
new file mode 100644
index 0000000..bd600d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc988.vhd
@@ -0,0 +1,916 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc988.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p06n01i00988pkg is
+------------------------------------USING ONLY WHITE MATTER---------------------------------
+--------------------------------------------------------------------------------------------
+---ACCESS TYPE FROM STANDARD PACKAGE
+
+  type boolean_ptr is access boolean ;                                  --simple boolean type   
+  type bit_ptr is access bit ;                                          --simple bit type
+  type char_ptr is access character;                                    --simple character type
+  type severity_level_ptr is access severity_level;                     --simple severity type
+  type integer_ptr is access integer;                                   --simple integer type   
+  type real_ptr is access real;                                         --simple real type
+  type time_ptr is access time;                                         --simple time type
+  type natural_ptr is access natural;                                   --simple natural type
+  type positive_ptr is access positive;                                 --simple positive type
+  type string_ptr is access string;                                     --simple string type
+  type bit_vector_ptr is access bit_vector;                             --simple bit_vector type
+
+--------------------------------------------------------------------------------------------
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+
+---------------------------------------------------------------------------------------------
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  subtype boolean_vector_st is boolean_vector(0 to 15);
+  subtype severity_level_vector_st is  severity_level_vector(0 to 15);
+  subtype integer_vector_st is  integer_vector(0 to 15);
+  subtype real_vector_st is  real_vector(0 to 15);
+  subtype time_vector_st is  time_vector(0 to 15);
+  subtype natural_vector_st is  natural_vector(0 to 15);
+  subtype positive_vector_st is  positive_vector(0 to 15);
+  
+---------------------------------------------------------------------------------------------
+--CONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vector is array (15 downto 0) of boolean;
+  type severity_level_cons_vector is array (15 downto 0) of severity_level;
+  type integer_cons_vector is array (15 downto 0) of integer;
+  type real_cons_vector is array (15 downto 0) of real;
+  type time_cons_vector is array (15 downto 0) of time;
+  type natural_cons_vector is array (15 downto 0) of natural;
+  type positive_cons_vector is array (15 downto 0) of positive;
+  
+---------------------------------------------------------------------------------------------
+  
+--CONSTRAINED ARRAY OF ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
+  type severity_level_cons_vectorofvector is array (0 to 15) of severity_level_cons_vector;
+  type integer_cons_vectorofvector is array (0 to 15) of integer_cons_vector ;
+  type real_cons_vectorofvector is array (0 to 15) of real_cons_vector;
+  type time_cons_vectorofvector is array (0 to 15) of time_cons_vector;
+  type natural_cons_vectorofvector is array (0 to 15) of natural_cons_vector;
+  type positive_cons_vectorofvector is array (0 to 15) of positive_cons_vector;
+  
+---------------------------------------------------------------------------------------------
+
+--UNCONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type s2boolean_vector is array (natural range <>,natural range <>) of boolean;
+  type s2bit_vector is array (natural range<>,natural range <>) of bit;
+  type s2char_vector is array (natural range<>,natural range <>) of character;
+  type s2severity_level_vector is array (natural range <>,natural range <>) of severity_level;
+  type s2integer_vector is array (natural range <>,natural range <>) of integer;
+  type s2real_vector is array (natural range <>,natural range <>) of real;
+  type s2time_vector is array (natural range <>,natural range <>) of time;
+  type s2natural_vector is array (natural range <>,natural range <>) of natural;
+  type s2positive_vector is array (natural range <>,natural range <>) of positive;
+  
+----------------------------------------------------------------------------------------------
+  
+--CONSTRAINED 2-DIMENSIONAL ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural
+  type column is range 1 to 64;
+  type row is range 1 to 1024;
+  type s2boolean_cons_vector is array (row,column) of boolean;
+  type s2bit_cons_vector is array (row,column) of bit;
+  type s2char_cons_vector is array (row,column) of character;
+  type s2severity_level_cons_vector is array (row,column) of severity_level;
+  type s2integer_cons_vector is array (row,column) of integer;
+  type s2real_cons_vector is array (row,column) of real;
+  type s2time_cons_vector is array (row,column) of time;
+  type s2natural_cons_vector is array (row,column) of natural;
+  type s2positive_cons_vector is array (row,column) of positive;
+  
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS FROM STANDARD PACKAGE
+  
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  
+  
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS AS UNCONSTRAINT ARRAYS
+  
+  type record_array_st is record
+                            a:boolean_vector_st;
+                            b:severity_level_vector_st;
+                            c:integer_vector_st;
+                            d:real_vector_st;
+                            e:time_vector_st;
+                            f:natural_vector_st;
+                            g:positive_vector_st;
+                          end record;
+  
+-----------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS AS CONSTRAINT ARRAYS
+  
+  type record_cons_array is record
+                              a:boolean_cons_vector;
+                              b:severity_level_cons_vector;
+                              c:integer_cons_vector;
+                              d:real_cons_vector;
+                              e:time_cons_vector;
+                              f:natural_cons_vector;
+                              g:positive_cons_vector;
+                            end record;
+  
+-----------------------------------------------------------------------------------------------
+  
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS
+  
+  type record_2cons_array is record
+                               a:s2boolean_cons_vector;
+                               b:s2bit_cons_vector;
+                               c:s2char_cons_vector;
+                               d:s2severity_level_cons_vector;
+                               e:s2integer_cons_vector;
+                               f:s2real_cons_vector;
+                               g:s2time_cons_vector;
+                               h:s2natural_cons_vector;
+                               i:s2positive_cons_vector;
+                             end record;
+
+-----------------------------------------------------------------------------------------------
+--RECORD WITH FIELDS AS 2-DIMENSIONAL CONSTRAINED ARRAYS OF ARRAY
+  type record_cons_arrayofarray is record
+                                     a:boolean_cons_vectorofvector;
+                                     b:severity_level_cons_vectorofvector;
+                                     c:integer_cons_vectorofvector;
+                                     d:real_cons_vectorofvector;
+                                     e:time_cons_vectorofvector;
+                                     f:natural_cons_vectorofvector;
+                                     g:positive_cons_vectorofvector;
+                                   end record;
+  
+-----------------------------------------------------------------------------------------------
+  type record_of_ptr is record
+                          a:boolean_ptr ;                                   --simple boolean type
+                          b:bit_ptr;                                        --simple bit type
+                          c:char_ptr;                                       --simple character type
+                          e:severity_level_ptr;                        --simple severity type
+                          f:integer_ptr;                                    --simple integer type
+                          g:  real_ptr ;                                    --simple real type
+                          h:time_ptr;                                       --simple time type
+                          i: natural_ptr;                                   --simple natural type
+
+                          j:positive_ptr;                                   --simple positive type
+                          k: string_ptr;                                    --simple string type
+                          l: bit_vector_ptr;                                --simple bit_vector type
+                        end record;
+  
+  
+-----------------------------------------------------------------------------------------------
+  type record_of_records is record
+                              a: record_std_package;
+                              c: record_cons_array;
+                              e: record_2cons_array;
+                              g: record_cons_arrayofarray;
+                              h: record_of_ptr;
+                              i: record_array_st;
+                            end record;
+  
+-----------------------------------------------------------------------------------------------
+--ACCESS TYPES FOR ABOVE
+-----------------------------------------------------------------------------------------------
+  
+  type boolean_vector_ptr is access boolean_vector;
+  type severity_level_vector_ptr is access severity_level_vector;
+  type integer_vector_ptr is access integer_vector;
+  type real_vector_ptr is access real_vector;
+  type time_vector_ptr is access time_vector;
+  type natural_vector_ptr is access natural_vector;
+  type positive_vector_ptr is access positive_vector;
+-----------------------------------------------------------------------------------------------
+  type boolean_vector_st_ptr is access boolean_vector_st;--(0 to 15);
+  type severity_level_vector_st_ptr is access  severity_level_vector_st;--(0 to 15);
+  type integer_vector_st_ptr is access  integer_vector_st;--(0 to 15);
+  type real_vector_st_ptr is access  real_vector_st;--(0 to 15);
+  type time_vector_st_ptr is access  time_vector_st;--(0 to 15);
+  type natural_vector_st_ptr is access  natural_vector_st;--(0 to 15);
+  type positive_vector_st_ptr is access  positive_vector_st;--(0 to 15);
+-----------------------------------------------------------------------------------------------
+  type boolean_cons_vector_ptr is access boolean_cons_vector;
+  type severity_level_cons_vector_ptr is access severity_level_cons_vector;
+  type integer_cons_vector_ptr is access  integer_cons_vector;
+  type real_cons_vector_ptr is access real_cons_vector;
+  type time_cons_vector_ptr is access time_cons_vector;
+  type natural_cons_vector_ptr is access natural_cons_vector;
+  type positive_cons_vector_ptr is access  positive_cons_vector;
+-----------------------------------------------------------------------------------------------
+  type boolean_cons_vectorofvector_ptr is access boolean_cons_vectorofvector;
+  type sev_lvl_cons_vecofvec_ptr is access severity_level_cons_vectorofvector;
+  type integer_cons_vectorofvector_ptr is access integer_cons_vectorofvector;
+  type real_cons_vectorofvector_ptr is access  real_cons_vectorofvector;
+  type time_cons_vectorofvector_ptr is access time_cons_vectorofvector;
+  type natural_cons_vectorofvector_ptr is access natural_cons_vectorofvector;
+  type posi_cons_vecofvec_ptr is access positive_cons_vectorofvector;
+-----------------------------------------------------------------------------------------------
+  type s2boolean_vector_ptr is access s2boolean_vector;
+  type s2bit_vector_ptr is access  s2bit_vector;
+  type s2char_vector_ptr is access s2char_vector;
+  type s2severity_level_vector_ptr is access s2severity_level_vector;
+  type s2integer_vector_ptr is access s2integer_vector;
+  type s2real_vector_ptr is access s2real_vector;
+  type s2time_vector_ptr is access  s2time_vector;
+  type s2positive_vector_ptr is access s2positive_vector;
+-----------------------------------------------------------------------------------------------
+  type s2boolean_cons_vector_ptr is access s2boolean_cons_vector;
+  type s2bit_cons_vector_ptr is access s2bit_cons_vector;
+  type s2char_cons_vector_ptr is access  s2char_cons_vector;
+  type s2sev_lvl_cons_vec_ptr is access s2severity_level_cons_vector;
+  type s2integer_cons_vector_ptr is access  s2integer_cons_vector;
+  type s2real_cons_vector_ptr is access  s2real_cons_vector;
+  type s2time_cons_vector_ptr is access  s2time_cons_vector;
+  type s2natural_cons_vector_ptr is access s2natural_cons_vector;
+  type s2positive_cons_vector_ptr is access s2positive_cons_vector;
+----------------------------------------------------------------------------------------------
+  type record_std_package_ptr is access record_std_package;
+  type record_cons_array_ptr is access  record_cons_array;
+  type record_2cons_array_ptr is access  record_2cons_array;
+  type record_cons_arrayofarray_ptr is access  record_cons_arrayofarray;
+  type record_of_ptr_ptr is access record_of_ptr;
+  type record_of_records_ptr is access record_of_records;
+  type record_array_st_ptr is access record_array_st;
+  
+-----------------------------------------------------------------------------------------------
+-------------------------USING PARTIAL GRAY & PARTIAL WHITE MATTER-----------------------------
+  
+  
+  
+  type four_value is ('Z','0','1','X');                                 --enumerated type
+  type four_value_map is array(four_value) of boolean;
+  subtype binary is four_value range '0' to '1';
+  type four_value_vector is array (natural range <>) of four_value;     --unconstraint array of
+  type byte is array(0 to 7) of bit;
+  subtype word is bit_vector(0 to  15);                                 --constrained array
+  function resolution(i:in four_value_vector) return four_value;        --bus resolution
+  subtype four_value_state is resolution four_value;                    --function type
+  type state_vector is array (natural range <>) of four_value_state;    --unconstraint array of
+  constant size :integer := 63;
+  type primary_memory is array(0 to size) of word;                      --array of an array
+  type primary_memory_module is                                         --record with field
+    record                                                                --as an array
+      enable:binary;
+      memory_number:primary_memory;
+    end record;
+  type whole_memory is array(0 to size) of primary_memory_module;       --array of a complex record
+  type current is range -2147483647 to +2147483647
+    units
+      nA;
+      uA = 1000 nA;
+      mA = 1000 uA;
+      A  = 1000 mA;
+    end units;
+  type resistance is range -2147483647 to +2147483647
+    units
+      uOhm;
+      mOhm = 1000 uOhm;
+      Ohm = 1000 mOhm;
+      KOhm  = 1000 Ohm;
+    end units;
+  subtype delay is integer range 1 to 10;
+  
+  type four_value_ptr is access four_value;
+  type four_value_map_ptr is access four_value_map;
+  type binary_ptr is access binary;
+  type four_value_vector_ptr is access four_value_vector;               --ennumerated type
+  type byte_ptr is access byte;
+  type word_ptr is access word;
+  type four_value_state_ptr is access four_value_state;
+  type state_vector_ptr is access state_vector;                         --type returned by resolu.
+  type primary_memory_ptr is access primary_memory;
+  type primary_memory_module_ptr is access primary_memory_module;
+  type whole_memory_ptr is access whole_memory;
+  type current_ptr is access current;
+  type resistance_ptr is access resistance;
+  type delay_ptr is access delay;
+-------------------------------------------------------------------------------------------
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  constant C10 : string := "shishir";
+  constant C11 : bit_vector := B"0011";
+  constant C12 : boolean_vector := (true,false);
+  constant C13 : severity_level_vector := (note,error);
+  constant C14 : integer_vector := (1,2,3,4);
+  constant C15 : real_vector := (1.0,2.0,3.0,4.0);
+  constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17 : natural_vector := (1,2,3,4);
+  constant C18 : positive_vector := (1,2,3,4);
+  constant C19 : boolean_cons_vector := (others => C1);
+  constant C20 : severity_level_cons_vector := (others => C4);
+  constant C21 : integer_cons_vector := (others => C5);
+  constant C22 : real_cons_vector := (others => C6);
+  constant C23 : time_cons_vector :=  (others => C7);
+  constant C24 : natural_cons_vector :=  (others => C8);
+  constant C25 : positive_cons_vector :=  (others => C9);
+  
+  constant C70 : boolean_vector_st :=(others => C1);
+  constant C71 :  severity_level_vector_st:= (others => C4);
+  constant C72 :  integer_vector_st:=(others => C5);
+  constant C73 :  real_vector_st:=(others => C6);
+  constant C74 :  time_vector_st:=(others => C7);
+  constant C75 :  natural_vector_st:=(others => C8);
+  constant C76 : positive_vector_st:=(others => C9);
+  
+  
+  constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
+  constant C27 : severity_level_cons_vectorofvector :=  (others => (others => C4));
+  constant C28 : integer_cons_vectorofvector := (others => (others => C5));
+  constant C29 : real_cons_vectorofvector := (others => (others => C6));
+  constant C30 : time_cons_vectorofvector := (others => (others => C7));
+  constant C31 : natural_cons_vectorofvector := (others => (others => C8));
+  constant C32 : positive_cons_vectorofvector := (others => (others => C9));
+--constant C33 : s2boolean_vector := ((true,true),(false,false));
+--constant C34 : s2bit_vector := ((B"0011"),(B"1100"));
+--constant C35 : s2char_vector := (('s','h'),('i','s'));
+--constant C36 : s2severity_level_vector := ((note,error),(error,note));
+--constant C37 : s2integer_vector := ((1,2,3,4),(4,3,2,1));
+--constant C38 : s2real_vector := ((1.0,2.0,3.0,4.0),(4.0,3.0,2.0,1.0));
+--constant C39 : s2time_vector := ((1 ns, 2 ns, 3 ns, 4 ns),(1 ns, 2 ns, 3 ns, 4 ns));
+--constant C40 : s2positive_vector := ((1,2,3,4),(4,3,2,1));
+  constant C41 : s2boolean_cons_vector := (others =>(others => C1));
+  constant C42 : s2bit_cons_vector := (others => (others => C2));
+  constant C43 : s2char_cons_vector := (others =>(others => C3));
+  constant C44 : s2severity_level_cons_vector := (others => (others => C4));
+  constant C45 : s2integer_cons_vector := (others => (others => C5));
+  constant C46 : s2real_cons_vector := (others =>(others => C6));
+  constant C47 : s2time_cons_vector := (others =>(others => C7));
+  constant C48 : s2natural_cons_vector := (others =>(others => C8));
+  constant C49 : s2positive_cons_vector := (others => (others => C9));
+  constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
+  constant C52 : record_2cons_array := (C41,C42,C43,C44,C45,C46,C47,C48,C49);
+  constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
+--constant C54 : record_of_ptr := (NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL);
+--constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
+--constant C55 : record_of_records := (C50,C51,C52,C53,C54,C54a);
+  constant C56 : four_value := 'Z';
+  constant C57 : four_value_map := (true,true,true,true);
+  constant C58 : binary := '0';
+  constant C59 : four_value_vector := ('1','0','1','0');
+  constant C60 : byte := (others => '0');
+  constant C61 : word := (others =>'0' );
+  constant C62 : four_value_state := 'Z';
+  constant C63 : state_vector := ('Z','Z','Z','Z');
+  constant C64 : primary_memory := (others => C61);
+  constant C65 : primary_memory_module := ('1',C64);
+  constant C66 : whole_memory := (others => C65);
+  constant C67 : current := 1 A;
+  constant C68 : resistance := 1 Ohm;
+  constant C69 : delay := 2;
+  
+end c06s03b00x00p06n01i00988pkg;
+
+package body c06s03b00x00p06n01i00988pkg is
+  function resolution(i:in four_value_vector) return four_value is
+    variable temp :four_value := 'Z';
+  begin
+    return temp;
+  end;
+end c06s03b00x00p06n01i00988pkg;
+
+use work.c06s03b00x00p06n01i00988pkg.all;
+
+ENTITY c06s03b00x00p06n01i00988ent IS
+END c06s03b00x00p06n01i00988ent;
+
+ARCHITECTURE c06s03b00x00p06n01i00988arch OF c06s03b00x00p06n01i00988ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable var1 : boolean_ptr := new boolean;
+    variable var2 : bit_ptr := new bit;
+    variable var3 : char_ptr := new character;
+    variable var4 : severity_level_ptr := new severity_level;
+    variable var5 : integer_ptr := new integer;
+    variable var6 : real_ptr := new real;
+    variable var7 : time_ptr := new time;
+    variable var8 : natural_ptr := new natural;
+    variable var9 : positive_ptr := new positive;
+    variable var10 : string_ptr := new string(1 to 7);
+    variable var11 : bit_vector_ptr := new bit_vector(0 to 3);
+    variable var12 : boolean_vector_ptr := new boolean_vector(0 to 1);
+    variable var13 : severity_level_vector_ptr := new severity_level_vector(0 to 1);
+    variable var14 : integer_vector_ptr := new integer_vector(0 to 3);
+    variable var15 : real_vector_ptr := new real_vector(0 to 3);
+    variable var16 : time_vector_ptr := new time_vector(0 to 3);
+    variable var17 : natural_vector_ptr := new natural_vector(0 to 3);
+    variable var18 : positive_vector_ptr := new positive_vector( 0 to 3);
+    variable var19 : boolean_cons_vector_ptr := new boolean_cons_vector;
+    variable var20 : severity_level_cons_vector_ptr := new severity_level_cons_vector;
+    variable var21 : integer_cons_vector_ptr := new integer_cons_vector;
+    variable var22 : real_cons_vector_ptr := new real_cons_vector;
+    variable var23 : time_cons_vector_ptr := new time_cons_vector;
+    variable var24 : natural_cons_vector_ptr := new natural_cons_vector;
+    variable var25 : positive_cons_vector_ptr := new positive_cons_vector;
+    variable var26 : boolean_cons_vectorofvector_ptr := new boolean_cons_vectorofvector;
+    variable var27 : sev_lvl_cons_vecofvec_ptr := new severity_level_cons_vectorofvector;
+    variable var28 : integer_cons_vectorofvector_ptr := new integer_cons_vectorofvector;
+    variable var29 : real_cons_vectorofvector_ptr := new real_cons_vectorofvector;
+    variable var30 : time_cons_vectorofvector_ptr := new time_cons_vectorofvector;
+    variable var31 : natural_cons_vectorofvector_ptr := new natural_cons_vectorofvector;
+    variable var32 : posi_cons_vecofvec_ptr := new positive_cons_vectorofvector;
+--variable var33 : s2boolean_vector_ptr := new s2boolean_vector;
+--variable var34 : s2bit_vector_ptr := new s2bit_vector;
+--variable var35 : s2char_vector_ptr := new s2char_vector;
+--variable var36 : s2severity_level_vector_ptr := new s2severity_level_vector;
+--variable var37 : s2integer_vector_ptr := new s2integer_vector;
+--variable var38 : s2real_vector_ptr := new s2real_vector;
+--variable var39 : s2time_vector_ptr := new s2time_vector;
+--variable var40 : s2positive_vector_ptr := new s2positive_vector;
+    variable var41 : s2boolean_cons_vector_ptr := new s2boolean_cons_vector;
+    variable var42 : s2bit_cons_vector_ptr := new s2bit_cons_vector;
+    variable var43 : s2char_cons_vector_ptr := new s2char_cons_vector;
+    variable var44 : s2sev_lvl_cons_vec_ptr := new s2severity_level_cons_vector;
+    variable var45 : s2integer_cons_vector_ptr := new s2integer_cons_vector;
+    variable var46 : s2real_cons_vector_ptr := new s2real_cons_vector;
+    variable var47 : s2time_cons_vector_ptr := new s2time_cons_vector;
+    variable var48 : s2natural_cons_vector_ptr := new s2natural_cons_vector;
+    variable var49 : s2positive_cons_vector_ptr := new s2positive_cons_vector;
+    variable var50 : record_std_package_ptr := new record_std_package;
+    variable var51 : record_cons_array_ptr := new record_cons_array;
+    variable var52 : record_2cons_array_ptr := new record_2cons_array;
+    variable var53 : record_cons_arrayofarray_ptr := new record_cons_arrayofarray;
+    variable var54 : record_of_ptr_ptr := new record_of_ptr;
+    variable var55 : record_of_records_ptr := new record_of_records;
+    variable var56 : four_value_ptr := new four_value;
+    variable var57 : four_value_map_ptr := new four_value_map;
+    variable var58 : binary_ptr := new binary;
+    variable var59 : four_value_vector_ptr := new four_value_vector(0 to 3);
+    variable var60 : byte_ptr := new byte;
+    variable var61 : word_ptr := new word;
+    variable var62 : four_value_state_ptr := new four_value_state;
+    variable var63 : state_vector_ptr := new state_vector(0 to 3);
+    variable var64 : primary_memory_ptr := new primary_memory;
+    variable var65 : primary_memory_module_ptr := new primary_memory_module;
+    variable var66 : whole_memory_ptr := new whole_memory;
+    variable var67 : current_ptr := new current;
+    variable var68 : resistance_ptr := new resistance;
+    variable var69 : delay_ptr := new delay;
+    variable var70 : boolean_vector_st_ptr := new boolean_vector_st;
+    variable var71 : severity_level_vector_st_ptr := new severity_level_vector_st;
+    variable var72 : integer_vector_st_ptr := new integer_vector_st;
+    variable var73 : real_vector_st_ptr := new real_vector_st;
+    variable var74 : time_vector_st_ptr := new time_vector_st;
+    variable var75 : natural_vector_st_ptr := new natural_vector_st;
+    variable var76 : positive_vector_st_ptr := new positive_vector_st;
+    variable var54a : record_array_st_ptr := new record_array_st;
+    
+    variable vari1 : boolean := C1;
+    variable vari2 : bit := C2;
+    variable vari3 : character := C3;
+    variable vari4 : severity_level := C4;
+    variable vari5 : integer := C5;
+    variable vari6 : real := C6;
+    variable vari7 : time := C7;
+    variable vari8 : natural := C8;
+    variable vari9 : positive := C9;
+    variable vari10 : string(1 to 7) := C10;
+    variable vari11 : bit_vector(0 to 3):= C11;
+    variable vari12 : boolean_vector(0 to 1):= C12;
+    variable vari13 : severity_level_vector(0 to 1) := C13;
+    variable vari14 : integer_vector(0 to 3) := C14;
+    variable vari15 : real_vector(0 to 3):= C15;
+    variable vari16 : time_vector(0 to 3):= C16;
+    variable vari17 : natural_vector(0 to 3):= C17;
+    variable vari18 : positive_vector(0 to 3):= C18;
+    variable vari19 : boolean_cons_vector := C19;
+    variable vari20 : severity_level_cons_vector := C20;
+    variable vari21 : integer_cons_vector := C21;
+    variable vari22 : real_cons_vector := C22;
+    variable vari23 : time_cons_vector := C23;
+    variable vari24 : natural_cons_vector := C24;
+    variable vari25 : positive_cons_vector := C25;
+    variable vari26 : boolean_cons_vectorofvector := C26;
+    variable vari27 : severity_level_cons_vectorofvector := C27;
+    variable vari28 : integer_cons_vectorofvector := C28;
+    variable vari29 : real_cons_vectorofvector := C29;
+    variable vari30 : time_cons_vectorofvector := C30;
+    variable vari31 : natural_cons_vectorofvector := C31;
+    variable vari32 : positive_cons_vectorofvector := C32;
+--variable vari33 : s2boolean_vector := C33;
+--variable vari34 : s2bit_vector := C34;
+--variable vari35 : s2char_vector := C35;
+--variable vari36 : s2severity_level_vector := C36;
+--variable vari37 : s2integer_vector := C37;
+--variable vari38 : s2real_vector := C38;
+--variable vari39 : s2time_vector := C39;
+--variable vari40 : s2positive_vector := C40;
+    variable vari41 : s2boolean_cons_vector := C41;
+    variable vari42 : s2bit_cons_vector := C42;
+    variable vari43 : s2char_cons_vector := C43;
+    variable vari44 : s2severity_level_cons_vector := C44;
+    variable vari45 : s2integer_cons_vector := C45;
+    variable vari46 : s2real_cons_vector := C46;
+    variable vari47 : s2time_cons_vector := C47;
+    variable vari48 : s2natural_cons_vector := C48;
+    variable vari49 : s2positive_cons_vector := C49;
+    variable vari50 : record_std_package := C50;
+    variable vari51 : record_cons_array := C51;
+    variable vari52 : record_2cons_array := C52;
+    variable vari53 : record_cons_arrayofarray := C53;
+--variable vari54 : record_of_ptr := C54;
+--variable vari55 : record_of_records := C55;
+    variable vari56 : four_value := C56;
+    variable vari57 : four_value_map := C57;
+    variable vari58 : binary := C58;
+    variable vari59 : four_value_vector(0 to 3):= C59;
+    variable vari60 : byte := C60;
+    variable vari61 : word := C61;
+    variable vari62 : four_value_state := C62;
+    variable vari63 : state_vector(0 to 3):= C63;
+    variable vari64 : primary_memory := C64;
+    variable vari65 : primary_memory_module := C65;
+    variable vari66 : whole_memory := C66;
+    variable vari67 : current := C67;
+    variable vari68 : resistance := C68;
+    variable vari69 : delay := C69;
+    variable vari70 : boolean_vector_st := C70;
+    variable vari71 : severity_level_vector_st := C71;
+    variable vari72 : integer_vector_st := C72;
+    variable vari73 : real_vector_st := C73;
+    variable vari74 : time_vector_st := C74;
+    variable vari75 : natural_vector_st := C75;
+    variable vari76 : positive_vector_st := C76;
+--variable vari54a : record_array_st := C54a;
+
+  BEGIN
+
+    var1.all := vari1;
+    var2.all := vari2;
+    var3.all := vari3;
+    var4.all := vari4;
+    var5.all := vari5;
+    var6.all := vari6;
+    var7.all := vari7;
+    var8.all := vari8;
+    var9.all := vari9;
+    var10.all := vari10;
+    var11.all := vari11;
+    var12.all := vari12;
+    var13.all := vari13;
+    var14.all := vari14;
+    var15.all := vari15;
+    var16.all := vari16;
+    var17.all := vari17;
+    var18.all := vari18;
+    var19.all := vari19;
+    var20.all := vari20;
+    var21.all := vari21;
+    var22.all := vari22;
+    var23.all := vari23;
+    var24.all := vari24;
+    var25.all := vari25;
+    var26.all := vari26;
+    var27.all := vari27;
+    var28.all := vari28;
+    var29.all := vari29;
+    var30.all := vari30;
+    var31.all := vari31;
+    var32.all := vari32;
+--var33.all := vari33;
+--var34.all := vari34;
+--var35.all := vari35;
+--var36.all := vari36;
+--var37.all := vari37;
+--var38.all := vari38;
+--var39.all := vari39;
+--var40.all := vari40;
+    var41.all := vari41;
+    var42.all := vari42;
+    var43.all := vari43;
+    var44.all := vari44;
+    var45.all := vari45;
+    var46.all := vari46;
+    var47.all := vari47;
+    var48.all := vari48;
+    var49.all := vari49;
+    var50.all := vari50;
+    var51.all := vari51;
+    var52.all := vari52;
+    var53.all := vari53;
+--var54.all := vari54;
+--var55.all := vari55;
+    var56.all := vari56;
+    var57.all := vari57;
+    var58.all := vari58;
+    var59.all := vari59;
+    var60.all := vari60;
+    var61.all := vari61;
+    var62.all := vari62;
+    var63.all := vari63;
+    var64.all := vari64;
+    var65.all := vari65;
+    var66.all := vari66;
+    var67.all := vari67;
+    var68.all := vari68;
+    var69.all := vari69;
+    var70.all := vari70;
+    var71.all := vari71;
+    var72.all := vari72;
+    var73.all := vari73;
+    var74.all := vari74;
+    var75.all := vari75;
+    var76.all := vari76;
+--var54a.all := vari54a;
+    
+    
+    
+    
+    ASSERT var1.all = C1 REPORT "Improper Assignment of var1" SEVERITY FAILURE;
+    ASSERT var2.all = C2 REPORT "Improper Assignment of var2" SEVERITY FAILURE;
+    ASSERT var3.all = C3 REPORT "Improper Assignment of var3" SEVERITY FAILURE;
+    ASSERT var4.all = C4 REPORT "Improper Assignment of var4" SEVERITY FAILURE;
+    ASSERT var5.all = C5 REPORT "Improper Assignment of var5" SEVERITY FAILURE;
+    ASSERT var6.all = C6 REPORT "Improper Assignment of var6" SEVERITY FAILURE;
+    ASSERT var7.all = C7 REPORT "Improper Assignment of var7" SEVERITY FAILURE;
+    ASSERT var8.all = C8 REPORT "Improper Assignment of var8" SEVERITY FAILURE;
+    ASSERT var9.all = C9 REPORT "Improper Assignment of var9" SEVERITY FAILURE;
+    ASSERT var10.all = C10 REPORT "Improper Assignment of var10" SEVERITY FAILURE;
+    ASSERT var11.all = C11 REPORT "Improper Assignment of var11" SEVERITY FAILURE;
+    ASSERT var12.all = C12 REPORT "Improper Assignment of var12" SEVERITY FAILURE;
+    ASSERT var13.all = C13 REPORT "Improper Assignment of var13" SEVERITY FAILURE;
+    ASSERT var14.all = C14 REPORT "Improper Assignment of var14" SEVERITY FAILURE;
+    ASSERT var15.all = C15 REPORT "Improper Assignment of var15" SEVERITY FAILURE;
+    ASSERT var16.all = C16 REPORT "Improper Assignment of var16" SEVERITY FAILURE;
+    ASSERT var17.all = C17 REPORT "Improper Assignment of var17" SEVERITY FAILURE;
+    ASSERT var18.all = C18 REPORT "Improper Assignment of var18" SEVERITY FAILURE;
+    ASSERT var19.all = C19 REPORT "Improper Assignment of var19" SEVERITY FAILURE;
+    ASSERT var20.all = C20 REPORT "Improper Assignment of var20" SEVERITY FAILURE;
+    ASSERT var21.all = C21 REPORT "Improper Assignment of var21" SEVERITY FAILURE;
+    ASSERT var22.all = C22 REPORT "Improper Assignment of var22" SEVERITY FAILURE;
+    ASSERT var23.all = C23 REPORT "Improper Assignment of var23" SEVERITY FAILURE;
+    ASSERT var24.all = C24 REPORT "Improper Assignment of var24" SEVERITY FAILURE;
+    ASSERT var25.all = C25 REPORT "Improper Assignment of var25" SEVERITY FAILURE;
+    ASSERT var26.all = C26 REPORT "Improper Assignment of var26" SEVERITY FAILURE;
+    ASSERT var27.all = C27 REPORT "Improper Assignment of var27" SEVERITY FAILURE;
+    ASSERT var28.all = C28 REPORT "Improper Assignment of var28" SEVERITY FAILURE;
+    ASSERT var29.all = C29 REPORT "Improper Assignment of var29" SEVERITY FAILURE;
+    ASSERT var30.all = C30 REPORT "Improper Assignment of var30" SEVERITY FAILURE;
+    ASSERT var31.all = C31 REPORT "Improper Assignment of var31" SEVERITY FAILURE;
+    ASSERT var32.all = C32 REPORT "Improper Assignment of var32" SEVERITY FAILURE;
+--ASSERT var33.all = C33 REPORT "Improper Assignment of var33" SEVERITY FAILURE;
+--ASSERT var34.all = C34 REPORT "Improper Assignment of var34" SEVERITY FAILURE;
+--ASSERT var35.all = C35 REPORT "Improper Assignment of var35" SEVERITY FAILURE;
+--ASSERT var36.all = C36 REPORT "Improper Assignment of var36" SEVERITY FAILURE;
+--ASSERT var37.all = C37 REPORT "Improper Assignment of var37" SEVERITY FAILURE;
+--ASSERT var38.all = C38 REPORT "Improper Assignment of var38" SEVERITY FAILURE;
+--ASSERT var39.all = C39 REPORT "Improper Assignment of var39" SEVERITY FAILURE;
+--ASSERT var40.all = C40 REPORT "Improper Assignment of var40" SEVERITY FAILURE;
+    ASSERT var41.all = C41 REPORT "Improper Assignment of var41" SEVERITY FAILURE;
+    ASSERT var42.all = C42 REPORT "Improper Assignment of var42" SEVERITY FAILURE;
+    ASSERT var43.all = C43 REPORT "Improper Assignment of var43" SEVERITY FAILURE;
+    ASSERT var44.all = C44 REPORT "Improper Assignment of var44" SEVERITY FAILURE;
+    ASSERT var45.all = C45 REPORT "Improper Assignment of var45" SEVERITY FAILURE;
+    ASSERT var46.all = C46 REPORT "Improper Assignment of var46" SEVERITY FAILURE;
+    ASSERT var47.all = C47 REPORT "Improper Assignment of var47" SEVERITY FAILURE;
+    ASSERT var48.all = C48 REPORT "Improper Assignment of var48" SEVERITY FAILURE;
+    ASSERT var49.all = C49 REPORT "Improper Assignment of var49" SEVERITY FAILURE;
+    ASSERT var50.all = C50 REPORT "Improper Assignment of var50" SEVERITY FAILURE;
+    ASSERT var51.all = C51 REPORT "Improper Assignment of var51" SEVERITY FAILURE;
+    ASSERT var52.all = C52 REPORT "Improper Assignment of var52" SEVERITY FAILURE;
+    ASSERT var53.all = C53 REPORT "Improper Assignment of var53" SEVERITY FAILURE;
+--ASSERT var54.all = C54 REPORT "Improper Assignment of var54" SEVERITY FAILURE;
+--ASSERT var54a.all = C54a REPORT "Improper Assignment of var54a" SEVERITY FAILURE;
+--ASSERT var55.all = C55 REPORT "Improper Assignment of var55" SEVERITY FAILURE;
+    ASSERT var56.all = C56 REPORT "Improper Assignment of var56" SEVERITY FAILURE;
+    ASSERT var57.all = C57 REPORT "Improper Assignment of var57" SEVERITY FAILURE;
+    ASSERT var58.all = C58 REPORT "Improper Assignment of var58" SEVERITY FAILURE;
+    ASSERT var59.all = C59 REPORT "Improper Assignment of var59" SEVERITY FAILURE;
+    ASSERT var60.all = C60 REPORT "Improper Assignment of var60" SEVERITY FAILURE;
+    ASSERT var61.all = C61 REPORT "Improper Assignment of var61" SEVERITY FAILURE;
+    ASSERT var62.all = C62 REPORT "Improper Assignment of var62" SEVERITY FAILURE;
+    ASSERT var63.all = C63 REPORT "Improper Assignment of var63" SEVERITY FAILURE;
+    ASSERT var64.all = C64 REPORT "Improper Assignment of var64" SEVERITY FAILURE;
+    ASSERT var65.all = C65 REPORT "Improper Assignment of var65" SEVERITY FAILURE;
+    ASSERT var66.all = C66 REPORT "Improper Assignment of var66" SEVERITY FAILURE;
+    ASSERT var67.all = C67 REPORT "Improper Assignment of var67" SEVERITY FAILURE;
+    ASSERT var68.all = C68 REPORT "Improper Assignment of var68" SEVERITY FAILURE;
+    ASSERT var69.all = C69 REPORT "Improper Assignment of var69" SEVERITY FAILURE;
+    ASSERT var70.all = C70 REPORT "Improper Assignment of var70" SEVERITY FAILURE;
+    ASSERT var71.all = C71 REPORT "Improper Assignment of var71" SEVERITY FAILURE;
+    ASSERT var72.all = C72 REPORT "Improper Assignment of var72" SEVERITY FAILURE;
+    ASSERT var73.all = C73 REPORT "Improper Assignment of var73" SEVERITY FAILURE;
+    ASSERT var74.all = C74 REPORT "Improper Assignment of var74" SEVERITY FAILURE;
+    ASSERT var75.all = C75 REPORT "Improper Assignment of var75" SEVERITY FAILURE;
+    ASSERT var76.all = C76 REPORT "Improper Assignment of var76" SEVERITY FAILURE;
+
+    assert NOT(   var1.all   = C1    and 
+                  var2.all   = C2    and 
+                  var3.all   = C3    and 
+                  var4.all   = C4    and 
+                  var5.all   = C5    and 
+                  var6.all   = C6    and 
+                  var7.all   = C7    and 
+                  var8.all   = C8    and 
+                  var9.all   = C9    and 
+                  var10.all   = C10    and 
+                  var11.all   = C11    and 
+                  var12.all   = C12    and 
+                  var13.all   = C13    and 
+                  var14.all   = C14    and 
+                  var15.all   = C15    and 
+                  var16.all   = C16    and 
+                  var17.all   = C17    and 
+                  var18.all   = C18    and 
+                  var19.all   = C19    and 
+                  var20.all   = C20    and 
+                  var21.all   = C21    and 
+                  var22.all   = C22    and 
+                  var23.all   = C23    and 
+                  var24.all   = C24    and 
+                  var25.all   = C25    and 
+                  var26.all   = C26    and 
+                  var27.all   = C27    and 
+                  var28.all   = C28    and 
+                  var29.all   = C29    and 
+                  var30.all   = C30    and 
+                  var31.all   = C31    and 
+                  var32.all   = C32    and 
+--      var33.all   = C33    and 
+--      var34.all   = C34    and 
+--      var35.all   = C35    and 
+--      var36.all   = C36    and 
+--      var37.all   = C37    and 
+--      var38.all   = C38    and 
+--      var39.all   = C39    and 
+--      var40.all   = C40    and 
+                  var41.all   = C41    and 
+                  var42.all   = C42    and 
+                  var43.all   = C43    and 
+                  var44.all   = C44    and 
+                  var45.all   = C45    and 
+                  var46.all   = C46    and 
+                  var47.all   = C47    and 
+                  var48.all   = C48    and 
+                  var49.all   = C49    and 
+                  var50.all   = C50    and 
+                  var51.all   = C51    and 
+                  var52.all   = C52    and 
+                  var53.all   = C53    and 
+--      var54.all   = C54    and 
+--      var54a.all   = C54a    and 
+--      var55.all   = C55    and 
+                  var56.all   = C56    and 
+                  var57.all   = C57    and 
+                  var58.all   = C58    and 
+                  var59.all   = C59    and 
+                  var60.all   = C60    and 
+                  var61.all   = C61    and 
+                  var62.all   = C62    and 
+                  var63.all   = C63    and 
+                  var64.all   = C64    and 
+                  var65.all   = C65    and 
+                  var66.all   = C66    and 
+                  var67.all   = C67    and 
+                  var68.all   = C68    and 
+                  var69.all   = C69    and 
+                  var70.all   = C70    and 
+                  var71.all   = C71    and 
+                  var72.all   = C72    and 
+                  var73.all   = C73    and 
+                  var74.all   = C74    and 
+                  var75.all   = C75    and 
+                  var76.all   = C76    ) 
+      report "***PASSED TEST: c06s03b00x00p06n01i00988" 
+      severity NOTE;
+    assert (   var1.all   = C1    and 
+               var2.all   = C2    and 
+               var3.all   = C3    and 
+               var4.all   = C4    and 
+               var5.all   = C5    and 
+               var6.all   = C6    and 
+               var7.all   = C7    and 
+               var8.all   = C8    and 
+               var9.all   = C9    and 
+               var10.all   = C10    and 
+               var11.all   = C11    and 
+               var12.all   = C12    and 
+               var13.all   = C13    and 
+               var14.all   = C14    and 
+               var15.all   = C15    and 
+               var16.all   = C16    and 
+               var17.all   = C17    and 
+               var18.all   = C18    and 
+               var19.all   = C19    and 
+               var20.all   = C20    and 
+               var21.all   = C21    and 
+               var22.all   = C22    and 
+               var23.all   = C23    and 
+               var24.all   = C24    and 
+               var25.all   = C25    and 
+               var26.all   = C26    and 
+               var27.all   = C27    and 
+               var28.all   = C28    and 
+               var29.all   = C29    and 
+               var30.all   = C30    and 
+               var31.all   = C31    and 
+               var32.all   = C32    and 
+--      var33.all   = C33    and 
+--      var34.all   = C34    and 
+--      var35.all   = C35    and 
+--      var36.all   = C36    and 
+--      var37.all   = C37    and 
+--      var38.all   = C38    and 
+--      var39.all   = C39    and 
+--      var40.all   = C40    and 
+               var41.all   = C41    and 
+               var42.all   = C42    and 
+               var43.all   = C43    and 
+               var44.all   = C44    and 
+               var45.all   = C45    and 
+               var46.all   = C46    and 
+               var47.all   = C47    and 
+               var48.all   = C48    and 
+               var49.all   = C49    and 
+               var50.all   = C50    and 
+               var51.all   = C51    and 
+               var52.all   = C52    and 
+               var53.all   = C53    and 
+--      var54.all   = C54    and 
+--      var54a.all   = C54a    and 
+--      var55.all   = C55    and 
+               var56.all   = C56    and 
+               var57.all   = C57    and 
+               var58.all   = C58    and 
+               var59.all   = C59    and 
+               var60.all   = C60    and 
+               var61.all   = C61    and 
+               var62.all   = C62    and 
+               var63.all   = C63    and 
+               var64.all   = C64    and 
+               var65.all   = C65    and 
+               var66.all   = C66    and 
+               var67.all   = C67    and 
+               var68.all   = C68    and 
+               var69.all   = C69    and 
+               var70.all   = C70    and 
+               var71.all   = C71    and 
+               var72.all   = C72    and 
+               var73.all   = C73    and 
+               var74.all   = C74    and 
+               var75.all   = C75    and 
+               var76.all   = C76    ) 
+      report "***FAILED TEST: c06s03b00x00p06n01i00988 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p06n01i00988arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc99.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc99.vhd
new file mode 100644
index 0000000..6a13aa5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc99.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc99.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n02i00099ent_a IS
+END c04s03b02x00p29n02i00099ent_a;
+
+ARCHITECTURE c04s03b02x00p29n02i00099arch_a OF c04s03b02x00p29n02i00099ent_a IS
+  
+  PROCEDURE p1 ( prm_in : IN INTEGER ) IS
+    ATTRIBUTE attr1 : INTEGER;
+    ATTRIBUTE attr1 OF prm_in : constant IS 300;
+  BEGIN
+    ASSERT prm_in'attr1 = 300 REPORT "ERROR: Bad value for prm_in'attr1" SEVERITY FAILURE;
+    assert NOT(prm_in'attr1 = 300)
+      report "***PASSED TEST: c04s03b02x00p29n02i00099"
+      severity NOTE;
+    assert (prm_in'attr1 = 300)
+      report "***FAILED TEST: c04s03b02x00p29n02i00099 - Attribute reading in subprogram fail."
+      severity ERROR;
+  END;
+  
+BEGIN
+  PROCESS
+  BEGIN
+--
+    p1 ( 0 );
+--
+    wait;
+  END PROCESS;
+END c04s03b02x00p29n02i00099arch_a;
+
+
+
+ENTITY c04s03b02x00p29n02i00099ent IS
+END c04s03b02x00p29n02i00099ent;
+
+ARCHITECTURE c04s03b02x00p29n02i00099arch OF c04s03b02x00p29n02i00099ent IS
+  COMPONENT c04s03b02x00p29n02i00099ent_a
+  END COMPONENT;
+  FOR cmp1 : c04s03b02x00p29n02i00099ent_a USE ENTITY work.c04s03b02x00p29n02i00099ent_a(c04s03b02x00p29n02i00099arch_a); 
+  
+  SIGNAL s : INTEGER;
+BEGIN
+
+  cmp1 : c04s03b02x00p29n02i00099ent_a;
+
+END c04s03b02x00p29n02i00099arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc992.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc992.vhd
new file mode 100644
index 0000000..6c0fa5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc992.vhd
@@ -0,0 +1,223 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc992.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c06s03b00x00p08n01i00992pkg IS
+--
+--  This packages contains declarations of User attributes
+--
+-- ----------------------------------------------------------------------
+--
+  TYPE RESISTANCE IS RANGE 0 TO 1E9
+    UNITS
+      pf;
+      nf = 1000 pf;
+      mf = 1000 nf;
+    END UNITS;
+  
+  TYPE t_logic IS (
+    U,  D,
+    Z0, Z1, ZDX, DZX, ZX,
+    W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
+    R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
+    F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
+    );
+--
+--          Scalar types Declarations
+--
+  SUBTYPE st_scl1 IS BOOLEAN;
+  SUBTYPE st_scl2 IS BIT;
+  SUBTYPE st_scl3 IS CHARACTER;
+  SUBTYPE st_scl4 IS INTEGER;
+  SUBTYPE st_scl5 IS REAL;
+  SUBTYPE st_scl6 IS TIME;
+  SUBTYPE st_scl7 IS RESISTANCE;
+  SUBTYPE st_scl8 IS t_logic;
+--
+--          character string types
+--
+  SUBTYPE st_str1 IS STRING;
+  SUBTYPE st_str2 IS STRING (1 TO 4);
+--
+--          Scalar types with a range constraint
+--
+  SUBTYPE cst_scl1 IS BOOLEAN    RANGE  TRUE   TO      TRUE;
+  SUBTYPE cst_scl2 IS BIT        RANGE   '0'   TO       '0';
+  SUBTYPE cst_scl3 IS CHARACTER  RANGE   'a'   TO       'z';
+  SUBTYPE cst_scl4 IS INTEGER    RANGE    10 DOWNTO       0;
+  SUBTYPE cst_scl5 IS REAL       RANGE   0.0   TO      10.0;
+  SUBTYPE cst_scl6 IS TIME       RANGE  0 fs   TO     10 ns;
+  SUBTYPE cst_scl7 IS RESISTANCE RANGE  0 pf   TO  10000 pf;
+  SUBTYPE cst_scl8 IS t_logic    RANGE    F0   TO        FX;
+  
+-- -----------------------------------------------------------------------------------------
+--      Attribute Declarations
+-- -----------------------------------------------------------------------------------------
+--
+  ATTRIBUTE atr_scl1 : st_scl1;
+  ATTRIBUTE atr_scl2 : st_scl2;
+  ATTRIBUTE atr_scl3 : st_scl3;
+  ATTRIBUTE atr_scl4 : st_scl4;
+  ATTRIBUTE atr_scl5 : st_scl5;
+  ATTRIBUTE atr_scl6 : st_scl6;
+  ATTRIBUTE atr_scl7 : st_scl7;
+  ATTRIBUTE atr_scl8 : st_scl8;
+  
+  ATTRIBUTE atr_str1 : st_str1;
+  ATTRIBUTE atr_str2 : st_str2;
+  
+  ATTRIBUTE cat_scl1 : cst_scl1;
+  ATTRIBUTE cat_scl2 : cst_scl2;
+  ATTRIBUTE cat_scl3 : cst_scl3;
+  ATTRIBUTE cat_scl4 : cst_scl4;
+  ATTRIBUTE cat_scl5 : cst_scl5;
+  ATTRIBUTE cat_scl6 : cst_scl6;
+  ATTRIBUTE cat_scl7 : cst_scl7;
+  ATTRIBUTE cat_scl8 : cst_scl8;
+-- =========================================================================================
+--
+--          Apply attributes to the package
+--
+  ATTRIBUTE atr_scl1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS      TRUE;
+  ATTRIBUTE atr_scl2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS       '0';
+  ATTRIBUTE atr_scl3 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS       'z';
+  ATTRIBUTE atr_scl4 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS         0;
+  ATTRIBUTE atr_scl5 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS      10.0;
+  ATTRIBUTE atr_scl6 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS     10 ns;
+  ATTRIBUTE atr_scl7 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS  10000 pf;
+  ATTRIBUTE atr_scl8 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS        FX;
+  
+  ATTRIBUTE atr_str1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS  "packit";
+  ATTRIBUTE atr_str2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS    "pack";
+  
+  ATTRIBUTE cat_scl1 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS      TRUE;
+  ATTRIBUTE cat_scl2 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS       '0';
+  ATTRIBUTE cat_scl3 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS       'z';
+  ATTRIBUTE cat_scl4 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS         0;
+  ATTRIBUTE cat_scl5 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS      10.0;
+  ATTRIBUTE cat_scl6 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS     10 ns;
+  ATTRIBUTE cat_scl7 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS  10000 pf;
+  ATTRIBUTE cat_scl8 OF c06s03b00x00p08n01i00992pkg: PACKAGE IS        FX;
+--
+END;
+
+
+use work.all;
+use c06s03b00x00p08n01i00992pkg.all;
+ENTITY c06s03b00x00p08n01i00992ent IS
+END c06s03b00x00p08n01i00992ent;
+
+ARCHITECTURE c06s03b00x00p08n01i00992arch OF c06s03b00x00p08n01i00992ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl1 =      TRUE 
+      REPORT "ERROR: Wrong value for 'atr_scl1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl2 =       '0' 
+      REPORT "ERROR: Wrong value for 'atr_scl2" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl3 =       'z' 
+      REPORT "ERROR: Wrong value for 'atr_scl3" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl4 =         0 
+      REPORT "ERROR: Wrong value for 'atr_scl4" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl5 =      10.0 
+      REPORT "ERROR: Wrong value for 'atr_scl5" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl6 =     10 ns 
+      REPORT "ERROR: Wrong value for 'atr_scl6" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl7 =  10000 pf 
+      REPORT "ERROR: Wrong value for 'atr_scl7" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_scl8 =        FX 
+      REPORT "ERROR: Wrong value for 'atr_scl8" SEVERITY FAILURE;
+    
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_str1 =  "packit" 
+      REPORT "ERROR: Wrong value for 'atr_str1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'atr_str2 =    "pack" 
+      REPORT "ERROR: Wrong value for 'atr_str2" SEVERITY FAILURE;
+    
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl1 =      TRUE 
+      REPORT "ERROR: Wrong value for 'cat_scl1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl2 =       '0' 
+      REPORT "ERROR: Wrong value for 'cat_scl2" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl3 =       'z' 
+      REPORT "ERROR: Wrong value for 'cat_scl3" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl4 =         0 
+      REPORT "ERROR: Wrong value for 'cat_scl4" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl5 =      10.0 
+      REPORT "ERROR: Wrong value for 'cat_scl5" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl6 =     10 ns 
+      REPORT "ERROR: Wrong value for 'cat_scl6" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl7 =  10000 pf 
+      REPORT "ERROR: Wrong value for 'cat_scl7" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00992pkg'cat_scl8 =        FX 
+      REPORT "ERROR: Wrong value for 'cat_scl8" SEVERITY FAILURE;
+
+    assert NOT( c06s03b00x00p08n01i00992pkg'atr_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00992pkg'atr_scl2 =       '0' 
+                and c06s03b00x00p08n01i00992pkg'atr_scl3 =       'z' 
+                and c06s03b00x00p08n01i00992pkg'atr_scl4 =         0 
+                and c06s03b00x00p08n01i00992pkg'atr_scl5 =      10.0 
+                and c06s03b00x00p08n01i00992pkg'atr_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00992pkg'atr_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00992pkg'atr_scl8 =        FX 
+                and c06s03b00x00p08n01i00992pkg'atr_str1 =  "packit" 
+                and c06s03b00x00p08n01i00992pkg'atr_str2 =    "pack" 
+                and c06s03b00x00p08n01i00992pkg'cat_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00992pkg'cat_scl2 =       '0' 
+                and c06s03b00x00p08n01i00992pkg'cat_scl3 =       'z' 
+                and c06s03b00x00p08n01i00992pkg'cat_scl4 =         0 
+                and c06s03b00x00p08n01i00992pkg'cat_scl5 =      10.0 
+                and c06s03b00x00p08n01i00992pkg'cat_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00992pkg'cat_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00992pkg'cat_scl8 =        FX) 
+      report "***PASSED TEST: c06s03b00x00p08n01i00992"
+      severity NOTE;
+    assert (    c06s03b00x00p08n01i00992pkg'atr_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00992pkg'atr_scl2 =       '0' 
+                and c06s03b00x00p08n01i00992pkg'atr_scl3 =       'z' 
+                and c06s03b00x00p08n01i00992pkg'atr_scl4 =         0 
+                and c06s03b00x00p08n01i00992pkg'atr_scl5 =      10.0 
+                and c06s03b00x00p08n01i00992pkg'atr_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00992pkg'atr_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00992pkg'atr_scl8 =        FX 
+                and c06s03b00x00p08n01i00992pkg'atr_str1 =  "packit" 
+                and c06s03b00x00p08n01i00992pkg'atr_str2 =    "pack" 
+                and c06s03b00x00p08n01i00992pkg'cat_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00992pkg'cat_scl2 =       '0' 
+                and c06s03b00x00p08n01i00992pkg'cat_scl3 =       'z' 
+                and c06s03b00x00p08n01i00992pkg'cat_scl4 =         0 
+                and c06s03b00x00p08n01i00992pkg'cat_scl5 =      10.0 
+                and c06s03b00x00p08n01i00992pkg'cat_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00992pkg'cat_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00992pkg'cat_scl8 =        FX) 
+      report "***FAILED TEST: c06s03b00x00p08n01i00992 - Expanded name denotes a primary unit contained in design library test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p08n01i00992arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc993.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc993.vhd
new file mode 100644
index 0000000..dac15e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc993.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc993.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p08n02i00993pkg is
+  type T1 is record
+               S1 : Bit ;
+               S2 : Integer;
+             end record;
+  type T2 is record
+               S11 : BIT ;
+               S12 : T1 ;
+             end record;
+end c06s03b00x00p08n02i00993pkg;
+
+use work.c06s03b00x00p08n02i00993pkg.all;
+ENTITY c06s03b00x00p08n02i00993ent IS
+END c06s03b00x00p08n02i00993ent;
+
+ARCHITECTURE c06s03b00x00p08n02i00993arch OF c06s03b00x00p08n02i00993ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T2 ;
+  BEGIN
+    V1.S12.S2 := 10 ;  -- No_Failure_here
+    wait for 10 ns;
+    assert NOT(V1.S12.S2 = 10)
+      report "***PASSED TEST: c06s03b00x00p08n02i00993"
+      severity NOTE;
+    assert (V1.S12.S2 = 10)
+      report "***FAILED TEST: c06s03b00x00p08n02i00993 - The expanded name denotes all primary units contained in a library if the prefix denotes the library and the suffix is the reserved word all."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p08n02i00993arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/compliant/tc995.vhd b/testsuite/vests/vhdl-93/billowitch/compliant/tc995.vhd
new file mode 100644
index 0000000..33cf42a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/compliant/tc995.vhd
@@ -0,0 +1,216 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc995.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE c06s03b00x00p08n01i00995pkg IS
+--
+--  This packages contains declarations of User attributes
+--
+-- ----------------------------------------------------------------------------------
+--
+  TYPE RESISTANCE IS RANGE 0 TO 1E9
+    UNITS
+      pf;
+      nf = 1000 pf;
+      mf = 1000 nf;
+    END UNITS;
+
+  TYPE t_logic IS (
+    U,  D,
+    Z0, Z1, ZDX, DZX, ZX,
+    W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
+    R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
+    F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
+    );
+--
+--          Scalar types Declarations
+--
+  SUBTYPE st_scl1 IS BOOLEAN;
+  SUBTYPE st_scl2 IS BIT;
+  SUBTYPE st_scl3 IS CHARACTER;
+  SUBTYPE st_scl4 IS INTEGER;
+  SUBTYPE st_scl5 IS REAL;
+  SUBTYPE st_scl6 IS TIME;
+  SUBTYPE st_scl7 IS RESISTANCE;
+  SUBTYPE st_scl8 IS t_logic;
+--
+--          character string types
+--
+  SUBTYPE st_str1 IS STRING;
+  SUBTYPE st_str2 IS STRING (1 TO 4);
+--
+--          Scalar types with a range constraint
+--
+  SUBTYPE cst_scl1 IS BOOLEAN    RANGE  TRUE   TO      TRUE;
+  SUBTYPE cst_scl2 IS BIT        RANGE   '0'   TO       '0';
+  SUBTYPE cst_scl3 IS CHARACTER  RANGE   'a'   TO       'z';
+  SUBTYPE cst_scl4 IS INTEGER    RANGE    10 DOWNTO       0;
+  SUBTYPE cst_scl5 IS REAL       RANGE   0.0   TO      10.0;
+  SUBTYPE cst_scl6 IS TIME       RANGE  0 fs   TO     10 ns;
+  SUBTYPE cst_scl7 IS RESISTANCE RANGE  0 pf   TO  10000 pf;
+  SUBTYPE cst_scl8 IS t_logic    RANGE    F0   TO        FX;
+  
+-- ------------------------------------------------------------------------------------
+--      Attribute Declarations
+-- ------------------------------------------------------------------------------------
+--
+  ATTRIBUTE atr_scl1 : st_scl1;
+  ATTRIBUTE atr_scl2 : st_scl2;
+  ATTRIBUTE atr_scl3 : st_scl3;
+  ATTRIBUTE atr_scl4 : st_scl4;
+  ATTRIBUTE atr_scl5 : st_scl5;
+  ATTRIBUTE atr_scl6 : st_scl6;
+  ATTRIBUTE atr_scl7 : st_scl7;
+  ATTRIBUTE atr_scl8 : st_scl8;
+  
+  ATTRIBUTE atr_str1 : st_str1;
+  ATTRIBUTE atr_str2 : st_str2;
+  
+  ATTRIBUTE cat_scl1 : cst_scl1;
+  ATTRIBUTE cat_scl2 : cst_scl2;
+  ATTRIBUTE cat_scl3 : cst_scl3;
+  ATTRIBUTE cat_scl4 : cst_scl4;
+  ATTRIBUTE cat_scl5 : cst_scl5;
+  ATTRIBUTE cat_scl6 : cst_scl6;
+  ATTRIBUTE cat_scl7 : cst_scl7;
+  ATTRIBUTE cat_scl8 : cst_scl8;
+  
+END;
+
+USE WORK.c06s03b00x00p08n01i00995pkg.all;
+ENTITY c06s03b00x00p08n01i00995ent IS
+  ATTRIBUTE atr_scl1 OF c06s03b00x00p08n01i00995ent: ENTITY IS      TRUE;
+  ATTRIBUTE atr_scl2 OF c06s03b00x00p08n01i00995ent: ENTITY IS       '0';
+  ATTRIBUTE atr_scl3 OF c06s03b00x00p08n01i00995ent: ENTITY IS       'z';
+  ATTRIBUTE atr_scl4 OF c06s03b00x00p08n01i00995ent: ENTITY IS         0;
+  ATTRIBUTE atr_scl5 OF c06s03b00x00p08n01i00995ent: ENTITY IS      10.0;
+  ATTRIBUTE atr_scl6 OF c06s03b00x00p08n01i00995ent: ENTITY IS     10 ns;
+  ATTRIBUTE atr_scl7 OF c06s03b00x00p08n01i00995ent: ENTITY IS  10000 pf;
+  ATTRIBUTE atr_scl8 OF c06s03b00x00p08n01i00995ent: ENTITY IS        FX;
+  
+  ATTRIBUTE atr_str1 OF c06s03b00x00p08n01i00995ent: ENTITY IS  "entity";
+  ATTRIBUTE atr_str2 OF c06s03b00x00p08n01i00995ent: ENTITY IS    "enty";
+  
+  ATTRIBUTE cat_scl1 OF c06s03b00x00p08n01i00995ent: ENTITY IS      TRUE;
+  ATTRIBUTE cat_scl2 OF c06s03b00x00p08n01i00995ent: ENTITY IS       '0';
+  ATTRIBUTE cat_scl3 OF c06s03b00x00p08n01i00995ent: ENTITY IS       'z';
+  ATTRIBUTE cat_scl4 OF c06s03b00x00p08n01i00995ent: ENTITY IS         0;
+  ATTRIBUTE cat_scl5 OF c06s03b00x00p08n01i00995ent: ENTITY IS      10.0;
+  ATTRIBUTE cat_scl6 OF c06s03b00x00p08n01i00995ent: ENTITY IS     10 ns;
+  ATTRIBUTE cat_scl7 OF c06s03b00x00p08n01i00995ent: ENTITY IS  10000 pf;
+  ATTRIBUTE cat_scl8 OF c06s03b00x00p08n01i00995ent: ENTITY IS        FX;
+END c06s03b00x00p08n01i00995ent;
+
+ARCHITECTURE c06s03b00x00p08n01i00995arch OF c06s03b00x00p08n01i00995ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl1 =      TRUE 
+      REPORT "ERROR: Wrong value for 'atr_scl1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl2 =       '0' 
+      REPORT "ERROR: Wrong value for 'atr_scl2" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl3 =       'z' 
+      REPORT "ERROR: Wrong value for 'atr_scl3" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl4 =         0 
+      REPORT "ERROR: Wrong value for 'atr_scl4" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl5 =      10.0 
+      REPORT "ERROR: Wrong value for 'atr_scl5" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl6 =     10 ns 
+      REPORT "ERROR: Wrong value for 'atr_scl6" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl7 =  10000 pf 
+      REPORT "ERROR: Wrong value for 'atr_scl7" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_scl8 =        FX 
+      REPORT "ERROR: Wrong value for 'atr_scl8" SEVERITY FAILURE;
+    
+    ASSERT c06s03b00x00p08n01i00995ent'atr_str1 =  "entity" 
+      REPORT "ERROR: Wrong value for 'atr_str1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'atr_str2 =    "enty" 
+      REPORT "ERROR: Wrong value for 'atr_str2" SEVERITY FAILURE;
+    
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl1 =      TRUE 
+      REPORT "ERROR: Wrong value for 'cat_scl1" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl2 =       '0' 
+      REPORT "ERROR: Wrong value for 'cat_scl2" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl3 =       'z' 
+      REPORT "ERROR: Wrong value for 'cat_scl3" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl4 =         0 
+      REPORT "ERROR: Wrong value for 'cat_scl4" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl5 =      10.0 
+      REPORT "ERROR: Wrong value for 'cat_scl5" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl6 =     10 ns 
+      REPORT "ERROR: Wrong value for 'cat_scl6" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl7 =  10000 pf 
+      REPORT "ERROR: Wrong value for 'cat_scl7" SEVERITY FAILURE;
+    ASSERT c06s03b00x00p08n01i00995ent'cat_scl8 =        FX 
+      REPORT "ERROR: Wrong value for 'cat_scl8" SEVERITY FAILURE;
+
+    assert NOT( c06s03b00x00p08n01i00995ent'atr_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00995ent'atr_scl2 =       '0' 
+                and c06s03b00x00p08n01i00995ent'atr_scl3 =       'z' 
+                and c06s03b00x00p08n01i00995ent'atr_scl4 =         0 
+                and c06s03b00x00p08n01i00995ent'atr_scl5 =      10.0 
+                and c06s03b00x00p08n01i00995ent'atr_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00995ent'atr_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00995ent'atr_scl8 =        FX 
+                and c06s03b00x00p08n01i00995ent'atr_str1 =  "entity" 
+                and c06s03b00x00p08n01i00995ent'atr_str2 =    "enty" 
+                and c06s03b00x00p08n01i00995ent'cat_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00995ent'cat_scl2 =       '0' 
+                and c06s03b00x00p08n01i00995ent'cat_scl3 =       'z' 
+                and c06s03b00x00p08n01i00995ent'cat_scl4 =         0 
+                and c06s03b00x00p08n01i00995ent'cat_scl5 =      10.0 
+                and c06s03b00x00p08n01i00995ent'cat_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00995ent'cat_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00995ent'cat_scl8 =        FX   ) 
+      report "***PASSED TEST: c06s03b00x00p08n01i00995"
+      severity NOTE;
+    assert (    c06s03b00x00p08n01i00995ent'atr_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00995ent'atr_scl2 =       '0' 
+                and c06s03b00x00p08n01i00995ent'atr_scl3 =       'z' 
+                and c06s03b00x00p08n01i00995ent'atr_scl4 =         0 
+                and c06s03b00x00p08n01i00995ent'atr_scl5 =      10.0 
+                and c06s03b00x00p08n01i00995ent'atr_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00995ent'atr_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00995ent'atr_scl8 =        FX 
+                and c06s03b00x00p08n01i00995ent'atr_str1 =  "entity" 
+                and c06s03b00x00p08n01i00995ent'atr_str2 =    "enty" 
+                and c06s03b00x00p08n01i00995ent'cat_scl1 =      TRUE 
+                and c06s03b00x00p08n01i00995ent'cat_scl2 =       '0' 
+                and c06s03b00x00p08n01i00995ent'cat_scl3 =       'z' 
+                and c06s03b00x00p08n01i00995ent'cat_scl4 =         0 
+                and c06s03b00x00p08n01i00995ent'cat_scl5 =      10.0 
+                and c06s03b00x00p08n01i00995ent'cat_scl6 =     10 ns 
+                and c06s03b00x00p08n01i00995ent'cat_scl7 =  10000 pf 
+                and c06s03b00x00p08n01i00995ent'cat_scl8 =        FX   ) 
+      report "***FAILED TEST: c06s03b00x00p08n01i00995 - Expanded name denotes a primary unit contained in design library test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p08n01i00995arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/README b/testsuite/vests/vhdl-93/billowitch/disputed/README
new file mode 100644
index 0000000..52e423b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/README
@@ -0,0 +1,61 @@
+############################################################################
+################  Error cases in Billowitch ################################
+############################################################################
+
+[1]tc1158.vhd : synopsys treats differently the BASE attribute
+[2]tc2284.vhd : synopsys problem with multiplication and division of physical
+	        types and real and integer
+[3]tc2568.vhd : synopsys problem with universal real types, addition and
+	        equality
+[4]tc814.vhd  : wrong test case, should be PASSED TEST and not FAILED TEST
+[5]tc1120.vhd : type of the constrained range of the unconstrained array is
+	        not given
+[6]tc1148.vhd : type mismatch error
+[7]tc1150.vhd : same as above.
+[8]tc1779.vhd : Guess it is a typo, defining a architecture of an entity
+	        which is defined later.
+[9]tc232.vhdl : synopsys reports the following error : "Numeric type
+                definition range must be locally static". 
+[10]tc233.vhd  : same as above
+[11]tc237.vhd  : same as above
+[12]tc238.vhd  : same as above
+[13]tc3090.vhd : Synopsys reports that the attribute specification is wrong.
+	         Name must denote entity of specified class in this
+	         declarative region.
+[14]tc3124.vhd : Synopsys reports "component local ----- must be
+	         associated as an actual with at least one entity formal".
+[15]tc3129.vhd : ,,
+[16]tc3130.vhd : ,,
+[17]tc3131.vhd : ,,
+[18]tc3132.vhd : ,,
+[19]tc3133.vhd : ,,
+[20]tc3134.vhd : ,,
+[21]tc3135.vhd : ,,
+[22]tc3136.vhd : ,,
+[23]tc851.vhd  : Synopsys reports the following error :
+	         for G(three downto zero )
+		       ^
+	         Slice discrete range direction is opposite that to prefix.
+[24]tc865.vhd  : ,,
+[25]tc882.vhd  : word work missing in the entity used in the configuration
+	         declaration 
+[27]tc996.vhd  : non-existing architecture name
+[28]tc1021.vhd : has two blocks. when simulating in SYnopsys, it goes on
+	         for ever. There is no termination condition.
+[29]tc1737.vhd : works correctly in synopsys. But runs forever.
+[30]tc1738.vhd : ,,
+[31]tc3065.vhd : ,,
+[32]tc1675.vhd : synopsys hangs, but gives the "passed test" message
+[33]tc1740.vhd : synopsys hangs, but gives the "passed test" message
+[34]tc1749.vhd : ,,
+[35]tc3018.vhd : correct, but can't be simulated because, it is just a package
+[36]tc737.vhd  : Top level entity has a generic (GC3) with no default value.
+[37]tc758.vhd  : Synopsys gives this error message:Top level entity has a port
+   	         (VGEN18) which is either unconstrained/is of mode IN and has
+                 no default value.
+[38]tc816.vhd  : Synopsys does not give "PASSED TEST", but if the order of
+	         architecture is changed, then it is works.
+[39]tc833.vhd  : does not print "FAILED TEST" or "PASSED TEST",because there is
+   	         only "FAILED TEST" in the file and that too is commented
+                 out. Dont know why !! .
+
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1021.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1021.vhd
new file mode 100644
index 0000000..07aa847
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1021.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1021.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01021ent IS
+END c06s03b00x00p10n01i01021ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01021arch OF c06s03b00x00p10n01i01021ent IS
+BEGIN
+  B1:Block
+    signal s1 : BIT;
+  begin
+    TESTING: PROCESS
+    BEGIN
+      wait for 1 ns;
+    END PROCESS TESTING;
+
+    B2:Block
+      signal s2 : BIT;
+    begin
+      TEST : PROCESS
+      BEGIN
+        s2 <= B1.s1;
+        wait for 2 ns;
+        assert NOT(s2='0')
+          report "***PASSED TEST: c06s03b00x00p10n01i01021" 
+          severity NOTE;
+        assert (s2='0')
+          report "***FAILED TEST: c06s03b00x00p10n01i01021 - Entity declaration does not occur in construct specifed by the prefix." 
+          severity ERROR;
+      END PROCESS TEST;
+    end block B2;
+  end block B1;
+
+END c06s03b00x00p10n01i01021arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1120.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1120.vhd
new file mode 100644
index 0000000..cfe0f35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1120.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1120.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01120ent IS
+  type idx   is range 1 to 10;
+  type aray1 is array (idx) of bit;
+  type aray2 is array (idx range <>) of aray1;
+END c06s05b00x00p03n01i01120ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01120arch OF c06s05b00x00p03n01i01120ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable v1, v2 : aray1;
+    variable v3     : aray2(1 to 2);
+    variable v4     : aray2(1 to 3);
+  BEGIN
+    --
+    -- Try slices consisting of slice names
+    --
+    v1 := "1111111111";
+    v1 := v3(1)(idx);           -- slice is a whole array
+    assert v2 = v1
+      report "Slice of a slice name as a value failed."
+      severity note ;
+    
+    v1 := "1111111111";
+    v4(2)(idx) := v1;           -- slice is a whole array
+    assert v4(2) = v1
+      report "Slice of a slice name as a target failed."
+      severity note ;
+    
+    v2(1) := v3(1)(1 to 1)(1 to 1)(1);       -- a one element slice
+    assert v3(1)(1) = v2(1)
+      report "One element slice of a slice name as a value failed."    
+      severity note ;
+    
+    v3(1)(1 to 1)(1 to 1)(1) := v1(1);       -- a one element slice
+    assert v3(1)(1) = v1(1)
+      report "One element slice of a slice name as a target failed." 
+      severity note ;
+
+    assert NOT(   v1       = "1111111111"   and
+                  v4(2)       = "1111111111"   and
+                  v2(1)      = '0'      and
+                  v3(1)(1)   = '1') 
+      report "***PASSED TEST: c06s05b00x00p03n01i01120" 
+      severity NOTE;
+    assert (   v1       = "1111111111"   and
+               v4(2)       = "1111111111"   and
+               v2(1)      = '0'      and
+               v3(1)(1)   = '1') 
+      report "***FAILED TEST: c06s05b00x00p03n01i01120 - The prefix of a slice may be a slice name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01120arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1148.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1148.vhd
new file mode 100644
index 0000000..3aa1d99
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1148.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1148.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p07n01i01148ent IS
+END c06s05b00x00p07n01i01148ent;
+
+ARCHITECTURE c06s05b00x00p07n01i01148arch OF c06s05b00x00p07n01i01148ent IS
+  type   A is array (10 downto 1) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable var : A := (66,66,others=>66);
+  BEGIN
+    wait for 5 ns;
+    assert NOT( var(1 downto 1) = 66 )
+      report "***PASSED TEST: c06s05b00x00p07n01i01148"
+      severity NOTE;
+    assert ( var(1 downto 1) = 66 )
+      report "***FAILED TEST: c06s05b00x00p07n01i01148 - A(N downto N) should be a slice that contains one element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p07n01i01148arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1150.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1150.vhd
new file mode 100644
index 0000000..4ccd13c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1150.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1150.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p07n01i01150ent IS
+END c06s05b00x00p07n01i01150ent;
+
+ARCHITECTURE c06s05b00x00p07n01i01150arch OF c06s05b00x00p07n01i01150ent IS
+  type   A is array (1 to 10) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable var : A := (6,6,others=>88);
+  BEGIN
+    wait for 5 ns;
+    assert NOT( var(1 to 1) = 6 )
+      report "***PASSED TEST: c06s05b00x00p07n01i01150"
+      severity NOTE;
+    assert ( var(1 to 1) = 6 )
+      report "***FAILED TEST: c06s05b00x00p07n01i01150 - A(N to N) should be a slice that contains one element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p07n01i01150arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1158.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1158.vhd
new file mode 100644
index 0000000..85702fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1158.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1158.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s06b00x00p02n01i01158pkg is
+  type    I1    is range 1 to 5;
+  subtype    I11    is I1 range 2 to 4;
+  type    A1    is array (I1 range 2 to 4) of BOOLEAN;
+end c06s06b00x00p02n01i01158pkg;
+
+use work.c06s06b00x00p02n01i01158pkg.all;
+ENTITY c06s06b00x00p02n01i01158ent IS
+  generic (V_all : A1 := (true,false,true));
+  port    (PT: BOOLEAN);
+END c06s06b00x00p02n01i01158ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01158arch OF c06s06b00x00p02n01i01158ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable  V      : boolean;
+    attribute AT1    : A1;
+    attribute AT1    of V : variable is V_all;
+    variable  k    : integer := 0;
+  BEGIN
+    if I11'BASE'Left = 1 then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c06s06b00x00p02n01i01158"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c06s06b00x00p02n01i01158 - The prefix of an attribute name may be a selected name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01158arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1675.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1675.vhd
new file mode 100644
index 0000000..e71aa98
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1675.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1675.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p06n01i01675ent IS
+END c09s01b00x00p06n01i01675ent;
+
+ARCHITECTURE c09s01b00x00p06n01i01675arch OF c09s01b00x00p06n01i01675ent IS
+  signal garde : boolean := true;
+BEGIN
+  lab: block ( garde )
+  begin
+    garde <= not GUARD after 20 ns;
+    assert ( GUARD = garde )
+      report "***FAILED TEST: c09s01b00x00p06n01i01675 - Implicit signal GUARD changed state and does not match explicit signal garde (FAIL)"
+      severity ERROR;
+  end block lab;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c09s01b00x00p06n01i01675 - This test needed manual check, no failure test assertion report"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p06n01i01675arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1737.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1737.vhd
new file mode 100644
index 0000000..90ec747
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1737.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1737.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s04b00x00p09n01i01737ent IS
+END c09s04b00x00p09n01i01737ent;
+
+ARCHITECTURE c09s04b00x00p09n01i01737arch OF c09s04b00x00p09n01i01737ent IS
+  signal   s1 : bit;
+  signal    s2 : bit;
+BEGIN
+
+  s1   <= not s1 after 70 ns;
+  s2   <= not s2 after 30 ns;
+
+  block_label1 : BLOCK (s1 = '1')
+  begin
+    assert (s2 = s2'last_value)
+      report "PASSED TEST"
+      severity NOTE;
+    TESTING: PROCESS(s2)
+    BEGIN
+      assert FALSE 
+        report "***PASSED TEST: c09s04b00x00p09n01i01737 - This test needs manual check, depend on the simulation time, the assertion 'PASSED TEST' should fire every time s2 is changed regardless of the value of the signal GUARD."
+        severity NOTE;
+    END PROCESS TESTING;
+  end block block_label1;
+
+END c09s04b00x00p09n01i01737arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1738.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1738.vhd
new file mode 100644
index 0000000..b9bcf2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1738.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1738.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s04b00x00p09n01i01738ent IS
+END c09s04b00x00p09n01i01738ent;
+
+ARCHITECTURE c09s04b00x00p09n01i01738arch OF c09s04b00x00p09n01i01738ent IS
+  signal   s1 : bit;
+BEGIN
+
+  s1   <= not s1 after 70 ns;
+
+  block_label1 : BLOCK (s1 = '1')
+  begin
+    assert not GUARD 
+      report "PASSED TEST"
+      severity NOTE;
+  end block block_label1;
+  
+  TESTING: PROCESS(s1)
+  BEGIN
+    if (now = 70 ns) then
+      assert FALSE 
+        report "***PASSED TEST: c09s04b00x00p09n01i01738 - This test needs manual check, 'PASSED TEST' assertion should fire at 70 ns, 210 ns, 350 ns ...( the cycle is 140 ns)."
+        severity NOTE;
+    end if;
+  END PROCESS TESTING;
+
+END c09s04b00x00p09n01i01738arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1740.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1740.vhd
new file mode 100644
index 0000000..fdf61a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1740.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1740.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p02n01i01740ent IS
+  port (clk : inout bit);
+END c09s05b00x00p02n01i01740ent;
+
+ARCHITECTURE c09s05b00x00p02n01i01740arch OF c09s05b00x00p02n01i01740ent IS
+  constant   period : Time := 50 ns;
+BEGIN
+  osc: clk <= not clk after period/2;    -- No_failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s05b00x00p02n01i01740"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b00x00p02n01i01740arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1749.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1749.vhd
new file mode 100644
index 0000000..43082e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1749.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1749.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p16n01i01749ent IS
+END c09s05b00x00p16n01i01749ent;
+
+ARCHITECTURE c09s05b00x00p16n01i01749arch OF c09s05b00x00p16n01i01749ent IS
+  signal a      : bit;
+  signal b      : bit;
+  signal grd    : boolean;
+BEGIN
+  grd   <=   not grd after 75 ns;
+
+  block_label : BLOCK (grd)
+  begin
+    b <= guarded '1' after 1 ns;
+  end block block_label;
+
+  BG: block (grd)
+  begin
+    TESTING: PROCESS
+    BEGIN
+      if GUARD then
+        a <= '1' after 1 ns;
+      end if;
+      wait on GUARD, a;
+    END PROCESS TESTING;
+  end block BG;
+
+  process(a,b)
+  begin
+    if (now > 1 ns) then
+      assert NOT( a=b )
+        report "***PASSED TEST: c09s05b00x00p16n01i01749"
+        severity NOTE;
+      assert ( a=b )
+        report "***FAILED TEST: c09s05b00x00p16n01i01749 - Concurrent signal assignment test failed."
+        severity ERROR;
+    end if;
+  end process;
+
+END c09s05b00x00p16n01i01749arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1779.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1779.vhd
new file mode 100644
index 0000000..7e93424
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1779.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1779.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s06b00x00p02n01i01779ent_a IS
+  port (signal input_1 : in  bit;
+        signal input_2 : in  bit;
+        signal output  : out bit);
+END c09s06b00x00p02n01i01779ent_a;
+
+ARCHITECTURE c09s06b00x00p02n01i01779arch_a OF c09s06b00x00p02n01i01779ent IS
+
+BEGIN
+
+END c09s06b00x00p02n01i01779arch_a;
+
+ENTITY c09s06b00x00p02n01i01779ent IS
+END c09s06b00x00p02n01i01779ent;
+
+ARCHITECTURE c09s06b00x00p02n01i01779arch OF c09s06b00x00p02n01i01779ent IS
+
+  component input2
+    port (signal input_1 : in  bit;
+          signal input_2 : in  bit;
+          signal output  : out bit);
+  end component;
+  for C : input2 use entity work.c09s06b00x00p02n01i01779ent_a(c09s06b00x00p02n01i01779arch_a);
+
+  signal A1, A2, A3 : bit;
+
+BEGIN
+
+  C : input2 port map (A1,A2,A3);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c09s06b00x00p02n01i01779" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s06b00x00p02n01i01779arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc2284.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc2284.vhd
new file mode 100644
index 0000000..fd38584
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc2284.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2284.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02284ent IS
+END c07s02b06x00p14n01i02284ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02284arch OF c07s02b06x00p14n01i02284ent IS
+  signal   SS : TIME;
+BEGIN
+  TESTING: PROCESS
+    variable A : TIME := 199 ns;
+    variable R : REAL := 7.9999;
+    variable S : INTEGER := 199;
+  BEGIN
+    SS <= A * R / S;                
+    wait for 10 ns;
+    assert NOT(SS = 7.9999 ns)
+      report "***PASSED TEST: c07s02b06x00p14n01i02284" 
+      severity NOTE;
+    assert (SS = 7.9999 ns)
+      report "***FAILED TEST: c07s02b06x00p14n01i02284 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02284arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc232.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc232.vhd
new file mode 100644
index 0000000..5ff3046
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc232.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc232.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p02n01i00232ent IS
+END c03s01b02x00p02n01i00232ent;
+
+ARCHITECTURE c03s01b02x00p02n01i00232arch OF c03s01b02x00p02n01i00232ent IS
+  type a is range (1+1) to (1 ms/1 ns);
+BEGIN
+  TESTING: PROCESS
+    variable k : a := 3;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p02n01i00232" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p02n01i00232 - The right bound in the range constraint is not a locally static expression of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p02n01i00232arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc233.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc233.vhd
new file mode 100644
index 0000000..fc31709
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc233.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc233.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p02n01i00233ent IS
+END c03s01b02x00p02n01i00233ent;
+
+ARCHITECTURE c03s01b02x00p02n01i00233arch OF c03s01b02x00p02n01i00233ent IS
+  type a is range (1 ns/1 fs) downto (1 fs/1 fs);
+BEGIN
+  TESTING: PROCESS
+    variable k : a := 3;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p02n01i00233"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p02n01i00233 - The right bound in the range constraint is not a locally static expression of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p02n01i00233arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc237.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc237.vhd
new file mode 100644
index 0000000..4dd5f67
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc237.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc237.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00237ent IS
+END c03s01b02x00p04n01i00237ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00237arch OF c03s01b02x00p04n01i00237ent IS
+  type t3 is range (1+1) to (ms/ns);
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 6;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p04n01i00237" 
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p04n01i00237 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00237arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc238.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc238.vhd
new file mode 100644
index 0000000..0c05ff7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc238.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc238.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00238ent IS
+END c03s01b02x00p04n01i00238ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00238arch OF c03s01b02x00p04n01i00238ent IS
+  type t3 is range (ns/fs) downto (fs/fs);  
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 6;
+  BEGIN
+    k := 5;
+    assert NOT(k=5) 
+      report "***PASSED TEST: c03s01b02x00p04n01i00238"
+      severity NOTE;
+    assert (k=5) 
+      report "***FAILED TEST: c03s01b02x00p04n01i00238 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00238arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc2568.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc2568.vhd
new file mode 100644
index 0000000..567544a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc2568.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2568.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s05b00x00p02n01i02568ent IS
+END c07s05b00x00p02n01i02568ent;
+
+ARCHITECTURE c07s05b00x00p02n01i02568arch OF c07s05b00x00p02n01i02568ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(6.023E+24 = (2.003E+24 + 4.02E+24))
+      report "***PASSED TEST: c07s05b00x00p02n01i02568"
+      severity NOTE;
+    assert (6.023E+24 = (2.003E+24 + 4.02E+24))
+      report "***FAILED TEST: c07s05b00x00p02n01i02568 - The same operations are defined for the type universal_integer as for any integer type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s05b00x00p02n01i02568arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3018.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3018.vhd
new file mode 100644
index 0000000..4afca98
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3018.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3018.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c11s02b00x00p05n03i03018pkg IS
+  constant my_bool : boolean := false;
+END c11s02b00x00p05n03i03018pkg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3065.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3065.vhd
new file mode 100644
index 0000000..37d3730
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3065.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3065.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s04b02x00p02n01i03065ent IS
+END c12s04b02x00p02n01i03065ent;
+
+ARCHITECTURE c12s04b02x00p02n01i03065arch OF c12s04b02x00p02n01i03065ent IS
+  type   intvector is array (natural range <>) of integer;
+  signal   V2 : intvector(1 to 5);
+  signal   V0 : integer := 66;
+BEGIN
+  FG2: for i in V2'range generate
+    IG1: if i = V2'left generate
+      V2(i) <= V0 after 1 ns;
+    end generate;
+    IG2: if i /= V2'left generate
+      V2(i) <= V2(i-1) after 1 ns;
+    end generate;
+    -- ..., V2(2) <= V2(1), V2(1) <= V0
+  end generate;
+  TESTING: PROCESS
+  BEGIN
+    wait for 50 ns;
+    assert NOT( V2 = (66,66,66,66,66) )
+      report "***PASSED TEST: c12s04b02x00p02n01i03065"
+      severity NOTE;
+    assert ( V2 = (66,66,66,66,66) )
+      report "***FAILED TEST: c12s04b02x00p02n01i03065 - Generate statement semantic test failed."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c12s04b02x00p02n01i03065arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3090.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3090.vhd
new file mode 100644
index 0000000..ff4e3aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3090.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3090.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p02n01i03090ent IS
+END c05s01b00x00p02n01i03090ent;
+
+ARCHITECTURE c05s01b00x00p02n01i03090arch OF c05s01b00x00p02n01i03090ent IS
+  type       a       is range 1 to 10;
+  attribute    arbitrary   : integer;
+  attribute    arbitrary    of a : type is 5;  -- No_Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( a'arbitrary = 5 )
+      report "***PASSED TEST: c05s01b00x00p02n01i03090"
+      severity NOTE;
+    assert ( a'arbitrary = 5 )
+      report "***FAILED TEST: c05s01b00x00p02n01i03090 - Attribute specification syntax test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p02n01i03090arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3124.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3124.vhd
new file mode 100644
index 0000000..d8bb477
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3124.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3124.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p01n01i03124ent_a IS
+  generic ( socket_g1 : Boolean;
+            socket_g2 : Bit;
+            socket_g3 : character;
+            socket_g4 : severity_level;
+            socket_g5 : integer;
+            socket_g6 : real;
+            socket_g7 : time;
+            socket_g8 : natural;
+            socket_g9 : positive
+            );
+  port    ( socket_p1 : inout Boolean;
+            socket_p2 : inout Bit;
+            socket_p3 : inout character;
+            socket_p4 : inout severity_level;
+            socket_p5 : inout integer;
+            socket_p6 : inout real;
+            socket_p7 : inout time;
+            socket_p8 : inout natural;
+            socket_p9 : inout positive
+            );
+END c05s02b01x02p01n01i03124ent_a;
+
+ARCHITECTURE c05s02b01x02p01n01i03124arch_a OF c05s02b01x02p01n01i03124ent_a IS
+
+BEGIN
+  socket_p1 <= socket_g1 after 22 ns;
+  socket_p2 <= socket_g2 after 22 ns;
+  socket_p3 <= socket_g3 after 22 ns;
+  socket_p4 <= socket_g4 after 22 ns;
+  socket_p5 <= socket_g5 after 22 ns;
+  socket_p6 <= socket_g6 after 22 ns;
+  socket_p7 <= socket_g7 after 22 ns;
+  socket_p8 <= socket_g8 after 22 ns;
+  socket_p9 <= socket_g9 after 22 ns;
+END c05s02b01x02p01n01i03124arch_a;
+
+
+
+ENTITY c05s02b01x02p01n01i03124ent IS
+END c05s02b01x02p01n01i03124ent;
+
+ARCHITECTURE c05s02b01x02p01n01i03124arch OF c05s02b01x02p01n01i03124ent IS
+  component ic_socket
+    generic ( socket_g1 : Boolean;
+              socket_g2 : Bit;
+              socket_g3 : character;
+              socket_g4 : severity_level;
+              socket_g5 : integer;
+              socket_g6 : real;
+              socket_g7 : time;
+              socket_g8 : natural;
+              socket_g9 : positive
+              );
+    port    ( socket_p1 : inout Boolean;
+              socket_p2 : inout Bit;
+              socket_p3 : inout character;
+              socket_p4 : inout severity_level;
+              socket_p5 : inout integer;
+              socket_p6 : inout real;
+              socket_p7 : inout time;
+              socket_p8 : inout natural;
+              socket_p9 : inout positive
+              );
+  end component;
+  signal socket_p1 :  Boolean;
+  signal socket_p2 :  Bit;
+  signal socket_p3 :  character;
+  signal socket_p4 :  severity_level;
+  signal socket_p5 :  integer;
+  signal socket_p6 :  real;
+  signal socket_p7 :  time;
+  signal socket_p8 :  natural;
+  signal socket_p9 :  positive;
+BEGIN
+  instance : ic_socket
+    generic map ( true,
+                  '1',
+                  '$',
+                  warning,
+                  -100002,
+                  -9.999,
+                  20 ns,
+                  23423,
+                  4564576
+                  )
+    port map    ( socket_p1,
+                  socket_p2,
+                  socket_p3,
+                  socket_p4,
+                  socket_p5,
+                  socket_p6,
+                  socket_p7,
+                  socket_p8,
+                  socket_p9
+                  );
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 30 ns;
+    assert NOT(    socket_p1 = true   and
+                   socket_p2 = '1'      and
+                   socket_p3 = '$'      and
+                   socket_p4 = warning   and
+                   socket_p5 = -100002   and
+                   socket_p6 = -9.999   and
+                   socket_p7 = 20 ns   and
+                   socket_p8 = 23423   and
+                   socket_p9 = 4564576   )
+      report "***PASSED TEST: c05s02b01x02p01n01i03124"
+      severity NOTE;
+    assert (    socket_p1 = true   and
+                socket_p2 = '1'      and
+                socket_p3 = '$'      and
+                socket_p4 = warning   and
+                socket_p5 = -100002   and
+                socket_p6 = -9.999   and
+                socket_p7 = 20 ns   and
+                socket_p8 = 23423   and
+                socket_p9 = 4564576   )
+      report "***FAILED TEST: c05s02b01x02p01n01i03124 - Positional association generic and port list test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s02b01x02p01n01i03124arch;
+
+
+
+
+configuration c05s02b01x02p01n01i03124cfg of c05s02b01x02p01n01i03124ent is
+  for c05s02b01x02p01n01i03124arch
+    for instance : ic_socket use entity work.c05s02b01x02p01n01i03124ent_a (c05s02b01x02p01n01i03124arch_a)
+                               generic map ( true,
+                                             '1',
+                                             '$',
+                                             warning,
+                                             -100002,
+                                             -9.999,
+                                             20 ns,
+                                             23423,
+                                             4564576
+                                             )
+                               port map    ( socket_p1,
+                                             socket_p2,
+                                             socket_p3,
+                                             socket_p4,
+                                             socket_p5,
+                                             socket_p6,
+                                             socket_p7,
+                                             socket_p8,
+                                             socket_p9
+                                             );
+    end for;
+  end for;
+end c05s02b01x02p01n01i03124cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3129.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3129.vhd
new file mode 100644
index 0000000..5f6fc5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3129.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3129.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03129ent_a IS
+  generic ( g1 : boolean := false );
+END c05s02b01x02p12n01i03129ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03129arch_a OF c05s02b01x02p12n01i03129ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 report "g1=false" severity FAILURE;   
+    assert NOT( g1 = true ) 
+      report "***PASSED TEST: c05s02b01x02p12n01i03129"
+      severity NOTE;
+    assert ( g1 = true ) 
+      report "***FAILED TEST: c05s02b01x02p12n01i03129 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03129arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03129ent IS
+END c05s02b01x02p12n01i03129ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03129arch OF c05s02b01x02p12n01i03129ent IS
+  component ic_socket
+    generic ( local_g1 : Boolean := true );
+  end component;
+BEGIN
+  instance : ic_socket;
+END c05s02b01x02p12n01i03129arch;
+
+
+configuration c05s02b01x02p12n01i03129cfg of c05s02b01x02p12n01i03129ent is
+  for c05s02b01x02p12n01i03129arch
+    for instance : ic_socket use entity work.c05s02b01x02p12n01i03129ent_a (c05s02b01x02p12n01i03129arch_a)
+                               generic map ( true );
+    end for;
+  end for;
+end c05s02b01x02p12n01i03129cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3130.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3130.vhd
new file mode 100644
index 0000000..c16a637
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3130.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3130.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03130ent_a IS
+  generic ( g1 : boolean := false );
+END c05s02b01x02p12n01i03130ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03130arch_a OF c05s02b01x02p12n01i03130ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 report "g1=false" severity FAILURE;   
+    assert NOT( g1 = true ) 
+      report "***PASSED TEST: c05s02b01x02p12n01i03130"
+      severity NOTE;
+    assert ( g1 = true ) 
+      report "***FAILED TEST: c05s02b01x02p12n01i03130 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03130arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03130ent IS
+END c05s02b01x02p12n01i03130ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03130arch OF c05s02b01x02p12n01i03130ent IS
+  component ic_socket
+    generic ( local_g1 : Boolean := true );
+  end component;
+  for instance : ic_socket use entity work.c05s02b01x02p12n01i03130ent_a (c05s02b01x02p12n01i03130arch_a)
+    generic map ( true );
+BEGIN
+  instance : ic_socket;
+END c05s02b01x02p12n01i03130arch;
+
+
+configuration c05s02b01x02p12n01i03130cfg of c05s02b01x02p12n01i03130ent is
+  for c05s02b01x02p12n01i03130arch
+  end for;
+end c05s02b01x02p12n01i03130cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3131.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3131.vhd
new file mode 100644
index 0000000..23d79a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3131.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3131.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03131ent_a IS
+  generic ( g1 : boolean := false );
+END c05s02b01x02p12n01i03131ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03131arch_a OF c05s02b01x02p12n01i03131ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 report "g1=false" severity FAILURE;   
+    assert NOT( g1 = true ) 
+      report "***PASSED TEST: c05s02b01x02p12n01i03131"
+      severity NOTE;
+    assert ( g1 = true ) 
+      report "***FAILED TEST: c05s02b01x02p12n01i03131 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03131arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03131ent IS
+END c05s02b01x02p12n01i03131ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03131arch OF c05s02b01x02p12n01i03131ent IS
+
+BEGIN
+  labeled : block
+    component ic_socket
+      generic ( local_g1 : Boolean := true );
+    end component;
+    for instance : ic_socket use entity work .c05s02b01x02p12n01i03131ent_a (c05s02b01x02p12n01i03131arch_a)
+      generic map ( true );
+  begin
+    instance : ic_socket;
+  end block;
+END c05s02b01x02p12n01i03131arch;
+
+
+configuration c05s02b01x02p12n01i03131cfg of c05s02b01x02p12n01i03131ent is
+  for c05s02b01x02p12n01i03131arch
+  end for;
+end c05s02b01x02p12n01i03131cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3132.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3132.vhd
new file mode 100644
index 0000000..d8717bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3132.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3132.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c05s02b01x02p12n01i03132pkg is
+  CONSTANT do_baby : boolean := true;
+end c05s02b01x02p12n01i03132pkg;
+
+
+ENTITY c05s02b01x02p12n01i03132ent_a IS
+  generic ( g1 : boolean := false );
+END c05s02b01x02p12n01i03132ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03132arch_a OF c05s02b01x02p12n01i03132ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 report "g1=false" severity FAILURE;   
+    assert NOT( g1 = true ) 
+      report "***PASSED TEST: c05s02b01x02p12n01i03132"
+      severity NOTE;
+    assert ( g1 = true ) 
+      report "***FAILED TEST: c05s02b01x02p12n01i03132 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03132arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03132ent IS
+END c05s02b01x02p12n01i03132ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03132arch OF c05s02b01x02p12n01i03132ent IS
+  component ic_socket
+    generic ( local_g1 : Boolean := true );
+  end component;
+  for instance : ic_socket use entity work.c05s02b01x02p12n01i03132ent_a (c05s02b01x02p12n01i03132arch_a)
+    generic map ( work.c05s02b01x02p12n01i03132pkg.do_baby );
+BEGIN
+  instance : ic_socket;
+END c05s02b01x02p12n01i03132arch;
+
+
+configuration c05s02b01x02p12n01i03132cfg of c05s02b01x02p12n01i03132ent is
+  for c05s02b01x02p12n01i03132arch
+  end for;
+end c05s02b01x02p12n01i03132cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3133.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3133.vhd
new file mode 100644
index 0000000..439f4c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3133.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3133.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c05s02b01x02p12n01i03133pkg is
+  CONSTANT do_baby : boolean := true;
+end c05s02b01x02p12n01i03133pkg;
+
+
+ENTITY c05s02b01x02p12n01i03133ent_a IS
+  generic ( g1 : boolean := false );
+END c05s02b01x02p12n01i03133ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03133arch_a OF c05s02b01x02p12n01i03133ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 report "g1=false" severity FAILURE;   
+    assert NOT( g1 = true ) 
+      report "***PASSED TEST: c05s02b01x02p12n01i03133"
+      severity NOTE;
+    assert ( g1 = true ) 
+      report "***FAILED TEST: c05s02b01x02p12n01i03133 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03133arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03133ent IS
+END c05s02b01x02p12n01i03133ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03133arch OF c05s02b01x02p12n01i03133ent IS
+BEGIN
+  labeled : block
+    component ic_socket
+      generic ( local_g1 : Boolean := true );
+    end component;
+    for instance : ic_socket use entity work.c05s02b01x02p12n01i03133ent_a (c05s02b01x02p12n01i03133arch_a)
+      generic map ( work.c05s02b01x02p12n01i03133pkg.do_baby );
+  begin
+    instance : ic_socket;
+  end block;
+END c05s02b01x02p12n01i03133arch;
+
+
+configuration c05s02b01x02p12n01i03133cfg of c05s02b01x02p12n01i03133ent is
+  for c05s02b01x02p12n01i03133arch
+  end for;
+end c05s02b01x02p12n01i03133cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3134.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3134.vhd
new file mode 100644
index 0000000..344d81d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3134.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3134.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03134ent_a IS
+  generic ( g1 : integer := 0 );
+END c05s02b01x02p12n01i03134ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03134arch_a OF c05s02b01x02p12n01i03134ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 /= 0    report "g1 = 0 "    severity FAILURE;
+    assert g1 /= 1    report "g1 = 1 "    severity FAILURE;
+    assert g1 = -1    report "g1 /= -1 "    severity FAILURE;
+    assert NOT(    g1 /= 0   and
+                   g1 /= 1   and
+                   g1 = -1   )   
+      report "***PASSED TEST: c05s02b01x02p12n01i03134"
+      severity NOTE;
+    assert (    g1 /= 0   and
+                g1 /= 1   and
+                g1 = -1   )   
+      report "***FAILED TEST: c05s02b01x02p12n01i03134 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03134arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03134ent IS
+  generic ( test_g : integer := -1 );
+END c05s02b01x02p12n01i03134ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03134arch OF c05s02b01x02p12n01i03134ent IS
+  component ic_socket
+    generic ( local_g1 : integer := 1 );
+  end component;
+BEGIN
+  instance : ic_socket;
+END c05s02b01x02p12n01i03134arch;
+
+
+configuration c05s02b01x02p12n01i03134cfg of c05s02b01x02p12n01i03134ent is
+  for c05s02b01x02p12n01i03134arch
+    for instance : ic_socket use entity work.c05s02b01x02p12n01i03134ent_a (c05s02b01x02p12n01i03134arch_a)
+                               generic map (test_g);
+    end for;
+  end for;
+end c05s02b01x02p12n01i03134cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3135.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3135.vhd
new file mode 100644
index 0000000..8a4bb23
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3135.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3135.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03135ent_a IS
+  generic ( g1 : integer := 0 );
+END c05s02b01x02p12n01i03135ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03135arch_a OF c05s02b01x02p12n01i03135ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 /= 0    report "g1 = 0 "    severity FAILURE;
+    assert g1 /= 1    report "g1 = 1 "    severity FAILURE;
+    assert g1 = -1    report "g1 /= -1 "    severity FAILURE;
+    assert NOT(    g1 /= 0   and
+                   g1 /= 1   and
+                   g1 = -1   )   
+      report "***PASSED TEST: c05s02b01x02p12n01i03135"
+      severity NOTE;
+    assert (    g1 /= 0   and
+                g1 /= 1   and
+                g1 = -1   )   
+      report "***FAILED TEST: c05s02b01x02p12n01i03135 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03135arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03135ent IS
+  generic ( test_g : integer := -1 );
+END c05s02b01x02p12n01i03135ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03135arch OF c05s02b01x02p12n01i03135ent IS
+  component ic_socket
+    generic ( local_g1 : integer := 1 );
+  end component;
+  for instance : ic_socket use entity work.c05s02b01x02p12n01i03135ent_a (c05s02b01x02p12n01i03135arch_a)
+    generic map (test_g);
+BEGIN
+  instance : ic_socket;
+END c05s02b01x02p12n01i03135arch;
+
+
+configuration c05s02b01x02p12n01i03135cfg of c05s02b01x02p12n01i03135ent is
+  for c05s02b01x02p12n01i03135arch
+  end for;
+end c05s02b01x02p12n01i03135cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3136.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3136.vhd
new file mode 100644
index 0000000..4bd7166
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3136.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3136.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s02b01x02p12n01i03136ent_a IS
+  generic ( g1 : integer := 0 );
+END c05s02b01x02p12n01i03136ent_a;
+
+ARCHITECTURE c05s02b01x02p12n01i03136arch_a OF c05s02b01x02p12n01i03136ent_a IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert g1 /= 0    report "g1 = 0 "    severity FAILURE;
+    assert g1 /= 1    report "g1 = 1 "    severity FAILURE;
+    assert g1 = -1    report "g1 /= -1 "    severity FAILURE;
+    assert NOT(    g1 /= 0   and
+                   g1 /= 1   and
+                   g1 = -1   )   
+      report "***PASSED TEST: c05s02b01x02p12n01i03136"
+      severity NOTE;
+    assert (    g1 /= 0   and
+                g1 /= 1   and
+                g1 = -1   )   
+      report "***FAILED TEST: c05s02b01x02p12n01i03136 - An actual associated with a formal generic in a generic map aspect be an expression test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c05s02b01x02p12n01i03136arch_a;
+
+
+
+
+ENTITY c05s02b01x02p12n01i03136ent IS
+  generic ( test_g : integer := -1 );
+END c05s02b01x02p12n01i03136ent;
+
+ARCHITECTURE c05s02b01x02p12n01i03136arch OF c05s02b01x02p12n01i03136ent IS
+BEGIN
+  labeled : block
+    component ic_socket
+      generic ( local_g1 : integer := 1 );
+    end component;
+    for instance : ic_socket use entity work.c05s02b01x02p12n01i03136ent_a (c05s02b01x02p12n01i03136arch_a)
+      generic map (test_g);
+  begin
+    instance : ic_socket;
+  end block;
+END c05s02b01x02p12n01i03136arch;
+
+
+configuration c05s02b01x02p12n01i03136cfg of c05s02b01x02p12n01i03136ent is
+  for c05s02b01x02p12n01i03136arch
+  end for;
+end c05s02b01x02p12n01i03136cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc59.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc59.vhd
new file mode 100644
index 0000000..c9ce7f5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc59.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc59.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p05n01i00059ent IS
+END c04s03b01x01p05n01i00059ent;
+
+ARCHITECTURE c04s03b01x01p05n01i00059arch OF c04s03b01x01p05n01i00059ent IS
+  signal S1 : integer := 10;
+BEGIN
+  TESTING : PROCESS
+    variable TimeCount : time := 0 ns;
+  BEGIN
+    S1 <= transport N1 after T1 ;    -- No_failure_here
+    wait for T1;
+    assert NOT(S1'active and S1 = 20)
+      report "***PASSED TEST:c04s03b01x01p05n01i00059"
+      severity NOTE;
+    assert (S1'active and S1 = 20)
+      report "***FAILED TEST:c04s03b01x01p05n01i00059 - Generics constant test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p05n01i00059arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc737.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc737.vhd
new file mode 100644
index 0000000..0f7e0b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc737.vhd
@@ -0,0 +1,122 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc737.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s01b01x01p04n01i00737ent_a is
+  generic (
+    constant gc1 : in integer;
+    constant gc2 : in real;
+    constant gc3 : in boolean
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x01p04n01i00737ent_a;
+
+architecture c01s01b01x01p04n01i00737arch_a of c01s01b01x01p04n01i00737ent_a is
+begin
+  p0: process
+  begin
+    wait for 1 ns;
+    if (gc1 = 5) AND (gc2 = 0.1234) AND (gc3) then
+      assert FALSE 
+        report "***PASSED TEST: c01s01b01x01p04n01i00737"
+        severity NOTE;
+    else
+      assert FALSE
+        report "***FAILED TEST: c01s01b01x01p04n01i00737 - Simple generic association in component instantiation (type conversion done on actual in generic map failed)."
+        severity ERROR;
+    end if;
+    wait;
+  end process;
+end c01s01b01x01p04n01i00737arch_a;
+
+
+ENTITY c01s01b01x01p04n01i00737ent IS
+  generic ( constant gen_con : integer := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x01p04n01i00737ent;
+
+ARCHITECTURE c01s01b01x01p04n01i00737arch OF c01s01b01x01p04n01i00737ent IS
+  constant    c1 : integer    := 33;
+  constant    c2 : real    := 1.23557;
+  constant    c3 : boolean    := FALSE;
+  signal       s1 : integer;
+  signal       s2 : integer;
+  signal       s3 : integer;
+
+  component comp1
+    generic (
+      constant dgc1 : integer;
+      constant dgc2 : real;
+      constant dgc3 : boolean
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+  
+  for u1 : comp1 use
+    entity work.c01s01b01x01p04n01i00737ent_a(c01s01b01x01p04n01i00737_arch_a)
+    generic map (dgc1, dgc2, dgc3)
+    port map ( dcent1, dcent2 );
+
+  function BoolToInt(bin : boolean) return integer is
+  begin
+    if bin then
+      return 5;
+    else
+      return 99;
+    end if;
+  end;
+  
+  function IntegerToReal(iin : integer) return real is
+  begin
+    return 0.1234;
+  end;
+  
+  function BitToBool(bin : bit) return boolean is
+  begin
+    if (bin = '1') then
+      return TRUE;
+    else
+      return FALSE;
+    end if;
+  end;
+
+BEGIN
+  
+  u1 : comp1
+    generic map (BoolToInt(TRUE), IntegerToReal(1234), BitToBool('1'))
+    port map (ee1,ee2);
+
+END c01s01b01x01p04n01i00737arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc758.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc758.vhd
new file mode 100644
index 0000000..b4e9123
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc758.vhd
@@ -0,0 +1,186 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc758.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x01p05n02i00758pkg is
+
+--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE
+--Index type is natural  
+  type boolean_vector       is array (natural range <>) of boolean;
+  type severity_level_vector    is array (natural range <>) of severity_level;
+  type integer_vector       is array (natural range <>) of integer; 
+  type real_vector       is array (natural range <>) of real;
+  type time_vector       is array (natural range <>) of time;
+  type natural_vector       is array (natural range <>) of natural;
+  type positive_vector    is array (natural range <>) of positive;
+
+  constant C1    : boolean    := true; 
+  constant C2    : bit       := '1';
+  constant C3    : character    := 's';
+  constant C4    : severity_level:= note; 
+  constant C5    : integer    := 3;
+  constant C6    : real       := 3.0;
+  constant C7    : time       := 3 ns;
+  constant C8    : natural    := 1;
+  constant C9    : positive    := 1;
+  constant C10    : string    := "shishir";
+  constant C11    : bit_vector    := B"0011";
+  constant C12    : boolean_vector:= (true,false); 
+  constant C13    : severity_level_vector := (note,error);
+  constant C14    : integer_vector:= (1,2,3,4); 
+  constant C15    : real_vector    := (1.0,2.0,3.0,4.0); 
+  constant C16    : time_vector    := (1 ns, 2 ns, 3 ns, 4 ns);
+  constant C17    : natural_vector:= (1,2,3,4);
+  constant C18    : positive_vector:= (1,2,3,4);
+
+end c01s01b01x01p05n02i00758pkg;
+
+use   work.c01s01b01x01p05n02i00758pkg.ALL;
+ENTITY c01s01b01x01p05n02i00758ent IS
+  generic(
+    zero    : integer := 0;
+    one     : integer := 1;
+    two     : integer := 2;
+    three   : integer := 3;
+    four    : integer := 4;
+    five    : integer := 5;
+    six     : integer := 6;
+    seven   : integer := 7;
+    eight   : integer := 8;
+    nine    : integer := 9;
+    fifteen   : integer:= 15;
+    Cgen1    : boolean := true;
+    Cgen2    : bit := '1';
+    Cgen3    : character := 's';
+    Cgen4    : severity_level := note;
+    Cgen5    : integer := 3;
+    Cgen6    : real := 3.0;
+    Cgen7    : time := 3 ns;
+    Cgen8    : natural := 1;
+    Cgen9    : positive := 1;
+    Cgen10    : string := "shishir";
+    Cgen11    : bit_vector := B"0011";
+    Cgen12    : boolean_vector := (true,false);
+    Cgen13    : severity_level_vector := (note,error);
+    Cgen14    : integer_vector := (1,2,3,4);
+    Cgen15    : real_vector := (1.0,2.0,3.0,4.0);
+    Cgen16    : time_vector := (1 ns, 2 ns, 3 ns, 4 ns);
+    Cgen17    : natural_vector := (1,2,3,4);
+    Cgen18    : positive_vector := (1,2,3,4)   );
+  port(
+    Vgen1    : boolean    := true;
+    Vgen2    : bit       := '1';
+    Vgen3    : character    := 's';
+    Vgen4    : severity_level:= note;
+    Vgen5    : integer    := 3;
+    Vgen6    : real       := 3.0;
+    Vgen7    : time       := 3 ns;
+    Vgen8    : natural    := 1;
+    Vgen9    : positive    := 1;
+    Vgen10    : string    := "shishir";
+    Vgen11    : bit_vector    := B"0011";
+    Vgen12    : boolean_vector:= (true,false);
+    Vgen13    : severity_level_vector := (note,error);
+    Vgen14    : integer_vector:= (1,2,3,4);
+    Vgen15    : real_vector    := (1.0,2.0,3.0,4.0);
+    Vgen16    : time_vector    := (1 ns, 2 ns, 3 ns, 4 ns);
+    Vgen17    : natural_vector:= (1,2,3,4);
+    Vgen18    : positive_vector:= (1,2,3,4)
+    );
+END c01s01b01x01p05n02i00758ent;
+
+ARCHITECTURE c01s01b01x01p05n02i00758arch OF c01s01b01x01p05n02i00758ent IS
+  
+BEGIN
+  assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error;
+  assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error;
+  assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error;
+  assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error;
+  assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error;
+  assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error;
+  assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error;
+  assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error;
+  assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error;
+  assert Vgen10 = C10 report "Initializing signal with generic Vgen10 does not work" severity error;
+  assert Vgen11 = C11 report "Initializing signal with generic Vgen11 does not work" severity error;
+  assert Vgen12 = C12 report "Initializing signal with generic Vgen12 does not work" severity error;
+  assert Vgen13 = C13 report "Initializing signal with generic Vgen13 does not work" severity error;
+  assert Vgen14 = C14 report "Initializing signal with generic Vgen14 does not work" severity error;
+  assert Vgen15 = C15 report "Initializing signal with generic Vgen15 does not work" severity error;
+  assert Vgen16 = C16 report "Initializing signal with generic Vgen16 does not work" severity error;
+  assert Vgen17 = C17 report "Initializing signal with generic Vgen17 does not work" severity error;
+  assert Vgen18 = C18 report "Initializing signal with generic Vgen18 does not work" severity error;
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert NOT(     Vgen1 = C1 and 
+                    Vgen2 = C2 and 
+                    Vgen3 = C3 and 
+                    Vgen4 = C4 and 
+                    Vgen5 = C5 and 
+                    Vgen6 = C6 and 
+                    Vgen7 = C7 and 
+                    Vgen8 = C8 and 
+                    Vgen9 = C9 and 
+                    Vgen10 = C10 and 
+                    Vgen11 = C11 and 
+                    Vgen12 = C12 and 
+                    Vgen13 = C13 and 
+                    Vgen14 = C14 and 
+                    Vgen15 = C15 and 
+                    Vgen16 = C16 and 
+                    Vgen17 = C17 and 
+                    Vgen18 = C18 ) 
+      report "***PASSED TEST: c01s01b01x01p05n02i00758"
+      severity NOTE;
+    assert(        Vgen1 = C1 and 
+                   Vgen2 = C2 and 
+                   Vgen3 = C3 and 
+                   Vgen4 = C4 and 
+                   Vgen5 = C5 and 
+                   Vgen6 = C6 and 
+                   Vgen7 = C7 and 
+                   Vgen8 = C8 and 
+                   Vgen9 = C9 and 
+                   Vgen10 = C10 and 
+                   Vgen11 = C11 and 
+                   Vgen12 = C12 and 
+                   Vgen13 = C13 and 
+                   Vgen14 = C14 and 
+                   Vgen15 = C15 and 
+                   Vgen16 = C16 and 
+                   Vgen17 = C17 and 
+                   Vgen18 = C18 ) 
+      report "***FAILED TEST: c01s01b01x01p05n02i00758 - Generic can be used to specify the size of ports."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p05n02i00758arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc814.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc814.vhd
new file mode 100644
index 0000000..7b526e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc814.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc814.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b00x00p04n02i00814ent IS
+END c01s02b00x00p04n02i00814ent;
+
+ARCHITECTURE c01s02b00x00p04n02i00814arch OF c01s02b00x00p04n02i00814ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s02b00x00p04n02i00814 - Entity declaration and architecture body must reside in the same library."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p04n02i00814arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc816.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc816.vhd
new file mode 100644
index 0000000..e8f634b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc816.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc816.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b00x00p06n01i00816ent IS
+END c01s02b00x00p06n01i00816ent;
+
+ARCHITECTURE c01s02b00x00p06n01i00816arch OF c01s02b00x00p06n01i00816ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***PASSED TEST: c01s02b00x00p06n01i00816"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p06n01i00816arch;
+
+
+ARCHITECTURE c01s02b00x00p06n01i00816arch_2 OF c01s02b00x00p06n01i00816ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    null;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p06n01i00816arch_2;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc833.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc833.vhd
new file mode 100644
index 0000000..b881fb1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc833.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc833.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s03b00x00p05n02i00833ent IS
+END c01s03b00x00p05n02i00833ent;
+
+ARCHITECTURE c01s03b00x00p05n02i00833arch OF c01s03b00x00p05n02i00833ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+--   assert FALSE
+--      report "***FAILED TEST: c01s03b00x00p05n02i00833 - Configuration declaration and corresponding entity declaration must reside in the same library."
+--      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b00x00p05n02i00833arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc851.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc851.vhd
new file mode 100644
index 0000000..f580da2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc851.vhd
@@ -0,0 +1,291 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc851.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00851pkg_b is
+  constant zero : integer ;
+  constant one  : integer ;
+  constant two  : integer ;
+  constant three: integer ;
+  constant four : integer ;
+  constant five : integer ;
+  constant six  : integer ;
+  constant seven: integer ;
+  constant eight: integer ;
+  constant nine : integer ;
+  constant fifteen: integer;
+end c01s03b01x00p12n01i00851pkg_b;
+
+package body c01s03b01x00p12n01i00851pkg_b is
+  constant zero : integer := 0;
+  constant one  : integer := 1;
+  constant two  : integer := 2;
+  constant three: integer := 3;
+  constant four : integer := 4;
+  constant five : integer := 5;
+  constant six  : integer := 6;
+  constant seven: integer := 7;
+  constant eight: integer := 8;
+  constant nine : integer := 9;
+  constant fifteen:integer:= 15;
+end c01s03b01x00p12n01i00851pkg_b;
+
+use work.c01s03b01x00p12n01i00851pkg_b.all;
+package c01s03b01x00p12n01i00851pkg_a is
+  constant low_number : integer := 0;
+  constant hi_number : integer := 3;
+  subtype hi_to_low_range is integer range low_number to hi_number;
+  type boolean_vector is array (natural range <>) of boolean;
+  type severity_level_vector is array (natural range <>) of severity_level;
+  type integer_vector is array (natural range <>) of integer;
+  type real_vector is array (natural range <>) of real;
+  type time_vector is array (natural range <>) of time;
+  type natural_vector is array (natural range <>) of natural;
+  type positive_vector is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type array_rec_std is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean := true;
+  constant C2 : bit := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer := 3;
+  constant C6 : real := 3.0;
+  constant C7 : time := 3 ns;
+  constant C8 : natural := 1;
+  constant C9 : positive := 1;
+  signal Sin1 : bit_vector(zero to five) ;
+  signal Sin2 : boolean_vector(zero to five) ;
+  signal Sin4 : severity_level_vector(zero to five) ;
+  signal Sin5 : integer_vector(zero to five) ;
+  signal Sin6 : real_vector(zero to five) ;
+  signal Sin7 : time_vector(zero to five) ;
+  signal Sin8 : natural_vector(zero to five) ;
+  signal Sin9 : positive_vector(zero to five) ;
+  signal Sin10: array_rec_std(zero to five) ;
+end c01s03b01x00p12n01i00851pkg_a;
+
+use work.c01s03b01x00p12n01i00851pkg_a.all;
+use work.c01s03b01x00p12n01i00851pkg_b.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00851pkg_a.all;
+use work.c01s03b01x00p12n01i00851pkg_b.all;
+ENTITY c01s03b01x00p12n01i00851ent IS
+END c01s03b01x00p12n01i00851ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00851arch OF c01s03b01x00p12n01i00851ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00851"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00851 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00851arch;
+
+configuration c01s03b01x00p12n01i00851cfg of c01s03b01x00p12n01i00851ent is
+  for c01s03b01x00p12n01i00851arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(three downto zero)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc865.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc865.vhd
new file mode 100644
index 0000000..840368f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc865.vhd
@@ -0,0 +1,278 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc865.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s03b01x00p12n01i00865pkg is
+  constant    low_number    : integer := 0;
+  constant    hi_number    : integer := 3;
+  subtype    hi_to_low_range    is integer range low_number to hi_number;
+  type    boolean_vector       is array (natural range <>) of boolean;
+  type    severity_level_vector    is array (natural range <>) of severity_level;
+  type    integer_vector       is array (natural range <>) of integer;
+  type    real_vector       is array (natural range <>) of real;
+  type    time_vector       is array (natural range <>) of time;
+  type    natural_vector       is array (natural range <>) of natural;
+  type    positive_vector    is array (natural range <>) of positive;
+  type record_std_package is record
+                               a: boolean;
+                               b: bit;
+                               c:character;
+                               d:severity_level;
+                               e:integer;
+                               f:real;
+                               g:time;
+                               h:natural;
+                               i:positive;
+                             end record;
+  type    array_rec_std       is array (natural range <>) of record_std_package;
+  type four_value is ('Z','0','1','X');                                 
+--enumerated type
+  constant C1 : boolean    := true;
+  constant C2 : bit    := '1';
+  constant C3 : character := 's';
+  constant C4 : severity_level := note;
+  constant C5 : integer    := 3;
+  constant C6 : real    := 3.0;
+  constant C7 : time    := 3 ns;
+  constant C8 : natural    := 1;
+  constant C9 : positive    := 1;
+  signal dumy : bit_vector(0 to 3);
+  signal Sin1 : bit_vector(0 to 5) ;
+  signal Sin2 : boolean_vector(0 to 5) ;
+  signal Sin4 : severity_level_vector(0 to 5) ;
+  signal Sin5 : integer_vector(0 to 5) ;
+  signal Sin6 : real_vector(0 to 5) ;
+  signal Sin7 : time_vector(0 to 5) ;
+  signal Sin8 : natural_vector(0 to 5) ;
+  signal Sin9 : positive_vector(0 to 5) ;
+  signal Sin10: array_rec_std(0 to 5) ;
+end c01s03b01x00p12n01i00865pkg;
+
+use work.c01s03b01x00p12n01i00865pkg.all;
+entity test is
+  port(
+    sigin1  : in  boolean ;
+    sigout1 : out boolean ;
+    sigin2  : in  bit ;
+    sigout2 : out bit ;
+    sigin4  : in  severity_level ;
+    sigout4 : out severity_level ;
+    sigin5  : in  integer ;
+    sigout5 : out integer ;
+    sigin6  : in  real ;
+    sigout6 : out real ;
+    sigin7  : in  time ;
+    sigout7 : out time ;
+    sigin8  : in  natural ;
+    sigout8 : out natural ;
+    sigin9  : in  positive ;
+    sigout9 : out positive ;
+    sigin10  : in  record_std_package ;
+    sigout10 : out record_std_package
+    );
+end;
+
+architecture test of test is
+begin
+  sigout1 <= sigin1;
+  sigout2 <= sigin2;
+  sigout4 <= sigin4;
+  sigout5 <= sigin5;
+  sigout6 <= sigin6;
+  sigout7 <= sigin7;
+  sigout8 <= sigin8;
+  sigout9 <= sigin9;
+  sigout10 <= sigin10;
+end;
+
+configuration testbench of test is
+  for test
+  end for;
+end;
+
+use work.c01s03b01x00p12n01i00865pkg.all;
+ENTITY c01s03b01x00p12n01i00865ent IS
+  generic(
+    zero : integer := 0;
+    one  : integer := 1;
+    two  : integer := 2;
+    three: integer := 3;
+    four : integer := 4;
+    five : integer := 5;
+    six  : integer := 6;
+    seven: integer := 7;
+    eight: integer := 8;
+    nine : integer := 9;
+    fifteen:integer:= 15);
+END c01s03b01x00p12n01i00865ent;
+
+ARCHITECTURE c01s03b01x00p12n01i00865arch OF c01s03b01x00p12n01i00865ent IS
+  component test
+    port(
+      sigin1  : in  boolean ;
+      sigout1 : out boolean ;
+      sigin2  : in  bit ;
+      sigout2 : out bit ;
+      sigin4  : in  severity_level ;
+      sigout4 : out severity_level ;
+      sigin5  : in  integer ;
+      sigout5 : out integer ;
+      sigin6  : in  real ;
+      sigout6 : out real ;
+      sigin7  : in  time ;
+      sigout7 : out time ;
+      sigin8  : in  natural ;
+      sigout8 : out natural ;
+      sigin9  : in  positive ;
+      sigout9 : out positive ;
+      sigin10  : in  record_std_package ;
+      sigout10 : out record_std_package
+      );
+  end component;
+begin
+  Sin1(zero) <='1';
+  Sin2(zero) <= true;
+  Sin4(zero) <= note;
+  Sin5(zero) <= 3;
+  Sin6(zero) <= 3.0;
+  Sin7(zero) <= 3 ns;
+  Sin8(zero) <= 1;
+  Sin9(zero) <= 1;
+  Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
+  K:block
+    component test
+      port(
+        sigin1  : in  boolean ;
+        sigout1 : out boolean ;
+        sigin2  : in  bit ;
+        sigout2 : out bit ;
+        sigin4  : in  severity_level ;
+        sigout4 : out severity_level ;
+        sigin5  : in  integer ;
+        sigout5 : out integer ;
+        sigin6  : in  real ;
+        sigout6 : out real ;
+        sigin7  : in  time ;
+        sigout7 : out time ;
+        sigin8  : in  natural ;
+        sigout8 : out natural ;
+        sigin9  : in  positive ;
+        sigout9 : out positive ;
+        sigin10  : in  record_std_package ;
+        sigout10 : out record_std_package
+        );
+    end component;
+
+  BEGIN
+    T5 : test
+      port map
+      (
+        Sin2(4),Sin2(5),
+        Sin1(4),Sin1(5),
+        Sin4(4),Sin4(5),
+        Sin5(4),Sin5(5),
+        Sin6(4),Sin6(5),
+        Sin7(4),Sin7(5),
+        Sin8(4),Sin8(5),
+        Sin9(4),Sin9(5),
+        Sin10(4),Sin10(5)
+        );
+    G: for i in zero to three generate
+      T1:test
+        port map
+        (
+          Sin2(i),Sin2(i+1),
+          Sin1(i),Sin1(i+1),
+          Sin4(i),Sin4(i+1),
+          Sin5(i),Sin5(i+1),
+          Sin6(i),Sin6(i+1),
+          Sin7(i),Sin7(i+1),
+          Sin8(i),Sin8(i+1),
+          Sin9(i),Sin9(i+1),
+          Sin10(i),Sin10(i+1)
+          );
+    end generate;
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
+    assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
+    assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
+    assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
+    assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
+    assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
+    assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
+    assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
+    assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
+    assert NOT(    Sin1(0) = sin1(5)   and
+                   Sin2(0) = Sin2(5)   and
+                   Sin4(0) = Sin4(5)   and
+                   Sin5(0) = Sin5(5)   and
+                   Sin6(0) = Sin6(5)   and
+                   Sin7(0) = Sin7(5)   and
+                   Sin8(0) = Sin8(5)   and
+                   Sin9(0) = Sin9(5)   and
+                   Sin10(0)= Sin10(0)   )
+      report "***PASSED TEST: c01s03b01x00p12n01i00865"
+      severity NOTE;
+    assert (    Sin1(0) = sin1(5)   and
+                Sin2(0) = Sin2(5)   and
+                Sin4(0) = Sin4(5)   and
+                Sin5(0) = Sin5(5)   and
+                Sin6(0) = Sin6(5)   and
+                Sin7(0) = Sin7(5)   and
+                Sin8(0) = Sin8(5)   and
+                Sin9(0) = Sin9(5)   and
+                Sin10(0)= Sin10(0)   )
+      report "***FAILED TEST: c01s03b01x00p12n01i00865 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p12n01i00865arch;
+
+configuration c01s03b01x00p12n01i00865cfg of c01s03b01x00p12n01i00865ent is
+  for c01s03b01x00p12n01i00865arch
+    for K
+      for T5:test use configuration work.testbench;
+      end for;
+      for G(zero to one)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+      for G(three downto two)
+        for T1:test
+          use configuration work.testbench;
+        end for;
+      end for;
+    end for;
+  end for;
+end;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc882.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc882.vhd
new file mode 100644
index 0000000..8f46577
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc882.vhd
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc882.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c10s01b00x00p07n01i00882ent_a is
+  generic (
+    GS1: INTEGER := 3;
+    GS2: INTEGER := 9
+    );
+  port (
+    PS1: out INTEGER;
+    PS2: out INTEGER
+    );
+end c10s01b00x00p07n01i00882ent_a;
+
+architecture c10s01b00x00p07n01i00882arch_a of c10s01b00x00p07n01i00882ent_a is
+  
+begin
+  process
+  begin
+    PS1 <= GS1 + 1;
+    PS2 <= GS2 + 2;
+    wait; -- forever
+  end process;
+end c10s01b00x00p07n01i00882arch_a;
+
+use WORK.c10s01b00x00p07n01i00882ent_a;
+ENTITY c10s01b00x00p07n01i00882ent IS
+END c10s01b00x00p07n01i00882ent;
+
+ARCHITECTURE c10s01b00x00p07n01i00882arch OF c10s01b00x00p07n01i00882ent IS
+  
+  signal G1: INTEGER;
+  signal G2: INTEGER;
+  signal A : INTEGER;
+  signal B : INTEGER;
+  component c10s01b00x00p07n01i00882ent_a
+    generic ( G1, G2: INTEGER );
+    port ( A, B: out INTEGER );
+  end component;
+  signal S1: INTEGER;
+  signal S2: INTEGER;
+  
+BEGIN
+  
+  A1: c10s01b00x00p07n01i00882ent_a generic map ( 3, 9 ) port map ( S1, S2 );
+  
+  -- verification
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert NOT( S1=4 and S2=11 )
+      report "***PASSED TEST: c10s01b00x00p07n01i00882"
+      severity NOTE;
+    assert ( S1=4 and S2=11 )
+      report "***FAILED TEST: c10s01b00x00p07n01i00882 - A declarative region is formed by the text of a component declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s01b00x00p07n01i00882arch;
+
+configuration c10s01b00x00p07n01i00882cfg of c10s01b00x00p07n01i00882ent is
+  for c10s01b00x00p07n01i00882arch
+    for A1: c10s01b00x00p07n01i00882ent_a
+      use entity c10s01b00x00p07n01i00882ent_a (c10s01b00x00p07n01i00882arch_a )
+        generic map ( G1, G2 )
+        port map ( A, B );
+    end for;
+  end for;
+end c10s01b00x00p07n01i00882cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc996.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc996.vhd
new file mode 100644
index 0000000..cd08a71
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc996.vhd
@@ -0,0 +1,200 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc996.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- too mangled up to fix for me
+
+PACKAGE c06s03b00x00p08n01i00996pkg IS
+--
+--  This packages contains declarations of User attributes
+--
+-- ----------------------------------------------------------------------
+--
+  TYPE RESISTANCE IS RANGE 0 TO 1E9
+    UNITS
+      pf;
+      nf = 1000 pf;
+      mf = 1000 nf;
+    END UNITS;
+
+  TYPE t_logic IS (
+    U,  D,
+    Z0, Z1, ZDX, DZX, ZX,
+    W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
+    R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
+    F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
+    );
+--
+--          Scalar types Declarations
+--
+  SUBTYPE st_scl1 IS BOOLEAN;
+  SUBTYPE st_scl2 IS BIT;
+  SUBTYPE st_scl3 IS CHARACTER;
+  SUBTYPE st_scl4 IS INTEGER;
+  SUBTYPE st_scl5 IS REAL;
+  SUBTYPE st_scl6 IS TIME;
+  SUBTYPE st_scl7 IS RESISTANCE;
+  SUBTYPE st_scl8 IS t_logic;
+--
+--          character string types
+--
+  SUBTYPE st_str1 IS STRING;
+  SUBTYPE st_str2 IS STRING (1 TO 4);
+  
+-- ---------------------------------------------------------------------
+--      Attribute Declarations
+-- ---------------------------------------------------------------------
+--
+  ATTRIBUTE atr_scl1 : st_scl1;
+  ATTRIBUTE atr_scl2 : st_scl2;
+  ATTRIBUTE atr_scl3 : st_scl3;
+  ATTRIBUTE atr_scl4 : st_scl4;
+  ATTRIBUTE atr_scl5 : st_scl5;
+  ATTRIBUTE atr_scl6 : st_scl6;
+  ATTRIBUTE atr_scl7 : st_scl7;
+  ATTRIBUTE atr_scl8 : st_scl8;
+  ATTRIBUTE atr_str1 : st_str1;
+  ATTRIBUTE atr_str2 : st_str2;
+  
+END;
+
+USE WORK.c06s03b00x00p08n01i00996pkg.all;
+ENTITY c06s03b00x00p08n01i00996ent IS
+  GENERIC (
+    p_scl1 : st_scl1;
+    p_scl2 : st_scl2;
+    p_scl3 : st_scl3;
+    p_scl4 : st_scl4;
+    p_scl5 : st_scl5;
+    p_scl6 : st_scl6;
+    p_scl7 : st_scl7;
+    p_scl8 : st_scl8;
+    p_str1 : st_str1;
+    p_str2 : st_str2;
+    labelid : STRING );
+END c06s03b00x00p08n01i00996ent;
+
+ARCHITECTURE c06s03b00x00p08n01i00996arch OF c06s03b00x00p08n01i00996ent IS
+--  This entity behavior checks the values of attributes referenced at the configuration.
+BEGIN
+  PROCESS
+  BEGIN
+    ASSERT p_scl1 =      TRUE 
+      REPORT "ERROR: Wrong value for " & labelid & "'atr_scl1" SEVERITY FAILURE;
+    ASSERT p_scl2 =       '0' 
+      REPORT "ERROR: Wrong value for " & labelid & "'atr_scl2" SEVERITY FAILURE;
+    ASSERT p_scl3 =       'z' 
+      REPORT "ERROR: Wrong value for " & labelid & "'atr_scl3" SEVERITY FAILURE;
+    ASSERT p_scl4 =         0 
+      REPORT "ERROR: Wrong value for " & labelid & "'atr_scl4" SEVERITY FAILURE;
+    ASSERT p_scl5 =      10.0 
+      REPORT "ERROR: Wrong value for " & labelid & "'atr_scl5" SEVERITY FAILURE;
+    ASSERT p_scl6 =     10 ns 
+      REPORT "ERROR: Wrong value for " & labelid & "'atr_scl6" SEVERITY FAILURE;
+    ASSERT p_scl7 =  10000 pf 
+      REPORT "ERROR: Wrong value for " & labelid & "'atr_scl7" SEVERITY FAILURE;
+    ASSERT p_scl8 =        FX 
+      REPORT "ERROR: Wrong value for " & labelid & "'atr_scl8" SEVERITY FAILURE;
+    ASSERT p_str1 =  "signal" 
+      REPORT "ERROR: Wrong value for " & labelid & "'atr_str1" SEVERITY FAILURE;
+    ASSERT p_str2 =    "XXXX" 
+      REPORT "ERROR: Wrong value for " & labelid & "'atr_str2" SEVERITY FAILURE;
+    
+    assert NOT( p_scl1 =      TRUE 
+                and p_scl2 =       '0' 
+                and p_scl3 =       'z' 
+                and p_scl4 =         0 
+                and p_scl5 =      10.0 
+                and p_scl6 =     10 ns 
+                and p_scl7 =  10000 pf 
+                and p_scl8 =        FX 
+                and p_str1 =  "signal" 
+                and p_str2 =    "XXXX") 
+      report "***PASSED TEST: c06s03b00x00p08n01i00996"
+      severity NOTE;
+    assert    ( p_scl1 =      TRUE 
+                and p_scl2 =       '0' 
+                and p_scl3 =       'z' 
+                and p_scl4 =         0 
+                and p_scl5 =      10.0 
+                and p_scl6 =     10 ns 
+                and p_scl7 =  10000 pf 
+                and p_scl8 =        FX 
+                and p_str1 =  "signal" 
+                and p_str2 =    "XXXX") 
+      report "***FAILED TEST: c06s03b00x00p08n01i00996 - Expanded name denotes a primary unit contained in design library test failed."
+      severity ERROR;
+    wait;
+  END PROCESS;
+END;
+
+
+USE WORK.c06s03b00x00p08n01i00996pkg.all;
+ENTITY c06s03b00x00p08n01i00996ent_a IS
+END c06s03b00x00p08n01i00996ent_a;
+
+ARCHITECTURE c06s03b00x00p08n01i00996arch OF c06s03b00x00p08n01i00996ent IS
+--
+  COMPONENT c06s03b00x00p08n01i00996ent_a
+  END COMPONENT;
+  
+BEGIN
+  check  : c06s03b00x00p08n01i00996ent_a;
+END c06s03b00x00p08n01i00996arch;
+
+USE WORK.c06s03b00x00p08n01i00996pkg.all;
+CONFIGURATION c06s03b00x00p08n01i00996cfg OF c06s03b00x00p08n01i00996ent IS
+  ATTRIBUTE atr_scl1 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS      TRUE;
+  ATTRIBUTE atr_scl2 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS       '0';
+  ATTRIBUTE atr_scl3 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS       'z';
+  ATTRIBUTE atr_scl4 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS         0;
+  ATTRIBUTE atr_scl5 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS      10.0;
+  ATTRIBUTE atr_scl6 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS     10 ns;
+  ATTRIBUTE atr_scl7 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS  10000 pf;
+  ATTRIBUTE atr_scl8 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS        FX;
+  ATTRIBUTE atr_str1 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS  "signal";
+  ATTRIBUTE atr_str2 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS    "XXXX";
+  
+  FOR c06s03b00x00p08n01i00996arch
+    FOR check : c06s03b00x00p08n01i00996ent_a  USE ENTITY WORK.c06s03b00x00p08n01i00996ent_a(c06s03b00x00p08n01i00996arch_a)
+                                                 GENERIC MAP (
+                                                   c06s03b00x00p08n01i00996cfg'atr_scl1,
+                                                   c06s03b00x00p08n01i00996cfg'atr_scl2,
+                                                   c06s03b00x00p08n01i00996cfg'atr_scl3,
+                                                   c06s03b00x00p08n01i00996cfg'atr_scl4,
+                                                   c06s03b00x00p08n01i00996cfg'atr_scl5,
+                                                   c06s03b00x00p08n01i00996cfg'atr_scl6,
+                                                   c06s03b00x00p08n01i00996cfg'atr_scl7,
+                                                   c06s03b00x00p08n01i00996cfg'atr_scl8,
+                                                   c06s03b00x00p08n01i00996cfg'atr_str1,
+                                                   c06s03b00x00p08n01i00996cfg'atr_str2,
+                                                   "work.c06s03b00x00p08n01i00996cfg" );
+    END FOR;
+  END FOR;
+END c06s03b00x00p08n01i00996cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/non_compliant.exp b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/non_compliant.exp
new file mode 100644
index 0000000..048709c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/non_compliant.exp
@@ -0,0 +1,1571 @@
+
+# Copyright (C) 2001 Clifton Labs, Inc
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  
+
+# Please email any bugs, comments, and/or additions to this file to:
+# vests@cliftonlabs.com
+
+# Authors: Philip A. Wilsey	philip.wilsey@ieee.org
+# 	   Dale E. Martin	dmartin@cliftonlabs.com
+
+# $Author: paw $
+# $Revision: 1.2 $
+
+# ------------------------------------------------------------------------
+#
+# $Id: non_compliant.exp,v 1.2 2001-10-19 23:29:32 paw Exp $
+#
+# ------------------------------------------------------------------------
+
+setup_test_group "Billowitch:Non-compliant Cases:Analyzer Failure" "1076-1993"
+
+run_non_compliant_test tc2.vhd
+run_non_compliant_test tc3.vhd
+run_non_compliant_test tc4.vhd
+run_non_compliant_test tc5.vhd
+run_non_compliant_test tc6.vhd
+run_non_compliant_test tc7.vhd
+run_non_compliant_test tc8.vhd
+run_non_compliant_test tc9.vhd
+
+run_non_compliant_test tc11.vhd
+run_non_compliant_test tc12.vhd
+run_non_compliant_test tc13.vhd
+run_non_compliant_test tc19.vhd
+run_non_compliant_test tc20.vhd
+run_non_compliant_test tc21.vhd
+run_non_compliant_test tc22.vhd
+run_non_compliant_test tc28.vhd
+run_non_compliant_test tc34.vhd
+run_non_compliant_test tc42.vhd
+run_non_compliant_test tc44.vhd
+run_non_compliant_test tc46.vhd
+run_non_compliant_test tc47.vhd
+run_non_compliant_test tc48.vhd
+run_non_compliant_test tc49.vhd
+run_non_compliant_test tc50.vhd
+run_non_compliant_test tc51.vhd
+run_non_compliant_test tc55.vhd
+run_non_compliant_test tc57.vhd
+run_non_compliant_test tc58.vhd
+run_non_compliant_test tc60.vhd
+run_non_compliant_test tc61.vhd
+run_non_compliant_test tc62.vhd
+run_non_compliant_test tc65.vhd
+run_non_compliant_test tc67.vhd
+run_non_compliant_test tc71.vhd
+run_non_compliant_test tc72.vhd
+run_non_compliant_test tc73.vhd
+run_non_compliant_test tc74.vhd
+run_non_compliant_test tc75.vhd
+run_non_compliant_test tc79.vhd
+run_non_compliant_test tc85.vhd
+run_non_compliant_test tc89.vhd
+run_non_compliant_test tc92.vhd
+run_non_compliant_test tc93.vhd
+run_non_compliant_test tc94.vhd
+run_non_compliant_test tc95.vhd
+run_non_compliant_test tc96.vhd
+run_non_compliant_test tc97.vhd
+
+run_non_compliant_test tc101.vhd
+run_non_compliant_test tc102.vhd
+run_non_compliant_test tc103.vhd
+run_non_compliant_test tc104.vhd
+run_non_compliant_test tc105.vhd
+run_non_compliant_test tc106.vhd
+run_non_compliant_test tc107.vhd
+run_non_compliant_test tc108.vhd
+run_non_compliant_test tc109.vhd
+run_non_compliant_test tc112.vhd
+run_non_compliant_test tc120.vhd
+run_non_compliant_test tc121.vhd
+run_non_compliant_test tc122.vhd
+run_non_compliant_test tc123.vhd
+run_non_compliant_test tc124.vhd
+run_non_compliant_test tc125.vhd
+run_non_compliant_test tc126.vhd
+run_non_compliant_test tc127.vhd
+run_non_compliant_test tc128.vhd
+run_non_compliant_test tc129.vhd
+run_non_compliant_test tc130.vhd
+run_non_compliant_test tc132.vhd
+run_non_compliant_test tc139.vhd
+run_non_compliant_test tc140.vhd
+run_non_compliant_test tc142.vhd
+run_non_compliant_test tc144.vhd
+run_non_compliant_test tc145.vhd
+run_non_compliant_test tc151.vhd
+run_non_compliant_test tc152.vhd
+run_non_compliant_test tc153.vhd
+run_non_compliant_test tc155.vhd
+run_non_compliant_test tc156.vhd
+run_non_compliant_test tc159.vhd
+run_non_compliant_test tc160.vhd
+run_non_compliant_test tc161.vhd
+run_non_compliant_test tc165.vhd
+run_non_compliant_test tc170.vhd
+run_non_compliant_test tc174.vhd
+run_non_compliant_test tc175.vhd
+run_non_compliant_test tc177.vhd
+run_non_compliant_test tc178.vhd
+run_non_compliant_test tc181.vhd
+run_non_compliant_test tc184.vhd
+run_non_compliant_test tc185.vhd
+run_non_compliant_test tc186.vhd
+run_non_compliant_test tc189.vhd
+run_non_compliant_test tc190.vhd
+run_non_compliant_test tc191.vhd
+run_non_compliant_test tc192.vhd
+run_non_compliant_test tc193.vhd
+run_non_compliant_test tc195.vhd
+run_non_compliant_test tc196.vhd
+run_non_compliant_test tc197.vhd
+run_non_compliant_test tc199.vhd
+run_non_compliant_test tc200.vhd
+run_non_compliant_test tc202.vhd
+run_non_compliant_test tc207.vhd
+run_non_compliant_test tc210.vhd
+run_non_compliant_test tc212.vhd
+run_non_compliant_test tc214.vhd
+run_non_compliant_test tc215.vhd
+run_non_compliant_test tc216.vhd
+run_non_compliant_test tc221.vhd
+run_non_compliant_test tc222.vhd
+run_non_compliant_test tc223.vhd
+run_non_compliant_test tc224.vhd
+run_non_compliant_test tc225.vhd
+run_non_compliant_test tc226.vhd
+run_non_compliant_test tc227.vhd
+run_non_compliant_test tc231.vhd
+run_non_compliant_test tc235.vhd
+run_non_compliant_test tc236.vhd
+run_non_compliant_test tc240.vhd
+run_non_compliant_test tc242.vhd
+run_non_compliant_test tc243.vhd
+run_non_compliant_test tc244.vhd
+run_non_compliant_test tc245.vhd
+run_non_compliant_test tc246.vhd
+run_non_compliant_test tc247.vhd
+run_non_compliant_test tc248.vhd
+run_non_compliant_test tc249.vhd
+run_non_compliant_test tc250.vhd
+run_non_compliant_test tc252.vhd
+run_non_compliant_test tc253.vhd
+run_non_compliant_test tc256.vhd
+run_non_compliant_test tc257.vhd
+run_non_compliant_test tc266.vhd
+run_non_compliant_test tc267.vhd
+run_non_compliant_test tc268.vhd
+run_non_compliant_test tc269.vhd
+run_non_compliant_test tc270.vhd
+run_non_compliant_test tc271.vhd
+run_non_compliant_test tc273.vhd
+run_non_compliant_test tc274.vhd
+run_non_compliant_test tc275.vhd
+run_non_compliant_test tc280.vhd
+run_non_compliant_test tc282.vhd
+run_non_compliant_test tc283.vhd
+run_non_compliant_test tc289.vhd
+run_non_compliant_test tc296.vhd
+run_non_compliant_test tc300.vhd
+run_non_compliant_test tc302.vhd
+run_non_compliant_test tc303.vhd
+run_non_compliant_test tc304.vhd
+run_non_compliant_test tc305.vhd
+run_non_compliant_test tc306.vhd
+run_non_compliant_test tc307.vhd
+run_non_compliant_test tc310.vhd
+run_non_compliant_test tc315.vhd
+run_non_compliant_test tc316.vhd
+run_non_compliant_test tc321.vhd
+run_non_compliant_test tc324.vhd
+run_non_compliant_test tc325.vhd
+run_non_compliant_test tc327.vhd
+run_non_compliant_test tc328.vhd
+run_non_compliant_test tc329.vhd
+run_non_compliant_test tc330.vhd
+run_non_compliant_test tc331.vhd
+run_non_compliant_test tc332.vhd
+run_non_compliant_test tc336.vhd
+run_non_compliant_test tc338.vhd
+run_non_compliant_test tc340.vhd
+run_non_compliant_test tc342.vhd
+run_non_compliant_test tc345.vhd
+run_non_compliant_test tc348.vhd
+run_non_compliant_test tc352.vhd
+run_non_compliant_test tc353.vhd
+run_non_compliant_test tc354.vhd
+run_non_compliant_test tc356.vhd
+run_non_compliant_test tc357.vhd
+run_non_compliant_test tc358.vhd
+run_non_compliant_test tc360.vhd
+run_non_compliant_test tc362.vhd
+run_non_compliant_test tc363.vhd
+run_non_compliant_test tc367.vhd
+run_non_compliant_test tc368.vhd
+run_non_compliant_test tc369.vhd
+run_non_compliant_test tc370.vhd
+run_non_compliant_test tc371.vhd
+run_non_compliant_test tc372.vhd
+run_non_compliant_test tc373.vhd
+run_non_compliant_test tc374.vhd
+run_non_compliant_test tc375.vhd
+run_non_compliant_test tc379.vhd
+run_non_compliant_test tc380.vhd
+run_non_compliant_test tc383.vhd
+run_non_compliant_test tc384.vhd
+run_non_compliant_test tc389.vhd
+run_non_compliant_test tc390.vhd
+run_non_compliant_test tc391.vhd
+run_non_compliant_test tc394.vhd
+run_non_compliant_test tc396.vhd
+run_non_compliant_test tc405.vhd
+run_non_compliant_test tc502.vhd
+run_non_compliant_test tc504.vhd
+run_non_compliant_test tc506.vhd
+run_non_compliant_test tc507.vhd
+run_non_compliant_test tc508.vhd
+run_non_compliant_test tc509.vhd
+run_non_compliant_test tc510.vhd
+run_non_compliant_test tc511.vhd
+run_non_compliant_test tc514.vhd
+run_non_compliant_test tc518.vhd
+run_non_compliant_test tc532.vhd
+run_non_compliant_test tc533.vhd
+run_non_compliant_test tc540.vhd
+run_non_compliant_test tc543.vhd
+run_non_compliant_test tc547.vhd
+run_non_compliant_test tc548.vhd
+run_non_compliant_test tc549.vhd
+run_non_compliant_test tc550.vhd
+run_non_compliant_test tc551.vhd
+run_non_compliant_test tc552.vhd
+run_non_compliant_test tc553.vhd
+run_non_compliant_test tc714.vhd
+run_non_compliant_test tc715.vhd
+run_non_compliant_test tc716.vhd
+run_non_compliant_test tc718.vhd
+run_non_compliant_test tc720.vhd
+run_non_compliant_test tc721.vhd
+run_non_compliant_test tc722.vhd
+run_non_compliant_test tc723.vhd
+run_non_compliant_test tc724.vhd
+run_non_compliant_test tc725.vhd
+run_non_compliant_test tc726.vhd
+run_non_compliant_test tc727.vhd
+run_non_compliant_test tc728.vhd
+run_non_compliant_test tc729.vhd
+run_non_compliant_test tc730.vhd
+run_non_compliant_test tc732.vhd
+run_non_compliant_test tc733.vhd
+run_non_compliant_test tc734.vhd
+run_non_compliant_test tc735.vhd
+run_non_compliant_test tc736.vhd
+run_non_compliant_test tc738.vhd
+run_non_compliant_test tc739.vhd
+run_non_compliant_test tc764.vhd
+run_non_compliant_test tc766.vhd
+run_non_compliant_test tc767.vhd
+run_non_compliant_test tc769.vhd
+run_non_compliant_test tc770.vhd
+run_non_compliant_test tc771.vhd
+run_non_compliant_test tc773.vhd
+run_non_compliant_test tc774.vhd
+run_non_compliant_test tc775.vhd
+run_non_compliant_test tc779.vhd
+run_non_compliant_test tc780.vhd
+run_non_compliant_test tc781.vhd
+run_non_compliant_test tc783.vhd
+run_non_compliant_test tc785.vhd
+run_non_compliant_test tc786.vhd
+run_non_compliant_test tc787.vhd
+run_non_compliant_test tc788.vhd
+run_non_compliant_test tc789.vhd
+run_non_compliant_test tc790.vhd
+run_non_compliant_test tc793.vhd
+run_non_compliant_test tc794.vhd
+run_non_compliant_test tc795.vhd
+run_non_compliant_test tc796.vhd
+run_non_compliant_test tc797.vhd
+run_non_compliant_test tc798.vhd
+run_non_compliant_test tc799.vhd
+run_non_compliant_test tc800.vhd
+run_non_compliant_test tc801.vhd
+run_non_compliant_test tc802.vhd
+run_non_compliant_test tc803.vhd
+run_non_compliant_test tc804.vhd
+run_non_compliant_test tc806.vhd
+run_non_compliant_test tc807.vhd
+run_non_compliant_test tc808.vhd
+run_non_compliant_test tc809.vhd
+run_non_compliant_test tc810.vhd
+run_non_compliant_test tc811.vhd
+run_non_compliant_test tc812.vhd
+run_non_compliant_test tc813.vhd
+run_non_compliant_test tc815.vhd
+run_non_compliant_test tc818.vhd
+run_non_compliant_test tc819.vhd
+run_non_compliant_test tc821.vhd
+run_non_compliant_test tc822.vhd
+run_non_compliant_test tc823.vhd
+run_non_compliant_test tc824.vhd
+run_non_compliant_test tc825.vhd
+run_non_compliant_test tc826.vhd
+run_non_compliant_test tc827.vhd
+run_non_compliant_test tc828.vhd
+run_non_compliant_test tc829.vhd
+run_non_compliant_test tc830.vhd
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+run_non_compliant_test tc2621.vhd
+run_non_compliant_test tc2622.vhd
+run_non_compliant_test tc2623.vhd
+run_non_compliant_test tc2624.vhd
+run_non_compliant_test tc2625.vhd
+run_non_compliant_test tc2626.vhd
+run_non_compliant_test tc2627.vhd
+run_non_compliant_test tc2628.vhd
+run_non_compliant_test tc2629.vhd
+run_non_compliant_test tc2630.vhd
+run_non_compliant_test tc2631.vhd
+run_non_compliant_test tc2632.vhd
+run_non_compliant_test tc2633.vhd
+run_non_compliant_test tc2634.vhd
+run_non_compliant_test tc2635.vhd
+run_non_compliant_test tc2636.vhd
+run_non_compliant_test tc2637.vhd
+run_non_compliant_test tc2638.vhd
+run_non_compliant_test tc2639.vhd
+run_non_compliant_test tc2640.vhd
+run_non_compliant_test tc2641.vhd
+run_non_compliant_test tc2644.vhd
+run_non_compliant_test tc2645.vhd
+run_non_compliant_test tc2646.vhd
+run_non_compliant_test tc2647.vhd
+run_non_compliant_test tc2648.vhd
+run_non_compliant_test tc2649.vhd
+run_non_compliant_test tc2650.vhd
+run_non_compliant_test tc2651.vhd
+run_non_compliant_test tc2652.vhd
+run_non_compliant_test tc2653.vhd
+run_non_compliant_test tc2654.vhd
+run_non_compliant_test tc2655.vhd
+run_non_compliant_test tc2656.vhd
+run_non_compliant_test tc2657.vhd
+run_non_compliant_test tc2658.vhd
+run_non_compliant_test tc2659.vhd
+run_non_compliant_test tc2660.vhd
+run_non_compliant_test tc2661.vhd
+run_non_compliant_test tc2662.vhd
+run_non_compliant_test tc2663.vhd
+run_non_compliant_test tc2664.vhd
+run_non_compliant_test tc2665.vhd
+run_non_compliant_test tc2666.vhd
+run_non_compliant_test tc2667.vhd
+run_non_compliant_test tc2668.vhd
+run_non_compliant_test tc2669.vhd
+run_non_compliant_test tc2670.vhd
+run_non_compliant_test tc2671.vhd
+run_non_compliant_test tc2672.vhd
+run_non_compliant_test tc2673.vhd
+run_non_compliant_test tc2674.vhd
+run_non_compliant_test tc2678.vhd
+run_non_compliant_test tc2680.vhd
+run_non_compliant_test tc2681.vhd
+run_non_compliant_test tc2682.vhd
+run_non_compliant_test tc2683.vhd
+run_non_compliant_test tc2684.vhd
+run_non_compliant_test tc2685.vhd
+run_non_compliant_test tc2686.vhd
+run_non_compliant_test tc2687.vhd
+run_non_compliant_test tc2688.vhd
+run_non_compliant_test tc2689.vhd
+run_non_compliant_test tc2691.vhd
+run_non_compliant_test tc2692.vhd
+run_non_compliant_test tc2693.vhd
+run_non_compliant_test tc2694.vhd
+run_non_compliant_test tc2695.vhd
+run_non_compliant_test tc2696.vhd
+run_non_compliant_test tc2706.vhd
+run_non_compliant_test tc2714.vhd
+run_non_compliant_test tc2715.vhd
+run_non_compliant_test tc2716.vhd
+run_non_compliant_test tc2717.vhd
+run_non_compliant_test tc2720.vhd
+run_non_compliant_test tc2721.vhd
+run_non_compliant_test tc2723.vhd
+run_non_compliant_test tc2727.vhd
+run_non_compliant_test tc2728.vhd
+run_non_compliant_test tc2729.vhd
+run_non_compliant_test tc2730.vhd
+run_non_compliant_test tc2731.vhd
+run_non_compliant_test tc2732.vhd
+run_non_compliant_test tc2741.vhd
+run_non_compliant_test tc2746.vhd
+run_non_compliant_test tc2748.vhd
+run_non_compliant_test tc2749.vhd
+run_non_compliant_test tc2750.vhd
+run_non_compliant_test tc2751.vhd
+run_non_compliant_test tc2752.vhd
+run_non_compliant_test tc2753.vhd
+run_non_compliant_test tc2754.vhd
+run_non_compliant_test tc2755.vhd
+run_non_compliant_test tc2756.vhd
+run_non_compliant_test tc2757.vhd
+run_non_compliant_test tc2762.vhd
+run_non_compliant_test tc2763.vhd
+run_non_compliant_test tc2764.vhd
+run_non_compliant_test tc2766.vhd
+run_non_compliant_test tc2770.vhd
+run_non_compliant_test tc2772.vhd
+run_non_compliant_test tc2773.vhd
+run_non_compliant_test tc2774.vhd
+run_non_compliant_test tc2775.vhd
+run_non_compliant_test tc2776.vhd
+run_non_compliant_test tc2777.vhd
+run_non_compliant_test tc2778.vhd
+run_non_compliant_test tc2779.vhd
+run_non_compliant_test tc2780.vhd
+run_non_compliant_test tc2781.vhd
+run_non_compliant_test tc2782.vhd
+run_non_compliant_test tc2783.vhd
+run_non_compliant_test tc2784.vhd
+run_non_compliant_test tc2785.vhd
+run_non_compliant_test tc2786.vhd
+run_non_compliant_test tc2787.vhd
+run_non_compliant_test tc2788.vhd
+run_non_compliant_test tc2789.vhd
+run_non_compliant_test tc2790.vhd
+run_non_compliant_test tc2791.vhd
+run_non_compliant_test tc2792.vhd
+run_non_compliant_test tc2793.vhd
+run_non_compliant_test tc2794.vhd
+run_non_compliant_test tc2795.vhd
+run_non_compliant_test tc2796.vhd
+run_non_compliant_test tc2797.vhd
+run_non_compliant_test tc2798.vhd
+run_non_compliant_test tc2799.vhd
+run_non_compliant_test tc2800.vhd
+run_non_compliant_test tc2801.vhd
+run_non_compliant_test tc2802.vhd
+run_non_compliant_test tc2803.vhd
+run_non_compliant_test tc2804.vhd
+run_non_compliant_test tc2805.vhd
+run_non_compliant_test tc2806.vhd
+run_non_compliant_test tc2807.vhd
+run_non_compliant_test tc2808.vhd
+run_non_compliant_test tc2809.vhd
+run_non_compliant_test tc2810.vhd
+run_non_compliant_test tc2811.vhd
+run_non_compliant_test tc2812.vhd
+run_non_compliant_test tc2813.vhd
+run_non_compliant_test tc2814.vhd
+run_non_compliant_test tc2815.vhd
+run_non_compliant_test tc2816.vhd
+run_non_compliant_test tc2817.vhd
+run_non_compliant_test tc2818.vhd
+run_non_compliant_test tc2819.vhd
+run_non_compliant_test tc2820.vhd
+run_non_compliant_test tc2821.vhd
+run_non_compliant_test tc2822.vhd
+run_non_compliant_test tc2823.vhd
+run_non_compliant_test tc2824.vhd
+run_non_compliant_test tc2825.vhd
+run_non_compliant_test tc2826.vhd
+run_non_compliant_test tc2827.vhd
+run_non_compliant_test tc2828.vhd
+run_non_compliant_test tc2829.vhd
+run_non_compliant_test tc2830.vhd
+run_non_compliant_test tc2831.vhd
+run_non_compliant_test tc2832.vhd
+run_non_compliant_test tc2833.vhd
+run_non_compliant_test tc2834.vhd
+run_non_compliant_test tc2835.vhd
+run_non_compliant_test tc2836.vhd
+run_non_compliant_test tc2837.vhd
+run_non_compliant_test tc2838.vhd
+run_non_compliant_test tc2839.vhd
+run_non_compliant_test tc2840.vhd
+run_non_compliant_test tc2841.vhd
+run_non_compliant_test tc2842.vhd
+run_non_compliant_test tc2843.vhd
+run_non_compliant_test tc2844.vhd
+run_non_compliant_test tc2845.vhd
+run_non_compliant_test tc2846.vhd
+run_non_compliant_test tc2847.vhd
+run_non_compliant_test tc2848.vhd
+run_non_compliant_test tc2849.vhd
+run_non_compliant_test tc2850.vhd
+run_non_compliant_test tc2851.vhd
+run_non_compliant_test tc2852.vhd
+run_non_compliant_test tc2855.vhd
+run_non_compliant_test tc2856.vhd
+run_non_compliant_test tc2857.vhd
+run_non_compliant_test tc2858.vhd
+run_non_compliant_test tc2859.vhd
+run_non_compliant_test tc2867.vhd
+run_non_compliant_test tc2869.vhd
+run_non_compliant_test tc2871.vhd
+run_non_compliant_test tc2872.vhd
+run_non_compliant_test tc2873.vhd
+run_non_compliant_test tc2875.vhd
+run_non_compliant_test tc2877.vhd
+run_non_compliant_test tc2878.vhd
+run_non_compliant_test tc2884.vhd
+run_non_compliant_test tc2885.vhd
+run_non_compliant_test tc2886.vhd
+run_non_compliant_test tc2887.vhd
+run_non_compliant_test tc2888.vhd
+run_non_compliant_test tc2889.vhd
+run_non_compliant_test tc2890.vhd
+run_non_compliant_test tc2891.vhd
+run_non_compliant_test tc2892.vhd
+run_non_compliant_test tc2893.vhd
+run_non_compliant_test tc2894.vhd
+run_non_compliant_test tc2895.vhd
+run_non_compliant_test tc2896.vhd
+run_non_compliant_test tc2897.vhd
+run_non_compliant_test tc2898.vhd
+run_non_compliant_test tc2899.vhd
+run_non_compliant_test tc2905.vhd
+run_non_compliant_test tc2906.vhd
+run_non_compliant_test tc2907.vhd
+run_non_compliant_test tc2908.vhd
+run_non_compliant_test tc2909.vhd
+run_non_compliant_test tc2910.vhd
+run_non_compliant_test tc2911.vhd
+run_non_compliant_test tc2912.vhd
+run_non_compliant_test tc2913.vhd
+run_non_compliant_test tc2914.vhd
+run_non_compliant_test tc2915.vhd
+run_non_compliant_test tc2916.vhd
+run_non_compliant_test tc2919.vhd
+run_non_compliant_test tc2920.vhd
+run_non_compliant_test tc2921.vhd
+run_non_compliant_test tc2922.vhd
+run_non_compliant_test tc2923.vhd
+run_non_compliant_test tc2924.vhd
+run_non_compliant_test tc2925.vhd
+run_non_compliant_test tc2926.vhd
+run_non_compliant_test tc2927.vhd
+run_non_compliant_test tc2928.vhd
+run_non_compliant_test tc2929.vhd
+run_non_compliant_test tc2930.vhd
+run_non_compliant_test tc2931.vhd
+run_non_compliant_test tc2933.vhd
+run_non_compliant_test tc2934.vhd
+run_non_compliant_test tc2935.vhd
+run_non_compliant_test tc2936.vhd
+run_non_compliant_test tc2937.vhd
+run_non_compliant_test tc2938.vhd
+run_non_compliant_test tc2939.vhd
+run_non_compliant_test tc2940.vhd
+run_non_compliant_test tc2941.vhd
+run_non_compliant_test tc2942.vhd
+run_non_compliant_test tc2943.vhd
+run_non_compliant_test tc2944.vhd
+run_non_compliant_test tc2946.vhd
+run_non_compliant_test tc2947.vhd
+run_non_compliant_test tc2953.vhd
+run_non_compliant_test tc2954.vhd
+run_non_compliant_test tc2956.vhd
+run_non_compliant_test tc2957.vhd
+run_non_compliant_test tc2958.vhd
+run_non_compliant_test tc2963.vhd
+run_non_compliant_test tc2965.vhd
+run_non_compliant_test tc2970.vhd
+run_non_compliant_test tc2971.vhd
+run_non_compliant_test tc2983.vhd
+run_non_compliant_test tc2984.vhd
+run_non_compliant_test tc2985.vhd
+run_non_compliant_test tc2986.vhd
+run_non_compliant_test tc2991.vhd
+run_non_compliant_test tc2992.vhd
+run_non_compliant_test tc2993.vhd
+run_non_compliant_test tc2994.vhd
+run_non_compliant_test tc2995.vhd
+run_non_compliant_test tc2996.vhd
+run_non_compliant_test tc2997.vhd
+run_non_compliant_test tc2998.vhd
+run_non_compliant_test tc2999.vhd
+run_non_compliant_test tc3000.vhd
+run_non_compliant_test tc3002.vhd
+run_non_compliant_test tc3003.vhd
+run_non_compliant_test tc3004.vhd
+run_non_compliant_test tc3006.vhd
+run_non_compliant_test tc3007.vhd
+run_non_compliant_test tc3008.vhd
+run_non_compliant_test tc3009.vhd
+run_non_compliant_test tc3011.vhd
+run_non_compliant_test tc3012.vhd
+run_non_compliant_test tc3013.vhd
+run_non_compliant_test tc3014.vhd
+run_non_compliant_test tc3015.vhd
+run_non_compliant_test tc3017.vhd
+run_non_compliant_test tc3019.vhd
+run_non_compliant_test tc3020.vhd
+run_non_compliant_test tc3021.vhd
+run_non_compliant_test tc3025.vhd
+run_non_compliant_test tc3026.vhd
+run_non_compliant_test tc3027.vhd
+run_non_compliant_test tc3028.vhd
+run_non_compliant_test tc3030.vhd
+run_non_compliant_test tc3031.vhd
+run_non_compliant_test tc3058.vhd
+run_non_compliant_test tc3064.vhd
+run_non_compliant_test tc3087.vhd
+run_non_compliant_test tc3088.vhd
+run_non_compliant_test tc3089.vhd
+run_non_compliant_test tc3091.vhd
+run_non_compliant_test tc3092.vhd
+run_non_compliant_test tc3093.vhd
+run_non_compliant_test tc3094.vhd
+run_non_compliant_test tc3095.vhd
+run_non_compliant_test tc3096.vhd
+run_non_compliant_test tc3097.vhd
+run_non_compliant_test tc3098.vhd
+run_non_compliant_test tc3103.vhd
+run_non_compliant_test tc3104.vhd
+run_non_compliant_test tc3105.vhd
+run_non_compliant_test tc3106.vhd
+run_non_compliant_test tc3107.vhd
+run_non_compliant_test tc3108.vhd
+run_non_compliant_test tc3161.vhd
+run_non_compliant_test tc3207.vhd
+
+end_test_group
+
+# $Log: non_compliant.exp,v $
+# Revision 1.2  2001-10-19 23:29:32  paw
+# Adding comments for cvs tracking information.
+#
+# Revision 1.1  2001/10/15 16:00:50  paw
+# Updating the compliant.exp script to properly use the functions in the new
+# savant test harness.
+#
+# Adding the scripts for non_compliant testing in the billowitch suite.
+#
+# When properly placed in the testsuite subdirectory of savant, a make check
+# will work.  Documentation will be added to the testsuite to describe how.
+#
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1000.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1000.vhd
new file mode 100644
index 0000000..a337b72
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1000.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1000.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01000pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i01000pkg;
+
+use work.c06s03b00x00p09n01i01000pkg.all;
+ENTITY c06s03b00x00p09n01i01000ent IS
+END c06s03b00x00p09n01i01000ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01000arch OF c06s03b00x00p09n01i01000ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST4 is c06s03b00x00p09n01i01000ent.c06s03b00x00p09n01i01000pkg.TWO (1 to 1);
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i01000 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01000arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1001.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1001.vhd
new file mode 100644
index 0000000..210cb02
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1001.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1001.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01001pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i01001pkg;
+
+use work.c06s03b00x00p09n01i01001pkg.all;
+ENTITY c06s03b00x00p09n01i01001ent IS
+END c06s03b00x00p09n01i01001ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01001arch OF c06s03b00x00p09n01i01001ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST6 is c06s03b00x00p09n01i01001pkg.UNKNOWN;
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i01001 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01001arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1002.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1002.vhd
new file mode 100644
index 0000000..1386af3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1002.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1002.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01002pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i01002pkg;
+
+use work.c06s03b00x00p09n01i01002pkg.all;
+ENTITY c06s03b00x00p09n01i01002ent IS
+END c06s03b00x00p09n01i01002ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01002arch OF c06s03b00x00p09n01i01002ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST7 is Q.TWO (1 to 1);
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i01002 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01002arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1003.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1003.vhd
new file mode 100644
index 0000000..922f9ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1003.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1003.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01003pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i01003pkg;
+
+use work.c06s03b00x00p09n01i01003pkg.all;
+ENTITY c06s03b00x00p09n01i01003ent IS
+END c06s03b00x00p09n01i01003ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01003arch OF c06s03b00x00p09n01i01003ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST8 is E.TWO (1 to 1);
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i01003 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01003arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1004.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1004.vhd
new file mode 100644
index 0000000..bbd0dc8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1004.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1004.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01004pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i01004pkg;
+
+use work.c06s03b00x00p09n01i01004pkg.all;
+ENTITY c06s03b00x00p09n01i01004ent IS
+END c06s03b00x00p09n01i01004ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01004arch OF c06s03b00x00p09n01i01004ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST8 is E.TWO (1 to 1);
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i01004 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01004arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1005.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1005.vhd
new file mode 100644
index 0000000..4e05208
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1005.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1005.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01005pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i01005pkg;
+
+use work.c06s03b00x00p09n01i01005pkg.all;
+ENTITY c06s03b00x00p09n01i01005ent IS
+END c06s03b00x00p09n01i01005ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01005arch OF c06s03b00x00p09n01i01005ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST10 is E.c06s03b00x00p09n01i01005pkg.TWO (1 to 1);
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i01005 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01005arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1006.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1006.vhd
new file mode 100644
index 0000000..e4464f5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1006.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1006.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01006pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i01006pkg;
+
+use work.c06s03b00x00p09n01i01006pkg.all;
+ENTITY c06s03b00x00p09n01i01006ent IS
+END c06s03b00x00p09n01i01006ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01006arch OF c06s03b00x00p09n01i01006ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST12 is E.c06s03b00x00p09n01i01006ent.FOUR (1 to 1);
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i01006 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01006arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1007.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1007.vhd
new file mode 100644
index 0000000..7c586ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1007.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1007.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01007pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i01007pkg;
+
+use work.c06s03b00x00p09n01i01007pkg.all;
+ENTITY c06s03b00x00p09n01i01007ent IS
+END c06s03b00x00p09n01i01007ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01007arch OF c06s03b00x00p09n01i01007ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST13 is c06s03b00x00p09n01i01007ent.E.FOUR (1 to 1);
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i01007 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01007arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1008.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1008.vhd
new file mode 100644
index 0000000..7a86128
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1008.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1008.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i01008pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i01008pkg;
+
+use work.ch0603_p00901_12_pkg.all;
+ENTITY c06s03b00x00p09n01i01008ent IS
+END c06s03b00x00p09n01i01008ent;
+
+ARCHITECTURE c06s03b00x00p09n01i01008arch OF c06s03b00x00p09n01i01008ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST14 is c06s03b00x00p09n01i01008pkg.NOTKNOWN;
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i01008 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i01008arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc101.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc101.vhd
new file mode 100644
index 0000000..4dba7fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc101.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc101.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00101ent IS
+  port ( signal S : out bit) ;
+END c04s03b02x00p29n06i00101ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00101arch OF c04s03b02x00p29n06i00101ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant T : TIME := 10 ns;
+  BEGIN
+    if S'STABLE(T) then  -- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p29n06i00101 - The attribute STABLE of a signal of mode out cannot be read." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00101arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1014.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1014.vhd
new file mode 100644
index 0000000..aa345b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1014.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1014.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01014ent IS
+END c06s03b00x00p10n01i01014ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01014arch OF c06s03b00x00p10n01i01014ent IS
+  signal p : bit := '0';
+  signal q : bit := '1';
+BEGIN
+  TESTING: PROCESS(c06s03b00x00p10n01i01014arch.p,c06s03b00x00p10n01i01014ent.q)
+  BEGIN
+    c06s03b00x00p10n01i01014ent.q <= c06s03b00x00p10n01i01014arch.p;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p10n01i01014 - Declaration of suffix must occur within the construct denoted by the prefix."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01014arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1015.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1015.vhd
new file mode 100644
index 0000000..6b5c4d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1015.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1015.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01015ent IS
+  port (p : in bit);
+END c06s03b00x00p10n01i01015ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01015arch OF c06s03b00x00p10n01i01015ent IS
+  signal G : integer;
+BEGIN
+  C:block
+  begin
+    TESTING: PROCESS
+      variable F : integer;
+    BEGIN
+      F :=  F + D.G;    -- ERROR: prefix must denote a block statement,
+      -- a process statement, or a loop statement.
+      null ;
+      assert FALSE 
+        report "***FAILED TEST: c06s03b00x00p10n01i01015 - Prefix must denote a block, process or loop statement." 
+        severity NOTE;
+    END PROCESS TESTING;
+  end block C;
+
+END c06s03b00x00p10n01i01015_arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1016.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1016.vhd
new file mode 100644
index 0000000..5ff30fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1016.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1016.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01016ent IS
+  port (p : in bit);
+END c06s03b00x00p10n01i01016ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01016arch OF c06s03b00x00p10n01i01016ent IS
+  signal G : integer;
+BEGIN
+  TESTING: PROCESS
+    variable F : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p10n01i01016 - Prefix must denote a block, process or loop statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  H: if TRUE generate
+    G <= G + H.F;       -- ERROR: declaration of suffix should be
+    -- within the construct denoted by the prefix.
+  end generate H;
+
+END c06s03b00x00p10n01i01016arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1017.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1017.vhd
new file mode 100644
index 0000000..56ba3b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1017.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1017.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01017ent IS
+  port (p : in bit);
+END c06s03b00x00p10n01i01017ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01017arch OF c06s03b00x00p10n01i01017ent IS
+
+BEGIN
+  b1 : block
+    type chars is ('a','b','c');
+    signal bs1 : BIT;
+  begin
+    B2: block
+      type chars is ('c','d','e');
+      signal bs2 : BIT;
+    begin
+      process
+        variable c : b1.chars;
+        variable d : b2.chars;
+      begin
+        d := b2.'a';
+                                        -- ERROR: Literal defined by selected
+                                        -- suffix not declared within construct
+                                        -- denoted by selected prefix.
+      end process;
+    end block B2;
+  end block b1;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p10n01i01017 - Entity declaration does not occur in construct specifed by the prefix." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01017arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1018.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1018.vhd
new file mode 100644
index 0000000..9fecabf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1018.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1018.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n01i01018ent IS
+  port (p : in bit);
+END c06s03b00x00p10n01i01018ent;
+
+ARCHITECTURE c06s03b00x00p10n01i01018arch OF c06s03b00x00p10n01i01018ent IS
+
+BEGIN
+  b1 : block
+    type chars is ('a','b','c');
+    signal bs1 : BIT;
+  begin
+    B2: block
+      signal bs2 : BIT;
+    begin
+      process
+      begin
+        NULL;
+      end process;
+      b3 : block
+        signal bs3a : BIT;
+        signal bs3b : BIT;
+      begin
+        bs3b <= B1.bs2;
+                                        -- ERROR: Entity defined by selected
+                                        -- suffix not declared within construct
+                                        -- denoted by selected prefix.
+      end block b3;
+    end block B2;
+  end block b1;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p10n01i01018 - Entity declaration does not occur in construct specifed by the prefix." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n01i01018arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc102.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc102.vhd
new file mode 100644
index 0000000..f31af87
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc102.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc102.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00102ent IS
+  port ( signal S : out bit) ;
+END c04s03b02x00p29n06i00102ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00102arch OF c04s03b02x00p29n06i00102ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant T : TIME := 10 ns;
+  BEGIN
+    if S'QUIET(T) then  -- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p29n06i00102- The attribute QUIET of a signal of mode out cannot be read." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00102arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1022.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1022.vhd
new file mode 100644
index 0000000..15d39db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1022.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1022.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p10n02i01022pkg is
+  procedure check (x: in integer; y: in boolean);
+end c06s03b00x00p10n02i01022pkg;
+
+use work.c06s03b00x00p10n02i01022pkg.all;
+ENTITY c06s03b00x00p10n02i01022ent IS
+END c06s03b00x00p10n02i01022ent;
+
+ARCHITECTURE c06s03b00x00p10n02i01022arch OF c06s03b00x00p10n02i01022ent IS
+  constant p: integer := 3;
+  constant q: boolean := true;
+BEGIN
+  TESTING: PROCESS
+    variable p: integer;
+    variable q: boolean;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p10n02i01022 - An expanded name is used outside the named construct."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+  check (TESTING.p, TESTING.q);     -- Failure_here
+
+END c06s03b00x00p10n02i01022arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1023.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1023.vhd
new file mode 100644
index 0000000..1b83b19
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1023.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1023.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n02i01023ent IS
+END c06s03b00x00p10n02i01023ent;
+
+ARCHITECTURE c06s03b00x00p10n02i01023arch OF c06s03b00x00p10n02i01023ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable j : integer;
+  BEGIN
+    L1: for i in 1 to 10 loop
+      e.j := L1.i;
+    end loop;
+    j := L1.i; -- illegal as reference to L1.i is allowed within the
+    -- loop L1 only.
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p10n02i01023 - An expanded name denoting an entity declared within a named construct is allowed only within the construct." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n02i01023arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1025.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1025.vhd
new file mode 100644
index 0000000..5fb5c2e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1025.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1025.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p10n02i01025ent IS
+END c06s03b00x00p10n02i01025ent;
+
+ARCHITECTURE c06s03b00x00p10n02i01025arch OF c06s03b00x00p10n02i01025ent IS
+
+BEGIN
+  B1 : block
+    constant C : integer := 10;
+  begin
+    B2 : block
+      constant C : integer := B1.c; -- Ok
+    begin
+      process
+      begin
+        null;
+      end process;
+    end block;
+    B3 : block
+      constant C : integer := B1.c; -- Ok
+      constant Bad_C : integer := B2.c;
+      -- Error : Initialization Expression is not visible.
+    begin
+      process
+      begin
+        null;
+      end process;
+    end block;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p10n02i01025 - Expanded name visible only in the construct." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p10n02i01025arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc103.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc103.vhd
new file mode 100644
index 0000000..ef90066
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc103.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc103.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00103ent IS
+  port ( signal S : out bit) ;
+END c04s03b02x00p29n06i00103ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00103arch OF c04s03b02x00p29n06i00103ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant T : TIME := 10 ns;
+  BEGIN
+    if (S'DELAYED(T)='1') then  -- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p29n06i00103- The attribute DELAYED of a signal of mode out cannot be read." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00103arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1036.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1036.vhd
new file mode 100644
index 0000000..e35c008
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1036.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1036.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p02n01i01036ent IS
+END c06s04b00x00p02n01i01036ent;
+
+ARCHITECTURE c06s04b00x00p02n01i01036arch OF c06s04b00x00p02n01i01036ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     T2 is array (0 to 31) of BIT;
+    variable V1 : T2 ;
+  BEGIN
+    V1(2 := '1' ;  -- Failure_here
+       assert FALSE 
+       report "***FAILED TEST: c06s04b00x00p02n01i01036 - Missing parentheses." 
+       severity ERROR;
+       wait;
+       END PROCESS TESTING;
+
+       END c06s04b00x00p02n01i01036arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc104.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc104.vhd
new file mode 100644
index 0000000..ce4160b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc104.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc104.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00104ent IS
+  port ( signal S : out bit) ;
+END c04s03b02x00p29n06i00104ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00104arch OF c04s03b02x00p29n06i00104ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if (S'EVENT) then  -- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p29n06i00104 - The attribute EVENT of a signal of mode out cannot be read." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00104arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1041.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1041.vhd
new file mode 100644
index 0000000..1d93af7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1041.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1041.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01041ent IS
+END c06s04b00x00p03n01i01041ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01041arch OF c06s04b00x00p03n01i01041ent IS
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if k(1) = 1 then
+      NULL;
+    end if; 
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n01i01041 - Prefix of an indexed name can only denote an array type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01041arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1042.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1042.vhd
new file mode 100644
index 0000000..c7cc02f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1042.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1042.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01042ent IS
+END c06s04b00x00p03n01i01042ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01042arch OF c06s04b00x00p03n01i01042ent IS
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type A1 is array (THREE) of BOOLEAN;
+    type ONE is range 1 to 1;
+    type A2 is array (ONE) of BOOLEAN;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := (1=>TRUE, 2=>TRUE, 3=>TRUE)(2);
+    -- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n01i01042 - Prefix of an indexed name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01042arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1043.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1043.vhd
new file mode 100644
index 0000000..62197b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1043.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1043.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01043ent IS
+END c06s04b00x00p03n01i01043ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01043arch OF c06s04b00x00p03n01i01043ent IS
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type A1 is array (THREE) of BOOLEAN;
+    type ONE is range 1 to 1;
+    type A2 is array (ONE) of BOOLEAN;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := (others=>TRUE)(2);
+    -- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n01i01043 - Prefix of an indexed name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01043arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1044.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1044.vhd
new file mode 100644
index 0000000..ff9306b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1044.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1044.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01044ent IS
+END c06s04b00x00p03n01i01044ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01044arch OF c06s04b00x00p03n01i01044ent IS
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type A1 is array (THREE) of BOOLEAN;
+    type ONE is range 1 to 1;
+    type A2 is array (ONE) of BOOLEAN;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := A1'(1=>TRUE, 2=>TRUE, 3=>TRUE)(2);
+    -- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n01i01044 - Prefix of an indexed name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01044arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1045.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1045.vhd
new file mode 100644
index 0000000..88c72cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1045.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1045.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01045ent IS
+END c06s04b00x00p03n01i01045ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01045arch OF c06s04b00x00p03n01i01045ent IS
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type A1 is array (THREE) of BOOLEAN;
+    type ONE is range 1 to 1;
+    type A2 is array (ONE) of BOOLEAN;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := A1'(others=>TRUE)(2);
+    -- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n01i01045 - Prefix of an indexed name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01045arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1046.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1046.vhd
new file mode 100644
index 0000000..1174e69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1046.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1046.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01046ent IS
+END c06s04b00x00p03n01i01046ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01046arch OF c06s04b00x00p03n01i01046ent IS
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type A1 is array (THREE) of BOOLEAN;
+    type ONE is range 1 to 1;
+    type A2 is array (ONE) of BOOLEAN;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := A1'(others=>TRUE)(2);
+    -- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n01i01046 - Prefix of an indexed name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01046arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1047.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1047.vhd
new file mode 100644
index 0000000..db47347
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1047.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1047.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01047ent IS
+END c06s04b00x00p03n01i01047ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01047arch OF c06s04b00x00p03n01i01047ent IS
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type A1 is array (THREE) of BOOLEAN;
+    type ONE is range 1 to 1;
+    type A2 is array (ONE) of BOOLEAN;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := (others=>TRUE)(1);
+    -- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n01i01047 - Prefix of an indexed name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01047arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1048.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1048.vhd
new file mode 100644
index 0000000..4ad980d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1048.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1048.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01048ent IS
+END c06s04b00x00p03n01i01048ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01048arch OF c06s04b00x00p03n01i01048ent IS
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type A1 is array (THREE) of BOOLEAN;
+    type ONE is range 1 to 1;
+    type A2 is array (ONE) of BOOLEAN;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := A2'(1=>TRUE)(1);
+    -- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n01i01048 - Prefix of an indexed name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01048arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1049.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1049.vhd
new file mode 100644
index 0000000..8fdf1ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1049.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1049.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n01i01049ent IS
+END c06s04b00x00p03n01i01049ent;
+
+ARCHITECTURE c06s04b00x00p03n01i01049arch OF c06s04b00x00p03n01i01049ent IS
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type A1 is array (THREE) of BOOLEAN;
+    type ONE is range 1 to 1;
+    type A2 is array (ONE) of BOOLEAN;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := A2'(others=>TRUE)(1);
+    -- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n01i01049 - Prefix of an indexed name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n01i01049arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc105.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc105.vhd
new file mode 100644
index 0000000..a5c6bf5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc105.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc105.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00105ent IS
+  port ( signal S : out bit) ;
+END c04s03b02x00p29n06i00105ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00105arch OF c04s03b02x00p29n06i00105ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if (S'ACTIVE) then  -- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p29n06i00105 - The attribute ACTIVE of a signal of mode out cannot be read." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00105arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1051.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1051.vhd
new file mode 100644
index 0000000..b8894ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1051.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1051.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01051ent IS
+END c06s04b00x00p03n02i01051ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01051arch OF c06s04b00x00p03n02i01051ent IS
+  type arrtype is array (1 to 10, 1 to 2) of real;
+BEGIN
+  TESTING: PROCESS
+    variable k : arrtype ;
+  BEGIN
+    str (1 + 2) := 1.2;   -- expression for second index position is
+    -- missing.
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01051 - There should exist an expresion for each index position of the array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01051arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1052.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1052.vhd
new file mode 100644
index 0000000..eaa5716
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1052.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1052.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01052ent IS
+END c06s04b00x00p03n02i01052ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01052arch OF c06s04b00x00p03n02i01052ent IS
+  type arrtype is array (positive range 1 to 10, bit range '0' to '1') of real;
+BEGIN
+  TESTING: PROCESS
+    variable k : arrtype ;
+  BEGIN
+    str (1 + 2, 0 + 2) := 1.2;  -- illegal.
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01052 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01052arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1053.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1053.vhd
new file mode 100644
index 0000000..5049338
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1053.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1053.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01053ent IS
+END c06s04b00x00p03n02i01053ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01053arch OF c06s04b00x00p03n02i01053ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+
+    type A11 is array (THREE) of BOOLEAN;
+    
+    variable V1: BOOLEAN;
+    variable V11: A11 ;
+  BEGIN
+    V1 := V11(1, 2);                 -- ONE MORE
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01053 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01053arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1054.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1054.vhd
new file mode 100644
index 0000000..0af280f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1054.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1054.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01054ent IS
+END c06s04b00x00p03n02i01054ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01054arch OF c06s04b00x00p03n02i01054ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (EN1, EN2, EN3);
+
+    type A12 is array (ENUM1) of BOOLEAN;
+    
+    variable V1: BOOLEAN;
+    variable V12: A12 ;
+  BEGIN
+    V1 := V12(EN3, EN2);             -- ONE MORE
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01054 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01054arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1055.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1055.vhd
new file mode 100644
index 0000000..8f4392b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1055.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1055.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01055ent IS
+END c06s04b00x00p03n02i01055ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01055arch OF c06s04b00x00p03n02i01055ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE    is range 1 to 3;
+    type A21    is array (THREE, THREE) of BOOLEAN;
+    
+    variable V1   : BOOLEAN;
+    variable V21: A21 ;
+  BEGIN
+    V1 := V21(2);                    -- ONE LESS
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01055 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01055arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1056.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1056.vhd
new file mode 100644
index 0000000..db64c55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1056.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1056.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01056ent IS
+END c06s04b00x00p03n02i01056ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01056arch OF c06s04b00x00p03n02i01056ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1    is (EN1, EN2, EN3);
+    type A22    is array (ENUM1, ENUM1) of BOOLEAN;
+    
+    variable V1   : BOOLEAN;
+    variable V22: A22 ;
+  BEGIN
+    V1 := V22(EN2);                  -- ONE LESS
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01056 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01056arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1057.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1057.vhd
new file mode 100644
index 0000000..be57b5c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1057.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1057.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01057ent IS
+END c06s04b00x00p03n02i01057ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01057arch OF c06s04b00x00p03n02i01057ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type A21 is array (THREE, THREE) of BOOLEAN;
+    
+    variable V1: BOOLEAN;
+
+    variable V21: A21 ;
+  BEGIN
+    V1 := V21(3, 2, 1);              -- ONE MORE
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01057 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01057arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1058.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1058.vhd
new file mode 100644
index 0000000..622d07a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1058.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1058.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01058ent IS
+END c06s04b00x00p03n02i01058ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01058arch OF c06s04b00x00p03n02i01058ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1    is (EN1, EN2, EN3);
+
+    type A22    is array (ENUM1, ENUM1) of BOOLEAN;
+    
+    variable V1: BOOLEAN;
+
+    variable V22: A22 ;
+  BEGIN
+    V1 := V22(EN1, EN2, EN3);        -- ONE MORE
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01058 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01058arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1059.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1059.vhd
new file mode 100644
index 0000000..6297e43
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1059.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1059.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01059ent IS
+END c06s04b00x00p03n02i01059ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01059arch OF c06s04b00x00p03n02i01059ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type ENUM1 is (EN1, EN2, EN3);
+    type A22 is array (ENUM1, ENUM1) of BOOLEAN;
+    type A31 is array (THREE) of A22;
+    
+    variable V1   : BOOLEAN;
+    variable V31: A31 ;
+  BEGIN
+    V1 := V31(2)(EN2);               -- ONE LESS
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01059 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01059arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc106.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc106.vhd
new file mode 100644
index 0000000..fbe1529
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc106.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc106.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00106ent IS
+  port ( signal S : out bit) ;
+END c04s03b02x00p29n06i00106ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00106arch OF c04s03b02x00p29n06i00106ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable T : TIME := 10 ns;
+  BEGIN
+    if (S'LAST_EVENT = T) then  -- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p29n06i00106 - The attribute LAST_EVENT of a signal of mode out cannot be read." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00106arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1060.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1060.vhd
new file mode 100644
index 0000000..e3a6ce2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1060.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1060.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01060ent IS
+END c06s04b00x00p03n02i01060ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01060arch OF c06s04b00x00p03n02i01060ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type ENUM1 is (EN1, EN2, EN3);
+
+    type A22 is array (ENUM1, ENUM1) of BOOLEAN;
+    type A31 is array (THREE) of A22;
+    
+    variable V1: BOOLEAN;
+    variable V31: A31 ;
+  BEGIN
+    V1 := V31(2)(EN3, EN2, EN1);     -- ONE MORE
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01060 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01060arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1061.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1061.vhd
new file mode 100644
index 0000000..30e7160
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1061.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1061.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01061ent IS
+END c06s04b00x00p03n02i01061ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01061arch OF c06s04b00x00p03n02i01061ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type ENUM1 is (EN1, EN2, EN3);
+
+    type A11 is array (THREE) of BOOLEAN;
+    type A32 is array (ENUM1, ENUM1) of A11;
+    
+    variable V1   : BOOLEAN;
+    variable V32: A32 ;
+  BEGIN
+    V1 := V32(EN2)(2);               -- ONE LESS
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01061 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01061arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1062.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1062.vhd
new file mode 100644
index 0000000..fb2e515
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1062.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1062.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01062ent IS
+END c06s04b00x00p03n02i01062ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01062arch OF c06s04b00x00p03n02i01062ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type ENUM1 is (EN1, EN2, EN3);
+
+    type A11 is array (THREE) of BOOLEAN;
+    type A32 is array (ENUM1, ENUM1) of A11;
+    
+    variable V1   : BOOLEAN;
+    variable V32: A32 ;
+  BEGIN
+    V1 := V32(EN1, EN2, EN3)(2);     -- ONE MORE
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01062 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01062arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1063.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1063.vhd
new file mode 100644
index 0000000..9a0003a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1063.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1063.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01063ent IS
+END c06s04b00x00p03n02i01063ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01063arch OF c06s04b00x00p03n02i01063ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type ENUM1 is (EN1, EN2, EN3);
+
+    type A22 is array (ENUM1, ENUM1) of BOOLEAN;
+    type A31 is array (THREE) of A22;
+    
+    variable V1: BOOLEAN;
+    variable V31: A31 ;
+  BEGIN
+    V1 := V31(1, EN2)(EN3);     -- ONE MORE AND ONE LESS
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01063 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01063arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1064.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1064.vhd
new file mode 100644
index 0000000..8f6b971
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1064.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1064.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01064ent IS
+END c06s04b00x00p03n02i01064ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01064arch OF c06s04b00x00p03n02i01064ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+    type ENUM1 is (EN1, EN2, EN3);
+
+    type A11 is array (THREE) of BOOLEAN;
+    type A32 is array (ENUM1, ENUM1) of A11;
+    
+    variable V1   : BOOLEAN;
+    variable V32: A32 ;
+  BEGIN
+    V1 := V32(EN3)(EN2, 1);     -- ONE LESS AND ONE MORE
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01064 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01064arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1065.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1065.vhd
new file mode 100644
index 0000000..ec76bc7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1065.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1065.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01065ent IS
+END c06s04b00x00p03n02i01065ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01065arch OF c06s04b00x00p03n02i01065ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+
+    type A21 is array (THREE, THREE) of BOOLEAN;
+    
+    variable V1: BOOLEAN;
+    variable V21: A21 ;
+  BEGIN
+    V1 := V21(2)(2);                 -- WRONG DIMENSIONALITY
+    -- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
+    -- INDEX POSITIONS IN TYPE DECLARATION
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01065 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01065arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1066.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1066.vhd
new file mode 100644
index 0000000..52e4738
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1066.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1066.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n02i01066ent IS
+END c06s04b00x00p03n02i01066ent;
+
+ARCHITECTURE c06s04b00x00p03n02i01066arch OF c06s04b00x00p03n02i01066ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type THREE is range 1 to 3;
+
+    type A11 is array (THREE) of BOOLEAN;
+    
+    variable V1: BOOLEAN;
+    variable V11: A11 ;
+  BEGIN
+    V1 := V11;    -- DEGENERATE CASE OF ONE LESS;
+    -- SEMANTIC ERROR: TYPE INCOMPATIBILITY IN ASSIGNMENT
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n02i01066 - The expresion should be the same type as the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n02i01066arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1068.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1068.vhd
new file mode 100644
index 0000000..6fcc4ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1068.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1068.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n04i01068ent IS
+END c06s04b00x00p03n04i01068ent;
+
+ARCHITECTURE c06s04b00x00p03n04i01068arch OF c06s04b00x00p03n04i01068ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable str : string(1 to 20) := "This is string check";
+  BEGIN
+    if str(21) = 'T' then  -- illegal as 21 does not belong to the index
+      -- range of str.
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n04i01068 - Index value should belong to the range of the corresponding index range of the array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n04i01068arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc107.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc107.vhd
new file mode 100644
index 0000000..2bca950
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc107.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc107.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00107ent IS
+  port ( signal S : out bit) ;
+END c04s03b02x00p29n06i00107ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00107arch OF c04s03b02x00p29n06i00107ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable T : TIME := 10 ns;
+  BEGIN
+    if (S'LAST_ACTIVE = T) then  -- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p29n06i00107 - The attribute LAST_ACTIVE of a signal of mode out cannot be read." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00107arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc108.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc108.vhd
new file mode 100644
index 0000000..2836c6e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc108.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc108.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00108ent IS
+  port ( signal S : out bit) ;
+END c04s03b02x00p29n06i00108ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00108arch OF c04s03b02x00p29n06i00108ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable T : TIME := 10 ns;
+  BEGIN
+    if (S'LAST_VALUE = bit'('1')) then  -- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p29n06i00108 - The attribute LAST_VALUE of a signal of mode out cannot be read." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00108arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1082.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1082.vhd
new file mode 100644
index 0000000..2ffdff3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1082.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1082.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01082ent IS
+END c06s05b00x00p02n01i01082ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01082arch OF c06s05b00x00p02n01i01082ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE is range 1 to 5;
+    type A51 is array (FIVE) of BOOLEAN;
+    type A53 is array (FIVE) of A51;
+    
+    variable V51: A51 ;
+    variable V53: A53 ;
+  BEGIN
+    V51(2 to 2, 3 to 3) := V51(2 to 2, 3 to 3);
+    -- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p02n01i01082 - Slice name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01082arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1083.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1083.vhd
new file mode 100644
index 0000000..4b187ce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1083.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1083.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01083ent IS
+END c06s05b00x00p02n01i01083ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01083arch OF c06s05b00x00p02n01i01083ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE is range 1 to 5;
+    type A51 is array (FIVE) of BOOLEAN;
+    type A53 is array (FIVE) of A51;
+    
+    variable V51: A51 ;
+    variable V53: A53 ;
+  BEGIN
+    V53(2 to 3, 3 to 4) := V53(2 to 3, 3 to 4);
+    -- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p02n01i01083 - Slice name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01083arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1084.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1084.vhd
new file mode 100644
index 0000000..9715f95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1084.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1084.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01084ent IS
+END c06s05b00x00p02n01i01084ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01084arch OF c06s05b00x00p02n01i01084ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE is range 1 to 5;
+    type A51 is array (FIVE) of BOOLEAN;
+    type A53 is array (FIVE) of A51;
+    
+    variable V51: A51 ;
+    variable V53: A53 ;
+  BEGIN
+    V51(2 downto 1, 3 to 4) := V51(2 downto 1, 3 to 4);       
+    -- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p02n01i01084 - Slice name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01084arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1085.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1085.vhd
new file mode 100644
index 0000000..8068d82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1085.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1085.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p02n01i01085ent IS
+END c06s05b00x00p02n01i01085ent;
+
+ARCHITECTURE c06s05b00x00p02n01i01085arch OF c06s05b00x00p02n01i01085ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type FIVE is range 1 to 5;
+    type A51 is array (FIVE) of BOOLEAN;
+    type A53 is array (FIVE) of A51;
+    
+    variable V51: A51 ;
+    variable V53: A53 ;
+  BEGIN
+    V53(2 downto 1, 1 to 4) := V53(2 downto 1, 1 to 4);       
+    -- SYNTAX ERROR: NO MULTIPLE DISCRETE RANGES IN SLICE NAMES
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p02n01i01085 - Slice name consists of a single discrete range enclosed within parentheses."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p02n01i01085arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc109.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc109.vhd
new file mode 100644
index 0000000..3fdb6b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc109.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc109.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00109ent IS
+  port ( signal S : out bit) ;
+END c04s03b02x00p29n06i00109ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00109arch OF c04s03b02x00p29n06i00109ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable T : TIME := 10 ns;
+  BEGIN
+    if (S'TRANSACTION = bit'('1')) then  -- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p29n06i00109 - The attribute TRANSACTION of a signal of mode out cannot be read." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00109arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1093.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1093.vhd
new file mode 100644
index 0000000..6414853
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1093.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1093.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01093ent IS
+END c06s05b00x00p03n01i01093ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01093arch OF c06s05b00x00p03n01i01093ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BIT_VECTOR is range 1 to 10;
+    variable NUM1 : BIT_VECTOR;
+  BEGIN
+    NUM1(0 to 1) := 0;  -- illegal.
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01093 - Prefix of a slice must be appropraite for a one-dimensional array object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01093arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1094.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1094.vhd
new file mode 100644
index 0000000..bf9e0c2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1094.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1094.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01094ent IS
+END c06s05b00x00p03n01i01094ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01094arch OF c06s05b00x00p03n01i01094ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type sting is array (1 to 5, 1 to 5) of character;
+    variable str : sting;
+  BEGIN
+    str(1 to 3, 1 to 3) := str(3 to 5, 3 to 5); -- slice of a two
+                                                -- dimensional array is
+                                                -- illegal.
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01094 - Prefix of a slice must be appropraite for a one-dimensional array object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01094arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1095.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1095.vhd
new file mode 100644
index 0000000..76cae58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1095.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1095.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01095ent IS
+END c06s05b00x00p03n01i01095ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01095arch OF c06s05b00x00p03n01i01095ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;   
+  BEGIN
+    V2 := (1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (3 to 3);
+    -- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01095 - Prefix of a slice must be appropraite for a one-dimensional array object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01095arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1096.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1096.vhd
new file mode 100644
index 0000000..78caeba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1096.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1096.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01096ent IS
+END c06s05b00x00p03n01i01096ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01096arch OF c06s05b00x00p03n01i01096ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;   
+  BEGIN
+    V2 := A5'(1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (3 to 3);
+    -- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01096 - Prefix of a slice must be appropraite for a one-dimensional array object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01096arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1097.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1097.vhd
new file mode 100644
index 0000000..ed219d6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1097.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1097.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01097ent IS
+END c06s05b00x00p03n01i01097ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01097arch OF c06s05b00x00p03n01i01097ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE is INTEGER range 1 to 5;
+    subtype THREE is INTEGER range 1 to 3;
+    subtype ONE is INTEGER range 1 to 1;
+    type A0 is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;   
+  BEGIN
+    V2 := (others=>TRUE)(3 to 3);
+    -- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01097 - Prefix of a slice must be appropraite for a one-dimensional array object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01097arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1098.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1098.vhd
new file mode 100644
index 0000000..bb769a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1098.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1098.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01098ent IS
+END c06s05b00x00p03n01i01098ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01098arch OF c06s05b00x00p03n01i01098ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;   
+  BEGIN
+    V2 := A5'(others=>TRUE)(3 to 3);
+    -- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01098 - Prefix of a slice must be appropraite for a one-dimensional array object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01098arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1099.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1099.vhd
new file mode 100644
index 0000000..98e3045
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1099.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1099.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01099ent IS
+END c06s05b00x00p03n01i01099ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01099arch OF c06s05b00x00p03n01i01099ent IS
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE is INTEGER range 1 to 5;
+    subtype THREE is INTEGER range 1 to 3;
+    subtype ONE is INTEGER range 1 to 1;
+    type A0 is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;   
+  BEGIN
+    V3 := (1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (2 to 4);
+    -- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01099 - Prefix of a slice must be appropraite for a one-dimensional array object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01099arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc11.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc11.vhd
new file mode 100644
index 0000000..a3afb06
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc11.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc11.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p02n01i00011ent IS
+END c04s02b00x00p02n01i00011ent;
+
+ARCHITECTURE c04s02b00x00p02n01i00011arch OF c04s02b00x00p02n01i00011ent IS
+  
+  -- Failure_here: Missing 'is':
+  subtype GROUND BIT range '0' to '0';
+  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST:c04s02b00x00p02n01i00011 - The reserved word is is misssing." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p02n01i00011arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1100.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1100.vhd
new file mode 100644
index 0000000..6fd316a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1100.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1100.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01100ent IS
+END c06s05b00x00p03n01i01100ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01100arch OF c06s05b00x00p03n01i01100ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;   
+  BEGIN
+    V3 := A5'(1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (2 to 4);
+    -- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01100 - Prefix of a slice must be appropraite for a one-dimensional array object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01100arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1101.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1101.vhd
new file mode 100644
index 0000000..fb2e38d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1101.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1101.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01101ent IS
+END c06s05b00x00p03n01i01101ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01101arch OF c06s05b00x00p03n01i01101ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;   
+  BEGIN
+    V3 := (others=>TRUE) (2 to 4);
+    -- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01101 - Prefix of a slice must be appropraite for a one-dimensional array object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01101arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1102.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1102.vhd
new file mode 100644
index 0000000..48b3601
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1102.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1102.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01102ent IS
+END c06s05b00x00p03n01i01102ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01102arch OF c06s05b00x00p03n01i01102ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;   
+  BEGIN
+    V3 := A5'(others=>TRUE) (2 to 4);
+    -- PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01102 - Prefix of a slice must be appropraite for a one-dimensional array object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01102arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1105.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1105.vhd
new file mode 100644
index 0000000..4e3ef08
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1105.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1105.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01105ent IS
+END c06s05b00x00p03n01i01105ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01105arch OF c06s05b00x00p03n01i01105ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;
+  BEGIN
+    V2 := (1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (3 to 3);
+    -- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01105 - Prefix of a slice name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01105arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1106.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1106.vhd
new file mode 100644
index 0000000..7b9afc3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1106.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1106.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01106ent IS
+END c06s05b00x00p03n01i01106ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01106arch OF c06s05b00x00p03n01i01106ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;
+  BEGIN
+    V2 := A5'(1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (3 to 3);
+    -- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01106 - Prefix of a slice name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01106arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1107.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1107.vhd
new file mode 100644
index 0000000..7b21517
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1107.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1107.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01107ent IS
+END c06s05b00x00p03n01i01107ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01107arch OF c06s05b00x00p03n01i01107ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;
+  BEGIN
+    V2 := (others=>TRUE)(3 to 3);
+    -- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01107 - Prefix of a slice name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01107arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1108.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1108.vhd
new file mode 100644
index 0000000..7633d9d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1108.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1108.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01108ent IS
+END c06s05b00x00p03n01i01108ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01108arch OF c06s05b00x00p03n01i01108ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;
+  BEGIN
+    V2 := A5'(others=>TRUE)(3 to 3);
+    -- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01108 - Prefix of a slice name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01108arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1109.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1109.vhd
new file mode 100644
index 0000000..17b0c12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1109.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1109.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01109ent IS
+END c06s05b00x00p03n01i01109ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01109arch OF c06s05b00x00p03n01i01109ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;
+  BEGIN
+    V3 := (1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (2 to 4);
+    -- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01109 - Prefix of a slice name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01109arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1110.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1110.vhd
new file mode 100644
index 0000000..a889ec9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1110.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1110.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01110ent IS
+END c06s05b00x00p03n01i01110ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01110arch OF c06s05b00x00p03n01i01110ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;
+  BEGIN
+    V3 := A5'(1=>TRUE, 2=>TRUE, 3=>TRUE, 4=>TRUE, 5=>TRUE) (2 to 4);
+    -- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01110 - Prefix of a slice name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01110arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1111.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1111.vhd
new file mode 100644
index 0000000..6fc9ca7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1111.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1111.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01111ent IS
+END c06s05b00x00p03n01i01111ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01111arch OF c06s05b00x00p03n01i01111ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;
+  BEGIN
+    V3 := (others=>TRUE) (2 to 4);
+    -- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01111 - Prefix of a slice name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01111arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1112.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1112.vhd
new file mode 100644
index 0000000..9b29e58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1112.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1112.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01112ent IS
+END c06s05b00x00p03n01i01112ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01112arch OF c06s05b00x00p03n01i01112ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype FIVE    is INTEGER range 1 to 5;
+    subtype THREE    is INTEGER range 1 to 3;
+    subtype ONE    is INTEGER range 1 to 1;
+    type A0       is array (INTEGER range <>) of BOOLEAN;
+    subtype A1 is A0 (FIVE);
+    subtype A2 is A0 (ONE);
+    subtype A3 is A0 (THREE);
+    subtype A5 is A0 (FIVE);
+    variable V2: A2;
+    variable V3: A3;
+  BEGIN
+    V3 := A5'(others=>TRUE) (2 to 4);
+    -- SYNTAX ERROR: PREFIX OF SLICE NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01112 - Prefix of a slice name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01112arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1113.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1113.vhd
new file mode 100644
index 0000000..f044b39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1113.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1113.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01113ent IS
+END c06s05b00x00p03n01i01113ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01113arch OF c06s05b00x00p03n01i01113ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    FIVE    is range 1 to 5;
+    type    A1B    is array (FIVE range <>) of BOOLEAN;
+    subtype A1    is A1B(FIVE);
+    type    A2B    is array (FIVE range <>, FIVE range <>) of A1;
+    subtype A2    is A2B(FIVE, FIVE);
+
+    variable V1: A1;
+    variable V2: A2;
+  BEGIN
+    V1(5) := V1(3)(3 to 3);  -- ERROR:  prefix of a slice name
+    -- cannot be an array element unless
+    -- the array element is an one-dimensional
+    -- array
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01113 - Prefix of a slice number must be a one-dimensional array type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01113arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1114.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1114.vhd
new file mode 100644
index 0000000..00e9714
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1114.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1114.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01114ent IS
+END c06s05b00x00p03n01i01114ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01114arch OF c06s05b00x00p03n01i01114ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    FIVE    is range 1 to 5;
+    type    A1B    is array (FIVE range <>) of BOOLEAN;
+    subtype A1    is A1B(FIVE);
+    type    A2B    is array (FIVE range <>, FIVE range <>) of A1;
+    subtype A2    is A2B(FIVE, FIVE);
+
+    variable V1: A1;
+    variable V2: A2;
+  BEGIN
+    V1(2 to 4) := V2(1 to 3);   -- ERROR: prefix of a slice name
+                                    -- cannot be a multi-dimensional
+                                        -- array object
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01114 - Prefix of a slice number must be a one-dimensional array type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01114arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1115.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1115.vhd
new file mode 100644
index 0000000..c48d5bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1115.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1115.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01115ent IS
+END c06s05b00x00p03n01i01115ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01115arch OF c06s05b00x00p03n01i01115ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    FIVE    is range 1 to 5;
+    type    A1B    is array (FIVE range <>) of BOOLEAN;
+    subtype A1    is A1B(FIVE);
+    type    A2B    is array (FIVE range <>, FIVE range <>) of A1;
+    subtype A2    is A2B(FIVE, FIVE);
+    
+    function G return A2 is
+    begin
+      return (others => (others => (others => false)));
+    end G;
+
+    variable V1: A1;
+    variable V2: A2;
+  BEGIN
+    V1(2 to 4) := G(3 to 5);   -- ERROR: prefix of a slice name
+    -- cannot be a function value
+    -- of a multi-dimensional array type
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01115 - Prefix of a slice number must be a one-dimensional array type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01115arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1116.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1116.vhd
new file mode 100644
index 0000000..70c4d3f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1116.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1116.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01116ent IS
+END c06s05b00x00p03n01i01116ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01116arch OF c06s05b00x00p03n01i01116ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    FIVE    is range 1 to 5;
+    type    A1B    is array (FIVE range <>) of BOOLEAN;
+    subtype A1    is A1B(FIVE);
+    type    A2B    is array (FIVE range <>, FIVE range <>) of A1;
+    subtype A2    is A2B(FIVE, FIVE);
+
+    type R is record
+                RE1:  INTEGER;
+              end record;
+
+    variable V1: A1;
+    variable V2: A2;
+    variable R1: R;
+  BEGIN
+    V1(3 to 4) := R1(2 to 5);   -- ERROR: prefix of a slice name
+                                    -- cannot be a record object
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01116 - Prefix of a slice number must be a one-dimensional array type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01116arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1118.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1118.vhd
new file mode 100644
index 0000000..2b5e67a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1118.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1118.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p03n01i01118ent IS
+END c06s05b00x00p03n01i01118ent;
+
+ARCHITECTURE c06s05b00x00p03n01i01118arch OF c06s05b00x00p03n01i01118ent IS
+
+  type idx   is range 1 to 10;
+  type aray1 is array (idx) of bit;
+  type aray2 is array (idx range <>) of aray1;
+
+BEGIN
+  TESTING: PROCESS
+    variable v1 : aray1;          -- default is all '0'
+  BEGIN
+    --
+    -- Try slices of aggregates
+    --
+    v1 := "1111111111";
+    v1 := aray1'(others => '0')(idx);        -- slice is the whole aggr
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p03n01i01118 - Slice of an aggregate as a value failed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p03n01i01118arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc112.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc112.vhd
new file mode 100644
index 0000000..491873d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc112.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc112.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n06i00112ent IS
+  port (   S1 : out BIT_VECTOR(0 to 3) := "1011";
+           S2 : out BIT := '1') ;
+END c04s03b02x00p29n06i00112ent;
+
+ARCHITECTURE c04s03b02x00p29n06i00112arch OF c04s03b02x00p29n06i00112ent IS
+  signal S3 : BIT;
+BEGIN
+
+  S3    <= S2 after 20 ns;      --Failure here
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x00p29n06i00112 - Interface object of mode out cannot be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n06i00112arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1124.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1124.vhd
new file mode 100644
index 0000000..1076fb8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1124.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1124.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01124ent IS
+END c06s05b00x00p04n01i01124ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01124arch OF c06s05b00x00p04n01i01124ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     BIT_VECTOR is array (positive range <>) of BIT;
+    variable NUM1 : BIT_VECTOR(1 to 10) := B"01_01_01_01_01";
+  BEGIN
+    NUM1(7 to 12) := B"010_010";
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01124 - Bounds of the slice cannot exceed those defined by the discrete range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01124arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1125.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1125.vhd
new file mode 100644
index 0000000..24a5169
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1125.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1125.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01125ent IS
+END c06s05b00x00p04n01i01125ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01125arch OF c06s05b00x00p04n01i01125ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       BIT_VECTOR is array (bit range <>) of BIT;
+    variable    NUM1 : BIT_VECTOR (0 to 1) := "00";    -- 0 to 1 is incorrect.
+                                                       -- should be '0' to '1'.
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01125 - Bounds of the discrete range must be the type of the index of the array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01125arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1127.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1127.vhd
new file mode 100644
index 0000000..b819e11
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1127.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1127.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01127ent IS
+END c06s05b00x00p04n01i01127ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01127arch OF c06s05b00x00p04n01i01127ent IS
+
+  type idx is range 1 to 10;
+  type aray1 is array (idx) of bit;
+  type aray2 is array (idx range <>) of aray1;
+BEGIN
+  TESTING: PROCESS
+    variable v2 : aray1;
+    variable v3 : aray2(1 to 2);
+  BEGIN
+    v2 := v3(2 to 2)(1);             -- wrong index
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01127 - Invalid index for slice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01127arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1128.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1128.vhd
new file mode 100644
index 0000000..519c5bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1128.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1128.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01128ent IS
+END c06s05b00x00p04n01i01128ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01128arch OF c06s05b00x00p04n01i01128ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type   NNUM1 is (M1, M2, M3, M4, M5);   
+    type    FIVE1 is range 1 to 5;
+    type    FIVE2 is range 1 to 5;
+    variable    VF1LOW:  FIVE1 := 2;
+    variable    VF2HIGH: FIVE2 := 4;
+    type    AE5 is array (M1 to M5) of BOOLEAN;
+    type    AF5 is array (FIVE1)    of BOOLEAN;
+
+    variable    VAE5: AE5 ;
+    variable    VAF5: AF5 ;
+  BEGIN
+    VAF5(2 to 4) := VAF5(VF1LOW to VF2HIGH);
+    -- ERROR: BOUNDS OF DISCRETE RANGE MUST BE OF SAME TYPE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01128 - Bounds of discrete ranges must be of same type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01128arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1129.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1129.vhd
new file mode 100644
index 0000000..4402fb2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1129.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1129.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01129ent IS
+END c06s05b00x00p04n01i01129ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01129arch OF c06s05b00x00p04n01i01129ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ENUM2 is (N1, N2, N3, N4, N5);
+    type FIVE1 is range 1 to 5;
+    type FIVE2 is range 1 to 5;
+
+    type    A1B is array (ENUM1 range <>) of BOOLEAN;
+    subtype    A1  is A1B(ENUM1);
+    type    A2B is array (ENUM2 range <>) of A1;
+
+    variable V1: A1 ;
+    constant FIVE2_2: FIVE2 := 2;
+    constant FIVE2_4: FIVE2 := 4;
+  BEGIN
+    V1(M2 to M4) := V1(N1 to N5);
+    -- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01129 - Discrete range incompatible with index type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01129arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1130.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1130.vhd
new file mode 100644
index 0000000..0e30e59
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1130.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1130.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01130ent IS
+END c06s05b00x00p04n01i01130ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01130arch OF c06s05b00x00p04n01i01130ent IS
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ENUM2 is (N1, N2, N3, N4, N5);
+    type FIVE1 is range 1 to 5;
+    type FIVE2 is range 1 to 5;
+
+    type    A1B is array (ENUM1 range <>) of BOOLEAN;
+    subtype    A1  is A1B(ENUM1);
+
+    variable V1: A1 ;
+    constant FIVE2_2: FIVE2 := 2;
+    constant FIVE2_4: FIVE2 := 4;
+  BEGIN
+    V1(M2 to M4) := V1(M1 to N5);
+    -- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01130 - Discrete range incompatible with index type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01130arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1131.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1131.vhd
new file mode 100644
index 0000000..e7119a1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1131.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1131.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01131ent IS
+END c06s05b00x00p04n01i01131ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01131arch OF c06s05b00x00p04n01i01131ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ENUM2 is (N1, N2, N3, N4, N5);
+    type FIVE1 is range 1 to 5;
+    type FIVE2 is range 1 to 5;
+
+    type A1B   is array (ENUM1 range <>) of BOOLEAN;
+    subtype A1 is A1B(ENUM1);
+
+    variable V1: A1 ;
+    constant FIVE2_2: FIVE2 := 2;
+    constant FIVE2_4: FIVE2 := 4;
+  BEGIN
+    V1(M2 to M4) := V1(N1 to M5);
+    -- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01131 - Discrete range incompatible with index type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01131arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1132.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1132.vhd
new file mode 100644
index 0000000..4de60b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1132.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1132.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01132ent IS
+END c06s05b00x00p04n01i01132ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01132arch OF c06s05b00x00p04n01i01132ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ENUM2 is (N1, N2, N3, N4, N5);
+    type FIVE1 is range 1 to 5;
+    type FIVE2 is range 1 to 5;
+
+    type    A1B    is array (ENUM1 range <>) of BOOLEAN;
+    subtype    A1    is A1B(ENUM1);
+    type    A2B    is array (ENUM2 range <>) of A1;
+    subtype    A2    is A2B(ENUM2);
+
+    variable V1: A1 ;
+    variable V2: A2 ;
+
+    constant FIVE2_2: FIVE2 := 2;
+    constant FIVE2_4: FIVE2 := 4;
+  BEGIN
+    V2(N3)(M2 to M4) := V2(N3)(N1 to N2);
+    -- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01132 - Discrete range incompatible with index type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01132arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1133.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1133.vhd
new file mode 100644
index 0000000..d36850b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1133.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1133.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01133ent IS
+END c06s05b00x00p04n01i01133ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01133arch OF c06s05b00x00p04n01i01133ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ENUM2 is (N1, N2, N3, N4, N5);
+    type FIVE1 is range 1 to 5;
+    type FIVE2 is range 1 to 5;
+
+    type    A3B is array (FIVE1 range <>) of BOOLEAN;
+    subtype    A3  is A3B(FIVE1);
+
+    variable V3: A3 ;
+
+    constant FIVE2_2: FIVE2 := 2;
+    constant FIVE2_4: FIVE2 := 4;
+  BEGIN
+    V3(2 to 4) := V3(FIVE2_2 to FIVE2_4);
+    -- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01133 - Discrete range incompatible with index type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01133arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1134.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1134.vhd
new file mode 100644
index 0000000..4471d14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1134.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1134.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01134ent IS
+END c06s05b00x00p04n01i01134ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01134arch OF c06s05b00x00p04n01i01134ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ENUM2 is (N1, N2, N3, N4, N5);
+    type FIVE1 is range 1 to 5;
+    type FIVE2 is range 1 to 5;
+
+    type    A4B is array (FIVE2 range <>) of A3;
+    subtype    A4  is A4B(FIVE2);
+
+    variable V4: A4 ;
+
+    constant FIVE2_2: FIVE2 := 2;
+    constant FIVE2_4: FIVE2 := 4;
+  BEGIN
+    V4(3)(2 to 4) := V4(3)(FIVE2_2 to FIVE2_4);
+    -- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01134 - Discrete range incompatible with index type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01134arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1135.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1135.vhd
new file mode 100644
index 0000000..b311746
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1135.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1135.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n01i01135ent IS
+END c06s05b00x00p04n01i01135ent;
+
+ARCHITECTURE c06s05b00x00p04n01i01135arch OF c06s05b00x00p04n01i01135ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5);
+    type ENUM2 is (N1, N2, N3, N4, N5);
+    type FIVE1 is range 1 to 5;
+    type FIVE2 is range 1 to 5;
+    variable VE1LOW: ENUM1 := M2;
+    variable VE2HIGH: ENUM2 := N4;
+    variable VF1LOW: FIVE1 := 2;
+    variable VF2HIGH: FIVE2 := 4;
+    type AE5 is array (M1 to M5) of BOOLEAN;
+    type AF5 is array (FIVE1) of BOOLEAN;
+    variable VAE5: AE5 ;
+    variable VAF5: AF5 ;
+  BEGIN
+    VAE5(M2 to M4) := VAE5(VE1LOW to VE2HIGH);
+    -- SEMANTIC ERROR: BOUNDS OF DISCRETE RANGE MUST BE OF SAME TYPE
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n01i01135 - Bounds of discrete ranges must be of same type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n01i01135arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1136.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1136.vhd
new file mode 100644
index 0000000..d7b9f09
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1136.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1136.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p04n02i01136ent IS
+  type idx   is range 1 to 10;
+  type aray1 is array (idx range <>) of bit;
+END c06s05b00x00p04n02i01136ent;
+
+ARCHITECTURE c06s05b00x00p04n02i01136arch OF c06s05b00x00p04n02i01136ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable v1, v2 : aray1(idx);         -- default is all '0'
+  BEGIN
+    --
+    -- Test the range direction
+    --
+    v1 := "1111111111";
+    v2 :=  v1(10 downto 1);  -- range is opposite
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p04n02i01136 - The direction of the discrete range must be the same as that of the prefix of the slice name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p04n02i01136arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1141.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1141.vhd
new file mode 100644
index 0000000..2a0cf78
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1141.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1141.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01141ent IS
+END c06s05b00x00p05n02i01141ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01141arch OF c06s05b00x00p05n02i01141ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1    is (M1, M2, M3, M4, M5, M6);
+    type A    is array ( ENUM1 range <> ) of BOOLEAN;
+    subtype A1    is A(M1 to M6) ;
+    subtype A2    is A(M6 downto M1) ;
+    variable V1: A1 ;
+    variable V2: A2 ;
+  BEGIN
+    V1(M2 to M4) := V1(M4 downto M2);
+    --ERROR: discrete range descending when the prefix
+    --type was declared with a ascending range results in a null
+    --slice, which is incompatible with non-null slice
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p05n02i01141 - Null slice is not compatible with non-null slice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01141arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1142.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1142.vhd
new file mode 100644
index 0000000..b559471
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1142.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1142.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01142ent IS
+END c06s05b00x00p05n02i01142ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01142arch OF c06s05b00x00p05n02i01142ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is (M1, M2, M3, M4, M5, M6);
+    type A     is array ( ENUM1 range <> ) of BOOLEAN;
+    subtype A1 is A(M1 to M6) ;
+    subtype A2 is A(M6 downto M1) ;
+    variable V1: A1 ;
+    variable V2: A2 ;
+  BEGIN
+    V2(M4 downto M2) := V2(M2 to M4);
+    --ERROR: discrete range ascending when the prefix     
+    --type was declared with a descending range results in a null
+    --slice, which is incompatible with non-null slice
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p05n02i01142 - Null slice is not compatible with non-null slice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01142arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1143.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1143.vhd
new file mode 100644
index 0000000..0ea4231
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1143.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1143.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01143ent IS
+END c06s05b00x00p05n02i01143ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01143arch OF c06s05b00x00p05n02i01143ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type B is  array ( INTEGER range <> ) of BOOLEAN;
+    subtype B1 is B(1 to 6) ;
+    subtype B2 is B(6 downto 1) ;
+    variable V3: B1 ;
+    variable V4: B2 ;
+  BEGIN
+    V3(2 to 4) := V3(4 downto 2);
+    --ERROR: discrete range descending when the prefix    
+    --type was declared with a ascending range results in a null
+    --slice, which is incompatible with non-null slice
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p05n02i01143 - Null slice is not compatible with non-null slice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01143arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1144.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1144.vhd
new file mode 100644
index 0000000..eda1cbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1144.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1144.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01144ent IS
+END c06s05b00x00p05n02i01144ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01144arch OF c06s05b00x00p05n02i01144ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    B  is array ( INTEGER range <> ) of BOOLEAN;
+    subtype B2 is B(6 downto 1) ;
+    variable V4: B2 ;
+  BEGIN
+    V4(4 downto 2) := V4(2 to 4);
+    --ERROR: discrete range ascending when the prefix     
+    --type was declared with a descending range results in a null
+    --slice, which is incompatible with non-null slice
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p05n02i01144 - Null slice is not compatible with non-null slice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01144arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1146.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1146.vhd
new file mode 100644
index 0000000..7e61a9c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1146.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1146.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s05b00x00p05n02i01146ent IS
+END c06s05b00x00p05n02i01146ent;
+
+ARCHITECTURE c06s05b00x00p05n02i01146arch OF c06s05b00x00p05n02i01146ent IS
+
+BEGIN
+  TESTING: PROCESS
+    TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+    SUBTYPE A6 IS A (1 TO 6);
+    SUBTYPE A8 IS A (1 TO 8);
+    FUNCTION func1 RETURN A6 IS
+    BEGIN
+      RETURN (1,2,3,4,5,6);
+    END;
+    VARIABLE ReturnValue : A8;
+  BEGIN
+    ReturnValue := func1(1 TO 8);
+    assert FALSE 
+      report "***FAILED TEST: c06s05b00x00p05n02i01146 - The bounds of the discrete range does not belong to the index range of the prefixing array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s05b00x00p05n02i01146arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1160.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1160.vhd
new file mode 100644
index 0000000..1264737
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1160.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1160.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01160ent IS
+END c06s06b00x00p02n01i01160ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01160arch OF c06s06b00x00p02n01i01160ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type I1 is range 1 to 3;
+    type A1 is array (I1) of BOOLEAN;
+  BEGIN
+    if (1|2|3=>TRUE)'LOW = 1 then
+      -- SYNTAX ERROR: AGGREGATE NOT ALLOWED AS PREFIX OF
+      -- ATTRIBUTE NAME
+      -- return;
+      null ;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: /c06s06b00x00p02n01i01160 - Prefix of an attribute name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01160arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1161.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1161.vhd
new file mode 100644
index 0000000..c464ca2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1161.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1161.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01161ent IS
+END c06s06b00x00p02n01i01161ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01161arch OF c06s06b00x00p02n01i01161ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type I1 is range 1 to 3;
+    type A1 is array (I1) of BOOLEAN;
+  BEGIN
+    if (A1'(1|2|3=>TRUE))'LOW = 1 then
+      -- SYNTAX ERROR: AGGREGATE NOT ALLOWED AS PREFIX OF
+      -- ATTRIBUTE NAME
+      -- return;
+      null ;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c06s06b00x00p02n01i01161 - Prefix of an attribute name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01161arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1162.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1162.vhd
new file mode 100644
index 0000000..259c7db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1162.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1162.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01162ent IS
+END c06s06b00x00p02n01i01162ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01162arch OF c06s06b00x00p02n01i01162ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type I1 is range 1 to 3;
+    type A1 is array (I1) of BOOLEAN;
+  BEGIN
+    if (1|2|3=>TRUE)'RIGHT = 3 then
+      -- SYNTAX ERROR: AGGREGATE NOT ALLOWED AS PREFIX OF
+      -- ATTRIBUTE NAME
+      -- return;
+      null ;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c06s06b00x00p02n01i01162 - Prefix of an attribute name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01162arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1163.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1163.vhd
new file mode 100644
index 0000000..c5c8db8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1163.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1163.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p02n01i01163ent IS
+END c06s06b00x00p02n01i01163ent;
+
+ARCHITECTURE c06s06b00x00p02n01i01163arch OF c06s06b00x00p02n01i01163ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type I1 is range 1 to 3;
+    type A1 is array (I1) of BOOLEAN;
+  BEGIN
+    if (A1'(1|2|3=>TRUE))'RIGHT = 3 then
+      -- SYNTAX ERROR: AGGREGATE NOT ALLOWED AS PREFIX OF
+      -- ATTRIBUTE NAME
+      -- return;
+      null ;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c06s06b00x00p02n01i01163 - Prefix of an attribute name cannot be an aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p02n01i01163arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1168.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1168.vhd
new file mode 100644
index 0000000..f2495b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1168.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1168.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p06n01i01168ent IS
+END c06s06b00x00p06n01i01168ent;
+
+ARCHITECTURE c06s06b00x00p06n01i01168arch OF c06s06b00x00p06n01i01168ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type II is range 1    to 1000;
+    type RR is range 0.0001 to 10000.01;
+    function F1 (A:II;B:RR) return BOOLEAN is
+      variable G1 : II;
+      variable G2 : RR;
+    begin
+      if (G1'HIGH(A) <= 0) then   -- ERROR: attribute does not have a
+                                          -- generic expression assoc. with it.
+        return FALSE;
+      end if;
+    end F1;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s06b00x00p06n01i01168 - Arrtribute does not have generic expression associated with it."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p06n01i01168arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1169.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1169.vhd
new file mode 100644
index 0000000..d2fbf40
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1169.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1169.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p06n01i01169ent IS
+END c06s06b00x00p06n01i01169ent;
+
+ARCHITECTURE c06s06b00x00p06n01i01169arch OF c06s06b00x00p06n01i01169ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type II is range 1 to 1000;
+    type RR is range 0.0001 to 10000.01;
+    function F1 (A:II;B:RR) return BOOLEAN is
+      variable G1 : II;
+      variable G2 : RR;
+    begin
+      if (G2'LOW(B) /= 0.0) then  -- ERROR: attribute does not have a
+        -- generic expression assoc. with it.
+        return FALSE;
+      end if;
+    end F1;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s06b00x00p06n01i01169 - Arrtribute does not have generic expression associated with it."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p06n01i01169arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1170.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1170.vhd
new file mode 100644
index 0000000..a626c26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1170.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1170.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p06n01i01170ent IS
+END c06s06b00x00p06n01i01170ent;
+
+ARCHITECTURE c06s06b00x00p06n01i01170arch OF c06s06b00x00p06n01i01170ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type II is range 1 to 1000;
+    type RR is range 0.0001 to 10000.01;
+    function F1 (A:II;B:RR) return BOOLEAN is
+      variable G1 : II;
+      variable G2 : RR;
+    begin
+      if (A'LEFT(0) /= 0) then  -- ERROR: attribute does not have a
+                                        -- generic expression assoc. with it.
+        return FALSE;
+      end if;
+    end F1;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s06b00x00p06n01i01170 - Arrtribute does not have generic expression associated with it."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p06n01i01170arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1171.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1171.vhd
new file mode 100644
index 0000000..d9df727
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1171.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1171.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p06n01i01171ent IS
+END c06s06b00x00p06n01i01171ent;
+
+ARCHITECTURE c06s06b00x00p06n01i01171arch OF c06s06b00x00p06n01i01171ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type II is range 1 to 1000;
+    type RR is range 0.0001 to 10000.01;
+    function F1 (A:II;B:RR) return BOOLEAN is
+      variable G1 : II;
+      variable G2 : RR;
+    begin
+      if (B'RIGHT(0.0) /= 0.0) then  -- ERROR: attribute does not have a
+                                             -- generic expression assoc.
+                                             -- with it.
+        return FALSE;
+      end if;
+    end F1;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s06b00x00p06n01i01171 - Arrtribute does not have generic expression associated with it."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p06n01i01171arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1172.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1172.vhd
new file mode 100644
index 0000000..cba73fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1172.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1172.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p06n01i01172ent IS
+END c06s06b00x00p06n01i01172ent;
+
+ARCHITECTURE c06s06b00x00p06n01i01172arch OF c06s06b00x00p06n01i01172ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type II is range 1 to 1000;
+    type RR is range 0.0001 to 10000.01;
+    function F1 (A:II;B:RR) return BOOLEAN is
+      variable G1 : II;
+      variable G2 : RR;
+    begin
+      if (A'BASE'LEFT(B) /= 11) then  -- ERROR: attribute does not have a
+                                              -- generic expression assoc.
+                                              -- with it
+        return FALSE;
+      end if;
+    end F1;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s06b00x00p06n01i01172 - Arrtribute does not have generic expression associated with it."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p06n01i01172arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1173.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1173.vhd
new file mode 100644
index 0000000..c76b99e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1173.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1173.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s06b00x00p06n01i01173ent IS
+END c06s06b00x00p06n01i01173ent;
+
+ARCHITECTURE c06s06b00x00p06n01i01173arch OF c06s06b00x00p06n01i01173ent IS
+  signal    POS : Integer;
+  attribute PIO : positive;
+  attribute PIO of POS : signal is 10; -- No_failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if (POS'PIO(1) = 10)  then  -- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c06s06b00x00p06n01i01173 - Static expression must not be present." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s06b00x00p06n01i01173arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1181.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1181.vhd
new file mode 100644
index 0000000..76d65b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1181.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1181.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s00b00x00p02n01i01181ent IS
+END c08s00b00x00p02n01i01181ent;
+
+ARCHITECTURE c08s00b00x00p02n01i01181arch OF c08s00b00x00p02n01i01181ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 5;
+    variable p : integer := 3;
+  BEGIN
+    if (k > p) generate
+    end generate;
+  end if;
+  assert FALSE 
+    report "***FAILED TEST: c08s00b00x00p02n01i01181 - Concurrent statement are not permitted within sequence of statements." 
+    severity ERROR;
+  wait;
+END PROCESS TESTING;
+
+END c08s00b00x00p02n01i01181arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1184.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1184.vhd
new file mode 100644
index 0000000..615f6f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1184.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1184.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p02n01i01184ent IS
+END c08s01b00x00p02n01i01184ent;
+
+ARCHITECTURE c08s01b00x00p02n01i01184arch OF c08s01b00x00p02n01i01184ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 0;
+    variable j : integer := 0;
+  BEGIN
+    wait until (j = 1) on i;
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p02n01i01184 - Condition clause before sensitivity clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p02n01i01184arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1185.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1185.vhd
new file mode 100644
index 0000000..f72ccd5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1185.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1185.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p02n01i01185ent IS
+END c08s01b00x00p02n01i01185ent;
+
+ARCHITECTURE c08s01b00x00p02n01i01185arch OF c08s01b00x00p02n01i01185ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 0;
+  BEGIN
+    wait for 60 ns on i;
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p02n01i01185 - Timeout clause before sensitivity clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p02n01i01185arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1186.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1186.vhd
new file mode 100644
index 0000000..58c8106
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1186.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1186.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p02n01i01186ent IS
+END c08s01b00x00p02n01i01186ent;
+
+ARCHITECTURE c08s01b00x00p02n01i01186arch OF c08s01b00x00p02n01i01186ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    wait for 60 ns until (k = 1);
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p02n01i01186 - Timeout clause before condition clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p02n01i01186arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1188.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1188.vhd
new file mode 100644
index 0000000..56f8229
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1188.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1188.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p03n01i01188ent IS
+END c08s01b00x00p03n01i01188ent;
+
+ARCHITECTURE c08s01b00x00p03n01i01188arch OF c08s01b00x00p03n01i01188ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;   
+    wait on ;
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p03n01i01188 - Sensitivity list is missed form wait on clause." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p03n01i01188arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1189.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1189.vhd
new file mode 100644
index 0000000..1cc46da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1189.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1189.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p03n01i01189ent IS
+END c08s01b00x00p03n01i01189ent;
+
+ARCHITECTURE c08s01b00x00p03n01i01189arch OF c08s01b00x00p03n01i01189ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;   
+    wait on ii;
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p03n01i01189 - Undefined signal in sensitivity list." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p03n01i01189arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1190.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1190.vhd
new file mode 100644
index 0000000..af43820
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1190.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1190.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p03n01i01190ent IS
+END c08s01b00x00p03n01i01190ent;
+
+ARCHITECTURE c08s01b00x00p03n01i01190arch OF c08s01b00x00p03n01i01190ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    variable ii : integer;
+  BEGIN
+    k <= 5 after 5 ns;   
+    wait on ii;
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p03n01i01190 - Variable in sensitivity list." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p03n01i01190arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1191.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1191.vhd
new file mode 100644
index 0000000..302e7b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1191.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1191.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p03n01i01191ent IS
+  port (signal I : in  Bit;
+        signal O : out Bit);
+END c08s01b00x00p03n01i01191ent;
+
+ARCHITECTURE c08s01b00x00p03n01i01191arch OF c08s01b00x00p03n01i01191ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;   
+    wait on O;
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p03n01i01191 - Output port in sensitivity list." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p03n01i01191arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1193.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1193.vhd
new file mode 100644
index 0000000..ba694f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1193.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1193.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p05n01i01193ent IS
+END c08s01b00x00p05n01i01193ent;
+
+ARCHITECTURE c08s01b00x00p05n01i01193arch OF c08s01b00x00p05n01i01193ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;
+    wait no k;
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p05n01i01193 - Reserved word 'on' is misspelled"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p05n01i01193arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1194.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1194.vhd
new file mode 100644
index 0000000..848e8b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1194.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1194.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p05n01i01194ent IS
+END c08s01b00x00p05n01i01194ent;
+
+ARCHITECTURE c08s01b00x00p05n01i01194arch OF c08s01b00x00p05n01i01194ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;
+    wait on k untli (k = 5);
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p05n01i01194 - Reserved word 'until' is misspelled"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p05n01i01194arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1195.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1195.vhd
new file mode 100644
index 0000000..994927b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1195.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1195.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p05n01i01195ent IS
+END c08s01b00x00p05n01i01195ent;
+
+ARCHITECTURE c08s01b00x00p05n01i01195arch OF c08s01b00x00p05n01i01195ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;
+    wait on k until (k = 5) rof 60 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p05n01i01195 - Reserved word 'for' is misspelled"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p05n01i01195arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1196.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1196.vhd
new file mode 100644
index 0000000..09c538f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1196.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1196.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p05n01i01196ent IS
+END c08s01b00x00p05n01i01196ent;
+
+ARCHITECTURE c08s01b00x00p05n01i01196arch OF c08s01b00x00p05n01i01196ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    variable j : integer := 0;
+  BEGIN
+    k <= 5 after 5 ns;
+    j := 5;
+    wait until j; 
+    assert FALSE
+      report "***FAILED TEST: c08s01b00x00p05n01i01196 - Reserved word 'until' must be followed by a boolean expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p05n01i01196arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1198.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1198.vhd
new file mode 100644
index 0000000..8eb3861
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1198.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1198.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p05n01i01198ent IS
+END c08s01b00x00p05n01i01198ent;
+
+ARCHITECTURE c08s01b00x00p05n01i01198arch OF c08s01b00x00p05n01i01198ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;
+    wait until 5; 
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p05n01i01198 - Condition clause in wait statement must be boolean expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p05n01i01198arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc12.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc12.vhd
new file mode 100644
index 0000000..2bed28f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc12.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc12.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p02n01i00012ent IS
+END c04s02b00x00p02n01i00012ent;
+
+ARCHITECTURE c04s02b00x00p02n01i00012arch OF c04s02b00x00p02n01i00012ent IS
+  
+  --reserved word misspelled
+  subtyp GROUND is BIT range '0' to '0';
+  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s02b00x00p02n01i00012 - The reserved word is misspelled." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p02n01i00012arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc120.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc120.vhd
new file mode 100644
index 0000000..23e67aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc120.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc120.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n15i00120ent IS
+  port (   lpt1 : linkage BIT;
+           lpt2 : linkage BIT;
+           lpt3 : linkage BIT;
+           lpt4 : linkage BIT;
+           lpt5 : linkage BIT;
+           lpt6 : linkage BIT) ;
+END c04s03b02x00p29n15i00120ent;
+
+ARCHITECTURE c04s03b02x00p29n15i00120arch OF c04s03b02x00p29n15i00120ent IS
+  signal   S1 : BIT;
+BEGIN
+
+  S1 <= lpt1;  -- Failure_here
+  -- ERROR: Interface elements of mode linkage may not be read except
+  -- by association with formal linkage ports of subcomponents.
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x00p29n15i00120 - Reading and updating are not permitted on this mode."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n15i00120arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1200.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1200.vhd
new file mode 100644
index 0000000..8acf047
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1200.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1200.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p07n01i01200ent IS
+END c08s01b00x00p07n01i01200ent;
+
+ARCHITECTURE c08s01b00x00p07n01i01200arch OF c08s01b00x00p07n01i01200ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    variable j : integer := 0;
+  BEGIN
+    k <= 5 after 5 ns;
+    j := 5;
+    wait for j;
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p07n01i01200 - Time expression is missing in the timeout expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p07n01i01200arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1201.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1201.vhd
new file mode 100644
index 0000000..33641df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1201.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1201.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p07n01i01201ent IS
+END c08s01b00x00p07n01i01201ent;
+
+ARCHITECTURE c08s01b00x00p07n01i01201arch OF c08s01b00x00p07n01i01201ent IS
+  signal k : integer := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= 5 after 5 ns;
+    wait for TRUE;
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p07n01i01201 - Timeout clause must use a time expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p07n01i01201arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1202.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1202.vhd
new file mode 100644
index 0000000..9598065
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1202.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1202.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p08n03i01202ent IS
+END c08s01b00x00p08n03i01202ent;
+
+ARCHITECTURE c08s01b00x00p08n03i01202arch OF c08s01b00x00p08n03i01202ent IS
+  signal A : bit_vector (10 to 13) := B"0101";
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 11;
+  BEGIN
+    wait on A(k);
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p08n03i01202 - Signal name in the ON expression is not static."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p08n03i01202arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1203.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1203.vhd
new file mode 100644
index 0000000..a9b24bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1203.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1203.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p08n03i01203ent IS
+END c08s01b00x00p08n03i01203ent;
+
+ARCHITECTURE c08s01b00x00p08n03i01203arch OF c08s01b00x00p08n03i01203ent IS
+  type   SWORD is ARRAY(0 to 31) of integer;
+  signal   Res   : SWORD;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer;
+  BEGIN
+    for k in 0 to 31 loop
+      wait on Res(k);
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p08n03i01203 - Signal name in the ON expression is not static."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p08n03i01203arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1204.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1204.vhd
new file mode 100644
index 0000000..3869e08
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1204.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1204.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p08n03i01204ent IS
+  port ( signal O : out BIT );
+END c08s01b00x00p08n03i01204ent;
+
+ARCHITECTURE c08s01b00x00p08n03i01204arch OF c08s01b00x00p08n03i01204ent IS
+BEGIN
+  TESTING: PROCESS
+    variable k : integer;
+  BEGIN
+    O <= '1';
+    wait on O;
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p08n03i01204 - Signal name in the ON expression is not static."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p08n03i01204arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc121.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc121.vhd
new file mode 100644
index 0000000..720675a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc121.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc121.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n15i00121ent_a IS
+  port (   cpt1 : in      BIT;
+           cpt2 : inout   BIT;
+           cpt3 : out     BIT;
+           cpt4 : buffer  BIT;
+           cpt5 : linkage BIT);
+END c04s03b02x00p29n15i00121ent_a;
+
+ARCHITECTURE c04s03b02x00p29n15i00121arch_a OF c04s03b02x00p29n15i00121ent_a IS
+BEGIN
+END c04s03b02x00p29n15i00121arch_a;
+
+
+
+
+ENTITY c04s03b02x00p29n15i00121ent IS
+  port (   lpt1 : linkage BIT;
+           lpt2 : linkage BIT;
+           lpt3 : linkage BIT;
+           lpt4 : linkage BIT;
+           lpt5 : linkage BIT;
+           lpt6 : linkage BIT) ;
+END c04s03b02x00p29n15i00121ent;
+
+ARCHITECTURE c04s03b02x00p29n15i00121arch OF c04s03b02x00p29n15i00121ent IS
+  component com1 
+    port (   cpt1 : in      BIT;
+             cpt2 : inout   BIT;
+             cpt3 : out     BIT;
+             cpt4 : buffer  BIT;
+             cpt5 : linkage BIT);
+  end component;
+  for CIS : com1 use entity work.ch040302_p03401_03_01_ent_a(ch040302_p03401_03_01_arch_a);
+BEGIN
+  CIS : com1 port map (cpt1 => lpt2, -- in formal  -- Failure_here
+                       -- ERROR: Interface elements of mode linkage may not be read except
+                       -- by association with formal linkage ports of subcomponents.
+                       
+                       cpt2 => lpt3, -- inout formal  -- Failure_here
+                       -- ERROR: Interface elements of mode linkage may not be read except
+                       -- by association with formal linkage ports of subcomponents.
+                       
+                       cpt3 => lpt4, -- out formal  -- Failure_here
+                       -- ERROR: Interface elements of mode linkage may not be read except
+                       -- by association with formal linkage ports of subcomponents.
+                       
+                       cpt4 => lpt5, -- buffer formal  -- Failure_here
+                       -- ERROR: Interface elements of mode linkage may not be read except
+                       -- by association with formal linkage ports of subcomponents.
+                       
+                       cpt5 => lpt6);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x00p29n15i00121 - Reading and updating are not permitted on this mode."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n15i00121arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1217.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1217.vhd
new file mode 100644
index 0000000..cc669c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1217.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1217.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p26n03i01217ent IS
+END c08s01b00x00p26n03i01217ent;
+
+ARCHITECTURE c08s01b00x00p26n03i01217arch OF c08s01b00x00p26n03i01217ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant t1 : time := 10 ns;
+    constant t2 : time := 20 ns;
+  BEGIN
+    wait for (t1 - t2);
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p26n03i01217 - The FOR clause in a WAIT statement must evaluate to a positive value."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p26n03i01217arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1219.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1219.vhd
new file mode 100644
index 0000000..57bd945
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1219.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1219.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p26n03i01219ent IS
+END c08s01b00x00p26n03i01219ent;
+
+ARCHITECTURE c08s01b00x00p26n03i01219arch OF c08s01b00x00p26n03i01219ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    --
+    -- The following wait statement is illegal; time
+    -- expressions may not be negative. This test is
+    -- based on 32 bit time values.
+    --
+    wait for x"FFFFFFFE";     -- illegal time expression (-1 ?)
+
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p26n03i01219 - Negative time expression accepted in a wait statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p26n03i01219arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc122.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc122.vhd
new file mode 100644
index 0000000..4d2570d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc122.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc122.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n15i00122ent IS
+  port (PT: linkage BOOLEAN);
+END c04s03b02x00p29n15i00122ent;
+
+ARCHITECTURE c04s03b02x00p29n15i00122arch OF c04s03b02x00p29n15i00122ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    Variable I2 : BOOLEAN;
+  BEGIN
+    I2 := PT'STABLE;   -- Failure_here
+    -- ERROR: ATTRIBUTES OF INTERFACE ELEMENTS OF MODE LINKAGE CANNOT BE READ
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x00p29n15i00122 - Attributes of interface elements of mode linkage can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n15i00122arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1226.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1226.vhd
new file mode 100644
index 0000000..ad93d17
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1226.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1226.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p29n01i01226ent IS
+END c08s01b00x00p29n01i01226ent;
+
+ARCHITECTURE c08s01b00x00p29n01i01226arch OF c08s01b00x00p29n01i01226ent IS
+BEGIN
+  TESTING: PROCESS
+    function test_1 (a:integer; b:boolean) return integer is
+      variable c : integer := 1;
+    begin
+      wait for 100 ns;
+      return c;
+    end;
+    variable k : integer := 0;
+    variable y : boolean := false;
+    variable i : integer;
+  BEGIN
+    i := test_1 (a=>k, b=>y);
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p29n01i01226 - Wait not allowed in a function subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p29n01i01226arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1228.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1228.vhd
new file mode 100644
index 0000000..ddf7346
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1228.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1228.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p29n02i01228ent IS
+  port(s1, s2 : bit);
+END c08s01b00x00p29n02i01228ent;
+
+ARCHITECTURE c08s01b00x00p29n02i01228arch OF c08s01b00x00p29n02i01228ent IS
+
+BEGIN
+  TESTING: PROCESS(s1,s2)
+  BEGIN
+    wait on s1, s2;
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p29n02i01228 - Wait not allowed in a process with a sensitivity list"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p29n02i01228arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1229.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1229.vhd
new file mode 100644
index 0000000..1e4bfaa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1229.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1229.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p29n02i01229ent IS
+  port(p : bit);
+  EEND c08s01b00x00p29n02i01229ent;
+
+  ARCHITECTURE c08s01b00x00p29n02i01229arch OF c08s01b00x00p29n02i01229ent IS
+
+  BEGIN
+    TESTING: PROCESS(p)
+      procedure test_1 (a :integer; b: boolean; c : out integer) is
+    begin
+      if b then c := a + 1;
+      end if;
+      wait for 1 ns;
+    end;
+    variable x : integer := 2;
+    variable y : boolean := False;
+    variable i : integer;
+    BEGIN
+      test_1 (a => x, b => y, c => i);   
+      assert FALSE
+        report "***FAILED TEST: c08s01b00x00p29n02i01229 - Wait not allowed in a procedure with process as parent." 
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c08s01b00x00p29n02i01229arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc123.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc123.vhd
new file mode 100644
index 0000000..6fe8cac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc123.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc123.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n15i00123ent IS
+  port (PT: linkage BOOLEAN);
+END c04s03b02x00p29n15i00123ent;
+
+ARCHITECTURE c04s03b02x00p29n15i00123arch OF c04s03b02x00p29n15i00123ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    Variable I2 : BOOLEAN;
+  BEGIN
+    I2 := PT'QUIET;      -- Failure_here
+    -- ERROR: ATTRIBUTES OF INTERFACE ELEMENTS OF MODE LINKAGE CANNOT BE READ
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x00p29n15i00123 - Attributes of interface elements of mode linkage can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n15i00123arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1231.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1231.vhd
new file mode 100644
index 0000000..c2a5de9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1231.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1231.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01231ent IS
+END c08s02b00x00p03n01i01231ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01231arch OF c08s02b00x00p03n01i01231ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert 1
+      report "Report this Note"
+      severity Note;   
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p03n01i01231 - condition in an assertion statement must be BOOLEAN type"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01231arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1235.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1235.vhd
new file mode 100644
index 0000000..90dd7da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1235.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1235.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01235ent IS
+END c08s02b00x00p03n01i01235ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01235arch OF c08s02b00x00p03n01i01235ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    erlab : assert FALSE;
+    severity NOTE;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p03n01i01235 - Labels are not permitted on sequential assertion statements." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01235arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1236.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1236.vhd
new file mode 100644
index 0000000..749139b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1236.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1236.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01236ent IS
+END c08s02b00x00p03n01i01236ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01236arch OF c08s02b00x00p03n01i01236ent IS
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 5;
+  BEGIN
+    assert k;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p03n01i01236 - The condition in the assert statement is not of type boolean" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01236arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1237.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1237.vhd
new file mode 100644
index 0000000..0987cc1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1237.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1237.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01237ent IS
+END c08s02b00x00p03n01i01237ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01237arch OF c08s02b00x00p03n01i01237ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real;
+  BEGIN
+    assert k;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p03n01i01237 - The condition in the assert statement is not of type boolean" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01237arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1238.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1238.vhd
new file mode 100644
index 0000000..9cda4ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1238.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1238.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01238ent IS
+END c08s02b00x00p03n01i01238ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01238arch OF c08s02b00x00p03n01i01238ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : BIT;
+  BEGIN
+    assert k;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p03n01i01238 - The condition in the assert statement is not of type boolean" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01238arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1239.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1239.vhd
new file mode 100644
index 0000000..bb5ba55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1239.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1239.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01239ent IS
+END c08s02b00x00p03n01i01239ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01239arch OF c08s02b00x00p03n01i01239ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : SEVERITY_LEVEL;
+  BEGIN
+    assert k;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p03n01i01239 - The condition in the assert statement is not of type boolean" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01239arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc124.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc124.vhd
new file mode 100644
index 0000000..3d3ec84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc124.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc124.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n15i00124ent IS
+  port (PT: linkage BOOLEAN);
+END c04s03b02x00p29n15i00124ent;
+
+ARCHITECTURE c04s03b02x00p29n15i00124arch OF c04s03b02x00p29n15i00124ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    Variable I2 : BOOLEAN;
+  BEGIN
+    I2 := PT'LAST_VALUE;      -- Failure_here
+    -- ERROR: ATTRIBUTES OF INTERFACE ELEMENTS OF MODE LINKAGE CANNOT BE READ
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x00p29n15i00124 - Attributes of interface elements of mode linkage can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n15i00124arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1240.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1240.vhd
new file mode 100644
index 0000000..61f613e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1240.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1240.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01240ent IS
+END c08s02b00x00p03n01i01240ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01240arch OF c08s02b00x00p03n01i01240ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     BYTE_T is array (1 to 8) of BIT;
+    variable k : BYTE_T;
+  BEGIN
+    assert k;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p03n01i01240 - The condition in the assert statement is not of type boolean" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01240arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1241.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1241.vhd
new file mode 100644
index 0000000..d2d3ed6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1241.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1241.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p03n01i01241ent IS
+END c08s02b00x00p03n01i01241ent;
+
+ARCHITECTURE c08s02b00x00p03n01i01241arch OF c08s02b00x00p03n01i01241ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert TRUE
+      severity WARNING
+      report "This should not get through";
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p03n01i01241 - The severity clause of an assert statement can not precede the report" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p03n01i01241arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1242.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1242.vhd
new file mode 100644
index 0000000..f37cdba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1242.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1242.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n01i01242ent IS
+END c08s02b00x00p04n01i01242ent;
+
+ARCHITECTURE c08s02b00x00p04n01i01242arch OF c08s02b00x00p04n01i01242ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant N2 : Character := 'R';
+  BEGIN
+
+    assert FALSE 
+      report N2 
+      severity NOTE;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n01i01242 - Expression type used in a report clause should be STRING"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n01i01242arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1243.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1243.vhd
new file mode 100644
index 0000000..8734a14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1243.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1243.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n01i01243ent IS
+END c08s02b00x00p04n01i01243ent;
+
+ARCHITECTURE c08s02b00x00p04n01i01243arch OF c08s02b00x00p04n01i01243ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable N2 : Character := 'R';
+  BEGIN
+
+    assert FALSE 
+      report N2 
+      severity NOTE;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n01i01243 - Expression type used in a report clause should be STRING"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n01i01243arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1244.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1244.vhd
new file mode 100644
index 0000000..06a0dc1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1244.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1244.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n01i01244ent IS
+END c08s02b00x00p04n01i01244ent;
+
+ARCHITECTURE c08s02b00x00p04n01i01244arch OF c08s02b00x00p04n01i01244ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable N2 : integer; 
+  BEGIN
+
+    assert FALSE 
+      report N2 
+      severity NOTE;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n01i01244 - Expression type used in a report clause should be STRING"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n01i01244arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1245.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1245.vhd
new file mode 100644
index 0000000..fa1c066
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1245.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1245.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n01i01245ent IS
+END c08s02b00x00p04n01i01245ent;
+
+ARCHITECTURE c08s02b00x00p04n01i01245arch OF c08s02b00x00p04n01i01245ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable N2 : real; 
+  BEGIN
+
+    assert FALSE 
+      report N2 
+      severity NOTE;
+    assert FALSE 
+      report "***FAILED TEST:c08s02b00x00p04n01i01245 - Expression type used in a report clause should be STRING"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n01i01245arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1246.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1246.vhd
new file mode 100644
index 0000000..89a9d85
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1246.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1246.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n01i01246ent IS
+END c08s02b00x00p04n01i01246ent;
+
+ARCHITECTURE c08s02b00x00p04n01i01246arch OF c08s02b00x00p04n01i01246ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable N2 : BIT; 
+  BEGIN
+
+    assert FALSE 
+      report N2 
+      severity NOTE;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n01i01246 - Expression type used in a report clause should be STRING"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n01i01246arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1247.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1247.vhd
new file mode 100644
index 0000000..ec90e71
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1247.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1247.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n01i01247ent IS
+END c08s02b00x00p04n01i01247ent;
+
+ARCHITECTURE c08s02b00x00p04n01i01247arch OF c08s02b00x00p04n01i01247ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable N2 : SEVERITY_LEVEL; 
+  BEGIN
+
+    assert FALSE 
+      report N2 
+      severity NOTE;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n01i01247 - Expression type used in a report clause should be STRING"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n01i01247arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1248.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1248.vhd
new file mode 100644
index 0000000..ea59d41
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1248.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1248.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n01i01248ent IS
+END c08s02b00x00p04n01i01248ent;
+
+ARCHITECTURE c08s02b00x00p04n01i01248arch OF c08s02b00x00p04n01i01248ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BYTE_T is array (1 to 8) of BIT;
+    variable N2 : BYTE_T; 
+  BEGIN
+
+    assert FALSE 
+      report N2 
+      severity NOTE;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n01i01248 - Expression type used in a report clause should be STRING"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n01i01248arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1249.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1249.vhd
new file mode 100644
index 0000000..ac49354
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1249.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1249.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01249ent IS
+END c08s02b00x00p04n02i01249ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01249arch OF c08s02b00x00p04n02i01249ent IS
+
+  type SEVERITY_LEVEL is (ONE, TWO, THREE);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE
+      report "Report this string"
+      severity ONE;   
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n02i01249 - Severity clause must specify an expression of predifined type SEVERITY_LEVEL."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01249arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc125.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc125.vhd
new file mode 100644
index 0000000..4ec3463
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc125.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc125.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n15i00125ent IS
+  port (PT: linkage BOOLEAN);
+END c04s03b02x00p29n15i00125ent;
+
+ARCHITECTURE c04s03b02x00p29n15i00125arch OF c04s03b02x00p29n15i00125ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    Variable I2 : BOOLEAN;
+  BEGIN
+    I2 := PT'DELAYED;      -- Failure_here
+    -- ERROR: ATTRIBUTES OF INTERFACE ELEMENTS OF MODE LINKAGE CANNOT BE READ
+    assert FALSE
+      report "***FAILED TEST:c04s03b02x00p29n15i00125 - Attributes of interface elements of mode linkage can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n15i00125arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1250.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1250.vhd
new file mode 100644
index 0000000..1a5b47c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1250.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1250.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01250ent IS
+END c08s02b00x00p04n02i01250ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01250arch OF c08s02b00x00p04n02i01250ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE
+      severity 3.0;   
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n02i01250 - Static expression must be of type SEVERITY_LEVEL" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01250_arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1251.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1251.vhd
new file mode 100644
index 0000000..2183016
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1251.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1251.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01251ent IS
+END c08s02b00x00p04n02i01251ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01251arch OF c08s02b00x00p04n02i01251ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE
+      report "Report this Note"
+      severity fatal;   
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n02i01251 - Predefined severity_level type with non-existent value" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01251arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1252.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1252.vhd
new file mode 100644
index 0000000..1c5400e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1252.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1252.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01252ent IS
+END c08s02b00x00p04n02i01252ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01252arch OF c08s02b00x00p04n02i01252ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer;
+  BEGIN
+
+    assert FALSE
+      report "Report this Note"
+      severity k;   
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n02i01252 - Predefined severity_level type with non-existent value" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01252arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1253.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1253.vhd
new file mode 100644
index 0000000..425b22e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1253.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1253.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01253ent IS
+END c08s02b00x00p04n02i01253ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01253arch OF c08s02b00x00p04n02i01253ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : real;
+  BEGIN
+
+    assert FALSE
+      report "Report this Note"
+      severity k;   
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n02i01253 - Predefined severity_level type with non-existent value" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01253arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1254.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1254.vhd
new file mode 100644
index 0000000..defcc9d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1254.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1254.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01254ent IS
+END c08s02b00x00p04n02i01254ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01254arch OF c08s02b00x00p04n02i01254ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : BIT;
+  BEGIN
+
+    assert FALSE
+      report "Report this Note"
+      severity k;   
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n02i01254 - Predefined severity_level type with non-existent value" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01254arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1255.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1255.vhd
new file mode 100644
index 0000000..ff72daf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1255.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1255.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p04n02i01255ent IS
+END c08s02b00x00p04n02i01255ent;
+
+ARCHITECTURE c08s02b00x00p04n02i01255arch OF c08s02b00x00p04n02i01255ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BYTE_T is array(1 to 8) of BIT;
+    variable k : BYTE_T;
+  BEGIN
+
+    assert FALSE
+      report "Report this Note"
+      severity k;   
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p04n02i01255 - Predefined severity_level type with non-existent value" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p04n02i01255arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc126.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc126.vhd
new file mode 100644
index 0000000..b328521
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc126.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc126.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x01p02n01i00126ent IS
+  port ( ) ;  -- Failure_here
+  -- ERROR - empty port list
+END c04s03b02x01p02n01i00126ent;
+
+ARCHITECTURE c04s03b02x01p02n01i00126arch OF c04s03b02x01p02n01i00126ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x01p02n01i00126 - Port list can not be empty."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x01p02n01i00126arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1264.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1264.vhd
new file mode 100644
index 0000000..8761524
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1264.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1264.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s02b00x00p06n01i01264ent IS
+END c08s02b00x00p06n01i01264ent;
+
+ARCHITECTURE c08s02b00x00p06n01i01264arch OF c08s02b00x00p06n01i01264ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable B : BIT;
+  BEGIN
+
+    assert B;
+    assert FALSE 
+      report "***FAILED TEST: c08s02b00x00p06n01i01264 - Condition must be of Boolean type"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s02b00x00p06n01i01264arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc127.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc127.vhd
new file mode 100644
index 0000000..0293029
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc127.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc127.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x01p04n01i00127ent IS
+  generic ( signal c1 : in integer ) ; -- Failure_here
+                                         -- signal declaration
+                                         -- not allowed
+END c04s03b02x01p04n01i00127ent;
+
+ARCHITECTURE c04s03b02x01p04n01i00127arch OF c04s03b02x01p04n01i00127ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x01p04n01i00127 - Only constant declarations allowed in generic interface list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x01p04n01i00127arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1270.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1270.vhd
new file mode 100644
index 0000000..dc183bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1270.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1270.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p02n01i01270ent IS
+END c08s04b00x00p02n01i01270ent;
+
+ARCHITECTURE c08s04b00x00p02n01i01270arch OF c08s04b00x00p02n01i01270ent IS
+  signal T1 : integer;
+BEGIN
+  TESTING: PROCESS
+    variable a : integer := 5;
+  BEGIN
+    T1   :=   a; 
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p02n01i01270 - Invalid assignment made to signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p02n01i01270arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1271.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1271.vhd
new file mode 100644
index 0000000..f5825ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1271.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1271.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p02n01i01271ent IS
+END c08s04b00x00p02n01i01271ent;
+
+ARCHITECTURE c08s04b00x00p02n01i01271arch OF c08s04b00x00p02n01i01271ent IS
+  signal T1 : integer := 5;
+BEGIN
+  TESTING: PROCESS
+    subtype a is integer range 1 to 10;   
+  BEGIN
+    T1   <=   a; 
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p02n01i01271 - Invalid waveform assigned to signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p02n01i01271arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1272.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1272.vhd
new file mode 100644
index 0000000..fc99342
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1272.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1272.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p02n01i01272ent IS
+END c08s04b00x00p02n01i01272ent;
+
+ARCHITECTURE c08s04b00x00p02n01i01272arch OF c08s04b00x00p02n01i01272ent IS
+  signal T1 : integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    T1   <=   1 after 10 ns transport; 
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p02n01i01272 - Reserved word 'transport' is out of place" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p02n01i01272arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1273.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1273.vhd
new file mode 100644
index 0000000..3afb9e2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1273.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1273.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p02n01i01273ent IS
+END c08s04b00x00p02n01i01273ent;
+
+ARCHITECTURE c08s04b00x00p02n01i01273arch OF c08s04b00x00p02n01i01273ent IS
+  signal T1 : integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    unk   <=   transport 1 after 10 ns ; 
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p02n01i01273 - Signal name not found." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p02n01i01273arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1274.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1274.vhd
new file mode 100644
index 0000000..6d842fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1274.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1274.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01274ent IS
+END c08s04b00x00p04n01i01274ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01274arch OF c08s04b00x00p04n01i01274ent IS
+  signal b : integer := 5;
+BEGIN
+  TESTING: PROCESS
+    subtype a is integer range 1 to 10;
+  BEGIN
+    a := b;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01274 - Target of signal assignment statement is not a signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01274arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1275.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1275.vhd
new file mode 100644
index 0000000..24068b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1275.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1275.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01275ent IS
+END c08s04b00x00p04n01i01275ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01275arch OF c08s04b00x00p04n01i01275ent IS
+  signal S1,S2,S3 : integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 > S2   <= S3;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01275 - Relational expressions are not allowed on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01275arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1276.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1276.vhd
new file mode 100644
index 0000000..2bbb493
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1276.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1276.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01276ent IS
+END c08s04b00x00p04n01i01276ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01276arch OF c08s04b00x00p04n01i01276ent IS
+  signal S1,S2,S3 : integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 and S2   <= S3;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01276 - Logical expressions are not allowed on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01276arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1277.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1277.vhd
new file mode 100644
index 0000000..2b5531f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1277.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1277.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01277ent IS
+END c08s04b00x00p04n01i01277ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01277arch OF c08s04b00x00p04n01i01277ent IS
+  signal S1 : integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1**2   <= S1;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01277 - Simple expressions are not allowed on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01277arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1278.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1278.vhd
new file mode 100644
index 0000000..221d7f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1278.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1278.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01278ent IS
+END c08s04b00x00p04n01i01278ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01278arch OF c08s04b00x00p04n01i01278ent IS
+  signal S1 : integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    abs S1   <= S1;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01278 - Simple expressions are not allowed on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01278arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1279.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1279.vhd
new file mode 100644
index 0000000..6c5ad7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1279.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1279.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01279ent IS
+END c08s04b00x00p04n01i01279ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01279arch OF c08s04b00x00p04n01i01279ent IS
+  signal S1 : integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    5.2E1 <= S1;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01279 - Literal expressions are not allowed on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01279arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc128.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc128.vhd
new file mode 100644
index 0000000..c856e7c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc128.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc128.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x01p04n01i00128ent IS
+  generic ( variable c1 : in integer );-- Failure_here
+                                         -- variable declaration
+                                         -- not allowed
+END c04s03b02x01p04n01i00128ent;
+
+ARCHITECTURE c04s03b02x01p04n01i00128arch OF c04s03b02x01p04n01i00128ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x01p04n01i00128 - Only constant declarations allowed in generic interface list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x01p04n01i00128arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1280.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1280.vhd
new file mode 100644
index 0000000..73c1169
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1280.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1280.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01280ent IS
+END c08s04b00x00p04n01i01280ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01280arch OF c08s04b00x00p04n01i01280ent IS
+  type   ENUM_1 is (ONE,TWO,THREE);
+  signal S1 : integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    TWO - ONE <= S1;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01280 - Literal expressions are not allowed on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01280arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1281.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1281.vhd
new file mode 100644
index 0000000..35afb34
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1281.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1281.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01281ent IS
+END c08s04b00x00p04n01i01281ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01281arch OF c08s04b00x00p04n01i01281ent IS
+  signal S1 : integer ;
+BEGIN
+  Function FUN_1 return BOOLEAN is
+  begin
+    return FALSE;
+  end FUN_1;
+  TESTING: PROCESS
+  BEGIN
+    FUN_1 <= S1;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01281 - Function calls are not allowed on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01281arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1282.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1282.vhd
new file mode 100644
index 0000000..6f469e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1282.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1282.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01282ent IS
+END c08s04b00x00p04n01i01282ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01282arch OF c08s04b00x00p04n01i01282ent IS
+  type   INIT_1 is range 16#1# to 16#FF#;
+  signal S1 : integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    INIT_1(S1) <= S1;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01282 - Type Conversions are not allowed on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01282arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1283.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1283.vhd
new file mode 100644
index 0000000..2fa27d8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1283.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1283.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01283ent IS
+END c08s04b00x00p04n01i01283ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01283arch OF c08s04b00x00p04n01i01283ent IS
+  type   INIT_1 is (ONE, TWO, THREE); 
+  signal S1 : integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    INIT_1'(S1) <= S1;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01283 - Qualified expressions are not allowed on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01283arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1284.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1284.vhd
new file mode 100644
index 0000000..370c026
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1284.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1284.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01284ent IS
+  port (X : in BIT; COUT : out BIT);
+END c08s04b00x00p04n01i01284ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01284arch OF c08s04b00x00p04n01i01284ent IS
+  signal S1 : BIT; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X <= S1;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01284 - A port whose mode is "IN" or "LINKAGE" can not be on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01284arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1285.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1285.vhd
new file mode 100644
index 0000000..60fde4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1285.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1285.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01285ent IS
+  port (X : in BIT; Z : linkage BIT; COUT : out BIT);
+END c08s04b00x00p04n01i01285ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01285arch OF c08s04b00x00p04n01i01285ent IS
+  signal S1 : BIT; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Z <= S1;
+    wait for 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01285 - A port whose mode is "LINKAGE" can not be on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01285arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1286.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1286.vhd
new file mode 100644
index 0000000..766a07c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1286.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1286.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01286ent IS
+  port (X : in BIT_VECTOR; COUT : out BIT);
+  alias ALIAN_1 : BIT_VECTOR (1 to 10) is X (1 to 10);
+END c08s04b00x00p04n01i01286ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01286arch OF c08s04b00x00p04n01i01286ent IS
+  signal S1 : BIT; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ALIAN_1 <= S1;
+    wait for 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01286 - An alias for a port whose mode is "IN" can not be on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01286arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1287.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1287.vhd
new file mode 100644
index 0000000..73d70b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1287.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1287.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01287ent IS
+END c08s04b00x00p04n01i01287ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01287arch OF c08s04b00x00p04n01i01287ent IS
+  signal S1 : BIT; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    unk <= transport '1' after 10 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01287 - Target of signal assignment statement is not a signal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01287arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1288.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1288.vhd
new file mode 100644
index 0000000..54dd116
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1288.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1288.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01288ent IS
+  port (X : in BIT_VECTOR; Z : linkage BIT_VECTOR; COUT : out BIT);
+  alias ALIAN_2 : BIT_VECTOR (1 to 10) is Z (1 to 10);
+END c08s04b00x00p04n01i01288ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01288arch OF c08s04b00x00p04n01i01288ent IS
+  signal S1 : BIT; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ALIAN_2(10) <= S1;
+    wait for 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01288 - An alias for a port whose mode is "LINKAGE" can not be on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01288arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1289.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1289.vhd
new file mode 100644
index 0000000..de474b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1289.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1289.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01289ent IS
+  port (X : in BIT_VECTOR; COUT : out BIT);
+  alias ALIAN_1 : BIT_VECTOR (1 to 10) is X (1 to 10);
+END c08s04b00x00p04n01i01289ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01289arch OF c08s04b00x00p04n01i01289ent IS
+  signal S1 : BIT; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ALIAN_1(2) <= S1;
+    wait for 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01289 - An alias for a port whose mode is "IN" can not be on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01289arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc129.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc129.vhd
new file mode 100644
index 0000000..8cdab81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc129.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc129.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x01p04n02i00129ent IS
+END c04s03b02x01p04n02i00129ent;
+
+ARCHITECTURE c04s03b02x01p04n02i00129arch OF c04s03b02x01p04n02i00129ent IS
+  component A2 
+    port (constant PT2: INTEGER);  -- Failure_here
+    -- ERROR: the only object class allowed in a local port is signal.
+  end component ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x01p04n02i00129 - The only object class allowed is signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x01p04n02i00129arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1290.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1290.vhd
new file mode 100644
index 0000000..e54b163
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1290.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1290.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01290ent IS
+  port (X : in BIT; COUT : out BIT);
+END c08s04b00x00p04n01i01290ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01290arch OF c08s04b00x00p04n01i01290ent IS
+  signal S1 : BIT; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    X(2) <= S1;
+    wait for 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01290 - A port whose mode is "IN" can not be on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01290arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1291.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1291.vhd
new file mode 100644
index 0000000..8a269ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1291.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1291.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01291ent IS
+END c08s04b00x00p04n01i01291ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01291arch OF c08s04b00x00p04n01i01291ent IS
+  signal S1 : BIT; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    hr <= S1;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01291 - A unit name (of a physical literal) cannot be the name used on the left-hand side of a signal assignment"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01291arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1293.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1293.vhd
new file mode 100644
index 0000000..77e1056
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1293.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1293.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p05n01i01293ent IS
+END c08s04b00x00p05n01i01293ent;
+
+ARCHITECTURE c08s04b00x00p05n01i01293arch OF c08s04b00x00p05n01i01293ent IS
+  signal done : bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    done <= '1' after 10 ns,
+            '0' after 20 ns
+            '1' after 35 ns;
+    wait for 70 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p05n01i01293 - Waveform elements should be separated by commas."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p05n01i01293arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1295.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1295.vhd
new file mode 100644
index 0000000..9f4bd16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1295.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1295.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01295ent IS
+END c08s04b00x00p06n01i01295ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01295arch OF c08s04b00x00p06n01i01295ent IS
+  signal DID : bit; 
+BEGIN
+  TESTING: PROCESS
+    variable NUM1 : bit;
+  BEGIN
+    NUM1 <= DID;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p06n01i01295 - Signal assignment to variable is not allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01295arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1296.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1296.vhd
new file mode 100644
index 0000000..5ff79e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1296.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1296.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01296ent IS
+END c08s04b00x00p06n01i01296ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01296arch OF c08s04b00x00p06n01i01296ent IS
+  signal X1 : Bit;
+BEGIN
+  TESTING: PROCESS(X1)
+    variable NUM1 : Bit;
+  BEGIN
+    NUM1 <= X1;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p06n01i01296 - The target of a signal assignment can not be a variable." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01296arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1297.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1297.vhd
new file mode 100644
index 0000000..76785bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1297.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1297.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01297ent IS
+END c08s04b00x00p06n01i01297ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01297arch OF c08s04b00x00p06n01i01297ent IS
+  signal   X1 : BIT;
+  type    q  is ('0', '1');
+  signal  q1 : q := '0';
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    q1 <= X1;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p06n01i01297 - The waveform element assigned to a signal must be of the same base type as the signal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01297arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1298.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1298.vhd
new file mode 100644
index 0000000..584ce4e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1298.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1298.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01298ent IS
+END c08s04b00x00p06n01i01298ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01298arch OF c08s04b00x00p06n01i01298ent IS
+  signal   X : integer := 5;
+BEGIN
+  TESTING: PROCESS
+    subtype q is integer range 1 to 10;
+  BEGIN
+    q <= X;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p06n01i01298 - The target of a signal assignment must be a signal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01298arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc13.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc13.vhd
new file mode 100644
index 0000000..fe6dd23
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc13.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc13.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p02n01i00013ent IS
+END c04s02b00x00p02n01i00013ent;
+
+ARCHITECTURE c04s02b00x00p02n01i00013arch OF c04s02b00x00p02n01i00013ent IS
+  type       T1 is array (positive range <>) of Integer;
+  subtype    T2 is T1(2 to 10)     -- Missing semicolon 
+    
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s02b00x00p02n01i00013 - Missing semicolon." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p02n01i00013arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc130.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc130.vhd
new file mode 100644
index 0000000..271e5ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc130.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc130.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x01p04n02i00130ent IS
+END c04s03b02x01p04n02i00130ent;
+
+ARCHITECTURE c04s03b02x01p04n02i00130arch OF c04s03b02x01p04n02i00130ent IS
+  component A3 
+    port (variable PT3: BOOLEAN);  -- Failure_here
+    -- ERROR: the only object class allowed in a local port list is signal.
+  end component ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x01p04n02i00130 - The only object class allowed is signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x01p04n02i00130arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1300.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1300.vhd
new file mode 100644
index 0000000..5619ecc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1300.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1300.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s04b00x00p06n01i01300pkg is
+  function FUN_1 return TIME;
+end c08s04b00x00p06n01i01300pkg;
+
+package body c08s04b00x00p06n01i01300pkg is
+  function FUN_1 return TIME is
+  begin
+    return 1 min;
+  end FUN_1;
+end c08s04b00x00p06n01i01300pkg;
+
+ENTITY c08s04b00x00p06n01i01300ent IS
+END c08s04b00x00p06n01i01300ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01300arch OF c08s04b00x00p06n01i01300ent IS
+  signal   X : integer := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    c08s04b00x00p06n01i01300pkg <= X;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p06n01i01300 - Package name can not be used on left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01300arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1301.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1301.vhd
new file mode 100644
index 0000000..9f04bca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1301.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1301.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01301ent IS
+END c08s04b00x00p06n01i01301ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01301arch OF c08s04b00x00p06n01i01301ent IS
+  signal   X : integer := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ch0804_par00601_08_ent <= X;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p06n01i01301 - A desing entityname can not be used on left-hand side of a singal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01301arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1302.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1302.vhd
new file mode 100644
index 0000000..2205982
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1302.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1302.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01302ent IS
+END c08s04b00x00p06n01i01302ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01302arch OF c08s04b00x00p06n01i01302ent IS
+  signal   X : integer := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    ch0804_par00601_09_arch <= X;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p06n01i01302 - the name of a body declaration can not appear on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01302arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1303.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1303.vhd
new file mode 100644
index 0000000..babf30c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1303.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1303.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01303ent IS
+END c08s04b00x00p06n01i01303ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01303arch OF c08s04b00x00p06n01i01303ent IS
+  signal   X : integer := 5;
+  type    INIT_1 is range 1 to 1000;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    INIT_1 <= X;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p06n01i01303 - A type name can not used on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01303arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1304.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1304.vhd
new file mode 100644
index 0000000..3cdfd5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1304.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1304.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01304ent IS
+END c08s04b00x00p06n01i01304ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01304arch OF c08s04b00x00p06n01i01304ent IS
+  signal   X : integer := 5;
+  type    INIT_1 is range 1 to 1000;
+  subtype SUBI_1 is INIT_1 range 10 to 20;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    SUBI_1 <= X;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p06n01i01304 - A subtype name can not used on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01304
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1305.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1305.vhd
new file mode 100644
index 0000000..49b24dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1305.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1305.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p06n01i01305ent IS
+END c08s04b00x00p06n01i01305ent;
+
+ARCHITECTURE c08s04b00x00p06n01i01305arch OF c08s04b00x00p06n01i01305ent IS
+  component COMP_1
+    port (A: in BIT; D : out BIT);
+  end component;
+  signal   X : integer := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    COMP_1 <= X;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p06n01i01305 - A component name can not used on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p06n01i01305arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1308.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1308.vhd
new file mode 100644
index 0000000..de0b3a0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1308.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1308.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n01i01308ent IS
+END c08s04b00x00p07n01i01308ent;
+
+ARCHITECTURE c08s04b00x00p07n01i01308arch OF c08s04b00x00p07n01i01308ent IS
+  signal S : BIT;
+  signal T : BIT;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (S,T) <= ('1','0') after 10 ns;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p07n01i01308 - If the target of the signal assignment statement is in the form of an aggregate, then the type of the aggregate must be determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n01i01308arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1311.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1311.vhd
new file mode 100644
index 0000000..5e4ed8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1311.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1311.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n02i01311ent IS
+END c08s04b00x00p07n02i01311ent;
+
+ARCHITECTURE c08s04b00x00p07n02i01311arch OF c08s04b00x00p07n02i01311ent IS
+  type sigrec is
+    record
+      A1 : bit;
+      A2 : integer;
+      A3 : character;
+      A4 : boolean;
+    end record;
+  signal   S1 : bit;
+  signal   S2 : integer;
+  signal   S3 : character;
+  signal   S4 : boolean;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (S1, S2, S3, S4) <= sigrec'('1', 1.2, '1', true);
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p07n02i01311 - Base type of waveform element is not the same as the base type of the signal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n02i01311arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1312.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1312.vhd
new file mode 100644
index 0000000..d9e737c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1312.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1312.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n03i01312ent IS
+END c08s04b00x00p07n03i01312ent;
+
+ARCHITECTURE c08s04b00x00p07n03i01312arch OF c08s04b00x00p07n03i01312ent IS
+  type   BIT_VECTOR is array (natural range <>) of bit;
+  type   INDEX   is range 3 downto 0;
+  subtype   BVI   is BIT_VECTOR(INDEX);
+  signal   S   : BVI;
+BEGIN
+  TESTING: PROCESS
+    variable k : Index;
+  BEGIN
+    (S(3), S(k), S(1), S(0)) <= BVI'('1', others => '0');
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p07n03i01312 - The expression in the element association is not locally static."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n03i01312arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1313.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1313.vhd
new file mode 100644
index 0000000..e351084
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1313.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1313.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n03i01313ent IS
+END c08s04b00x00p07n03i01313ent;
+
+ARCHITECTURE c08s04b00x00p07n03i01313arch OF c08s04b00x00p07n03i01313ent IS
+  subtype   BV2 is BIT_VECTOR(0 to 1);
+  signal S : BV2;
+  signal T : BV2;
+BEGIN
+  TESTING: PROCESS
+    variable BITV : BV2     := B"11";
+    variable I    : integer := 1;
+  BEGIN
+    (S(I), T(I)) <= BITV after 5 ns;
+    wait for 10 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p07n03i01313 - The expression in the element association is not locally static."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n03i01313arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1314.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1314.vhd
new file mode 100644
index 0000000..c7101b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1314.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1314.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n03i01314ent IS
+  generic (GEN : in INTEGER);
+END c08s04b00x00p07n03i01314ent;
+
+ARCHITECTURE c08s04b00x00p07n03i01314arch OF c08s04b00x00p07n03i01314ent IS
+  subtype   BV2 is BIT_VECTOR(0 to 1);
+  signal S : BV2;
+  signal T : BV2;
+BEGIN
+  TESTING: PROCESS
+    variable BITV : BV2     := B"11";
+  BEGIN
+    (S(GEN), T(GEN)) <= BITV after 5 ns;
+    wait for 10 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p07n03i01314 - The expression in the element association is not locally static."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n03i01314arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1315.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1315.vhd
new file mode 100644
index 0000000..a43bded
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1315.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1315.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p07n03i01315ent IS
+  generic (GEN : in INTEGER);
+END c08s04b00x00p07n03i01315ent;
+
+ARCHITECTURE c08s04b00x00p07n03i01315arch OF c08s04b00x00p07n03i01315ent IS
+  subtype CH2  is STRING( 1 to 2 );
+BEGIN
+  TESTING: PROCESS
+    variable STRV     : CH2 := "bb";
+    variable C1, C2   : CHARACTER;
+  BEGIN
+    -- Assign to a non-signal.  ERROR:
+    ( C1,C2 ) <= STRV after 20 ns;
+    wait for 10 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p07n03i01315 - The expression in the element association is not locally static."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p07n03i01315arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1319.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1319.vhd
new file mode 100644
index 0000000..33ad31e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1319.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1319.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p08n01i01319ent IS
+END c08s04b00x00p08n01i01319ent;
+
+ARCHITECTURE c08s04b00x00p08n01i01319arch OF c08s04b00x00p08n01i01319ent IS
+  type aggsig is array (1 to 4) of bit;
+  signal S  : aggsig;
+  signal S1 : bit;
+  signal S2 : bit;
+  signal S3 : bit;
+  signal S4 : bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S <= (bit'('0'), bit'('1'), bit'('0'),bit'('1'));
+    (S1, S2, S1, S4) <= S;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p08n01i01319 - Signal is identified as target more than once in the same assignment."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p08n01i01319arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc132.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc132.vhd
new file mode 100644
index 0000000..6270396
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc132.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc132.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p04n01i00132ent IS
+  port (
+    A1 : in         Bit;
+    A2 : inout      Bit;
+    A3 : linkage    Bit;
+    A4 : out        Bit;
+    A5 : Buffer     Bit
+    ) ;
+END c04s03b02x02p04n01i00132ent;
+
+ARCHITECTURE c04s03b02x02p04n01i00132arch OF c04s03b02x02p04n01i00132ent IS
+  component Local
+    port (
+      C1 : in         Bit;
+      C2 : inout      Bit;
+      C3 : linkage    Bit;
+      C4 : out        Bit;
+      C5 : Buffer     Bit
+      );
+  end component;
+BEGIN
+  CLSI : Local port map
+    (open => A1, open => A2, open => A3, open => A4, open => A5);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x02p04n01i00132 - Open is not a valid formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p04n01i00132arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1320.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1320.vhd
new file mode 100644
index 0000000..85403bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1320.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1320.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p08n03i01320ent IS
+END c08s04b00x00p08n03i01320ent;
+
+ARCHITECTURE c08s04b00x00p08n03i01320arch OF c08s04b00x00p08n03i01320ent IS
+  type BIT_VECTOR is array (natural range <>) of bit;
+  subtype BVI is BIT_VECTOR(0 to 31);
+  signal S : BVI;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (S(0 to 5), S(6), S(7 to 7)) <= BVI'(0 to 5 => '0', 6 => '1', others => '0');
+    assert FALSE 
+      report "***FAILED TEST: c08s04b00x00p08n03i01320 - The expression in element association can not be a discrete range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p08n03i01320arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1324.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1324.vhd
new file mode 100644
index 0000000..14334e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1324.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1324.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p02n01i01324ent IS
+END c08s04b01x00p02n01i01324ent;
+
+ARCHITECTURE c08s04b01x00p02n01i01324arch OF c08s04b01x00p02n01i01324ent IS
+  signal   k : BIT ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= '1' aftre 10 ns;
+    wait for 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s04b01x00p02n01i01324 - The reserved word 'after' is misspelled in the after clause" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p02n01i01324arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1325.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1325.vhd
new file mode 100644
index 0000000..b78eee4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1325.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1325.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p02n01i01325ent IS
+END c08s04b01x00p02n01i01325ent;
+
+ARCHITECTURE c08s04b01x00p02n01i01325arch OF c08s04b01x00p02n01i01325ent IS
+  signal   k : BIT ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= nul after 10 ns;
+    wait for 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s04b01x00p02n01i01325 - The reserved word 'null' is misspelled" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p02n01i01325arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1326.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1326.vhd
new file mode 100644
index 0000000..8fd0ef9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1326.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1326.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p02n01i01326ent IS
+END c08s04b01x00p02n01i01326ent;
+
+ARCHITECTURE c08s04b01x00p02n01i01326arch OF c08s04b01x00p02n01i01326ent IS
+  signal   k : BIT ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= '1' 10 ns;
+    wait for 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s04b01x00p02n01i01326 - The reserved word 'after' is missing in the after clause" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p02n01i01326arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1329.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1329.vhd
new file mode 100644
index 0000000..0ddcc41
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1329.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1329.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p03n05i01329ent IS
+END c08s04b01x00p03n05i01329ent;
+
+ARCHITECTURE c08s04b01x00p03n05i01329arch OF c08s04b01x00p03n05i01329ent IS
+  signal S1, S2, S3 : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S3 <= S1 after 10 ns, null after 100 ns, S2 after 150 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b01x00p03n05i01329 - Null waveform can not be assigned to unguarded signals."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p03n05i01329arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1330.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1330.vhd
new file mode 100644
index 0000000..ab4b8da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1330.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1330.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n01i01330ent IS
+  port (clock : out bit);
+END c08s04b01x00p04n01i01330ent;
+
+ARCHITECTURE c08s04b01x00p04n01i01330arch OF c08s04b01x00p04n01i01330ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    clock <= '1' after 10 ns,
+             '0' after 20 ns,
+             '1' after 30 ns,
+             '0' after X,
+             '1' after 70 ns;
+    wait for 80 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b01x00p04n01i01330 - Time expression must be of predefined type TIME as defined in package STANDARD."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n01i01330arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1333.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1333.vhd
new file mode 100644
index 0000000..2205fd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1333.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1333.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n03i01333ent IS
+END c08s04b01x00p04n03i01333ent;
+
+ARCHITECTURE c08s04b01x00p04n03i01333arch OF c08s04b01x00p04n03i01333ent IS
+  signal S : Bit;
+BEGIN
+  TESTING: PROCESS
+    constant t1 : time := 10  ns;
+    constant t2 : time := 100 ns;
+  BEGIN
+    S <= '0' after (t1 - t2);
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b01x00p04n03i01333 - Time expression must be positive"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n03i01333arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1334.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1334.vhd
new file mode 100644
index 0000000..1d4b822
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1334.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1334.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n03i01334ent IS
+END c08s04b01x00p04n03i01334ent;
+
+ARCHITECTURE c08s04b01x00p04n03i01334arch OF c08s04b01x00p04n03i01334ent IS
+  signal S : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S <= '0' after -5 ns; 
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b01x00p04n03i01334 - Time expression must be positive"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n03i01334arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1345.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1345.vhd
new file mode 100644
index 0000000..3244d49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1345.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1345.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p06n05i01345ent IS
+END c08s04b01x00p06n05i01345ent;
+
+ARCHITECTURE c08s04b01x00p06n05i01345arch OF c08s04b01x00p06n05i01345ent IS
+  signal k : integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <=   1 after 10 ns,
+           2 after 20 ns,
+           3 after 30 ns,
+           2 after 20 ns,
+           4 after 40 ns,
+           5 after 50 ns;
+    wait for 80 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b01x00p06n05i01345 - The sequence of new transactions must be in ascending order with respect to time."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p06n05i01345arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1346.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1346.vhd
new file mode 100644
index 0000000..bb09cec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1346.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1346.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p06n05i01346ent IS
+END c08s04b01x00p06n05i01346ent;
+
+ARCHITECTURE c08s04b01x00p06n05i01346arch OF c08s04b01x00p06n05i01346ent IS
+  signal k : integer;
+  signal c : integer := 5;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <=   c after 5 ns, 5 after 5 ns;
+    wait for 10 ns;
+    assert FALSE  
+      report "***FAILED TEST: c08s04b01x00p06n05i01346 - Multiple time expressions with same value in one waveform are not permitted." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p06n05i01346arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1351.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1351.vhd
new file mode 100644
index 0000000..284130f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1351.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1351.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p02n01i01351ent IS
+END c08s05b00x00p02n01i01351ent;
+
+ARCHITECTURE c08s05b00x00p02n01i01351arch OF c08s05b00x00p02n01i01351ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x : integer) return integer is
+    begin
+      return (10 * x);
+    end;
+    variable k : integer := 0;
+    variable p : integer := 12;
+  BEGIN
+    check(k) := check(p) + 24;
+    assert FALSE
+      report "***FAILED TEST: c08s05b00x00p02n01i01351 - Target of a variable assignment can only be a name or an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p02n01i01351arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1352.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1352.vhd
new file mode 100644
index 0000000..3d55284
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1352.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1352.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p02n01i01352ent IS
+END c08s05b00x00p02n01i01352ent;
+
+ARCHITECTURE c08s05b00x00p02n01i01352arch OF c08s05b00x00p02n01i01352ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    (0, 0, 0) := (0, 0, 0); 
+    assert FALSE
+      report "***FAILED TEST: c08s05b00x00p02n01i01352 - Target of a variable assignment can only be a name or an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p02n01i01352arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1353.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1353.vhd
new file mode 100644
index 0000000..ee5976e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1353.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1353.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p02n01i01353ent IS
+END c08s05b00x00p02n01i01353ent;
+
+ARCHITECTURE c08s05b00x00p02n01i01353arch OF c08s05b00x00p02n01i01353ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a,b : integer;
+  BEGIN
+    (a + b) := 10; 
+    assert FALSE
+      report "***FAILED TEST: c08s05b00x00p02n01i01353 - Target of a variable assignment can only be a name or an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p02n01i01353arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1355.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1355.vhd
new file mode 100644
index 0000000..e521a56
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1355.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1355.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01355ent IS
+END c08s05b00x00p03n01i01355ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01355arch OF c08s05b00x00p03n01i01355ent IS
+
+BEGIN
+  BL : block
+  begin
+    L2 : for I in 1 to 3 generate 
+      TESTING: PROCESS
+      BEGIN
+        I := I + 1;
+        
+        assert FALSE 
+          report "***FAILED TEST: c08s05b00x00p03n01i01355 - The name of thetarget of the variable assignment statement must denote a variable"
+          severity ERROR;
+        wait;
+      END PROCESS TESTING;
+    end generate;
+  end block;
+
+END c08s05b00x00p03n01i01355arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1357.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1357.vhd
new file mode 100644
index 0000000..bf288c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1357.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1357.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01357ent IS
+END c08s05b00x00p03n01i01357ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01357arch OF c08s05b00x00p03n01i01357ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 12;
+    variable r : boolean; 
+  BEGIN
+    r := i;
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01357 - Target and the expression on the right-hand side should have the same type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01357arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1358.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1358.vhd
new file mode 100644
index 0000000..551baff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1358.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1358.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01358ent IS
+END c08s05b00x00p03n01i01358ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01358arch OF c08s05b00x00p03n01i01358ent IS
+
+  signal s : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 12;
+  BEGIN
+    s := i;
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01358 - Target of a variable assignment is not a variable." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01358arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1376.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1376.vhd
new file mode 100644
index 0000000..0be6b8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1376.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1376.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01376ent IS
+END c08s05b00x00p03n01i01376ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01376arch OF c08s05b00x00p03n01i01376ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    type type1 is range 1 to 10;
+    type type2 is range 1 to 10;
+
+    variable v1 : type1 := 1;
+    variable v2 : type2 := 1; 
+    
+  BEGIN
+    --
+    -- The following variable assignment is illegal and
+    -- should generate a type mis-match error.
+    --
+    v1 := v2;                         -- mismatched types
+
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01376 - Named variable and right-hand side expression type mismatched." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01376arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1377.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1377.vhd
new file mode 100644
index 0000000..7f484a1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1377.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1377.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01377ent IS
+END c08s05b00x00p03n01i01377ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01377arch OF c08s05b00x00p03n01i01377ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type type1 is range 1 to 10;
+
+    variable v1 : type1 := 1;
+  BEGIN
+    --
+    -- The following variable assignment is illegal and
+    -- should generate an out-of-range error.
+    --
+    v1 := 0;                          -- zero is out of range
+
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01377 - Right-hand-side expression is out of range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01377arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1378.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1378.vhd
new file mode 100644
index 0000000..70c1496
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1378.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1378.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01378ent IS
+END c08s05b00x00p03n01i01378ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01378arch OF c08s05b00x00p03n01i01378ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type type1 is range 1 to 10;
+
+    variable v1 : type1 := 1;
+  BEGIN
+    --
+    -- The following variable assignment is illegal and
+    -- should generate a type mis-match error.
+    --
+    v1 := 1.0;                        -- mismatched types
+
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01378 - Right-hand-side expression type did not match the named variable." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01378arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1379.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1379.vhd
new file mode 100644
index 0000000..a96a162
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1379.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1379.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01379ent IS
+END c08s05b00x00p03n01i01379ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01379arch OF c08s05b00x00p03n01i01379ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable v1, v2 : integer := 0;
+
+    function add (v1, v2 : integer) return integer is
+    begin
+      return v1 + v2;
+    end add;
+  BEGIN
+
+    v1 := 1;
+    add := v1 + v2;                   -- illegal assignment to function name
+
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01379 - Target of a variable assignment can not be an operator name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01379arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1380.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1380.vhd
new file mode 100644
index 0000000..cd3bf23
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1380.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1380.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01380ent IS
+END c08s05b00x00p03n01i01380ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01380arch OF c08s05b00x00p03n01i01380ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable t1 : time := 100 ns;
+  BEGIN
+
+    sec := t1;                        -- illegal assignment to time unit
+
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01380 - Target of a variable assignment can not be a unit name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01380arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1381.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1381.vhd
new file mode 100644
index 0000000..50a919e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1381.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1381.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s05b00x00p03n01i01381pkg is
+  type base_type is ( 'B', 'O', 'X', 'b', 'o', 'x' );
+end ch0805_p00301_27_pkg;
+
+use work.c08s05b00x00p03n01i01381pkg.all;
+ENTITY c08s05b00x00p03n01i01381ent IS
+END c08s05b00x00p03n01i01381ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01381arch OF c08s05b00x00p03n01i01381ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable v1 : integer := 0;
+  BEGIN
+
+    pack := v1;                       -- illegal package name target
+
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01381 - Target of a variable assignment can not be the name of a package." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01381arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1382.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1382.vhd
new file mode 100644
index 0000000..8d665cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1382.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1382.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01382ent IS
+END c08s05b00x00p03n01i01382ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01382arch OF c08s05b00x00p03n01i01382ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable v1 : integer := 0;
+  BEGIN
+
+    ch0805_p00301_28_ent := v1;                       -- illegal name target
+
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01382 - Target of a variable assignment can not be the name of a design entity." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01382arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1383.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1383.vhd
new file mode 100644
index 0000000..2ac90da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1383.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1383.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01383ent IS
+END c08s05b00x00p03n01i01383ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01383arch OF c08s05b00x00p03n01i01383ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable v1 : integer := 0;
+  BEGIN
+
+    ch0805_p00301_29_arch := v1;                       -- illegal name target
+
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01383 - Target of a variable assignment can not be the name of an architecture body." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01383arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1384.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1384.vhd
new file mode 100644
index 0000000..8cceaeb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1384.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1384.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01384ent IS
+END c08s05b00x00p03n01i01384ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01384arch OF c08s05b00x00p03n01i01384ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type small_int is range 0 to 7;
+    variable v1 : small_int := 0;
+  BEGIN
+
+    small_int := v1;                  -- illegal type name target
+
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01384 - Target of a variable assignment can not be the name of a type name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01384arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1385.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1385.vhd
new file mode 100644
index 0000000..0593ed4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1385.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1385.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p03n01i01385ent IS
+END c08s05b00x00p03n01i01385ent;
+
+ARCHITECTURE c08s05b00x00p03n01i01385arch OF c08s05b00x00p03n01i01385ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype small_int is range 0 to 7;
+    variable v1 : small_int := 0;
+  BEGIN
+
+    small_int := v1;                  -- illegal type name target
+
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p03n01i01385 - Target of a variable assignment can not be the name of a subtype name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p03n01i01385arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1388.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1388.vhd
new file mode 100644
index 0000000..59317bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1388.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1388.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n02i01388ent IS
+END c08s05b00x00p04n02i01388ent;
+
+ARCHITECTURE c08s05b00x00p04n02i01388arch OF c08s05b00x00p04n02i01388ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 16) of integer;
+    variable k : A1;
+  BEGIN
+    k (1 to 4) := (4.0, 3.0, 2.0, 1.0);
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p04n02i01388 - Base types of variable and expression do not match."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n02i01388arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc139.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc139.vhd
new file mode 100644
index 0000000..7d3c2cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc139.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc139.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p09n01i00139ent IS
+END c04s03b02x02p09n01i00139ent;
+
+ARCHITECTURE c04s03b02x02p09n01i00139arch OF c04s03b02x02p09n01i00139ent IS
+  procedure P1 (p : in integer := 3; r: inout integer) is        
+  begin
+    r := p / 3 ;
+  end;
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+  BEGIN
+    P1 (x);  -- Failure_here
+    -- named association missing.
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x02p09n01i00139 - The actual list for procedure call does not match the formal list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p09n01i00139arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1391.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1391.vhd
new file mode 100644
index 0000000..bec0255
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1391.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1391.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p04n03i01391ent IS
+END c08s05b00x00p04n03i01391ent;
+
+ARCHITECTURE c08s05b00x00p04n03i01391arch OF c08s05b00x00p04n03i01391ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ARR is array(0 to 1) of bit;
+    variable i : integer := 1;
+    variable j : integer := 2;
+    variable S : BIT_VECTOR(0 to 1);
+    variable T : BIT_VECTOR(0 to 2);
+  BEGIN
+    (S(i),T(j)) := ARR'('0','1');
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p04n03i01391 - Each element association of the aggregate must be a locally static name that denotes a variable"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p04n03i01391arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1395.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1395.vhd
new file mode 100644
index 0000000..8c5f4ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1395.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1395.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p05n02i01395ent IS
+END c08s05b00x00p05n02i01395ent;
+
+ARCHITECTURE c08s05b00x00p05n02i01395arch OF c08s05b00x00p05n02i01395ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       A1 is array (1 to 2) of integer;
+    variable    XC1, XC2 : A1;
+  BEGIN
+    XC1       := (1 => 1, 2 => 2);
+    (XC2(1), XC2(1)):= A1'(XC1);
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p05n02i01395 - The same element is being assigned a value by more than one association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p05n02i01395arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1396.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1396.vhd
new file mode 100644
index 0000000..b360012
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1396.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1396.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p06n01i01396ent IS
+END c08s05b00x00p06n01i01396ent;
+
+ARCHITECTURE c08s05b00x00p06n01i01396arch OF c08s05b00x00p06n01i01396ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := (1.0 + 2.0);
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p06n01i01396 - The variable and assigned expression must be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p06n01i01396arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1397.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1397.vhd
new file mode 100644
index 0000000..c61d142
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1397.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1397.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p06n01i01397ent IS
+END c08s05b00x00p06n01i01397ent;
+
+ARCHITECTURE c08s05b00x00p06n01i01397arch OF c08s05b00x00p06n01i01397ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := '0'; 
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p06n01i01397 - The variable and assigned expression must be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p06n01i01397arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1398.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1398.vhd
new file mode 100644
index 0000000..a1a6697
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1398.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1398.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY ch0805_p00601_04_03_ent IS
+END ch0805_p00601_04_03_ent;
+
+ARCHITECTURE ch0805_p00601_04_03_arch OF ch0805_p00601_04_03_ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype a is integer range 1 to 10;
+    variable k : integer := 5;
+  BEGIN
+    a := k; 
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p06n01i01398 - If the target of a variable assignment statement is a name, then the name must denote a variable." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p06n01i01398arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc140.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc140.vhd
new file mode 100644
index 0000000..b458bcf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc140.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc140.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p09n01i00140ent IS
+  PORT (   SIGNAL a    : IN bit;
+           SIGNAL b    : IN integer;
+           SIGNAL c    : IN boolean;
+           SIGNAL d    : IN time;
+           SIGNAL e    : IN real;
+           SIGNAL oint    : INOUT integer);
+END c04s03b02x02p09n01i00140ent;
+
+ARCHITECTURE c04s03b02x02p09n01i00140arch OF c04s03b02x02p09n01i00140ent IS
+  function funct1(   fpar1:bit   :='1';
+                     fpar2:integer   :=455;
+                     fpar3:boolean   :=true;
+                     fpar4:time   :=55.77 ns;
+                     fpar5:real   :=34.558) return integer is
+  begin
+    return 1;
+  end funct1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    oint <= funct1(fpar3=>c,fpar2=>b,fpar1=>a,fpar4=>d,nosuch=>e);
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x02p09n01i00140 - Named association parameter where name is not in formal parameter list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p09n01i00140arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1406.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1406.vhd
new file mode 100644
index 0000000..1b72a51
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1406.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1406.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p07n01i01406ent IS
+END c08s05b00x00p07n01i01406ent;
+
+ARCHITECTURE c08s05b00x00p07n01i01406arch OF c08s05b00x00p07n01i01406ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type arr is array (1 to 3) of integer;
+    variable p : arr;
+  BEGIN
+    p := (1=>3, 2=>2.3, 3=>3);
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p07n01i01406 - Type of the subelement does not match the type of the aggregate element." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p07n01i01406arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1407.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1407.vhd
new file mode 100644
index 0000000..b1ee389
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1407.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1407.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01407ent IS
+END c08s05b01x00p01n01i01407ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01407arch OF c08s05b01x00p01n01i01407ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable B : Bit_vector (0 to 10) := B"01010010101"; 
+  BEGIN
+    B(1 to 0)   := B"01";
+    B(4 to 2)   := B"101";
+    assert FALSE 
+      report "***FAILED TEST: c08s05b01x00p01n01i01407 - Every element of the array variable should have a matching element in the array value and vice versa."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01407arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1408.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1408.vhd
new file mode 100644
index 0000000..72b04fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1408.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1408.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01408ent IS
+END c08s05b01x00p01n01i01408ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01408arch OF c08s05b01x00p01n01i01408ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type      A1 is array (1 to 15) of integer;
+    variable   XC : A1; 
+  BEGIN
+    XC (4 to 1) := (4,3,2,1);
+    assert FALSE 
+      report "***FAILED TEST: c08s05b01x00p01n01i01408 - the type of the target and the value assigned to the target in an array variable assignment statement must be the same." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01408arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1411.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1411.vhd
new file mode 100644
index 0000000..05c2902
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1411.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1411.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01411ent IS
+END c08s05b01x00p01n01i01411ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01411arch OF c08s05b01x00p01n01i01411ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type      A1 is array (1 to 15) of integer;
+    variable   XC : A1; 
+  BEGIN
+    XC (4 to 1) := 4321;
+    assert FALSE 
+      report "***PASSED TEST: c08s05b01x00p01n01i01411" 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01411arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1415.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1415.vhd
new file mode 100644
index 0000000..5548a9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1415.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1415.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01415ent IS
+END c08s05b01x00p01n01i01415ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01415arch OF c08s05b01x00p01n01i01415ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BIT_VECTOR is array (natural range <>) of BIT;
+    type A01_VECTOR is array (natural range <>) of BIT;
+    variable NUM1 : BIT_VECTOR(0 to 1);
+    variable NUM2 : A01_VECTOR(0 to 1);
+  BEGIN
+    NUM1 := NUM2;
+    assert FALSE 
+      report "***FAILED TEST: c08s05b01x00p01n01i01415 - The type of the target and the value assigned to the target in an array variable assignment must be the same." 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01415arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1416.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1416.vhd
new file mode 100644
index 0000000..ff2e9e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1416.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1416.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01416ent IS
+END c08s05b01x00p01n01i01416ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01416arch OF c08s05b01x00p01n01i01416ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ARAY_1 is array (INTEGER range <>) of BIT;
+    subtype SUB_ONE      is ARAY_1 (1 to 10);
+    subtype SUB_TWO    is ARAY_1 (1 to 100);
+    subtype SUB_THREE    is ARAY_1 (41 to 60);
+    variable V1 : SUB_ONE;
+    variable V2 : SUB_TWO;
+    variable V3 : SUB_THREE;
+  BEGIN
+    V1 := V3;
+    assert FALSE 
+      report "***FAILED TEST: c08s05b01x00p01n01i01416 - The number of components has to be the same." 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01416arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1417.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1417.vhd
new file mode 100644
index 0000000..ee1fab0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1417.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1417.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01417ent IS
+END c08s05b01x00p01n01i01417ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01417arch OF c08s05b01x00p01n01i01417ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable B : Bit_vector (0 to 10) := B"01010010101";
+  BEGIN
+    B(1 to 0)   :=      B"01" ;
+    B(4 to 2)   :=      B"101"; -- non-null assignments cannot be made
+    -- to null slices.
+    assert FALSE 
+      report "***FAILED TEST: c08s05b01x00p01n01i01417 - Every element of the array variable should have a matching element in the array value and vice versa." 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01417arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1418.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1418.vhd
new file mode 100644
index 0000000..cc92a03
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1418.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1418.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b01x00p01n01i01418ent IS
+END c08s05b01x00p01n01i01418ent;
+
+ARCHITECTURE c08s05b01x00p01n01i01418arch OF c08s05b01x00p01n01i01418ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 15) of integer;
+    variable XC : A1;
+  BEGIN
+    XC (4 to 1) := (4, 3, 2, 1); -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c08s05b01x00p01n01i01418 - The type of the target and the value assigned to the target in an array variable assignment statement must be the same." 
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b01x00p01n01i01418arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1419.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1419.vhd
new file mode 100644
index 0000000..841ab9e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1419.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1419.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p02n01i01419ent IS
+END c08s06b00x00p02n01i01419ent;
+
+ARCHITECTURE c08s06b00x00p02n01i01419arch OF c08s06b00x00p02n01i01419ent IS
+
+BEGIN
+  TESTING: PROCESS
+    signal some    : integer := 12;
+    signal p    : integer := 3;
+    signal q    : boolean := true;
+  BEGIN
+    some (p,q);
+    assert FALSE
+      report "***FAILED TEST: c08s06b00x00p02n01i01419 - A name that is not a procedure is used in a procedure call statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p02n01i01419arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc142.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc142.vhd
new file mode 100644
index 0000000..65ef544
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc142.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc142.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p10n01i00142ent IS
+  PORT (   SIGNAL a    : IN bit;
+           SIGNAL b    : IN integer;
+           SIGNAL c    : IN boolean;
+           SIGNAL d    : IN time;
+           SIGNAL e    : IN real;
+           SIGNAL oint    : INOUT integer);
+END c04s03b02x02p10n01i00142ent;
+
+ARCHITECTURE c04s03b02x02p10n01i00142arch OF c04s03b02x02p10n01i00142ent IS
+  function funct1(   fpar1:bit   :='1';
+                     fpar2:integer   :=455;
+                     fpar3:boolean   :=true;
+                     fpar4:time   :=55.77 ns;
+                     fpar5:real   :=34.558) return integer is
+  begin
+    return 1;
+  end funct1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    oint    <= funct1(fpar3=>c,fpar2=>b,fpar1=>a,d,e);
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p10n01i00142 - Positional association can not follow named association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p10n01i00142arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1420.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1420.vhd
new file mode 100644
index 0000000..5f0979c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1420.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1420.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p02n01i01420ent IS
+END c08s06b00x00p02n01i01420ent;
+
+ARCHITECTURE c08s06b00x00p02n01i01420arch OF c08s06b00x00p02n01i01420ent IS
+  signal some    : integer := 12;
+BEGIN
+  TESTING: PROCESS
+    procedure check (x : in  integer; y : out boolean) is
+    begin
+      if x = 1 then
+        y := true;
+      else
+        y := false;
+      end if;
+    end;
+    variable p : integer := 3;
+    variable q : boolean := true;
+  BEGIN
+    some (p,q);
+    assert FALSE
+      report "***FAILED TEST: c08s06b00x00p02n01i01420 - Incorrect procedure call, procedure 'some' does not exist." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p02n01i01420arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1426.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1426.vhd
new file mode 100644
index 0000000..391b9cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1426.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1426.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p05n01i01426ent IS
+END c08s06b00x00p05n01i01426ent;
+
+ARCHITECTURE c08s06b00x00p05n01i01426arch OF c08s06b00x00p05n01i01426ent IS
+
+  procedure copy_int ( variable src, dest : inout integer ) is
+    --
+    -- This procedure copies the value of the first argument
+    -- into the second argument.
+    --
+  begin
+    dest := src;
+  end copy_int;
+
+
+BEGIN
+  TESTING : PROCESS
+    variable v1,v2 : integer := 0;
+  BEGIN
+
+    --
+    -- Try calling the procedure with three arguments
+    --
+    v1 := 5;
+    copy_int(v1, v2, 5);              -- too many arguments
+
+    assert FALSE 
+      report "***FAILED TEST: c08s06b00x00p05n01i01426 - Procedure call without an actual parameter part is permitted." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p05n01i01426arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1427.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1427.vhd
new file mode 100644
index 0000000..ac45fae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1427.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1427.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p06n01i01427ent IS
+END c08s06b00x00p06n01i01427ent;
+
+ARCHITECTURE c08s06b00x00p06n01i01427arch OF c08s06b00x00p06n01i01427ent IS
+  procedure check(x : in integer; y : in boolean) is
+  begin
+  end;
+  signal k : real;
+  signal q : boolean;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L1 : check(k,q);
+    assert FALSE 
+      report "***FAILED TEST: c08s06b00x00p06n01i01427 - The parameters in the procedure declaration and the corresponding arguments in the procedure call are not of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p06n01i01427arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1428.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1428.vhd
new file mode 100644
index 0000000..74d2bf8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1428.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1428.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p06n01i01428ent IS
+END c08s06b00x00p06n01i01428ent;
+
+ARCHITECTURE c08s06b00x00p06n01i01428arch OF c08s06b00x00p06n01i01428ent IS
+  procedure check(x : in integer; y : in boolean) is
+  begin
+  end;
+  signal k : real;
+  signal q : boolean;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L1 : check(k,q);
+    assert FALSE 
+      report "***FAILED TEST: c08s06b00x00p06n01i01428 - Type of argument incompatible with type of parameter" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p06n01i01428arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1429.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1429.vhd
new file mode 100644
index 0000000..d93bd63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1429.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1429.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p06n01i01429ent IS
+END c08s06b00x00p06n01i01429ent;
+
+ARCHITECTURE c08s06b00x00p06n01i01429arch OF c08s06b00x00p06n01i01429ent IS
+
+  --
+  -- Define two different types with the same value sets
+  --
+  type int_type1 is range 0 to 7;
+  type int_type2 is range 0 to 7;
+
+  --
+  -- and a procedure to use one of the types
+  --
+  procedure copy_int ( variable src, dest : inout int_type1
+                       ) is
+    --
+    -- This procedure just copies one argument's value to the other
+    --
+  begin
+    dest := src;
+  end copy_int;
+
+BEGIN
+  TESTING: PROCESS
+
+    variable v1 : int_type1 := 0;
+    variable v2 : int_type2 := 0;
+
+  BEGIN
+    --
+    -- Make a procedure call where the arguments do not match
+    -- the types declared in the definition.
+    --
+    copy_int(v1, v2);                 -- v2 : type mismatch
+
+    assert FALSE 
+      report "***FAILED TEST: c08s06b00x00p06n01i01429 - Type of argument incompatible with type of parameter" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p06n01i01429arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1430.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1430.vhd
new file mode 100644
index 0000000..3f3df45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1430.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1430.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s06b00x00p06n01i01430ent IS
+END c08s06b00x00p06n01i01430ent;
+
+ARCHITECTURE c08s06b00x00p06n01i01430arch OF c08s06b00x00p06n01i01430ent IS
+
+  --
+  -- Define two different types with the same value sets
+  --
+  type int_type1 is range 0 to 7;
+  type int_type2 is range 0 to 7;
+
+  --
+  -- and a procedure to use one of the types
+  --
+  procedure copy_int ( variable src  : in int_type1;
+                       variable dest : inout int_type2
+                       ) is
+    --
+    -- This procedure just copies one argument's value to the other
+    -- after doing a type conversion.
+    --
+  begin
+    dest := int_type2(src);
+  end copy_int;
+
+BEGIN
+  TESTING: PROCESS
+
+    variable v1 : int_type1 := 0;
+    variable v2 : int_type2 := 0;
+
+  BEGIN
+    --
+    -- Make a procedure call where the arguments do not match
+    -- the types declared in the definition.
+    --
+    copy_int(v2, v1);                 -- v2 : type mismatch
+
+    assert FALSE 
+      report "***FAILED TEST: c08s06b00x00p06n01i01430 - Type of argument incompatible with type of parameter" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s06b00x00p06n01i01430arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1431.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1431.vhd
new file mode 100644
index 0000000..37b1032
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1431.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1431.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01431ent IS
+END c08s07b00x00p02n01i01431ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01431arch OF c08s07b00x00p02n01i01431ent IS
+
+begin
+
+  TEST_PROCESS:  process
+    variable I : INTEGER := 47;
+
+  begin
+    -- Misspelled reserved word 'if'
+    fi  (I = 47) then
+      NULL;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c08s07b00x00p02n01i01431 - misspelled reserved word 'if'"
+      severity ERROR;
+    wait;
+  end process TEST_PROCESS;
+
+END c08s07b00x00p02n01i01431arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1432.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1432.vhd
new file mode 100644
index 0000000..5b74686
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1432.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1432.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01432ent IS
+END c08s07b00x00p02n01i01432ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01432arch OF c08s07b00x00p02n01i01432ent IS
+
+begin
+
+  TEST_PROCESS:  process
+    variable I : INTEGER := 47;
+
+  begin
+    -- Missing  reserved word 'then' ERROR
+    if  (I = 47) 
+      NULL;
+  end if;
+  assert FALSE 
+    report "***FAILED TEST: c08s07b00x00p02n01i01432 - missing reserved word 'then' after IF" 
+    severity FAILURE;   
+  wait;
+end process TEST_PROCESS;
+
+END c08s07b00x00p02n01i01432arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1433.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1433.vhd
new file mode 100644
index 0000000..948eb2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1433.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1433.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01433ent IS
+END c08s07b00x00p02n01i01433ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01433arch OF c08s07b00x00p02n01i01433ent IS
+begin
+
+  TEST_PROCESS:  process
+    variable I : INTEGER := 47;
+  begin
+    -- Misspelled 'elsif'.
+    if  (I /= 47) then
+      NULL;
+      elseif (I = 47) then
+        NULL;
+      end if;
+      assert FALSE 
+        report "***FAILED TEST: c08s07b00x00p02n01i01433 - reserved word 'elsif' is misspelled"
+        severity ERROR;
+      wait;
+    end process TEST_PROCESS;
+
+    END c08s07b00x00p02n01i01433arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1434.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1434.vhd
new file mode 100644
index 0000000..cc0222f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1434.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1434.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01434ent IS
+END c08s07b00x00p02n01i01434ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01434arch OF c08s07b00x00p02n01i01434ent IS
+begin
+
+  TEST_PROCESS:  process
+    variable I : INTEGER := 47;
+  begin
+    if  (I /= 47) the
+      NULL;   
+  else if (I = 47) then
+         NULL;
+       end if;
+       assert FALSE 
+         report "***FAILED TEST: c08s07b00x00p02n01i01434 - reserved word 'then' misspelled"
+         severity ERROR;
+       wait;
+  end process TEST_PROCESS;
+
+END c08s07b00x00p02n01i01434arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1435.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1435.vhd
new file mode 100644
index 0000000..094577b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1435.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1435.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01435ent IS
+END c08s07b00x00p02n01i01435ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01435arch OF c08s07b00x00p02n01i01435ent IS
+begin
+
+  TEST_PROCESS:  process
+    variable I : INTEGER := 47;
+  begin
+    -- Missing 'then' on 'elsif'.
+    if  (I /= 47) then
+      NULL;
+    elsif (I = 47) 
+      NULL;
+  end if;
+  assert FALSE 
+    report "***FAILED TEST: c08s07b00x00p02n01i01435 - reserved word 'then' after 'elsif' is missing"
+    severity ERROR;
+  wait;
+end process TEST_PROCESS;
+
+END c08s07b00x00p02n01i01435arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1436.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1436.vhd
new file mode 100644
index 0000000..dcbe2b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1436.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1436.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01436ent IS
+END c08s07b00x00p02n01i01436ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01436arch OF c08s07b00x00p02n01i01436ent IS
+begin
+
+  TEST_PROCESS:  process
+    variable I : INTEGER := 47;
+  begin
+    -- 'else' before 'elsif'.
+    if  (I /= 47) then
+      NULL;
+    else
+      NULL;
+    elsif (I = 47) then
+      NULL;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c08s07b00x00p02n01i01436 - reserved word 'elsif' is misplaced"
+      severity ERROR;
+    wait;
+  end process TEST_PROCESS;
+
+END c08s07b00x00p02n01i01436arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1437.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1437.vhd
new file mode 100644
index 0000000..dbe3a2d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1437.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1437.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01437ent IS
+END c08s07b00x00p02n01i01437ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01437arch OF c08s07b00x00p02n01i01437ent IS
+begin
+  P2_1 : process
+    variable v_integer : integer := 10;
+  begin
+    if    v_integer /= 10 then
+      NULL;
+      els
+        NULL;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c08s07b00x00p02n01i01437 - reserved word 'else' is misspelled"
+      severity ERROR;
+    wait;
+  end process P2_1 ;
+
+END c08s07b00x00p02n01i01437arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1438.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1438.vhd
new file mode 100644
index 0000000..9eae7dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1438.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1438.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01438ent IS
+END c08s07b00x00p02n01i01438ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01438arch OF c08s07b00x00p02n01i01438ent IS
+
+begin
+  process
+    variable VAR_1: INTEGER := 3;
+  begin
+    if VAR_1 > 2 then
+      NULL;
+      assert FALSE 
+        report "***FAILED TEST: c08s07b00x00p02n01i01438 - reserved word 'end if;' is missing"
+        severity ERROR;
+      wait;
+    end process;
+
+    END c08s07b00x00p02n01i01438arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1439.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1439.vhd
new file mode 100644
index 0000000..ce52a68
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1439.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1439.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01439ent IS
+END c08s07b00x00p02n01i01439ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01439arch OF c08s07b00x00p02n01i01439ent IS
+
+BEGIN
+  process
+    variable VAR_1: INTEGER := 3;
+  begin
+    if VAR_1 > 2 then
+      NULL;
+      en if;
+      assert FALSE 
+        report "***FAILED TEST: c08s07b00x00p02n01i01439 - reserved word 'end if;' is misspelled"
+        severity ERROR;
+      wait;
+    end process;
+
+    END c08s07b00x00p02n01i01439arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc144.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc144.vhd
new file mode 100644
index 0000000..765a28f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc144.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc144.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p12n01i00144pkg is
+  procedure P1 (a : in integer; b: out integer);
+  function  F1 (I : in integer) return real;
+end c04s03b02x02p12n01i00144pkg;
+
+package body c04s03b02x02p12n01i00144pkg is
+  procedure P1 (a: in integer; b: out integer) is
+  begin
+    b := a;
+  end;
+  
+  function  F1 (I: in integer) return real is
+    variable y : real := 1.0;
+  begin
+    return (y);
+  end;
+end c04s03b02x02p12n01i00144pkg;
+
+use work.c04s03b02x02p12n01i00144pkg.all;
+ENTITY c04s03b02x02p12n01i00144ent IS
+END c04s03b02x02p12n01i00144ent;
+
+ARCHITECTURE c04s03b02x02p12n01i00144arch OF c04s03b02x02p12n01i00144ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    variable x : integer := 1;
+    variable y : integer;
+  BEGIN
+    P1 (10, F1(b) => x );   --  Failure_here
+    y := x;
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p12n01i00144 - Imbedded function call has improper subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p12n01i00144arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1440.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1440.vhd
new file mode 100644
index 0000000..7841587
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1440.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1440.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01440ent IS
+END c08s07b00x00p02n01i01440ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01440arch OF c08s07b00x00p02n01i01440ent IS
+
+begin
+  process
+    variable k : INTEGER := 1;
+  begin
+    if k = 1 then
+      NULL;
+    end if
+      assert FALSE 
+      report "***FAILED TEST: c08s07b00x00p02n01i01440 - missing semicolon after 'end if'"
+      severity ERROR;
+    wait;
+  end process;
+END c08s07b00x00p02n01i01440arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1441.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1441.vhd
new file mode 100644
index 0000000..75908df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1441.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1441.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01441ent IS
+END c08s07b00x00p02n01i01441ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01441arch OF c08s07b00x00p02n01i01441ent IS
+
+begin
+  process
+    variable k : INTEGER := 1;
+  begin
+    if k = 1 then
+      NULL;
+    end if;
+    NULL;
+  elsif
+    NULL:
+    assert FALSE 
+    report "***FAILED TEST: c08s07b00x00p02n01i01441 - missing semicolon after 'end if'"
+    severity ERROR;
+    wait;
+  end process;
+
+END c08s07b00x00p02n01i01441arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1449.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1449.vhd
new file mode 100644
index 0000000..9044f41
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1449.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1449.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p02n01i01449ent IS
+END c08s07b00x00p02n01i01449ent;
+
+ARCHITECTURE c08s07b00x00p02n01i01449arch OF c08s07b00x00p02n01i01449ent IS
+
+  type boolean_enum is (less_than, equal_to, greater_than);
+
+  function be_compare ( constant i1, i2 : integer ) return boolean_enum is
+  begin
+    --
+    -- This if statement has two else clauses; the second one
+    -- is illegal.
+    --
+    if i1 < i2 then
+      return less_than;
+    else                              -- This 'else' is OK
+      return greater_than;
+    else                              -- This 'else' is illegal
+      return equal_to;
+    end if;
+  end be_compare;
+
+begin
+  TESTING: process
+    variable be_val : boolean_enum;   -- function return value
+    variable v1, v2 : integer := 0;   -- equal test values
+  begin
+    --
+    -- This first function call should get an error message
+    -- if it even gets that far.
+    --
+    be_val := be_compare(v1,v2);
+
+    assert FALSE 
+      report "***FAILED TEST: c08s07b00x00p02n01i01449 - If statement can only have one else clause." 
+      severity ERROR;
+
+    wait;
+  end process TESTING;
+
+END c08s07b00x00p02n01i01449arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc145.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc145.vhd
new file mode 100644
index 0000000..c8f1070
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc145.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc145.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p12n01i00145pkg is
+  procedure P1 (a    : in integer; b: out integer);
+  function  F1 (I1, I2   : in integer) return real;
+end c04s03b02x02p12n01i00145pkg;
+
+package body c04s03b02x02p12n01i00145pkg is
+  procedure P1 (a: in integer; b: out integer) is
+  begin
+    b := a;
+  end;
+  
+  function  F1 (I1, I2: in integer) return real is
+    variable y : real := 1.0;
+  begin
+    return (y);
+  end;
+end c04s03b02x02p12n01i00145pkg;
+
+use work.c04s03b02x02p12n01i00145pkg.all;
+ENTITY c04s03b02x02p12n01i00145ent IS
+END c04s03b02x02p12n01i00145ent;
+
+ARCHITECTURE c04s03b02x02p12n01i00145arch OF c04s03b02x02p12n01i00145ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    variable x1 : real := 1.0;
+    variable x2 : real := 1.0;
+    variable y  : real ;
+  BEGIN
+    P1 (10, F1(b, x1) => x2 );   -- Failure_here
+                                     -- function has more than one parameter.
+    y := x2;
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p12n01i00145 - Formal part in named association has improper format."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p12n01i00145arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1453.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1453.vhd
new file mode 100644
index 0000000..6b13a60
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1453.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1453.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p01n01i01453ent IS
+END c08s07b00x00p01n01i01453ent;
+
+ARCHITECTURE c08s07b00x00p01n01i01453arch OF c08s07b00x00p01n01i01453ent IS
+
+BEGIN
+  transmit: process
+    variable   s := 10;
+  begin
+    if s + 10 then      -- failure_here           condition not boolean.
+      NULL;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c08s07b00x00p01n01i01453 - Expression of IF statement must be of type BOOLEAN"
+      severity ERROR;
+    wait;
+  end process transmit;
+
+END c08s07b00x00p01n01i01453arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1454.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1454.vhd
new file mode 100644
index 0000000..c1134b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1454.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1454.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p01n01i01454ent IS
+END c08s07b00x00p01n01i01454ent;
+
+ARCHITECTURE c08s07b00x00p01n01i01454arch OF c08s07b00x00p01n01i01454ent IS
+
+begin
+  TESTING: process
+    variable b1, b2 : bit := '0';
+  begin
+    if '1' then      -- failure_here           condition not boolean.
+      b1 := '1';
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c08s07b00x00p01n01i01454 - Expression of IF statement is not of type BOOLEAN"
+      severity ERROR;
+    wait;
+  end process TESTING;
+
+END c08s07b00x00p01n01i01454arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1455.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1455.vhd
new file mode 100644
index 0000000..5282b41
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1455.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1455.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s07b00x00p01n01i01455ent IS
+END c08s07b00x00p01n01i01455ent;
+
+ARCHITECTURE c08s07b00x00p01n01i01455arch OF c08s07b00x00p01n01i01455ent IS
+
+begin
+  TESTING: process
+    variable i1, i2 : integer := 0;
+  begin
+    if 1 then      -- failure_here           condition not boolean.
+      i1 := 1;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c08s07b00x00p01n01i01455 - Expression of IF statement is not of type BOOLEAN"
+      severity ERROR;
+    wait;
+  end process TESTING;
+
+END c08s07b00x00p01n01i01455arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1464.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1464.vhd
new file mode 100644
index 0000000..36a5247
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1464.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1464.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p02n01i01464ent IS
+END c08s08b00x00p02n01i01464ent;
+
+ARCHITECTURE c08s08b00x00p02n01i01464arch OF c08s08b00x00p02n01i01464ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+    variable k : integer := 0;
+  BEGIN
+    case x 
+      when 1 => k := 5;
+    when 2 => NULL;
+    when 3 => NULL;
+    when others => NULL;
+  end case;
+  assert FALSE 
+    report "***FAILED TEST: c08s08b00x00p02n01i01464 - missing reserved word 'is'"
+    severity ERROR;
+  wait;
+END PROCESS TESTING;
+
+END c08s08b00x00p02n01i01464arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1465.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1465.vhd
new file mode 100644
index 0000000..f521ef4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1465.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1465.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p02n01i01465ent IS
+END c08s08b00x00p02n01i01465ent;
+
+ARCHITECTURE c08s08b00x00p02n01i01465arch OF c08s08b00x00p02n01i01465ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+    variable k : integer := 0;
+  BEGIN
+    case  is 
+      when 1 => k := 5;
+    when 2 => NULL;
+    when 3 => NULL;
+    when others => NULL;
+  end case;
+  assert FALSE 
+    report "***FAILED TEST: c08s08b00x00p02n01i01465 - missing expression after the reserved word 'case'"
+    severity ERROR;
+  wait;
+END PROCESS TESTING;
+
+END c08s08b00x00p02n01i01465arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1466.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1466.vhd
new file mode 100644
index 0000000..5574fb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1466.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1466.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p02n01i01466ent IS
+END c08s08b00x00p02n01i01466ent;
+
+ARCHITECTURE c08s08b00x00p02n01i01466arch OF c08s08b00x00p02n01i01466ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+  BEGIN
+    case x is 
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p02n01i01466 - missing case statement alternatives in case statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p02n01i01466arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1467.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1467.vhd
new file mode 100644
index 0000000..b807365
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1467.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1467.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p02n01i01467ent IS
+END c08s08b00x00p02n01i01467ent;
+
+ARCHITECTURE c08s08b00x00p02n01i01467arch OF c08s08b00x00p02n01i01467ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+    variable k : integer := 0;
+  BEGIN
+    case x is
+      when 1 => k := 5;
+      when others => NULL;
+    end case
+      assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p02n01i01467 - Missing semicolon after the reserved word 'end case'." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p02n01i01467arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1468.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1468.vhd
new file mode 100644
index 0000000..5c0d98d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1468.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1468.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p03n01i01468ent IS
+END c08s08b00x00p03n01i01468ent;
+
+ARCHITECTURE c08s08b00x00p03n01i01468arch OF c08s08b00x00p03n01i01468ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 0;
+  BEGIN
+    case x is
+      1 => NULL;
+      when 2 => NULL:
+                  when 3 => NULL;
+      when others => NULL;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p03n01i01468 - missing reserved word 'when'"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p03n01i01468_arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1469.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1469.vhd
new file mode 100644
index 0000000..98d3a78
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1469.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1469.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p03n01i01469ent IS
+END c08s08b00x00p03n01i01469ent;
+
+ARCHITECTURE c08s08b00x00p03n01i01469arch OF c08s08b00x00p03n01i01469ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 0;
+  BEGIN
+    case x is
+      when 1 => NULL;
+      when   => NULL:
+                  when 3 => NULL;
+      when others => NULL;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p03n01i01469 - missing choices"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p03n01i01469arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1470.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1470.vhd
new file mode 100644
index 0000000..4e48ea7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1470.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1470.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p03n01i01470ent IS
+END c08s08b00x00p03n01i01470ent;
+
+ARCHITECTURE c08s08b00x00p03n01i01470arch OF c08s08b00x00p03n01i01470ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 0;
+  BEGIN
+    case x is
+      when 1 => NULL;
+      when 2 => NULL:
+                  when 3    NULL;
+      when others => NULL;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p03n01i01470 - missing arrows"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p03n01i01470arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1471.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1471.vhd
new file mode 100644
index 0000000..fd8f0a3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1471.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1471.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p03n01i01471ent IS
+END c08s08b00x00p03n01i01471ent;
+
+ARCHITECTURE c08s08b00x00p03n01i01471arch OF c08s08b00x00p03n01i01471ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 0;
+  BEGIN
+    case x is
+      when 1 => NULL;
+      when 2 => NULL:
+                  when 3 => NULL;
+      when others => ;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p03n01i01471 - missing sequence of statement in a case alternative"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p03n01i01471arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1472.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1472.vhd
new file mode 100644
index 0000000..a0b16b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1472.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1472.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p03n01i01472ent IS
+END c08s08b00x00p03n01i01472ent;
+
+ARCHITECTURE c08s08b00x00p03n01i01472arch OF c08s08b00x00p03n01i01472ent IS
+
+  type primary is (blue, red, yellow);
+
+  --
+  -- Test that the '<=' can not be used
+  --
+  function color_to_int ( constant color : primary
+                          ) return integer is
+  begin
+    case color is
+      when others <=                -- should be '=>'
+                                    return primary'pos(color);
+    end case;
+  end color_to_int;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p03n01i01472 - Signal assignment operator can not be used as case alternative delimiter." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p03n01i01472arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1476.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1476.vhd
new file mode 100644
index 0000000..f0a1730
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1476.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1476.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01476ent IS
+END c08s08b00x00p04n01i01476ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01476arch OF c08s08b00x00p04n01i01476ent IS
+
+  type   t_int1 is range 0 to 100;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : integer := 50;
+  BEGIN
+    case i is
+      when t_int1'low to 60    => k := 5;
+      when 61 to 88       => NULL;
+      when others       => NULL;
+    end case;
+    assert FALSE
+      report "***FAILED TEST: c08s08b00x00p04n01i01476 - all of the choices must have the same type as the expression"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01476arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1477.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1477.vhd
new file mode 100644
index 0000000..b8df91e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1477.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1477.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01477ent IS
+END c08s08b00x00p04n01i01477ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01477arch OF c08s08b00x00p04n01i01477ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable r1 : real := 0.1;
+  BEGIN
+    case r1 is                        -- illegal, must be discrete
+      when 0.0 to 1.0 =>
+        assert false
+          report "REAL allowed as case expression."
+          severity note ;
+      when others =>
+        assert false
+          report "REAL allowed as case expression."
+          severity note ;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p04n01i01477 - Real type is not allowed in expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01477arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1478.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1478.vhd
new file mode 100644
index 0000000..cba4f86
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1478.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1478.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01478ent IS
+END c08s08b00x00p04n01i01478ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01478arch OF c08s08b00x00p04n01i01478ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type i_array_type is array (1 to 5) of integer;
+    variable a1 : i_array_type := (others => 0);
+  BEGIN
+
+    case a1 is                        -- illegal, must be discrete
+      when 0 =>
+        assert false
+          report "Array allowed as case expression."
+          severity note ;
+      when others =>
+        assert false
+          report "Array allowed as case expression."
+          severity note ;
+    end case;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p04n01i01478 - Array type is not allowed in expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01478arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1479.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1479.vhd
new file mode 100644
index 0000000..a0223b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1479.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1479.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01479ent IS
+END c08s08b00x00p04n01i01479ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01479arch OF c08s08b00x00p04n01i01479ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    procedure boo_boo ( variable i1 : inout integer
+                        ) is
+    begin
+      -- Just return what is submitted
+    end boo_boo;
+    variable boo_b : integer := 0;
+
+  BEGIN
+
+    case boo_boo(boo_b) is                    -- illegal, must be function
+      when 0 =>
+        assert false
+          report "Procedure call allowed as case expression."
+          severity note ;
+      when others =>
+        assert false
+          report "Procedure call allowed as case expression."
+          severity note ;
+    end case;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p04n01i01479 - Procedure call is not allowed in expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01479arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1480.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1480.vhd
new file mode 100644
index 0000000..d7de8f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1480.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1480.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01480ent IS
+END c08s08b00x00p04n01i01480ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01480arch OF c08s08b00x00p04n01i01480ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    function f return real is
+      type    t1 is (one,two,three,four);
+      subtype    st is t1 range one to three;
+      variable    v  : st := one;
+    begin
+      case v is
+        when one =>
+          return 0.1;
+        when two to four =>       -- error : range violates constraints
+          return 9.0;
+      end case;
+    end f;
+
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p04n01i01480 - Static range violation." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01480arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1481.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1481.vhd
new file mode 100644
index 0000000..423c896
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1481.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1481.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01481ent IS
+END c08s08b00x00p04n01i01481ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01481arch OF c08s08b00x00p04n01i01481ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    function f return boolean is
+      variable v1 : natural := 6;
+    begin
+      case v1 is
+        when -1 to 5 =>           -- error : range violates constraint
+          return true;
+        when others =>
+          return false;
+      end case;
+    end f;
+
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p04n01i01481 - Static range violation." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01481arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1482.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1482.vhd
new file mode 100644
index 0000000..9f1aa49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1482.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1482.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n01i01482ent IS
+END c08s08b00x00p04n01i01482ent;
+
+ARCHITECTURE c08s08b00x00p04n01i01482arch OF c08s08b00x00p04n01i01482ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+    subtype  st is integer range 20 to 45;
+    variable v1 : st := 20;
+    constant c1 : integer := 14;
+
+  BEGIN
+
+    case v1 is
+      when 0 to 100  =>            -- error : range violates constraint
+        v1 := 33;
+      when others =>
+        v1 := 20;
+    end case;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p04n01i01482 - Static range violation." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n01i01482arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1484.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1484.vhd
new file mode 100644
index 0000000..caef471
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1484.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1484.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p04n03i01484ent IS
+END c08s08b00x00p04n03i01484ent;
+
+ARCHITECTURE c08s08b00x00p04n03i01484arch OF c08s08b00x00p04n03i01484ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : integer := 2;
+  BEGIN
+    case i is
+      when  2      =>   k = 5;
+      when true   =>    NULL;
+      when others   =>   NULL;
+    end case;
+    assert NOT( k = 5 )
+      report "***PASSED TEST: c08s08b00x00p04n03i01484"
+      severity NOTE;
+    assert ( k = 5 )
+      report "***FAILED TEST: c08s08b00x00p04n03i01484 -  The case statement alternatives must be of the same type as the expression"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p04n03i01484arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1489.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1489.vhd
new file mode 100644
index 0000000..6f48b91
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1489.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1489.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p05n01i01489ent IS
+END c08s08b00x00p05n01i01489ent;
+
+ARCHITECTURE c08s08b00x00p05n01i01489arch OF c08s08b00x00p05n01i01489ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type x is (Jan,Feb,Mar);
+    variable y:x;
+  BEGIN
+    case y is
+      when Jan   => NULL;
+      when Feb   => NULL;
+      when Mar   => NULL;
+      when Jan   => NULL;
+      when others   => NULL;
+    end case;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p05n01i01489 - Each choice in a case statement may only be represented once"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p05n01i01489arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1490.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1490.vhd
new file mode 100644
index 0000000..53ac868
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1490.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1490.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p05n01i01490ent IS
+END c08s08b00x00p05n01i01490ent;
+
+ARCHITECTURE c08s08b00x00p05n01i01490arch OF c08s08b00x00p05n01i01490ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type x is (Jan,Feb,Mar,Apr);
+    variable y:x;
+
+  BEGIN
+    case y is
+      when Jan   => NULL;
+      when Feb   => NULL;
+      when Mar   => NULL;
+    end case;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p05n01i01490 - the choice OTHERS must be present when all alternatives are not covered "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p05n01i01490arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1492.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1492.vhd
new file mode 100644
index 0000000..81b9d8a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1492.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1492.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p05n01i01492ent IS
+END c08s08b00x00p05n01i01492ent;
+
+ARCHITECTURE c08s08b00x00p05n01i01492arch OF c08s08b00x00p05n01i01492ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable b1, b2 : boolean ;= true;
+  BEGIN
+    case b1 is
+    end case;   -- illegal
+
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p05n01i01492 - Case statement must have at least one alternative." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p05n01i01492arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1494.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1494.vhd
new file mode 100644
index 0000000..d1e8ebd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1494.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1494.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p07n01i01494ent IS
+END c08s08b00x00p07n01i01494ent;
+
+ARCHITECTURE c08s08b00x00p07n01i01494arch OF c08s08b00x00p07n01i01494ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable kk : STRING(1 to N) ; 
+  BEGIN
+    case kk is
+      when "TH"   =>   NULL;
+      when "AB"   =>    NULL;
+      when others   =>   NULL;
+    end case; 
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p07n01i01494 - Case Expression must denote a locally static subtype" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p07n01i01494arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1498.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1498.vhd
new file mode 100644
index 0000000..e056647
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1498.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1498.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n01i01498ent IS
+END c08s08b00x00p14n01i01498ent;
+
+ARCHITECTURE c08s08b00x00p14n01i01498arch OF c08s08b00x00p14n01i01498ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer ;
+    variable p : integer := 5;
+    variable q : integer ;
+  BEGIN
+    case p is
+      when k      =>   NULL;
+      when q      =>    NULL;
+      when others   =>   NULL;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p14n01i01498 - Simple expression is not static" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n01i01498arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1501.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1501.vhd
new file mode 100644
index 0000000..f5e2ba3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1501.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1501.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n02i01501ent IS
+END c08s08b00x00p14n02i01501ent;
+
+ARCHITECTURE c08s08b00x00p14n02i01501arch OF c08s08b00x00p14n02i01501ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST is INTEGER range 20 to 45;
+    variable V1 : ST := 20;
+  BEGIN
+    case V1 is
+      when 20.0 to 22.0   =>   NULL; 
+      when others      =>    NULL;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p14n02i01501 - Non-discrete ranges are not allowed in case choices" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n02i01501arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1502.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1502.vhd
new file mode 100644
index 0000000..e7fecfc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1502.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1502.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n03i01502ent IS
+END c08s08b00x00p14n03i01502ent;
+
+ARCHITECTURE c08s08b00x00p14n03i01502arch OF c08s08b00x00p14n03i01502ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type months is (Jan, Feb,Mar);
+    variable x : months;
+  BEGIN
+    case x is
+      when Jan   =>   NULL;
+      when Feb   =>   NULL;
+      when Others   =>   NULL;
+      when Mar   =>   NULL;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p14n03i01502 - The choice OTHERS must be the last alternative in a CASE statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n03i01502arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1503.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1503.vhd
new file mode 100644
index 0000000..c8e0398
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1503.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1503.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n03i01503ent IS
+END c08s08b00x00p14n03i01503ent;
+
+ARCHITECTURE c08s08b00x00p14n03i01503arch OF c08s08b00x00p14n03i01503ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer;
+  BEGIN
+    case x is
+      when 1   =>   NULL;
+      when 2   =>   NULL;
+      when 3   =>   NULL;
+      when 4   =>   NULL;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p14n03i01503 - OTHERS choice is required as an alternative in a CASE statement" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n03i01503arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1504.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1504.vhd
new file mode 100644
index 0000000..0b003ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1504.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1504.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n03i01504ent IS
+END c08s08b00x00p14n03i01504ent;
+
+ARCHITECTURE c08s08b00x00p14n03i01504arch OF c08s08b00x00p14n03i01504ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer;
+  BEGIN
+    case x is
+      when 1 to 19      =>   NULL;
+      when others | 32   =>   NULL;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p14n03i01504 - OTHERS choice is allowed as the last choice and it must be the only choice" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n03i01504arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1506.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1506.vhd
new file mode 100644
index 0000000..0a3caed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1506.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1506.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s08b00x00p14n04i01506ent IS
+END c08s08b00x00p14n04i01506ent;
+
+ARCHITECTURE c08s08b00x00p14n04i01506arch OF c08s08b00x00p14n04i01506ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type day is (sun,mon,tue,wed,thu,fri,sat);
+
+    type rec_type is
+      record 
+        element : day;
+      end record;
+
+    variable s_day ; day;
+  BEGIN
+    case s_day is
+      when sun   => NULL;
+      when mon   => NULL;
+      when elements   => NULL;
+      when others   => NULL;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c08s08b00x00p14n04i01506 - A simple name is not allowed as an alternative in a CASE statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s08b00x00p14n04i01506arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc151.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc151.vhd
new file mode 100644
index 0000000..87f90e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc151.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc151.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p16n01i00151ent_a IS
+  port (signal input_1 : in  bit;
+        signal input_2 : in  bit_vector;
+        signal output  : out bit);
+END c04s03b02x02p16n01i00151ent_a;
+
+ARCHITECTURE c04s03b02x02p16n01i00151arch_a OF c04s03b02x02p16n01i00151ent_a IS
+BEGIN
+END c04s03b02x02p16n01i00151arch_a;
+
+
+ENTITY c04s03b02x02p16n01i00151ent IS
+  port (X: in BIT; Z: out BIT);
+END c04s03b02x02p16n01i00151ent;
+
+ARCHITECTURE c04s03b02x02p16n01i00151arch OF c04s03b02x02p16n01i00151ent IS
+  component input2
+    port (signal input_1 : in  bit;
+          signal input_2 : in  bit_vector;
+          signal output  : out bit);
+  end component;
+  for G1 : input2 use entity work.ch04030202_p01601_02_ent_a(ch04030202_p01601_02_arch_a);
+  type    bit_vector    is array (positive range <>) of bit;
+  signal    A1       :  bit_vector;
+BEGIN
+
+  G1: input2 port map (X, A1, Z); -- Failure_here
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p16n01i00151 - The type of an actual should be same as that of the formal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p16n01i00151arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1513.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1513.vhd
new file mode 100644
index 0000000..f3d7116
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1513.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1513.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p02n01i01513ent IS
+END c08s09b00x00p02n01i01513ent;
+
+ARCHITECTURE c08s09b00x00p02n01i01513arch OF c08s09b00x00p02n01i01513ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L1 : loop
+    end L1;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p02n01i01513 - Missing reserved word 'end loop' in a loop statement" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p02n01i01513arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc152.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc152.vhd
new file mode 100644
index 0000000..acd4d71
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc152.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc152.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p16n01i00152ent_a IS
+  port (signal input_1 : in  bit;
+        signal input_2 : in  bit;
+        signal output  : out bit);
+END c04s03b02x02p16n01i00152ent_a;
+
+ARCHITECTURE c04s03b02x02p16n01i00152arch_a OF c04s03b02x02p16n01i00152ent_a IS
+BEGIN
+END c04s03b02x02p16n01i00152arch_a;
+
+
+ENTITY c04s03b02x02p16n01i00152ent IS
+  port (X: in BIT; Z: out BIT);
+END c04s03b02x02p16n01i00152ent;
+
+ARCHITECTURE c04s03b02x02p16n01i00152arch OF c04s03b02x02p16n01i00152ent IS
+  component input2
+    port (signal input_1 : in  bit;
+          signal input_2 : in  bit;
+          signal output  : out bit);
+  end component;
+  for G1 : input2 use entity work.c04s03b02x02p16n01i00152ent_a(c04s03b02x02p16n01i00152arch_a);
+  type    byte    is    array (1 to 8) of bit;
+  signal    A1    :    byte;
+BEGIN
+
+  G1: input2 port map (X, A1, Z); -- Failure_here
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p16n01i00152 - The type of an actual should be same as that of the formal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p16n01i00152arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1520.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1520.vhd
new file mode 100644
index 0000000..d79da61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1520.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1520.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p05n01i01520ent IS
+END c08s09b00x00p05n01i01520ent;
+
+ARCHITECTURE c08s09b00x00p05n01i01520arch OF c08s09b00x00p05n01i01520ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant k : integer := 0;
+  BEGIN
+    l1 : loop
+    end loop kk;
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p05n01i01520 - The label at the end of the loop statement does not match the loop label"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p05n01i01520arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1525.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1525.vhd
new file mode 100644
index 0000000..87868de
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1525.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1525.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p08n01i01525ent IS
+END c08s09b00x00p08n01i01525ent;
+
+ARCHITECTURE c08s09b00x00p08n01i01525arch OF c08s09b00x00p08n01i01525ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    while not '0' loop
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p08n01i01525 - while condition is not boolean expression" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p08n01i01525arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1526.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1526.vhd
new file mode 100644
index 0000000..53210f8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1526.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1526.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p08n01i01526ent IS
+END c08s09b00x00p08n01i01526ent;
+
+ARCHITECTURE c08s09b00x00p08n01i01526arch OF c08s09b00x00p08n01i01526ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    while "HELLO" & "O" loop
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p08n01i01526 - while condition is not boolean expression" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p08n01i01526arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1527.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1527.vhd
new file mode 100644
index 0000000..92881df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1527.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1527.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p08n01i01527ent IS
+END c08s09b00x00p08n01i01527ent;
+
+ARCHITECTURE c08s09b00x00p08n01i01527arch OF c08s09b00x00p08n01i01527ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable NSS : integer := 5;
+    variable MIN : integer := 6;
+  BEGIN
+    while NSS * MIN loop
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p08n01i01527 - while condition is not boolean expression" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p08n01i01527arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1528.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1528.vhd
new file mode 100644
index 0000000..c2c3881
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1528.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1528.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p08n01i01528ent IS
+END c08s09b00x00p08n01i01528ent;
+
+ARCHITECTURE c08s09b00x00p08n01i01528arch OF c08s09b00x00p08n01i01528ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    while '1' and '0' loop
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p08n01i01528 - while condition is not boolean expression" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p08n01i01528arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc153.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc153.vhd
new file mode 100644
index 0000000..25735e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc153.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc153.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p16n01i00153pkg is
+  procedure P1 (a : in integer; b: inout integer);
+end ch04030202_p01601_03_pkg;
+
+package body c04s03b02x02p16n01i00153pkg is
+  procedure P1 (a: in integer; b: inout integer) is
+  begin
+    b := a;
+  end;
+end c04s03b02x02p16n01i00153pkg;
+
+
+use work.c04s03b02x02p16n01i00153pkg.all;
+ENTITY c04s03b02x02p16n01i00153ent IS
+END c04s03b02x02p16n01i00153ent;
+
+ARCHITECTURE c04s03b02x02p16n01i00153arch OF c04s03b02x02p16n01i00153ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+    variable x : real := 1.0;
+  BEGIN
+    P1 (10, b => x);  -- Failure_here
+    -- b and x have different types
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p16n01i00153 - Type mismatch."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p16n01i00153arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1532.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1532.vhd
new file mode 100644
index 0000000..29c4c47
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1532.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1532.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n02i01532ent IS
+END c08s09b00x00p09n02i01532ent;
+
+ARCHITECTURE c08s09b00x00p09n02i01532arch OF c08s09b00x00p09n02i01532ent IS
+
+BEGIN
+  TESTING: PROCESS
+
+  BEGIN
+    --
+    -- Loop must have discrete parameters
+    --
+    L1: for c in 1.2 to 2.54 loop     -- parameters must be discrete
+      null;
+    end loop L1;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p09n02i01532 - Loop parameters must be discrete."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n02i01532arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1533.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1533.vhd
new file mode 100644
index 0000000..a1dc011
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1533.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1533.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n02i01533ent IS
+END c08s09b00x00p09n02i01533ent;
+
+ARCHITECTURE c08s09b00x00p09n02i01533arch OF c08s09b00x00p09n02i01533ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    i1, i2, i3 : integer := 1;
+  BEGIN
+
+    --
+    -- Initialize two integer variables so their division yeilds a real
+    -- 
+    i2 := 11;
+    i3 := 3;
+    --
+    -- Loop must have discrete parameters
+    --
+    L1: for c in i1 to real(i2) / i3 loop     -- parameters must be discrete
+      null;
+    end loop L1;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p09n02i01533 - Loop parameters must be discrete."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n02i01533arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1534.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1534.vhd
new file mode 100644
index 0000000..ddf9761
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1534.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1534.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n02i01534ent IS
+END c08s09b00x00p09n02i01534ent;
+
+ARCHITECTURE c08s09b00x00p09n02i01534arch OF c08s09b00x00p09n02i01534ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable    i1, i2, i3 : integer := 1;
+  BEGIN
+
+    --
+    -- Initialize two integer variables so their division yeilds a real
+    -- 
+    i2 := 11;
+    i3 := 3;
+    --
+    -- Loop must have discrete parameters
+    --
+    L1: for c in real(i2) / i3 to i2 loop     -- parameters must be discrete
+      null;
+    end loop L1;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p09n02i01534 - Loop parameters must be discrete."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n02i01534arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1535.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1535.vhd
new file mode 100644
index 0000000..c19bf99
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1535.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1535.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n03i01535ent IS
+END c08s09b00x00p09n03i01535ent;
+
+ARCHITECTURE c08s09b00x00p09n03i01535arch OF c08s09b00x00p09n03i01535ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable i : integer := 10;
+  BEGIN
+    i := 3;
+    for i in 1 to 5 loop
+      k := k + 1;
+      i := 4;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p09n03i01535 -  The loop index can not be the target of an assignment statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n03i01535arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1537.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1537.vhd
new file mode 100644
index 0000000..5e71fff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1537.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1537.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n05i01537ent IS
+END c08s09b00x00p09n05i01537ent;
+
+ARCHITECTURE c08s09b00x00p09n05i01537arch OF c08s09b00x00p09n05i01537ent IS
+  procedure copy ( variable v_in  : in integer := 0;
+                   variable v_out : out integer
+                   ) is
+  begin
+    v_out := v_in;
+  end copy;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    L1: for i in 4 to 5 loop
+      copy (6, i);                  -- illegal: 2nd param is mode "inout"
+    end loop L1;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p09n05i01537 - A loop parameter can not be an actual corresponding to a formal of mode out "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n05i01537arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1538.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1538.vhd
new file mode 100644
index 0000000..f5eb333
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1538.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1538.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p09n05i01538ent IS
+END c08s09b00x00p09n05i01538ent;
+
+ARCHITECTURE c08s09b00x00p09n05i01538arch OF c08s09b00x00p09n05i01538ent IS
+  procedure copy ( variable v_in : in integer := 0;
+                   variable v_out : inout integer
+                   ) is
+  begin
+    v_out := v_in;
+  end copy;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    L1: for i in 4 to 5 loop
+      copy (6, i);                  -- illegal: 2nd param is mode "inout"
+    end loop L1;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p09n05i01538 - A loop parameter can not be an actual corresponding to a formal of mode inout "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p09n05i01538arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1541.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1541.vhd
new file mode 100644
index 0000000..530611a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1541.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1541.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01541ent IS
+END c08s09b00x00p10n01i01541ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01541arch OF c08s09b00x00p10n01i01541ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    s : for j in 1 to 100 loop
+      s := 3;
+    end loop s;
+    s := 3;
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p10n01i01541 - The target of the variable assignment statement is not declared" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01541arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1542.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1542.vhd
new file mode 100644
index 0000000..466a6a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1542.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1542.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s09b00x00p10n01i01542ent IS
+END c08s09b00x00p10n01i01542ent;
+
+ARCHITECTURE c08s09b00x00p10n01i01542arch OF c08s09b00x00p10n01i01542ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    s : for j in PS to FS loop
+    end loop s;
+    assert FALSE 
+      report "***FAILED TEST: c08s09b00x00p10n01i01542 - Discrete range must have discrete upper and lower bounds" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s09b00x00p10n01i01542arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc155.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc155.vhd
new file mode 100644
index 0000000..9a72309
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc155.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc155.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p16n02i00155pkg is
+  procedure P1 (a: in integer; b: out integer);
+end c04s03b02x02p16n02i00155pkg;
+
+package body c04s03b02x02p16n02i00155pkg is
+  procedure P1 (a: in integer; b: out integer) is
+  begin
+    b := a;
+  end;
+end c04s03b02x02p16n02i00155pkg;
+
+
+use work.c04s03b02x02p16n02i00155pkg.all;
+ENTITY c04s03b02x02p16n02i00155ent IS
+END c04s03b02x02p16n02i00155ent;
+
+ARCHITECTURE c04s03b02x02p16n02i00155arch OF c04s03b02x02p16n02i00155ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : real := 1.0;
+  BEGIN
+    P1 (10, b => x);  -- Failure_here
+    -- b and x have different types
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p16n02i00155 - Type mis-match during procedure call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p16n02i00155arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1556.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1556.vhd
new file mode 100644
index 0000000..cf0c01c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1556.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1556.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p02n01i01556ent IS
+END c08s10b00x00p02n01i01556ent;
+
+ARCHITECTURE c08s10b00x00p02n01i01556arch OF c08s10b00x00p02n01i01556ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for i in 1 to 10 loop
+      next 
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p02n01i01556 - Missing semicolon in the loop statement" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p02n01i01556arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1557.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1557.vhd
new file mode 100644
index 0000000..ed8bc30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1557.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1557.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p02n01i01557ent IS
+END c08s10b00x00p02n01i01557ent;
+
+ARCHITECTURE c08s10b00x00p02n01i01557arch OF c08s10b00x00p02n01i01557ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    L1: for b in boolean loop
+      next when b L1;               -- label must precede when clause
+    end loop L1;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p02n01i01557 - Illegal clause ordering." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p02n01i01557arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1559.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1559.vhd
new file mode 100644
index 0000000..8f1069d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1559.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1559.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01559ent IS
+END c08s10b00x00p03n01i01559ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01559arch OF c08s10b00x00p03n01i01559ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L : for i in 1 to 10 loop
+    end loop;
+    next L;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p03n01i01559 - A next statement with a loop label must be inside the loop containing that label" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01559arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc156.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc156.vhd
new file mode 100644
index 0000000..87999f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc156.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc156.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p17n01i00156ent IS
+  PORT ( ii: INOUT integer);
+  PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
+  BEGIN
+    IF add THEN
+      i4 := (i1+i2+i3);
+    ELSE
+      i4 := (i1-i2)-i3;
+    END IF;
+  END;
+END c04s03b02x02p17n01i00156ent;
+
+ARCHITECTURE c04s03b02x02p17n01i00156arch OF c04s03b02x02p17n01i00156ent IS
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE a1 : INTEGER := 57;
+    VARIABLE a2 : INTEGER := 68;
+    VARIABLE a3 : INTEGER := 77;
+    VARIABLE b1 : BIT := '1';
+    VARIABLE b2 : BIT := '0';
+    FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
+    BEGIN
+      IF (inp > 0) THEN
+        RETURN (TRUE);
+      ELSE
+        RETURN (FALSE);
+      END IF;
+    END;
+    FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
+    BEGIN
+      IF (inp = '1') THEN
+        RETURN (22);
+      ELSE
+        RETURN (23);
+      END IF;
+    END;
+  BEGIN
+    WAIT FOR 1 ns;
+    addup(i2=>conv1(b1),add=>conv1(a2),i1=>conv1(b2),i3=>a1,i4=>a1);    
+    WAIT FOR 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p17n01i00156 - Type coversion return wrong type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p17n01i00156arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1561.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1561.vhd
new file mode 100644
index 0000000..06f54e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1561.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1561.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01561ent IS
+END c08s10b00x00p03n01i01561ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01561arch OF c08s10b00x00p03n01i01561ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable s : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      next K when i = 3;
+      s := s + 1;
+    end loop L;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p03n01i01561 - A next statement with a label loop must be inside that loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01561arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1562.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1562.vhd
new file mode 100644
index 0000000..78fb2ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1562.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1562.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01562ent IS
+END c08s10b00x00p03n01i01562ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01562arch OF c08s10b00x00p03n01i01562ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 0;
+    variable K : integer := 1;
+  BEGIN
+    L : for i in 1 to 10 loop
+      next K when i = 3;
+    end loop L;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p03n01i01562 - A next statement with a loop label must exist inside that loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01562arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1563.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1563.vhd
new file mode 100644
index 0000000..e3c2c9c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1563.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1563.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01563ent IS
+END c08s10b00x00p03n01i01563ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01563arch OF c08s10b00x00p03n01i01563ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for i in 1 to 10 loop
+      next K;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p03n01i01563 - The loop label after the NEXT statement does not exist" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01563arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1564.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1564.vhd
new file mode 100644
index 0000000..dc3692d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1564.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1564.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p03n01i01564ent IS
+END c08s10b00x00p03n01i01564ent;
+
+ARCHITECTURE c08s10b00x00p03n01i01564arch OF c08s10b00x00p03n01i01564ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for i in 1 to 10 loop
+    end loop;
+    next;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p03n01i01564 - A NEXT statement must be inside a loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p03n01i01564arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1575.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1575.vhd
new file mode 100644
index 0000000..a26c926
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1575.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1575.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01575ent IS
+END c08s10b00x00p04n01i01575ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01575arch OF c08s10b00x00p04n01i01575ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L : for i in 1 to 10 loop
+      next L when 5;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p04n01i01575 - The condition in a next statement has to be of type boolean" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01575arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1577.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1577.vhd
new file mode 100644
index 0000000..3d58e17
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1577.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1577.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01577ent IS
+END c08s10b00x00p04n01i01577ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01577arch OF c08s10b00x00p04n01i01577ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L : for i in 1 to 10 loop
+      next when 5.0;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p04n01i01577 - The condition in a next statement has to be of type boolean" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01577arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1578.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1578.vhd
new file mode 100644
index 0000000..e95f82e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1578.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1578.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01578ent IS
+END c08s10b00x00p04n01i01578ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01578arch OF c08s10b00x00p04n01i01578ent IS
+  type   bool is (t,f);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L : for i in 1 to 10 loop
+      next when t;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p04n01i01578 - The condition in a next statement has to be of type boolean" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01578arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1579.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1579.vhd
new file mode 100644
index 0000000..a25b0fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1579.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1579.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01579ent IS
+END c08s10b00x00p04n01i01579ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01579arch OF c08s10b00x00p04n01i01579ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L : for i in 1 to 10 loop
+      next when 't';
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p04n01i01579 - The condition in a next statement has to be of type boolean" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01579arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1580.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1580.vhd
new file mode 100644
index 0000000..4d832ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1580.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1580.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s10b00x00p04n01i01580ent IS
+END c08s10b00x00p04n01i01580ent;
+
+ARCHITECTURE c08s10b00x00p04n01i01580arch OF c08s10b00x00p04n01i01580ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L : for i in 1 to 10 loop
+      next when "tt";
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s10b00x00p04n01i01580 - The condition in a next statement has to be of type boolean" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s10b00x00p04n01i01580arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1584.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1584.vhd
new file mode 100644
index 0000000..4415da4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1584.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1584.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p02n01i01584ent IS
+END c08s11b00x00p02n01i01584ent;
+
+ARCHITECTURE c08s11b00x00p02n01i01584arch OF c08s11b00x00p02n01i01584ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    while i < 10 loop
+      exit 
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p02n01i01584 - Missing semicolon in the loop statement" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p02n01i01584arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1586.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1586.vhd
new file mode 100644
index 0000000..85f673e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1586.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1586.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p02n01i01586ent IS
+END c08s11b00x00p02n01i01586ent;
+
+ARCHITECTURE c08s11b00x00p02n01i01586arch OF c08s11b00x00p02n01i01586ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    L1: for b in boolean loop
+      exit when b L1;               -- label must precede when clause
+    end loop L1;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p02n01i01586 - Illegal clause ordering in exit statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p02n01i01586arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1588.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1588.vhd
new file mode 100644
index 0000000..5ff648a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1588.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1588.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01588ent IS
+END c08s11b00x00p03n01i01588ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01588arch OF c08s11b00x00p03n01i01588ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L : for i in 1 to 10 loop
+    end loop;
+    exit L;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p03n01i01588 - An EXIT statement with a loop label must be in a loop"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01588arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc159.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc159.vhd
new file mode 100644
index 0000000..3583eef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc159.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc159.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p19n05i00159pkg is
+  type       t is array (1 to 4) of integer;
+  procedure    p (a: in t);
+end c04s03b02x02p19n05i00159pkg;
+
+package body c04s03b02x02p19n05i00159pkg is
+  procedure p (a: in t) is
+  begin
+  end p;
+end c04s03b02x02p19n05i00159pkg;
+
+
+use work.c04s03b02x02p19n05i00159pkg.all;
+ENTITY c04s03b02x02p19n05i00159ent IS
+END c04s03b02x02p19n05i00159ent;
+
+ARCHITECTURE c04s03b02x02p19n05i00159arch OF c04s03b02x02p19n05i00159ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 2;
+  BEGIN
+    p (t'(i => 12, others => 0));  -- Failure_here
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p19n05i00159 - Subelements of an association list may only be locally static names."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p19n05i00159arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1590.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1590.vhd
new file mode 100644
index 0000000..87f193a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1590.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1590.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01590ent IS
+END c08s11b00x00p03n01i01590ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01590arch OF c08s11b00x00p03n01i01590ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    L : for i in 1 to 10 loop
+      exit K when i = 3;
+    end loop L;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p03n01i01590 - The exit label does not match the loop label" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01590arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1591.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1591.vhd
new file mode 100644
index 0000000..b0c8662
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1591.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1591.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01591ent IS
+END c08s11b00x00p03n01i01591ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01591arch OF c08s11b00x00p03n01i01591ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 1;
+    variable K : integer := 1;
+  BEGIN
+    L : while i < 10 loop
+      exit K when i = 3;
+    end loop L;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p03n01i01591 - The exit label does not match the loop label" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01591arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1592.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1592.vhd
new file mode 100644
index 0000000..9fe619a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1592.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1592.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01592ent IS
+END c08s11b00x00p03n01i01592ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01592arch OF c08s11b00x00p03n01i01592ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for i in 1 to 10 loop
+      exit L;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p03n01i01592 - A loop label is not allowed in an exit statement which is in an unlabeled loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01592arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1593.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1593.vhd
new file mode 100644
index 0000000..98beffd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1593.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1593.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01593ent IS
+END c08s11b00x00p03n01i01593ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01593arch OF c08s11b00x00p03n01i01593ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for i in 1 to 10 loop
+      exit L;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p03n01i01593 - A loop label is not allowed in an exit statement which is in an unlabeled loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01593arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1595.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1595.vhd
new file mode 100644
index 0000000..483aec5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1595.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1595.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01595ent IS
+END c08s11b00x00p03n01i01595ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01595arch OF c08s11b00x00p03n01i01595ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for i in 1 to 10 loop
+    end loop;
+    exit;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p03n01i01595 - EXIT must be in a loop" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01595arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc160.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc160.vhd
new file mode 100644
index 0000000..9618328
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc160.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc160.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x02p19n04i00160pkg is
+  type rec_type is
+    record
+      a, b, c : integer;
+    end record;
+  procedure P1 (p : in rec_type; q: in integer; r: out integer);
+end c04s03b02x02p19n04i00160pkg;
+
+package body c04s03b02x02p19n04i00160pkg is
+  procedure P1 (p : in rec_type; q: in integer; r: out integer) is
+  begin
+    r := (p.a + p.b + p.c)/3 * q;
+  end;
+end c04s03b02x02p19n04i00160pkg;
+
+
+use work.c04s03b02x02p19n04i00160pkg.all;
+ENTITY c04s03b02x02p19n04i00160ent IS
+END c04s03b02x02p19n04i00160ent;
+
+ARCHITECTURE c04s03b02x02p19n04i00160arch OF c04s03b02x02p19n04i00160ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 1;
+  BEGIN
+    P1 (p.a => 1, p.b => 2, p.a => 3, p.c => 4, q => 12);
+                                        -- Failure_here
+                                        -- p.a named twice.
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p19n04i00160 - Subelements of an association list may only be assigned once."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p19n04i00160arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1602.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1602.vhd
new file mode 100644
index 0000000..935f780
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1602.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1602.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p03n01i01602ent IS
+END c08s11b00x00p03n01i01602ent;
+
+ARCHITECTURE c08s11b00x00p03n01i01602arch OF c08s11b00x00p03n01i01602ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    L1: for i in 4 to 5 loop
+      exit TESTING;                       -- wrong label
+    end loop L1;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p03n01i01602 - Illegal label for exit statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p03n01i01602arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1604.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1604.vhd
new file mode 100644
index 0000000..c6ab5e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1604.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1604.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01604ent IS
+END c08s11b00x00p04n01i01604ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01604arch OF c08s11b00x00p04n01i01604ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      exit L when 'A';
+      k := i;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p04n01i01604 - The condition in an exit statement must be of boolean type" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01604arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1605.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1605.vhd
new file mode 100644
index 0000000..377a2f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1605.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1605.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01605ent IS
+END c08s11b00x00p04n01i01605ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01605arch OF c08s11b00x00p04n01i01605ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      exit L when k + 3;
+      k := i;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p04n01i01605 - The condition in an exit statement must be of boolean type" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01605arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1609.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1609.vhd
new file mode 100644
index 0000000..86daec9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1609.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1609.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01609ent IS
+END c08s11b00x00p04n01i01609ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01609arch OF c08s11b00x00p04n01i01609ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      exit L when 1.0;
+      k := i;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p04n01i01609 - The condition in an exit statement must be of boolean type" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01609arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc161.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc161.vhd
new file mode 100644
index 0000000..dd3cb3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc161.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc161.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p19n04i00161ent IS
+  PORT (   SIGNAL a    : IN bit;
+           SIGNAL b    : IN integer;
+           SIGNAL c    : IN boolean;
+           SIGNAL d    : IN time;
+           SIGNAL e,f    : IN real;
+           SIGNAL oint    : INOUT integer);
+END c04s03b02x02p19n04i00161ent;
+
+ARCHITECTURE c04s03b02x02p19n04i00161arch OF c04s03b02x02p19n04i00161ent IS
+  function funct1(   fpar1   :bit   :='1';
+                     fpar2   :integer:=455;
+                     fpar3   :boolean:=true;
+                     fpar4   :time   :=55.77 ns;
+                     fpar5   :real   :=34.558) return integer is
+  begin
+    return 1;
+  end funct1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    oint <= funct1(fpar5=>f,fpar3=>c,fpar2=>b,fpar1=>a,fpar4=>d,fpar5=>e);
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p19n04i00161 - Same formal parameter name can not be used more than once."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p19n04i00161arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1610.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1610.vhd
new file mode 100644
index 0000000..b9e6546
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1610.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1610.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01610ent IS
+END c08s11b00x00p04n01i01610ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01610arch OF c08s11b00x00p04n01i01610ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      exit L when 1;
+      k := i;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p04n01i01610 - The condition in an exit statement must be of boolean type" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01610arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1611.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1611.vhd
new file mode 100644
index 0000000..74dd869
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1611.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1611.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01611ent IS
+END c08s11b00x00p04n01i01611ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01611arch OF c08s11b00x00p04n01i01611ent IS
+  type bool is (t,f);
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      exit L when t;
+      k := i;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p04n01i01611 - The condition in an exit statement must be of boolean type" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01611arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1612.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1612.vhd
new file mode 100644
index 0000000..aaa9651
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1612.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1612.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s11b00x00p04n01i01612ent IS
+END c08s11b00x00p04n01i01612ent;
+
+ARCHITECTURE c08s11b00x00p04n01i01612arch OF c08s11b00x00p04n01i01612ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    L : for i in 1 to 10 loop
+      exit L when "Tt";
+      k := i;
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST: c08s11b00x00p04n01i01612 - The condition in an exit statement must be of boolean type" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s11b00x00p04n01i01612arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1615.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1615.vhd
new file mode 100644
index 0000000..a9f1848
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1615.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1615.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p02n01i01615ent IS
+END c08s12b00x00p02n01i01615ent;
+
+ARCHITECTURE c08s12b00x00p02n01i01615arch OF c08s12b00x00p02n01i01615ent IS
+  function ts (x1:bit) return integer is
+  begin
+    return(1)
+  end ts;
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    k := ts('1');
+    assert FALSE
+      report "***FAILED TEST: c08s12b00x00p02n01i01615 - Missing semicolon in the loop statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p02n01i01615arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1616.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1616.vhd
new file mode 100644
index 0000000..5f6ab37
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1616.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1616.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01616ent IS
+END c08s12b00x00p03n01i01616ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01616arch OF c08s12b00x00p03n01i01616ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+    variable j : boolean := true;
+  BEGIN
+    if j then return k;
+              assert FALSE 
+                report "***FAILED TEST: c08s12b00x00p03n01i01616 - A return statement must be inside a subprogram body"
+                severity ERROR;
+              wait;
+    END PROCESS TESTING;
+
+    END c08s12b00x00p03n01i01616arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1618.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1618.vhd
new file mode 100644
index 0000000..69d018c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1618.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1618.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01618ent IS
+END c08s12b00x00p03n01i01618ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01618arch OF c08s12b00x00p03n01i01618ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    return;
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p03n01i01618 - A return statement is only allowed within the body of a function" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01618arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1620.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1620.vhd
new file mode 100644
index 0000000..de7a8ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1620.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1620.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01620ent IS
+  return true;      -- illegal in entity declaration region.
+END c08s12b00x00p03n01i01620ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01620arch OF c08s12b00x00p03n01i01620ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p03n01i01620 - Return statement only allowed within the body of a function or procedure." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01620arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1621.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1621.vhd
new file mode 100644
index 0000000..6d8a987
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1621.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1621.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01621ent IS
+begin
+  return true;      -- illegal in entity statement region.
+END c08s12b00x00p03n01i01621ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01621arch OF c08s12b00x00p03n01i01621ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p03n01i01621 - Return statement only allowed within the body of a function or procedure." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01621arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1622.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1622.vhd
new file mode 100644
index 0000000..57d3908
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1622.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1622.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01622ent IS
+END c08s12b00x00p03n01i01622ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01622arch OF c08s12b00x00p03n01i01622ent IS
+  return true;      -- illegal in architecture declaration region.
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p03n01i01622 - Return statement only allowed within the body of a function or procedure." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01622arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1623.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1623.vhd
new file mode 100644
index 0000000..3ce69e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1623.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1623.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01623ent IS
+END c08s12b00x00p03n01i01623ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01623arch OF c08s12b00x00p03n01i01623ent IS
+
+BEGIN
+  return true;      -- illegal in architecture statement region.
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p03n01i01623 - Return statement only allowed within the body of a function or procedure." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01623arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1624.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1624.vhd
new file mode 100644
index 0000000..3ac18b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1624.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1624.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s12b00x00p03n01i01624pkg is
+  return true;                          -- illegal in package spec
+end c08s12b00x00p03n01i01624pkg;
+
+ENTITY c08s12b00x00p03n01i01624ent IS
+END c08s12b00x00p03n01i01624ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01624arch OF c08s12b00x00p03n01i01624ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p03n01i01624 - Return statement only allowed within the body of a function or procedure." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01624arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1625.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1625.vhd
new file mode 100644
index 0000000..14111ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1625.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1625.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c08s12b00x00p03n01i01625pkg is
+end c08s12b00x00p03n01i01625pkg;
+
+package body c08s12b00x00p03n01i01625pkg is
+  return true;                          -- illegal in package
+  body
+end c08s12b00x00p03n01i01625pkg;
+
+ENTITY c08s12b00x00p03n01i01625ent IS
+END c08s12b00x00p03n01i01625ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01625arch OF c08s12b00x00p03n01i01625ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p03n01i01625 - Return statement only allowed within the body of a function or procedure." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01625arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1626.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1626.vhd
new file mode 100644
index 0000000..6a28151
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1626.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1626.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01626ent IS
+END c08s12b00x00p03n01i01626ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01626arch OF c08s12b00x00p03n01i01626ent IS
+
+BEGIN
+
+  B1: block
+  begin
+    return true;                      -- illegal in block statement
+  end block B1;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p03n01i01626 - Return statement only allowed within the body of a function or procedure." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01626arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1627.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1627.vhd
new file mode 100644
index 0000000..1ca9109
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1627.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1627.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01627ent IS
+END c08s12b00x00p03n01i01627ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01627arch OF c08s12b00x00p03n01i01627ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+    return true;         -- illegal in a process statement
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p03n01i01627 - Return statement only allowed within the body of a function or procedure." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01627arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1628.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1628.vhd
new file mode 100644
index 0000000..a3ffa29
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1628.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1628.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p03n01i01628ent IS
+END c08s12b00x00p03n01i01628ent;
+
+ARCHITECTURE c08s12b00x00p03n01i01628arch OF c08s12b00x00p03n01i01628ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+
+    L1: for b in boolean loop
+      return true;                  -- illegal in loop statement
+    end loop L1;
+
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p03n01i01628 - Return statement only allowed within the body of a function or procedure." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p03n01i01628arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1629.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1629.vhd
new file mode 100644
index 0000000..47c3b0a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1629.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1629.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p04n01i01629ent IS
+END c08s12b00x00p04n01i01629ent;
+
+ARCHITECTURE c08s12b00x00p04n01i01629arch OF c08s12b00x00p04n01i01629ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 0;
+    procedure return_exp_check is
+    begin
+      i := 10;
+      return i;
+    end;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p04n01i01629 - A return statement in a procedure may not have an expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p04n01i01629arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1631.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1631.vhd
new file mode 100644
index 0000000..23dd730
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1631.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1631.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p04n02i01631ent IS
+END c08s12b00x00p04n02i01631ent;
+
+ARCHITECTURE c08s12b00x00p04n02i01631arch OF c08s12b00x00p04n02i01631ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function return_exp_check return integer is
+      variable k : integer := 0;
+    begin
+      k := 10;
+      return;
+    end;
+    variable i : integer := 0;
+  BEGIN
+    i := return_exp_check;
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p04n02i01631 - Return statement in a function must have an expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p04n02i01631arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1632.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1632.vhd
new file mode 100644
index 0000000..db1ae28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1632.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1632.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p05n01i01632ent IS
+END c08s12b00x00p05n01i01632ent;
+
+ARCHITECTURE c08s12b00x00p05n01i01632arch OF c08s12b00x00p05n01i01632ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function f1(in1:real) return integer is
+    begin
+      return(1.2);
+    end f1;
+    variable k : integer := 0;
+  BEGIN
+    k := f1(1.5);
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p05n01i01632 - The return type must be the same base tyep declared in the specification of the function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n01i01632arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1638.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1638.vhd
new file mode 100644
index 0000000..09cb72e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1638.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1638.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p05n03i01638ent IS
+END c08s12b00x00p05n03i01638ent;
+
+ARCHITECTURE c08s12b00x00p05n03i01638arch OF c08s12b00x00p05n03i01638ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function f1(in1:real) return integer is
+    begin
+      exit;
+    end;
+    variable k : integer := 0;
+  BEGIN
+    k := f1(1.2);
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p05n03i01638 - A function must be completed by a return statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p05n03i01638arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1640.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1640.vhd
new file mode 100644
index 0000000..83cc2f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1640.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1640.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s12b00x00p06n01i01640ent IS
+END c08s12b00x00p06n01i01640ent;
+
+ARCHITECTURE c08s12b00x00p06n01i01640arch OF c08s12b00x00p06n01i01640ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function ts (x1:bit) return integer is
+    begin
+      return ('1');
+    end ts;
+    variable k : integer := 0;
+  BEGIN
+    k := ts('1');   
+    assert FALSE 
+      report "***FAILED TEST: c08s12b00x00p06n01i01640 - Value of the expression is of different subtype." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s12b00x00p06n01i01640arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1645.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1645.vhd
new file mode 100644
index 0000000..496f973
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1645.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1645.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s13b00x00p02n01i01645ent IS
+END c08s13b00x00p02n01i01645ent;
+
+ARCHITECTURE c08s13b00x00p02n01i01645arch OF c08s13b00x00p02n01i01645ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    NULL
+      assert FALSE
+      report "***FAILED TEST: c08s13b00x00p02n01i01645 - Missing semicolon in the null statement"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s13b00x00p02n01i01645arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc165.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc165.vhd
new file mode 100644
index 0000000..eb30a1a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc165.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc165.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x02p23n01i00165ent IS
+  PORT (SIGNAL a    : IN bit;
+        SIGNAL b    : IN integer;
+        SIGNAL c    : IN boolean;
+        SIGNAL d    : IN time;
+        SIGNAL e    : IN real;
+        SIGNAL oint    : INOUT integer);
+END c04s03b02x02p23n01i00165ent;
+
+ARCHITECTURE c04s03b02x02p23n01i00165arch OF c04s03b02x02p23n01i00165ent IS
+  function funct1(   fpar1   :bit      :='1';
+                     fpar2   :integer   :=455;
+                     fpar3   :boolean   :=true;
+                     fpar4   :time      :=55.77 ns;
+                     fpar5   :real      :=34.558) return integer is
+  begin
+    return 1;
+  end funct1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    oint <= funct1(a,b,,d,e);
+    assert FALSE
+      report "***FAILED TEST: c04s03b02x02p23n01i00165 - Positional association list is not allowed after the default expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x02p23n01i00165arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1652.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1652.vhd
new file mode 100644
index 0000000..6260569
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1652.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1652.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s00b00x00p02n01i01652ent IS
+END c09s00b00x00p02n01i01652ent;
+
+ARCHITECTURE c09s00b00x00p02n01i01652arch OF c09s00b00x00p02n01i01652ent IS
+  signal S1 : integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <=    0;
+    ;
+    assert FALSE 
+      report "***FAILED TEST: c09s00b00x00p02n01i01652 - An empty statement is not permitted in a set of statements."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s00b00x00p02n01i01652arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1656.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1656.vhd
new file mode 100644
index 0000000..cf90fab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1656.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1656.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p02n01i01656ent IS
+END c09s01b00x00p02n01i01656ent;
+
+ARCHITECTURE c09s01b00x00p02n01i01656arch OF c09s01b00x00p02n01i01656ent IS
+
+BEGIN
+
+  block                         -- block label required, but missing
+  begin
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p02n01i01656 - Block label is required for block statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p02n01i01656arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1657.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1657.vhd
new file mode 100644
index 0000000..396d497
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1657.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1657.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p02n01i01657ent IS
+END c09s01b00x00p02n01i01657ent;
+
+ARCHITECTURE c09s01b00x00p02n01i01657arch OF c09s01b00x00p02n01i01657ent IS
+
+BEGIN
+
+  lab : block ( )                   --guard condition must not be empty 
+  begin
+  end block lab;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p02n01i01657 - Guard condition must not be empty." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p02n01i01657arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1660.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1660.vhd
new file mode 100644
index 0000000..04f81cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1660.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1660.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p02n01i01660ent IS
+END c09s01b00x00p02n01i01660ent;
+
+ARCHITECTURE c09s01b00x00p02n01i01660arch OF c09s01b00x00p02n01i01660ent IS
+
+BEGIN
+
+  B:block
+    signal D: BIT;
+  begin
+    D <= '1';
+  end;           -- Failure_here
+  -- The reserved word block expected.
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p02n01i01660 - The reserved word block expected." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p02n01i01660arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1661.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1661.vhd
new file mode 100644
index 0000000..3666185
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1661.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1661.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p02n01i01661ent IS
+END c09s01b00x00p02n01i01661ent;
+
+ARCHITECTURE c09s01b00x00p02n01i01661arch OF c09s01b00x00p02n01i01661ent IS
+
+BEGIN
+
+  B:block
+    signal D: BIT;
+  begin
+    D <= '1';
+  end block           -- Failure_here
+
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c09s01b00x00p02n01i01661 - Semicolon expected." 
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+    END c09s01b00x00p02n01i01661arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1663.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1663.vhd
new file mode 100644
index 0000000..fc0a2c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1663.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1663.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p03n01i01663ent IS
+  port (A, B: inout bit);
+END c09s01b00x00p03n01i01663ent;
+
+ARCHITECTURE c09s01b00x00p03n01i01663arch OF c09s01b00x00p03n01i01663ent IS
+  signal       S1, S2, S3   : bit       := '0';
+BEGIN
+
+  BL: block                          
+    port map    (S1, S2); --Failure_here
+  begin
+  end block BL;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p03n01i01663 - A port map can not appear without being preceded by a port clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p03n01i01663arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1664.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1664.vhd
new file mode 100644
index 0000000..341a3a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1664.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1664.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p04n01i01664ent IS
+END c09s01b00x00p04n01i01664ent;
+
+ARCHITECTURE c09s01b00x00p04n01i01664arch OF c09s01b00x00p04n01i01664ent IS
+
+BEGIN
+  BBB: block
+    variable v: integer;   --  Failure_here
+  begin
+  end block;   
+  
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p04n01i01664 - A variable declaration is not allowed in a block declarative part."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p04n01i01664arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1666.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1666.vhd
new file mode 100644
index 0000000..bd4f432
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1666.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1666.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p05n01i01666ent IS
+END c09s01b00x00p05n01i01666ent;
+
+ARCHITECTURE c09s01b00x00p05n01i01666arch OF c09s01b00x00p05n01i01666ent IS
+
+BEGIN
+  B:block
+    signal A: BIT;
+  begin
+    if A then     -- Failure_here
+      -- Sequential statement not allowed.
+    end if;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p05n01i01666 - Sequential statement not allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p05n01i01666arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1667.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1667.vhd
new file mode 100644
index 0000000..b77ca3a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1667.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1667.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p05n01i01667ent IS
+END c09s01b00x00p05n01i01667ent;
+
+ARCHITECTURE c09s01b00x00p05n01i01667arch OF c09s01b00x00p05n01i01667ent IS
+
+BEGIN
+  B:block
+    variable err : boolean := true;   -- illegal location for variable decl
+  begin
+    err := true;                      -- illegal location for variable assignment
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p05n01i01667 - Sequential statement not allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p05n01i01667arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1668.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1668.vhd
new file mode 100644
index 0000000..e0f22ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1668.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1668.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p05n01i01668ent IS
+END c09s01b00x00p05n01i01668ent;
+
+ARCHITECTURE c09s01b00x00p05n01i01668arch OF c09s01b00x00p05n01i01668ent IS
+
+BEGIN
+  B:block
+    signal err : boolean := true;
+  begin
+    case err is                       -- illegal location for case statement
+      when true | false =>
+        assert false
+          report "'case' statement accepted in an entity statement."
+          severity note ;
+    end case;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p05n01i01668 - Sequential statement not allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p05n01i01668arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1669.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1669.vhd
new file mode 100644
index 0000000..0d96119
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1669.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1669.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p05n01i01669ent IS
+END c09s01b00x00p05n01i01669ent;
+
+ARCHITECTURE c09s01b00x00p05n01i01669arch OF c09s01b00x00p05n01i01669ent IS
+
+BEGIN
+  B:block
+
+  begin
+    L: loop              -- illegal location for loop statement
+    end loop L;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p05n01i01669 - Sequential statement not allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p05n01i01669arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1670.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1670.vhd
new file mode 100644
index 0000000..a40df38
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1670.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1670.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p05n01i01670ent IS
+END c09s01b00x00p05n01i01670ent;
+
+ARCHITECTURE c09s01b00x00p05n01i01670arch OF c09s01b00x00p05n01i01670ent IS
+
+BEGIN
+  B:block
+
+  begin
+    next;                  -- illegal location for next statement
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p05n01i01670 - Sequential statement not allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p05n01i01670arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1671.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1671.vhd
new file mode 100644
index 0000000..e1e377b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1671.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1671.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p05n01i01671ent IS
+END c09s01b00x00p05n01i01671ent;
+
+ARCHITECTURE c09s01b00x00p05n01i01671arch OF c09s01b00x00p05n01i01671ent IS
+
+BEGIN
+  B:block
+
+  begin
+    exit;                             -- illegal location for exit statement
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p05n01i01671 - Sequential statement not allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p05n01i01671arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1672.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1672.vhd
new file mode 100644
index 0000000..91128c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1672.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1672.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p05n01i01672ent IS
+END c09s01b00x00p05n01i01672ent;
+
+ARCHITECTURE c09s01b00x00p05n01i01672arch OF c09s01b00x00p05n01i01672ent IS
+
+BEGIN
+  B:block
+
+  begin
+    return;                        -- illegal location for return statement
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p05n01i01672 - Sequential statement not allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p05n01i01672arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1673.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1673.vhd
new file mode 100644
index 0000000..d43a495
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1673.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1673.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p05n01i01673ent IS
+END c09s01b00x00p05n01i01673ent;
+
+ARCHITECTURE c09s01b00x00p05n01i01673arch OF c09s01b00x00p05n01i01673ent IS
+
+BEGIN
+  B:block
+
+  begin
+    null;                   -- illegal location for null statement
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p05n01i01673 - Sequential statement not allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p05n01i01673arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1674.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1674.vhd
new file mode 100644
index 0000000..a747416
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1674.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1674.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p06n02i01674ent IS
+  generic (   width:      Positive);
+  port (      inword: in  Bit_Vector (width-1 downto 0);
+              load:   in  Bit;
+              outword:out Bit_Vector (width-1 downto 0));
+END c09s01b00x00p06n02i01674ent;
+
+ARCHITECTURE c09s01b00x00p06n02i01674arch OF c09s01b00x00p06n02i01674ent IS
+
+BEGIN
+
+  B: block (1 + 2 + 3) -- Failure_here
+  begin
+    outword <= guarded inword after 10 ns;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p06n02i01674 - Guard expression can not be the type of integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p06n02i01674arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1676.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1676.vhd
new file mode 100644
index 0000000..04211d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1676.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1676.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p07n01i01676ent IS
+  port (p: in boolean);
+END c09s01b00x00p07n01i01676ent;
+
+ARCHITECTURE c09s01b00x00p07n01i01676arch OF c09s01b00x00p07n01i01676ent IS
+
+BEGIN
+
+  B: block (p)
+  begin
+    GUARD <= p;  -- Failure_here
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p07n01i01676 - Implicit signal GUARD can not have a source."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p07n01i01676arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1680.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1680.vhd
new file mode 100644
index 0000000..459558c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1680.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1680.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s01b00x00p09n01i01680ent IS
+END c09s01b00x00p09n01i01680ent;
+
+ARCHITECTURE c09s01b00x00p09n01i01680arch OF c09s01b00x00p09n01i01680ent IS
+
+BEGIN
+
+  lab : block
+  begin
+  end block lab2;                       -- labels must match, but don't
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s01b00x00p09n01i01680 - Labels appears at the end of a block statement must match the block label."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s01b00x00p09n01i01680arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1682.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1682.vhd
new file mode 100644
index 0000000..c7d2d24
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1682.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1682.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p02n01i01682ent IS
+END c09s02b00x00p02n01i01682ent;
+
+ARCHITECTURE c09s02b00x00p02n01i01682arch OF c09s02b00x00p02n01i01682ent IS
+
+BEGIN
+  TESTING: PROCESS(   )
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p02n01i01682 - Empty sensitivity list is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p02n01i01682arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1683.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1683.vhd
new file mode 100644
index 0000000..737b1a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1683.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1683.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p02n01i01683ent IS
+  port (A : bit);
+END c09s02b00x00p02n01i01683ent;
+
+ARCHITECTURE c09s02b00x00p02n01i01683arch OF c09s02b00x00p02n01i01683ent IS
+  signal   B : bit;
+BEGIN
+  TESTING PROCESS( A  )    -- Failure here
+            -- Colon is missing
+          BEGIN
+            B <= A;
+            assert FALSE 
+              report "***FAILED TEST: c09s02b00x00p02n01i01683 - Colon is missing between the label and the reserved word process." 
+              severity ERROR;
+          END PROCESS TESTING;
+
+          END c09s02b00x00p02n01i01683arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1685.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1685.vhd
new file mode 100644
index 0000000..bcf7a6c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1685.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1685.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p02n01i01685ent IS
+  port (A : bit);
+END c09s02b00x00p02n01i01685ent;
+
+ARCHITECTURE c09s02b00x00p02n01i01685arch OF c09s02b00x00p02n01i01685ent IS
+  signal B : bit;
+BEGIN
+
+  P1:process (A)
+  begin
+    B <= A;
+  end ;     -- Failure_here
+  -- the reserved word 'process' expected.
+  
+  TESTING : PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p02n01i01685 - Reserved word process is missing after the reserved word end." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p02n01i01685arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1686.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1686.vhd
new file mode 100644
index 0000000..561d2b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1686.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1686.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p02n01i01686ent IS
+  port (A : bit);
+END c09s02b00x00p02n01i01686ent;
+
+ARCHITECTURE c09s02b00x00p02n01i01686arch OF c09s02b00x00p02n01i01686ent IS
+  signal B : bit;
+BEGIN
+
+  P1:process (A)
+  begin
+    B <= A;
+  end process P1     -- Failure_here
+    -- Semicolon is missing.
+    
+    TESTING : PROCESS
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c09s02b00x00p02n01i01686 - Semicolon is missing at the end of a process statement." 
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+    END c09s02b00x00p02n01i01686arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1687.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1687.vhd
new file mode 100644
index 0000000..253e6cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1687.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1687.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01687ent IS
+  port (B:Bit);
+END c09s02b00x00p03n01i01687ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01687arch OF c09s02b00x00p03n01i01687ent IS
+
+BEGIN
+  TESTING: PROCESS(B)
+    component C1 port ( B : BIT ); -- illegal: no component declaration here
+    end component ;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p03n01i01687 - Component declarations are not permitted in process statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p03n01i01687arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1688.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1688.vhd
new file mode 100644
index 0000000..bb09bca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1688.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1688.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01688ent IS
+  port (B:Bit);
+END c09s02b00x00p03n01i01688ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01688arch OF c09s02b00x00p03n01i01688ent IS
+
+BEGIN
+  TESTING: PROCESS(B)
+    signal S : Bit; --illegal: no signal declaration here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p03n01i01688 - Signal declarations are not permitted in process statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p03n01i01688arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1689.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1689.vhd
new file mode 100644
index 0000000..f124ccb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1689.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1689.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01689ent IS
+  port (B:Bit);
+END c09s02b00x00p03n01i01689ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01689arch OF c09s02b00x00p03n01i01689ent IS
+  component C1 port ( B : BIT );
+  end component ;
+  signal S1 : BIT ;
+BEGIN
+  TESTING: PROCESS(B)
+    for all : C1 use entity work.E -- illegal: no configuration spec here
+    port map ( S1 => B ) ;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p03n01i01689 - Configuration  declarations are not permitted in process statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p03n01i01689arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1692.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1692.vhd
new file mode 100644
index 0000000..527cf73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1692.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1692.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01692ent IS
+  port (B:BIT; C:out BIT) ;   
+END c09s02b00x00p03n01i01692ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01692arch OF c09s02b00x00p03n01i01692ent IS
+
+BEGIN
+  process
+    port map (X=>I1, Y => i2); -- Failure_here
+    -- SEMANTICS ERROR: interface declaration may not
+    -- be in a process statement
+  begin
+    null;
+  end process;   
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p03n01i01692 - Interface declarations are not allowed in process statements." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p03n01i01692arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1693.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1693.vhd
new file mode 100644
index 0000000..db3a079
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1693.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1693.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01693ent IS
+  port (B:BIT; C:out BIT) ;   
+END c09s02b00x00p03n01i01693ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01693arch OF c09s02b00x00p03n01i01693ent IS
+
+BEGIN
+  process
+  begin
+    architecture B6 of E1 is -- Failure_here
+      --SEMANTICS ERROR: body declarations may not be in a process statement.
+    begin
+      process
+      begin
+        null;
+      end process;
+    end B6;
+    null;
+    end process;   
+
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c09s02b00x00p03n01i01693 - Body declarations are not allowed in process statements." 
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+    END c09s02b00x00p03n01i01693arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1694.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1694.vhd
new file mode 100644
index 0000000..3d50d6c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1694.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1694.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01694ent IS
+END c09s02b00x00p03n01i01694ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01694arch OF c09s02b00x00p03n01i01694ent IS
+
+BEGIN
+  TEST_PROCESS:  process
+    -- Illegal Configuration specification.
+    for all : TEST use entity TEST( TEST_BEHAVIOR );
+  begin
+  end process TEST_PROCESS;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p03n01i01694 - Configuration specifications may not be declared inside a process." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p03n01i01694arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1695.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1695.vhd
new file mode 100644
index 0000000..02917be
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1695.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1695.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p03n01i01695ent IS
+END c09s02b00x00p03n01i01695ent;
+
+ARCHITECTURE c09s02b00x00p03n01i01695arch OF c09s02b00x00p03n01i01695ent IS
+
+BEGIN
+  TEST_PROCESS:  process
+    -- Illegal Disconnection specification.  ERROR:
+    disconnect all : BIT after 0 ns;
+  begin
+  end process TEST_PROCESS;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p03n01i01695 - Disconnection specifications may not be declared inside a process." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p03n01i01695arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1696.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1696.vhd
new file mode 100644
index 0000000..3c26051
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1696.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1696.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p05n01i01696ent IS
+END c09s02b00x00p05n01i01696ent;
+
+ARCHITECTURE c09s02b00x00p05n01i01696arch OF c09s02b00x00p05n01i01696ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    process  -- ERROR:
+    begin
+      wait;
+    end process;
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p05n01i01696 - Process statements are illegal inside the body a process."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p05n01i01696arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1697.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1697.vhd
new file mode 100644
index 0000000..4ebf6bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1697.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1697.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p05n01i01697ent IS
+END c09s02b00x00p05n01i01697ent;
+
+ARCHITECTURE c09s02b00x00p05n01i01697arch OF c09s02b00x00p05n01i01697ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    B:block  -- ERROR:
+    begin
+    end block B;
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p05n01i01697 - Block statements are illegal inside a process."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p05n01i01697arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1699.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1699.vhd
new file mode 100644
index 0000000..c9566e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1699.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1699.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p05n01i01699ent IS
+END c09s02b00x00p05n01i01699ent;
+
+ARCHITECTURE c09s02b00x00p05n01i01699arch OF c09s02b00x00p05n01i01699ent IS
+
+  procedure conc_proc is
+  begin
+    assert false
+      report "Labeled procedure call allowed in process statement."
+      severity note ;
+  end conc_proc;
+
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN               -- only concurrent procedure may be labeled.
+    P1:   conc_proc;            -- illegal location for concurrent procedure
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p05n01i01699 - Process statement can only have sequential statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p05n01i01699arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc170.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc170.vhd
new file mode 100644
index 0000000..05f83fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc170.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc170.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n01i00170ent IS
+END c04s03b03x01p03n01i00170ent;
+
+ARCHITECTURE c04s03b03x01p03n01i00170arch OF c04s03b03x01p03n01i00170ent IS
+  type x is range 1 to 10;
+  signal Addr : bit;
+  alias SIGN1 : x is x; -- fails_here
+  alias SIGN2 : bit is Addr;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST:c04s03b03x01p03n01i00170 - The name referred to in the alias declaration for SIGN1 is not a static name that refers to an object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n01i00170arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1700.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1700.vhd
new file mode 100644
index 0000000..c86a04f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1700.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1700.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p05n01i01700ent IS
+END c09s02b00x00p05n01i01700ent;
+
+ARCHITECTURE c09s02b00x00p05n01i01700arch OF c09s02b00x00p05n01i01700ent IS
+
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN               
+    --
+    -- Test concurrent assertion statement
+    -- Note: only the concurrent version may be labeled
+    --
+    A1: assert false               -- illegal location for assert statement
+      report "Labeled assertion allowed in process statement."
+      severity note ;
+
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p05n01i01700 - Process statement can only have sequential statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p05n01i01700arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1701.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1701.vhd
new file mode 100644
index 0000000..4274e16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1701.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1701.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p05n01i01701ent IS
+END c09s02b00x00p05n01i01701ent;
+
+ARCHITECTURE c09s02b00x00p05n01i01701arch OF c09s02b00x00p05n01i01701ent IS
+  signal b_sig : boolean := true;
+BEGIN
+
+  TESTING: PROCESS
+    variable trigger : integer := 0;
+  BEGIN               
+    --
+    -- Test concurrent conditional signal assignment
+    --
+    b_sig <= false when trigger = 0 else -- illegal loc for conc statement
+             true;
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p05n01i01701 - Process statement can only have sequential statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p05n01i01701arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1702.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1702.vhd
new file mode 100644
index 0000000..b91f468
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1702.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1702.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p05n01i01702ent IS
+END c09s02b00x00p05n01i01702ent;
+
+ARCHITECTURE c09s02b00x00p05n01i01702arch OF c09s02b00x00p05n01i01702ent IS
+  signal b_sig : boolean := true;
+BEGIN
+
+  TESTING: PROCESS
+    variable trigger : integer := 0;
+  BEGIN               
+    --
+    -- Test concurrent selected signal assignment
+    --
+    with trigger select     -- illegal concurrent selected signal assignment
+            b_sig <= false when 0
+                     true  when others;
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p05n01i01702 - Process statement can only have sequential statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p05n01i01702arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1706.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1706.vhd
new file mode 100644
index 0000000..5cfe837
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1706.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1706.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p07n01i01706ent IS
+END c09s02b00x00p07n01i01706ent;
+
+ARCHITECTURE c09s02b00x00p07n01i01706arch OF c09s02b00x00p07n01i01706ent IS
+  signal   b_sig   : boolean   := true;
+BEGIN
+  TESTING: PROCESS( b_sig )
+  BEGIN
+    wait on b_sig;       -- illegal location for wait statement
+
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p07n01i01706 - Wait statement in process with explicitly sensitivity list is illegal." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s02b00x00p07n01i01706arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1712.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1712.vhd
new file mode 100644
index 0000000..5f18af5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1712.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1712.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p10n01i01712ent IS
+  port    (signal max : in natural);
+
+  type    word      is array (natural range <>) of bit;
+  subtype    mem_array is word (0 to 7);
+END c09s02b00x00p10n01i01712ent;
+
+ARCHITECTURE c09s02b00x00p10n01i01712arch OF c09s02b00x00p10n01i01712ent IS
+  signal idx : natural;
+  signal mem : mem_array;
+BEGIN
+  TESTING: PROCESS(mem(0 to idx))
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p10n01i01712 - Process sensitivity list with array slices bounded can not be a varialbe." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s02b00x00p10n01i01712arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1713.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1713.vhd
new file mode 100644
index 0000000..8a6992c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1713.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1713.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p10n01i01713ent IS
+  port    (signal max : in natural);
+
+  type    word      is array (natural range <>) of bit;
+  subtype    mem_array is word (0 to 7);
+END c09s02b00x00p10n01i01713ent;
+
+ARCHITECTURE c09s02b00x00p10n01i01713arch OF c09s02b00x00p10n01i01713ent IS
+  signal idx : natural;
+  signal mem : mem_array;
+BEGIN
+  TESTING: PROCESS(mem_array'(others => '1'))
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p10n01i01713 - Process sensitivity list can not be a qualified aggregate." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s02b00x00p10n01i01713arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1714.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1714.vhd
new file mode 100644
index 0000000..3330f1d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1714.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1714.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p10n01i01714ent IS
+  port    (signal max : in natural);
+
+  type    word      is array (natural range <>) of bit;
+  subtype    mem_array is word (0 to 7);
+END c09s02b00x00p10n01i01714ent;
+
+ARCHITECTURE c09s02b00x00p10n01i01714arch OF c09s02b00x00p10n01i01714ent IS
+  signal idx : natural;
+  signal mem : mem_array;
+BEGIN
+  TESTING: PROCESS(bit_vector'("10101"))
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p10n01i01714 - Process sensitivity list can not be a qualified string." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s02b00x00p10n01i01714arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1715.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1715.vhd
new file mode 100644
index 0000000..eb08164
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1715.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1715.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p10n01i01715ent IS
+  port (signal max : in  natural;
+        signal mox : out natural);
+END c09s02b00x00p10n01i01715ent;
+
+ARCHITECTURE c09s02b00x00p10n01i01715arch OF c09s02b00x00p10n01i01715ent IS
+
+BEGIN
+  TESTING: PROCESS(mox)
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p10n01i01715 - Signal with mode OUT can not be list in sensitivity list." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s02b00x00p10n01i01715arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1716.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1716.vhd
new file mode 100644
index 0000000..c9097d1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1716.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1716.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p11n02i01716ent IS
+END c09s02b00x00p11n02i01716ent;
+
+ARCHITECTURE c09s02b00x00p11n02i01716arch OF c09s02b00x00p11n02i01716ent IS
+
+BEGIN
+  TESTIN: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p11n02i01716 - The label appear at the end of a process statement, it must repeat the process label."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s02b00x00p11n02i01716arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1722.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1722.vhd
new file mode 100644
index 0000000..fa82f55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1722.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1722.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p03n01i01722ent IS
+END c12s06b01x00p03n01i01722ent;
+
+ARCHITECTURE c12s06b01x00p03n01i01722arch OF c12s06b01x00p03n01i01722ent IS
+  signal k : bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    k <= ;
+    assert FALSE 
+      report "***FAILED TEST: c12s06b01x00p03n01i01722 - A driver always contains at least one transaction."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p03n01i01722arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1726.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1726.vhd
new file mode 100644
index 0000000..277f46c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1726.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1726.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p04n01i01726ent IS
+END c12s06b01x00p04n01i01726ent;
+
+ARCHITECTURE c12s06b01x00p04n01i01726arch OF c12s06b01x00p04n01i01726ent IS
+  signal clk : bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    --
+    -- The signal assignment below tries to make two
+    -- assignments at the same (current) time.
+    --
+    clk <=    '0' after 20 ns, 
+              '1' after 20 ns;
+    assert FALSE 
+      report "***FAILED TEST: c12s06b01x00p04n01i01726 - The signal assignment can not make two assignment at the same (20 ns) time."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p04n01i01726arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1730.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1730.vhd
new file mode 100644
index 0000000..6fae177
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1730.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1730.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s03b00x00p02n01i01730ent IS
+  port (signal AA,BB: in bit);
+END c09s03b00x00p02n01i01730ent;
+
+ARCHITECTURE c09s03b00x00p02n01i01730arch OF c09s03b00x00p02n01i01730ent IS
+
+  procedure P1 (signal A,B: in bit; signal C: out bit) is
+  begin
+    C <= A and B;
+  end;
+  
+  signal   CC : bit;
+BEGIN
+
+  PROC  P1 (AA,BB,CC);     -- Failure_here
+  -- Colon is misssing   
+
+  assert FALSE 
+    report "***FAILED TEST: c09s03b00x00p02n01i01730 - Colon between the label and a procedure call statement is missing." 
+    severity ERROR;
+
+END c09s03b00x00p02n01i01730arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1731.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1731.vhd
new file mode 100644
index 0000000..5a2f2e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1731.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1731.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s03b00x00p04n01i01731ent IS
+  port (signal  bool : inout boolean := true);
+END c09s03b00x00p04n01i01731ent;
+
+ARCHITECTURE c09s03b00x00p04n01i01731arch OF c09s03b00x00p04n01i01731ent IS
+  procedure var_param ( variable var : inout boolean
+                        ) is
+  begin
+    var := false;
+  end var_param;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    var_param(bool);
+    assert FALSE 
+      report "***FAILED TEST: c09s03b00x00p04n01i01731 - Illegal variable formal parameter in procedure call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s03b00x00p04n01i01731arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc174.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc174.vhd
new file mode 100644
index 0000000..96988b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc174.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc174.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n02i00174ent IS
+END c04s03b03x01p03n02i00174ent;
+
+ARCHITECTURE c04s03b03x01p03n02i00174arch OF c04s03b03x01p03n02i00174ent IS
+  signal    Data    : integer;
+  alias    SIGN    : bit is Data;  -- Failure_here
+  -- Data is of type integer and not bit
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    Data   <= 100 after 50 ns;
+    wait for 50 ns;
+    assert FALSE
+      report "***FAILED TEST: c04s03b03x01p03n02i00174 - Alias base type does not match subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n02i00174arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1741.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1741.vhd
new file mode 100644
index 0000000..1b29cd1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1741.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1741.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p02n01i01741ent IS
+  port (clk : inout bit);
+END c09s05b00x00p02n01i01741ent;
+
+ARCHITECTURE c09s05b00x00p02n01i01741arch OF c09s05b00x00p02n01i01741ent IS
+  constant   period : Time := 50 ns;
+BEGIN
+  osc  clk <= not clk after period/2;    -- Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b00x00p02n01i01741 - Colon is missing between the label and concurrent signal assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b00x00p02n01i01741arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1742.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1742.vhd
new file mode 100644
index 0000000..12f080b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1742.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1742.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p03n01i01742ent IS
+END c09s05b00x00p03n01i01742ent;
+
+ARCHITECTURE c09s05b00x00p03n01i01742arch OF c09s05b00x00p03n01i01742ent IS
+  signal   err : bit;
+BEGIN
+  err   <= transport guarded '1';   
+  assert FALSE 
+    report "***FAILED TEST: c09s05b00x00p03n01i01742 - Guarded must appear precede transport."
+    severity ERROR;
+
+END c09s05b00x00p03n01i01742arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1743.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1743.vhd
new file mode 100644
index 0000000..93d5093
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1743.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1743.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p03n01i01743ent IS
+END c09s05b00x00p03n01i01743ent;
+
+ARCHITECTURE c09s05b00x00p03n01i01743arch OF c09s05b00x00p03n01i01743ent IS
+  signal   err : bit;
+BEGIN
+  B : block
+  begin
+    err   <= transport guarded '1';   
+    assert FALSE 
+      report "***FAILED TEST: c09s05b00x00p03n01i01743 - Reserved word guarded must appear precede transport."
+      severity ERROR;
+  end block B;
+
+END c09s05b00x00p03n01i01743arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1746.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1746.vhd
new file mode 100644
index 0000000..3000f21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1746.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1746.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p06n03i01746ent IS
+END c09s05b00x00p06n03i01746ent;
+
+ARCHITECTURE c09s05b00x00p06n03i01746arch OF c09s05b00x00p06n03i01746ent IS
+  type a       is array (1 to 4) of boolean;
+  type arrbool    is array (positive range <>) of boolean;
+
+  function F (BB: arrbool) return boolean is
+  begin
+    return false;
+  end;
+  
+  signal i, j :  F boolean bus    := true;
+  signal k, l :    boolean    := true;
+  signal m    : a    := (true, false, true, false);
+BEGIN
+  (i, j, k, l) <= transport a'(m(1), m(2), m(3), m(4)) after 10 ns;
+  --  Failure_here
+  --  i and j are guarded signals and k and l are unguarded signals.
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b00x00p06n03i01746 - Guarded signal and Ungarded signal is mixed used."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b00x00p06n03i01746arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc175.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc175.vhd
new file mode 100644
index 0000000..03c74ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc175.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc175.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n02i00175ent IS
+END c04s03b03x01p03n02i00175ent;
+
+ARCHITECTURE c04s03b03x01p03n02i00175arch OF c04s03b03x01p03n02i00175ent IS
+  signal    Addr    : bit;
+  alias    SIGN1    : integer is Addr;     -- Failure_here
+                                           -- error as Addr is of type bit
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert FALSE
+      report "***FAILED TEST: c04s03b03x01p03n02i00175 - Alias base type does not match subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n02i00175arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1750.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1750.vhd
new file mode 100644
index 0000000..2cf75de
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1750.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1750.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p21n01i01750ent IS
+  generic (g1: integer := 12);
+  port (
+    input1: in  bit ;
+    input2: in  bit ;
+    clk   : in  boolean;
+    output: out bit);
+END c09s05b00x00p21n01i01750ent;
+
+ARCHITECTURE c09s05b00x00p21n01i01750arch OF c09s05b00x00p21n01i01750ent IS
+  type boolvec is array (positive range <>) of boolean;
+  function F (BB: boolvec) return boolean is
+  begin
+    return TRUE;
+  end;
+  
+  signal i :  F boolean bus;
+  signal k :  boolean ;
+BEGIN
+  i <= transport k;  -- Failure_here
+  -- i is a guarded target while the statement is not a guarded assignment
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b00x00p21n01i01750 - Ungarded signal can not assign to a guarded signal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b00x00p21n01i01750arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1751.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1751.vhd
new file mode 100644
index 0000000..fa6d707
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1751.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1751.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p25n01i01751ent IS
+END c09s05b00x00p25n01i01751ent;
+
+ARCHITECTURE c09s05b00x00p25n01i01751arch OF c09s05b00x00p25n01i01751ent IS
+  type a       is array (1 to 4) of boolean;
+  type arr_bvec    is array (positive range <>) of a;
+
+  function F (AB: arr_bvec) return a is
+  begin
+    return (true,true,true,true);
+  end;
+  
+  signal G    : bit;
+  signal i       : F a bus;
+  signal m   : a := (true, false, true, false);
+  constant c1, c2 : integer := 1;
+BEGIN
+  G <= '1' after 10 ns;
+
+  B1: block(G = '1')
+  begin
+    (i(1), i(2), i(3), i(4))    <= guarded a'(true, false, false, true);
+    (i(c1), i(c2), i(3), i(4))    <= guarded a'(true, false, false, true);
+    -- Failure_here :  i(c1) and i(c2) are same signal names        
+    (i(1), i(2), i(3), i(1))    <= guarded a'(true, false, false, true);
+    -- Failure_here : i(1) appears twice
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 50 ns;
+    assert FALSE 
+      report "***FAILED TEST: c09s05b00x00p25n01i01751 - No two signal names may identify the same object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b00x00p25n01i01751arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1752.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1752.vhd
new file mode 100644
index 0000000..671f702
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1752.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1752.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p25n01i01752ent IS
+  generic (g1: integer := 12);
+  port (
+    input1: in  bit ;
+    input2: in  bit ;
+    clk   : in  boolean;
+    output: out bit);
+END c09s05b00x00p25n01i01752ent;
+
+ARCHITECTURE c09s05b00x00p25n01i01752arch OF c09s05b00x00p25n01i01752ent IS
+  type a is array (1 to 4) of boolean;
+  signal i    :  a;
+BEGIN
+  (i(g1), i(2), i(3), i(4)) <= a'(true, false, false, true);
+  -- Failure_here : i(g1) is not a locally static name
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b00x00p25n01i01752 - Only locally static signal names may contain here." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b00x00p25n01i01752arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1754.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1754.vhd
new file mode 100644
index 0000000..d2542bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1754.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1754.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p26n01i01754ent IS
+END c09s05b00x00p26n01i01754ent;
+
+ARCHITECTURE c09s05b00x00p26n01i01754arch OF c09s05b00x00p26n01i01754ent IS
+  signal   err : bit;
+BEGIN
+  B : block
+  BEGIN
+    err <= null;
+    assert FALSE 
+      report "***FAILED TEST: c09s05b00x00p26n01i01754 - Null waveform element can not appear in a waveform of a concurrent signal assignment statement."
+      severity ERROR;
+  END block B;
+
+END c09s05b00x00p26n01i01754arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1755.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1755.vhd
new file mode 100644
index 0000000..e65d893
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1755.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1755.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b00x00p26n01i01755ent IS
+END c09s05b00x00p26n01i01755ent;
+
+ARCHITECTURE c09s05b00x00p26n01i01755arch OF c09s05b00x00p26n01i01755ent IS
+  signal   err : bit;
+BEGIN
+  err <= null;
+  assert FALSE 
+    report "***FAILED TEST: c09s05b00x00p26n01i01755 - Null waveform element can not appear in a waveform of a concurrent signal assignment statement."
+    severity ERROR;
+
+END c09s05b00x00p26n01i01755arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1758.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1758.vhd
new file mode 100644
index 0000000..91d7a5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1758.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1758.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b01x00p02n01i01758ent IS
+END c09s05b01x00p02n01i01758ent;
+
+ARCHITECTURE c09s05b01x00p02n01i01758arch OF c09s05b01x00p02n01i01758ent IS
+  signal   A,B   : bit;
+BEGIN
+  CONSIG: A <= transport '1' when B = '1' else
+               transport '0';    -- Failure_here
+  -- an option not allowed.
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b01x00p02n01i01758 - An option can not insert in conditional waveforms."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b01x00p02n01i01758arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1759.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1759.vhd
new file mode 100644
index 0000000..c588d74
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1759.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1759.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b01x00p03n01i01759ent IS
+  generic (g1: integer := 12);
+  port (
+    input1: in  bit ;
+    input2: in  bit ;
+    clk   : in  boolean;
+    output: out bit);
+END c09s05b01x00p03n01i01759ent;
+
+ARCHITECTURE c09s05b01x00p03n01i01759arch OF c09s05b01x00p03n01i01759ent IS
+  signal local    : boolean;
+  signal local1    : boolean;
+BEGIN
+  local1 <=    not (clk)    when local    = true    else
+               not (local)    when clk    = false else
+               clk       when local    = false else
+               local       when clk    = true    else
+               not (clk) or not (local) when clk = true; -- Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b01x00p03n01i01759 - A conditional signal assignment can not end with a condition."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b01x00p03n01i01759arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1760.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1760.vhd
new file mode 100644
index 0000000..1343cd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1760.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1760.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b01x00p21n01i01760ent IS
+  port (PT: inout integer; PT2: inout character); 
+END c09s05b01x00p21n01i01760ent;
+
+ARCHITECTURE c09s05b01x00p21n01i01760arch OF c09s05b01x00p21n01i01760ent IS
+  signal S1, S2 : boolean;
+BEGIN
+  PT <=    5 when S1 /= S2 else
+           6 when S1 > S2 else
+           7 when S1 + S2 else  -- Failure_here
+           --ERROR conditions must be like those of
+           -- an if statement in a process statement
+           9;
+
+  PT2 <=    'A' when S1 - S2 else  -- Failure_here
+            --ERROR the waveform must be like if statement
+            -- in a process statement.
+            'B' when S2 = S2 else
+            'C' ;
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b01x00p21n01i01760 - The if statement must be such that it is in a process statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b01x00p21n01i01760arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1764.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1764.vhd
new file mode 100644
index 0000000..3a7051c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1764.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1764.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p02n01i01764ent IS
+END c09s05b02x00p02n01i01764ent;
+
+ARCHITECTURE c09s05b02x00p02n01i01764arch OF c09s05b02x00p02n01i01764ent IS
+  signal TS: integer;
+  signal B: bit;
+BEGIN
+
+  with B
+    TS <= transport 1 when '0',  -- Failure_here
+    -- the reserved word 'select' is missing
+    2 when '1';
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b02x00p02n01i01764 - the reserved word select is missing."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b02x00p02n01i01764arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1765.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1765.vhd
new file mode 100644
index 0000000..4b793cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1765.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1765.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p02n01i01765ent IS
+END c09s05b02x00p02n01i01765ent;
+
+ARCHITECTURE c09s05b02x00p02n01i01765arch OF c09s05b02x00p02n01i01765ent IS
+  signal TS   : integer;
+  signal B   : bit;
+BEGIN
+
+  with B select
+    TS <= transport 1 when '0',
+    transport 2 when '1'; -- Failure_here
+  -- option not allowed
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b02x00p02n01i01765 - Option is not allowed here." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b02x00p02n01i01765arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1767.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1767.vhd
new file mode 100644
index 0000000..5ffe244
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1767.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1767.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p03n01i01767ent IS
+END c09s05b02x00p03n01i01767ent;
+
+ARCHITECTURE c09s05b02x00p03n01i01767arch OF c09s05b02x00p03n01i01767ent IS
+
+  signal TS   : integer;
+  signal B   : bit;
+
+BEGIN
+
+  with B select
+    TS <= transport 1 when '0'
+    2 when '1'; -- Failure_here
+  -- comma is missing
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b02x00p03n01i01767 - Comma is missing between conditional waveforms."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b02x00p03n01i01767arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1768.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1768.vhd
new file mode 100644
index 0000000..5a4b282
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1768.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1768.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01768ent IS
+END c09s05b02x00p11n01i01768ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01768arch OF c09s05b02x00p11n01i01768ent IS
+  signal   i,j   : real := 1.0;
+BEGIN
+
+  with i select     -- Failure_here
+            j <= transport 1.0    when 1.0,
+                 0.2    when 0.2,
+                 1.0e24 when 0.0,
+                 0.0    when others;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b02x00p11n01i01768 - Select expression in a selected assignment statement should be a discrete type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01768arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1769.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1769.vhd
new file mode 100644
index 0000000..fd75275
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1769.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1769.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01769ent IS
+END c09s05b02x00p11n01i01769ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01769arch OF c09s05b02x00p11n01i01769ent IS
+  type x is (Jan,Feb,Mar);
+  signal y : x;
+  signal Month_Num : integer;
+BEGIN
+
+  with y select
+    Month_num <= transport 1 when Jan,
+    2 when Feb,
+    3 when Mar,
+    4 when Jan; -- Failure_here
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b02x00p11n01i01769 - Select expression in a selected assignment statement can not appear more than one choice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01769arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc177.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc177.vhd
new file mode 100644
index 0000000..15a4163
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc177.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc177.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b03x01p03n02i00177ent IS
+END c04s03b03x01p03n02i00177ent;
+
+ARCHITECTURE c04s03b03x01p03n02i00177arch OF c04s03b03x01p03n02i00177ent IS
+  type    array1    is    array (positive range <>, natural range <>) of integer;
+  signal    c1    :    array1(1 to 8, 0 to 7);
+  alias    one_bit :    array1 is c1; -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert FALSE
+      report "***FAILED TEST: c04s03b03x01p03n02i00177 - Multi-dimensional arrays not allowed in alias declarations."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b03x01p03n02i00177arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1770.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1770.vhd
new file mode 100644
index 0000000..c5ae0ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1770.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1770.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01770ent IS
+END c09s05b02x00p11n01i01770ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01770arch OF c09s05b02x00p11n01i01770ent IS
+  type string4 is array( 1 to 4 ) of CHARACTER;
+  signal x : string4;
+  signal y : integer;
+BEGIN
+
+  with x select
+    y <= transport  1 when "one",   -- Failure_here
+    2 when "two",   -- Failure_here
+    0 when others;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b02x00p11n01i01770 - Select expression in a selected assignment statement is not the same type of a choice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01770arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1771.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1771.vhd
new file mode 100644
index 0000000..d96f805
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1771.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1771.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01771ent IS
+END c09s05b02x00p11n01i01771ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01771arch OF c09s05b02x00p11n01i01771ent IS
+  type x is (Jan,Feb,Mar);
+  signal y : x;
+  signal Month_Num : integer;
+BEGIN
+
+  with y select
+    Month_num <= transport 1 when Jan,
+    2 when Feb,
+    3 when others,      -- Failure_here
+                            -- choice 'others' is not last.
+    4 when Mar;
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b02x00p11n01i01771 - Choice of others should be the last alternative." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01771arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1772.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1772.vhd
new file mode 100644
index 0000000..cfec24b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1772.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1772.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01772ent IS
+END c09s05b02x00p11n01i01772ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01772arch OF c09s05b02x00p11n01i01772ent IS
+  signal   i, j : integer := 1;
+BEGIN
+
+  j <= transport 1 when 1,
+       2 when 2;
+  -- Failure_here
+  -- Not every value of select expressions is represented.
+  -- 'others' choice is needed.
+
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b02x00p11n01i01772 - Each value of the type of the select expression is represented once and only once in teh set of choices."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01772arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1773.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1773.vhd
new file mode 100644
index 0000000..e9f1557
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1773.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1773.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01773ent IS
+END c09s05b02x00p11n01i01773ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01773arch OF c09s05b02x00p11n01i01773ent IS
+
+  type day is (sun, mon, tue, wed, thu, fri, sat);
+  type rec_type is
+    record
+      element: day;
+    end record;
+
+  signal s_day: day;
+  signal j: integer;
+
+BEGIN
+
+  with s_day select
+    j <= transport 1 when sun,
+    2 when mon,
+    0 when element,  -- Failure_here
+    -- ERROR: An element simple name is not allowed as a choice
+    3 when others;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b02x00p11n01i01773 - An element simple name is not allowed as a choice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01773arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1774.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1774.vhd
new file mode 100644
index 0000000..48ee924
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1774.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1774.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s05b02x00p11n01i01774ent IS
+END c09s05b02x00p11n01i01774ent;
+
+ARCHITECTURE c09s05b02x00p11n01i01774arch OF c09s05b02x00p11n01i01774ent IS
+  type x is (Jan,Feb,Mar);
+  signal y : x;
+  signal Month_Num : integer;
+BEGIN
+
+  with y select
+    Month_num <= transport 1 when Jan,
+    3 when Mar;
+  -- Failure_here
+  -- The choice Feb is ommited.
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s05b02x00p11n01i01774 - Each value of the type of the select expression should be represented once and exactly once." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s05b02x00p11n01i01774arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1777.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1777.vhd
new file mode 100644
index 0000000..fff454a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1777.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1777.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s06b00x00p02n01i01777ent IS
+END c09s06b00x00p02n01i01777ent;
+
+ARCHITECTURE c09s06b00x00p02n01i01777arch OF c09s06b00x00p02n01i01777ent IS
+  component error
+    port    ( signal   should_be_second : boolean := true );
+    generic ( constant should_be_first  : integer := 1 );
+  end component; -- error
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s06b00x00p02n01i01777 - The generic map aspect must proceed the port map aspect if both are present."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s06b00x00p02n01i01777arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1778.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1778.vhd
new file mode 100644
index 0000000..35c3676
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1778.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1778.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s06b00x00p02n01i01778ent IS
+END c09s06b00x00p02n01i01778ent;
+
+ARCHITECTURE c09s06b00x00p02n01i01778arch OF c09s06b00x00p02n01i01778ent IS
+  component C
+    generic ( c2 : in integer := 122903 );
+  end component;
+BEGIN
+  C generic map (p);  -- Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s06b00x00p02n01i01778 - A colon(:) is expected after the instantiation label." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s06b00x00p02n01i01778arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc178.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc178.vhd
new file mode 100644
index 0000000..fcdea02
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc178.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc178.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p01n05i00178ent IS
+END c04s04b00x00p01n05i00178ent;
+
+ARCHITECTURE c04s04b00x00p01n05i00178arch OF c04s04b00x00p01n05i00178ent IS
+  signal S1 : INTEGER;
+  signal S2 : BOOLEAN;   
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1'DELAYED <= S2;  -- Failure_here
+    -- ERROR - predefined signal attribute must not be driven
+    S1'STABLE <= S2;  -- Failure_here
+    -- ERROR - predefined signal attribute must not be driven
+    S1'QUIET <= S2; -- Failure_here
+    -- ERROR - predefined signal attribute must not be driven
+    assert FALSE 
+      report "***FAILED TEST: c04s04b00x00p01n05i00178 - Predefined atttribute DELAYED can not be driven."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p01n05i00178arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1780.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1780.vhd
new file mode 100644
index 0000000..32b9d95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1780.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1780.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s06b00x00p04n01i01780ent IS
+END c09s06b00x00p04n01i01780ent;
+
+ARCHITECTURE c09s06b00x00p04n01i01780arch OF c09s06b00x00p04n01i01780ent IS
+  signal a, b, p, q: bit;
+
+  component comp1
+    port (p1, p2:bit);
+  end component;
+
+  for L1 : comp1 use entity work.ch0906_p00401_01_ent;
+BEGIN
+  L1:comp2                    -- Failure_here: comp2 not declared
+    port map (q, p);
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s06b00x00p04n01i01780 - The component name in the component instantiation statement must be the name of a component declared in a component declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s06b00x00p04n01i01780arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1783.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1783.vhd
new file mode 100644
index 0000000..b8e4e90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1783.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1783.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s06b00x00p04n06i01783ent IS
+  port (X: in BIT; Y: in BIT_VECTOR; Z: out BIT);
+END c09s06b00x00p04n06i01783ent;
+
+ARCHITECTURE c09s06b00x00p04n06i01783arch OF c09s06b00x00p04n06i01783ent IS
+  component input2
+    generic (g1: integer );
+    port (signal input_1 : in  bit;
+          signal input_2 : in  bit_vector;
+          signal output  : out bit);
+  end component;
+BEGIN
+  G1: input2
+    port map (X,Y,Z);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s06b00x00p04n06i01783 - Each local generic must be associated at least once."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s06b00x00p04n06i01783arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1784.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1784.vhd
new file mode 100644
index 0000000..6f1e580
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1784.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1784.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s06b00x00p04n06i01784ent IS
+  generic (X: in BIT_VECTOR(0 to 2); Z: in BIT);
+END c09s06b00x00p04n06i01784ent;
+
+ARCHITECTURE c09s06b00x00p04n06i01784arch OF c09s06b00x00p04n06i01784ent IS
+  component input2
+    generic (input_1 : in  bit;
+             input_2 : in  bit;
+             output  : in  bit);
+  end component;
+
+  constant A1 : bit := '1';
+BEGIN
+  G1: input2
+    generic map (input_1 => X(0), input_1 => X(1), output => A1);
+  --    Failure_here
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s06b00x00p04n06i01784 - Each local generic must be associated exactly once."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s06b00x00p04n06i01784arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1786.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1786.vhd
new file mode 100644
index 0000000..76ec44b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1786.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1786.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c09s06b00x00p04n08i01786ent_a is
+  port ( signal clk : in bit;
+         signal i_bus : in bit_vector(0 to 7);
+         signal o_bus : out bit_vector(0 to 7)
+         );
+end c09s06b00x00p04n08i01786ent_a;
+
+ENTITY c09s06b00x00p04n08i01786ent IS
+  port ( signal clock : in bit;
+         signal in_bus : in bit_vector(0 to 7);
+         signal out_bus : out bit_vector(0 to 7)
+         );
+END c09s06b00x00p04n08i01786ent;
+
+ARCHITECTURE c09s06b00x00p04n08i01786arch OF c09s06b00x00p04n08i01786ent IS
+  component c09s06b00x00p04n08i01786ent_a
+    port ( signal clk : in bit;
+           signal i_bus : in bit_vector(0 to 7);
+           signal o_bus : out bit_vector(0 to 7)
+           );
+  end component; -- Test
+
+BEGIN
+  err : c09s06b00x00p04n08i01786ent_a
+    port map ( i_bus => in_bus,
+               i_bus => in_bus,
+               o_bus => out_bus
+               );
+
+  assert FALSE 
+    report "***FAILED TEST: c09s06b00x00p04n08i01786 - Each local port must be associated exactly once."
+    severity ERROR;
+
+END c09s06b00x00p04n08i01786arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1788.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1788.vhd
new file mode 100644
index 0000000..c1aa209
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1788.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1788.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s07b00x00p02n01i01788ent IS
+END c09s07b00x00p02n01i01788ent;
+
+ARCHITECTURE c09s07b00x00p02n01i01788arch OF c09s07b00x00p02n01i01788ent IS
+  signal   TS,SS   :    bit_vector(1 to 3);
+BEGIN
+  for I in 1 to 3 generate     -- Failure_here
+    -- generate label is missing    TS(I) <= SS(I);
+  end generate;
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s07b00x00p02n01i01788 - In the generate statement, the reserved word generate must be preceded by a generate label."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s07b00x00p02n01i01788arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1789.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1789.vhd
new file mode 100644
index 0000000..3fb7f86
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1789.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1789.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s07b00x00p02n01i01789ent IS
+END c09s07b00x00p02n01i01789ent;
+
+ARCHITECTURE c09s07b00x00p02n01i01789arch OF c09s07b00x00p02n01i01789ent IS
+
+BEGIN
+  BL: block
+  begin
+
+    L1: for i in 1 to 3 generate        
+      if i = 5 then
+        null;
+      end if;   
+    end generate L1;
+
+  end block;
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s07b00x00p02n01i01789 - In the generate statement, the reserved word generate must be followed by zero or more concurrent statements." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s07b00x00p02n01i01789arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1790.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1790.vhd
new file mode 100644
index 0000000..c7703a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1790.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1790.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s07b00x00p02n01i01790ent IS
+END c09s07b00x00p02n01i01790ent;
+
+ARCHITECTURE c09s07b00x00p02n01i01790arch OF c09s07b00x00p02n01i01790ent IS
+  signal TS,SS: bit_vector(1 to 3);
+BEGIN
+  GEN: for I in 1 to 3 generate
+    TS(I) <= SS(I);
+  end generate
+    -- Failure_here
+    -- Semicolon missing before 'end'
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c09s07b00x00p02n01i01790 - In the generate statement, the reserved word end generate must be followed by a semicolon." 
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+    END c09s07b00x00p02n01i01790arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1791.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1791.vhd
new file mode 100644
index 0000000..e2a8efc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1791.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1791.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s07b00x00p05n01i01791ent IS
+END c09s07b00x00p05n01i01791ent;
+
+ARCHITECTURE c09s07b00x00p05n01i01791arch OF c09s07b00x00p05n01i01791ent IS
+
+BEGIN
+  L1: for I in 1 to 3 generate
+  end generate L1;
+
+  L2: if true generate
+  end generate L1;            -- failure_here
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s07b00x00p05n01i01791 - Label appears at the end of a generate statement must repeat the generate label."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c09s07b00x00p05n01i01791arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1794.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1794.vhd
new file mode 100644
index 0000000..a0cffa9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1794.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1794.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s07b00x00p06n02i01794ent IS
+END c09s07b00x00p06n02i01794ent;
+
+ARCHITECTURE c09s07b00x00p06n02i01794arch OF c09s07b00x00p06n02i01794ent IS
+
+  procedure i_proof_1 (x : real) is
+  begin
+  end i_proof_1;
+
+BEGIN
+
+  glabel1 : FOR i in 0.0 to 8.0 generate
+    i_proof_1(i);
+  end generate glabel1;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s07b00x00p06n02i01794 - The generate parameter type should be the base type of the discrete range of the generate parameter specification."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s07b00x00p06n02i01794arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1795.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1795.vhd
new file mode 100644
index 0000000..c351589
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1795.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1795.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s07b00x00p06n02i01795ent IS
+END c09s07b00x00p06n02i01795ent;
+
+ARCHITECTURE c09s07b00x00p06n02i01795arch OF c09s07b00x00p06n02i01795ent IS
+
+  procedure i_proof_1 (x : time) is
+  begin
+  end i_proof_1;
+
+BEGIN
+
+  glabel1 : FOR i in 0 ns to 8 ns generate
+    i_proof_1(i);
+  end generate glabel1;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c09s07b00x00p06n02i01795 - The generate parameter type should be the base type of the discrete range of the generate parameter specification.(Time did not have a discrete range.)"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c09s07b00x00p06n02i01795arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1796.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1796.vhd
new file mode 100644
index 0000000..581c098
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1796.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1796.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p02n01i01796ent IS
+END c07s01b00x00p02n01i01796ent;
+
+ARCHITECTURE c07s01b00x00p02n01i01796arch OF c07s01b00x00p02n01i01796ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 3;
+    variable y : integer := 5;
+    variable z : integer := 9;
+  BEGIN
+    if ((x <= y) nor (x <= z) nor (y <= z)) Then   -- Failure_here
+      -- sequence of nor operators
+      -- not allowed in an expression
+      x:= y+z;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c07s01b00x00p02n01i01796 - Expression with a sequence of nand or nor operators is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p02n01i01796arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1797.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1797.vhd
new file mode 100644
index 0000000..0aa60aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1797.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1797.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p02n01i01797ent IS
+END c07s01b00x00p02n01i01797ent;
+
+ARCHITECTURE c07s01b00x00p02n01i01797arch OF c07s01b00x00p02n01i01797ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c07s01b00x00p02n01i01797"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c07s01b00x00p02n01i01797"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c07s01b00x00p02n01i01797arch;
+
+-- CONFIGURATION c07s01b00x00p02n01i01797cfg OF c07s01b00x00p02n01i01797ent IS
+--     FOR c07s01b00x00p02n01i01797arch
+--     END FOR;
+-- END c07s01b00x00p02n01i01797cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1799.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1799.vhd
new file mode 100644
index 0000000..e75c6fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1799.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1799.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p02n01i01799ent IS
+END c07s01b00x00p02n01i01799ent;
+
+ARCHITECTURE c07s01b00x00p02n01i01799arch OF c07s01b00x00p02n01i01799ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 3;
+    variable y : integer := 5;
+    variable z : integer := 9;
+  BEGIN
+    if ((x <= y) xnor (x <= z) xnor (y <= z)) Then   -- Failure_here
+      -- sequence of nor operators
+      -- not allowed in an expression
+      x:= y+z;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c07s01b00x00p02n01i01799 - Expression with a sequence of nand or nor operators is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p02n01i01799arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1800.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1800.vhd
new file mode 100644
index 0000000..0fe1d7d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1800.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1800.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p03n01i01800ent IS
+END c07s01b00x00p03n01i01800ent;
+
+ARCHITECTURE c07s01b00x00p03n01i01800arch OF c07s01b00x00p03n01i01800ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : real := 4;
+    variable y : real := 6.7;
+    variable z : real := 4.8;
+    variable p : real;
+  BEGIN
+    if  y = x = z then   -- Failure_here
+      -- only a single relational operator allowed.
+      p := y + z + x;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c07s01b00x00p03n01i01800 - Only a single relational operator is used to combine expressions and form realtions."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p03n01i01800arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1802.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1802.vhd
new file mode 100644
index 0000000..3877281
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1802.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1802.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p05n01i01802ent IS
+END c07s01b00x00p05n01i01802ent;
+
+ARCHITECTURE c07s01b00x00p05n01i01802arch OF c07s01b00x00p05n01i01802ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 3;
+    variable y : integer := 5;
+    variable z : integer := 9;
+  BEGIN
+    if ((x + -z) < (y + x)) then  -- Failure_here
+      -- sign can appear only before the first term.
+      x := y * z;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c07s01b00x00p05n01i01802 - Sign can appear only before the first term in a simple expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p05n01i01802arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1805.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1805.vhd
new file mode 100644
index 0000000..d0747e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1805.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1805.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i01805ent IS
+END c07s01b00x00p07n01i01805ent;
+
+ARCHITECTURE c07s01b00x00p07n01i01805arch OF c07s01b00x00p07n01i01805ent IS
+  signal POS : Boolean;
+  signal P1  : Boolean := False;
+  signal P2  : Boolean := True;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    POS <= P1 and (not ) after 20 ns;   -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s01b00x00p07n01i01805 - Missing Primary."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i01805arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1806.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1806.vhd
new file mode 100644
index 0000000..1b1dc0e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1806.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1806.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p07n01i01806ent IS
+END c07s01b00x00p07n01i01806ent;
+
+ARCHITECTURE c07s01b00x00p07n01i01806arch OF c07s01b00x00p07n01i01806ent IS
+  signal POS : integer;
+  signal P1  : integer := 2;
+  signal P2  : integer := - 1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    POS <= P1 and (abs ) after 20 ns;   -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s01b00x00p07n01i01806 - Missing Primary."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p07n01i01806arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc181.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc181.vhd
new file mode 100644
index 0000000..e62fc13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc181.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc181.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p03n01i00181ent IS
+END c04s04b00x00p03n01i00181ent;
+
+ARCHITECTURE c04s04b00x00p03n01i00181arch OF c04s04b00x00p03n01i00181ent IS
+  attribute p  POSITIVE;         --Failure Here
+  signal s: integer;
+  attribute p of s: signal is 10;  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s04b00x00p03n01i00181 - Missing colon." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p03n01i00181arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1811.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1811.vhd
new file mode 100644
index 0000000..caadcd7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1811.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1811.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01811ent IS
+END c07s01b00x00p08n01i01811ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01811arch OF c07s01b00x00p08n01i01811ent IS
+  type    small_int    is range 0 to 7;
+  signal   s_int       : small_int := small_int;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01811 - Type name are not permitted as primaries in an initialization expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01811arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1812.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1812.vhd
new file mode 100644
index 0000000..94b1d18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1812.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1812.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01812ent IS
+END c07s01b00x00p08n01i01812ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01812arch OF c07s01b00x00p08n01i01812ent IS
+  type    small_int    is range 0 to 7;
+  signal   s_int       : small_int := 0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if (small_int > s_int) then
+      null;
+    end if;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01812 - Type name are not permitted as primaries."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01812arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1814.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1814.vhd
new file mode 100644
index 0000000..8c270c3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1814.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1814.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01814ent IS
+END c07s01b00x00p08n01i01814ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01814arch OF c07s01b00x00p08n01i01814ent IS
+  type    small_int    is range 0 to 7;
+  type   byte      is range small_int to 3;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01814 - Type name are not permitted as primaries in a range expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01814arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1815.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1815.vhd
new file mode 100644
index 0000000..1e7090a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1815.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1815.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01815ent IS
+END c07s01b00x00p08n01i01815ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01815arch OF c07s01b00x00p08n01i01815ent IS
+  type    small_int    is range 0 to 7;
+  signal   sm_int      : small_int := 0;
+BEGIN
+  B : block (sm_int = small_int)       -- type name illegal
+  begin
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01815 - Type name are not permitted as primaries in a block guard expression."
+      severity ERROR;
+  end block B;
+
+END c07s01b00x00p08n01i01815arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1816.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1816.vhd
new file mode 100644
index 0000000..1e0665a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1816.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1816.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01816ent IS
+  type    small_int    is range 0 to 7;
+  type   cmd_bus      is array (small_int) of bit;
+END c07s01b00x00p08n01i01816ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01816arch OF c07s01b00x00p08n01i01816ent IS
+  signal s_int : small_int := 0;
+  signal s_bus : cmd_bus;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= s_bus'right(small_int);
+    wait;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01816 - Type names are not permitted as primaries in an attribute argument."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01816arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1817.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1817.vhd
new file mode 100644
index 0000000..8c5ac9e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1817.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1817.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01817ent IS
+  type    small_int    is range 0 to 7;
+END c07s01b00x00p08n01i01817ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01817arch OF c07s01b00x00p08n01i01817ent IS
+  signal s_int : small_int;
+BEGIN
+  with small_int select                 -- type name illegal here
+           s_int <= 6 after 10 ns when true;
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01817 - Type names are not permitted as primaries in an attribute argument."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01817arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1818.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1818.vhd
new file mode 100644
index 0000000..b640857
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1818.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1818.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01818ent IS
+  type    small_int    is range 0 to 7;
+  type   byte      is range 0 to 3;
+END c07s01b00x00p08n01i01818ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01818arch OF c07s01b00x00p08n01i01818ent IS
+  function test return small_int is
+  begin
+    return small_int;                 -- type name illegal here
+  end test;
+
+  signal s_int : small_int := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= test after 5 ns;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01818 - Type names are not permitted as primaries in a function return statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01818arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1819.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1819.vhd
new file mode 100644
index 0000000..aca96c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1819.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1819.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01819ent IS
+  type    small_int    is range 0 to 7;
+  type   byte      is range 0 to 3;
+END c07s01b00x00p08n01i01819ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01819arch OF c07s01b00x00p08n01i01819ent IS
+  function test return small_int is
+    variable tmp : small_int := 0;
+  begin
+    tmp := small_int;                 -- type name illegal here
+    return tmp;
+  end test;
+
+  signal s_int : small_int := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= test after 5 ns;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01819 - Type names are not permitted as primaries in a variable assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01819arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1820.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1820.vhd
new file mode 100644
index 0000000..0ea4886
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1820.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1820.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01820ent IS
+  type    small_int    is range 0 to 7;
+  type   byte      is range 0 to 3;
+END c07s01b00x00p08n01i01820ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01820arch OF c07s01b00x00p08n01i01820ent IS
+  function test return small_int is
+    variable tmp : small_int := 0;
+  begin
+    case small_int is                 -- type name illegal here
+      when 0    => tmp := 0;
+      when others => tmp := 1;
+    end case;
+    return tmp;
+  end test;
+
+  signal s_int : small_int := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= test after 5 ns;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01820 - Type names are not permitted as primaries in a case expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01820arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1821.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1821.vhd
new file mode 100644
index 0000000..e53af5c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1821.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1821.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01821ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int) of small_int;
+END c07s01b00x00p08n01i01821ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01821arch OF c07s01b00x00p08n01i01821ent IS
+  signal s_bus : cmd_bus;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_bus <= (0 => small_int, others =>0) after 5 ns; -- type name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01821 - Type names are not permitted as primaries in an element association expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01821arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1822.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1822.vhd
new file mode 100644
index 0000000..2b99a92
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1822.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1822.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01822ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int) of small_int;
+END c07s01b00x00p08n01i01822ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01822arch OF c07s01b00x00p08n01i01822ent IS
+  signal s_bus : cmd_bus;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_bus(0) <= small_int'(small_int) after 5 ns; -- type name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01822 - Type names are not permitted as primaries in a qualified expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01822arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1823.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1823.vhd
new file mode 100644
index 0000000..417a392
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1823.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1823.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01823ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int) of small_int;
+END c07s01b00x00p08n01i01823ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01823arch OF c07s01b00x00p08n01i01823ent IS
+  signal s_bus : cmd_bus;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_bus(0) <= small_int(small_int) after 5 ns; -- type name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01823 - Type names are not permitted as primaries in a type conversion expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01823arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1824.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1824.vhd
new file mode 100644
index 0000000..900ac55
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1824.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1824.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s01b00x00p08n01i01824pkg is
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  constant    bus_width    : small_int := 7;
+end c07s01b00x00p08n01i01824pkg;
+
+use work.c07s01b00x00p08n01i01824pkg.all;
+entity c07s01b00x00p08n01i01824ent_a is
+  port ( signal in_bus    : in  cmd_bus (0 to bus_width);
+         signal out_bus    : out cmd_bus (0 to bus_width));
+end c07s01b00x00p08n01i01824ent_a;
+
+architecture c07s01b00x00p08n01i01824arch_a of c07s01b00x00p08n01i01824ent_a is
+begin
+end c07s01b00x00p08n01i01824arch_a;
+
+use work.c07s01b00x00p08n01i01824pkg.all;
+ENTITY c07s01b00x00p08n01i01824ent IS
+END c07s01b00x00p08n01i01824ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01824arch OF c07s01b00x00p08n01i01824ent IS
+  signal ibus, obus : cmd_bus(small_int);
+  
+  component test
+    port ( signal in_bus    : in  cmd_bus (0 to small_int(bus_width - 1));
+           signal out_bus    : out cmd_bus (0 to small_int(bus_width - 1)));
+  end component;
+  for err : test use entity work.c07s01b00x00p08n01i01824ent_a(c07s01b00x00p08n01i01824arch_a);
+BEGIN
+  err : test port map ( ibus, small_int );       -- type name illegal here    
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01824 - Type names are not permitted as primaries in a component instantiation port map statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01824arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1825.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1825.vhd
new file mode 100644
index 0000000..ccf29a9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1825.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1825.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01825ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01825ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01825arch OF c07s01b00x00p08n01i01825ent IS
+  signal s_int : small_int := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert s_int > ch0701_p00801_16_ent              -- entity name illegal here
+      report "Entity name accepted as primary in an expression."
+      severity note ;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01825 - Entity name are not permitted as primaries in an assert condition."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01825arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1826.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1826.vhd
new file mode 100644
index 0000000..818498b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1826.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1826.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01826ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01826ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01826arch OF c07s01b00x00p08n01i01826ent IS
+  signal s_int : small_int := c07s01b00x00p08n01i01826ent;    --entity name illegal here
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01826 - Entity name are not permitted as primaries in an initialization expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01826arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1827.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1827.vhd
new file mode 100644
index 0000000..7697dd1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1827.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1827.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01827ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01827ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01827arch OF c07s01b00x00p08n01i01827ent IS
+  type byte is range ch0701_p00801_18_ent to 3;            -- entity name illegal here
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01827 - Entity name are not permitted as primaries in a range expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01827arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1828.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1828.vhd
new file mode 100644
index 0000000..f126120
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1828.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1828.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01828ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01828ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01828arch OF c07s01b00x00p08n01i01828ent IS
+  signal sm_int : small_int := 0;
+BEGIN
+  B: block ( sm_int = c07s01b00x00p08n01i01828ent )       -- entity name illegal here
+  begin
+    assert false
+      report "Entity name accepted in block guard expression."
+      severity note ;
+  end block B;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01828 - Entity name are not permitted as primaries in a block guard expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01828arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1829.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1829.vhd
new file mode 100644
index 0000000..75e81a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1829.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1829.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01829ent IS
+  type small_int is range 0 to 7;
+  type cmd_bus is array (small_int) of bit;
+END c07s01b00x00p08n01i01829ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01829arch OF c07s01b00x00p08n01i01829ent IS
+  signal s_bus : cmd_bus;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_bus (c07s01b00x00p08n01i01829ent) <= '0' after 5 ns;          -- entity name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01829 - Entity name are not permitted as primaries in an index expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01829arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1830.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1830.vhd
new file mode 100644
index 0000000..e61eed6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1830.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1830.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01830ent IS
+  type small_int    is range 0 to 7;
+  type cmd_bus    is array (small_int) of bit;
+END c07s01b00x00p08n01i01830ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01830arch OF c07s01b00x00p08n01i01830ent IS
+  signal s_int : small_int := 0;
+  signal s_bus : cmd_bus;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= s_bus'right(c07s01b00x00p08n01i01830ent);         -- entity name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01830 - Entity name are not permitted as primaries in an attribute argument."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01830arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1831.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1831.vhd
new file mode 100644
index 0000000..bf74226
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1831.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1831.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01831ent IS
+  type small_int    is range 0 to 7;
+END c07s01b00x00p08n01i01831ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01831arch OF c07s01b00x00p08n01i01831ent IS
+  signal s_int : small_int;
+BEGIN
+  with c07s01b00x00p08n01i01831ent select                 -- entity name illegal here
+              s_int <= s_int + 1 after 10 ns when true;
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01831 - Entity name are not permitted as primaries in a select signal assignment expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01831arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1832.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1832.vhd
new file mode 100644
index 0000000..81c57d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1832.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1832.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01832ent IS
+  type small_int    is range 0 to 7;
+  type byte    is range 0 to 3;
+END c07s01b00x00p08n01i01832ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01832arch OF c07s01b00x00p08n01i01832ent IS
+  function test return small_int is
+  begin
+    return c07s01b00x00p08n01i01832nt;   -- entity name illegal here
+  end test;
+
+  signal s_int : small_int := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= test after 5 ns;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01832 - Entity name are not permitted as primaries in a function return statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01832arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1833.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1833.vhd
new file mode 100644
index 0000000..5aef8a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1833.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1833.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01833ent IS
+  type small_int    is range 0 to 7;
+  type byte    is range 0 to 3;
+END c07s01b00x00p08n01i01833ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01833arch OF c07s01b00x00p08n01i01833ent IS
+  function test return small_int is
+    variable tmp : small_int := 0;
+  begin
+    tmp := c07s01b00x00p08n01i01833ent;                 -- entity name illegal here
+    return tmp;
+  end test;
+
+  signal s_int : small_int := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= test after 5 ns;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01833 - Entity name are not permitted as primaries in a variable assignment statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01833arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1834.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1834.vhd
new file mode 100644
index 0000000..1e5631e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1834.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1834.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01834ent IS
+  type small_int    is range 0 to 7;
+END c07s01b00x00p08n01i01834ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01834arch OF c07s01b00x00p08n01i01834ent IS
+
+BEGIN
+  TESTING : PROCESS
+    variable tmp : small_int := 0;
+  BEGIN
+    case c07s01b00x00p08n01i01834ent is                 -- entity name illegal here
+      when 0    => tmp := 0;
+      when others => tmp := 1;
+    end case;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01834 - Entity name are not permitted as primaries in a case expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01834arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1835.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1835.vhd
new file mode 100644
index 0000000..14b32d2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1835.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1835.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01835ent IS
+  type small_int    is range 0 to 7;
+  type cmd_bus    is array (small_int) of small_int;
+END c07s01b00x00p08n01i01835ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01835arch OF c07s01b00x00p08n01i01835ent IS
+  signal s_bus : cmd_bus;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_bus <= (0 => c07s01b00x00p08n01i01835ent, others => 0) after 5 ns;--entity name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01835 - Entity name are not permitted as primaries in an element association expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01835arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1836.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1836.vhd
new file mode 100644
index 0000000..1367378
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1836.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1836.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01836ent IS
+  type small_int    is range 0 to 7;
+  type cmd_bus    is array (small_int) of small_int;
+END c07s01b00x00p08n01i01836ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01836arch OF c07s01b00x00p08n01i01836ent IS
+  signal s_bus : cmd_bus;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_bus(0) <= small_int'(c07s01b00x00p08n01i01836ent) after 5 ns; -- entity name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01836 - Entity name are not permitted as primaries in a qualfied expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01836arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1837.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1837.vhd
new file mode 100644
index 0000000..9b3d445
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1837.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1837.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01837ent IS
+  type small_int    is range 0 to 7;
+  type cmd_bus    is array (small_int) of small_int;
+END c07s01b00x00p08n01i01837ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01837arch OF c07s01b00x00p08n01i01837ent IS
+  signal s_bus : cmd_bus;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_bus(0) <= small_int(c07s01b00x00p08n01i01837ent) after 5 ns; -- entity name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01837 - Entity name are not permitted as primaries in a type conversion expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01837arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1838.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1838.vhd
new file mode 100644
index 0000000..50ba5ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1838.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1838.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s01b00x00p08n01i01838pkg is
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  constant    bus_width    : small_int := 7;
+end c07s01b00x00p08n01i01838pkg;
+
+use work.c07s01b00x00p08n01i01838pkg.all;
+entity c07s01b00x00p08n01i01838ent_a is
+  generic ( constant bus_width : small_int);
+  port ( signal in_bus    : in  cmd_bus (0 to bus_width);
+         signal out_bus    : out cmd_bus (0 to bus_width));
+end c07s01b00x00p08n01i01838ent_a;
+
+architecture c07s01b00x00p08n01i01838arch_a of c07s01b00x00p08n01i01838ent_a is
+begin
+end c07s01b00x00p08n01i01838arch_a;
+
+use work.c07s01b00x00p08n01i01838pkg.all;
+ENTITY c07s01b00x00p08n01i01838ent IS
+END c07s01b00x00p08n01i01838ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01838arch OF c07s01b00x00p08n01i01838ent IS
+  signal ibus, obus : cmd_bus(small_int);
+
+  component test
+    generic ( constant bus_width : natural := 7);
+    port ( signal in_bus    : in  cmd_bus (0 to small_int(bus_width - 1));
+           signal out_bus    : out cmd_bus (0 to small_int(bus_width - 1)));
+  end component;
+  for err : test use entity work.c07s01b00x00p08n01i01838ent_a(c07s01b00x00p08n01i01838arch_a);
+
+BEGIN
+  err : test generic map ( c07s01b00x00p08n01i01838ent ) -- entity name illegal here
+    port map ( ibus, obus );
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01838 - Entity names are not permitted as primaries in a component instantiation generic map statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01838arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1839.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1839.vhd
new file mode 100644
index 0000000..211046c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1839.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1839.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s01b00x00p08n01i01839pkg is
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  constant    bus_width    : small_int := 7;
+end c07s01b00x00p08n01i01839pkg;
+
+use work.c07s01b00x00p08n01i01839pkg.all;
+entity c07s01b00x00p08n01i01839ent_a is
+  port ( signal in_bus    : in  cmd_bus (0 to bus_width);
+         signal out_bus    : out cmd_bus (0 to bus_width));
+end c07s01b00x00p08n01i01839ent_a;
+
+architecture c07s01b00x00p08n01i01839arch_a of c07s01b00x00p08n01i01839ent_a is
+begin
+end c07s01b00x00p08n01i01839arch_a;
+
+use work.c07s01b00x00p08n01i01839pkg.all;
+ENTITY c07s01b00x00p08n01i01839ent IS
+END c07s01b00x00p08n01i01839ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01839arch OF c07s01b00x00p08n01i01839ent IS
+  signal ibus, obus : cmd_bus(small_int);
+
+  component test
+    port ( signal in_bus    : in  cmd_bus (0 to small_int(bus_width));
+           signal out_bus    : out cmd_bus (0 to small_int(bus_width)));
+  end component;
+  for err : test use entity work.c07s01b00x00p08n01i01839ent_a(c07s01b00x00p08n01i01839arch_a);
+
+BEGIN
+  err : test port map ( ibus, c07s01b00x00p08n01i01839ent ); --entity name illegal here
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01839 - Entity names are not permitted as primaries in a component instantiation port map statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc07s01b00x00p08n01i01839arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc184.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc184.vhd
new file mode 100644
index 0000000..82f62fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc184.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc184.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p05n01i00184ent IS
+END c04s04b00x00p05n01i00184ent;
+
+ARCHITECTURE c04s04b00x00p05n01i00184arch OF c04s04b00x00p05n01i00184ent IS
+  type COORDINATE is
+    record
+      X, Y: INTEGER;
+    end record;
+  type       acccor    is access COORDINATE;
+  attribute    ill1   : acccor;   --Failure here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c04s04b00x00p05n01i00184 - In an attribute declaration, the type mark must denote a subtype that is neither an access type nor a file type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p05n01i00184arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1840.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1840.vhd
new file mode 100644
index 0000000..6f708ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1840.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1840.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01840ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01840ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01840arch OF c07s01b00x00p08n01i01840ent IS
+  signal s_int : small_int := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    assert s_int > c07s01b00x00p08n01i01840arch    -- body name illegal here
+      report "architecture body name accepted as primary in a condition."
+      severity note ;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01840 - Architecture body names are not permitted as primaries in a condition expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01840arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1841.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1841.vhd
new file mode 100644
index 0000000..5aeb5ce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1841.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1841.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01841ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01841ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01841arch OF c07s01b00x00p08n01i01841ent IS
+  signal s_int : small_int := 0;
+BEGIN
+  blk: block ( s_int = 0 )
+  begin
+  end block blk;
+
+  TESTING : PROCESS
+  BEGIN
+    assert s_int > blk    -- block label illegal here
+      report "block label accepted as primary in a condition."
+      severity note ;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01841 - Block lables are not permitted as primaries in a condition expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01841arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1842.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1842.vhd
new file mode 100644
index 0000000..28de5d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1842.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1842.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01842ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01842ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01842arch OF c07s01b00x00p08n01i01842ent IS
+  signal s_int : small_int := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    assert s_int > TESTING    -- process label illegal here
+      report "process label accepted as primary in a condition."
+      severity note ;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01842 - Process lables are not permitted as primaries in a condition expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01842arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1843.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1843.vhd
new file mode 100644
index 0000000..f3aa973
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1843.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1843.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01843ent IS
+  type small_int is range 0 to 7;
+
+END c07s01b00x00p08n01i01843ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01843arch OF c07s01b00x00p08n01i01843ent IS
+  signal s_int : small_int := 0;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    lop : for i in small_int loop
+      null;
+    end loop lop;
+
+    assert s_int > lop    -- loop label illegal here
+      report "loop label accepted as primary in a condition."
+      severity note ;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01843 - Loop lables are not permitted as primaries in a condition expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01843arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1844.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1844.vhd
new file mode 100644
index 0000000..4c97b73
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1844.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1844.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01844ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01844ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01844arch OF c07s01b00x00p08n01i01844ent IS
+  signal s_int : small_int := 0;
+BEGIN
+  sig : s_int <= 5 after 5 ns;
+  TESTING : PROCESS
+  BEGIN
+    assert s_int > sig    -- signal assignment label illegal here
+      report "signal assignment label accepted as primary in a condition."
+      severity note ;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01844 - Signal assignment lables are not permitted as primaries in a condition expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01844arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1845.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1845.vhd
new file mode 100644
index 0000000..a678810
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1845.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1845.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01845ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01845ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01845arch OF c07s01b00x00p08n01i01845ent IS
+  signal s_int : small_int := ch0701_p00801_36_arch;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01845 - Architecture body names are not permitted as primaries in an initialization expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01845arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1846.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1846.vhd
new file mode 100644
index 0000000..5576d96
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1846.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1846.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01846ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01846ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01846arch OF c07s01b00x00p08n01i01846ent IS
+  signal s_int : small_int;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01846 - Process labels are not permitted as primaries in an initialization expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  b: block ( s_int = 0 )
+    signal s_int2 : small_int := TESTING;   -- process label illegal here
+  begin
+  end block b;
+
+END c07s01b00x00p08n01i01846arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1847.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1847.vhd
new file mode 100644
index 0000000..a930263
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1847.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1847.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01847ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01847ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01847arch OF c07s01b00x00p08n01i01847ent IS
+  signal s_int : small_int;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    lop : for i in small_int loop
+      null;
+    end loop lop;
+
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01847 - Loop labels are not permitted as primaries in an initialization expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  b: block ( s_int = 0 )
+    signal tmp : small_int := lop;
+  begin
+  end block b;
+
+END c07s01b00x00p08n01i01847arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1848.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1848.vhd
new file mode 100644
index 0000000..b4e678c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1848.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1848.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01848ent IS
+  type small_int is range 0 to 7;
+END c07s01b00x00p08n01i01848ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01848arch OF c07s01b00x00p08n01i01848ent IS
+  signal s_int : small_int;
+BEGIN
+
+  sig : s_int <= 5 after 5 ns;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01848 - Signal assignment labels are not permitted as primaries in an initialization expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  b : block (s_int = 0)
+    signal tmp : small_int := sig;
+  begin
+  end block b;
+
+END c07s01b00x00p08n01i01848arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1849.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1849.vhd
new file mode 100644
index 0000000..219d31e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1849.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1849.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01849ent IS
+END c07s01b00x00p08n01i01849ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01849arch OF c07s01b00x00p08n01i01849ent IS
+  type byte is range c07s01b00x00p08n01i01849arch to 3;
+BEGIN
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01849 - Architecture body names are not permitted as primaries in a range expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01849arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc185.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc185.vhd
new file mode 100644
index 0000000..cc04ac0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc185.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc185.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p05n01i00185ent IS
+END c04s04b00x00p05n01i00185ent;
+
+ARCHITECTURE c04s04b00x00p05n01i00185arch OF c04s04b00x00p05n01i00185ent IS
+  type       FT    is file of integer;
+  attribute    ill2   : FT;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c04s04b00x00p05n01i00185 - In an attribute declaration, the type mark must denote a subtype that is neither an access type nor a file type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p05n01i00185arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1850.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1850.vhd
new file mode 100644
index 0000000..f230718
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1850.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1850.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01850ent IS
+END c07s01b00x00p08n01i01850ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01850arch OF c07s01b00x00p08n01i01850ent IS
+  signal s_int : integer;
+BEGIN
+  b: block ( s_int = 0 )
+    type byte is range b to 3;        -- block label illegal here
+  begin
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01850 - Block labels are not permitted as primaries in a range expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01850arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1851.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1851.vhd
new file mode 100644
index 0000000..0a8e576
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1851.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1851.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01851ent IS
+END c07s01b00x00p08n01i01851ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01851arch OF c07s01b00x00p08n01i01851ent IS
+
+BEGIN
+  TESTING : PROCESS
+    type byte is range TESTING to 3; -- process label illegal here
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01851 - Process labels are not permitted as primaries in a range expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01851arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1852.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1852.vhd
new file mode 100644
index 0000000..bd5400e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1852.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1852.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01852ent IS
+END c07s01b00x00p08n01i01852ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01852arch OF c07s01b00x00p08n01i01852ent IS
+  signal sma_int : integer;
+BEGIN
+  sig : sma_int <= 6 after 5 ns;
+
+  TESTING : PROCESS
+    type byte is range sig to 33; -- process label illegal here
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01852 - Signal assignment labels are not permitted as primaries in a range expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01852arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1853.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1853.vhd
new file mode 100644
index 0000000..94577fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1853.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1853.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01853ent IS
+END c07s01b00x00p08n01i01853ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01853arch OF c07s01b00x00p08n01i01853ent IS
+  signal sma_int : integer;
+BEGIN
+  b: block ( sma_int = ch0701_p00801_44_arch )   -- body name illegal here
+  begin
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01853 - Architecture body names are not permitted as primaries in a block guard expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01853arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1854.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1854.vhd
new file mode 100644
index 0000000..de6e523
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1854.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1854.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01854ent IS
+END c07s01b00x00p08n01i01854ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01854arch OF c07s01b00x00p08n01i01854ent IS
+  signal sma_int : integer;
+BEGIN
+  b: block ( sma_int = b )       -- block label illegal here
+  begin
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01854 - Block labels are not permitted as primaries in a block guard expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01854arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1855.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1855.vhd
new file mode 100644
index 0000000..987f29a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1855.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1855.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01855ent IS
+END c07s01b00x00p08n01i01855ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01855arch OF c07s01b00x00p08n01i01855ent IS
+  signal sma_int : integer;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01855 - Process labels are not permitted as primaries in a block guard expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  b: block ( sma_int = TESTING )       -- process label illegal here
+  begin
+  end block b;
+
+END c07s01b00x00p08n01i01855arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1856.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1856.vhd
new file mode 100644
index 0000000..5abe6c7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1856.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1856.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01856ent IS
+END c07s01b00x00p08n01i01856ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01856arch OF c07s01b00x00p08n01i01856ent IS
+  signal sma_int : integer;
+BEGIN
+  sig : sma_int <= 5 after 5 ns;
+
+  b: block ( sma_int = sig )       -- signal assignment label illegal here
+  begin
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01856 - Signal assignment labels are not permitted as primaries in a block guard expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01856arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1857.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1857.vhd
new file mode 100644
index 0000000..95e59e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1857.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1857.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01857ent IS
+END c07s01b00x00p08n01i01857ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01857arch OF c07s01b00x00p08n01i01857ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    ibus, obus, obus2    : cmd_bus(small_int);
+  signal    s_int          : small_int := 0;
+  signal   bool         : boolean;
+BEGIN
+  s : bool <= s_int = ibus'right(1) after 5 ns;
+  with bool select
+    obus (ch0701_p00801_48_arch)<= 5 after 5 ns when true, -- body name illegal here
+    obus (5)          <= 5 after 5 ns when false; 
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01857 - Architecture body names are not permitted as primaries in an index expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01857arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1858.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1858.vhd
new file mode 100644
index 0000000..6f7cb58
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1858.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1858.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01858ent IS
+END c07s01b00x00p08n01i01858ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01858arch OF c07s01b00x00p08n01i01858ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    ibus, obus       : cmd_bus(small_int);
+  signal    s_int          : small_int := 0;
+  signal   bool         : boolean;
+BEGIN
+  blk : block (s_int = 0)
+  begin
+  end block blk;
+
+  s : bool <= s_int = ibus'right(1) after 5 ns;
+
+  with bool select
+    obus (blk)   <= 5 after 5 ns when true, -- block labels illegal here
+    obus (5)    <= 4 after 5 ns when false; 
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01858 - Blcok labels are not permitted as primaries in an index expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01858arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1859.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1859.vhd
new file mode 100644
index 0000000..f304f65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1859.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1859.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01859ent IS
+END c07s01b00x00p08n01i01859ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01859arch OF c07s01b00x00p08n01i01859ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    ibus, obus      : cmd_bus(small_int);
+  signal    s_int          : small_int := 0;
+  signal   bool         : boolean;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01859 - Process labels are not permitted as primaries in an index expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  s: bool <= s_int = ibus'right(1) after 5 ns;
+
+  with bool select
+    obus (TESTING)   <= 5 after 5 ns when true, -- process labels illegal here
+    obus (5)       <= 4 after 5 ns when false; 
+
+END c07s01b00x00p08n01i01859arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc186.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc186.vhd
new file mode 100644
index 0000000..0953764
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc186.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc186.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s04b00x00p12n01i00186ent IS
+END c04s04b00x00p12n01i00186ent;
+
+ARCHITECTURE c04s04b00x00p12n01i00186arch OF c04s04b00x00p12n01i00186ent IS
+  attribute    POSI    : NATURAL;
+  attribute    POSI of S: signal is 10;    --- Failure_here
+  signal       S    : Integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c04s04b00x00p12n01i00186 - Entity declaration does not exist."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s04b00x00p12n01i00186arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1860.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1860.vhd
new file mode 100644
index 0000000..9c2c09a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1860.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1860.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01860ent IS
+END c07s01b00x00p08n01i01860ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01860arch OF c07s01b00x00p08n01i01860ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+
+    lop : for i in small_int loop
+      obus(lop) <= 5 after 5 ns;
+    end loop lop;
+
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01860 - Loop labels are not permitted as primaries in an index expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01860arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1861.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1861.vhd
new file mode 100644
index 0000000..76bfe53
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1861.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1861.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01861ent IS
+END c07s01b00x00p08n01i01861ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01861arch OF c07s01b00x00p08n01i01861ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+  signal   bool         : boolean;
+BEGIN
+  sig : bool    <= true after 5 ns;
+
+  obus(sig)   <= 5    after 5 ns;   --signal assignment label illegal here
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01861 - Signal assignment labels are not permitted as primaries in an index expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01861arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1862.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1862.vhd
new file mode 100644
index 0000000..c7928dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1862.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1862.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01862ent IS
+END c07s01b00x00p08n01i01862ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01862arch OF c07s01b00x00p08n01i01862ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+  signal   s_int         : small_int;   
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int<=obus'right(c07s01b00x00p08n01i01862arch) after 5 ns; --architecture body name illegal here 
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01862 - Architecture body names are not permitted as primaries in an attribute expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01862arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1863.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1863.vhd
new file mode 100644
index 0000000..62d04d0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1863.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1863.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01863ent IS
+END c07s01b00x00p08n01i01863ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01863arch OF c07s01b00x00p08n01i01863ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+  signal   s_int         : small_int;   
+BEGIN
+
+  blk : block(s_int = 0)
+  begin
+    s_int <= obus'right(blk) after 5 ns;  -- block label illegal here
+  end block blk;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01863 - Block labels are not permitted as primaries in an attribute expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01863arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1864.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1864.vhd
new file mode 100644
index 0000000..cb881bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1864.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1864.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01864ent IS
+END c07s01b00x00p08n01i01864ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01864arch OF c07s01b00x00p08n01i01864ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+  signal   s_int         : small_int;   
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= obus'right(TESTING) after 5 ns;  -- process label illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01864 - Process labels are not permitted as primaries in an attribute expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01864arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1865.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1865.vhd
new file mode 100644
index 0000000..f4df796
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1865.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1865.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01865ent IS
+END c07s01b00x00p08n01i01865ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01865arch OF c07s01b00x00p08n01i01865ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+  signal   s_int         : small_int;   
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    lop : for i in small_int loop
+      s_int <= obus'right(lop) after 5 ns;  -- loop label illegal here
+    end loop lop;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01865 - Loop labels are not permitted as primaries in an attribute expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01865arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1866.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1866.vhd
new file mode 100644
index 0000000..5fa0656
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1866.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1866.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01866ent IS
+END c07s01b00x00p08n01i01866ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01866arch OF c07s01b00x00p08n01i01866ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+  signal   s_int         : small_int;   
+  signal   bool         : boolean;
+BEGIN
+  sig : bool <= true after 5 ns;   
+
+  TESTING : PROCESS
+  BEGIN
+    s_int <= obus'right(sig) after 5 ns;  -- signal assignment label illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01866 - Signal assignment labels are not permitted as primaries in an attribute expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01866arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1867.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1867.vhd
new file mode 100644
index 0000000..55d962b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1867.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1867.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01867ent IS
+END c07s01b00x00p08n01i01867ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01867arch OF c07s01b00x00p08n01i01867ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+  signal   s_int         : small_int;   
+  signal   bool         : boolean;
+BEGIN
+  with c07s01b00x00p08n01i01867arch select   --body name illegal here
+      obus <= (0 => 1, others => 0) after 5 ns when true;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01867 - Architecture body names are not permitted as primaries in a selected signal expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01867arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1868.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1868.vhd
new file mode 100644
index 0000000..3d34562
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1868.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1868.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01868ent IS
+END c07s01b00x00p08n01i01868ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01868arch OF c07s01b00x00p08n01i01868ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+  signal   s_int         : small_int;   
+  signal   bool         : boolean;
+BEGIN
+  blk : block (s_int = 0)
+  begin
+    with blk select    -- block label illegal here
+         obus(0) <= 5 after 5 ns when true;
+  end block blk;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01868 - Block labels are not permitted as primaries in a selected signal expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01868arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1869.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1869.vhd
new file mode 100644
index 0000000..beac8b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1869.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1869.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01869ent IS
+END c07s01b00x00p08n01i01869ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01869arch OF c07s01b00x00p08n01i01869ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01869 - Process labels are not permitted as primaries in a selected signal expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  with TESTING select   --process label illegal here
+      obus(0)   <= 5 after 5 ns when true;
+
+END c07s01b00x00p08n01i01869arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1870.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1870.vhd
new file mode 100644
index 0000000..b766400
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1870.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1870.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01870ent IS
+END c07s01b00x00p08n01i01870ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01870arch OF c07s01b00x00p08n01i01870ent IS
+  type    small_int       is range 0 to 7;
+  type    cmd_bus       is array (small_int range <>) of small_int;
+  signal    obus          : cmd_bus(small_int);
+  signal   bool         : boolean;
+BEGIN
+
+  sig : bool   <= true after 5 ns;
+
+  with sig select      -- signal assignment label illegal here
+      obus(0)   <= 5 after 5 ns when true;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01870 - Signal assignment labels are not permitted as primaries in a selected signal expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01870arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1871.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1871.vhd
new file mode 100644
index 0000000..62b123b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1871.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1871.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01871ent IS
+END c07s01b00x00p08n01i01871ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01871arch OF c07s01b00x00p08n01i01871ent IS
+  type    small_int       is range 0 to 7;
+
+  function value return small_int is
+    variable tmp : small_int := 0;   
+  begin
+    case tmp is
+      when 0       => tmp := 0;
+      when others    => tmp := 1;
+    end case;
+    return c07s01b00x00p08n01i01871arch;  -- architecture body name illegal here         
+  end value;
+
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01871 - Architecture body names are not permitted as primaries in a function return expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01871arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1872.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1872.vhd
new file mode 100644
index 0000000..ea820aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1872.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1872.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01872ent IS
+END c07s01b00x00p08n01i01872ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01872arch OF c07s01b00x00p08n01i01872ent IS
+  type    small_int       is range 0 to 7;
+  signal   s_int         : small_int;
+BEGIN
+
+  blk : block (s_int = 0)
+    function value return small_int is
+      variable tmp : small_int := 0; 
+    begin
+      case tmp is
+        when 0          => tmp := 0;
+        when others     => tmp := 1;
+      end case;
+      return blk;  -- block labels illegal here
+    end value;
+  begin
+  end block blk;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01872 - Block labels are not permitted as primaries in a function return expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01872arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1873.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1873.vhd
new file mode 100644
index 0000000..0d6008d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1873.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1873.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01873ent IS
+END c07s01b00x00p08n01i01873ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01873arch OF c07s01b00x00p08n01i01873ent IS
+  type    small_int       is range 0 to 7;
+BEGIN
+  TESTING : PROCESS
+
+    function value return small_int is
+      variable tmp : small_int := 0; 
+    begin
+      case tmp is
+        when 0          => tmp := 0;
+        when others     => tmp := 1;
+      end case;
+      return TESTING;  -- process labels illegal here
+    end value;
+
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01873d - Process labels are not permitted as primaries in a function return expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01873arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1874.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1874.vhd
new file mode 100644
index 0000000..f54be03
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1874.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1874.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01874ent IS
+END c07s01b00x00p08n01i01874ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01874arch OF c07s01b00x00p08n01i01874ent IS
+  type    small_int       is range 0 to 7;
+  signal   s_int         : small_int;
+  signal   bool         : boolean;
+BEGIN
+  sig : bool <= true after 5 ns;
+
+  b : block (s_int = 0)
+    function value return small_int is
+      variable tmp : small_int := 0; 
+    begin
+      case tmp is
+        when 0          => tmp := 0;
+        when others     => tmp := 1;
+      end case;
+      return sig;  -- signal assignment labels illegal here
+    end value;
+  begin   
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01874 - Signal assignment labels are not permitted as primaries in a function return expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01874arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1875.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1875.vhd
new file mode 100644
index 0000000..aff7d9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1875.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1875.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01875ent IS
+END c07s01b00x00p08n01i01875ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01875arch OF c07s01b00x00p08n01i01875ent IS
+  type    small_int       is range 0 to 7;
+BEGIN
+  TESTING : PROCESS
+    variable car : small_int;
+  BEGIN
+    car := c07s01b00x00p08n01i01875arch;   --architecture body name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01875 - Architecture body names are not permitted as primaries in a variable assignment expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01875arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1876.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1876.vhd
new file mode 100644
index 0000000..00af8af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1876.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1876.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01876ent IS
+END c07s01b00x00p08n01i01876ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01876arch OF c07s01b00x00p08n01i01876ent IS
+  type    small_int       is range 0 to 7;
+  signal   s_int         : small_int;
+BEGIN
+  blk : block (s_int = 0)
+  begin
+  end block blk;
+
+  TESTING : PROCESS
+    variable car : small_int;
+  BEGIN
+    car := blk;   --block labels illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01876 - Block labels are not permitted as primaries in a variable assignment expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01876arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1877.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1877.vhd
new file mode 100644
index 0000000..24fe41d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1877.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1877.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01877ent IS
+END c07s01b00x00p08n01i01877ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01877arch OF c07s01b00x00p08n01i01877ent IS
+  type    small_int       is range 0 to 7;
+BEGIN
+  TESTING : PROCESS
+    variable car : small_int;
+  BEGIN
+    car := TESTING;   --process labels illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01877 - Process labels are not permitted as primaries in a variable assignment expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01877arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1878.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1878.vhd
new file mode 100644
index 0000000..88e20dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1878.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1878.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01878ent IS
+END c07s01b00x00p08n01i01878ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01878arch OF c07s01b00x00p08n01i01878ent IS
+  type    small_int    is range 0 to 7;
+  signal   bool      : boolean;
+BEGIN
+  sig : bool <= true after 5 ns;
+
+  TESTING : PROCESS
+    variable car : small_int;
+  BEGIN
+    car := sig;   --signal assignment labels illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01878 - Signal assignment labels are not permitted as primaries in a variable assignment expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01878arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1879.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1879.vhd
new file mode 100644
index 0000000..5e5d600
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1879.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1879.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01879ent IS
+END c07s01b00x00p08n01i01879ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01879arch OF c07s01b00x00p08n01i01879ent IS
+  type    small_int    is range 0 to 7;
+BEGIN
+
+  TESTING : PROCESS
+    variable tmp : small_int;
+  BEGIN
+    case c07s01b00x00p08n01i01879arch is       -- body name illegal here
+      when 0       => tmp := 0;
+      when others    => tmp := 1;
+    end case;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01879 - Architecture body names are not permitted as primaries in a case expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01879arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1880.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1880.vhd
new file mode 100644
index 0000000..6fc6ebf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1880.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1880.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01880ent IS
+END c07s01b00x00p08n01i01880ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01880arch OF c07s01b00x00p08n01i01880ent IS
+  type    small_int    is range 0 to 7;
+  signal   s_int      : small_int;
+BEGIN
+  blk : block(s_int = 0)
+  begin
+  end block blk;
+
+  TESTING : PROCESS
+    variable tmp : small_int;
+  BEGIN
+    case blk is       -- block labels illegal here
+      when 0       => tmp := 0;
+      when others    => tmp := 1;
+    end case;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01880 - Block labels are not permitted as primaries in a case expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01880arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1881.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1881.vhd
new file mode 100644
index 0000000..0782507
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1881.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1881.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01881ent IS
+END c07s01b00x00p08n01i01881ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01881arch OF c07s01b00x00p08n01i01881ent IS
+  type    small_int    is range 0 to 7;
+BEGIN
+
+  TESTING : PROCESS
+    variable tmp : small_int;
+  BEGIN
+    case TESTING is       -- process labels illegal here
+      when 0       => tmp := 0;
+      when others    => tmp := 1;
+    end case;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01881 - Process labels are not permitted as primaries in a case expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01881arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1882.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1882.vhd
new file mode 100644
index 0000000..4d9b480
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1882.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1882.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01882ent IS
+END c07s01b00x00p08n01i01882ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01882arch OF c07s01b00x00p08n01i01882ent IS
+  type    small_int    is range 0 to 7;
+  signal   s_int      : small_int;
+  signal   bool      : boolean;
+BEGIN
+  sig : bool <= true;
+
+  TESTING : PROCESS
+    variable tmp : small_int;
+  BEGIN
+    case sig is       -- signal assignment labels illegal here
+      when 0       => tmp := 0;
+      when others    => tmp := 1;
+    end case;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01882 - Signal assignment labels are not permitted as primaries in a case expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01882arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1883.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1883.vhd
new file mode 100644
index 0000000..01841f0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1883.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1883.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01883ent IS
+END c07s01b00x00p08n01i01883ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01883arch OF c07s01b00x00p08n01i01883ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    obus      : cmd_bus(small_int);
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    obus <= (0 =>c07s01b00x00p08n01i01883arch, others => 5) after 5 ns; 
+    -- architecture body name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01883 - Architecture body names are not permitted as primaries in a element association expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01883arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1884.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1884.vhd
new file mode 100644
index 0000000..843f71e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1884.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1884.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01884ent IS
+END c07s01b00x00p08n01i01884ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01884arch OF c07s01b00x00p08n01i01884ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal   s_int      : small_int;
+  signal    obus      : cmd_bus(small_int);
+BEGIN
+
+  blk : block (s_int = 0)
+  begin
+  end block blk;
+
+  TESTING : PROCESS
+  BEGIN
+    obus <= (0 => blk, others => 5) after 5 ns; -- block label illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01884 - Block labels are not permitted as primaries in a element association expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01884arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1885.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1885.vhd
new file mode 100644
index 0000000..9b3deba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1885.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1885.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01885ent IS
+END c07s01b00x00p08n01i01885ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01885arch OF c07s01b00x00p08n01i01885ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    obus      : cmd_bus(small_int);
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    obus <= (0 => TESTING, others => 5) after 5 ns; -- process label illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01885 - Process labels are not permitted as primaries in a element association expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01885arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1886.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1886.vhd
new file mode 100644
index 0000000..2c8c941
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1886.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1886.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01886ent IS
+END c07s01b00x00p08n01i01886ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01886arch OF c07s01b00x00p08n01i01886ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    obus      : cmd_bus(small_int);
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    lop : for i in small_int loop
+      obus <= (0 => lop, others => 5) after 5 ns; -- loop label illegal here
+    end loop;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01886 - Loop labels are not permitted as primaries in a element association expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01886arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1887.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1887.vhd
new file mode 100644
index 0000000..459e713
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1887.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1887.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01887ent IS
+END c07s01b00x00p08n01i01887ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01887arch OF c07s01b00x00p08n01i01887ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    obus      : cmd_bus(small_int);
+  signal   bool      : boolean;
+BEGIN
+  sig : bool <= true;
+
+  TESTING : PROCESS
+  BEGIN
+    obus <= (0 => sig, others => 5) after 5 ns; 
+    -- signal assignment label illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01887 - Signal assignment labels are not permitted as primaries in a element association expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01887arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1888.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1888.vhd
new file mode 100644
index 0000000..203c20b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1888.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1888.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01888ent IS
+END c07s01b00x00p08n01i01888ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01888arch OF c07s01b00x00p08n01i01888ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    ibus      : cmd_bus(small_int);
+  signal   s_int      : small_int;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= ibus'right(small_int'(c07s01b00x00p08n01i01888arch)) after 5 ns; 
+    -- architecture body name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01888 - Architecture body names are not permitted as primaries in a qualified expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01888arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1889.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1889.vhd
new file mode 100644
index 0000000..fff5920
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1889.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1889.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01889ent IS
+END c07s01b00x00p08n01i01889ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01889arch OF c07s01b00x00p08n01i01889ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    ibus      : cmd_bus(small_int);
+  signal   s_int      : small_int;
+BEGIN
+
+  blk : block (s_int = 0)
+  begin
+  end block blk;
+
+  TESTING : PROCESS
+  BEGIN
+    s_int <= ibus'right(small_int'(blk)) after 5 ns; 
+    -- architecture body name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01889 - Block labels are not permitted as primaries in a qualified expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01889arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc189.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc189.vhd
new file mode 100644
index 0000000..4016b2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc189.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc189.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s05b00x00p02n01i00189ent IS
+END c04s05b00x00p02n01i00189ent;
+
+ARCHITECTURE c04s05b00x00p02n01i00189arch OF c04s05b00x00p02n01i00189ent IS
+  component A2 generic (constant G2 : out BOOLEAN);  -- Failure_here
+               -- ERROR: the
+               -- only mode allowed in a
+               -- local generic list is in.
+  end component ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s05b00x00p02n01i00189 - Mode out is not allowed in a local generic."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s05b00x00p02n01i00189arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1890.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1890.vhd
new file mode 100644
index 0000000..010e94a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1890.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1890.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01890ent IS
+END c07s01b00x00p08n01i01890ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01890arch OF c07s01b00x00p08n01i01890ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    ibus      : cmd_bus(small_int);
+  signal   s_int      : small_int;
+BEGIN
+
+  TESTING : PROCESS
+  BEGIN
+    s_int <= ibus'right(small_int'(TESTING)) after 5 ns; 
+    -- process label illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01890 - Process labels are not permitted as primaries in a qualified expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01890arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1891.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1891.vhd
new file mode 100644
index 0000000..063bc09
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1891.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1891.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01891ent IS
+END c07s01b00x00p08n01i01891ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01891arch OF c07s01b00x00p08n01i01891ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    ibus      : cmd_bus(small_int);
+  signal   s_int      : small_int;
+BEGIN
+
+  TESTING : PROCESS
+  BEGIN
+    lop : for i in small_int loop
+      s_int <= ibus'right(small_int'(lop)) after 5 ns; 
+      -- loop label illegal here
+    end loop lop;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01891 - Loop labels are not permitted as primaries in a qualified expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01891arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1892.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1892.vhd
new file mode 100644
index 0000000..3e50ad5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1892.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1892.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01892ent IS
+END c07s01b00x00p08n01i01892ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01892arch OF c07s01b00x00p08n01i01892ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    ibus      : cmd_bus(small_int);
+  signal   s_int      : small_int;
+BEGIN
+  sig : s_int <= 0;
+
+  TESTING : PROCESS
+  BEGIN
+    s_int <= ibus'right(small_int'(sig)) after 5 ns; 
+    -- signal assignment label illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01892 - Signal assignment labels are not permitted as primaries in a qualified expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01892arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1893.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1893.vhd
new file mode 100644
index 0000000..f01cc24
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1893.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1893.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01893ent IS
+END c07s01b00x00p08n01i01893ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01893arch OF c07s01b00x00p08n01i01893ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    ibus      : cmd_bus(small_int);
+  signal   s_int      : small_int;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= ibus'right(small_int(c07s01b00x00p08n01i01893arch)) after 5 ns;
+    -- architecture body name illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01893 - Architecture body names are not permitted as primaries in a type conversion expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01893arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1894.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1894.vhd
new file mode 100644
index 0000000..074fc48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1894.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1894.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01894ent IS
+END c07s01b00x00p08n01i01894ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01894arch OF c07s01b00x00p08n01i01894ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    ibus      : cmd_bus(small_int);
+  signal   s_int      : small_int;
+BEGIN
+  blk : block(s_int = 0)
+  begin
+  end block blk;
+
+  TESTING : PROCESS
+  BEGIN
+    s_int <= ibus'right(small_int(blk)) after 5 ns;
+    -- block labels illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01894 - Block labels are not permitted as primaries in a type conversion expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01894arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1895.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1895.vhd
new file mode 100644
index 0000000..31b8a5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1895.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1895.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01895ent IS
+END c07s01b00x00p08n01i01895ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01895arch OF c07s01b00x00p08n01i01895ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    ibus      : cmd_bus(small_int);
+  signal   s_int      : small_int;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    s_int <= ibus'right(small_int(TESTING)) after 5 ns;
+    -- process labels illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01895 - Process labels are not permitted as primaries in a type conversion expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01895arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1896.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1896.vhd
new file mode 100644
index 0000000..7786b27
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1896.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1896.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01896ent IS
+END c07s01b00x00p08n01i01896ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01896arch OF c07s01b00x00p08n01i01896ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    ibus      : cmd_bus(small_int);
+  signal   s_int      : small_int;
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    lop : for i in small_int loop
+      s_int <= ibus'right(small_int(lop)) after 5 ns;
+      -- loop labels illegal here
+    end loop lop;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01896 - Loop labels are not permitted as primaries in a type conversion expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01896arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1897.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1897.vhd
new file mode 100644
index 0000000..4ff8e28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1897.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1897.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01897ent IS
+END c07s01b00x00p08n01i01897ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01897arch OF c07s01b00x00p08n01i01897ent IS
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  signal    ibus      : cmd_bus(small_int);
+  signal   s_int      : small_int;
+  signal   bool      : boolean;
+BEGIN
+  sig : bool <= true;
+
+  TESTING : PROCESS
+  BEGIN
+    s_int <= ibus'right(small_int(sig)) after 5 ns;
+    -- signal assignment labels illegal here
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01897 - Signal assignment labels are not permitted as primaries in a type conversion expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01897arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1898.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1898.vhd
new file mode 100644
index 0000000..5e4b43c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1898.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1898.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s01b00x00p08n01i01898pkg is
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  constant    bus_width    : small_int := 7;
+end c07s01b00x00p08n01i01898pkg;
+
+
+use work.c07s01b00x00p08n01i01898pkg.all;
+entity c07s01b00x00p08n01i01898ent_a is
+  generic    ( constant bus_width : small_int);
+  port    ( signal in_bus  : in  cmd_bus (0 to bus_width);
+            signal out_bus : out cmd_bus (0 to bus_width));
+end c07s01b00x00p08n01i01898ent_a;
+
+architecture c07s01b00x00p08n01i01898arch_a of c07s01b00x00p08n01i01898ent_a is
+begin
+  assert true ;
+end c07s01b00x00p08n01i01898arch_a;
+
+
+use work.c07s01b00x00p08n01i01898pkg.all;
+ENTITY c07s01b00x00p08n01i01898ent IS
+END c07s01b00x00p08n01i01898ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01898arch OF c07s01b00x00p08n01i01898ent IS
+
+  constant    bus_width    : natural    := 8;
+  signal    s_int       : small_int    := 0;
+  signal    ibus, obus, obus2 : cmd_bus(small_int);
+
+  component test
+    generic ( constant bus_width : small_int := 5 );
+    port ( signal in_bus    : in  cmd_bus (0 to small_int(bus_width));
+           signal out_bus    : out cmd_bus (0 to small_int(bus_width)));
+  end component;
+
+BEGIN
+  b: block ( s_int = 0 )
+    signal bool : boolean := false;
+    
+    function value return small_int is
+      variable tmp : small_int := 0;
+    begin
+      case tmp is
+        when 0 =>
+          tmp := 0;
+        when others =>
+          tmp := 1;
+      end case;
+      
+      return tmp;
+    end value;
+    
+    for c : test use entity work.c07s01b00x00p08n01i01898ent_a(c07s01b00x00p08n01i01898arch_a);
+  begin
+    obus    <= (0 => 1, others => 0) after 5 ns;
+    s: bool <= s_int = ibus'right(1) after 5 ns;
+    
+    c : test
+      generic map ( c07s01b00x00p08n01i01898arch ) --architecture body name illegal here
+      port map ( ibus, obus2 );
+    
+    p: process ( s_int )
+    begin
+      l: for i in small_int loop
+        assert false
+          report "body name accepted as primary in a component instantiation generic map expression."
+          severity note ;
+        exit l;
+      end loop l;
+    end process p;
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01898 - Architecture body names are not permitted as primaries in a component instantiation generic map expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01898arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1899.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1899.vhd
new file mode 100644
index 0000000..28f3320
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1899.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1899.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s01b00x00p08n01i01899pkg is
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  constant    bus_width    : small_int := 7;
+end c07s01b00x00p08n01i01899pkg;
+
+
+use work.c07s01b00x00p08n01i01899pkg.all;
+entity c07s01b00x00p08n01i01899ent_a is
+  generic    ( constant bus_width : small_int);
+  port    ( signal in_bus : in cmd_bus (0 to bus_width);
+            signal out_bus : out cmd_bus (0 to bus_width));
+end c07s01b00x00p08n01i01899ent_a;
+
+architecture c07s01b00x00p08n01i01899arch_a of c07s01b00x00p08n01i01899ent_a is
+begin
+  assert true ;
+end c07s01b00x00p08n01i01899arch_a;
+
+
+use work.c07s01b00x00p08n01i01899pkg.all;
+ENTITY c07s01b00x00p08n01i01899ent IS
+END c07s01b00x00p08n01i01899ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01899arch OF c07s01b00x00p08n01i01899ent IS
+
+  constant    bus_width    : natural    := 8;
+  signal    s_int       : small_int    := 0;
+  signal    ibus, obus, obus2 : cmd_bus(small_int);
+
+  component test
+    generic ( constant bus_width : small_int := 5 );
+    port ( signal in_bus    : in  cmd_bus (0 to small_int(bus_width));
+           signal out_bus    : out cmd_bus (0 to small_int(bus_width)));
+  end component;
+
+BEGIN
+  b: block ( s_int = 0 )
+    signal bool : boolean := false;
+    
+    function value return small_int is
+      variable tmp : small_int := 0;
+    begin
+      case tmp is
+        when 0 =>
+          tmp := 0;
+        when others =>
+          tmp := 1;
+      end case;
+      
+      return tmp;
+    end value;
+    
+    for c : test use entity work.c07s01b00x00p08n01i01899ent_a(c07s01b00x00p08n01i01899arch_a);
+  begin
+    obus    <= (0 => 1, others => value) after 5 ns;
+    s: bool <= s_int = ibus'right(1) after 5 ns;
+    
+    c : test
+      generic map ( b ) --block labels illegal here
+      port map ( ibus, obus2 );
+    
+    p: process ( s_int )
+    begin
+      l: for i in small_int loop
+        assert false
+          report "body name accepted as primary in a component instantiation generic map expression."
+          severity note ;
+        exit l;
+      end loop l;
+    end process p;
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01899d - Block labels are not permitted as primaries in a component instantiation generic map expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01899arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc19.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc19.vhd
new file mode 100644
index 0000000..c0e70b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc19.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc19.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p09n03i00019ent IS
+END c04s02b00x00p09n03i00019ent;
+
+ARCHITECTURE c04s02b00x00p09n03i00019arch OF c04s02b00x00p09n03i00019ent IS
+  type A1 is range 50 to 100;
+  subtype B1 is A1 range 1 to 60;             -- Failure_here
+  subtype C1 is B1 range 2 to 50;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST:c04s02b00x00p09n03i00019 - Range constraints for the subtype declarations contradict the range of the subtype indication.(integer)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p09n03i00019arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc190.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc190.vhd
new file mode 100644
index 0000000..decdbaa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc190.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc190.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s05b00x00p02n01i00190ent IS
+END c04s05b00x00p02n01i00190ent;
+
+ARCHITECTURE c04s05b00x00p02n01i00190arch OF c04s05b00x00p02n01i00190ent IS
+  component A2 generic (constant G2 : inout BOOLEAN);  -- Failure_here
+               -- ERROR: the
+               -- only mode allowed in a
+               -- local generic list is in.
+  end component ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s05b00x00p02n01i00190 - Mode inout is not allowed in a local generic."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s05b00x00p02n01i00190arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1900.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1900.vhd
new file mode 100644
index 0000000..0a5d333
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1900.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1900.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p08n01i01900ent_a IS
+  generic ( constant bus_width : natural);
+  port ( signal in_bus : in integer;
+         signal out_bus : out integer);
+END c07s01b00x00p08n01i01900ent_a;
+
+ARCHITECTURE c07s01b00x00p08n01i01900arch_a OF c07s01b00x00p08n01i01900ent_a IS
+BEGIN
+  assert true;
+END c07s01b00x00p08n01i01900arch_a;
+
+
+ENTITY c07s01b00x00p08n01i01900ent IS
+END c07s01b00x00p08n01i01900ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01900arch OF c07s01b00x00p08n01i01900ent IS
+
+  constant    bus_width       : natural:= 8;
+  signal    s_int          : integer;
+  signal    ibus, obus, obus2    : integer;
+
+  component test
+    generic ( constant bus_width : natural := 5 );
+    port ( signal in_bus    : in  integer; 
+           signal out_bus    : out integer ); 
+  end component;
+
+BEGIN
+  b: block ( s_int = 0 )
+    for c2 : test use entity work.ch0701_p00801_91_ent_a(c07s01b00x00p08n01i01900arch_a);
+  begin
+    p: process ( s_int )
+    begin
+      l: for i in 0 to 7 loop
+        assert false
+          report "process labels accepted as primary in a component instantiation generic map expression."
+          severity note ;
+        exit l;
+      end loop l;
+    end process p;
+    c2 : test    generic map (p) -- process label illegal here
+      port map (ibus, obus2);
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01900 - Process labels are not permitted as primaries in a component instantiation generic map expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01900arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1901.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1901.vhd
new file mode 100644
index 0000000..3f4fda6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1901.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1901.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s01b00x00p08n01i01901pkg is
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  constant    bus_width    :  small_int := 7;
+end c07s01b00x00p08n01i01901pkg;
+
+use work.c07s01b00x00p08n01i01901pkg.all;
+ENTITY c07s01b00x00p08n01i01901ent_a IS
+  port ( signal in_bus  : in    cmd_bus (0 to bus_width);
+         signal out_bus : out cmd_bus (0 to bus_width));
+END c07s01b00x00p08n01i01901ent_a;
+
+ARCHITECTURE c07s01b00x00p08n01i01901arch_a OF c07s01b00x00p08n01i01901ent_a IS
+BEGIN
+  assert true;
+END c07s01b00x00p08n01i01901arch_a;
+
+
+use work.c07s01b00x00p08n01i01901pkg.all;
+ENTITY c07s01b00x00p08n01i01901ent IS
+END c07s01b00x00p08n01i01901ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01901arch OF c07s01b00x00p08n01i01901ent IS
+
+  constant    bus_width       : natural    := 7;
+  signal    s_int          : small_int    := 0;
+  signal    ibus, obus, obus2    : cmd_bus(small_int);
+
+  component test
+    port ( signal in_bus    : in  cmd_bus (0 to small_int(bus_width));
+           signal out_bus    : out cmd_bus (0 to small_int(bus_width))); 
+  end component;
+
+BEGIN
+  b: block ( s_int = 0 )
+    signal bool : boolean := false;
+
+    function value return small_int is
+      variable tmp : small_int := 0;
+    begin
+      case tmp is
+        when 0 =>
+          tmp := 0;
+        when others =>
+          tmp := 1;
+      end case;
+      return tmp;
+    end value;
+
+    for c : test use entity work.c07s01b00x00p08n01i01901ent_a(c07s01b00x00p08n01i01901arch_a);
+  begin
+    obus <= (0 => 1, others => value) after 5 ns;
+    s: bool <= s_int = ibus'right(1) after 5 ns;
+    
+    c : test port map ( ibus, c07s01b00x00p08n01i01901arch ); -- body name illegal here 
+
+    p: process ( s_int )
+    begin
+      l: for i in small_int loop
+        assert false
+          report "body name accepted as primary in a component instantiation port map expression."
+          severity note ;
+        exit l;
+      end loop l;
+    end process p;
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01901 - Architecture body name are not permitted as primaries in a component instantiation port map expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01901arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1902.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1902.vhd
new file mode 100644
index 0000000..207e699
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1902.vhd
@@ -0,0 +1,107 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1902.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s01b00x00p08n01i01902pkg is
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  constant    bus_width    :  small_int := 7;
+end c07s01b00x00p08n01i01902pkg;
+
+use work.c07s01b00x00p08n01i01902pkg.all;
+ENTITY c07s01b00x00p08n01i01902ent_a IS
+  port ( signal in_bus : in cmd_bus (0 to bus_width);
+         signal out_bus : out cmd_bus (0 to bus_width));
+END c07s01b00x00p08n01i01902ent_a;
+
+ARCHITECTURE c07s01b00x00p08n01i01902arch_a OF c07s01b00x00p08n01i01902ent_a IS
+BEGIN
+  assert true;
+END c07s01b00x00p08n01i01902arch_a;
+
+
+use work.c07s01b00x00p08n01i01902pkg.all;
+ENTITY c07s01b00x00p08n01i01902ent IS
+END c07s01b00x00p08n01i01902ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01902arch OF c07s01b00x00p08n01i01902ent IS
+
+  constant    bus_width       : natural    := 7;
+  signal    s_int          : small_int    := 0;
+  signal    ibus, obus, obus2    : cmd_bus(small_int);
+
+  component test
+    port ( signal in_bus    : in  cmd_bus (0 to small_int(bus_width));
+           signal out_bus    : out cmd_bus (0 to small_int(bus_width))); 
+  end component;
+
+BEGIN
+  b: block ( s_int = 0 )
+    signal bool : boolean := false;
+
+    function value return small_int is
+      variable tmp : small_int := 0;
+    begin
+      case tmp is
+        when 0 =>
+          tmp := 0;
+        when others =>
+          tmp := 1;
+      end case;
+      return tmp;
+    end value;
+
+    for c : test use entity work.c07s01b00x00p08n01i01902ent_a(c07s01b00x00p08n01i0190293_arch_a);
+  begin
+    obus <= (0 => 1, others => value) after 5 ns;
+    s: bool <= s_int = ibus'right(1) after 5 ns;
+    
+    c : test port map ( ibus, b ); -- block label illegal here 
+
+    p: process ( s_int )
+    begin
+      l: for i in small_int loop
+        assert false
+          report "block label accepted as primary in a component instantiation port map expression."
+          severity note ;
+        exit l;
+      end loop l;
+    end process p;
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01902 - Block labels are not permitted as primaries in a component instantiation port map expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01902arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1903.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1903.vhd
new file mode 100644
index 0000000..da4480a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1903.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1903.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s01b00x00p08n01i01903pkg is
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  constant    bus_width    :  small_int := 7;
+end c07s01b00x00p08n01i01903pkg;
+
+use work.c07s01b00x00p08n01i01903pkg.all;
+ENTITY c07s01b00x00p08n01i01903ent_a IS
+  port ( signal in_bus    : in    cmd_bus (0 to bus_width);
+         signal out_bus    : out    cmd_bus (0 to bus_width));
+END c07s01b00x00p08n01i01903ent_a;
+
+ARCHITECTURE c07s01b00x00p08n01i01903arch_a OF c07s01b00x00p08n01i01903ent_a IS
+BEGIN
+  assert true;
+END c07s01b00x00p08n01i01903arch_a;
+
+
+use work.c07s01b00x00p08n01i01903pkg.all;
+ENTITY c07s01b00x00p08n01i01903ent IS
+END c07s01b00x00p08n01i01903ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01903arch OF c07s01b00x00p08n01i01903ent IS
+
+  constant    bus_width       : natural    := 7;
+  signal    s_int          : small_int    := 0;
+  signal    ibus, obus, obus2    : cmd_bus(small_int);
+
+  component test
+    port ( signal in_bus    : in  cmd_bus (0 to small_int(bus_width));
+           signal out_bus    : out cmd_bus (0 to small_int(bus_width))); 
+  end component;
+
+BEGIN
+  b: block ( s_int = 0 )
+    signal bool : boolean := false;
+
+    function value return small_int is
+      variable tmp : small_int := 0;
+    begin
+      case tmp is
+        when 0 =>
+          tmp := 0;
+        when others =>
+          tmp := 1;
+      end case;
+      return tmp;
+    end value;
+
+    for c : test use entity work.c07s01b00x00p08n01i01903ent_a(c07s01b00x00p08n01i01903arch_a);
+  begin
+    obus <= (0 => 1, others => value) after 5 ns;
+    s: bool <= s_int = ibus'right(1) after 5 ns;
+    
+    p: process ( s_int )
+    begin
+      l: for i in small_int loop
+        assert false
+          report "process label accepted as primary in a component instantiation port map expression."
+          severity note ;
+        exit l;
+      end loop l;
+    end process p;
+
+    c : test port map ( ibus, p ); -- process label illegal here 
+
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01903 - Process labels are not permitted as primaries in a component instantiation port map expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01903arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1904.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1904.vhd
new file mode 100644
index 0000000..ba8f1e9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1904.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1904.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s01b00x00p08n01i01904pkg is
+  type    small_int    is range 0 to 7;
+  type    cmd_bus    is array (small_int range <>) of small_int;
+  constant    bus_width    :  small_int := 7;
+end c07s01b00x00p08n01i01904pkg;
+
+use work.c07s01b00x00p08n01i01904pkg.all;
+ENTITY c07s01b00x00p08n01i01904ent_a IS
+  port ( signal in_bus : in cmd_bus (0 to bus_width);
+         signal out_bus : out cmd_bus (0 to bus_width));
+END c07s01b00x00p08n01i01904ent_a;
+
+ARCHITECTURE c07s01b00x00p08n01i01904arch_a OF c07s01b00x00p08n01i01904ent_a IS
+BEGIN
+  assert true;
+END c07s01b00x00p08n01i01904arch_a;
+
+
+use work.c07s01b00x00p08n01i01904pkg.all;
+ENTITY c07s01b00x00p08n01i01904ent IS
+END c07s01b00x00p08n01i01904ent;
+
+ARCHITECTURE c07s01b00x00p08n01i01904arch OF c07s01b00x00p08n01i01904ent IS
+
+  constant    bus_width       : natural    := 7;
+  signal    s_int          : small_int    := 0;
+  signal    ibus, obus, obus2    : cmd_bus(small_int);
+
+  component test
+    port ( signal in_bus    : in  cmd_bus (0 to small_int(bus_width - 1));
+           signal out_bus    : out cmd_bus (0 to small_int(bus_width - 1))); 
+  end component;
+
+BEGIN
+  b: block ( s_int = 0 )
+    signal bool : boolean := false;
+
+    function value return small_int is
+      variable tmp : small_int := 0;
+    begin
+      case tmp is
+        when 0 =>
+          tmp := 0;
+        when others =>
+          tmp := 1;
+      end case;
+      return tmp;
+    end value;
+
+    for c : test use entity work.c07s01b00x00p08n01i01904ent_a(c07s01b00x00p08n01i01904arch_a);
+  begin
+    obus <= (0 => 1, others => value) after 5 ns;
+    s: bool <= s_int = ibus'right(1) after 5 ns;
+    
+    c : test port map ( ibus, s ); -- signal assignment label illegal here 
+
+    p: process ( s_int )
+    begin
+      l: for i in small_int loop
+        assert false
+          report "signal assignment label accepted as primary in a component instantiation port map expression."
+          severity note ;
+        exit l;
+      end loop l;
+    end process p;
+
+  end block b;
+
+  TESTING : PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s01b00x00p08n01i01904 - Signal assignment labels are not permitted as primaries in a component instantiation port map expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p08n01i01904arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1905.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1905.vhd
new file mode 100644
index 0000000..4ab7e33
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1905.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1905.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s01b00x00p09n02i01905ent IS
+END c07s01b00x00p09n02i01905ent;
+
+ARCHITECTURE c07s01b00x00p09n02i01905arch OF c07s01b00x00p09n02i01905ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x, y: bit := '1';
+  BEGIN
+    y := x xor work; -- Failure_here
+    -- the name work has no value assigned to it.
+    assert FALSE 
+      report "***FAILED TEST: c07s01b00x00p09n02i01905 - Names denoting objects or values can only be used as primaries."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s01b00x00p09n02i01905arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc191.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc191.vhd
new file mode 100644
index 0000000..5183774
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc191.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc191.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s05b00x00p02n01i00191ent IS
+END c04s05b00x00p02n01i00191ent;
+
+ARCHITECTURE c04s05b00x00p02n01i00191arch OF c04s05b00x00p02n01i00191ent IS
+  component A2 generic (constant G2 : buffer BOOLEAN);  -- Failure_here
+               -- ERROR: the
+               -- only mode allowed in a
+               -- local generic list is in.
+  end component ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s05b00x00p02n01i00191 - Mode buffer is not allowed in a local generic."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s05b00x00p02n01i00191arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1913.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1913.vhd
new file mode 100644
index 0000000..ade51d7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1913.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1913.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n01i01913ent IS
+END c07s02b01x00p01n01i01913ent;
+
+ARCHITECTURE c07s02b01x00p01n01i01913arch OF c07s02b01x00p01n01i01913ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x : integer := 3;
+    variable y : integer := 5;
+    variable z : integer := 9;
+  BEGIN
+    if ((x and y) and (y or z)) then
+    end if;  -- logical operators defined only for BIT and BOOLEAN.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n01i01913 - Logical operators  defined only for predefined types BIT and BOOLEAN."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n01i01913arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc192.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc192.vhd
new file mode 100644
index 0000000..14fd88b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc192.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc192.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s05b00x00p02n01i00192ent IS
+END c04s05b00x00p02n01i00192ent;
+
+ARCHITECTURE c04s05b00x00p02n01i00192arch OF c04s05b00x00p02n01i00192ent IS
+  component A2 generic (constant G2 : linkage BOOLEAN);  -- Failure_here
+               -- ERROR: the
+               -- only mode allowed in a
+               -- local generic list is in.
+  end component ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s05b00x00p02n01i00192 - Mode linkage is not allowed in a local generic."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s05b00x00p02n01i00192arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1926.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1926.vhd
new file mode 100644
index 0000000..09c913d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1926.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1926.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01926ent IS
+END c07s02b01x00p01n02i01926ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01926arch OF c07s02b01x00p01n02i01926ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A is array ( 1 to 1, 1 to 1 ) of BOOLEAN;
+    variable A1 : A;
+  BEGIN
+    A1 := A'(1=>(1=>TRUE)) and A'(1=>(1=>FALSE)); -- Failure_here
+    -- SEMANTIC ERROR:  "and" not defined for multi-dimensional arrays.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n02i01926 - Logical operators are not valid for multi-dimensional arrays."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01926arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1927.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1927.vhd
new file mode 100644
index 0000000..2508a0e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1927.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1927.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01927ent IS
+END c07s02b01x00p01n02i01927ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01927arch OF c07s02b01x00p01n02i01927ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A is array ( 1 to 1, 1 to 1 ) of BOOLEAN;
+    variable A1 : A;
+  BEGIN
+    A1 := A'(1=>(1=>TRUE))  or A'(1=>(1=>FALSE)); -- Failure_here
+    -- SEMANTIC ERROR:   "or" not defined for multi-dimensional arrays.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n02i01927d - Logical operators are not valid for multi-dimensional arrays."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01927arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1928.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1928.vhd
new file mode 100644
index 0000000..1331dc6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1928.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1928.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01928ent IS
+END c07s02b01x00p01n02i01928ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01928arch OF c07s02b01x00p01n02i01928ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type B is array ( 1 to 1, 1 to 1 ) of BIT;
+    variable B1 : B;
+  BEGIN
+    B1 := B'(1=>(1=>'1')) xor B'(1=>(1=>'0')); -- Failure_here
+    -- SEMANTIC ERROR:  "xor" not defined for multi-dimensional arrays.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n02i01928 - Logical operators are not valid for multi-dimensional arrays."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01928arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1929.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1929.vhd
new file mode 100644
index 0000000..093883a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1929.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1929.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01929ent IS
+END c07s02b01x00p01n02i01929ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01929arch OF c07s02b01x00p01n02i01929ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type B is array ( 1 to 1, 1 to 1 ) of BIT;
+    variable B1 : B;
+  BEGIN
+    B1 := not B'(1=>(1=>'0')); -- Failure_here
+    -- SEMANTIC ERROR:  "not" not defined for multi-dimensional arrays.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n02i01929 - Logical operators are not valid for multi-dimensional arrays."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01929arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc193.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc193.vhd
new file mode 100644
index 0000000..4ce39da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc193.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc193.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s05b00x00p02n01i00193ent IS
+END c04s05b00x00p02n01i00193ent;
+
+ARCHITECTURE c04s05b00x00p02n01i00193arch OF c04s05b00x00p02n01i00193ent IS
+  component C1
+    generic (T1 : TIME; T2 : Integer) ;
+    port (P1 : in BIT;
+          P2 : out BIT ;
+          P3 : linkage BIT) ;
+  end component                 -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s05b00x00p02n01i00193 - Missing semicolon." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s05b00x00p02n01i00193arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1930.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1930.vhd
new file mode 100644
index 0000000..c2c3d35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1930.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1930.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n02i01930ent IS
+END c07s02b01x00p01n02i01930ent;
+
+ARCHITECTURE c07s02b01x00p01n02i01930arch OF c07s02b01x00p01n02i01930ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type B is array ( 1 to 1, 1 to 1 ) of BIT;
+    variable B1 : B;
+  BEGIN
+    B1 := B'(1=>(1=>'0')) nor B'(1=>(1=>'1')); -- Failure_here
+    -- SEMANTIC ERROR:  "nor" not defined for multi-dimensional arrays.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n02i01930 - Logical operators are not valid for multi-dimensional arrays."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n02i01930arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1933.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1933.vhd
new file mode 100644
index 0000000..b813cfd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1933.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1933.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01933ent IS
+END c07s02b01x00p01n04i01933ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01933arch OF c07s02b01x00p01n04i01933ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (positive range <>) of boolean;
+    variable x : array_one( 1 to 10);
+    variable y : array_one(1 to 5);
+    variable z : array_one(1 to 10);
+    type array_two is array (positive range <>) of bit;
+    variable a : array_two( 1 to 10);
+    variable b : array_two(1 to 5);
+    variable c : array_two(1 to 10);
+  BEGIN
+    z := (x and y);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n04i01933 - Operands should be arrays of the same length."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01933arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1934.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1934.vhd
new file mode 100644
index 0000000..dfd0fbe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1934.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1934.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01934ent IS
+END c07s02b01x00p01n04i01934ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01934arch OF c07s02b01x00p01n04i01934ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (positive range <>) of boolean;
+    variable x : array_one( 1 to 10);
+    variable y : array_one(1 to 5);
+    variable z : array_one(1 to 10);
+    type array_two is array (positive range <>) of bit;
+    variable a : array_two( 1 to 10);
+    variable b : array_two(1 to 5);
+    variable c : array_two(1 to 10);
+  BEGIN
+    z := (x or   y);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n04i01934 - Operands should be arrays of the same length."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01934arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1935.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1935.vhd
new file mode 100644
index 0000000..a56a660
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1935.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1935.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01935ent IS
+END c07s02b01x00p01n04i01935ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01935arch OF c07s02b01x00p01n04i01935ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (positive range <>) of boolean;
+    variable x : array_one( 1 to 10);
+    variable y : array_one(1 to 5);
+    variable z : array_one(1 to 10);
+    type array_two is array (positive range <>) of bit;
+    variable a : array_two( 1 to 10);
+    variable b : array_two(1 to 5);
+    variable c : array_two(1 to 10);
+  BEGIN
+    z := (x nand  y);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n04i01935 - Operands should be arrays of the same length."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01935arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1936.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1936.vhd
new file mode 100644
index 0000000..3a6a501
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1936.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1936.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01936ent IS
+END c07s02b01x00p01n04i01936ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01936arch OF c07s02b01x00p01n04i01936ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (positive range <>) of boolean;
+    variable x : array_one( 1 to 10);
+    variable y : array_one(1 to 5);
+    variable z : array_one(1 to 10);
+    type array_two is array (positive range <>) of bit;
+    variable a : array_two( 1 to 10);
+    variable b : array_two(1 to 5);
+    variable c : array_two(1 to 10);
+  BEGIN
+    z := (x xor  y);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n04i01936 - Operands should be arrays of the same length."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01936arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1937.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1937.vhd
new file mode 100644
index 0000000..867c5ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1937.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1937.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01937ent IS
+END c07s02b01x00p01n04i01937ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01937arch OF c07s02b01x00p01n04i01937ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (positive range <>) of boolean;
+    variable x : array_one( 1 to 10);
+    variable y : array_one(1 to 5);
+    variable z : array_one(1 to 10);
+    type array_two is array (positive range <>) of bit;
+    variable a : array_two( 1 to 10);
+    variable b : array_two(1 to 5);
+    variable c : array_two(1 to 10);
+  BEGIN
+    c := (a and  b);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n04i01937 - Operands should be arrays of the same length."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01937arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1938.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1938.vhd
new file mode 100644
index 0000000..2caa0c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1938.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1938.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01938ent IS
+END c07s02b01x00p01n04i01938ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01938arch OF c07s02b01x00p01n04i01938ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (positive range <>) of boolean;
+    variable x : array_one( 1 to 10);
+    variable y : array_one(1 to 5);
+    variable z : array_one(1 to 10);
+    type array_two is array (positive range <>) of bit;
+    variable a : array_two( 1 to 10);
+    variable b : array_two(1 to 5);
+    variable c : array_two(1 to 10);
+  BEGIN
+    c := (a or  b);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n04i01938 - Operands should be arrays of the same length."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01938arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1939.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1939.vhd
new file mode 100644
index 0000000..99d9da0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1939.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1939.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01939ent IS
+END c07s02b01x00p01n04i01939ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01939arch OF c07s02b01x00p01n04i01939ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (positive range <>) of boolean;
+    variable x : array_one( 1 to 10);
+    variable y : array_one(1 to 5);
+    variable z : array_one(1 to 10);
+    type array_two is array (positive range <>) of bit;
+    variable a : array_two( 1 to 10);
+    variable b : array_two(1 to 5);
+    variable c : array_two(1 to 10);
+  BEGIN
+    c := (a nand  b);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n04i01939 - Operands should be arrays of the same length."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01939arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1940.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1940.vhd
new file mode 100644
index 0000000..07af1af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1940.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1940.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01940ent IS
+END c07s02b01x00p01n04i01940ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01940arch OF c07s02b01x00p01n04i01940ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (positive range <>) of boolean;
+    variable x : array_one( 1 to 10);
+    variable y : array_one(1 to 5);
+    variable z : array_one(1 to 10);
+    type array_two is array (positive range <>) of bit;
+    variable a : array_two( 1 to 10);
+    variable b : array_two(1 to 5);
+    variable c : array_two(1 to 10);
+  BEGIN
+    c := (a nor  b);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n04i01940 - Operands should be arrays of the same length."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01940arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1941.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1941.vhd
new file mode 100644
index 0000000..29148c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1941.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1941.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n04i01941ent IS
+END c07s02b01x00p01n04i01941ent;
+
+ARCHITECTURE c07s02b01x00p01n04i01941arch OF c07s02b01x00p01n04i01941ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (positive range <>) of boolean;
+    variable x : array_one( 1 to 10);
+    variable y : array_one(1 to 5);
+    variable z : array_one(1 to 10);
+    type array_two is array (positive range <>) of bit;
+    variable a : array_two( 1 to 10);
+    variable b : array_two(1 to 5);
+    variable c : array_two(1 to 10);
+  BEGIN
+    c := (a xor  b);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b01x00p01n04i01941 - Operands should be arrays of the same length."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n04i01941arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc195.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc195.vhd
new file mode 100644
index 0000000..b79a53b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc195.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc195.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s00b00x00p11n01i00195ent IS
+END c03s00b00x00p11n01i00195ent;
+
+ARCHITECTURE c03s00b00x00p11n01i00195arch OF c03s00b00x00p11n01i00195ent IS
+  type       T1 is array (0 to 31) of BIT;
+  subtype    T2 is integer range 2 to 20;
+  signal    S1 : T2 ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= 25 after 10 ns; 
+    wait for 20 ns;
+    assert NOT(S1 = 25)
+      report "***PASSED TEST: c03s00b00x00p11n01i00195"
+      severity NOTE;
+    assert ( S1 = 25 )
+      report "***FAILED TEST: c03s00b00x00p11n01i00195 - Value doesn't belong to the range of the subtype of the object." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s00b00x00p11n01i00195arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc196.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc196.vhd
new file mode 100644
index 0000000..f020890
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc196.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc196.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p03n01i00196ent IS
+END c03s01b00x00p03n01i00196ent;
+
+ARCHITECTURE c03s01b00x00p03n01i00196arch OF c03s01b00x00p03n01i00196ent IS
+  type er1 is 0 to 4;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b00x00p03n01i00196 - The reserved word 'range' is missing in the range constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p03n01i00196arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc197.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc197.vhd
new file mode 100644
index 0000000..c84d069
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc197.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc197.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p04n01i00197ent IS
+END c03s01b00x00p04n01i00197ent;
+
+ARCHITECTURE c03s01b00x00p04n01i00197arch OF c03s01b00x00p04n01i00197ent IS
+  type t1 is range 0 to 300;
+  type t2 is range -100 to 0;
+  type t3 is range t1 to t2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b00x00p04n01i00197 - Illegal assignment in range constraint for type declaration of 't3'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p04n01i00197arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1977.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1977.vhd
new file mode 100644
index 0000000..6a4f70f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1977.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1977.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p01n02i01977ent IS
+END c07s02b02x00p01n02i01977ent;
+
+ARCHITECTURE c07s02b02x00p01n02i01977arch OF c07s02b02x00p01n02i01977ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    array_type is array (1 to 10) of integer;
+    constant    x : integer    := 3;
+    variable    y : array_type    := (0,9,8,7,6,5,4,3,2,1);
+  BEGIN
+    if (x = y) then  -- Failure_here
+      --operands should be of the same type.
+      NULL;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b02x00p01n02i01977 - Operands of a relational operator should be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p01n02i01977arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1979.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1979.vhd
new file mode 100644
index 0000000..2cc65b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1979.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1979.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p01n02i01979ent IS
+END c07s02b02x00p01n02i01979ent;
+
+ARCHITECTURE c07s02b02x00p01n02i01979arch OF c07s02b02x00p01n02i01979ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable NUM1 : BIT_VECTOR(0 to 1)    := B"01";
+    variable NUM2 : STRING(1 to 2)       := "01";
+  BEGIN
+    if (NUM1 = NUM2) then -- Failure_here
+      NULL;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b02x00p01n02i01979 - Operands of a relational operator should be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p01n02i01979arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1980.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1980.vhd
new file mode 100644
index 0000000..ea7b90b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1980.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1980.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p01n02i01980ent IS
+END c07s02b02x00p01n02i01980ent;
+
+ARCHITECTURE c07s02b02x00p01n02i01980arch OF c07s02b02x00p01n02i01980ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Define a subtype of a subtype.
+    subtype ZERO is NATURAL range 0 to 0;
+
+    -- Define a subtype of a different type.
+    type A is range 0 to 10;
+    subtype ASUB is A;
+    
+    -- Define variables of these subtypes.
+    variable ZEROV     : ZERO := 0;
+    variable AV        : ASUB := 0;
+  BEGIN
+    -- Failure_here : Should not be legal to compare these two types.
+    if (ZEROV = AV) then
+      NULL;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b02x00p01n02i01980 - Operands of a relational operator should be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p01n02i01980arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1989.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1989.vhd
new file mode 100644
index 0000000..f8afac9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1989.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1989.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01989ent IS
+END c07s02b02x00p07n01i01989ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01989arch OF c07s02b02x00p07n01i01989ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ft is file of integer;
+    file f1 : ft is "01.vhdl";
+    file f2 : ft is "02.vhdl";
+  BEGIN
+    if (f1=f2) then    -- Failure_here
+      -- equality and inequality operators are
+      NULL;        -- not defined for file types.
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b02x00p07n01i01989 - Equality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01989arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc199.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc199.vhd
new file mode 100644
index 0000000..c534e9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc199.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc199.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p04n01i00199ent IS
+END c03s01b00x00p04n01i00199ent;
+
+ARCHITECTURE c03s01b00x00p04n01i00199arch OF c03s01b00x00p04n01i00199ent IS
+  type t1 is range (1 = 1) to (1 = 1);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b00x00p04n01i00199 -The bounds in the range constraint are not legal."  
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p04n01i00199arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1990.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1990.vhd
new file mode 100644
index 0000000..96ae3a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1990.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1990.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p07n01i01990ent IS
+END c07s02b02x00p07n01i01990ent;
+
+ARCHITECTURE c07s02b02x00p07n01i01990arch OF c07s02b02x00p07n01i01990ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ft is file of integer;
+    file f1 : ft is "01.vhdl";
+    file f2 : ft is "02.vhdl";
+  BEGIN
+    if (f1/=f2) then    -- Failure_here
+      -- equality and inequality operators are
+      NULL;        -- not defined for file types.
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b02x00p07n01i01990 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i01990arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2.vhd
new file mode 100644
index 0000000..d3c32dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s01b00x00p03n01i00002ent IS
+END c04s01b00x00p03n01i00002ent;
+
+ARCHITECTURE c04s01b00x00p03n01i00002arch OF c04s01b00x00p03n01i00002ent IS
+  type t1  range 0.012345 to 300.012345;  -- Error: missing 'is'
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s01b00x00p03n01i00002 - The reserved word 'is' is missing in the type declaration." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s01b00x00p03n01i00002arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc20.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc20.vhd
new file mode 100644
index 0000000..95c0042
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc20.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc20.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p09n03i00020ent IS
+END c04s02b00x00p09n03i00020ent;
+
+ARCHITECTURE c04s02b00x00p09n03i00020arch OF c04s02b00x00p09n03i00020ent IS
+  type    A2 is range 50.0 to 100.0;
+  subtype B2 is A2 range 1.0 to 60.0;         -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s02b00x00p09n03i00020 - Range constraints for the subtype declarations contradict the range of the subtype indication.(real)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s02b00x00p09n03i00020arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc200.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc200.vhd
new file mode 100644
index 0000000..5a5ef81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc200.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc200.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p04n01i00200ent IS
+END c03s01b00x00p04n01i00200ent;
+
+ARCHITECTURE c03s01b00x00p04n01i00200arch OF c03s01b00x00p04n01i00200ent IS
+  type twos_complement_integer is range -32768 to 32767;
+  type J is
+    range twos_complement_integer  -- Failure_here
+    units
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b00x00p04n01i00200 -The bounds in the range constraint are not legal."  
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p04n01i00200arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2002.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2002.vhd
new file mode 100644
index 0000000..0d88df9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2002.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2002.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:40:54 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:27:56 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:35:51 1996  --
+--                 ****************************               --
+
+
+use std.textio.all;
+ENTITY c07s02b02x00p07n01i02002ent IS
+END c07s02b02x00p07n01i02002ent;
+
+ARCHITECTURE c07s02b02x00p07n01i02002arch OF c07s02b02x00p07n01i02002ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file f1 : text open write_mode is "aout";
+    file f2 : text open write_mode is "aout";
+  BEGIN
+    if f1 = f2 then
+      null;
+    end if;
+    assert FALSE
+      report "***FAILED TEST: c07s02b02x00p07n01i02002 - Equality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i02002arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2003.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2003.vhd
new file mode 100644
index 0000000..474aa46
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2003.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2003.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:40:54 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:27:56 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:35:51 1996  --
+--                 ****************************               --
+
+
+use std.textio.all;
+ENTITY c07s02b02x00p07n01i02003ent IS
+END c07s02b02x00p07n01i02003ent;
+
+ARCHITECTURE c07s02b02x00p07n01i02003arch OF c07s02b02x00p07n01i02003ent IS
+
+BEGIN
+  TESTING: PROCESS
+    file f1 : text open write_mode is "aout";
+    file f2 : text open write_mode is "aout";
+  BEGIN
+    if f1 /= f2 then
+      null;
+    end if;
+    assert FALSE
+      report "***FAILED TEST: c07s02b02x00p07n01i02003 - Inequality operators are not defined for file types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p07n01i02003arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2009.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2009.vhd
new file mode 100644
index 0000000..8c88c12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2009.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2009.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b02x00p10n01i02009ent IS
+END c07s02b02x00p10n01i02009ent;
+
+ARCHITECTURE c07s02b02x00p10n01i02009arch OF c07s02b02x00p10n01i02009ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        i : integer;
+      end record;
+    variable j, k : rec_type;
+  BEGIN
+    j.i := 2;
+    k.i := 1;
+    if (k<j) then   -- Failure_here
+      NULL;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b02x00p10n01i02009 - Ordering operators are defined only for scalar type or any discrete array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b02x00p10n01i02009arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2018.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2018.vhd
new file mode 100644
index 0000000..0796e39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2018.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2018.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02018ent IS
+END c07s02b04x00p01n01i02018ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02018arch OF c07s02b04x00p01n01i02018ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable y : bit;
+  BEGIN
+    y := bit'('1') + 3;  -- Failure_here
+    -- + operator predefined only for numeric
+    -- types.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02018 - The adding operators are predefined only for numeric types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02018arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2019.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2019.vhd
new file mode 100644
index 0000000..f3f906d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2019.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2019.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02019ent IS
+END c07s02b04x00p01n01i02019ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02019arch OF c07s02b04x00p01n01i02019ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_type is array (1 to 10) of integer;
+    variable x : array_type := (1,2,3,4,5,6,7,8,9,10);
+    variable y : array_type := (1,2,3,4,5,6,7,8,9,0);
+    variable z : array_type;
+  BEGIN
+    z := (x + y); -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02019 - The adding operators are predefined only for numeric types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02019arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc202.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc202.vhd
new file mode 100644
index 0000000..baff337
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc202.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc202.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p04n01i00202ent IS
+END c03s01b00x00p04n01i00202ent;
+
+ARCHITECTURE c03s01b00x00p04n01i00202arch OF c03s01b00x00p04n01i00202ent IS
+  type a is range 6 to ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b00x00p04n01i00202 -The range must be either a range attribute name or two simple expressions combined with a direction operator." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p04n01i00202_arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2020.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2020.vhd
new file mode 100644
index 0000000..fa5694a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2020.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2020.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02020ent IS
+END c07s02b04x00p01n01i02020ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02020arch OF c07s02b04x00p01n01i02020ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_type is array (1 to 10) of integer;
+    variable x : array_type := (1,2,3,4,5,6,7,8,9,10);
+    variable y : array_type := (1,2,3,4,5,6,7,8,9,0);
+    variable z : array_type;
+  BEGIN
+    z := (x - y); -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02020 - The adding operators are predefined only for numeric types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02020arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2023.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2023.vhd
new file mode 100644
index 0000000..7de80ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2023.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2023.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02023ent IS
+END c07s02b04x00p01n01i02023ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02023arch OF c07s02b04x00p01n01i02023ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     SWITCH_LEVEL is ('0', '1', 'X');
+    variable SWITCHV : SWITCH_LEVEL := '0';
+  BEGIN
+    SWITCHV := SWITCHV + '1';
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02023 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02023arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2024.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2024.vhd
new file mode 100644
index 0000000..03dcdf2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2024.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2024.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02024ent IS
+END c07s02b04x00p01n01i02024ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02024arch OF c07s02b04x00p01n01i02024ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     SWITCH_LEVEL is ('0', '1', 'X');
+    variable SWITCHV : SWITCH_LEVEL := '0';
+    subtype  LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    variable LOGICV  : LOGIC_SWITCH := '0';
+  BEGIN
+    LOGICV := LOGICV + SWITCHV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02024 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02024arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2025.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2025.vhd
new file mode 100644
index 0000000..3959e68
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2025.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2025.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02025ent IS
+END c07s02b04x00p01n01i02025ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02025arch OF c07s02b04x00p01n01i02025ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     SWITCH_LEVEL is ('0', '1', 'X');
+    subtype  LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    variable LOGICV  : LOGIC_SWITCH := '0';
+  BEGIN
+    LOGICV := LOGICV + '0';
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02025 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02025arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2026.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2026.vhd
new file mode 100644
index 0000000..bcc4580
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2026.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2026.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02026ent IS
+END c07s02b04x00p01n01i02026ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02026arch OF c07s02b04x00p01n01i02026ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     SWITCH_LEVEL is ('0', '1', 'X');
+    variable SWITCHV : SWITCH_LEVEL := '0';
+  BEGIN
+    SWITCHV := SWITCHV - '1';
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02026 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02026arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2027.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2027.vhd
new file mode 100644
index 0000000..4baa189
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2027.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2027.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02027ent IS
+END c07s02b04x00p01n01i02027ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02027arch OF c07s02b04x00p01n01i02027ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     SWITCH_LEVEL is ('0', '1', 'X');
+    variable SWITCHV : SWITCH_LEVEL := '0';
+    subtype  LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    variable LOGICV  : LOGIC_SWITCH := '0';
+  BEGIN
+    LOGICV := LOGICV - SWITCHV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02027 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02027arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2028.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2028.vhd
new file mode 100644
index 0000000..b84088d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2028.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2028.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02028ent IS
+END c07s02b04x00p01n01i02028ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02028arch OF c07s02b04x00p01n01i02028ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     SWITCH_LEVEL is ('0', '1', 'X');
+    subtype  LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    variable LOGICV  : LOGIC_SWITCH := '0';
+  BEGIN
+    LOGICV := LOGICV - '0';
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02028 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02028arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2029.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2029.vhd
new file mode 100644
index 0000000..7efc754
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2029.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2029.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02029ent IS
+END c07s02b04x00p01n01i02029ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02029arch OF c07s02b04x00p01n01i02029ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable CHARV   : CHARACTER    := '0';
+  BEGIN
+    CHARV := CHARV + NULL;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02029 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02029arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2030.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2030.vhd
new file mode 100644
index 0000000..7d7172d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2030.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2030.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02030ent IS
+END c07s02b04x00p01n01i02030ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02030arch OF c07s02b04x00p01n01i02030ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable CHARV   : CHARACTER    := '0';
+  BEGIN
+    CHARV := CHARV - NULL;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02030 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02030arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2031.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2031.vhd
new file mode 100644
index 0000000..dd9d347
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2031.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2031.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02031ent IS
+END c07s02b04x00p01n01i02031ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02031arch OF c07s02b04x00p01n01i02031ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable CHARV   : CHARACTER    := '0';
+  BEGIN
+    CHARV := '0' + '2';
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02031 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02031arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2032.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2032.vhd
new file mode 100644
index 0000000..1b772b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2032.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2032.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02032ent IS
+END c07s02b04x00p01n01i02032ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02032arch OF c07s02b04x00p01n01i02032ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable CHARV   : CHARACTER    := '0';
+  BEGIN
+    CHARV := '0' - '2';
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02032 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02032arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2033.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2033.vhd
new file mode 100644
index 0000000..519df12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2033.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2033.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02033ent IS
+END c07s02b04x00p01n01i02033ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02033arch OF c07s02b04x00p01n01i02033ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITV   : BIT    := '0';
+  BEGIN
+    BITV := BITV + '1';
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02033 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02033arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2034.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2034.vhd
new file mode 100644
index 0000000..7bbca85
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2034.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2034.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02034ent IS
+END c07s02b04x00p01n01i02034ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02034arch OF c07s02b04x00p01n01i02034ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITV   : BIT    := '1';
+  BEGIN
+    BITV := BITV - '0';
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02034 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02034arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2035.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2035.vhd
new file mode 100644
index 0000000..f8553dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2035.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2035.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02035ent IS
+END c07s02b04x00p01n01i02035ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02035arch OF c07s02b04x00p01n01i02035ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITV   : BIT    := '0';
+  BEGIN
+    BITV := BITV - BITV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02035 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02035arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2036.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2036.vhd
new file mode 100644
index 0000000..2c218d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2036.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2036.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02036ent IS
+END c07s02b04x00p01n01i02036ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02036arch OF c07s02b04x00p01n01i02036ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BOOLV   : BOOLEAN    := FALSE;
+  BEGIN
+    BOOLV := BOOLV + BOOLV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02036 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02036arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2037.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2037.vhd
new file mode 100644
index 0000000..7d8d014
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2037.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2037.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02037ent IS
+END c07s02b04x00p01n01i02037ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02037arch OF c07s02b04x00p01n01i02037ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BOOLV   : BOOLEAN    := FALSE;
+  BEGIN
+    BOOLV := BOOLV + TRUE;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02037 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02037arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2038.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2038.vhd
new file mode 100644
index 0000000..5a2eaed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2038.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2038.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02038ent IS
+END c07s02b04x00p01n01i02038ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02038arch OF c07s02b04x00p01n01i02038ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BOOLV   : BOOLEAN    := FALSE;
+  BEGIN
+    BOOLV := BOOLV - TRUE;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02038 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02038arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2039.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2039.vhd
new file mode 100644
index 0000000..9039859
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2039.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2039.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02039ent IS
+END c07s02b04x00p01n01i02039ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02039arch OF c07s02b04x00p01n01i02039ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BOOLV   : BOOLEAN    := FALSE;
+  BEGIN
+    BOOLV := BOOLV - FALSE;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02039 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02039arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2040.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2040.vhd
new file mode 100644
index 0000000..e0ecad1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2040.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2040.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02040ent IS
+END c07s02b04x00p01n01i02040ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02040arch OF c07s02b04x00p01n01i02040ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV  : SEVERITY_LEVEL := NOTE;
+  BEGIN
+    SEVERV := SEVERV + SEVERV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02040 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02040arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2041.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2041.vhd
new file mode 100644
index 0000000..da1cf7f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2041.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2041.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02041ent IS
+END c07s02b04x00p01n01i02041ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02041arch OF c07s02b04x00p01n01i02041ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV  : SEVERITY_LEVEL := NOTE;
+  BEGIN
+    SEVERV := SEVERV + WARNING;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02041 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02041arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2042.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2042.vhd
new file mode 100644
index 0000000..dfa7eec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2042.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2042.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02042ent IS
+END c07s02b04x00p01n01i02042ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02042arch OF c07s02b04x00p01n01i02042ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV  : SEVERITY_LEVEL := NOTE;
+  BEGIN
+    SEVERV := SEVERV - WARNING;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02042 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02042arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2043.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2043.vhd
new file mode 100644
index 0000000..61bb0c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2043.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2043.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02043ent IS
+END c07s02b04x00p01n01i02043ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02043arch OF c07s02b04x00p01n01i02043ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV  : SEVERITY_LEVEL := NOTE;
+  BEGIN
+    SEVERV := SEVERV - NOTE;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02043 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02043arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2044.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2044.vhd
new file mode 100644
index 0000000..55a703c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2044.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2044.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02044ent IS
+END c07s02b04x00p01n01i02044ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02044arch OF c07s02b04x00p01n01i02044ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type      MEMORY is array (INTEGER range <>) of BIT;
+    variable  MEMORYV : MEMORY( 0 to 31 );
+  BEGIN
+    MEMORYV : MEMORYV + MEMORYV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02044 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02044arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2045.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2045.vhd
new file mode 100644
index 0000000..3701ced
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2045.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2045.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02045ent IS
+END c07s02b04x00p01n01i02045ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02045arch OF c07s02b04x00p01n01i02045ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     WORD   is array(0 to 31) of BIT;
+    variable WORDV   : WORD;
+  BEGIN
+    WORDV := WORDV - WORDV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02045 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02045arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2046.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2046.vhd
new file mode 100644
index 0000000..bd81dfa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2046.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2046.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02046ent IS
+END c07s02b04x00p01n01i02046ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02046arch OF c07s02b04x00p01n01i02046ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BYTE   is array(7 downto 0) of BIT;
+    variable    BYTEV : BYTE;
+  BEGIN
+    BYTEV := BVTEV - BYTEV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02046 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02046arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2047.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2047.vhd
new file mode 100644
index 0000000..0bd856a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2047.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2047.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02047ent IS
+END c07s02b04x00p01n01i02047ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02047arch OF c07s02b04x00p01n01i02047ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable STRINGV : STRING( 1 to 8 );
+  BEGIN
+    STRINGV := STRINGV + "hello, world";
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02047 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02047arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2048.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2048.vhd
new file mode 100644
index 0000000..aaf76b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2048.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2048.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02048ent IS
+END c07s02b04x00p01n01i02048ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02048arch OF c07s02b04x00p01n01i02048ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable STRINGV : STRING( 1 to 8 );
+  BEGIN
+    STRINGV := "goodbye" + "hello, world";
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02048 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02048arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2049.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2049.vhd
new file mode 100644
index 0000000..6162180
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2049.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2049.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02049ent IS
+END c07s02b04x00p01n01i02049ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02049arch OF c07s02b04x00p01n01i02049ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable STRINGV : STRING( 1 to 8 );
+  BEGIN
+    STRINGV := "goodbye" - "hello, world";
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02049 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02049arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2050.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2050.vhd
new file mode 100644
index 0000000..0722971
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2050.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2050.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02050ent IS
+END c07s02b04x00p01n01i02050ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02050arch OF c07s02b04x00p01n01i02050ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable STRINGV : STRING( 1 to 8 );
+  BEGIN
+    STRINGV := STRINGV - "hello, world";
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02050 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02050arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2051.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2051.vhd
new file mode 100644
index 0000000..9fd0139
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2051.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2051.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02051ent IS
+END c07s02b04x00p01n01i02051ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02051arch OF c07s02b04x00p01n01i02051ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITSTRV : BIT_VECTOR( 0 to 7 ); 
+  BEGIN
+    BITSTRV := BITSTRV + "01010101"; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02051 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02051arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2052.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2052.vhd
new file mode 100644
index 0000000..c105fb1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2052.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2052.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02052ent IS
+END c07s02b04x00p01n01i02052ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02052arch OF c07s02b04x00p01n01i02052ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITSTRV : BIT_VECTOR( 0 to 7 ); 
+  BEGIN
+    BITSTRV := "10101010" + "01010101"; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02052 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02052arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2053.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2053.vhd
new file mode 100644
index 0000000..a48b639
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2053.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2053.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02053ent IS
+END c07s02b04x00p01n01i02053ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02053arch OF c07s02b04x00p01n01i02053ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    variable RECV    : DATE;
+  BEGIN
+    RECV := RECV + (DAY=>14, MONTH=>2, YEAR=>1988);
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02053 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02053arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2054.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2054.vhd
new file mode 100644
index 0000000..d1cde7b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2054.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2054.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02054ent IS
+END c07s02b04x00p01n01i02054ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02054arch OF c07s02b04x00p01n01i02054ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    variable RECV    : DATE;
+  BEGIN
+    RECV := RECV - (DAY=>14, MONTH=>2, YEAR=>1988);
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02054 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02054arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2055.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2055.vhd
new file mode 100644
index 0000000..29c328c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2055.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2055.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02055ent IS
+END c07s02b04x00p01n01i02055ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02055arch OF c07s02b04x00p01n01i02055ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEMORY   is array(INTEGER range <>) of BIT;
+    type ADDRESS  is access MEMORY;
+    variable ADDRESSV: ADDRESS;
+  BEGIN
+    ADDRESSV := ADDRESSV + NULL;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02055 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02055arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2056.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2056.vhd
new file mode 100644
index 0000000..25ca925
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2056.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2056.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02056ent IS
+END c07s02b04x00p01n01i02056ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02056arch OF c07s02b04x00p01n01i02056ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEMORY   is array(INTEGER range <>) of BIT;
+    type ADDRESS  is access MEMORY;
+    variable ADDRESSV: ADDRESS;
+  BEGIN
+    ADDRESSV := ADDRESSV - NULL;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02056 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02056arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2057.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2057.vhd
new file mode 100644
index 0000000..4655e24
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2057.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2057.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02057ent IS
+END c07s02b04x00p01n01i02057ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02057arch OF c07s02b04x00p01n01i02057ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type   FT   is file of BIT;
+    file   FILEV    : FT  is  "input_file";
+  BEGIN
+    FILEV := FILEV + FILEV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02057 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02057arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2058.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2058.vhd
new file mode 100644
index 0000000..a8a17fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2058.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2058.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n01i02058ent IS
+END c07s02b04x00p01n01i02058ent;
+
+ARCHITECTURE c07s02b04x00p01n01i02058arch OF c07s02b04x00p01n01i02058ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type   FT   is file of BIT;
+    file   FILEV    : FT  is  "input_file";
+  BEGIN
+    FILEV := FILEV - FILEV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n01i02058 - The adding operators + and - are predefined for any numeric type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n01i02058arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2059.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2059.vhd
new file mode 100644
index 0000000..c4cdff6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2059.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2059.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02059ent IS
+END c07s02b04x00p01n02i02059ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02059arch OF c07s02b04x00p01n02i02059ent IS
+  signal S1 : BOOLEAN := TRUE;
+  signal S2 : BOOLEAN := FALSE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    case (S1&S2) is      -- Failure_here
+      when others => null;
+    end case;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02059 - Concatenation operator cannot be used with this type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02059arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2060.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2060.vhd
new file mode 100644
index 0000000..ed28598
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2060.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2060.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02060ent IS
+END c07s02b04x00p01n02i02060ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02060arch OF c07s02b04x00p01n02i02060ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable x, y: integer := 1;
+  BEGIN
+    y := x + 2 - bit'('1') + 3;  -- Failure_here
+                                     -- operands must be of the same type.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02060 - Operands must be of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02060arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2064.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2064.vhd
new file mode 100644
index 0000000..00b665d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2064.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2064.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02064ent IS
+END c07s02b04x00p01n02i02064ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02064arch OF c07s02b04x00p01n02i02064ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+--                             m        = 100 cm;    -- meter 
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+--                             ft       = 12 inch;   -- foot
+--                             yd       = 3 ft;      -- yard
+      end units;
+    
+    -- Local declarations.
+    variable INTV    : INTEGER      := 0;
+    variable DISTV   : DISTANCE     := 1 A;
+  BEGIN
+    INTV := INTV + DISTV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02064 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02064arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2065.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2065.vhd
new file mode 100644
index 0000000..bcc402e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2065.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2065.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02065ent IS
+END c07s02b04x00p01n02i02065ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02065arch OF c07s02b04x00p01n02i02065ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+--                             m        = 100 cm;    -- meter 
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+--                             ft       = 12 inch;   -- foot
+--                             yd       = 3 ft;      -- yard
+      end units;
+    
+    -- Local declarations.
+    variable INTV    : INTEGER      := 0;
+    variable DISTV   : DISTANCE     := 1 A;
+  BEGIN
+    INTV := INTV + DISTV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02065 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02065arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2066.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2066.vhd
new file mode 100644
index 0000000..4380169
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2066.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2066.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02066ent IS
+END c07s02b04x00p01n02i02066ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02066arch OF c07s02b04x00p01n02i02066ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable INTV    : INTEGER      := 0;
+    variable REALV   : REAL         := 0.0;
+  BEGIN
+    INTV := INTV + REALV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02066 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02066arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2067.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2067.vhd
new file mode 100644
index 0000000..bcbd269
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2067.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2067.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02067ent IS
+END c07s02b04x00p01n02i02067ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02067arch OF c07s02b04x00p01n02i02067ent IS
+  subtype POSITIVE_R is real range 0.0 to real'high;
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable INTV    : INTEGER      := 0;
+    variable POSRV   : POSITIVE_R   := 0.0;
+  BEGIN
+    INTV := INTV + POSRV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02067 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02067arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2068.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2068.vhd
new file mode 100644
index 0000000..e95a294
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2068.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2068.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02068ent IS
+END c07s02b04x00p01n02i02068ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02068arch OF c07s02b04x00p01n02i02068ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different type declarations.
+    -- integer types.
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+--                             m        = 100 cm;    -- meter 
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+--                             ft       = 12 inch;   -- foot
+--                             yd       = 3 ft;      -- yard
+      end units;
+    
+    -- Local declarations.
+    variable POSV    : POSITIVE     := 0;
+    variable DISTV   : DISTANCE     := 1 A;
+  BEGIN
+    POSV := POSV + DISTV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02068 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02068arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2069.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2069.vhd
new file mode 100644
index 0000000..f95f43c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2069.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2069.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02069ent IS
+END c07s02b04x00p01n02i02069ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02069arch OF c07s02b04x00p01n02i02069ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different type declarations.
+    -- integer types.
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    
+    -- Local declarations.
+    variable POSV    : POSITIVE     := 0;
+    variable TIMEV   : TIME         := 1 ns;
+  BEGIN
+    POSV := POSV + TIMEV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02069 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02069arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc207.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc207.vhd
new file mode 100644
index 0000000..1647ae4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc207.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc207.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p09n01i00207ent IS
+END c03s01b00x00p09n01i00207ent;
+
+ARCHITECTURE c03s01b00x00p09n01i00207arch OF c03s01b00x00p09n01i00207ent IS
+  type week is (Mon, Tue, Wed, Thur, Fri, Sat, Sun);
+  subtype weekend is integer range Sat to Sun;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b00x00p09n01i00207 - Constraints for the subtype declaration do not match the base type of integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p09n01i00207arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2070.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2070.vhd
new file mode 100644
index 0000000..13775f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2070.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2070.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02070ent IS
+END c07s02b04x00p01n02i02070ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02070arch OF c07s02b04x00p01n02i02070ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different type declarations.
+    -- integer types.
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    
+    -- Local declarations.
+    variable POSV    : POSITIVE     := 0;
+    variable REALV   : REAL         := 0.0;
+  BEGIN
+    POSV := POSV + REALV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02070 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02070arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2071.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2071.vhd
new file mode 100644
index 0000000..0403016
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2071.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2071.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02071ent IS
+END c07s02b04x00p01n02i02071ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02071arch OF c07s02b04x00p01n02i02071ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different type declarations.
+    -- integer types.
+    type POSITIVE        is range 0 to INTEGER'HIGH;
+    
+    -- floating point types.
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    
+    -- Local declarations.
+    variable POSV    : POSITIVE     := 0;
+    variable POSRV   : POSITIVE_R   := 0.0;
+  BEGIN
+    POSV := POSV + POSRV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02071 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02071arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2072.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2072.vhd
new file mode 100644
index 0000000..f6827f5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2072.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2072.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02072ent IS
+END c07s02b04x00p01n02i02072ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02072arch OF c07s02b04x00p01n02i02072ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+--                             m        = 100 cm;    -- meter 
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+--                             ft       = 12 inch;   -- foot
+--                             yd       = 3 ft;      -- yard
+      end units;
+    
+    -- floating point types.
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    
+    -- Local declarations.
+    variable DISTV   : DISTANCE     := 1 A;
+    variable TIMEV   : TIME         := 1 ns;
+  BEGIN
+    DISTV := DISTV + TIMEV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02072 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02072arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2073.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2073.vhd
new file mode 100644
index 0000000..e65db1f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2073.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2073.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02073ent IS
+END c07s02b04x00p01n02i02073ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02073arch OF c07s02b04x00p01n02i02073ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+--                             m        = 100 cm;    -- meter 
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+--                             ft       = 12 inch;   -- foot
+--                             yd       = 3 ft;      -- yard
+      end units;
+    
+    -- floating point types.
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    
+    -- Local declarations.
+    variable DISTV   : DISTANCE     := 1 A;
+    variable REALV   : REAL         := 0.0;
+  BEGIN
+    DISTV := DISTV + REALV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02073 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02073arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2074.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2074.vhd
new file mode 100644
index 0000000..6f43496
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2074.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2074.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02074ent IS
+END c07s02b04x00p01n02i02074ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02074arch OF c07s02b04x00p01n02i02074ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+--                             m        = 100 cm;    -- meter 
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+--                             ft       = 12 inch;   -- foot
+--                             yd       = 3 ft;      -- yard
+      end units;
+    
+    -- floating point types.
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    
+    -- Local declarations.
+    variable DISTV   : DISTANCE     := 1 A;
+    variable POSRV   : POSITIVE_R   := 0.0;
+  BEGIN
+    DISTV := DISTV + POSRV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02074 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02074arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2075.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2075.vhd
new file mode 100644
index 0000000..71c7449
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2075.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2075.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02075ent IS
+END c07s02b04x00p01n02i02075ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02075arch OF c07s02b04x00p01n02i02075ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable TIMEV   : TIME         := 1 ns;
+    variable REALV   : REAL         := 0.0;
+  BEGIN
+    TIMEV := TIMEV + REALV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02075 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02075arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2076.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2076.vhd
new file mode 100644
index 0000000..eb182c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2076.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2076.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b04x00p01n02i02076ent IS
+END c07s02b04x00p01n02i02076ent;
+
+ARCHITECTURE c07s02b04x00p01n02i02076arch OF c07s02b04x00p01n02i02076ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- floating point types.
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    
+    -- Local declarations.
+    variable TIMEV   : TIME         := 1 ns;
+    variable POSRV   : POSITIVE_R   := 0.0;
+  BEGIN
+    TIMEV := TIMEV + POSRV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b04x00p01n02i02076 - The operands of the operators + and - cannot be of different types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b04x00p01n02i02076arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc21.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc21.vhd
new file mode 100644
index 0000000..741bb0a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc21.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc21.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p09n03i00021ent IS
+END c04s02b00x00p09n03i00021ent;
+
+ARCHITECTURE c04s02b00x00p09n03i00021arch OF c04s02b00x00p09n03i00021ent IS
+  type    A3 is ('a', 'b', 'c', 'd', 'e');
+  subtype B3 is A3 range 'b' to 'd';
+  subtype C3 is B3 range 'a' to 'e';          -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST:c04s02b00x00p09n03i00021 - Range constraints for the subtype declarations contradict the range of the subtype indication.(character)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p09n03i00021arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc210.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc210.vhd
new file mode 100644
index 0000000..762c8d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc210.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc210.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b00x00p09n01i00210ent IS
+END c03s01b00x00p09n01i00210ent;
+
+ARCHITECTURE c03s01b00x00p09n01i00210arch OF c03s01b00x00p09n01i00210ent IS
+  type hex is range 0 to 15;
+  subtype byte is hex range 0.0 to 7;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b00x00p09n01i00210 - The type of expression is not the same as the base type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b00x00p09n01i00210arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc212.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc212.vhd
new file mode 100644
index 0000000..7d55f0e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc212.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc212.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p02n01i00212ent IS
+END c03s01b01x00p02n01i00212ent;
+
+ARCHITECTURE c03s01b01x00p02n01i00212arch OF c03s01b01x00p02n01i00212ent IS
+  type ENUM1 is ( );
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b01x00p02n01i00212 - Literal list in enumeration type definition cannot be empty."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p02n01i00212arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc214.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc214.vhd
new file mode 100644
index 0000000..26f25f8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc214.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc214.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p03n01i00214ent IS
+END c03s01b01x00p03n01i00214ent;
+
+ARCHITECTURE c03s01b01x00p03n01i00214arch OF c03s01b01x00p03n01i00214ent IS
+  type ENUM2 is (3);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b01x00p03n01i00214 - Enumeration literal cannot be a string or integer literal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p03n01i00214arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc215.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc215.vhd
new file mode 100644
index 0000000..f4f2453
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc215.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc215.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p03n01i00215ent IS
+END c03s01b01x00p03n01i00215ent;
+
+ARCHITECTURE c03s01b01x00p03n01i00215arch OF c03s01b01x00p03n01i00215ent IS
+  type ENUM3 is (TUV, "XYZ");  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b01x00p03n01i00215 - Enumeration literal cannot be a string or integer lliteral." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p03n01i00215arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc216.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc216.vhd
new file mode 100644
index 0000000..ccd6046
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc216.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc216.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p04n01i00216ent IS
+END c03s01b01x00p04n01i00216ent;
+
+ARCHITECTURE c03s01b01x00p04n01i00216arch OF c03s01b01x00p04n01i00216ent IS
+  type t37 is ('a', 'b', 'a');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b01x00p04n01i00216 - Element listed twice in the declaration for the enumeration type t37."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p04n01i00216arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2170.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2170.vhd
new file mode 100644
index 0000000..b38105c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2170.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2170.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02170ent IS
+END c07s02b05x00p01n01i02170ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02170arch OF c07s02b05x00p01n01i02170ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant z1: boolean := + true;  -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s02b05x00p01n01i02170 - Signs + can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02170arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2171.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2171.vhd
new file mode 100644
index 0000000..789424d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2171.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2171.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b05x00p01n01i02171ent IS
+END c07s02b05x00p01n01i02171ent;
+
+ARCHITECTURE c07s02b05x00p01n01i02171arch OF c07s02b05x00p01n01i02171ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant z1: boolean := - true;  -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s02b05x00p01n01i02171 - Signs - can be used with only numeric types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b05x00p01n01i02171arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2188.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2188.vhd
new file mode 100644
index 0000000..8b19a13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2188.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2188.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02188ent IS
+END c07s02b00x00p01n02i02188ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02188arch OF c07s02b00x00p01n02i02188ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant a : integer := 3;
+    constant b : integer := 5;
+    variable c : integer;
+  BEGIN
+    c := a/-b;   -- Failure_here
+    -- signed operator cannot follow /.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02188 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02188arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2189.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2189.vhd
new file mode 100644
index 0000000..fbefde9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2189.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2189.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02189ent IS
+END c07s02b00x00p01n02i02189ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02189arch OF c07s02b00x00p01n02i02189ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_ARRAY is array (1 to 2) of CHARACTER;
+    variable I : INTEGER;
+    variable R : REAL;
+    variable B : BOOLEAN;
+    variable A : A_ARRAY;
+  BEGIN
+    R := R + - R;  -- Failure_here
+    -- SYNTAX ERROR:  signed operator cannot follow adding operator.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02189 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02189arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2190.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2190.vhd
new file mode 100644
index 0000000..4866ad5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2190.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2190.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02190ent IS
+END c07s02b00x00p01n02i02190ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02190arch OF c07s02b00x00p01n02i02190ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_ARRAY is array (1 to 2) of CHARACTER;
+    variable I : INTEGER;
+    variable R : REAL;
+    variable B : BOOLEAN;
+    variable A : A_ARRAY;
+  BEGIN
+    R := R - - R;  -- Failure_here
+    -- SYNTAX ERROR:  signed operator cannot follow adding operator.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02190 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02190arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2191.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2191.vhd
new file mode 100644
index 0000000..6c67da6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2191.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2191.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02191ent IS
+END c07s02b00x00p01n02i02191ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02191arch OF c07s02b00x00p01n02i02191ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_ARRAY is array (1 to 2) of CHARACTER;
+    variable I : INTEGER;
+    variable R : REAL;
+    variable B : BOOLEAN;
+    variable A : A_ARRAY;
+  BEGIN
+    A(1 to 2) := A(1) & - A(2);  -- Failure_here
+    -- SYNTAX ERROR:  signed operator cannot follow adding operator.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02191 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02191arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2192.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2192.vhd
new file mode 100644
index 0000000..dca5722
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2192.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2192.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02192ent IS
+END c07s02b00x00p01n02i02192ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02192arch OF c07s02b00x00p01n02i02192ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_ARRAY is array (1 to 2) of CHARACTER;
+    variable I : INTEGER;
+    variable R : REAL;
+    variable B : BOOLEAN;
+    variable A : A_ARRAY;
+  BEGIN
+    R := R * + R;  -- Failure_here
+    -- SYNTAX ERROR:  signed operator cannot follow multiplying operator.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02192 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02192arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2193.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2193.vhd
new file mode 100644
index 0000000..dc23a48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2193.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2193.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02193ent IS
+END c07s02b00x00p01n02i02193ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02193arch OF c07s02b00x00p01n02i02193ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_ARRAY is array (1 to 2) of CHARACTER;
+    variable I : INTEGER;
+    variable R : REAL;
+    variable B : BOOLEAN;
+    variable A : A_ARRAY;
+  BEGIN
+    R := R * + R;  -- Failure_here
+    -- SYNTAX ERROR:  signed operator cannot follow multiplying operator.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02193 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02193arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2194.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2194.vhd
new file mode 100644
index 0000000..5eeb89d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2194.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2194.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02194ent IS
+END c07s02b00x00p01n02i02194ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02194arch OF c07s02b00x00p01n02i02194ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_ARRAY is array (1 to 2) of CHARACTER;
+    variable I : INTEGER;
+    variable R : REAL;
+    variable B : BOOLEAN;
+    variable A : A_ARRAY;
+  BEGIN
+    I := I mod + I;   -- Failure_here
+    -- SYNTAX ERROR:  signed operator cannot follow multiplying operator.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02194 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02194arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2195.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2195.vhd
new file mode 100644
index 0000000..2d2a6a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2195.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2195.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02195ent IS
+END c07s02b00x00p01n02i02195ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02195arch OF c07s02b00x00p01n02i02195ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_ARRAY is array (1 to 2) of CHARACTER;
+    variable I : INTEGER;
+    variable R : REAL;
+    variable B : BOOLEAN;
+    variable A : A_ARRAY;
+  BEGIN
+    R := I rem - I;  -- Failure_here
+    -- SYNTAX ERROR:  signed operator cannot follow multiplying operator.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02195 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02195arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2196.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2196.vhd
new file mode 100644
index 0000000..7e13bda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2196.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2196.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02196ent IS
+END c07s02b00x00p01n02i02196ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02196arch OF c07s02b00x00p01n02i02196ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_ARRAY is array (1 to 2) of CHARACTER;
+    variable I : INTEGER;
+    variable R : REAL;
+    variable B : BOOLEAN;
+    variable A : A_ARRAY;
+  BEGIN
+    R := R ** + I;  -- Failure_here
+    -- SYNTAX ERROR:  signed operator cannot follow misc. operator.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02196 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02196arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2197.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2197.vhd
new file mode 100644
index 0000000..4c1df4a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2197.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2197.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02197ent IS
+END c07s02b00x00p01n02i02197ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02197arch OF c07s02b00x00p01n02i02197ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_ARRAY is array (1 to 2) of CHARACTER;
+    variable I : INTEGER;
+    variable R : REAL;
+    variable B : BOOLEAN;
+    variable A : A_ARRAY;
+  BEGIN
+    R := abs - R;  -- Failure_here
+    -- SYNTAX ERROR:  signed operator cannot follow misc.  operator.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02197 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02197arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2198.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2198.vhd
new file mode 100644
index 0000000..ef763f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2198.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2198.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b00x00p01n02i02198ent IS
+END c07s02b00x00p01n02i02198ent;
+
+ARCHITECTURE c07s02b00x00p01n02i02198arch OF c07s02b00x00p01n02i02198ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_ARRAY is array (1 to 2) of CHARACTER;
+    variable I : INTEGER;
+    variable R : REAL;
+    variable B : BOOLEAN;
+    variable A : A_ARRAY;
+  BEGIN
+    B := not - B; -- Failure_here
+    -- SYNTAX ERROR:  signed operator cannot follow logical operator.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b00x00p01n02i02198 - Signed operand cannot follow a mutiplying operator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b00x00p01n02i02198arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc22.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc22.vhd
new file mode 100644
index 0000000..7e1ac95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc22.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc22.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p09n03i00022ent IS
+END c04s02b00x00p09n03i00022ent;
+
+ARCHITECTURE c04s02b00x00p09n03i00022arch OF c04s02b00x00p09n03i00022ent IS
+  subtype B4 is time range 10 ns to 100 ns;
+  subtype C4 is B4   range 1  ns to 150 ns;   -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s02b00x00p09n03i00022 - Range constraints for the subtype declarations contradict the range of the subtype indication.(physical)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p09n03i00022arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2201.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2201.vhd
new file mode 100644
index 0000000..8d52025
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2201.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2201.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02201ent IS
+END c07s02b06x00p01n01i02201ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02201arch OF c07s02b06x00p01n01i02201ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (1 to 10) of boolean;
+    type array_two is array (1 to 20) of boolean;
+    variable x : array_one;
+    variable y : array_two;
+    variable z : integer;
+  BEGIN
+    z := x * y;  -- Failure_here
+    -- multiplying operator cannot operate on array types.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02201 - Multiplying operators are predefined only for integer and floating point types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02201arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2202.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2202.vhd
new file mode 100644
index 0000000..18228f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2202.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2202.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02202ent IS
+END c07s02b06x00p01n01i02202ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02202arch OF c07s02b06x00p01n01i02202ent IS
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (1 to 10) of boolean;
+    type array_two is array (1 to 20) of boolean;
+    variable x : array_one;
+    variable y : array_two;
+    variable z : integer;
+  BEGIN
+    z := x / y;  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02202 - Multiplying operators are predefined only for integer and floating point types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02202arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2207.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2207.vhd
new file mode 100644
index 0000000..0937960
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2207.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2207.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02207ent IS
+END c07s02b06x00p01n01i02207ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02207arch OF c07s02b06x00p01n01i02207ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x : real := 15.5;
+    constant y : integer := 9;
+    variable z : integer;
+  BEGIN
+    z := x mod y;  -- Failure_here
+    -- mod is  not defined for real types.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02207 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02207arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2209.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2209.vhd
new file mode 100644
index 0000000..8e32c6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2209.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2209.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02209ent IS
+END c07s02b06x00p01n01i02209ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02209arch OF c07s02b06x00p01n01i02209ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    -- Local declarations.
+    variable SWITCHV : SWITCH_LEVEL := '0';
+    variable k    : integer;
+  BEGIN
+    k := SWITCHV mod '1';
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02209 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02209arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc221.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc221.vhd
new file mode 100644
index 0000000..9356128
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc221.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc221.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00221ent IS
+END c03s01b01x00p07n01i00221ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00221arch OF c03s01b01x00p07n01i00221ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    if ('0' = '0') then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c03s01b01x00p07n01i00221"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c03s01b01x00p07n01i00221 - The type of the overloaded enumeration literal is not determined form the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00221arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2210.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2210.vhd
new file mode 100644
index 0000000..7e6174b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2210.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2210.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02210ent IS
+END c07s02b06x00p01n01i02210ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02210arch OF c07s02b06x00p01n01i02210ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    
+    -- Local declarations.
+    variable SWITCHV : SWITCH_LEVEL := '0';
+    variable LOGICV  : LOGIC_SWITCH := '0';
+    variable k    : integer;
+  BEGIN
+    k := LOGICV mod SWITCHV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02210 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02210arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2211.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2211.vhd
new file mode 100644
index 0000000..5cec481
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2211.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2211.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02211ent IS
+END c07s02b06x00p01n01i02211ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02211arch OF c07s02b06x00p01n01i02211ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    -- Local declarations.
+    variable LOGICV  : LOGIC_SWITCH := '0';
+    variable k    : integer;
+  BEGIN
+    k := LOGICV mod '0'; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02211 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02211arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2212.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2212.vhd
new file mode 100644
index 0000000..55f4240
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2212.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2212.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02212ent IS
+END c07s02b06x00p01n01i02212ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02212arch OF c07s02b06x00p01n01i02212ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    -- Local declarations.
+    variable SWITCHV : SWITCH_LEVEL := '0';
+    variable k    : integer;
+  BEGIN
+    k := SWITCHV rem '1'; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02212 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02212arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2213.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2213.vhd
new file mode 100644
index 0000000..73a66bf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2213.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2213.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02213ent IS
+END c07s02b06x00p01n01i02213ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02213arch OF c07s02b06x00p01n01i02213ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    -- Local declarations.
+    variable SWITCHV : SWITCH_LEVEL := '0';
+    variable LOGICV  : LOGIC_SWITCH := '0';
+    variable k    : integer;
+  BEGIN
+    k := LOGICV rem SWITCHV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02213 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02213arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2214.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2214.vhd
new file mode 100644
index 0000000..19a2fbd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2214.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2214.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02214ent IS
+END c07s02b06x00p01n01i02214ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02214arch OF c07s02b06x00p01n01i02214ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    
+    -- Local declarations.
+    variable LOGICV  : LOGIC_SWITCH := '0';
+    variable k    : integer;
+  BEGIN
+    k := LOGICV rem '0'; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02214 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02214arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2215.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2215.vhd
new file mode 100644
index 0000000..8e1b905
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2215.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2215.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02215ent IS
+END c07s02b06x00p01n01i02215ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02215arch OF c07s02b06x00p01n01i02215ent IS
+BEGIN
+  TESTING: PROCESS
+    -- All different non-numeric type declarations.
+    -- Local declarations.
+    variable CHARV   : CHARACTER    := '0';
+    variable k    : integer;
+  BEGIN
+    k := NULL mod CHARV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02215 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02215arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2216.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2216.vhd
new file mode 100644
index 0000000..9bcaf9c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2216.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2216.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02216ent IS
+END c07s02b06x00p01n01i02216ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02216arch OF c07s02b06x00p01n01i02216ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k    : integer;
+  BEGIN
+    k := '0' mod '2'; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02216 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02216arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2217.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2217.vhd
new file mode 100644
index 0000000..959a02e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2217.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2217.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02217ent IS
+END c07s02b06x00p01n01i02217ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02217arch OF c07s02b06x00p01n01i02217ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable BITV    : BIT          := '0';
+    variable k    : integer;
+  BEGIN
+    k := BITV mod '1'; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02217 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02217arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2218.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2218.vhd
new file mode 100644
index 0000000..742f4b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2218.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2218.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02218ent IS
+END c07s02b06x00p01n01i02218ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02218arch OF c07s02b06x00p01n01i02218ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable CHARV   : CHARACTER    := '0';
+    variable k    : integer;
+  BEGIN
+    k := NULL rem CHARV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02218 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02218arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2219.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2219.vhd
new file mode 100644
index 0000000..094f90e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2219.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2219.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02219ent IS
+END c07s02b06x00p01n01i02219ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02219arch OF c07s02b06x00p01n01i02219ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k    : integer;
+  BEGIN
+    k := '0' rem '2'; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02219 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02219arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc222.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc222.vhd
new file mode 100644
index 0000000..caec72a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc222.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc222.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00222ent IS
+END c03s01b01x00p07n01i00222ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00222arch OF c03s01b01x00p07n01i00222ent IS
+  type ENUM1 is (FF, GG);
+  type ENUM2 is (GG, HH);
+  type ENUM3 is (FALSE);
+  type ENUM4 is ('A', 'Z');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if (GG = GG) then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c03s01b01x00p07n01i00222"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c03s01b01x00p07n01i00222 - Literal cannot be determined." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00222arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2220.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2220.vhd
new file mode 100644
index 0000000..8ac5ff9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2220.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2220.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02220ent IS
+END c07s02b06x00p01n01i02220ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02220arch OF c07s02b06x00p01n01i02220ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITV    : BIT          := '0';
+    variable k    : integer;
+  BEGIN
+    k := BITV mod BITV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02220 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02220arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2221.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2221.vhd
new file mode 100644
index 0000000..de6e38a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2221.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2221.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02221ent IS
+END c07s02b06x00p01n01i02221ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02221arch OF c07s02b06x00p01n01i02221ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITV    : BIT          := '0';
+    variable k    : integer;
+  BEGIN
+    k := BITV rem '0'; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02221 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02221arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2222.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2222.vhd
new file mode 100644
index 0000000..34d43e5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2222.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2222.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02222ent IS
+END c07s02b06x00p01n01i02222ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02222arch OF c07s02b06x00p01n01i02222ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITV    : BIT          := '0';
+    variable k    : integer;
+  BEGIN
+    k := BITV rem '1'; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02222 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02222arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2223.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2223.vhd
new file mode 100644
index 0000000..8c82e38
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2223.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2223.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02223ent IS
+END c07s02b06x00p01n01i02223ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02223arch OF c07s02b06x00p01n01i02223ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BOOLV   : BOOLEAN      := FALSE;
+    variable k    : integer;
+  BEGIN
+    k := BOOLV mod BOOLV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02223 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02223arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2224.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2224.vhd
new file mode 100644
index 0000000..8be545a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2224.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2224.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02224ent IS
+END c07s02b06x00p01n01i02224ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02224arch OF c07s02b06x00p01n01i02224ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BOOLV   : BOOLEAN      := FALSE;
+    variable k    : integer;
+  BEGIN
+    k := BOOLV mod TRUE; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02224 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02224arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2225.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2225.vhd
new file mode 100644
index 0000000..bfb425b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2225.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2225.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02225ent IS
+END c07s02b06x00p01n01i02225ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02225arch OF c07s02b06x00p01n01i02225ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BOOLV   : BOOLEAN      := FALSE;
+    variable k    : integer;
+  BEGIN
+    k := BOOLV rem FALSE; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02225 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02225arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2226.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2226.vhd
new file mode 100644
index 0000000..a9df28b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2226.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2226.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02226ent IS
+END c07s02b06x00p01n01i02226ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02226arch OF c07s02b06x00p01n01i02226ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BOOLV   : BOOLEAN      := FALSE;
+    variable k    : integer;
+  BEGIN
+    k := BOOLV rem TRUE; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02226 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02226arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2227.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2227.vhd
new file mode 100644
index 0000000..e5be24b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2227.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2227.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02227ent IS
+END c07s02b06x00p01n01i02227ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02227arch OF c07s02b06x00p01n01i02227ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV  : SEVERITY_LEVEL := NOTE;
+    variable k    : integer;
+  BEGIN
+    k := SEVERV mod SEVERV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02227 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02227arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2228.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2228.vhd
new file mode 100644
index 0000000..a26287b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2228.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2228.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02228ent IS
+END c07s02b06x00p01n01i02228ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02228arch OF c07s02b06x00p01n01i02228ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV  : SEVERITY_LEVEL := NOTE;
+    variable k    : integer;
+  BEGIN
+    k := SEVERV mod WARNING; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02228 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02228arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2229.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2229.vhd
new file mode 100644
index 0000000..5c2813c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2229.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2229.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02229ent IS
+END c07s02b06x00p01n01i02229ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02229arch OF c07s02b06x00p01n01i02229ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV  : SEVERITY_LEVEL := NOTE;
+    variable k    : integer;
+  BEGIN
+    k := SEVERV rem NOTE; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02229 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02229arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc223.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc223.vhd
new file mode 100644
index 0000000..a4d9091
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc223.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc223.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00223ent IS
+END c03s01b01x00p07n01i00223ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00223arch OF c03s01b01x00p07n01i00223ent IS
+  type ENUM1 is (FF, GG);
+  type ENUM2 is (GG, HH);
+  type ENUM3 is (FALSE);
+  type ENUM4 is ('A', 'Z');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if (FALSE = FALSE) then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c03s01b01x00p07n01i00223"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c03s01b01x00p07n01i00223 - Literal cannot be determined." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00223arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2230.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2230.vhd
new file mode 100644
index 0000000..4a9aa44
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2230.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2230.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02230ent IS
+END c07s02b06x00p01n01i02230ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02230arch OF c07s02b06x00p01n01i02230ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV  : SEVERITY_LEVEL := NOTE;
+    variable k    : integer;
+  BEGIN
+    k := SEVERV rem WARNING; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02230 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02230arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2231.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2231.vhd
new file mode 100644
index 0000000..30477cf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2231.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2231.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02231ent IS
+END c07s02b06x00p01n01i02231ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02231arch OF c07s02b06x00p01n01i02231ent IS
+BEGIN
+  TESTING: PROCESS
+    variable REALV   : REAL;
+    variable k    : integer;
+  BEGIN
+    k := REALV mod 3.0; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02231 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02231arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2232.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2232.vhd
new file mode 100644
index 0000000..9a23d61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2232.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2232.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02232ent IS
+END c07s02b06x00p01n01i02232ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02232arch OF c07s02b06x00p01n01i02232ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type POSITIVE_R    is range 0.0 to REAL'HIGH;
+    variable REALV   : REAL;
+    variable POSRV   : POSITIVE_R;
+    variable k    : integer;
+  BEGIN
+    k := POSRV mod REALV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02232 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02232arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2233.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2233.vhd
new file mode 100644
index 0000000..193407d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2233.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2233.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02233ent IS
+END c07s02b06x00p01n01i02233ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02233arch OF c07s02b06x00p01n01i02233ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+    variable DISTV   : DISTANCE;
+    variable k    : integer;
+  BEGIN
+    k := DISTV mod 1 A; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02233 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02233arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2234.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2234.vhd
new file mode 100644
index 0000000..2f6a23a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2234.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2234.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02234ent IS
+END c07s02b06x00p01n01i02234ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02234arch OF c07s02b06x00p01n01i02234ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+        
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+      end units;
+    
+    variable k    : integer;
+  BEGIN
+    k := 4 nm mod 1 A; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02234 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02234arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2235.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2235.vhd
new file mode 100644
index 0000000..5bdc0ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2235.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2235.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02235ent IS
+END c07s02b06x00p01n01i02235ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02235arch OF c07s02b06x00p01n01i02235ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable TIMEV   : TIME;
+    variable k    : integer;
+  BEGIN
+    k := TIMEV mod 1 ns; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02235 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02235arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2236.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2236.vhd
new file mode 100644
index 0000000..c30d3bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2236.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2236.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02236ent IS
+END c07s02b06x00p01n01i02236ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02236arch OF c07s02b06x00p01n01i02236ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k    : integer;
+  BEGIN
+    k := 4 sec mod 1 ns; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02236 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02236arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2237.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2237.vhd
new file mode 100644
index 0000000..8a5c158
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2237.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2237.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02237ent IS
+END c07s02b06x00p01n01i02237ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02237arch OF c07s02b06x00p01n01i02237ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- array types.
+    type MEMORY is array(INTEGER range <>) of BIT;
+
+    variable MEMORYV : MEMORY( 0 to 31 );
+    variable k    : integer;
+  BEGIN
+    k := MEMORYV mod MEMORYV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02237 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02237arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2238.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2238.vhd
new file mode 100644
index 0000000..d60f53d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2238.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2238.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02238ent IS
+END c07s02b06x00p01n01i02238ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02238arch OF c07s02b06x00p01n01i02238ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- array types.
+    type WORD   is array(0 to 31) of BIT;
+    
+    -- Local declarations.
+    variable WORDV   : WORD;
+    variable k    : integer;
+  BEGIN
+    k := WORDV rem WORDV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02238 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02238arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2239.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2239.vhd
new file mode 100644
index 0000000..30d274d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2239.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2239.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02239ent IS
+END c07s02b06x00p01n01i02239ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02239arch OF c07s02b06x00p01n01i02239ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BYTE   is array(7 downto 0) of BIT;
+    variable BYTEV   : BYTE;
+    variable k    : integer;
+  BEGIN
+    k := BYTEV rem BYTEV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02239 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02239arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc224.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc224.vhd
new file mode 100644
index 0000000..f8c958b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc224.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc224.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00224ent IS
+END c03s01b01x00p07n01i00224ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00224arch OF c03s01b01x00p07n01i00224ent IS
+  type ENUM1 is (FF, GG);
+  type ENUM2 is (GG, HH);
+  type ENUM3 is (FALSE);
+  type ENUM4 is ('A', 'Z');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if ('A' = 'Z') then
+      k := 5;
+    end if;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c03s01b01x00p07n01i00224"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c03s01b01x00p07n01i00224 - Literal cannot be determined." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00224arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2240.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2240.vhd
new file mode 100644
index 0000000..2857e18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2240.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2240.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02240ent IS
+END c07s02b06x00p01n01i02240ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02240arch OF c07s02b06x00p01n01i02240ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable STRINGV : STRING( 1 to 32 );
+    variable k    : integer;
+  BEGIN
+    k := STRINGV mod "hello, world"; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02240 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02240arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2241.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2241.vhd
new file mode 100644
index 0000000..32c7abd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2241.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2241.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02241ent IS
+END c07s02b06x00p01n01i02241ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02241arch OF c07s02b06x00p01n01i02241ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k    : integer;
+  BEGIN
+    k := "goodbye, world" mod "hello, world";
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02241 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02241arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2242.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2242.vhd
new file mode 100644
index 0000000..e7d1b6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2242.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2242.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02242ent IS
+END c07s02b06x00p01n01i02242ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02242arch OF c07s02b06x00p01n01i02242ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITSTRV : BIT_VECTOR( 0 to 31 );
+    variable k    : integer;
+  BEGIN
+    k := BITSTRV mod X"7777"; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02242 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02242arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2243.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2243.vhd
new file mode 100644
index 0000000..663cc20
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2243.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2243.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02243ent IS
+END c07s02b06x00p01n01i02243ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02243arch OF c07s02b06x00p01n01i02243ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k    : integer;
+  BEGIN
+    k := B"1010101010" mod X"FFFF"; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02243 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02243arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2244.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2244.vhd
new file mode 100644
index 0000000..11fc8d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2244.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2244.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02244ent IS
+END c07s02b06x00p01n01i02244ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02244arch OF c07s02b06x00p01n01i02244ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITSTRV : BIT_VECTOR( 0 to 31 );
+    variable k    : integer;
+  BEGIN
+    k := BITSTRV rem X"7777"; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02244 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02244arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2245.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2245.vhd
new file mode 100644
index 0000000..a7e4aff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2245.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2245.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02245ent IS
+END c07s02b06x00p01n01i02245ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02245arch OF c07s02b06x00p01n01i02245ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k    : integer;
+  BEGIN
+    k := B"1010101010" rem X"FFFF"; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02245 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02245arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2246.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2246.vhd
new file mode 100644
index 0000000..8e766cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2246.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2246.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02246ent IS
+END c07s02b06x00p01n01i02246ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02246arch OF c07s02b06x00p01n01i02246ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- record types.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    
+    variable RECV    : DATE;
+    variable k    : integer;
+  BEGIN
+    k := RECV mod ( DAY => 14, MONTH => 2, YEAR => 1988 ); 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02246 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02246arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2247.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2247.vhd
new file mode 100644
index 0000000..b4c472b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2247.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2247.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02247ent IS
+END c07s02b06x00p01n01i02247ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02247arch OF c07s02b06x00p01n01i02247ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- record types.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    
+    variable RECV    : DATE;
+    variable k    : integer;
+  BEGIN
+    k := RECV rem ( DAY => 14, MONTH => 2, YEAR => 1988 ); 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02247 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02247arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2248.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2248.vhd
new file mode 100644
index 0000000..53d9563
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2248.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2248.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02248ent IS
+END c07s02b06x00p01n01i02248ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02248arch OF c07s02b06x00p01n01i02248ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- array types.
+    type MEMORY is array(INTEGER range <>) of BIT;
+    -- access types.
+    type ADDRESS  is access MEMORY;
+    
+    variable ADDRESSV: ADDRESS;
+    variable k    : integer;
+  BEGIN
+    k := ADDRESSV mod NULL; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02248 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02248arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2249.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2249.vhd
new file mode 100644
index 0000000..15dc87a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2249.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2249.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02249ent IS
+END c07s02b06x00p01n01i02249ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02249arch OF c07s02b06x00p01n01i02249ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type WORD   is array(0 to 31) of BIT;
+
+    type WORDPTR  is access WORD;
+    
+    variable WORDPTRV,
+      WORDPTR2V: WORDPTR;
+    variable k    : integer;
+  BEGIN
+    k := WORDPTRV mod WORDPTR2V; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02249 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02249arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc225.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc225.vhd
new file mode 100644
index 0000000..e273f39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc225.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc225.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00225ent IS
+END c03s01b01x00p07n01i00225ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00225arch OF c03s01b01x00p07n01i00225ent IS
+  type ENUM1 is (FF, GG);
+  type ENUM2 is (GG, HH);
+  type ENUM3 is (FALSE);
+  type ENUM4 is ('A', 'Z');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for X in GG to GG loop
+      k := 5;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c03s01b01x00p07n01i00225"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c03s01b01x00p07n01i00225 - Literal cannot be determined." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00225arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2250.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2250.vhd
new file mode 100644
index 0000000..e636b51
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2250.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2250.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02250ent IS
+END c07s02b06x00p01n01i02250ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02250arch OF c07s02b06x00p01n01i02250ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- array types.
+    type MEMORY is array(INTEGER range <>) of BIT;
+    type ADDRESS  is access MEMORY;
+    
+    variable ADDRESSV: ADDRESS;
+    variable k    : integer;
+  BEGIN
+    k := ADDRESSV rem NULL; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02250 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02250arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2251.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2251.vhd
new file mode 100644
index 0000000..77de060
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2251.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2251.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02251ent IS
+END c07s02b06x00p01n01i02251ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02251arch OF c07s02b06x00p01n01i02251ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- array types.
+    type WORD   is array(0 to 31) of BIT;
+
+    -- access types.
+    type WORDPTR  is access WORD;
+    
+    variable WORDPTRV,
+      WORDPTR2V: WORDPTR;
+    variable k    : integer;
+  BEGIN
+    k := WORDPTRV rem WORDPTR2V; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02251 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02251arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2252.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2252.vhd
new file mode 100644
index 0000000..c14d91e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2252.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2252.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02252ent IS
+END c07s02b06x00p01n01i02252ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02252arch OF c07s02b06x00p01n01i02252ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- file types.
+    type FileType is file of BIT;
+    
+    -- Local declarations.
+    file     FILEV   : FileType is "input_file";
+    variable k    : integer;
+  BEGIN
+    k := FILEV mod FILEV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02252 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02252arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2253.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2253.vhd
new file mode 100644
index 0000000..2d8ac7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2253.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2253.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02253ent IS
+END c07s02b06x00p01n01i02253ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02253arch OF c07s02b06x00p01n01i02253ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- file types.
+    type FileType is file of BIT;
+    
+    -- Local declarations.
+    file     FILEV   : FileType is "input_file";
+    variable k    : integer;
+  BEGIN
+    k := FILEV rem FILEV; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02253 - Operators mod and rem are predefined for any integer type only." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02253arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2254.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2254.vhd
new file mode 100644
index 0000000..9c5b764
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2254.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2254.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02254ent IS
+END c07s02b06x00p01n01i02254ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02254arch OF c07s02b06x00p01n01i02254ent IS
+BEGIN
+  TESTING: PROCESS
+    variable I : INTEGER;
+  BEGIN
+    I := 1 / 0;             -- should yield divide-by-zero error
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02254 - Integer can not divided by zero."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02254arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2255.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2255.vhd
new file mode 100644
index 0000000..597ed53
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2255.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2255.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02255ent IS
+END c07s02b06x00p01n01i02255ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02255arch OF c07s02b06x00p01n01i02255ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable R : REAL;
+  BEGIN
+    R := 1.0 / 0.0;         -- should yield divide-by-zero error
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02255 - Floating point can not divided by zero."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02255arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2256.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2256.vhd
new file mode 100644
index 0000000..b50ca4b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2256.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2256.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p01n01i02256ent IS
+END c07s02b06x00p01n01i02256ent;
+
+ARCHITECTURE c07s02b06x00p01n01i02256arch OF c07s02b06x00p01n01i02256ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable I : INTEGER;
+  BEGIN
+    I := 1 mod 0;           -- should yield divide-by-zero error
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p01n01i02256 - Divide by zero is an error."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p01n01i02256arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc226.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc226.vhd
new file mode 100644
index 0000000..ffd0824
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc226.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc226.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00226ent IS
+END c03s01b01x00p07n01i00226ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00226arch OF c03s01b01x00p07n01i00226ent IS
+  type ENUM1 is (FF, GG);
+  type ENUM2 is (GG, HH);
+  type ENUM3 is (FALSE);
+  type ENUM4 is ('A', 'Z');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for X in '0' to '1' loop
+      k := 5;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c03s01b01x00p07n01i00226"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c03s01b01x00p07n01i00226 - Literal cannot be determined." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00226arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc227.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc227.vhd
new file mode 100644
index 0000000..ca04673
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc227.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc227.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b01x00p07n01i00227ent IS
+END c03s01b01x00p07n01i00227ent;
+
+ARCHITECTURE c03s01b01x00p07n01i00227arch OF c03s01b01x00p07n01i00227ent IS
+  type ENUM1 is (FF, GG);
+  type ENUM2 is (GG, HH);
+  type ENUM3 is (FALSE);
+  type ENUM4 is ('A', 'Z');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    for X in FALSE to FALSE loop
+      k := 5;
+    end loop;
+    assert NOT( k=5 )
+      report "***PASSED TEST: c03s01b01x00p07n01i00227"
+      severity NOTE;
+    assert ( k=5 )
+      report "***FAILED TEST: c03s01b01x00p07n01i00227 - Literal cannot be determined." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b01x00p07n01i00227arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2273.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2273.vhd
new file mode 100644
index 0000000..ad209e1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2273.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2273.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02273ent IS
+END c07s02b06x00p14n01i02273ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02273arch OF c07s02b06x00p14n01i02273ent IS
+BEGIN
+  TESTING: PROCESS
+    variable T : TIME := 1 sec;
+  BEGIN
+    T := T * 10 sec;  -- Failure_here
+    -- SEMANTIC ERROR:  if one operand is physical, then the other must
+    --             an integer or floating point type.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p14n01i02273 - If one operand is of type physical, the other has to be of type integer or real." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02273arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2274.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2274.vhd
new file mode 100644
index 0000000..f7eaf76
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2274.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2274.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02274ent IS
+END c07s02b06x00p14n01i02274ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02274arch OF c07s02b06x00p14n01i02274ent IS
+BEGIN
+  TESTING: PROCESS
+    type     SINGLE_NUMERIC_ARRAY is array ( 1 to 1 ) of REAL;
+    function F ( A : SINGLE_NUMERIC_ARRAY ) return SINGLE_NUMERIC_ARRAY is
+      variable B : TIME := 1 sec;
+    begin
+      return A * B; -- Failure_here
+      -- SEMANTIC ERROR:  if one operand is physical, then the other
+      --             must be integer or floating point.
+    end F;
+    variable A : SINGLE_NuMERIC_ARRAY;
+    variable T : TIME := 1 sec;
+  BEGIN
+    T := 1 MS * F(A);  -- Failure_here
+    -- SEMANTIC ERROR:  if one operand is physical, then the other must
+    --             an integer or floating point type.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p14n01i02274 - If one operand is of type physical, the other has to be of type integer or real." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02274arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2275.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2275.vhd
new file mode 100644
index 0000000..1d866b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2275.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2275.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02275ent IS
+END c07s02b06x00p14n01i02275ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02275arch OF c07s02b06x00p14n01i02275ent IS
+BEGIN
+  TESTING: PROCESS
+    type ENUMERATION_TYPE is (ONE,TWO,THREE,FOUR);
+    variable T : TIME := 1 sec;
+  BEGIN
+    T := ONE * 1 MIN;  -- Failure_here
+    -- SEMANTIC ERROR:  if one operand is physical, then the other must
+    --             an integer or floating point type.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p14n01i02275 - If one operand is of type physical, the other has to be of type integer or real." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02275arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2276.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2276.vhd
new file mode 100644
index 0000000..5359420
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2276.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2276.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02276ent IS
+END c07s02b06x00p14n01i02276ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02276arch OF c07s02b06x00p14n01i02276ent IS
+BEGIN
+  TESTING: PROCESS
+    type DISTANCE is range 1 to 118
+      units
+        FURLONG;
+      end units;
+    variable D : DISTANCE;
+    variable T : TIME := 1 sec;
+  BEGIN
+    D := T * 1 FURLONG;  -- Failure_here
+    -- SEMANTIC ERROR:  if one operand is physical, then the other must
+    --             an integer or floating point type.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p14n01i02276 - If one operand is of type physical, the other has to be of type integer or real." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02276arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2277.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2277.vhd
new file mode 100644
index 0000000..e26db80
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2277.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2277.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02277ent IS
+END c07s02b06x00p14n01i02277ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02277arch OF c07s02b06x00p14n01i02277ent IS
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+--                             m        = 100 cm;    -- meter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+--                             ft       = 12 inch;   -- foot
+--                             yd       = 3 ft;      -- yard
+      end units;
+    
+    -- Local declarations.
+    variable INTV    : INTEGER;
+    variable DISTV   : DISTANCE;
+  BEGIN
+    INTV := INTV / DISTV;   -- ERROR:
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p14n01i02277 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02277arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2278.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2278.vhd
new file mode 100644
index 0000000..d1746c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2278.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2278.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02278ent IS
+END c07s02b06x00p14n01i02278ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02278arch OF c07s02b06x00p14n01i02278ent IS
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable INTV    : INTEGER;
+    variable TIMEV   : TIME;
+  BEGIN
+    INTV := INTV / TIMEV;   -- ERROR:
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p14n01i02278 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02278arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2279.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2279.vhd
new file mode 100644
index 0000000..69df498
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2279.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2279.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02279ent IS
+END c07s02b06x00p14n01i02279ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02279arch OF c07s02b06x00p14n01i02279ent IS
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable REALV   : REAL;
+    variable TIMEV   : TIME;
+  BEGIN
+    REALV := REALV / TIMEV;   -- ERROR:
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p14n01i02279 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02279arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2280.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2280.vhd
new file mode 100644
index 0000000..7a8db53
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2280.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2280.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02280ent IS
+END c07s02b06x00p14n01i02280ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02280arch OF c07s02b06x00p14n01i02280ent IS
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+--                             m        = 100 cm;    -- meter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+--                             ft       = 12 inch;   -- foot
+--                             yd       = 3 ft;      -- yard
+      end units;
+    
+    -- Local declarations.
+    variable REALV   : REAL;
+    variable DISTV   : DISTANCE;
+  BEGIN
+    REALV := REALV / DISTV;   -- ERROR:
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p14n01i02280 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02280arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2281.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2281.vhd
new file mode 100644
index 0000000..77af878
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2281.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2281.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02281ent IS
+END c07s02b06x00p14n01i02281ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02281arch OF c07s02b06x00p14n01i02281ent IS
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+--                             m        = 100 cm;    -- meter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+--                             ft       = 12 inch;   -- foot
+--                             yd       = 3 ft;      -- yard
+      end units;
+    
+    -- Local declarations.
+    variable INTV    : INTEGER;
+    variable DISTV   : DISTANCE;
+    variable TIMEV   : TIME;
+  BEGIN
+    -- Test multiplying two different physical types.
+    INTV  := DISTV * TIMEV; -- ERROR
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p14n01i02281 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02281arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2282.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2282.vhd
new file mode 100644
index 0000000..e17fd39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2282.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2282.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b06x00p14n01i02282ent IS
+END c07s02b06x00p14n01i02282ent;
+
+ARCHITECTURE c07s02b06x00p14n01i02282arch OF c07s02b06x00p14n01i02282ent IS
+BEGIN
+  TESTING: PROCESS
+    -- user defined physical types.
+    type DISTANCE is range 0 to 1E9
+      units
+        -- Base units.
+        A;                    -- angstrom
+
+        -- Metric lengths.
+        nm       = 10 A;      -- nanometer
+        um       = 1000 nm;   -- micrometer (or micron)
+        mm       = 1000 um;   -- millimeter
+        cm       = 10 mm;     -- centimeter
+--                             m        = 100 cm;    -- meter
+        
+        -- English lengths.
+        mil      = 254000 A;  -- mil
+        inch     = 1000 mil;  -- inch
+--                             ft       = 12 inch;   -- foot
+--                             yd       = 3 ft;      -- yard
+      end units;
+    
+    -- Local declarations.
+    variable INTV    : INTEGER;
+    variable DISTV   : DISTANCE;
+    variable TIMEV   : TIME;
+  BEGIN
+    -- Try dividing them.
+    INTV := DISTV / TIMEV;  -- ERROR
+    assert FALSE 
+      report "***FAILED TEST: c07s02b06x00p14n01i02282 - Incompatible operands: May not be multiplied or divided." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b06x00p14n01i02282arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2306.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2306.vhd
new file mode 100644
index 0000000..1ad172e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2306.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2306.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02306ent IS
+END c07s02b07x00p01n01i02306ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02306arch OF c07s02b07x00p01n01i02306ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_one is array (1 to 10) of boolean;
+    variable x : array_one;
+    variable z : integer;
+  BEGIN
+    z := abs(x);  -- Failure_here
+    -- abs is not defined for array types.
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02306 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02306arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc231.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc231.vhd
new file mode 100644
index 0000000..67aa769
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc231.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc231.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p02n01i00231ent IS
+END c03s01b02x00p02n01i00231ent;
+
+ARCHITECTURE c03s01b02x00p02n01i00231arch OF c03s01b02x00p02n01i00231ent IS
+  type a is range (1+1) to (10.0 + 20.0);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p02n01i00231 - The right bound in the range constraint is not a locally static expression of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p02n01i00231arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2310.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2310.vhd
new file mode 100644
index 0000000..ac8f2f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2310.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2310.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02310ent IS
+END c07s02b07x00p01n01i02310ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02310arch OF c07s02b07x00p01n01i02310ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- enumerated types.
+    type     SWITCH_LEVEL is ('0', '1', 'X');
+    -- Local declarations.
+    variable SWITCHV  : SWITCH_LEVEL := '0';
+  BEGIN
+    SWITCHV  := ABS SWITCHV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02310 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02310arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2311.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2311.vhd
new file mode 100644
index 0000000..76a66d6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2311.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2311.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02311ent IS
+END c07s02b07x00p01n01i02311ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02311arch OF c07s02b07x00p01n01i02311ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- enumerated types.
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    -- Local declarations.
+    variable LOGICV   : LOGIC_SWITCH := '0';
+  BEGIN
+    LOGICV   := ABS LOGICV;   
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02311 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02311arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2312.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2312.vhd
new file mode 100644
index 0000000..2c47b40
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2312.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2312.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02312ent IS
+END c07s02b07x00p01n01i02312ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02312arch OF c07s02b07x00p01n01i02312ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable CHARV    : CHARACTER    := '0';
+  BEGIN
+    CHARV    := ABS CHARV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02312 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02312arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2313.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2313.vhd
new file mode 100644
index 0000000..ee97e81
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2313.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2313.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02313ent IS
+END c07s02b07x00p01n01i02313ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02313arch OF c07s02b07x00p01n01i02313ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- Local declarations.
+    variable BITV     : BIT          := '0';
+  BEGIN
+    BITV     := ABS BITV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02313 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02313arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2314.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2314.vhd
new file mode 100644
index 0000000..912491c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2314.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2314.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02314ent IS
+END c07s02b07x00p01n01i02314ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02314arch OF c07s02b07x00p01n01i02314ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV   : SEVERITY_LEVEL := NOTE;
+  BEGIN
+    SEVERV   := ABS SEVERV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02314 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02314arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2315.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2315.vhd
new file mode 100644
index 0000000..ed284a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2315.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2315.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02315ent IS
+END c07s02b07x00p01n01i02315ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02315arch OF c07s02b07x00p01n01i02315ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEMORY is array(INTEGER range <>) of BIT;
+    variable MEMORYV  : MEMORY( 0 to 31 );
+  BEGIN
+    MEMORYV  := ABS MEMORYV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02315 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02315arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2316.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2316.vhd
new file mode 100644
index 0000000..a477419
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2316.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2316.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02316ent IS
+END c07s02b07x00p01n01i02316ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02316arch OF c07s02b07x00p01n01i02316ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type WORD   is array(0 to 31) of BIT;
+    variable WORDV    : WORD;
+  BEGIN
+    WORDV    := ABS WORDV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02316 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02316arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2317.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2317.vhd
new file mode 100644
index 0000000..78f3579
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2317.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2317.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02317ent IS
+END c07s02b07x00p01n01i02317ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02317arch OF c07s02b07x00p01n01i02317ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BYTE   is array(7 downto 0) of BIT;
+    variable BYTEV    : BYTE;
+  BEGIN
+    BYTEV    := ABS BYTEV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02317 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02317arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2318.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2318.vhd
new file mode 100644
index 0000000..7e067fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2318.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2318.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02318ent IS
+END c07s02b07x00p01n01i02318ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02318arch OF c07s02b07x00p01n01i02318ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable STRINGV  : STRING( 1 to 9 );
+  BEGIN
+    STRINGV  := ABS STRINGV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02318 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02318arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2319.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2319.vhd
new file mode 100644
index 0000000..4aa2db2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2319.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2319.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02319ent IS
+END c07s02b07x00p01n01i02319ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02319arch OF c07s02b07x00p01n01i02319ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITSTRV  : BIT_VECTOR( 0 to 7 );
+  BEGIN
+    BITSTRV  := ABS BITSTRV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02319 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02319arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2320.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2320.vhd
new file mode 100644
index 0000000..83582b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2320.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2320.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02320ent IS
+END c07s02b07x00p01n01i02320ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02320arch OF c07s02b07x00p01n01i02320ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    variable RECV     : DATE;
+  BEGIN
+    RECV     := ABS RECV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02320 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02320arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2321.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2321.vhd
new file mode 100644
index 0000000..11ff78c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2321.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2321.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02321ent IS
+END c07s02b07x00p01n01i02321ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02321arch OF c07s02b07x00p01n01i02321ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEMORY is array(INTEGER range <>) of BIT;
+    type ADDRESS  is access MEMORY;
+    variable ADDRESSV : ADDRESS;
+  BEGIN
+    ADDRESSV := ABS ADDRESSV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02321 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02321arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2322.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2322.vhd
new file mode 100644
index 0000000..0a559bb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2322.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2322.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02322ent IS
+END c07s02b07x00p01n01i02322ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02322arch OF c07s02b07x00p01n01i02322ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type WORD   is array(0 to 31) of BIT;
+    type WORDPTR  is access WORD;
+    variable WORDPTRV : WORDPTR;
+  BEGIN
+    WORDPTRV := ABS WORDPTRV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02322 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02322arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2323.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2323.vhd
new file mode 100644
index 0000000..7e90b41
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2323.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2323.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p01n01i02323ent IS
+END c07s02b07x00p01n01i02323ent;
+
+ARCHITECTURE c07s02b07x00p01n01i02323arch OF c07s02b07x00p01n01i02323ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- file types.
+    type FT is file of BIT;
+    file     FILEV    : FT is "input_file";
+  BEGIN
+    FILEV    := ABS FILEV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p01n01i02323 - Unary operator abs is predefined for any numeric type only."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p01n01i02323arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2327.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2327.vhd
new file mode 100644
index 0000000..a5ce981
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2327.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2327.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02327ent IS
+END c07s02b07x00p02n02i02327ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02327arch OF c07s02b07x00p02n02i02327ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x : integer := 4;
+    constant y : boolean := true;
+    variable z : integer;
+  BEGIN
+    z := y**x; -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02327 - The exponentiating operator is predefined only for integer and floating point types."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02327arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2328.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2328.vhd
new file mode 100644
index 0000000..efe6e70
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2328.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2328.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02328ent IS
+END c07s02b07x00p02n02i02328ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02328arch OF c07s02b07x00p02n02i02328ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x : real := 4.5;
+    constant y : integer := 5;
+    variable z : integer;
+  BEGIN
+    z := y**x;   -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02328 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02328arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2333.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2333.vhd
new file mode 100644
index 0000000..c917b2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2333.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2333.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02333ent IS
+END c07s02b07x00p02n02i02333ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02333arch OF c07s02b07x00p02n02i02333ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    variable SWITCHV  : SWITCH_LEVEL := '0';
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := SWITCHV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02333 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02333arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2334.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2334.vhd
new file mode 100644
index 0000000..e66bd63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2334.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2334.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02334ent IS
+END c07s02b07x00p02n02i02334ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02334arch OF c07s02b07x00p02n02i02334ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    variable LOGICV   : LOGIC_SWITCH := '0';
+    variable INTV       : LOGIC_SWITCH := '0';
+  BEGIN
+    INTV     := LOGICV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02334 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02334arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2335.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2335.vhd
new file mode 100644
index 0000000..b479263
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2335.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2335.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02335ent IS
+END c07s02b07x00p02n02i02335ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02335arch OF c07s02b07x00p02n02i02335ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable CHARV       : CHARACTER    := '0';
+    variable INTV       : CHARACTER    := '0';
+  BEGIN
+    INTV     := CHARV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02335 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02335arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2336.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2336.vhd
new file mode 100644
index 0000000..a361415
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2336.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2336.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02336ent IS
+END c07s02b07x00p02n02i02336ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02336arch OF c07s02b07x00p02n02i02336ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITV     : BIT          := '0';
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := BITV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02336 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02336arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2337.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2337.vhd
new file mode 100644
index 0000000..ee92e3a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2337.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2337.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02337ent IS
+END c07s02b07x00p02n02i02337ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02337arch OF c07s02b07x00p02n02i02337ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV   : SEVERITY_LEVEL := NOTE;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := SEVERV ** 2; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02337 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02337arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2338.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2338.vhd
new file mode 100644
index 0000000..0826539
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2338.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2338.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02338ent IS
+END c07s02b07x00p02n02i02338ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02338arch OF c07s02b07x00p02n02i02338ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEMORY is array(INTEGER range <>) of BIT;
+    variable MEMORYV  : MEMORY( 0 to 31 );
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := MEMORYV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02338 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02338arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2339.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2339.vhd
new file mode 100644
index 0000000..1da569f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2339.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2339.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02339ent IS
+END c07s02b07x00p02n02i02339ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02339arch OF c07s02b07x00p02n02i02339ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type WORD   is array(0 to 31) of BIT;
+    variable WORDV    : WORD;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := WORDV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02339 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02339arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2340.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2340.vhd
new file mode 100644
index 0000000..2329bf9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2340.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2340.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02340ent IS
+END c07s02b07x00p02n02i02340ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02340arch OF c07s02b07x00p02n02i02340ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BYTE   is array(7 downto 0) of BIT;
+    variable BYTEV    : BYTE;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := BYTEV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02340 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02340arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2341.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2341.vhd
new file mode 100644
index 0000000..7e8df6b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2341.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2341.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02341ent IS
+END c07s02b07x00p02n02i02341ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02341arch OF c07s02b07x00p02n02i02341ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable STRINGV  : STRING( 1 to 8 );
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := STRINGV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02341 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02341arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2342.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2342.vhd
new file mode 100644
index 0000000..e5e7a3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2342.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2342.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02342ent IS
+END c07s02b07x00p02n02i02342ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02342arch OF c07s02b07x00p02n02i02342ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- record types.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    variable RECV     : DATE;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := RECV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02342 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02342arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2343.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2343.vhd
new file mode 100644
index 0000000..d58d715
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2343.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2343.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02343ent IS
+END c07s02b07x00p02n02i02343ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02343arch OF c07s02b07x00p02n02i02343ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEMORY is array(INTEGER range <>) of BIT;
+    type ADDRESS  is access MEMORY;
+    variable ADDRESSV : ADDRESS;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := ADDRESSV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02343 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02343arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2344.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2344.vhd
new file mode 100644
index 0000000..99f7257
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2344.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2344.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02344ent IS
+END c07s02b07x00p02n02i02344ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02344arch OF c07s02b07x00p02n02i02344ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type WORD   is array(0 to 31) of BIT;
+    type WORDPTR  is access WORD;
+    variable WORDPTRV : WORDPTR;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := WORDPTRV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02344 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02344arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2345.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2345.vhd
new file mode 100644
index 0000000..016e0e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2345.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2345.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02345ent IS
+END c07s02b07x00p02n02i02345ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02345arch OF c07s02b07x00p02n02i02345ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- file types.
+    type FT is file of BIT;
+    file     FILEV    : FT is "input_file";
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := FILEV ** 2;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02345 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02345arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2346.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2346.vhd
new file mode 100644
index 0000000..df4ff84
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2346.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2346.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02346ent IS
+END c07s02b07x00p02n02i02346ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02346arch OF c07s02b07x00p02n02i02346ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    variable SWITCHV  : SWITCH_LEVEL := '0';
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** SWITCHV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02346 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02346arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2347.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2347.vhd
new file mode 100644
index 0000000..15315fd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2347.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2347.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02347ent IS
+END c07s02b07x00p02n02i02347ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02347arch OF c07s02b07x00p02n02i02347ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    SWITCH_LEVEL is ('0', '1', 'X');
+    subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
+    variable LOGICV   : LOGIC_SWITCH := '0';
+    variable INTV     : integer;
+  BEGIN
+    INTV     := 2 ** LOGICV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02347 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02347arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2348.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2348.vhd
new file mode 100644
index 0000000..bb55eec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2348.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2348.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02348ent IS
+END c07s02b07x00p02n02i02348ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02348arch OF c07s02b07x00p02n02i02348ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable CHARV    : CHARACTER    := '0';
+    variable INTV    : INTEGER;
+  BEGIN
+    INTV     := 2 * CHARV ;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02348 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02348arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2349.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2349.vhd
new file mode 100644
index 0000000..e2299f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2349.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2349.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02349ent IS
+END c07s02b07x00p02n02i02349ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02349arch OF c07s02b07x00p02n02i02349ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable BITV     : BIT          := '0';
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** BITV;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02349 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02349arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc235.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc235.vhd
new file mode 100644
index 0000000..749358e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc235.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc235.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00235ent IS
+  port (  p1 : inout integer;
+          p2 : inout integer);
+END c03s01b02x00p04n01i00235ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00235arch OF c03s01b02x00p04n01i00235ent IS
+  type t3 is range p1 to p2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00235 -The range constraints in the type definition of 't3' must be locally static."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00235arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2350.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2350.vhd
new file mode 100644
index 0000000..7bff53d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2350.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2350.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02350ent IS
+END c07s02b07x00p02n02i02350ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02350arch OF c07s02b07x00p02n02i02350ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable SEVERV   : SEVERITY_LEVEL := NOTE;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** SEVERV ; 
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02350 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02350arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2351.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2351.vhd
new file mode 100644
index 0000000..91e76b7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2351.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2351.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02351ent IS
+END c07s02b07x00p02n02i02351ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02351arch OF c07s02b07x00p02n02i02351ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEMORY is array(INTEGER range <>) of BIT;
+    variable MEMORYV  : MEMORY( 0 to 31 );
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** MEMORYV ;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02351 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02351arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2352.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2352.vhd
new file mode 100644
index 0000000..441457e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2352.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2352.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02352ent IS
+END c07s02b07x00p02n02i02352ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02352arch OF c07s02b07x00p02n02i02352ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type WORD   is array(0 to 31) of BIT;
+    variable WORDV    : WORD;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** WORDV ;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02352 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02352arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2353.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2353.vhd
new file mode 100644
index 0000000..da29ab0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2353.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2353.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02353ent IS
+END c07s02b07x00p02n02i02353ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02353arch OF c07s02b07x00p02n02i02353ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type BYTE   is array(7 downto 0) of BIT;
+    variable BYTEV    : BYTE;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** BYTEV ;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02353 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02353arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2354.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2354.vhd
new file mode 100644
index 0000000..a28aa5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2354.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2354.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02354ent IS
+END c07s02b07x00p02n02i02354ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02354arch OF c07s02b07x00p02n02i02354ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable STRINGV  : STRING( 1 to 8 );
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** STRINGV ;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02354 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02354arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2355.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2355.vhd
new file mode 100644
index 0000000..bbdcbe1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2355.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2355.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02355ent IS
+END c07s02b07x00p02n02i02355ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02355arch OF c07s02b07x00p02n02i02355ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- record types.
+    type DATE is
+      record
+        DAY           : INTEGER range 1 to 31;
+        MONTH         : INTEGER range 1 to 12;
+        YEAR          : INTEGER range -10000 to 1988;
+      end record;
+    variable RECV     : DATE;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** RECV ;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02355 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02355arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2356.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2356.vhd
new file mode 100644
index 0000000..0dda035
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2356.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2356.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02356ent IS
+END c07s02b07x00p02n02i02356ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02356arch OF c07s02b07x00p02n02i02356ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type MEMORY is array(INTEGER range <>) of BIT;
+    type ADDRESS  is access MEMORY;
+    variable ADDRESSV : ADDRESS;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** ADDRESSV ;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02356 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02356arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2357.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2357.vhd
new file mode 100644
index 0000000..70c7ce5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2357.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2357.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02357ent IS
+END c07s02b07x00p02n02i02357ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02357arch OF c07s02b07x00p02n02i02357ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type WORD   is array(0 to 31) of BIT;
+    type WORDPTR  is access WORD;
+    variable WORDPTRV : WORDPTR;
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** WORDPTRV ;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02357 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02357arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2358.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2358.vhd
new file mode 100644
index 0000000..d0d382f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2358.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2358.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p02n02i02358ent IS
+END c07s02b07x00p02n02i02358ent;
+
+ARCHITECTURE c07s02b07x00p02n02i02358arch OF c07s02b07x00p02n02i02358ent IS
+
+BEGIN
+  TESTING: PROCESS
+    -- file types.
+    type FT is file of BIT;
+    file     FILEV    : FT is "input_file";
+    variable INTV     : INTEGER;
+  BEGIN
+    INTV     := 2 ** FILEV ;
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p02n02i02358 - Exponent can only be of type Integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p02n02i02358arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc236.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc236.vhd
new file mode 100644
index 0000000..47165e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc236.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc236.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00236ent IS
+END c03s01b02x00p04n01i00236ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00236arch OF c03s01b02x00p04n01i00236ent IS
+  type t3 is range (1+1) to (10.0 + 2.0); 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00236 - The right bound in the range constraint is not a locally static expression of type integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00236arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2361.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2361.vhd
new file mode 100644
index 0000000..afcc330
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2361.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2361.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p10n02i02361ent IS
+END c07s02b07x00p10n02i02361ent;
+
+ARCHITECTURE c07s02b07x00p10n02i02361arch OF c07s02b07x00p10n02i02361ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type NEW_INTEGER is range INTEGER'LOW to INTEGER'HIGH;
+    variable A : integer := 5;
+    variable k : NEW_INTEGER := 0;
+  BEGIN
+    k := A ** (-2);    --Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p10n02i02361 - Left operand must be floating point type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p10n02i02361arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2362.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2362.vhd
new file mode 100644
index 0000000..ce80071
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2362.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2362.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b07x00p10n02i02362ent IS
+END c07s02b07x00p10n02i02362ent;
+
+ARCHITECTURE c07s02b07x00p10n02i02362arch OF c07s02b07x00p10n02i02362ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type NEW_INTEGER is range INTEGER'LOW to INTEGER'HIGH;
+    variable k : NEW_INTEGER := 10 ** (-2);
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s02b07x00p10n02i02362 - Left operand must be floating point type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b07x00p10n02i02362arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2375.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2375.vhd
new file mode 100644
index 0000000..79a07e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2375.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2375.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p02n01i02375ent IS
+END c07s03b02x00p02n01i02375ent;
+
+ARCHITECTURE c07s03b02x00p02n01i02375arch OF c07s03b02x00p02n01i02375ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       x1 is array (1 to 2) of integer;
+    constant    v1 : x1    := (0 0);   -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p02n01i02375 - A comma(,) is missing between the elements of the aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p02n01i02375arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2376.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2376.vhd
new file mode 100644
index 0000000..cbdaf69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2376.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2376.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p02n01i02376ent IS
+END c07s03b02x00p02n01i02376ent;
+
+ARCHITECTURE c07s03b02x00p02n01i02376arch OF c07s03b02x00p02n01i02376ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type x1 is array (1 to 2) of integer;
+    constant v1: x1 := 0, 0;   -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p02n01i02376 - Parentheses enclosing the elements of the aggregate are missing." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p02n01i02376arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2377.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2377.vhd
new file mode 100644
index 0000000..73c545a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2377.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2377.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p02n01i02377ent IS
+END c07s03b02x00p02n01i02377ent;
+
+ARCHITECTURE c07s03b02x00p02n01i02377arch OF c07s03b02x00p02n01i02377ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM is ( ONE, TWO, THREE, FOUR );
+    function F_ENUM (       A : ENUM := ONE;
+                            B : ENUM := TWO ) return ENUM is
+    begin
+      return A;
+    end F_ENUM;
+    variable V : ENUM := F_ENUM(,); -- Failure_here
+    -- SYNTAX ERROR:  null parameter association not legal.
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p02n01i02377 - Null association element is not allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p02n01i02377arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2379.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2379.vhd
new file mode 100644
index 0000000..2ce94ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2379.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2379.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p03n01i02379ent IS
+END c07s03b02x00p03n01i02379ent;
+
+ARCHITECTURE c07s03b02x00p03n01i02379arch OF c07s03b02x00p03n01i02379ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T1 is array (1 to 5) of integer;
+    constant C1 : T1 := (1 => 0, 2 => 2,others  4) ; -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p03n01i02379 - Missing operator." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p03n01i02379arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2381.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2381.vhd
new file mode 100644
index 0000000..cfff5d6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2381.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2381.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p04n01i02381ent IS
+END c07s03b02x00p04n01i02381ent;
+
+ARCHITECTURE c07s03b02x00p04n01i02381arch OF c07s03b02x00p04n01i02381ent IS
+  type T1 is array (1 to 5) of integer;
+  constant C1 : T1 := (1 2 => 0, others => 4) ; -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p04n01i02381 - Missing vertical bar." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p04n01i02381arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2385.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2385.vhd
new file mode 100644
index 0000000..676653d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2385.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2385.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02385ent IS
+END c07s03b02x00p07n01i02385ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02385arch OF c07s03b02x00p07n01i02385ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_type is array (1 to 10) of integer;
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : real;
+                  ele_3 : boolean;
+                  ele_4 : array_type;
+                end record;
+
+    type array_three is array (1 to 6) of integer;
+    variable x : rec :=
+      (ele_1 => 1, ele_2 => 2.3, true,
+       (1,2,3,4,5,6,7,8,9,0));  -- Failure_here
+    -- positional associations should occur before named associations.   
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p07n01i02385 - Positional associations should appear before named associations in the same aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02385arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2386.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2386.vhd
new file mode 100644
index 0000000..af5dca4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2386.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2386.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02386ent IS
+END c07s03b02x00p07n01i02386ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02386arch OF c07s03b02x00p07n01i02386ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_three is array (1 to 6) of integer;
+    variable x : array_three := (1 =>10, 3 => 30,
+                                 others => 20, 2 => 25); -- Failure_here
+    -- no association can
+    -- follow an others association.
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p07n01i02386 - No association can follow an others association." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02386arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2393.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2393.vhd
new file mode 100644
index 0000000..fee9c3e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2393.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2393.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n02i02393ent IS
+END c07s03b02x00p07n02i02393ent;
+
+ARCHITECTURE c07s03b02x00p07n02i02393arch OF c07s03b02x00p07n02i02393ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type t25 is record
+                  elem_1: integer;
+                end record;
+    variable v25 : t25;
+  BEGIN
+    v25 := (25);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p07n02i02393 - Aggregate specification should be using named association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n02i02393arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2397.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2397.vhd
new file mode 100644
index 0000000..f041716
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2397.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2397.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p07n01i02397ent IS
+END c07s03b02x00p07n01i02397ent;
+
+ARCHITECTURE c07s03b02x00p07n01i02397arch OF c07s03b02x00p07n01i02397ent IS
+  signal err : bit_vector(0 to 1) := (1 => '0', '1');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s03b02x00p07n01i02397 - Positional element association must occur before all named element association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p07n01i02397arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2398.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2398.vhd
new file mode 100644
index 0000000..a3dba3f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2398.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2398.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n01i02398ent IS
+END c07s03b02x00p08n01i02398ent;
+
+ARCHITECTURE c07s03b02x00p08n01i02398arch OF c07s03b02x00p08n01i02398ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : real;
+                end record;
+    type t22 is array (1 to 10) of integer;
+    variable v22 : t22;
+  BEGIN
+    v22 := (ele_1 => 22, others => 0);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p08n01i02398 - Element associations by an element simple name is allowed only in recordi aggregates."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n01i02398arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc240.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc240.vhd
new file mode 100644
index 0000000..f3fb57a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc240.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc240.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00240ent IS
+END c03s01b02x00p04n01i00240ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00240arch OF c03s01b02x00p04n01i00240ent IS
+  type a is range (1+1) to 10;
+  type b is range (10+1) to 100;
+  type c is range a to b; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00240 - The bounds in the range constraint are not locally static expressions of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00240arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2402.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2402.vhd
new file mode 100644
index 0000000..3948ddb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2402.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2402.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n02i02402ent IS
+END c07s03b02x00p08n02i02402ent;
+
+ARCHITECTURE c07s03b02x00p08n02i02402arch OF c07s03b02x00p08n02i02402ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is record
+                       ele_1 : integer;
+                       ele_2 : integer;
+                     end record;
+    variable v20 : rec_type;
+  BEGIN
+    v20 := (1 + 1 => 20, ele_2 => 0);  -- Failure_here
+    -- simple expression
+    -- associations allowed only in array agregates.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p08n02i02402 - Element associations by simple expressions allowed only in array aggregates."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n02i02402arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2405.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2405.vhd
new file mode 100644
index 0000000..d06a2bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2405.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2405.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n05i02405ent IS
+END c07s03b02x00p08n05i02405ent;
+
+ARCHITECTURE c07s03b02x00p08n05i02405arch OF c07s03b02x00p08n05i02405ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  type RECORD_TYPE is record
+                        E1,E2,E3 : BOOLEAN;
+                      end record;
+  signal S2 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= (E2 => TRUE, others | E1 => FALSE); -- Failure_here
+    -- SEMANTIC ERROR:  "others" must be only choice in an association.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p08n05i02405 - Only one others association is allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n05i02405arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2406.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2406.vhd
new file mode 100644
index 0000000..712701e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2406.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2406.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n05i02406ent IS
+END c07s03b02x00p08n05i02406ent;
+
+ARCHITECTURE c07s03b02x00p08n05i02406arch OF c07s03b02x00p08n05i02406ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;
+  signal S1 : ARRAY_TYPE(1 to 2) ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= (others=>TRUE,TRUE); -- Failure_here
+    -- SEMANTIC ERROR:  association cannot follow "others" association.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p08n05i02406 - Nothing may follow an others association." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n05i02406arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2407.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2407.vhd
new file mode 100644
index 0000000..697d326
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2407.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2407.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n05i02407ent IS
+END c07s03b02x00p08n05i02407ent;
+
+ARCHITECTURE c07s03b02x00p08n05i02407arch OF c07s03b02x00p08n05i02407ent IS
+  type ARRAY_TYPE is array (INTEGER range <>) of BOOLEAN;      
+  type RECORD_TYPE is record
+                        E1,E2 : BOOLEAN;
+                      end record;
+  signal S2 : RECORD_TYPE;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S2 <= (others=>TRUE,others=>FALSE); -- Failure_here
+    -- SEMANTIC ERROR:  more than one "others" association.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p08n05i02407 - Only one others association is allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n05i02407arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2409.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2409.vhd
new file mode 100644
index 0000000..fd0bc23
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2409.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2409.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p08n05i02409ent IS
+END c07s03b02x00p08n05i02409ent;
+
+ARCHITECTURE c07s03b02x00p08n05i02409arch OF c07s03b02x00p08n05i02409ent IS
+  signal err : bit_vector(0 to 2);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    err <= (1 => '1', others => '0', others => '1');
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s03b02x00p08n05i02409 - Only one others association is allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p08n05i02409arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2410.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2410.vhd
new file mode 100644
index 0000000..a8044f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2410.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2410.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p09n01i02410ent IS
+END c07s03b02x00p09n01i02410ent;
+
+ARCHITECTURE c07s03b02x00p09n01i02410arch OF c07s03b02x00p09n01i02410ent IS
+  type     array_three is array (1 to 6) of integer;
+  constant x : array_three := (1, 2, 3, 4, 5, 6);
+  constant y : array_three := (1 => 1, 2 => 2, 2 => 3,others => 0);
+  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p09n01i02410 - An element of the value defined by an aggregate can be represented only once in an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p09n01i02410arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2411.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2411.vhd
new file mode 100644
index 0000000..e082d8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2411.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2411.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p09n01i02411ent IS
+END c07s03b02x00p09n01i02411ent;
+
+ARCHITECTURE c07s03b02x00p09n01i02411arch OF c07s03b02x00p09n01i02411ent IS
+  type BIT_VECTOR is array
+    (natural range <>, natural range <>) of BIT;
+BEGIN
+  TESTING: PROCESS
+    variable NUM1 : BIT_VECTOR(0 to 1, 0 to 7) := (
+      ('0', '0'), ('1', '1'),
+      ('0', '1'), ('1', '1'),
+      ('0', '1'), ('0', '1'),
+      ('0', '1'), ('1', '1'),
+      ('1', '0'), ('1', '0')
+      );  -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p09n01i02411 - Each element of the value defined by an aggregate must be represented once and only once in the aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p09n01i02411arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2413.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2413.vhd
new file mode 100644
index 0000000..7668367
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2413.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2413.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p09n01i02413ent IS
+END c07s03b02x00p09n01i02413ent;
+
+ARCHITECTURE c07s03b02x00p09n01i02413arch OF c07s03b02x00p09n01i02413ent IS
+  signal err : bit_vector(0 to 1) := (0 => '1', 1 => '0', 1 => '1');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 2 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s03b02x00p09n01i02413 - Each element of aggregate must be represented once and only once in the aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p09n01i02413arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2414.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2414.vhd
new file mode 100644
index 0000000..1665176
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2414.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2414.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p10n01i02414ent IS
+END c07s03b02x00p10n01i02414ent;
+
+ARCHITECTURE c07s03b02x00p10n01i02414arch OF c07s03b02x00p10n01i02414ent IS
+  type s27 is array (1 to 4) of integer;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : s27 := (1, 2, 3, 4);
+  BEGIN
+    (v1(1) , v1(2)) := (v1(3), v1(4)); -- Failure_here
+                                           -- type of aggregate not
+                                           -- determinable from context
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p10n01i02414 - Type of the aggregate must be determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p10n01i02414arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2416.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2416.vhd
new file mode 100644
index 0000000..161fa5f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2416.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2416.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x00p10n02i02416ent IS
+END c07s03b02x00p10n02i02416ent;
+
+ARCHITECTURE c07s03b02x00p10n02i02416arch OF c07s03b02x00p10n02i02416ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_2 : real;
+                  ele_3 : boolean;
+                end record;
+    variable v24 : rec;
+  BEGIN
+    v24 := (ele_2 => 23, ele_3 => True);      -- Failure_here
+                                              -- ele_2 is real.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x00p10n02i02416 - Elements of an aggregate should have the same type as that determined by the aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p10n02i02416arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2418.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2418.vhd
new file mode 100644
index 0000000..7ab3ce3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2418.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2418.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s03b02x00p10n01i02418pkg is
+  type byte is range 0 to 15;
+  type cmd_bus is array (0 to 3) of byte;
+end c07s03b02x00p10n01i02418pkg;
+
+use work.c07s03b02x00p10n01i02418pkg.all;
+ENTITY c07s03b02x00p10n01i02418ent IS
+  port ( signal b_inp : in boolean := (0 to 3 => 0) = (0 to 3 => 1));
+END c07s03b02x00p10n01i02418ent;
+
+ARCHITECTURE c07s03b02x00p10n01i02418arch OF c07s03b02x00p10n01i02418ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c07s03b02x00p10n01i02418 - The type of the aggregate is not determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p10n01i02418
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2419.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2419.vhd
new file mode 100644
index 0000000..5065c91
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2419.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2419.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s03b02x00p10n01i02419pkg is
+  type byte       is range 0 to 15;
+  type cmd_bus    is array (0 to 3) of byte;
+end c07s03b02x00p10n01i02419pkg;
+
+use work.c07s03b02x00p10n01i02419pkg.all;
+ENTITY c07s03b02x00p10n01i02419ent IS
+  port ( signal b_inp : in boolean := cmd_bus'(0 to 3 => 0) = (0 to 3 => 1));
+END c07s03b02x00p10n01i02419ent;
+
+ARCHITECTURE c07s03b02x00p10n01i02419arch OF c07s03b02x00p10n01i02419ent IS
+  signal b_sig : boolean := cmd_bus'(0 to 3 => 0) = (0 to 3 => 1);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    b_sig <= (0 to 3 => 0) = (0 to 3 => 1);
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s03b02x00p10n01i02419 - The type of the aggregate is not determinable from the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x00p10n01i02419arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc242.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc242.vhd
new file mode 100644
index 0000000..ab6a6d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc242.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc242.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00242ent IS
+END c03s01b02x00p04n01i00242ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00242arch OF c03s01b02x00p04n01i00242ent IS
+  type a is range (1+1) to 10.0;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00242 - The right bound in the range constraint is not a locally static expression of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00242arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2420.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2420.vhd
new file mode 100644
index 0000000..58181ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2420.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2420.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n01i02420ent IS
+END c07s03b02x01p01n01i02420ent;
+
+ARCHITECTURE c07s03b02x01p01n01i02420arch OF c07s03b02x01p01n01i02420ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : real;
+                  ele_3 : boolean;
+                  ele_4 : integer;
+                end record;
+    variable p : rec :=
+      (ele_3 => true, 
+       ele_1 => 1,
+       ele_2 => 3.4,
+       ele_5 => 12); -- Failure_here
+    -- ele_5 does not belong to the record type.
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x01p01n01i02420 - Element names must denote elments of the record type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n01i02420arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2422.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2422.vhd
new file mode 100644
index 0000000..345fbaa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2422.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2422.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n01i02422ent IS
+END c07s03b02x01p01n01i02422ent;
+
+ARCHITECTURE c07s03b02x01p01n01i02422arch OF c07s03b02x01p01n01i02422ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_RECORD is record
+                       A : CHARACTER;
+                     end record;
+    type B_RECORD is record
+                       B : CHARACTER;
+                     end record;
+    variable A : A_RECORD;
+    variable B : B_RECORD;
+  BEGIN
+    A := A_RECORD'(B=>'E'); -- Failure_here
+    -- SEMANTICS ERROR:  choice does not denote record element
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x01p01n01i02422 - Given element name does not match the record type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n01i02422arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2423.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2423.vhd
new file mode 100644
index 0000000..777e98c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2423.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2423.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n01i02423ent IS
+END c07s03b02x01p01n01i02423ent;
+
+ARCHITECTURE c07s03b02x01p01n01i02423arch OF c07s03b02x01p01n01i02423ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_RECORD is record
+                       A : CHARACTER;
+                     end record;
+    type B_RECORD is record
+                       B : CHARACTER;
+                     end record;
+    variable A : A_RECORD;
+    variable B : B_RECORD;
+  BEGIN
+    B := (A=>'F');          -- Failure_here
+    -- SEMANTICS ERROR:  choice does not denote record element
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x01p01n01i02423 - Given element name does not match the record type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n01i02423arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2424.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2424.vhd
new file mode 100644
index 0000000..dd6fde4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2424.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2424.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n02i02424ent IS
+END c07s03b02x01p01n02i02424ent;
+
+ARCHITECTURE c07s03b02x01p01n02i02424arch OF c07s03b02x01p01n02i02424ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_type is array (1 to 10) of integer;
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : real;
+                  ele_3 : boolean;
+                  ele_4 : array_type;
+                end record;
+    variable p : rec := (3,1.0,true,(1,3,5,7,9,0,8,6,4,2),others => 3); 
+    -- Failure_here
+        -- others should be used to
+            -- represent at least one element.
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x01p01n02i02424 - The choice others in a record aggregate should represent at least one element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n02i02424arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2426.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2426.vhd
new file mode 100644
index 0000000..a43508a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2426.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2426.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n03i02426ent IS
+END c07s03b02x01p01n03i02426ent;
+
+ARCHITECTURE c07s03b02x01p01n03i02426arch OF c07s03b02x01p01n03i02426ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : real;
+                  ele_3 : boolean;
+                end record;
+    variable p  :rec := (ele_1 => 4, others => true);  -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x01p01n03i02426 - Element association with others choice should be used to represent elements of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n03i02426arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2427.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2427.vhd
new file mode 100644
index 0000000..2ae30e2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2427.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2427.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n03i02427ent IS
+END c07s03b02x01p01n03i02427ent;
+
+ARCHITECTURE c07s03b02x01p01n03i02427arch OF c07s03b02x01p01n03i02427ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : real;
+                  ele_3 : boolean;
+                end record;
+    constant p  :rec := (ele_1 | ele_2 | ele_3 => 4.5);  -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x01p01n03i02427 - Element association with others choice should be used to represent elements of the same type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n03i02427arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2429.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2429.vhd
new file mode 100644
index 0000000..54c315d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2429.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2429.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x01p01n04i02429ent IS
+END c07s03b02x01p01n04i02429ent;
+
+ARCHITECTURE c07s03b02x01p01n04i02429arch OF c07s03b02x01p01n04i02429ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec is record
+                  ele_1 : integer;
+                  ele_2 : integer;
+                  ele_3 : boolean;
+                end record;
+    variable p : rec := (1,ele_2 => (3 < 5),ele_3 => true);  -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x01p01n04i02429 - Expression of an element association must have the same type as the associated record element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x01p01n04i02429arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc243.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc243.vhd
new file mode 100644
index 0000000..4db4faa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc243.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc243.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00243ent IS
+END c03s01b02x00p04n01i00243ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00243arch OF c03s01b02x00p04n01i00243ent IS
+  type CLSI is (Jasmine, Jim, Milan, Paul, Saurin);
+  constant x: CLSI := Jim;
+  constant y: CLSI := Paul;
+  type People is range x to y; 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00243 - Type mis-match in integer range constraint for type 'People'." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00243arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2431.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2431.vhd
new file mode 100644
index 0000000..00bfb51
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2431.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2431.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02431ent IS
+END c07s03b02x02p01n01i02431ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02431arch OF c07s03b02x02p01n01i02431ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type array_three is array (1 to 6) of integer;
+    variable x : array_three := (1=>2,2=>3,3=>4,4=>6.32,5=>6,6=>7);  -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p01n01i02431 - Expression of each element association must be of the element type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02431arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2433.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2433.vhd
new file mode 100644
index 0000000..2a992de
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2433.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2433.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02433ent IS
+END c07s03b02x02p01n01i02433ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02433arch OF c07s03b02x02p01n01i02433ent IS
+  subtype    BV1 is    BIT_VECTOR (2 downto 1);
+  constant    C18 :    BV1 := (3 => '1', others => '0');
+  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p01n01i02433 - Expression of each element association must be of the element type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02433arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2434.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2434.vhd
new file mode 100644
index 0000000..3b3b294
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2434.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2434.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02434ent IS
+END c07s03b02x02p01n01i02434ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02434arch OF c07s03b02x02p01n01i02434ent IS
+BEGIN
+  TESTING: PROCESS
+    type BIT_VECTOR is array (natural range <>, positive range <>) of BIT;
+    variable NUM1 : BIT_VECTOR(0 to 1) := ( ('0', '0'), ('1', '1'),
+                                            ('0', '1'), ('1', '1'),
+                                            ('0', '1'), ('0', '1'),
+                                            ('1', '0'), ('1', '0')  );
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p01n01i02434 - The elements of the aggregate of the one-dimensional array type do not specify values of the index type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02434arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2437.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2437.vhd
new file mode 100644
index 0000000..3368f08
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2437.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2437.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n02i02437ent IS
+END c07s03b02x02p01n02i02437ent;
+
+ARCHITECTURE c07s03b02x02p01n02i02437arch OF c07s03b02x02p01n02i02437ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    A_ARRAY is array ( boolean range <>,integer range <>) of integer;
+    subtype A_CON   is A_ARRAY (FALSE to TRUE, 1 to 2);
+    function F return A_CON is
+    begin
+      return ( others => 3 ); -- Failure_here
+      -- ERROR : Each element association must be an n-1 dimensional array aggregate
+    end;
+  BEGIN
+    assert  FALSE 
+      report "***FAILED TEST: c07s03b02x02p01n02i02437 - Each element association must be a n-1 dimensional array aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n02i02437arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2438.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2438.vhd
new file mode 100644
index 0000000..3fe0dc6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2438.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2438.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n02i02438ent IS
+END c07s03b02x02p01n02i02438ent;
+
+ARCHITECTURE c07s03b02x02p01n02i02438arch OF c07s03b02x02p01n02i02438ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    ENUM    is ( ONE, TWO, THREE, FOUR, FIVE );
+    type    A_ARRAY is array ( boolean range <>,integer range <>) of integer;
+    type    B_ARRAY is array ( ENUM range <>, ENUM range <> ) of real;
+    subtype A_CON   is A_ARRAY (FALSE to TRUE, 1 to 2);
+    function F return A_CON is
+    begin
+      return ( FALSE =>
+               ( 1 =>
+                 B_ARRAY'( ONE =>
+                           ( FIVE => 2.0),
+                           TWO =>
+                           (FIVE => 3.0)
+                           ),
+                 2 =>
+                 B_ARRAY'( ONE =>
+                           ( FIVE => 2.0),
+                           TWO =>
+                           (FIVE => 3.0)
+                           )
+                 )
+               );
+    end;
+  BEGIN
+    assert  FALSE 
+      report "***FAILED TEST: c07s03b02x02p01n02i02438 - Each element association must be a n-1 dimensional array aggregate." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n02i02438arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc244.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc244.vhd
new file mode 100644
index 0000000..44278f8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc244.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc244.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00244ent IS
+END c03s01b02x00p04n01i00244ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00244arch OF c03s01b02x00p04n01i00244ent IS
+  type CLSI is (Jasmine, Jim, Milan, Paul, Saurin);
+  constant x: CLSI := Jim;
+  constant y: CLSI := Paul;
+  type People is range CLSI'(Milan) to CLSI'(Saurin); 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00244 - Type mis-match in integer range constraint for type 'People'." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00244_arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2441.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2441.vhd
new file mode 100644
index 0000000..58ea542
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2441.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2441.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02441ent IS
+  type a_index    is range 0 to 15;
+  type a_bus       is array (a_index range <>) of bit;
+END c07s03b02x02p01n01i02441ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02441arch OF c07s03b02x02p01n01i02441ent IS
+  signal a_sig : a_bus(a_index range 0 to 3) := (4 => '1', others => '0');
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s03b02x02p01n01i02441 - Each choice must specify values of the index type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02441arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2442.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2442.vhd
new file mode 100644
index 0000000..9b28e32
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2442.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2442.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02442ent IS
+  type a_index    is range 0 to 15;
+  type a_bus       is array (a_index range <>) of bit;
+END c07s03b02x02p01n01i02442ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02442arch OF c07s03b02x02p01n01i02442ent IS
+  signal a_sig : a_bus(a_index range 0 to 3);
+BEGIN
+  TESTING: PROCESS
+    variable tmp : a_index := 0;
+  BEGIN
+    for i in a_index loop
+      tmp := i mod 4;
+      a_sig(tmp to tmp) <= 1;
+      if tmp >= 4 then
+        assert false
+          report "Choice index out of range."
+          severity note ;
+        exit;
+      end if;
+    end loop;
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s03b02x02p01n01i02442 - Each choice must specify values of the index type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02442arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2443.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2443.vhd
new file mode 100644
index 0000000..da99caa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2443.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2443.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02443ent IS
+  type idx    is range 0 to 15;
+  type aray    is array (idx) of positive;
+END c07s03b02x02p01n01i02443ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02443arch OF c07s03b02x02p01n01i02443ent IS
+  signal sig : aray := (others => 0);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s03b02x02p01n01i02443 - The expression of each element association must be of the element type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02443arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2444.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2444.vhd
new file mode 100644
index 0000000..136e555
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2444.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2444.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p01n01i02444ent IS
+  type idx    is range 0 to 15;
+  type aray    is array (idx) of positive;
+END c07s03b02x02p01n01i02444ent;
+
+ARCHITECTURE c07s03b02x02p01n01i02444arch OF c07s03b02x02p01n01i02444ent IS
+  signal sig : aray;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    sig <= (others => 0);
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c07s03b02x02p01n01i02444 - An aggregate of a one-dimensional array type the expression of each element association must be of the element type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p01n01i02444arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2445.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2445.vhd
new file mode 100644
index 0000000..c79ab52
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2445.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2445.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p02n01i02445ent IS
+END c07s03b02x02p02n01i02445ent;
+
+ARCHITECTURE c07s03b02x02p02n01i02445arch OF c07s03b02x02p02n01i02445ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    array_three is array (1 to 6) of integer;
+    variable x : array_three := ( 1,3,5, 5 => 10,
+                                  6 => 12, 4 => 8); -- Failure_Here
+    -- all associations
+    -- must be either positional or named.
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p02n01i02445 - All element associations of an array aggregate must be either all positional or all named."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p02n01i02445arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2447.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2447.vhd
new file mode 100644
index 0000000..bdd8814
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2447.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2447.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p02n02i02447ent IS
+END c07s03b02x02p02n02i02447ent;
+
+ARCHITECTURE c07s03b02x02p02n02i02447arch OF c07s03b02x02p02n02i02447ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type       t16 is array (1 to 1) of integer;
+    variable   v16 : t16;
+  BEGIN
+    v16 := (1 to 0 => 16, 1 => 12);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p02n02i02447 - Named association of an array aggregate can have a choice that is a null range only if the aggregate includes a single element association."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p02n02i02447arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2449.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2449.vhd
new file mode 100644
index 0000000..42107f8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2449.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2449.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p02n02i02449ent IS
+END c07s03b02x02p02n02i02449ent;
+
+ARCHITECTURE c07s03b02x02p02n02i02449arch OF c07s03b02x02p02n02i02449ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type t17 is array (0 to 0) of integer;
+    variable v17 : t17;
+  BEGIN
+    v17 := (1 to 0 | p => 17);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p02n02i02449 - Named association of an array aggregate can have a choice that is a null range only if the single element association has a single choice." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p02n02i02449arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc245.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc245.vhd
new file mode 100644
index 0000000..3c38af8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc245.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc245.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00245ent IS
+END c03s01b02x00p04n01i00245ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00245arch OF c03s01b02x00p04n01i00245ent IS
+  type I1 is range 1 to 9.0;  -- Failure_here
+  -- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
+  -- MUST BE OF INTEGER TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00245 - Range constraint must be an integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00245arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2450.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2450.vhd
new file mode 100644
index 0000000..4f58ff7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2450.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2450.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02450ent IS
+END c07s03b02x02p03n02i02450ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02450arch OF c07s03b02x02p03n02i02450ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM is ( ONE );
+    
+    type A_ARRAY is array ( integer range <> ) of integer;       
+    type B_ARRAY is array ( boolean range <> ) of real;
+    type C_ARRAY is array ( ENUM range <>, ENUM range <>) of bit;
+    
+    subtype A_CON is A_ARRAY ( 1 to 4 );
+    subtype B_CON is B_ARRAY ( FALSE to TRUE );
+    subtype C_CON is C_ARRAY ( ONE to ONE, ONE to ONE );
+
+    function F_A ( PAR : A_ARRAY ) return A_CON is
+    begin   return (1,2,3,4);       
+    end F_A;
+    
+    function F_B ( PAR : B_ARRAY ) return B_CON is
+    begin   return (1.0, 2.0);      
+    end F_B;
+    
+    function F_C ( PAR : C_ARRAY ) return C_CON is
+    begin   return (ONE=>(ONE=>'0'));               
+    end F_C;
+
+    variable V_A : A_CON ;
+    variable V_B : B_CON ;
+    variable V_C : C_CON ;
+
+  BEGIN
+    V_A := F_A( F_A( (1,2,others=>3) ) ); -- Failure_here        
+    -- SEMANTIC ERROR:  "others" used in aggregate which corresponds to
+    --                  an unconstrained formal parameter
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p03n02i02450 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02450arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2451.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2451.vhd
new file mode 100644
index 0000000..e9942c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2451.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2451.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02451ent IS
+END c07s03b02x02p03n02i02451ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02451arch OF c07s03b02x02p03n02i02451ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM is ( ONE );
+    
+    type A_ARRAY is array ( integer range <> ) of integer;       
+    type B_ARRAY is array ( boolean range <> ) of real;
+    type C_ARRAY is array ( ENUM range <>, ENUM range <>) of bit;
+    
+    subtype A_CON is A_ARRAY ( 1 to 4 );
+    subtype B_CON is B_ARRAY ( FALSE to TRUE );
+    subtype C_CON is C_ARRAY ( ONE to ONE, ONE to ONE );
+
+    function F_A ( PAR : A_ARRAY ) return A_CON is
+    begin   return (1,2,3,4);       
+    end F_A;
+    
+    function F_B ( PAR : B_ARRAY ) return B_CON is
+    begin   return (1.0, 2.0);      
+    end F_B;
+    
+    function F_C ( PAR : C_ARRAY ) return C_CON is
+    begin   return (ONE=>(ONE=>'0'));               
+    end F_C;
+
+    variable V_A : A_CON ;
+    variable V_B : B_CON ;
+    variable V_C : C_CON ;
+
+  BEGIN
+    V_B := F_B( F_B( (1.0,others=>2.0) ) ); -- Failure_here
+    -- SEMANTIC ERROR:  "others" used in aggregate which corresponds to
+    --                  an unconstrained formal parameter.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p03n02i02451 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02451arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc246.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc246.vhd
new file mode 100644
index 0000000..d6c47b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc246.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc246.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00246ent IS
+END c03s01b02x00p04n01i00246ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00246arch OF c03s01b02x00p04n01i00246ent IS
+  type I2 is range FALSE to TRUE;  -- Failure_here
+  -- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
+  -- MUST BE OF INTEGER TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00246 - Range constraint must be an integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00246arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2468.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2468.vhd
new file mode 100644
index 0000000..6bb9cf6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2468.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2468.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02468ent IS
+END c07s03b02x02p03n02i02468ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02468arch OF c07s03b02x02p03n02i02468ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    A_ARRAY is array ( integer range <> ) of integer;
+    SUBTYPE A_CON   IS A_ARRAY ( 1 to 4 );
+
+    function F_A ( PAR : A_CON ) return A_CON is
+    begin
+      return (1,2,3,4);
+    end F_A;
+
+    variable V_A : A_CON ;
+  BEGIN
+    V_A := F_A( A_ARRAY'(1,2,others=>3) ); -- Failure_here
+    -- SEMANTIC ERROR:  "others" used in aggregate in qualified expression
+    --      whose type mark denotes an unconstrained array type.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p03n02i02468 - Others cannot be used with an unconstrained array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02468arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2469.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2469.vhd
new file mode 100644
index 0000000..7f2a36d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2469.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2469.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02469ent IS
+END c07s03b02x02p03n02i02469ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02469arch OF c07s03b02x02p03n02i02469ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type B_ARRAY is array ( boolean range <> ) of real;
+    
+    subtype B_CON is B_ARRAY ( FALSE to TRUE );
+
+    function F_B ( PAR : B_CON ) return B_CON is
+    begin
+      return (1.0,2.0);
+    end F_B;
+    
+    variable V_B : B_CON ;
+  BEGIN
+    V_B := F_B( B_ARRAY'(1.0,others=>2.0) );  -- Failure_here
+    -- SEMANTIC ERROR:  "others" used in aggregate in qualified expression
+    --      whose type mark denotes an unconstrained array type.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p03n02i02469 - Others cannot be used with an unconstrained array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02469arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc247.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc247.vhd
new file mode 100644
index 0000000..1b2ae5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc247.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc247.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00247ent IS
+END c03s01b02x00p04n01i00247ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00247arch OF c03s01b02x00p04n01i00247ent IS
+  type I3 is range "0" to "9";  -- Failure_here
+  -- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
+  -- MUST BE OF INTEGER TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00247 - Range constraint must be an integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00247arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2470.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2470.vhd
new file mode 100644
index 0000000..754ee7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2470.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2470.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p03n02i02470ent IS
+END c07s03b02x02p03n02i02470ent;
+
+ARCHITECTURE c07s03b02x02p03n02i02470arch OF c07s03b02x02p03n02i02470ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type    ENUM    is ( ONE );
+    type    C_ARRAY is array ( ENUM range <>, ENUM range <> ) of bit;
+    subtype C_CON    is C_ARRAY ( ONE to ONE, ONE to ONE );
+
+    function F_C ( PAR : C_CON ) return C_CON is
+    begin
+      return (ONE=>(ONE=>'0'));
+    end F_C;
+
+    variable V_C : C_CON ;
+  BEGIN
+    V_C := F_C( C_ARRAY'(ONE=>('1',others=>'0')) );  -- Failure_here
+    -- SEMANTIC ERROR:  "others" used in aggregate in qualified expression
+    --      whose type mark denotes an unconstrained array type.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p03n02i02470 - Others cannot be used with an unconstrained array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p03n02i02470arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2473.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2473.vhd
new file mode 100644
index 0000000..a0c797a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2473.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2473.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n02i02473ent IS
+END c07s03b02x02p13n02i02473ent;
+
+ARCHITECTURE c07s03b02x02p13n02i02473arch OF c07s03b02x02p13n02i02473ent IS
+  type    UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
+  subtype CA_UP   is UNCONSTRAINED_ARRAY ( 1 to 10 );
+  subtype CA_DOWN is UNCONSTRAINED_ARRAY (10 downto 1);
+  function F_bad (C : CA_UP) return CA_DOWN is
+  begin
+    return CA_DOWN'((1 to 15 => 'B'));   -- failure_here
+  end F_bad;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    F_bad("niuniuniun");
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p13n02i02473 - The range of the subtype of the aggregate array is not the same as that of the index subtype of the base subtype of the aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n02i02473arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2476.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2476.vhd
new file mode 100644
index 0000000..7204d47
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2476.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2476.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b02x02p13n04i02476ent IS
+END c07s03b02x02p13n04i02476ent;
+
+ARCHITECTURE c07s03b02x02p13n04i02476arch OF c07s03b02x02p13n04i02476ent IS
+  type    index_values is (one, two, three);
+  type    ucarr is array (index_values range <>) of Boolean;      
+  subtype carr  is ucarr (index_values'low to index_values'high);
+  function f2 (i : integer) return carr is
+  begin
+    return (True, True, TRUE, False);  -- Failure_here      
+    -- SEMANTIC ERROR : Last element association specifies
+    --  index which is out of bounds for the array.
+  end f2;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    f2(1);
+    assert FALSE 
+      report "***FAILED TEST: c07s03b02x02p13n04i02476 - Indices are out of bounds for the array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b02x02p13n04i02476arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc248.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc248.vhd
new file mode 100644
index 0000000..47e23cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc248.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc248.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00248ent IS
+END c03s01b02x00p04n01i00248ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00248arch OF c03s01b02x00p04n01i00248ent IS
+  type I4 is range "000" to "999";  -- Failure_here
+  -- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
+  -- MUST BE OF INTEGER TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00248 - Range constraint must be an integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00248arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2482.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2482.vhd
new file mode 100644
index 0000000..2043714
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2482.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2482.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s03b03x00p01n01i02482pkg is
+  function uno return natural;
+  constant a_bit : bit_vector (uno to uno) := ( uno => '1' );
+end c07s03b03x00p01n01i02482pkg;
+
+package body c07s03b03x00p01n01i02482pkg is
+  function uno return natural is
+  begin
+    return 1;
+  end uno;
+end c07s03b03x00p01n01i02482pkg;
+
+ENTITY c07s03b03x00p01n01i02482ent IS
+END c07s03b03x00p01n01i02482ent;
+
+ARCHITECTURE c07s03b03x00p01n01i02482arch OF c07s03b03x00p01n01i02482ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    uno;
+    assert FALSE
+      report "***FAILED TEST: c07s03b03x00p01n01i02482 - Function body is not defined."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p01n01i02482arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2488.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2488.vhd
new file mode 100644
index 0000000..8ec1f88
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2488.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2488.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p02n01i02488ent IS
+END c07s03b03x00p02n01i02488ent;
+
+ARCHITECTURE c07s03b03x00p02n01i02488arch OF c07s03b03x00p02n01i02488ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function func1    (a2 : integer) return integer is
+    begin
+      return 5;
+    end func1;
+    variable x: integer := 1;
+    variable y: integer;
+  BEGIN
+    y := func1 ();
+    assert FALSE 
+      report "***FAILED TEST: c07s03b03x00p02n01i02488 - Missing parameter list." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p02n01i02488arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2489.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2489.vhd
new file mode 100644
index 0000000..c44649e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2489.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2489.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n01i02489ent IS
+END c07s03b03x00p04n01i02489ent;
+
+ARCHITECTURE c07s03b03x00p04n01i02489arch OF c07s03b03x00p04n01i02489ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x:integer; y:boolean) return boolean is
+    begin
+      if y then
+        return true;
+      else
+        return false;
+      end if;
+    end;
+    variable p: integer := 3;
+    variable q: boolean := true;
+    variable r: boolean;
+  BEGIN
+    r := check (p);
+    assert FALSE 
+      report "***FAILED TEST: c07s03b03x00p04n01i02489 - Each formal parameter of a function should have exactly one actual parameter associated with it in a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n01i02489arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc249.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc249.vhd
new file mode 100644
index 0000000..31e2a60
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc249.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc249.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00249ent IS
+END c03s01b02x00p04n01i00249ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00249arch OF c03s01b02x00p04n01i00249ent IS
+  type I5 is range B"000" to B"111";  -- Failure_here
+  -- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
+  -- MUST BE OF INTEGER TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00249 - Range constraint must be an integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00249arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2490.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2490.vhd
new file mode 100644
index 0000000..56b8eff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2490.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2490.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n01i02490ent IS
+END c07s03b03x00p04n01i02490ent;
+
+ARCHITECTURE c07s03b03x00p04n01i02490arch OF c07s03b03x00p04n01i02490ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x:integer; y:boolean; z:real) return boolean is
+    begin
+      if y then
+        return true;
+      end if;
+      return false;
+    end;
+    variable p : integer := 3;
+    variable q : boolean := true;
+    variable s : boolean;
+    variable r : real;
+    variable r1: real;
+  BEGIN
+    s := check (p, q, r, r1);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s03b03x00p04n01i02490 - Each formal parameter of a function should have exactly one actual parameter associated with it in a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n01i02490arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2491.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2491.vhd
new file mode 100644
index 0000000..fea955e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2491.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2491.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n01i02491ent IS
+END c07s03b03x00p04n01i02491ent;
+
+ARCHITECTURE c07s03b03x00p04n01i02491arch OF c07s03b03x00p04n01i02491ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function F_REAL ( A,B,C : REAL; D : REAL := 4.0 ) return REAL is
+    begin
+      return A + B + C + D;
+    end F_REAL;
+    subtype R is REAL range REAL'LEFT to F_REAL( 1.0, 2.0, 3.0, B=>4.0 );-- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b03x00p04n01i02491 - Each formal parameter of a function should have exactly one actual parameter associated with it in a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n01i02491arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2492.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2492.vhd
new file mode 100644
index 0000000..2f50940
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2492.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2492.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n01i02492ent IS
+END c07s03b03x00p04n01i02492ent;
+
+ARCHITECTURE c07s03b03x00p04n01i02492arch OF c07s03b03x00p04n01i02492ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type SNACK is
+      range 1 to 1e8
+      units
+        fn;             -- figanewton
+        bf = 12 fn;     -- boxafiganewton
+      end units;
+    function F_SNACK (      A : REAL := 1.0;
+                            B : INTEGER;
+                            C : SNACK ) return SNACK is
+    begin
+      return C;
+    end F_SNACK;
+  BEGIN
+    PT <= F_SNACK(B=>5);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s03b03x00p04n01i02492 - Each formal parameter of a function should have exactly one actual parameter associated with it in a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n01i02492arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2493.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2493.vhd
new file mode 100644
index 0000000..19ca155
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2493.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2493.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n01i02493ent IS
+END c07s03b03x00p04n01i02493ent;
+
+ARCHITECTURE c07s03b03x00p04n01i02493arch OF c07s03b03x00p04n01i02493ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type     index_values is (one, two, three);
+    type     ucarr is array  (index_values range <>) of Boolean;
+    subtype  carr is ucarr   (index_values'low to index_values'high);
+    function f1 (i : integer) return carr is
+    begin
+      return (index_values'LOW => TRUE, others => False);
+    end f1;
+    variable V1 : CARR;
+    variable I1 : Integer := 10;
+  BEGIN
+    V1 := f1(I1,10) ;        -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s03b03x00p04n01i02493 - Each formal parameter of a function should have exactly one actual parameter associated with it in a function call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n01i02493arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2497.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2497.vhd
new file mode 100644
index 0000000..07a593b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2497.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2497.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p04n02i02497ent IS
+END c07s03b03x00p04n02i02497ent;
+
+ARCHITECTURE c07s03b03x00p04n02i02497arch OF c07s03b03x00p04n02i02497ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function func1 (a1 : real; b1 : integer:= 12) return integer is 
+    begin
+      return 5;
+    end;
+    variable x: real := 1.2;
+    variable y: integer ;
+  BEGIN
+    y := func1 (y,x);
+    assert FALSE 
+      report "***FAILED TEST: c07s03b03x00p04n02i02497 - The actual parameter can be specified explicitly by an association element in the association list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p04n02i02497arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2498.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2498.vhd
new file mode 100644
index 0000000..26eaa31
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2498.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2498.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b03x00p05n01i02498ent IS
+END c07s03b03x00p05n01i02498ent;
+
+ARCHITECTURE c07s03b03x00p05n01i02498arch OF c07s03b03x00p05n01i02498ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function check (x:integer; y:boolean; z:real) return boolean is
+    begin
+      if y then
+        return true;
+      else return false;
+      end if;
+    end;
+    variable p: integer := 3;
+    variable q: boolean := true;
+    variable r: integer;            -- should be real.
+    variable s: boolean;
+  BEGIN
+    s := check (p, q, r);  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c07s03b03x00p05n01i02498 - Actual parameter must belong to the subtype of the associated formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b03x00p05n01i02498arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc250.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc250.vhd
new file mode 100644
index 0000000..53e3b9d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc250.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc250.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00250ent IS
+END c03s01b02x00p04n01i00250ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00250arch OF c03s01b02x00p04n01i00250ent IS
+  type I6 is range TWO to THREE;  -- Failure_here
+  -- SEMANTIC ERROR: RANGE CONSTRAINT IN INTEGER TYPE DEFINITION
+  -- MUST BE OF INTEGER TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00250 - Range constraint must be an integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00250arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2503.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2503.vhd
new file mode 100644
index 0000000..bca0a3b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2503.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2503.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p02n01i02503ent IS
+END c07s03b04x00p02n01i02503ent;
+
+ARCHITECTURE c07s03b04x00p02n01i02503arch OF c07s03b04x00p02n01i02503ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        x : bit;
+        y : integer;
+        z : boolean;
+      end record;
+    variable S :rec_type;
+  BEGIN
+    S   := rec_type(bit'('0'), 1, true);
+    assert FALSE 
+      report "***FAILED TEST: c07s03b04x00p02n01i02503 - Missing apostrophe." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p02n01i02503arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2504.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2504.vhd
new file mode 100644
index 0000000..7b41159
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2504.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2504.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p03n01i02504ent IS
+END c07s03b04x00p03n01i02504ent;
+
+ARCHITECTURE c07s03b04x00p03n01i02504arch OF c07s03b04x00p03n01i02504ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type bit_vctor is array (bit'('0') to bit'('C') ) of integer;
+    -- Failure_here
+    -- 'C' is not of type bit.
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b04x00p03n01i02504 - Operand must have the same type as the base type of the type mark."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p03n01i02504arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2505.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2505.vhd
new file mode 100644
index 0000000..e4bf53d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2505.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2505.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p03n01i02505ent IS
+END c07s03b04x00p03n01i02505ent;
+
+ARCHITECTURE c07s03b04x00p03n01i02505arch OF c07s03b04x00p03n01i02505ent IS
+  signal OUT_BIT : bit;
+BEGIN
+  TESTING: PROCESS
+    variable G_BOOL : boolean;
+  BEGIN
+    OUT_BIT <= bit'(G_BOOL); -- Failure_here
+    -- SEMANTIC ERROR:  type of expression does not match type mark.
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b04x00p03n01i02505 - Expression type does not match type mark." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p03n01i02505arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2507.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2507.vhd
new file mode 100644
index 0000000..048684e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2507.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2507.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p03n01i02507ent IS
+END c07s03b04x00p03n01i02507ent;
+
+ARCHITECTURE c07s03b04x00p03n01i02507arch OF c07s03b04x00p03n01i02507ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function F1 ( PARAM : bit ) return boolean is
+    begin
+      return boolean'(PARAM); -- Failure_here
+      -- SEMANTIC ERROR:  type of expression does not match type mark.
+    end F1;
+    variable k : boolean;
+  BEGIN
+    k := F1('1');
+    assert FALSE 
+      report "***FAILED TEST: c07s03b04x00p03n01i02507 - Expression type does not match type mark." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p03n01i02507arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2508.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2508.vhd
new file mode 100644
index 0000000..64bd4de
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2508.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2508.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p03n01i02508ent IS
+END c07s03b04x00p03n01i02508ent;
+
+ARCHITECTURE c07s03b04x00p03n01i02508arch OF c07s03b04x00p03n01i02508ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A_REC is record    
+                    E : integer;    
+                  end record;
+    type B_REC is record    
+                    E : integer;    
+                  end record;
+    function F2 ( PARAM : A_REC ) return B_REC is
+    begin
+      return B_REC'(PARAM); -- Failure_here
+      -- SEMANTIC ERROR:  type of expression does not match type mark.
+    end F2;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b04x00p03n01i02508 - Expression type does not match type mark." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p03n01i02508arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2509.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2509.vhd
new file mode 100644
index 0000000..846b9b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2509.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2509.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b04x00p03n01i02509ent IS
+  generic ( G_BOOL : boolean ) ;
+  port    ( OUT_BIT : out bit ) ;
+  ENTITY c07s03b04x00p03n01i02509ent IS
+
+  BEGIN
+    TESTING: PROCESS
+      OUT_BIT <= bit'(G_BOOL); -- Failure_here
+      -- SEMANTIC ERROR:  type of expression does not match type mark.
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c07s03b04x00p03n01i02509 - Expression type does not match type mark." 
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c07s03b04x00p03n01i02509arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2510.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2510.vhd
new file mode 100644
index 0000000..b2a899b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2510.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2510.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c07s03b04x00p03n01i02510pkg is
+  type A_REC is record    
+                  E : integer;    
+                end record;
+  type B_REC is record    
+                  E : integer;    
+                end record;
+end c07s03b04x00p03n01i02510pkg;
+
+use work.c07s03b04x00p03n01i02510pkg.all;
+
+ENTITY c07s03b04x00p03n01i02510ent IS
+  generic ( G_BREC : B_REC ) ;
+  port    ( OUT_A  : out A_REC ) ;
+END c07s03b04x00p03n01i02510ent;
+
+ARCHITECTURE c07s03b04x00p03n01i02510arch OF c07s03b04x00p03n01i02510ent IS
+
+BEGIN
+  TESTING: PROCESS
+    OUT_A <= A_REC'(G_BREC); -- Failure_here
+    -- SEMANTIC ERROR:  type of expression does not match type mark.
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b04x00p03n01i02510 - Expression type does not match type mark." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b04x00p03n01i02510arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2512.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2512.vhd
new file mode 100644
index 0000000..7ec6e49
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2512.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2512.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p02n01i02512ent IS
+END c07s03b05x00p02n01i02512ent;
+
+ARCHITECTURE c07s03b05x00p02n01i02512arch OF c07s03b05x00p02n01i02512ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Apples  is range 0 to 75;
+    type Oranges is range 0 to 75;
+    variable Macintosh : Apples;
+    variable Seville, valencia : Oranges;
+  BEGIN
+    Macintosh := Apples (Seville)  ;
+    Seville  :=  Oranges () ;    -- Failure_here
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p02n01i02512 - Missing expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p02n01i02512arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2514.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2514.vhd
new file mode 100644
index 0000000..d7beb41
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2514.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2514.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n02i02514ent IS
+END c07s03b05x00p03n02i02514ent;
+
+ARCHITECTURE c07s03b05x00p03n02i02514arch OF c07s03b05x00p03n02i02514ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Grapes  is (Sweet, Sour);
+    type Oranges is (Sweet, Bitter);
+    variable Green : Grapes;
+    variable Seville, valencia : Oranges;
+  BEGIN
+    Green := Grapes (Sweet);  -- Failure_here
+                                  -- Sweet is not determinable
+                                      -- independent of the context.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p03n02i02514 - Type of operand must be determinable independent of the context."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n02i02514arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2516.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2516.vhd
new file mode 100644
index 0000000..f3b39f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2516.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2516.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n03i02516ent IS
+END c07s03b05x00p03n03i02516ent;
+
+ARCHITECTURE c07s03b05x00p03n03i02516arch OF c07s03b05x00p03n03i02516ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Grapes  is (Sweet, Sour);
+    type Oranges is (Sweet, Bitter);
+    variable Green : Grapes;
+    variable Seville, valencia : Oranges;
+  BEGIN
+    Green := Grapes (null);  -- Failure_here
+                                 -- null is not allowed.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p03n03i02516 - Operand cannot be the literal null, an alloator, an aggregate, or a string literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n03i02516arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2517.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2517.vhd
new file mode 100644
index 0000000..f491560
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2517.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2517.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n03i02517ent IS
+END c07s03b05x00p03n03i02517ent;
+
+ARCHITECTURE c07s03b05x00p03n03i02517arch OF c07s03b05x00p03n03i02517ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype  Grapes  is STRING;
+    constant Green : Grapes := Grapes ("CLSI");  -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p03n03i02517 - Operand cannot be the literal null, an alloator, an aggregate, or a string literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n03i02517arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2518.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2518.vhd
new file mode 100644
index 0000000..67cc650
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2518.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2518.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n03i02518ent IS
+END c07s03b05x00p03n03i02518ent;
+
+ARCHITECTURE c07s03b05x00p03n03i02518arch OF c07s03b05x00p03n03i02518ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Grapes is array (1 to 4) of real;
+    variable Green : Grapes;
+  BEGIN
+    Green := Grapes (1.1, 1.2, 1.3, 1.4);
+                                        -- Failure_here
+                                        -- Aggregate is not allowed.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p03n03i02518 - Operand cannot be the literal null, an alloator, an aggregate, or a string literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n03i02518arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc252.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc252.vhd
new file mode 100644
index 0000000..45a101e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc252.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc252.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00252ent IS
+END c03s01b02x00p04n01i00252ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00252arch OF c03s01b02x00p04n01i00252ent IS
+-- Failure_here: 1.0E-8 is an error, because it is not an integer
+  type time is range 0 to 1.0E-8 units
+                                   fs;
+                                 end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00252 - Bound not of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00252arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2521.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2521.vhd
new file mode 100644
index 0000000..c0f86b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2521.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2521.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p03n04i02521ent IS
+END c07s03b05x00p03n04i02521ent;
+
+ARCHITECTURE c07s03b05x00p03n04i02521arch OF c07s03b05x00p03n04i02521ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Apples  is range 0 to 75;
+    type Oranges is range 0 to 75;
+    variable Macintosh : Apples;
+    variable Seville, valencia : Oranges;
+  BEGIN
+    Macintosh := Apples (Seville)  ;
+    Seville  :=  Oranges (Macintosh,10) ;    -- Failure_here
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p03n04i02521 - Multiple expression are not allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p03n04i02521arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2523.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2523.vhd
new file mode 100644
index 0000000..22d6409
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2523.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2523.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p04n01i02523ent IS
+END c07s03b05x00p04n01i02523ent;
+
+ARCHITECTURE c07s03b05x00p04n01i02523arch OF c07s03b05x00p04n01i02523ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Apples  is range 0 to 75;
+    type Oranges is range 0 to 75;
+    variable Macintosh : Apples;
+    variable Seville   : Oranges;
+  BEGIN
+    Macintosh := Apples (Seville)  ;
+    Seville  :=  Oranges (100) ;    
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p04n01i02523 - Value does not belong to the subtype indicated by the type mark." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p04n01i02523arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2526.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2526.vhd
new file mode 100644
index 0000000..3cc8633
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2526.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2526.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p06n03i02526ent IS
+END c07s03b05x00p06n03i02526ent;
+
+ARCHITECTURE c07s03b05x00p06n03i02526arch OF c07s03b05x00p06n03i02526ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type Apples  is range 0 to 75;
+    type Oranges is range 0 to 75;
+    type MVL is ('0','1','Z') ;
+    variable Macintosh : Apples;
+    variable Seville, valencia : Oranges;
+    variable V1 : MVL;
+  BEGIN
+    Macintosh := Apples (Seville)  ;
+    V1 :=  Oranges (76) ;    -- Failure_here
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p06n03i02526 - Target type is not an Integer or floating point type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p06n03i02526arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc253.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc253.vhd
new file mode 100644
index 0000000..5ef725f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc253.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc253.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p04n01i00253ent IS
+  generic (constant gencons    : integer);
+  port    (pout          : out integer);
+  type    tygee is range gencons to 1000;
+END c03s01b02x00p04n01i00253ent;
+
+ARCHITECTURE c03s01b02x00p04n01i00253arch OF c03s01b02x00p04n01i00253ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    pout <= 1;
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p04n01i00253 - Bound of a range constraint used in an integer definition must be locally static."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p04n01i00253arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2534.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2534.vhd
new file mode 100644
index 0000000..80e4322
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2534.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2534.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p13n02i02534ent IS
+END c07s03b05x00p13n02i02534ent;
+
+ARCHITECTURE c07s03b05x00p13n02i02534arch OF c07s03b05x00p13n02i02534ent IS
+  type    Memory is array (Integer range <>) of Integer;
+  subtype T1     is Memory (1 to 6) ;
+  subtype T2     is Memory (2 to 4) ;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T1 ;
+    variable V2 : T2 := (2,3,6) ;
+  BEGIN
+    V1 := Memory (V2) ;    -- Failure_here
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p13n02i02534 - Bounds of the result are different from the index subtype of the target."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p13n02i02534arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2536.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2536.vhd
new file mode 100644
index 0000000..9267559
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2536.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2536.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p13n03i02536ent IS
+END c07s03b05x00p13n03i02536ent;
+
+ARCHITECTURE c07s03b05x00p13n03i02536arch OF c07s03b05x00p13n03i02536ent IS
+  type Memory is array (Integer range <>) of Integer;
+  subtype T1 is Memory (1 to 6) ;
+  subtype T2 is Memory (1 to 6) ;
+  subtype T3 is Memory (2 to 4) ;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T1 ;
+    variable V2 : T3 := (2,3,6) ;
+  BEGIN
+    V1 := T2 (V2) ;    -- Failure_here
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p13n03i02536 - A check is made that for each element of the operand there is a matching element of the target subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p13n03i02536arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2537.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2537.vhd
new file mode 100644
index 0000000..13ca09b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2537.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2537.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02537ent IS
+END c07s03b05x00p14n01i02537ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02537arch OF c07s03b05x00p14n01i02537ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type X1 is  range 1.0 to 100.0 ;
+    type X2 is  range 1.0 to 100.0 ;
+    type I1 is  range 1   to 1000000;
+    type I2 is  range 1   to 10000000 ;
+    variable RE1 : X1 ;
+    variable RE2 : X2 ;
+    variable IN1 : I1 ;
+    variable IN2 : I2 ;
+  BEGIN
+    RE1 := RE2 + RE2;  -- Failure_here
+    -- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
+    -- UNIVERSAL INTEGER OR UNIVERSAL REAL.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p14n01i02537 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02537arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2538.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2538.vhd
new file mode 100644
index 0000000..f5bddd1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2538.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2538.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02538ent IS
+END c07s03b05x00p14n01i02538ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02538arch OF c07s03b05x00p14n01i02538ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type X1 is  range 1.0 to 100.0 ;
+    type X2 is  range 1.0 to 100.0 ;
+    type I1 is  range 1   to 1000000;
+    type I2 is  range 1   to 10000000 ;
+    variable RE1 : X1 ;
+    variable RE2 : X2 ;
+    variable IN1 : I1 ;
+    variable IN2 : I2 ;
+  BEGIN
+    IN1 := IN2 + IN2;  -- Failure_here
+    -- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
+    -- UNIVERSAL INTEGER OR UNIVERSAL REAL.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p14n01i02538 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02538arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2539.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2539.vhd
new file mode 100644
index 0000000..6b71e04
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2539.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2539.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02539ent IS
+END c07s03b05x00p14n01i02539ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02539arch OF c07s03b05x00p14n01i02539ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type X1 is  range 1.0 to 100.0 ;
+    type X2 is  range 1.0 to 100.0 ;
+    type I1 is  range 1   to 1000000;
+    type I2 is  range 1   to 10000000 ;
+    variable RE1 : X1 ;
+    variable RE2 : X2 ;
+    variable IN1 : I1 ;
+    variable IN2 : I2 ;
+  BEGIN
+    IN1 := IN2 + IN2;  -- Failure_here
+    -- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
+    -- UNIVERSAL INTEGER OR UNIVERSAL REAL.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p14n01i02539 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02539arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2540.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2540.vhd
new file mode 100644
index 0000000..eb0a32d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2540.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2540.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02540ent IS
+END c07s03b05x00p14n01i02540ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02540arch OF c07s03b05x00p14n01i02540ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type X1 is  range 1.0 to 100.0 ;
+    type X2 is  range 1.0 to 100.0 ;
+    type I1 is  range 1   to 1000000;
+    type I2 is  range 1   to 10000000 ;
+    variable RE1 : X1 ;
+    variable RE2 : X2 ;
+    variable IN1 : I1 ;
+    variable IN2 : I2 ;
+  BEGIN
+    RE2 := RE2 * RE1 ;  -- Failure_here
+    -- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
+    -- UNIVERSAL INTEGER OR UNIVERSAL REAL.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p14n01i02540 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02540arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2541.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2541.vhd
new file mode 100644
index 0000000..fad13e2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2541.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2541.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02541ent IS
+END c07s03b05x00p14n01i02541ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02541arch OF c07s03b05x00p14n01i02541ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type X1 is  range 1.0 to 100.0 ;
+    type X2 is  range 1.0 to 100.0 ;
+    type I1 is  range 1   to 1000000;
+    type I2 is  range 1   to 10000000 ;
+    variable RE1 : X1 ;
+    variable RE2 : X2 ;
+    variable IN1 : I1 ;
+    variable IN2 : I2 ;
+  BEGIN
+    RE2 := RE2 * RE1 ;  -- Failure_here
+    -- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
+    -- UNIVERSAL INTEGER OR UNIVERSAL REAL.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p14n01i02541 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02541arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2542.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2542.vhd
new file mode 100644
index 0000000..5000b95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2542.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2542.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02542ent IS
+END c07s03b05x00p14n01i02542ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02542arch OF c07s03b05x00p14n01i02542ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type X1 is  range 1.0 to 100.0 ;
+    type X2 is  range 1.0 to 100.0 ;
+    type I1 is  range 1   to 1000000;
+    type I2 is  range 1   to 10000000 ;
+    variable RE1 : X1 ;
+    variable RE2 : X2 ;
+    variable IN1 : I1 ;
+    variable IN2 : I2 ;
+  BEGIN
+    RE2 := RE1/RE2;  -- Failure_here
+    -- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
+    -- UNIVERSAL INTEGER OR UNIVERSAL REAL.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p14n01i02542 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02542arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2543.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2543.vhd
new file mode 100644
index 0000000..71cc532
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2543.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2543.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02543ent IS
+END c07s03b05x00p14n01i02543ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02543arch OF c07s03b05x00p14n01i02543ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type X1 is  range 1.0 to 100.0 ;
+    type X2 is  range 1.0 to 100.0 ;
+    type I1 is  range 1   to 1000000;
+    type I2 is  range 1   to 10000000 ;
+    variable RE1 : X1 ;
+    variable RE2 : X2 ;
+    variable IN1 : I1 ;
+    variable IN2 : I2 ;
+  BEGIN
+    IN2 := IN1/IN2;  -- Failure_here
+    -- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
+    -- UNIVERSAL INTEGER OR UNIVERSAL REAL.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p14n01i02543 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02543arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2544.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2544.vhd
new file mode 100644
index 0000000..0ec4c20
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2544.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2544.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02544ent IS
+END c07s03b05x00p14n01i02544ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02544arch OF c07s03b05x00p14n01i02544ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type X1 is  range 1.0 to 100.0 ;
+    type X2 is  range 1.0 to 100.0 ;
+    type I1 is  range 1   to 1000000;
+    type I2 is  range 1   to 10000000 ;
+    variable RE1 : X1 ;
+    variable RE2 : X2 ;
+    variable IN1 : I1 ;
+    variable IN2 : I2 ;
+  BEGIN
+    IN2 := IN2 - IN1;  -- Failure_here
+    -- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
+    -- UNIVERSAL INTEGER OR UNIVERSAL REAL.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p14n01i02544 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02544arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2545.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2545.vhd
new file mode 100644
index 0000000..851bc0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2545.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2545.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p14n01i02545ent IS
+END c07s03b05x00p14n01i02545ent;
+
+ARCHITECTURE c07s03b05x00p14n01i02545arch OF c07s03b05x00p14n01i02545ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type X1 is  range 1.0 to 100.0 ;
+    type X2 is  range 1.0 to 100.0 ;
+    type I1 is  range 1   to 1000000;
+    type I2 is  range 1   to 10000000 ;
+    variable RE1 : X1 ;
+    variable RE2 : X2 ;
+    variable IN1 : I1 ;
+    variable IN2 : I2 ;
+  BEGIN
+    RE1 := RE2 - RE1;  -- Failure_here
+    -- ERROR: TYPE CONVERSION CANNOT OCCUR ON AN OPERAND OF ANY TYPE BUT
+    -- UNIVERSAL INTEGER OR UNIVERSAL REAL.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p14n01i02545 - Type conversion can only occur on operand of universal real or integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p14n01i02545arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2548.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2548.vhd
new file mode 100644
index 0000000..a41393e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2548.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2548.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p08n01i02548ent IS
+END c07s03b05x00p08n01i02548ent;
+
+ARCHITECTURE c07s03b05x00p08n01i02548arch OF c07s03b05x00p08n01i02548ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type century is  array (1 to 1000) of real ;
+    type millenia is array (1 to 100 ) of real ;
+    variable hundreds : century  ;
+    variable thousand : millenia ;
+  BEGIN
+    thousand := millenia (hundreds);
+    -- Failure_here
+    -- dimensionality not same.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p08n01i02548 - Operand and the target type should have the same dimensionality in a type conversion."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p08n01i02548arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2549.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2549.vhd
new file mode 100644
index 0000000..41bac50
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2549.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2549.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b05x00p07n01i02549ent IS
+END c07s03b05x00p07n01i02549ent;
+
+ARCHITECTURE c07s03b05x00p07n01i02549arch OF c07s03b05x00p07n01i02549ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type century is  array (1 to 2) of real ;
+    type millenia is array (bit'('0') to bit'('1') ) of real ;
+    variable hundreds : century  ;
+    variable thousand : millenia ;
+  BEGIN
+    thousand := millenia (hundreds);
+    -- Failure_here
+    -- index types not same.
+    assert FALSE 
+      report "***FAILED TEST: c07s03b05x00p07n01i02549 - Operand and the target type should have the same index type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b05x00p07n01i02549arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2552.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2552.vhd
new file mode 100644
index 0000000..1c2e27b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2552.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2552.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p02n01i02552ent IS
+END c07s03b06x00p02n01i02552ent;
+
+ARCHITECTURE c07s03b06x00p02n01i02552arch OF c07s03b06x00p02n01i02552ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CELL;
+    type LINK is access CELL;
+    type CELL is
+      record
+        VALUE : Integer;
+        SUCC  : LINK;
+        PRED  : LINK;
+      end record;
+    variable HEAD : LINK :=  CELL'(0,null,null);   -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b06x00p02n01i02552 - Missing keyword 'new'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p02n01i02552arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2553.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2553.vhd
new file mode 100644
index 0000000..2e3075f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2553.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2553.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p02n01i02553ent IS
+END c07s03b06x00p02n01i02553ent;
+
+ARCHITECTURE c07s03b06x00p02n01i02553arch OF c07s03b06x00p02n01i02553ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable b : bit;
+  BEGIN
+    b := new bit;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b06x00p02n01i02553 - Not an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p02n01i02553arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2554.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2554.vhd
new file mode 100644
index 0000000..e0dac6b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2554.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2554.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p02n01i02554ent IS
+END c07s03b06x00p02n01i02554ent;
+
+ARCHITECTURE c07s03b06x00p02n01i02554arch OF c07s03b06x00p02n01i02554ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable b : bit_vector(0 to 31);
+  BEGIN
+    b := new bit_vector;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b06x00p02n01i02554 - Not an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p02n01i02554arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2555.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2555.vhd
new file mode 100644
index 0000000..f4359c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2555.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2555.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p02n01i02555ent IS
+END c07s03b06x00p02n01i02555ent;
+
+ARCHITECTURE c07s03b06x00p02n01i02555arch OF c07s03b06x00p02n01i02555ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable b : integer;
+  BEGIN
+    b := new integer;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b06x00p02n01i02555 - Not an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p02n01i02555arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2556.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2556.vhd
new file mode 100644
index 0000000..e3e4343
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2556.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2556.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p02n01i02556ent IS
+END c07s03b06x00p02n01i02556ent;
+
+ARCHITECTURE c07s03b06x00p02n01i02556arch OF c07s03b06x00p02n01i02556ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable b : real;
+  BEGIN
+    b := new real;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b06x00p02n01i02556 - Not an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p02n01i02556arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2557.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2557.vhd
new file mode 100644
index 0000000..6c3d17f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2557.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2557.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p02n01i02557ent IS
+END c07s03b06x00p02n01i02557ent;
+
+ARCHITECTURE c07s03b06x00p02n01i02557arch OF c07s03b06x00p02n01i02557ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable b : boolean;
+  BEGIN
+    b := new boolean;
+    assert FALSE 
+      report "***FAILED TEST: c07s03b06x00p02n01i02557 - Not an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p02n01i02557arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc256.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc256.vhd
new file mode 100644
index 0000000..4a0d38c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc256.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc256.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p08n01i00256ent IS
+END c03s01b02x00p08n01i00256ent;
+
+ARCHITECTURE c03s01b02x00p08n01i00256arch OF c03s01b02x00p08n01i00256ent IS
+  -- Failure_here: 1E10 is larger than integer range
+  type time is range 0 to 1E10 
+    units
+      fs;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p08n01i00256 - Integer declared outside bounds."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p08n01i00256arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2560.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2560.vhd
new file mode 100644
index 0000000..6ccb3e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2560.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2560.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p05n02i02560ent IS
+END c07s03b06x00p05n02i02560ent;
+
+ARCHITECTURE c07s03b06x00p05n02i02560arch OF c07s03b06x00p05n02i02560ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type CELL;
+    type LINK is access CELL;
+    type CELL is
+      record
+        VALUE : Bit;
+        SUCC  : Bit;
+      end record;
+    type T1 is access BIT_VECTOR ;
+    variable HEAD : LINK :=  new CELL'('1','0') ;
+    variable V2   : T1   := new BIT_VECTOR ;     --- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b06x00p05n02i02560 - Subtype indication cannot be an unconstrained array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p05n02i02560arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2561.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2561.vhd
new file mode 100644
index 0000000..e873f2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2561.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2561.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s03b06x00p05n03i02561ent IS
+END c07s03b06x00p05n03i02561ent;
+
+ARCHITECTURE c07s03b06x00p05n03i02561arch OF c07s03b06x00p05n03i02561ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ONETWO is range 1 to 2;
+    type more_bad_sig_drivers is array (positive range <>) of ONETWO;
+    function F2( candidate : more_bad_sig_drivers  )  return ONETWO is
+      variable R : ONETWO;
+    begin
+      return R;
+    end F2;
+    type LINK is access ONETWO;
+    variable HEAD : LINK :=  new F2 ONETWO;      --- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c07s03b06x00p05n03i02561 - Subtype indication should not include a resolution function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s03b06x00p05n03i02561arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc257.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc257.vhd
new file mode 100644
index 0000000..a1a06b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc257.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc257.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p08n01i00257ent IS
+END c03s01b02x00p08n01i00257ent;
+
+ARCHITECTURE c03s01b02x00p08n01i00257arch OF c03s01b02x00p08n01i00257ent IS
+  -- The statement really creates two errors, one for underflow and one for overflow
+  subtype itest is integer range -2147483648 to 2147483648;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p08n01i00257 - Integer declared outside bounds."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p08n01i00257arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2571.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2571.vhd
new file mode 100644
index 0000000..06b4422
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2571.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2571.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s05b00x00p16n02i02571ent IS
+END c07s05b00x00p16n02i02571ent;
+
+ARCHITECTURE c07s05b00x00p16n02i02571arch OF c07s05b00x00p16n02i02571ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(2E26 = (2E13*1E13))
+      report "***PASSED TEST: c07s05b00x00p16n02i02571"
+      severity NOTE;
+    assert (2E26 = (2E13*1E13))
+      report "***FAILED TEST: c07s05b00x00p16n02i02571 - The values of the operands and the result lie within the range of the integer type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s05b00x00p16n02i02571arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2572.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2572.vhd
new file mode 100644
index 0000000..a557e9c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2572.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2572.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s05b00x00p16n03i02572ent IS
+END c07s05b00x00p16n03i02572ent;
+
+ARCHITECTURE c07s05b00x00p16n03i02572arch OF c07s05b00x00p16n03i02572ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert NOT(2.12E80 = (1.06E40*2.0E40))
+      report "***PASSED TEST: c07s05b00x00p16n03i02572"
+      severity NOTE;
+    assert (2.12E80 = (1.06E40*2.0E40))
+      report "***FAILED TEST: c07s05b00x00p16n03i02572 - Integer operands and result lie outside the bounds of floating point type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s05b00x00p16n03i02572arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2574.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2574.vhd
new file mode 100644
index 0000000..c8ff944
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2574.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2574.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s02b00x00p02n01i02574ent IS
+END c13s02b00x00p02n01i02574ent;
+
+ARCHITECTURE c13s02b00x00p02n01i02574arch OF c13s02b00x00p02n01i02574ent IS
+  type MEMisrange4to4 ;     -- Meant to be MEM is range 4 to 4 but
+  -- could be confused for an incomplete type.
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s02b00x00p02n01i02574 - Adjacent lexical elements should be separated by a separator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s02b00x00p02n01i02574arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2576.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2576.vhd
new file mode 100644
index 0000000..c244a65
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2576.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2576.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s02b00x00p04n02i02576ent IS
+  port (PT:BOOLEAN) ;
+  type REL1is range 1.0 to 10.0;
+  --ERROR: AT LEAST ONE SPACE MUST SEPARATE ADJACENT IDENTIFIERS
+END c13s02b00x00p04n02i02576ent;
+
+ARCHITECTURE c13s02b00x00p04n02i02576arch OF c13s02b00x00p04n02i02576ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s02b00x00p04n02i02576 - There should be atleast one space between adjacent identifiers."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s02b00x00p04n02i02576arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2577.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2577.vhd
new file mode 100644
index 0000000..78427ce
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2577.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2577.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s02b00x00p05n01i02577ent IS
+END c13s02b00x00p05n01i02577ent;
+
+ARCHITECTURE c13s02b00x00p05n01i02577arch OF c13s02b00x00p05n01i02577ent IS
+  -- ERROR: compound delimiter := contains a space
+  constant c1: character: ='A';   -- failure_here   
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s02b00x00p05n01i02577 - Compound delimiter cannot contain a space."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s02b00x00p05n01i02577arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2579.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2579.vhd
new file mode 100644
index 0000000..877e38a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2579.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2579.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s02b00x00p12n01i02579ent IS
+
+  port (PT:BOOLEAN) ;
+  ty
+    pe ONE is range 1 to 1;
+  --ERROR: RESERVED WORDS MUST FIT ON ONE LINE
+
+END c13s02b00x00p12n01i02579ent;
+
+ARCHITECTURE c13s02b00x00p12n01i02579arch OF c13s02b00x00p12n01i02579ent IS
+
+  b
+    egin
+--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s02b00x00p12n01i02579 - Reserved words must fit on one line."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s02b00x00p12n01i02579arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2580.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2580.vhd
new file mode 100644
index 0000000..246b8a6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2580.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2580.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02580ent IS
+END c13s03b01x00p02n01i02580ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02580arch OF c13s03b01x00p02n01i02580ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable "k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02580 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02580arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2581.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2581.vhd
new file mode 100644
index 0000000..ac2c87c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2581.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2581.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02581ent IS
+END c13s03b01x00p02n01i02581ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02581arch OF c13s03b01x00p02n01i02581ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k! : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02581 - Identifier can not end with '!'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02581arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2582.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2582.vhd
new file mode 100644
index 0000000..66ae5bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2582.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2582.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02582ent IS
+END c13s03b01x00p02n01i02582ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02582arch OF c13s03b01x00p02n01i02582ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k# : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02582 - Identifier can not end with '#'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02582arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2583.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2583.vhd
new file mode 100644
index 0000000..118f089
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2583.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2583.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02583ent IS
+END c13s03b01x00p02n01i02583ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02583arch OF c13s03b01x00p02n01i02583ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k% : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02583 - Identifier can not end with '%'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02583arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2584.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2584.vhd
new file mode 100644
index 0000000..0fe854b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2584.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2584.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02584ent IS
+END c13s03b01x00p02n01i02584ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02584arch OF c13s03b01x00p02n01i02584ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k^ : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02584 - Identifier can not end with '^'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02584arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2585.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2585.vhd
new file mode 100644
index 0000000..5446b69
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2585.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2585.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02585ent IS
+END c13s03b01x00p02n01i02585ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02585arch OF c13s03b01x00p02n01i02585ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k& : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02585 - Identifier can not end with '&'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02585arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2586.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2586.vhd
new file mode 100644
index 0000000..6302685
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2586.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2586.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02586ent IS
+END c13s03b01x00p02n01i02586ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02586arch OF c13s03b01x00p02n01i02586ent IS
+  ARCHITECTURE ch130301_p00201_06_arch OF ch130301_p00201_06_ent IS
+
+  BEGIN
+    TESTING: PROCESS
+      variable k* : integer := 0;
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c13s03b01x00p02n01i02586 - Identifier can not end with '*'."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c13s03b01x00p02n01i02586arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2587.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2587.vhd
new file mode 100644
index 0000000..ee8c5fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2587.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2587.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02587ent IS
+END c13s03b01x00p02n01i02587ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02587arch OF c13s03b01x00p02n01i02587ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k( : integer := 0;
+                BEGIN
+                  assert FALSE 
+                    report "***FAILED TEST: c13s03b01x00p02n01i02587 - Identifier can not end with '('."
+                    severity ERROR;
+                  wait;
+                END PROCESS TESTING;
+
+                END c13s03b01x00p02n01i02587arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2588.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2588.vhd
new file mode 100644
index 0000000..c8198c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2588.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2588.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02588ent IS
+END c13s03b01x00p02n01i02588ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02588arch OF c13s03b01x00p02n01i02588ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k) : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02588 - Identifier can not end with ')'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02588arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2589.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2589.vhd
new file mode 100644
index 0000000..36f6f7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2589.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2589.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02589ent IS
+END c13s03b01x00p02n01i02589ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02589arch OF c13s03b01x00p02n01i02589ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k+ : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02589 - Identifier can not end with '+'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02589arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2590.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2590.vhd
new file mode 100644
index 0000000..00f6461
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2590.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2590.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02590ent IS
+END c13s03b01x00p02n01i02590ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02590arch OF c13s03b01x00p02n01i02590ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k~ : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02590 - Identifier can not end with '~'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02590arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2591.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2591.vhd
new file mode 100644
index 0000000..641bf6c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2591.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2591.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02591ent IS
+END c13s03b01x00p02n01i02591ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02591arch OF c13s03b01x00p02n01i02591ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k- : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02591 - Identifier can not end with '-'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02591arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2592.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2592.vhd
new file mode 100644
index 0000000..6903723
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2592.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2592.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02592ent IS
+END c13s03b01x00p02n01i02592ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02592arch OF c13s03b01x00p02n01i02592ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k= : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02592 - Identifier can not end with '='."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02592arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2593.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2593.vhd
new file mode 100644
index 0000000..79b75ad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2593.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2593.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02593ent IS
+END c13s03b01x00p02n01i02593ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02593arch OF c13s03b01x00p02n01i02593ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k` : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02593 - Identifier can not end with '`'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02593arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2594.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2594.vhd
new file mode 100644
index 0000000..c91de07
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2594.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2594.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02594ent IS
+END c13s03b01x00p02n01i02594ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02594arch OF c13s03b01x00p02n01i02594ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k{ : integer := 0;
+                BEGIN
+                  assert FALSE 
+                    report "***FAILED TEST: c13s03b01x00p02n01i02594 - Identifier can not end with '{'."
+                    severity ERROR;
+                  wait;
+                END PROCESS TESTING;
+
+                END c13s03b01x00p02n01i02594arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2595.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2595.vhd
new file mode 100644
index 0000000..289ebc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2595.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2595.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02595ent IS
+END c13s03b01x00p02n01i02595ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02595arch OF c13s03b01x00p02n01i02595ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k} : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02595 - Identifier can not end with '}'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02595arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2596.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2596.vhd
new file mode 100644
index 0000000..cb26d7a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2596.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2596.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02596ent IS
+END c13s03b01x00p02n01i02596ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02596arch OF c13s03b01x00p02n01i02596ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k[ : integer := 0;
+                BEGIN
+                  assert FALSE 
+                    report "***FAILED TEST: c13s03b01x00p02n01i02596 - Identifier can not end with '['."
+                    severity ERROR;
+                  wait;
+                END PROCESS TESTING;
+
+                END c13s03b01x00p02n01i02596arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2597.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2597.vhd
new file mode 100644
index 0000000..738a905
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2597.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2597.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02597ent IS
+END c13s03b01x00p02n01i02597ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02597arch OF c13s03b01x00p02n01i02597ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k] : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02597 - Identifier can not end with ']'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02597arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2598.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2598.vhd
new file mode 100644
index 0000000..9cf5418
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2598.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2598.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02598ent IS
+END c13s03b01x00p02n01i02598ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02598arch OF c13s03b01x00p02n01i02598ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k; : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02598 - Identifier can not end with ';'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02598arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2599.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2599.vhd
new file mode 100644
index 0000000..b04f242
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2599.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2599.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02599ent IS
+END c13s03b01x00p02n01i02599ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02599arch OF c13s03b01x00p02n01i02599ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k' : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02599 - Identifier can not end with '''."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02599arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2600.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2600.vhd
new file mode 100644
index 0000000..34f78c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2600.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2600.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02600ent IS
+END c13s03b01x00p02n01i02600ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02600arch OF c13s03b01x00p02n01i02600ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k: : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02600 - Identifier can not end with ':'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02600arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2601.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2601.vhd
new file mode 100644
index 0000000..c645ecf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2601.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2601.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02601ent IS
+END c13s03b01x00p02n01i02601ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02601arch OF c13s03b01x00p02n01i02601ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k" : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02601 - Identifier can not end with '"'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02601arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2602.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2602.vhd
new file mode 100644
index 0000000..203147f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2602.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2602.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02602ent IS
+END c13s03b01x00p02n01i02602ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02602arch OF c13s03b01x00p02n01i02602ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k, : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02602 - Identifier can not end with ','."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02602arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2603.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2603.vhd
new file mode 100644
index 0000000..1a24397
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2603.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2603.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02603ent IS
+END c13s03b01x00p02n01i02603ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02603arch OF c13s03b01x00p02n01i02603ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k. : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02603 - Identifier can not end with '.'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02603arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2604.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2604.vhd
new file mode 100644
index 0000000..e1ad106
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2604.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2604.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02604ent IS
+END c13s03b01x00p02n01i02604ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02604arch OF c13s03b01x00p02n01i02604ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k/ : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02604 - Identifier can not end with '/'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02604arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2605.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2605.vhd
new file mode 100644
index 0000000..1ec2211
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2605.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2605.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02605ent IS
+END c13s03b01x00p02n01i02605ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02605arch OF c13s03b01x00p02n01i02605ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k< : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02605 - Identifier can not end with '<'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02605arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2606.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2606.vhd
new file mode 100644
index 0000000..8c4c8d1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2606.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2606.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02606ent IS
+END c13s03b01x00p02n01i02606ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02606arch OF c13s03b01x00p02n01i02606ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k> : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02606 - Identifier can not end with '>'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02606arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2607.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2607.vhd
new file mode 100644
index 0000000..b77c205
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2607.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2607.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02607ent IS
+END c13s03b01x00p02n01i02607ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02607arch OF c13s03b01x00p02n01i02607ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k? : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02607 - Identifier can not end with '?'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02607arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2608.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2608.vhd
new file mode 100644
index 0000000..0fa7132
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2608.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2608.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02608ent IS
+END c13s03b01x00p02n01i02608ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02608arch OF c13s03b01x00p02n01i02608ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k\ : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02608 - Identifier can not end with '\'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02608arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2609.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2609.vhd
new file mode 100644
index 0000000..cb23472
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2609.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2609.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02609ent IS
+END c13s03b01x00p02n01i02609ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02609arch OF c13s03b01x00p02n01i02609ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable 01k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02609 - Identifier can not begin with a digit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02609arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2610.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2610.vhd
new file mode 100644
index 0000000..6da7e93
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2610.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2610.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02610ent IS
+END c13s03b01x00p02n01i02610ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02610arch OF c13s03b01x00p02n01i02610ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k| : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02610 - Identifier can not end with '|'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02610arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2611.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2611.vhd
new file mode 100644
index 0000000..553ab10
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2611.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2611.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02611ent IS
+END c13s03b01x00p02n01i02611ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02611arch OF c13s03b01x00p02n01i02611ent IS
+BEGIN
+  TESTING: PROCESS
+    variable k!k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02611 - Identifier can not contain '!'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02611arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2612.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2612.vhd
new file mode 100644
index 0000000..f97af15
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2612.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2612.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02612ent IS
+END c13s03b01x00p02n01i02612ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02612arch OF c13s03b01x00p02n01i02612ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k#k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02612 - Identifier can not contain '#'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02612arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2613.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2613.vhd
new file mode 100644
index 0000000..2678ecf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2613.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2613.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02613ent IS
+END c13s03b01x00p02n01i02613ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02613arch OF c13s03b01x00p02n01i02613ent IS
+BEGIN
+  TESTING: PROCESS
+    variable k%k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02613 - Identifier can not contain '%'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02613arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2614.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2614.vhd
new file mode 100644
index 0000000..c1d1035
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2614.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2614.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02614ent IS
+END c13s03b01x00p02n01i02614ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02614arch OF c13s03b01x00p02n01i02614ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k^k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02614 - Identifier can not contain '^'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02614arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2615.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2615.vhd
new file mode 100644
index 0000000..53bd56a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2615.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2615.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02615ent IS
+END c13s03b01x00p02n01i02615ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02615arch OF c13s03b01x00p02n01i02615ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k&k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02615 - Identifier can not contain '&'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02615arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2616.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2616.vhd
new file mode 100644
index 0000000..2325de9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2616.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2616.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02616ent IS
+END c13s03b01x00p02n01i02616ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02616arch OF c13s03b01x00p02n01i02616ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k*k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02616 - Identifier can not contain '*'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02616arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2617.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2617.vhd
new file mode 100644
index 0000000..c2242c6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2617.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2617.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02617ent IS
+END c13s03b01x00p02n01i02617ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02617arch OF c13s03b01x00p02n01i02617ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k(k : integer := 0;
+               BEGIN
+                 assert FALSE 
+                   report "***FAILED TEST: c13s03b01x00p02n01i02617 - Identifier can not contain '('."
+                   severity ERROR;
+                 wait;
+               END PROCESS TESTING;
+
+               END c13s03b01x00p02n01i02617arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2618.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2618.vhd
new file mode 100644
index 0000000..e7d5f46
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2618.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2618.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02618ent IS
+END c13s03b01x00p02n01i02618ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02618arch OF c13s03b01x00p02n01i02618ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k)k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02618 - Identifier can not contain ')'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02618arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2619.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2619.vhd
new file mode 100644
index 0000000..2336f5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2619.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2619.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02619ent IS
+END c13s03b01x00p02n01i02619ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02619arch OF c13s03b01x00p02n01i02619ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k+k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02619 - Identifier can not contain '+'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02619arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2620.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2620.vhd
new file mode 100644
index 0000000..ac6ce45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2620.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2620.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02620ent IS
+END c13s03b01x00p02n01i02620ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02620arch OF c13s03b01x00p02n01i02620ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k~k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02620 - Identifier can not contain '~'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02620arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2621.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2621.vhd
new file mode 100644
index 0000000..f1f93ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2621.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2621.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02621ent IS
+END c13s03b01x00p02n01i02621ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02621arch OF c13s03b01x00p02n01i02621ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k-k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02621 - Identifier can not contain '-'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02621arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2622.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2622.vhd
new file mode 100644
index 0000000..8deffba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2622.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2622.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02622ent IS
+END c13s03b01x00p02n01i02622ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02622arch OF c13s03b01x00p02n01i02622ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k=k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02622 - Identifier can not contain '='."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02622arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2623.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2623.vhd
new file mode 100644
index 0000000..73db20f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2623.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2623.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02623ent IS
+END c13s03b01x00p02n01i02623ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02623arch OF c13s03b01x00p02n01i02623ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k`k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02623 - Identifier can not contain '`'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02623arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2624.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2624.vhd
new file mode 100644
index 0000000..a8edf35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2624.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2624.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02624ent IS
+END c13s03b01x00p02n01i02624ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02624arch OF c13s03b01x00p02n01i02624ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k{k : integer := 0;
+               BEGIN
+                 assert FALSE 
+                   report "***FAILED TEST: c13s03b01x00p02n01i02624 - Identifier can not contain '{'."
+                   severity ERROR;
+                 wait;
+               END PROCESS TESTING;
+
+               END c13s03b01x00p02n01i02624arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2625.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2625.vhd
new file mode 100644
index 0000000..26cb79d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2625.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2625.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02625ent IS
+END c13s03b01x00p02n01i02625ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02625arch OF c13s03b01x00p02n01i02625ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k}k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02625 - Identifier can not contain '}'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02625arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2626.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2626.vhd
new file mode 100644
index 0000000..00836a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2626.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2626.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02626ent IS
+END c13s03b01x00p02n01i02626ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02626arch OF c13s03b01x00p02n01i02626ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k[k : integer := 0;
+               BEGIN
+                 assert FALSE 
+                   report "***FAILED TEST: c13s03b01x00p02n01i02626 - Identifier can not contain '['."
+                   severity ERROR;
+                 wait;
+               END PROCESS TESTING;
+
+               END c13s03b01x00p02n01i02626arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2627.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2627.vhd
new file mode 100644
index 0000000..234fd03
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2627.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2627.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02627ent IS
+END c13s03b01x00p02n01i02627ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02627arch OF c13s03b01x00p02n01i02627ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k]k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02627 - Identifier can not contain ']'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02627arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2628.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2628.vhd
new file mode 100644
index 0000000..282102c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2628.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2628.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02628ent IS
+END c13s03b01x00p02n01i02628ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02628arch OF c13s03b01x00p02n01i02628ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k;k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02628 - Identifier can not contain ';'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02628arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2629.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2629.vhd
new file mode 100644
index 0000000..5ffc2d2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2629.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2629.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02629ent IS
+END c13s03b01x00p02n01i02629ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02629arch OF c13s03b01x00p02n01i02629ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k'k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02629 - Identifier can not contain '''."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02629arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2630.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2630.vhd
new file mode 100644
index 0000000..0f4bb9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2630.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2630.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02630ent IS
+END c13s03b01x00p02n01i02630ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02630arch OF c13s03b01x00p02n01i02630ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k:k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02630 - Identifier can not contain ':'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02630arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2631.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2631.vhd
new file mode 100644
index 0000000..099a893
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2631.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2631.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02631ent IS
+END c13s03b01x00p02n01i02631ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02631arch OF c13s03b01x00p02n01i02631ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k"k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02631 - Identifier can not contain '"'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02631arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2632.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2632.vhd
new file mode 100644
index 0000000..88c9bc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2632.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2632.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02632ent IS
+END c13s03b01x00p02n01i02632ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02632arch OF c13s03b01x00p02n01i02632ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k,k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02632 - Identifier can not contain ','."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02632arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2633.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2633.vhd
new file mode 100644
index 0000000..b3ed2cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2633.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2633.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02633ent IS
+END c13s03b01x00p02n01i02633ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02633arch OF c13s03b01x00p02n01i02633ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k.k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02633 - Identifier can not contain '.'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02633arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2634.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2634.vhd
new file mode 100644
index 0000000..080d4b2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2634.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2634.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02634ent IS
+END c13s03b01x00p02n01i02634ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02634arch OF c13s03b01x00p02n01i02634ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k/k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02634 - Identifier can not contain '/'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02634arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2635.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2635.vhd
new file mode 100644
index 0000000..1b1e850
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2635.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2635.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02635ent IS
+END c13s03b01x00p02n01i02635ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02635arch OF c13s03b01x00p02n01i02635ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k<k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02635 - Identifier can not contain '<'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02635arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2636.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2636.vhd
new file mode 100644
index 0000000..775ff1c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2636.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2636.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02636ent IS
+END c13s03b01x00p02n01i02636ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02636arch OF c13s03b01x00p02n01i02636ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k>k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02636 - Identifier can not contain '>'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02636arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2637.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2637.vhd
new file mode 100644
index 0000000..bcca3c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2637.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2637.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02637ent IS
+END c13s03b01x00p02n01i02637ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02637arch OF c13s03b01x00p02n01i02637ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k?k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02637 - Identifier can not contain '?'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02637arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2638.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2638.vhd
new file mode 100644
index 0000000..8544244
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2638.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2638.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02638ent IS
+END c13s03b01x00p02n01i02638ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02638arch OF c13s03b01x00p02n01i02638ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k\k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02638 - Identifier can not contain '\'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02638arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2639.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2639.vhd
new file mode 100644
index 0000000..24f90e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2639.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2639.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02639ent IS
+END c13s03b01x00p02n01i02639ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02639arch OF c13s03b01x00p02n01i02639ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k|k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02639 - Identifier can not contain '|'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02639arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2640.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2640.vhd
new file mode 100644
index 0000000..ffbe006
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2640.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2640.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02640ent IS
+END c13s03b01x00p02n01i02640ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02640arch OF c13s03b01x00p02n01i02640ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02640 - Identifier can not contain ' '."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02640arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2641.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2641.vhd
new file mode 100644
index 0000000..c8c5046
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2641.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2641.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02641ent IS
+END c13s03b01x00p02n01i02641ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02641arch OF c13s03b01x00p02n01i02641ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k__k : integer := 0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02641 - Identifier can not contain '__'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02641arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2644.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2644.vhd
new file mode 100644
index 0000000..9f6b3df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2644.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2644.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02644ent IS
+END c13s03b01x00p02n01i02644ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02644arch OF c13s03b01x00p02n01i02644ent IS
+  -- ERROR: name of the constant contains 2 consecutive underlines  
+  constant te__st: character:='A';  --failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02644 - Consecutive underlines are not allowed in an identifier." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02644arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2645.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2645.vhd
new file mode 100644
index 0000000..3cd42db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2645.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2645.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02645ent IS
+END c13s03b01x00p02n01i02645ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02645arch OF c13s03b01x00p02n01i02645ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable #k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02645 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02645arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2646.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2646.vhd
new file mode 100644
index 0000000..5569675
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2646.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2646.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02646ent IS
+END c13s03b01x00p02n01i02646ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02646arch OF c13s03b01x00p02n01i02646ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable &k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02646 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02646arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2647.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2647.vhd
new file mode 100644
index 0000000..7fc8860
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2647.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2647.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02647ent IS
+END c13s03b01x00p02n01i02647ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02647arch OF c13s03b01x00p02n01i02647ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable 'k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02647 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02647arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2648.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2648.vhd
new file mode 100644
index 0000000..855e415
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2648.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2648.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02648ent IS
+END c13s03b01x00p02n01i02648ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02648arch OF c13s03b01x00p02n01i02648ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable (k : integer;
+              BEGIN
+                assert FALSE 
+                  report "***FAILED TEST: c13s03b01x00p02n01i02648 - Identifier can only begin with a letter."
+                  severity ERROR;
+                wait;
+              END PROCESS TESTING;
+
+              END c13s03b01x00p02n01i02648arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2649.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2649.vhd
new file mode 100644
index 0000000..ffd94fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2649.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2649.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02649ent IS
+END c13s03b01x00p02n01i02649ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02649arch OF c13s03b01x00p02n01i02649ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable )k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02649 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02649arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2650.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2650.vhd
new file mode 100644
index 0000000..1df1de2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2650.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2650.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02650ent IS
+END c13s03b01x00p02n01i02650ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02650arch OF c13s03b01x00p02n01i02650ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable *k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02650 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02650arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2651.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2651.vhd
new file mode 100644
index 0000000..c4c74fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2651.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2651.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02651ent IS
+END c13s03b01x00p02n01i02651ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02651arch OF c13s03b01x00p02n01i02651ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable +k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02651 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02651arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2652.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2652.vhd
new file mode 100644
index 0000000..9913c3c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2652.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2652.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02652ent IS
+END c13s03b01x00p02n01i02652ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02652arch OF c13s03b01x00p02n01i02652ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable -k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02652 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02652arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2653.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2653.vhd
new file mode 100644
index 0000000..eafbdd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2653.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2653.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02653ent IS
+END c13s03b01x00p02n01i02653ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02653arch OF c13s03b01x00p02n01i02653ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable .k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02653 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02653arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2654.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2654.vhd
new file mode 100644
index 0000000..33e0260
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2654.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2654.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02654ent IS
+END c13s03b01x00p02n01i02654ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02654arch OF c13s03b01x00p02n01i02654ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable /k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02654 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02654arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2655.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2655.vhd
new file mode 100644
index 0000000..a2d6a35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2655.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2655.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02655ent IS
+END c13s03b01x00p02n01i02655ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02655arch OF c13s03b01x00p02n01i02655ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable :k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02655d - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02655arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2656.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2656.vhd
new file mode 100644
index 0000000..ed38a00
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2656.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2656.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02656ent IS
+END c13s03b01x00p02n01i02656ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02656arch OF c13s03b01x00p02n01i02656ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable ;k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02656 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02656arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2657.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2657.vhd
new file mode 100644
index 0000000..93435f3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2657.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2657.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02657ent IS
+END c13s03b01x00p02n01i02657ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02657arch OF c13s03b01x00p02n01i02657ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable <k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02657 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02657arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2658.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2658.vhd
new file mode 100644
index 0000000..d073dd9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2658.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2658.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02658ent IS
+END c13s03b01x00p02n01i02658ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02658arch OF c13s03b01x00p02n01i02658ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable =k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02658 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02658arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2659.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2659.vhd
new file mode 100644
index 0000000..a326b6c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2659.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2659.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02659ent IS
+END c13s03b01x00p02n01i02659ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02659arch OF c13s03b01x00p02n01i02659ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable >k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02659 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02659arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc266.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc266.vhd
new file mode 100644
index 0000000..e57996d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc266.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc266.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p02n01i00266ent IS
+END c03s01b03x00p02n01i00266ent;
+
+ARCHITECTURE c03s01b03x00p02n01i00266arch OF c03s01b03x00p02n01i00266ent IS
+  type UPLE is
+    units  -- Failure_here
+      -- ERROR - SYNTAX ERROR: PHYSICAL TYPE DEFINITION MUST HAVE RANGE CONSTRAINT
+      single;
+      double = 2 single;
+      triple = 3 single;
+      quadruple = 2 double;
+      pentuple = 5 single;
+      sextuple = 2 triple;
+      septuple = 7 single;
+      octuple = 2 quadruple;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p02n01i00266 - Physical type definition must have range constraint." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p02n01i00266arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2660.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2660.vhd
new file mode 100644
index 0000000..d31a50c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2660.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2660.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02660ent IS
+END c13s03b01x00p02n01i02660ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02660arch OF c13s03b01x00p02n01i02660ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable _k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02660 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02660arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2661.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2661.vhd
new file mode 100644
index 0000000..1037743
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2661.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2661.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02661ent IS
+END c13s03b01x00p02n01i02661ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02661arch OF c13s03b01x00p02n01i02661ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable |k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02661 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02661arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2662.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2662.vhd
new file mode 100644
index 0000000..0ed769b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2662.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2662.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02662ent IS
+END c13s03b01x00p02n01i02662ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02662arch OF c13s03b01x00p02n01i02662ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable !k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02662 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02662arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2663.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2663.vhd
new file mode 100644
index 0000000..5d05ba2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2663.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2663.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02663ent IS
+END c13s03b01x00p02n01i02663ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02663arch OF c13s03b01x00p02n01i02663ent IS
+BEGIN
+  TESTING: PROCESS
+    variable $k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02663 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02663arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2664.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2664.vhd
new file mode 100644
index 0000000..57c6dc7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2664.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2664.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02664ent IS
+END c13s03b01x00p02n01i02664ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02664arch OF c13s03b01x00p02n01i02664ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable %k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02664 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02664arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2665.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2665.vhd
new file mode 100644
index 0000000..507142e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2665.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2665.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02665ent IS
+END c13s03b01x00p02n01i02665ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02665arch OF c13s03b01x00p02n01i02665ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable @k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02665 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02665arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2666.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2666.vhd
new file mode 100644
index 0000000..40ad8c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2666.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2666.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02666ent IS
+END c13s03b01x00p02n01i02666ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02666arch OF c13s03b01x00p02n01i02666ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable ?k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02666 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02666arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2667.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2667.vhd
new file mode 100644
index 0000000..632fa14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2667.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2667.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02667ent IS
+END c13s03b01x00p02n01i02667ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02667arch OF c13s03b01x00p02n01i02667ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable [k : integer;
+              BEGIN
+                assert FALSE 
+                  report "***FAILED TEST: c13s03b01x00p02n01i02667 - Identifier can only begin with a letter."
+                  severity ERROR;
+                wait;
+              END PROCESS TESTING;
+
+              END c13s03b01x00p02n01i02667arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2668.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2668.vhd
new file mode 100644
index 0000000..893fb01
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2668.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2668.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02668ent IS
+END c13s03b01x00p02n01i02668ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02668arch OF c13s03b01x00p02n01i02668ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable \k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02668 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02668arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2669.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2669.vhd
new file mode 100644
index 0000000..39ee538
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2669.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2669.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02669ent IS
+END c13s03b01x00p02n01i02669ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02669arch OF c13s03b01x00p02n01i02669ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable ]k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02669 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02669arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc267.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc267.vhd
new file mode 100644
index 0000000..daa0456
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc267.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc267.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p02n01i00267ent IS
+END c03s01b03x00p02n01i00267ent;
+
+ARCHITECTURE c03s01b03x00p02n01i00267arch OF c03s01b03x00p02n01i00267ent IS
+  type UPLE is range 1 to 8
+    units
+      single = 1 single;  -- Failure_here
+      -- ERROR - SYNTAX ERROR: BASE UNIT DECLARATION MISSING   
+      double = 2 single;
+      triple = 3 single;
+      quadruple = 2 double;
+      pentuple = 5 single;
+      sextuple = 2 triple;
+      septuple = 7 single;
+      octuple = 2 quadruple;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p02n01i00267 - Physical type declaration must have a base unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p02n01i00267arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2670.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2670.vhd
new file mode 100644
index 0000000..06ce738
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2670.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2670.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02670ent IS
+END c13s03b01x00p02n01i02670ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02670arch OF c13s03b01x00p02n01i02670ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable ^k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02670 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02670arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2671.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2671.vhd
new file mode 100644
index 0000000..5dfe148
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2671.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2671.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02671ent IS
+END c13s03b01x00p02n01i02671ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02671arch OF c13s03b01x00p02n01i02671ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable `k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02671 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02671arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2672.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2672.vhd
new file mode 100644
index 0000000..bb14e46
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2672.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2672.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02672ent IS
+END c13s03b01x00p02n01i02672ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02672arch OF c13s03b01x00p02n01i02672ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable {k : integer;
+              BEGIN
+                assert FALSE 
+                  report "***FAILED TEST: c13s03b01x00p02n01i02672 - Identifier can only begin with a letter."
+                  severity ERROR;
+                wait;
+              END PROCESS TESTING;
+
+              END c13s03b01x00p02n01i02672arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2673.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2673.vhd
new file mode 100644
index 0000000..738ecf4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2673.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2673.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02673ent IS
+END c13s03b01x00p02n01i02673ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02673arch OF c13s03b01x00p02n01i02673ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable }k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02673 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02673arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2674.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2674.vhd
new file mode 100644
index 0000000..ed48c0d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2674.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2674.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p02n01i02674ent IS
+END c13s03b01x00p02n01i02674ent;
+
+ARCHITECTURE c13s03b01x00p02n01i02674arch OF c13s03b01x00p02n01i02674ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable ~k : integer;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p02n01i02674 - Identifier can only begin with a letter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p02n01i02674arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2678.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2678.vhd
new file mode 100644
index 0000000..bb14dc1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2678.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2678.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s03b01x00p05n02i02678ent IS
+END c13s03b01x00p05n02i02678ent;
+
+ARCHITECTURE c13s03b01x00p05n02i02678arch OF c13s03b01x00p05n02i02678ent IS
+  constant   UPPER_CASE : integer := 27;
+  -- ERROR: double declaration due to case insensitivity;
+  signal       upper_case:integer;     -- failure_here.
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s03b01x00p05n02i02678 - Identifiers differing only in the use of corresponding upper and lower case letters are considered as the same."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s03b01x00p05n02i02678arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc268.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc268.vhd
new file mode 100644
index 0000000..1ea1adf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc268.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc268.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p02n01i00268ent IS
+END c03s01b03x00p02n01i00268ent;
+
+ARCHITECTURE c03s01b03x00p02n01i00268arch OF c03s01b03x00p02n01i00268ent IS
+  type UPLE is range 1 to 8
+    units
+      single;
+      double;  -- Failure_here
+      -- SYNTAX ERROR: MORE THAN ONE BASE UNIT DECLARATION
+      triple = 3 single;
+      quadruple = 2 double;
+      pentuple = 5 single;
+      sextuple = 2 triple;
+      septuple = 7 single;
+      octuple = 2 quadruple;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p02n01i00268 - Only one base type declaration allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p02n01i00268arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2680.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2680.vhd
new file mode 100644
index 0000000..7a4184e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2680.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2680.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02680ent IS
+  --ERROR: underline cannot lead an integer literal
+  constant a:integer:=_1234; -- failure_here
+END c13s04b01x00p02n01i02680ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02680arch OF c13s04b01x00p02n01i02680ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p02n01i02680 - Decimal literal can only begin with an integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02680arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2681.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2681.vhd
new file mode 100644
index 0000000..9981574
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2681.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2681.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02681ent IS
+  --ERROR: underline cannot lead a real literal
+  constant a:real:=_1234.5678; -- failure_here
+END c13s04b01x00p02n01i02681ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02681arch OF c13s04b01x00p02n01i02681ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p02n01i02681 - Decimal literal can only begin with an integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02681arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2682.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2682.vhd
new file mode 100644
index 0000000..be9de70
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2682.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2682.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02682ent IS
+  --ERROR: leading decimal point not allowed
+  constant A1: REAL:=.12;   -- failure_here
+END c13s04b01x00p02n01i02682ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02682arch OF c13s04b01x00p02n01i02682ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p02n01i02682 - Decimal literal can only begin with an integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02682arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2683.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2683.vhd
new file mode 100644
index 0000000..70c821b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2683.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2683.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02683ent IS
+  --ERROR: trailing decimal point not allowed
+  constant A1: REAL:=12.;    -- failure_here
+END c13s04b01x00p02n01i02683ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02683arch OF c13s04b01x00p02n01i02683ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p02n01i02683 - Integer should follow the dot in a real integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02683arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2684.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2684.vhd
new file mode 100644
index 0000000..278a3ca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2684.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2684.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02684ent IS
+  --ERROR: underline cannot be adjacent to a decimal point
+  constant b:real:=2._34;  -- failure_here
+END c13s04b01x00p02n01i02684ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02684arch OF c13s04b01x00p02n01i02684ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p02n01i02684 - Only integer follows the dot in a real literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02684arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2685.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2685.vhd
new file mode 100644
index 0000000..a4577fe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2685.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2685.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02685ent IS
+  --ERROR: underline cannot be adjacent on the left to 'E' in an integer literal
+  constant a:integer:=1234_E2;     -- failure_here
+END c13s04b01x00p02n01i02685ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02685arch OF c13s04b01x00p02n01i02685ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p02n01i02685 - Only integer can be to the left of the exponent in a decimal literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02685arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2686.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2686.vhd
new file mode 100644
index 0000000..e433fe2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2686.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2686.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02686ent IS
+  --ERROR: only 1 decimal point allowed in real literal
+  constant A1: REAL:=3.5.7;   -- failure_here
+END c13s04b01x00p02n01i02686ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02686arch OF c13s04b01x00p02n01i02686ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p02n01i02686 - Two decimal points are not permitted in real literals."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02686arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2687.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2687.vhd
new file mode 100644
index 0000000..c86d46a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2687.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2687.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02687ent IS
+  --ERROR: only 1 decimal point allowed in real literal
+  constant A1: REAL:=3..57;   -- failure_here
+END c13s04b01x00p02n01i02687ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02687arch OF c13s04b01x00p02n01i02687ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p02n01i02687 - Two decimal points are not permitted in real literals."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02687arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2688.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2688.vhd
new file mode 100644
index 0000000..a766d6b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2688.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2688.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02688ent IS
+  constant n: real := 45.3 E+11;  -- failure_here
+END c13s04b01x00p02n01i02688ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02688arch OF c13s04b01x00p02n01i02688ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p02n01i02688 - No space is allowed in literals."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02688arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2689.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2689.vhd
new file mode 100644
index 0000000..1a3ed1a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2689.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2689.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p02n01i02689ent IS
+  --ERROR: no space is allowed in an integer literal
+  constant a:integer:=54 321;  -- failure_here
+END c13s04b01x00p02n01i02689ent;
+
+ARCHITECTURE c13s04b01x00p02n01i02689arch OF c13s04b01x00p02n01i02689ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p02n01i02689 - No space is allowed in literals."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p02n01i02689arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc269.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc269.vhd
new file mode 100644
index 0000000..04aa591
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc269.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc269.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p03n01i00269ent IS
+END c03s01b03x00p03n01i00269ent;
+
+ARCHITECTURE c03s01b03x00p03n01i00269arch OF c03s01b03x00p03n01i00269ent IS
+  type T is
+    range 1 to 100
+    units
+      I            -- failure_here
+        J = 2 I;
+      K = 2 J;
+      L = 10 K;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p03n01i00269 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p03n01i00269arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2691.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2691.vhd
new file mode 100644
index 0000000..f05832b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2691.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2691.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p03n01i02691ent IS
+  --ERROR: underline cannot trail an integer literal
+  constant a:integer:=567_;  -- failure_here
+END c13s04b01x00p03n01i02691ent;
+
+ARCHITECTURE c13s04b01x00p03n01i02691arch OF c13s04b01x00p03n01i02691ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p03n01i02691 - Underlines cannot trail a decimal literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p03n01i02691arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2692.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2692.vhd
new file mode 100644
index 0000000..438c725
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2692.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2692.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p04n01i02692ent IS
+  --ERROR: only 1 (+) in exponent allowed in real literal
+  constant A1: REAL:=123E--45;  -- failure_here
+END c13s04b01x00p04n01i02692ent;
+
+ARCHITECTURE c13s04b01x00p04n01i02692arch OF c13s04b01x00p04n01i02692ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p04n01i02692 - Exponents of decimal literals can have a single plus or minus (optional)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p04n01i02692arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2693.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2693.vhd
new file mode 100644
index 0000000..ae1733b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2693.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2693.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p04n01i02693ent IS
+  --ERROR: only 1 (+) in exponent allowed in real literal
+  constant A1: REAL:=123E++45;  -- failure_here
+END c13s04b01x00p04n01i02693ent;
+
+ARCHITECTURE c13s04b01x00p04n01i02693arch OF c13s04b01x00p04n01i02693ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p04n01i02693 - Exponents of decimal literals can have a single plus or minus (optional)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p04n01i02693arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2694.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2694.vhd
new file mode 100644
index 0000000..9d9dd23
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2694.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2694.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p04n01i02694ent IS
+  --ERROR: underline cannot be adjacent on the right to 'E' in an integer literal
+  constant a:integer:=1234E_2;  -- failure_here
+END c13s04b01x00p04n01i02694ent;
+
+ARCHITECTURE c13s04b01x00p04n01i02694arch OF c13s04b01x00p04n01i02694ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p04n01i02694 - Exponents of decimal literals can have a single plus or minus following the E (optional)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p04n01i02694arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2695.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2695.vhd
new file mode 100644
index 0000000..7eca9b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2695.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2695.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p04n01i02695ent IS
+  --ERROR: only integer exponent allowed in real literal
+  constant A1: REAL:=123E4.5;   -- failure_here
+END c13s04b01x00p04n01i02695ent;
+
+ARCHITECTURE c13s04b01x00p04n01i02695arch OF c13s04b01x00p04n01i02695ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p04n01i02695 - Only integer exponents are legal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p04n01i02695arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2696.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2696.vhd
new file mode 100644
index 0000000..af9dd6a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2696.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2696.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p04n01i02696ent IS
+  --ERROR: No extended digit is allowed in the exponent
+  constant a:integer:=16#54321#A; -- failure_here   
+END c13s04b01x00p04n01i02696ent;
+
+ARCHITECTURE c13s04b01x00p04n01i02696arch OF c13s04b01x00p04n01i02696ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p04n01i02696 - Only integer exponents are legal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p04n01i02696arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc270.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc270.vhd
new file mode 100644
index 0000000..a15a537
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc270.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc270.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p05n01i00270ent IS
+END c03s01b03x00p05n01i00270ent;
+
+ARCHITECTURE c03s01b03x00p05n01i00270arch OF c03s01b03x00p05n01i00270ent IS
+  type T is
+    range 1 to 100
+    units
+      I ;  
+      J = 2 I;
+      K = 2 P;   -- Failure_here
+      L = 10 K;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p05n01i00270 - Improper unit name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p05n01i00270arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2706.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2706.vhd
new file mode 100644
index 0000000..966ae37
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2706.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2706.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b01x00p06n02i02706ent IS
+END c13s04b01x00p06n02i02706ent;
+
+ARCHITECTURE c13s04b01x00p06n02i02706arch OF c13s04b01x00p06n02i02706ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable total_time : integer;
+  BEGIN
+    total_time := 123234e-3;    -- failure_here
+    assert FALSE
+      report "***FAILED TEST: c13s04b01x00p06n02i02706 - An integer literal may not have a negative exponent."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b01x00p06n02i02706arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc271.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc271.vhd
new file mode 100644
index 0000000..96bb6b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc271.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc271.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p06n01i00271ent IS
+END c03s01b03x00p06n01i00271ent;
+
+ARCHITECTURE c03s01b03x00p06n01i00271arch OF c03s01b03x00p06n01i00271ent IS
+  type GLORIA is range 1 to 6
+    units
+      PRIM;
+      SEC1 = 6 PRIM;
+      SEC2 = 36 SEC1;  -- Failure_here
+      -- ERROR - SEMANTICS ERROR: Position Number of sec2 exceeds
+      -- range of physical type
+    end units;
+BEGIN
+  TESTING: PROCESS
+    variable temp : GLORIA := 10 PRIM;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p06n01i00271 - Position number exceeds range of physical type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p06n01i00271arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2714.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2714.vhd
new file mode 100644
index 0000000..e4e712f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2714.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2714.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p01n01i02714ent IS
+END c13s04b02x00p01n01i02714ent;
+
+ARCHITECTURE c13s04b02x00p01n01i02714arch OF c13s04b02x00p01n01i02714ent IS
+BEGIN
+  TESTING: PROCESS
+    variable total_time : real;
+  BEGIN
+    total_time := 17#FF.FF#;    -- failure_here
+    assert FALSE
+      report "***FAILED TEST: c13s04b02x00p01n01i02714 - The base of a based literal must be less than 16."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p01n01i02714arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2715.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2715.vhd
new file mode 100644
index 0000000..0de0919
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2715.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2715.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p01n01i02715ent IS
+END c13s04b02x00p01n01i02715ent;
+
+ARCHITECTURE c13s04b02x00p01n01i02715arch OF c13s04b02x00p01n01i02715ent IS
+BEGIN
+  TESTING: PROCESS
+    variable I : INTEGER;
+    variable R : REAL;
+  BEGIN
+    I := 0#121#E2;        -- ERROR : invalid base
+    assert FALSE 
+      report "***FAILED TEST: c13s04b02x00p01n01i02715 - No base less than '2' or greater than '16' is allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p01n01i02715arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2716.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2716.vhd
new file mode 100644
index 0000000..b566e57
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2716.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2716.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p01n01i02716ent IS
+END c13s04b02x00p01n01i02716ent;
+
+ARCHITECTURE c13s04b02x00p01n01i02716arch OF c13s04b02x00p01n01i02716ent IS
+BEGIN
+  TESTING: PROCESS
+    variable I : INTEGER;
+    variable R : REAL;
+  BEGIN
+    I := 1#0000#;         -- ERROR : invalid base
+    assert FALSE 
+      report "***FAILED TEST: c13s04b02x00p01n01i02716 - No base less than '2' or greater than '16' is allowed." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p01n01i02716arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2717.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2717.vhd
new file mode 100644
index 0000000..efaec07
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2717.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2717.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p02n01i02717ent IS
+END c13s04b02x00p02n01i02717ent;
+
+ARCHITECTURE c13s04b02x00p02n01i02717arch OF c13s04b02x00p02n01i02717ent IS
+  constant T2 : Real := 5#1234.4321 ; --- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b02x00p02n01i02717 - Missing sharp."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p02n01i02717arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2720.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2720.vhd
new file mode 100644
index 0000000..bca57cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2720.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2720.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p03n01i02720ent IS
+  --ERROR: No extended digit is allowed in the base
+  constant a:integer:=A#54321#;   -- failure_here
+END c13s04b02x00p03n01i02720ent;
+
+ARCHITECTURE c13s04b02x00p03n01i02720arch OF c13s04b02x00p03n01i02720ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b02x00p03n01i02720 - Base of a based literal can only be an integer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p03n01i02720arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2721.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2721.vhd
new file mode 100644
index 0000000..21eedd9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2721.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2721.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p04n01i02721ent IS
+END c13s04b02x00p04n01i02721ent;
+
+ARCHITECTURE c13s04b02x00p04n01i02721arch OF c13s04b02x00p04n01i02721ent IS
+  constant T3 : Integer := 2#1111_11__1111# ;   -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s04b02x00p04n01i02721 - Consecutive underlines are not allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p04n01i02721arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2723.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2723.vhd
new file mode 100644
index 0000000..d081a4f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2723.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2723.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p06n03i02723ent IS
+  -- ERROR: r is not a valid hex digit
+  constant m: integer := 16#Fr#;    -- failure_here
+END c13s04b02x00p06n03i02723ent;
+
+ARCHITECTURE c13s04b02x00p06n03i02723arch OF c13s04b02x00p06n03i02723ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s04b02x00p06n03i02723 - The only letters allowed as extended digits are the letters A through F."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p06n03i02723arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2727.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2727.vhd
new file mode 100644
index 0000000..a11a227
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2727.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2727.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s04b02x00p07n01i02727ent IS
+END c13s04b02x00p07n01i02727ent;
+
+ARCHITECTURE c13s04b02x00p07n01i02727arch OF c13s04b02x00p07n01i02727ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable total_time : real;
+  BEGIN
+    total_time := 6#6589.55#;   --Failure_here
+    assert FALSE
+      report "***FAILED TEST: c13s04b02x00p07n01i02727 - The value of each digit in a based literal must be less than that of the base."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s04b02x00p07n01i02727arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2728.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2728.vhd
new file mode 100644
index 0000000..912f350
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2728.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2728.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s05b00x00p01n01i02728ent IS
+END c13s05b00x00p01n01i02728ent;
+
+ARCHITECTURE c13s05b00x00p01n01i02728arch OF c13s05b00x00p01n01i02728ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : character;
+  BEGIN
+    k := '';
+    assert FALSE 
+      report "***FAILED TEST: c13s05b00x00p01n01i02728 - A character literal may not be empty."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s05b00x00p01n01i02728arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2729.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2729.vhd
new file mode 100644
index 0000000..73bff33
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2729.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2729.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s05b00x00p01n01i02729ent IS
+END c13s05b00x00p01n01i02729ent;
+
+ARCHITECTURE c13s05b00x00p01n01i02729arch OF c13s05b00x00p01n01i02729ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : character;
+  BEGIN
+    k := 'aa';
+    assert FALSE 
+      report "***FAILED TEST: c13s05b00x00p01n01i02729 - A character literal must have only one character between quotes." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s05b00x00p01n01i02729arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc273.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc273.vhd
new file mode 100644
index 0000000..f0ce5f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc273.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc273.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00273ent IS
+END c03s01b03x00p07n01i00273ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00273arch OF c03s01b03x00p07n01i00273ent IS
+  type UPLE is range 1.0 to 9.0  -- Failure_here
+    -- ERROR - SEMANTIC ERROR: PHYSICAL TYPE DEFINITION RANGE CONSTRAINT
+    -- MUST BE OF INTEGER TYPE
+    units
+      single;
+      double = 2 single;
+      triple = 3 single;
+      quadruple = 2 double;
+      pentuple = 5 single;
+      sextuple = 2 triple;
+      septuple = 7 single;
+      octuple = 2 quadruple;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p07n01i00273 - Physical type definition range constraint must be constant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00273arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2730.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2730.vhd
new file mode 100644
index 0000000..b3ceaae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2730.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2730.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s05b00x00p01n01i02730ent IS
+END c13s05b00x00p01n01i02730ent;
+
+ARCHITECTURE c13s05b00x00p01n01i02730arch OF c13s05b00x00p01n01i02730ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : character;
+  BEGIN
+    k := '  ';
+    assert FALSE 
+      report "***FAILED TEST: c13s05b00x00p01n01i02730 - Double space is not allowed in a character literal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s05b00x00p01n01i02730arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2731.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2731.vhd
new file mode 100644
index 0000000..3af28ea
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2731.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2731.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s05b00x00p01n01i02731ent IS
+END c13s05b00x00p01n01i02731ent;
+
+ARCHITECTURE c13s05b00x00p01n01i02731arch OF c13s05b00x00p01n01i02731ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : character;
+  BEGIN
+    k := '';
+    assert FALSE 
+      report "***FAILED TEST: c13s05b00x00p01n01i02731 - ^A can not be used as a character literal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s05b00x00p01n01i02731arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2732.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2732.vhd
new file mode 100644
index 0000000..40b4648
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2732.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2732.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s05b00x00p01n01i02732ent IS
+END c13s05b00x00p01n01i02732ent;
+
+ARCHITECTURE c13s05b00x00p01n01i02732arch OF c13s05b00x00p01n01i02732ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : character;
+  BEGIN
+    k := '';
+    assert FALSE 
+      report "***FAILED TEST: c13s05b00x00p01n01i02732 - ^B can not be used as a character literal." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s05b00x00p01n01i02732arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc274.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc274.vhd
new file mode 100644
index 0000000..d96a84b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc274.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc274.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00274ent IS
+END c03s01b03x00p07n01i00274ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00274arch OF c03s01b03x00p07n01i00274ent IS
+  type J is
+    range 0.0 to 100.0 -- Failure_here
+    units
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p07n01i00274 - The bounds in the range constraint are not locally static expressions of type integer." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00274arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2741.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2741.vhd
new file mode 100644
index 0000000..39fe9c9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2741.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2741.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s06b00x00p03n02i02741ent IS
+  --ERROR: need 2 quotation characters as input for a string literal
+  constant c: string:=""";   -- failure_here
+END c13s06b00x00p03n02i02741ent;
+
+ARCHITECTURE c13s06b00x00p03n02i02741arch OF c13s06b00x00p03n02i02741ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert   FALSE 
+      report "***FAILED TEST: c13s06b00x00p03n02i02741 - Single quotation mark cannot be a string literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s06b00x00p03n02i02741arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2746.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2746.vhd
new file mode 100644
index 0000000..6dbb797
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2746.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2746.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p02n01i02746ent IS
+END c13s07b00x00p02n01i02746ent;
+
+ARCHITECTURE c13s07b00x00p02n01i02746arch OF c13s07b00x00p02n01i02746ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable k : bit_vector(0 to 7) := b'0''1''0''1''0''1''0''1';
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p02n01i02746 - Bit value should be enclosed between two quotation."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p02n01i02746arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2748.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2748.vhd
new file mode 100644
index 0000000..f86580c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2748.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2748.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p02n01i02748ent IS
+END c13s07b00x00p02n01i02748ent;
+
+ARCHITECTURE c13s07b00x00p02n01i02748arch OF c13s07b00x00p02n01i02748ent IS
+  type arr is array (1 to 5) of bit;
+  constant C1 : arr := "00_1_11";       -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p02n01i02748 - Missing Base specifier." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p02n01i02748arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2749.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2749.vhd
new file mode 100644
index 0000000..4580be9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2749.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2749.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p03n01i02749ent IS
+END c13s07b00x00p03n01i02749ent;
+
+ARCHITECTURE c13s07b00x00p03n01i02749arch OF c13s07b00x00p03n01i02749ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector (1 to 8) := b"_0101_0101";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p03n01i02749 - Leading underscores are not allowed in bit values."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p03n01i02749arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc275.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc275.vhd
new file mode 100644
index 0000000..b80748a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc275.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc275.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p07n01i00275ent IS
+END c03s01b03x00p07n01i00275ent;
+
+ARCHITECTURE c03s01b03x00p07n01i00275arch OF c03s01b03x00p07n01i00275ent IS
+  type twos_complement_integer1 is range -32768 to 0;
+  type twos_complement_integer2 is range 0 to 32767;
+  type J is
+    range twos_complement_integer1 to twos_complement_integer2
+    units           --  Failure_here
+      A;
+      B = 10 A;
+      C = 10 B;
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p07n01i00275 - The bounds in the range constraint are not locally static expressions."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p07n01i00275arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2750.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2750.vhd
new file mode 100644
index 0000000..c42683d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2750.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2750.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p03n01i02750ent IS
+END c13s07b00x00p03n01i02750ent;
+
+ARCHITECTURE c13s07b00x00p03n01i02750arch OF c13s07b00x00p03n01i02750ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector (1 to 8) := b"0101__0101";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p03n01i02750 - Consecutive underscores are not allowed in bit values."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p03n01i02750arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2751.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2751.vhd
new file mode 100644
index 0000000..743a503
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2751.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2751.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p03n01i02751ent IS
+END c13s07b00x00p03n01i02751ent;
+
+ARCHITECTURE c13s07b00x00p03n01i02751arch OF c13s07b00x00p03n01i02751ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector (1 to 8) := b"0101_0101_";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p03n01i02751 - Trailing underscores are not allowed in bit values."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p03n01i02751arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2752.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2752.vhd
new file mode 100644
index 0000000..3e990c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2752.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2752.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p03n01i02752ent IS
+END c13s07b00x00p03n01i02752ent;
+
+ARCHITECTURE c13s07b00x00p03n01i02752arch OF c13s07b00x00p03n01i02752ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector (1 to 8) := b"";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p03n01i02752 - Bit string must contain at least one digit.(Test for base specifier of B)" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p03n01i02752arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2753.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2753.vhd
new file mode 100644
index 0000000..862de76
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2753.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2753.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p03n01i02753ent IS
+END c13s07b00x00p03n01i02753ent;
+
+ARCHITECTURE c13s07b00x00p03n01i02753arch OF c13s07b00x00p03n01i02753ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector (1 to 8) := o"";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p03n01i02753 - Bit string must contain at least one digit.(Test for base specifier of O)" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p03n01i02753arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2754.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2754.vhd
new file mode 100644
index 0000000..040fada
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2754.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2754.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p03n01i02754ent IS
+END c13s07b00x00p03n01i02754ent;
+
+ARCHITECTURE c13s07b00x00p03n01i02754arch OF c13s07b00x00p03n01i02754ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector (1 to 8) := x"";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p03n01i02754 - Bit string must contain at least one digit.(Test for base specifier of X)" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p03n01i02754arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2755.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2755.vhd
new file mode 100644
index 0000000..5054ed9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2755.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2755.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p03n01i02755ent IS
+END c13s07b00x00p03n01i02755ent;
+
+ARCHITECTURE c13s07b00x00p03n01i02755arch OF c13s07b00x00p03n01i02755ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector (1 to 8) := b"0101 0101";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p03n01i02755 - Spaces are not allowed in bit string." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p03n01i02755arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2756.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2756.vhd
new file mode 100644
index 0000000..64e599d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2756.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2756.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p03n01i02756ent IS
+END c13s07b00x00p03n01i02756ent;
+
+ARCHITECTURE c13s07b00x00p03n01i02756arch OF c13s07b00x00p03n01i02756ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector (1 to 8) := b"0101.0101";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p03n01i02756 - Decimal points are not allowed in bit string." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p03n01i02756arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2757.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2757.vhd
new file mode 100644
index 0000000..bbe6549
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2757.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2757.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p03n01i02757ent IS
+END c13s07b00x00p03n01i02757ent;
+
+ARCHITECTURE c13s07b00x00p03n01i02757arch OF c13s07b00x00p03n01i02757ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector (1 to 8) := b"'0''1''0''1''0''1''0''1'";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p03n01i02757 - Apostrophes are not allowed in bit string." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p03n01i02757arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2762.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2762.vhd
new file mode 100644
index 0000000..7a85726
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2762.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2762.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p06n01i02762ent IS
+END c13s07b00x00p06n01i02762ent;
+
+ARCHITECTURE c13s07b00x00p06n01i02762arch OF c13s07b00x00p06n01i02762ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant clear : bit_vector := B"0010_1020";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p06n01i02762d - The extended digits in the bit value are restricted to 0 to 1 for the base specifier `B'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p06n01i02762arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2763.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2763.vhd
new file mode 100644
index 0000000..fd578f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2763.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2763.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p06n02i02763ent IS
+END c13s07b00x00p06n02i02763ent;
+
+ARCHITECTURE c13s07b00x00p06n02i02763arch OF c13s07b00x00p06n02i02763ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant empty ; bit_vector := O"058";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p06n02i02763 - For the base specifier `O', the extended digits are restricted to the digits 0 through 7."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p06n02i02763arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2764.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2764.vhd
new file mode 100644
index 0000000..dface5a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2764.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2764.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p06n03i02764ent IS
+END c13s07b00x00p06n03i02764ent;
+
+ARCHITECTURE c13s07b00x00p06n03i02764arch OF c13s07b00x00p06n03i02764ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant null_value : bit_vector := X"2AG";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s07b00x00p06n03i02764 - For the base specifier `X', the extended digits are restricted to '0' to 'F'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p06n03i02764arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2766.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2766.vhd
new file mode 100644
index 0000000..40999d8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2766.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2766.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s07b00x00p07n01i02766ent IS
+END c13s07b00x00p07n01i02766ent;
+
+ARCHITECTURE c13s07b00x00p07n01i02766arch OF c13s07b00x00p07n01i02766ent IS
+  constant clear : bit_vector := B"100_113_101";    -- failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c13s07b00x00p07n01i02766 - Only bit values are allowed when the base specifier is B."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s07b00x00p07n01i02766arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2770.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2770.vhd
new file mode 100644
index 0000000..94aef94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2770.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2770.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s08b00x00p01n01i02770ent IS
+END c13s08b00x00p01n01i02770ent;
+
+ARCHITECTURE c13s08b00x00p01n01i02770arch OF c13s08b00x00p01n01i02770ent IS
+
+--This is an
+  error.
+--ERROR: COMMENTS MUST BE ON ONE LINE
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s08b00x00p01n01i02770 - Comments must be on one line."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s08b00x00p01n01i02770arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2772.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2772.vhd
new file mode 100644
index 0000000..c467db2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2772.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2772.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ABS is
+end ABS;
+
+ENTITY c13s09b00x00p99n01i02772ent IS
+END c13s09b00x00p99n01i02772ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02772arch OF c13s09b00x00p99n01i02772ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02772 - Reserved word ABS can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02772arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2773.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2773.vhd
new file mode 100644
index 0000000..ffe3016
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2773.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2773.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ACCESS is
+end ACCESS;
+
+ENTITY c13s09b00x00p99n01i02773ent IS
+END c13s09b00x00p99n01i02773ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02773arch OF c13s09b00x00p99n01i02773ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02773 - Reserved word ACCESS can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02773arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2774.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2774.vhd
new file mode 100644
index 0000000..07e9854
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2774.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2774.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity AFTER is
+end AFTER;
+
+ENTITY c13s09b00x00p99n01i02774ent IS
+END c13s09b00x00p99n01i02774ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02774arch OF c13s09b00x00p99n01i02774ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02774 - Reserved word AFTER can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02774arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2775.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2775.vhd
new file mode 100644
index 0000000..e6df1e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2775.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2775.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ALIAS is
+end ALIAS;
+
+ENTITY c13s09b00x00p99n01i02775ent IS
+END c13s09b00x00p99n01i02775ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02775arch OF c13s09b00x00p99n01i02775ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02775 - Reserved word ALIAS can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02775arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2776.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2776.vhd
new file mode 100644
index 0000000..2ea0304
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2776.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2776.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ALL is
+end ALL;
+
+ENTITY c13s09b00x00p99n01i02776ent IS
+END c13s09b00x00p99n01i02776ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02776arch OF c13s09b00x00p99n01i02776ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02776 - Reserved word ALL can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02776arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2777.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2777.vhd
new file mode 100644
index 0000000..5eda80e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2777.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2777.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity AND is
+end AND;
+
+ENTITY c13s09b00x00p99n01i02777ent IS
+END c13s09b00x00p99n01i02777ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02777arch OF c13s09b00x00p99n01i02777ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02777 - Reserved word AND can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02777arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2778.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2778.vhd
new file mode 100644
index 0000000..94aa9b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2778.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2778.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ARCHITECTURE is
+end ARCHITECTURE;
+
+ENTITY c13s09b00x00p99n01i02778ent IS
+END c13s09b00x00p99n01i02778ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02778arch OF c13s09b00x00p99n01i02778ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02778 - Reserved word ARCHITECTURE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02778arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2779.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2779.vhd
new file mode 100644
index 0000000..0f3033a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2779.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2779.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ARRAY is
+end ARRAY;
+
+ENTITY c13s09b00x00p99n01i02779ent IS
+END c13s09b00x00p99n01i02779ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02779arch OF c13s09b00x00p99n01i02779ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02779 - Reserved word ARRAY can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02779_arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2780.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2780.vhd
new file mode 100644
index 0000000..f496c0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2780.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2780.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ASSERT is
+end ASSERT;
+
+ENTITY c13s09b00x00p99n01i02780ent IS
+END c13s09b00x00p99n01i02780ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02780arch OF c13s09b00x00p99n01i02780ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02780 - Reserved word ASSERT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02780arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2781.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2781.vhd
new file mode 100644
index 0000000..08127d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2781.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2781.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ATTRIBUTE is
+end ATTRIBUTE;
+
+ENTITY c13s09b00x00p99n01i02781ent IS
+END c13s09b00x00p99n01i02781ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02781arch OF c13s09b00x00p99n01i02781ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02781 - Reserved word ATTRIBUTE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02781arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2782.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2782.vhd
new file mode 100644
index 0000000..6b21071
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2782.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2782.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity BEGIN is
+             end BEGIN;
+
+                      ENTITY c13s09b00x00p99n01i02782ent IS
+                      END c13s09b00x00p99n01i02782ent;
+
+                      ARCHITECTURE c13s09b00x00p99n01i02782arch OF c13s09b00x00p99n01i02782ent IS
+
+                      BEGIN
+                        TESTING: PROCESS
+                        BEGIN
+                          assert FALSE 
+                            report "***FAILED TEST: c13s09b00x00p99n01i02782 - Reserved word BEGIN can not be used as an entity name."
+                            severity ERROR;
+                          wait;
+                        END PROCESS TESTING;
+
+                      END c13s09b00x00p99n01i02782arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2783.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2783.vhd
new file mode 100644
index 0000000..ca03b0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2783.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2783.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity BLOCK is
+             end BLOCK;
+
+             ENTITY c13s09b00x00p99n01i02783ent IS
+             END c13s09b00x00p99n01i02783ent;
+
+             ARCHITECTURE c13s09b00x00p99n01i02783arch OF c13s09b00x00p99n01i02783ent IS
+
+             BEGIN
+               TESTING: PROCESS
+               BEGIN
+                 assert FALSE 
+                   report "***FAILED TEST: c13s09b00x00p99n01i02783 - Reserved word BLOCK can not be used as an entity name."
+                   severity ERROR;
+                 wait;
+               END PROCESS TESTING;
+
+             END c13s09b00x00p99n01i02783arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2784.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2784.vhd
new file mode 100644
index 0000000..2cac20c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2784.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2784.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity BODY is
+end BODY;
+
+ENTITY c13s09b00x00p99n01i02784ent IS
+END c13s09b00x00p99n01i02784ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02784arch OF c13s09b00x00p99n01i02784ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02784 - Reserved word BODY can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02784arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2785.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2785.vhd
new file mode 100644
index 0000000..02ab129
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2785.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2785.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity BUFFER is
+end BUFFER;
+
+ENTITY c13s09b00x00p99n01i02785ent IS
+END c13s09b00x00p99n01i02785ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02785arch OF c13s09b00x00p99n01i02785ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02785 - Reserved word BUFFER can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02785arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2786.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2786.vhd
new file mode 100644
index 0000000..125de41
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2786.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2786.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity BUS is
+end BUS;
+
+ENTITY c13s09b00x00p99n01i02786ent IS
+END c13s09b00x00p99n01i02786ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02786arch OF c13s09b00x00p99n01i02786ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02786 - Reserved word BUS can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02786arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2787.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2787.vhd
new file mode 100644
index 0000000..de246c3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2787.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2787.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity CASE is
+end CASE;
+
+ENTITY c13s09b00x00p99n01i02787ent IS
+END c13s09b00x00p99n01i02787ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02787arch OF c13s09b00x00p99n01i02787ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02787 - Reserved word CASE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02787arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2788.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2788.vhd
new file mode 100644
index 0000000..c8e1ba0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2788.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2788.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity COMPONENT is
+       end COMPONENT;
+
+       ENTITY c13s09b00x00p99n01i02788ent IS
+       END c13s09b00x00p99n01i02788ent;
+
+       ARCHITECTURE c13s09b00x00p99n01i02788arch OF c13s09b00x00p99n01i02788ent IS
+
+       BEGIN
+         TESTING: PROCESS
+         BEGIN
+           assert FALSE 
+             report "***FAILED TEST: c13s09b00x00p99n01i02788 - Reserved word COMPONENT can not be used as an entity name."
+             severity ERROR;
+           wait;
+         END PROCESS TESTING;
+
+       END c13s09b00x00p99n01i02788arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2789.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2789.vhd
new file mode 100644
index 0000000..5cfa27a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2789.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2789.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity CONFIGURATION is
+end CONFIGURATION;
+
+ENTITY c13s09b00x00p99n01i02789ent IS
+END c13s09b00x00p99n01i02789ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02789arch OF c13s09b00x00p99n01i02789ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02789 - Reserved word CONFIGURATION can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02789arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2790.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2790.vhd
new file mode 100644
index 0000000..aa56a10
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2790.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2790.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity CONSTANT is
+end CONSTANT;
+
+ENTITY c13s09b00x00p99n01i02790ent IS
+END c13s09b00x00p99n01i02790ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02790arch OF c13s09b00x00p99n01i02790ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02790 - Reserved word CONSTANT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02790arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2791.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2791.vhd
new file mode 100644
index 0000000..e9e98f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2791.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2791.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity DISCONNECT is
+end DISCONNECT;
+
+ENTITY c13s09b00x00p99n01i02791ent IS
+END c13s09b00x00p99n01i02791ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02791arch OF c13s09b00x00p99n01i02791ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02791 - Reserved word DISCONNECT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02791arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2792.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2792.vhd
new file mode 100644
index 0000000..fa66029
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2792.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2792.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity DOWNTO is
+end DOWNTO;
+
+ENTITY c13s09b00x00p99n01i02792ent IS
+END c13s09b00x00p99n01i02792ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02792arch OF c13s09b00x00p99n01i02792ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02792 - Reserved word DOWNTO can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02792arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2793.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2793.vhd
new file mode 100644
index 0000000..6c77ee5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2793.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2793.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ELSE is
+            end ELSE;
+
+                    ENTITY c13s09b00x00p99n01i02793ent IS
+                    END c13s09b00x00p99n01i02793ent;
+
+                    ARCHITECTURE c13s09b00x00p99n01i02793arch OF c13s09b00x00p99n01i02793ent IS
+
+                    BEGIN
+                      TESTING: PROCESS
+                      BEGIN
+                        assert FALSE 
+                          report "***FAILED TEST: c13s09b00x00p99n01i02793 - Reserved word ELSE can not be used as an entity name."
+                          severity ERROR;
+                        wait;
+                      END PROCESS TESTING;
+
+                    END c13s09b00x00p99n01i02793arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2794.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2794.vhd
new file mode 100644
index 0000000..a5dacb1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2794.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2794.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ELSIF is
+end ELSIF;
+
+ENTITY c13s09b00x00p99n01i02794ent IS
+END c13s09b00x00p99n01i02794ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02794arch OF c13s09b00x00p99n01i02794ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02794 - Reserved word ELSIF can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02794arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2795.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2795.vhd
new file mode 100644
index 0000000..eee8ca6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2795.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2795.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity END is
+end END;
+
+ENTITY c13s09b00x00p99n01i02795ent IS
+END c13s09b00x00p99n01i02795ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02795arch OF c13s09b00x00p99n01i02795ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02795 - Reserved word END can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02795arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2796.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2796.vhd
new file mode 100644
index 0000000..6b4307f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2796.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2796.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ENTITY is
+end ENTITY;
+
+ENTITY c13s09b00x00p99n01i02796ent IS
+END c13s09b00x00p99n01i02796ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02796arch OF c13s09b00x00p99n01i02796ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02796 - Reserved word ENTITY can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02796arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2797.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2797.vhd
new file mode 100644
index 0000000..fe53dbd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2797.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2797.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity EXIT is
+end EXIT;
+
+ENTITY c13s09b00x00p99n01i02797ent IS
+END c13s09b00x00p99n01i02797ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02797arch OF c13s09b00x00p99n01i02797ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02797 - Reserved word EXIT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02797arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2798.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2798.vhd
new file mode 100644
index 0000000..93e66b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2798.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2798.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity FILE is
+end FILE;
+
+ENTITY c13s09b00x00p99n01i02798ent IS
+END c13s09b00x00p99n01i02798ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02798arch OF c13s09b00x00p99n01i02798ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02798 - Reserved word FILE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02798arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2799.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2799.vhd
new file mode 100644
index 0000000..0fedb76
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2799.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2799.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity FOR is
+end FOR;
+
+ENTITY c13s09b00x00p99n01i02799ent IS
+END c13s09b00x00p99n01i02799ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02799arch OF c13s09b00x00p99n01i02799ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02799 - Reserved word FOR can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02799arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc28.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc28.vhd
new file mode 100644
index 0000000..acb64e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc28.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc28.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s02b00x00p11n01i00028ent IS
+END c04s02b00x00p11n01i00028ent;
+
+ARCHITECTURE c04s02b00x00p11n01i00028arch OF c04s02b00x00p11n01i00028ent IS
+  type MVL is ('0', '1', 'Z') ;
+  type MVL_VEC is array (positive range <>) of MVL;
+  function tristate (X:MVL_VEC) return MVL is
+  begin
+    return '1';
+  end tristate ;
+  type    T1  is access MVL ;
+  subtype ST1 is tristate T1;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s02b00x00p11n01i00028- Subtype indication denoting an access type can not contain a resolution function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s02b00x00p11n01i00028arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc280.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc280.vhd
new file mode 100644
index 0000000..a94e1fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc280.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc280.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p08n02i00280ent IS
+END c03s01b03x00p08n02i00280ent;
+
+ARCHITECTURE c03s01b03x00p08n02i00280arch OF c03s01b03x00p08n02i00280ent IS
+  type J is                 -- physical type decl
+    range 0 to 1000
+    units
+      A;
+      B = 10.1 A;       -- Failure_here.
+      C = 10 B;
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p08n02i00280 - Unit names declared in secondary unit declarations must be integral multiples of the base unit ."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p08n02i00280arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2800.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2800.vhd
new file mode 100644
index 0000000..173d167
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2800.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2800.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity FUNCTION is
+end FUNCTION;
+
+ENTITY c13s09b00x00p99n01i02800ent IS
+END c13s09b00x00p99n01i02800ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02800arch OF c13s09b00x00p99n01i02800ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02800 - Reserved word FUNCTION can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02800arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2801.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2801.vhd
new file mode 100644
index 0000000..37906b8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2801.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2801.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity GENERATE is
+                end GENERATE;
+
+                ENTITY c13s09b00x00p99n01i02801ent IS
+                END c13s09b00x00p99n01i02801ent;
+
+                ARCHITECTURE c13s09b00x00p99n01i02801arch OF c13s09b00x00p99n01i02801ent IS
+
+                BEGIN
+                  TESTING: PROCESS
+                  BEGIN
+                    assert FALSE 
+                      report "***FAILED TEST: c13s09b00x00p99n01i02801 - Reserved word GENERATE can not be used as an entity name."
+                      severity ERROR;
+                    wait;
+                  END PROCESS TESTING;
+
+                END c13s09b00x00p99n01i02801arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2802.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2802.vhd
new file mode 100644
index 0000000..e6da9f0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2802.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2802.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity GENERIC is
+end GENERIC;
+
+ENTITY c13s09b00x00p99n01i02802ent IS
+END c13s09b00x00p99n01i02802ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02802arch OF c13s09b00x00p99n01i02802ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02802 - Reserved word GENERIC can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02802arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2803.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2803.vhd
new file mode 100644
index 0000000..fe35015
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2803.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2803.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity GUARDED is
+end GUARDED;
+
+ENTITY c13s09b00x00p99n01i02803ent IS
+END c13s09b00x00p99n01i02803ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02803arch OF c13s09b00x00p99n01i02803ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02803 - Reserved word GUARDED can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02803arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2804.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2804.vhd
new file mode 100644
index 0000000..c486934
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2804.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2804.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity IF is
+       end IF;
+
+       ENTITY c13s09b00x00p99n01i02804ent IS
+       END c13s09b00x00p99n01i02804ent;
+
+       ARCHITECTURE c13s09b00x00p99n01i02804arch OF c13s09b00x00p99n01i02804ent IS
+
+       BEGIN
+         TESTING: PROCESS
+         BEGIN
+           assert FALSE 
+             report "***FAILED TEST: c13s09b00x00p99n01i02804 - Reserved word IF can not be used as an entity name."
+             severity ERROR;
+           wait;
+         END PROCESS TESTING;
+
+       END c13s09b00x00p99n01i02804arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2805.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2805.vhd
new file mode 100644
index 0000000..fd32a13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2805.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2805.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity IN is
+end IN;
+
+ENTITY c13s09b00x00p99n01i02805ent IS
+END c13s09b00x00p99n01i02805ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02805arch OF c13s09b00x00p99n01i02805ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02805 - Reserved word IN can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02805arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2806.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2806.vhd
new file mode 100644
index 0000000..68a45f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2806.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2806.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity INOUT is
+end INOUT;
+
+ENTITY c13s09b00x00p99n01i02806ent IS
+END c13s09b00x00p99n01i02806ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02806arch OF c13s09b00x00p99n01i02806ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02806 - Reserved word INOUT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02806arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2807.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2807.vhd
new file mode 100644
index 0000000..fb0617e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2807.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2807.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity IS is
+          end IS;
+
+          ENTITY c13s09b00x00p99n01i02807ent IS
+          END c13s09b00x00p99n01i02807ent;
+
+          ARCHITECTURE c13s09b00x00p99n01i02807arch OF c13s09b00x00p99n01i02807ent IS
+
+          BEGIN
+            TESTING: PROCESS
+            BEGIN
+              assert FALSE 
+                report "***FAILED TEST: c13s09b00x00p99n01i02807 - Reserved word IS can not be used as an entity name."
+                severity ERROR;
+              wait;
+            END PROCESS TESTING;
+
+          END c13s09b00x00p99n01i02807arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2808.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2808.vhd
new file mode 100644
index 0000000..f820fdd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2808.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2808.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity LABEL is
+end LABEL;
+
+ENTITY c13s09b00x00p99n01i02808ent IS
+END c13s09b00x00p99n01i02808ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02808arch OF c13s09b00x00p99n01i02808ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02808 - Reserved word LABEL can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02808arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2809.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2809.vhd
new file mode 100644
index 0000000..474b4f0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2809.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2809.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity LIBRARY is
+end LIBRARY;
+
+ENTITY c13s09b00x00p99n01i02809ent IS
+END c13s09b00x00p99n01i02809ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02809arch OF c13s09b00x00p99n01i02809ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02809 - Reserved word LIBRARY can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02809arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2810.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2810.vhd
new file mode 100644
index 0000000..599f88d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2810.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2810.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity LINKAGE is
+end LINKAGE;
+
+ENTITY c13s09b00x00p99n01i02810ent IS
+END c13s09b00x00p99n01i02810ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02810arch OF c13s09b00x00p99n01i02810ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02810 - Reserved word LINKAGE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02810arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2811.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2811.vhd
new file mode 100644
index 0000000..d629c6b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2811.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2811.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity LOOP is
+            end LOOP;
+
+            ENTITY c13s09b00x00p99n01i02811ent IS
+            END c13s09b00x00p99n01i02811ent;
+
+            ARCHITECTURE c13s09b00x00p99n01i02811arch OF c13s09b00x00p99n01i02811ent IS
+
+            BEGIN
+              TESTING: PROCESS
+              BEGIN
+                assert FALSE 
+                  report "***FAILED TEST: c13s09b00x00p99n01i02811 - Reserved word LOOP can not be used as an entity name."
+                  severity ERROR;
+                wait;
+              END PROCESS TESTING;
+
+            END c13s09b00x00p99n01i02811arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2812.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2812.vhd
new file mode 100644
index 0000000..34eeea2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2812.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2812.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity NAND is
+end NAND;
+
+ENTITY c13s09b00x00p99n01i02812ent IS
+END c13s09b00x00p99n01i02812ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02812arch OF c13s09b00x00p99n01i02812ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02812 - Reserved word NAND can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02812arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2813.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2813.vhd
new file mode 100644
index 0000000..61e08ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2813.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2813.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity NEW is
+end NEW;
+
+ENTITY c13s09b00x00p99n01i02813ent IS
+END c13s09b00x00p99n01i02813ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02813arch OF c13s09b00x00p99n01i02813ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02813 - Reserved word NEW can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02813arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2814.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2814.vhd
new file mode 100644
index 0000000..23ed8da
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2814.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2814.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity NEXT is
+end NEXT;
+
+ENTITY c13s09b00x00p99n01i02814ent IS
+END c13s09b00x00p99n01i02814ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02814arch OF c13s09b00x00p99n01i02814ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02814 - Reserved word NEXT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02814
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2815.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2815.vhd
new file mode 100644
index 0000000..895ed36
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2815.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2815.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity NOR is
+end NOR;
+
+ENTITY c13s09b00x00p99n01i02815ent IS
+END c13s09b00x00p99n01i02815ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02815arch OF c13s09b00x00p99n01i02815ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02815 - Reserved word NOR can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02815arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2816.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2816.vhd
new file mode 100644
index 0000000..bf7afad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2816.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2816.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity NOT is
+end NOT;
+
+ENTITY c13s09b00x00p99n01i02816ent IS
+END c13s09b00x00p99n01i02816ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02816arch OF c13s09b00x00p99n01i02816ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02816 - Reserved word NOT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02816arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2817.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2817.vhd
new file mode 100644
index 0000000..170c780
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2817.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2817.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity NULL is
+end NULL;
+
+ENTITY c13s09b00x00p99n01i02817ent IS
+END c13s09b00x00p99n01i02817ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02817arch OF c13s09b00x00p99n01i02817ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02817 - Reserved word NULL can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02817arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2818.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2818.vhd
new file mode 100644
index 0000000..ab9d301
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2818.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2818.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity OF is
+end OF;
+
+ENTITY c13s09b00x00p99n01i02818ent IS
+END c13s09b00x00p99n01i02818ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02818arch OF c13s09b00x00p99n01i02818ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02818 - Reserved word OF can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02818arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2819.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2819.vhd
new file mode 100644
index 0000000..f9d48c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2819.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2819.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity ON is
+end ON;
+
+ENTITY c13s09b00x00p99n01i02819ent IS
+END c13s09b00x00p99n01i02819ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02819arch OF c13s09b00x00p99n01i02819ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02819 - Reserved word ON can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02819arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc282.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc282.vhd
new file mode 100644
index 0000000..6d9fae5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc282.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc282.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p08n02i00282ent IS
+END c03s01b03x00p08n02i00282ent;
+
+ARCHITECTURE c03s01b03x00p08n02i00282arch OF c03s01b03x00p08n02i00282ent IS
+  type time is range 0 to 1E8 units
+                                fs;
+-- -- Failure_here: min is not defined
+                                ps = 10 min;
+                              end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p08n02i00282 - Unit names declared in secondary unit declarations must be integral multiples of the base unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p08n02i00282arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2820.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2820.vhd
new file mode 100644
index 0000000..fb11932
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2820.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2820.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity OPEN is
+end OPEN;
+
+ENTITY c13s09b00x00p99n01i02820ent IS
+END c13s09b00x00p99n01i02820ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02820arch OF c13s09b00x00p99n01i02820ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02820 - Reserved word OPEN can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02820arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2821.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2821.vhd
new file mode 100644
index 0000000..31df827
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2821.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2821.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity OR is
+end OR;
+
+ENTITY c13s09b00x00p99n01i02821ent IS
+END c13s09b00x00p99n01i02821ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02821arch OF c13s09b00x00p99n01i02821ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02821 - Reserved word OR can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02821arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2822.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2822.vhd
new file mode 100644
index 0000000..132aad5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2822.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2822.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity OTHERS is
+end OTHERS;
+
+ENTITY c13s09b00x00p99n01i02822ent IS
+END c13s09b00x00p99n01i02822ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02822arch OF c13s09b00x00p99n01i02822ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02822 - Reserved word OTHERS can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02822arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2823.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2823.vhd
new file mode 100644
index 0000000..f3c352c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2823.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2823.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity OUT is
+end OUT;
+
+ENTITY c13s09b00x00p99n01i02823ent IS
+END c13s09b00x00p99n01i02823ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02823arch OF c13s09b00x00p99n01i02823ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02823 - Reserved word OUT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02823arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2824.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2824.vhd
new file mode 100644
index 0000000..733c8fb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2824.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2824.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity PACKAGE is
+end PACKAGE;
+
+ENTITY c13s09b00x00p99n01i02824ent IS
+END c13s09b00x00p99n01i02824ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02824arch OF c13s09b00x00p99n01i02824ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02824 - Reserved word PACKAGE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02824arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2825.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2825.vhd
new file mode 100644
index 0000000..bec1f3b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2825.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2825.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity PORT is
+end PORT;
+
+ENTITY c13s09b00x00p99n01i02825ent IS
+END c13s09b00x00p99n01i02825ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02825arch OF c13s09b00x00p99n01i02825ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02825 - Reserved word PORT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02825arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2826.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2826.vhd
new file mode 100644
index 0000000..835ae52
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2826.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2826.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity PROCEDURE is
+end PROCEDURE;
+
+ENTITY c13s09b00x00p99n01i02826ent IS
+END c13s09b00x00p99n01i02826ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02826arch OF c13s09b00x00p99n01i02826ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02826 - Reserved word PROCEDURE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02826arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2827.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2827.vhd
new file mode 100644
index 0000000..13c7e47
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2827.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2827.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity PROCESS is
+               end PROCESS;
+
+               ENTITY c13s09b00x00p99n01i02827ent IS
+               END c13s09b00x00p99n01i02827ent;
+
+               ARCHITECTURE c13s09b00x00p99n01i02827arch OF c13s09b00x00p99n01i02827ent IS
+
+               BEGIN
+                 TESTING: PROCESS
+                 BEGIN
+                   assert FALSE 
+                     report "***FAILED TEST: c13s09b00x00p99n01i02827 - Reserved word PROCESS can not be used as an entity name."
+                     severity ERROR;
+                   wait;
+                 END PROCESS TESTING;
+
+               END c13s09b00x00p99n01i02827arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2828.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2828.vhd
new file mode 100644
index 0000000..8104ab5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2828.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2828.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity MAP is
+end MAP;
+
+ENTITY c13s09b00x00p98n01i02828ent IS
+END c13s09b00x00p98n01i02828ent;
+
+ARCHITECTURE c13s09b00x00p98n01i02828arch OF c13s09b00x00p98n01i02828ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p98n01i02828 - Reserved word MAP can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p98n01i02828arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2829.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2829.vhd
new file mode 100644
index 0000000..e7568dd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2829.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2829.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity MOD is
+end MOD;
+
+ENTITY c13s09b00x00p99n01i02829ent IS
+END c13s09b00x00p99n01i02829ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02829arch OF c13s09b00x00p99n01i02829ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02829 - Reserved word MOD can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02829arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc283.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc283.vhd
new file mode 100644
index 0000000..f77bcf9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc283.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc283.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p10n01i00283ent IS
+END c03s01b03x00p10n01i00283ent;
+
+ARCHITECTURE c03s01b03x00p10n01i00283arch OF c03s01b03x00p10n01i00283ent IS
+  type J is               -- physical type decl
+    range 0 to 1000
+    units
+      A;
+      B = 10 A;
+      C = 10.1 B;     -- Failure_here
+      D = 10 C;
+    end units;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p10n01i00283 - Abstract literal portion of a physical literal appearing in a secondary unit declaration must be integer literal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p10n01i00283arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2830.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2830.vhd
new file mode 100644
index 0000000..1af5cbf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2830.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2830.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity RANGE is
+end RANGE;
+
+ENTITY c13s09b00x00p99n01i02830ent IS
+END c13s09b00x00p99n01i02830ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02830arch OF c13s09b00x00p99n01i02830ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02830 - Reserved word RANGE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02830arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2831.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2831.vhd
new file mode 100644
index 0000000..3dab707
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2831.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2831.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity RECORD is
+              end RECORD;
+
+              ENTITY c13s09b00x00p99n01i02831ent IS
+              END c13s09b00x00p99n01i02831ent;
+
+              ARCHITECTURE c13s09b00x00p99n01i02831arch OF c13s09b00x00p99n01i02831ent IS
+
+              BEGIN
+                TESTING: PROCESS
+                BEGIN
+                  assert FALSE 
+                    report "***FAILED TEST: c13s09b00x00p99n01i02831 - Reserved word RECORD can not be used as an entity name."
+                    severity ERROR;
+                  wait;
+                END PROCESS TESTING;
+
+              END c13s09b00x00p99n01i02831arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2832.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2832.vhd
new file mode 100644
index 0000000..2380165
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2832.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2832.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity REM is
+end REM;
+
+ENTITY c13s09b00x00p99n01i02832ent IS
+END c13s09b00x00p99n01i02832ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02832arch OF c13s09b00x00p99n01i02832ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02832 - Reserved word REM can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02832arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2833.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2833.vhd
new file mode 100644
index 0000000..250cf00
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2833.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2833.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity REPORT is
+end REPORT;
+
+ENTITY c13s09b00x00p99n01i02833ent IS
+END c13s09b00x00p99n01i02833ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02833arch OF c13s09b00x00p99n01i02833ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02833 - Reserved word REPORT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02833arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2834.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2834.vhd
new file mode 100644
index 0000000..00a7627
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2834.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2834.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity RETURN is
+end RETURN;
+
+ENTITY c13s09b00x00p99n01i02834ent IS
+END c13s09b00x00p99n01i02834ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02834arch OF c13s09b00x00p99n01i02834ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02834 - Reserved word RETURN can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02834arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2835.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2835.vhd
new file mode 100644
index 0000000..0da6c43
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2835.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2835.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity SELECT is
+end SELECT;
+
+ENTITY c13s09b00x00p99n01i02835ent IS
+END c13s09b00x00p99n01i02835ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02835arch OF c13s09b00x00p99n01i02835ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02835 - Reserved word SELECT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02835arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2836.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2836.vhd
new file mode 100644
index 0000000..f8e0479
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2836.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2836.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity SEVERITY is
+end SEVERITY;
+
+ENTITY c13s09b00x00p99n01i02836ent IS
+END c13s09b00x00p99n01i02836ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02836arch OF c13s09b00x00p99n01i02836ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02836 - Reserved word SEVERITY can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02836arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2837.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2837.vhd
new file mode 100644
index 0000000..5985560
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2837.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2837.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity SIGNAL is
+end SIGNAL;
+
+ENTITY c13s09b00x00p99n01i02837ent IS
+END c13s09b00x00p99n01i02837ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02837arch OF c13s09b00x00p99n01i02837ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02837 - Reserved word SIGNAL can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02837arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2838.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2838.vhd
new file mode 100644
index 0000000..5d2576a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2838.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2838.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity SUBTYPE is
+end SUBTYPE;
+
+ENTITY c13s09b00x00p99n01i02838ent IS
+END c13s09b00x00p99n01i02838ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02838arch OF c13s09b00x00p99n01i02838ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02838 - Reserved word SUBTYPE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02838arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2839.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2839.vhd
new file mode 100644
index 0000000..7875c90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2839.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2839.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity THEN is
+            end THEN;
+
+                    ENTITY c13s09b00x00p99n01i02839ent IS
+                    END c13s09b00x00p99n01i02839ent;
+
+                    ARCHITECTURE c13s09b00x00p99n01i02839arch OF c13s09b00x00p99n01i02839ent IS
+
+                    BEGIN
+                      TESTING: PROCESS
+                      BEGIN
+                        assert FALSE 
+                          report "***FAILED TEST: c13s09b00x00p99n01i02839 - Reserved word THEN can not be used as an entity name."
+                          severity ERROR;
+                        wait;
+                      END PROCESS TESTING;
+
+                    END c13s09b00x00p99n01i02839arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2840.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2840.vhd
new file mode 100644
index 0000000..f3c37a6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2840.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2840.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity TO is
+end TO;
+
+ENTITY c13s09b00x00p99n01i02840ent IS
+END c13s09b00x00p99n01i02840ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02840arch OF c13s09b00x00p99n01i02840ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02840 - Reserved word TO can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02840arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2841.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2841.vhd
new file mode 100644
index 0000000..8fbf21c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2841.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2841.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity TRANSPORT is
+end TRANSPORT;
+
+ENTITY c13s09b00x00p99n01i02841ent IS
+END c13s09b00x00p99n01i02841ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02841arch OF c13s09b00x00p99n01i02841ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02841 - Reserved word TRANSPORT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02841arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2842.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2842.vhd
new file mode 100644
index 0000000..5d60282
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2842.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2842.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity TYPE is
+end TYPE;
+
+ENTITY c13s09b00x00p99n01i02842ent IS
+END c13s09b00x00p99n01i02842ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02842arch OF c13s09b00x00p99n01i02842ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02842 - Reserved word TYPE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02842arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2843.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2843.vhd
new file mode 100644
index 0000000..1e81521
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2843.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2843.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity UNITS is
+             end UNITS;
+
+             ENTITY c13s09b00x00p99n01i02843ent IS
+             END c13s09b00x00p99n01i02843ent;
+
+             ARCHITECTURE c13s09b00x00p99n01i02843arch OF c13s09b00x00p99n01i02843ent IS
+
+             BEGIN
+               TESTING: PROCESS
+               BEGIN
+                 assert FALSE 
+                   report "***FAILED TEST: c13s09b00x00p99n01i02843 - Reserved word UNITS can not be used as an entity name."
+                   severity ERROR;
+                 wait;
+               END PROCESS TESTING;
+
+             END c13s09b00x00p99n01i02843arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2844.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2844.vhd
new file mode 100644
index 0000000..9c94a72
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2844.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2844.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity UNTIL is
+end UNTIL;
+
+ENTITY c13s09b00x00p99n01i02844ent IS
+END c13s09b00x00p99n01i02844ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02844arch OF c13s09b00x00p99n01i02844ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02844 - Reserved word UNTIL can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02844arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2845.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2845.vhd
new file mode 100644
index 0000000..f5a950f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2845.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2845.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity USE is
+end USE;
+
+ENTITY c13s09b00x00p99n01i02845ent IS
+END c13s09b00x00p99n01i02845ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02845arch OF c13s09b00x00p99n01i02845ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02845 - Reserved word USE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02845arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2846.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2846.vhd
new file mode 100644
index 0000000..da13fbc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2846.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2846.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity VARIABLE is
+end VARIABLE;
+
+ENTITY c13s09b00x00p99n01i02846ent IS
+END c13s09b00x00p99n01i02846ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02846arch OF c13s09b00x00p99n01i02846ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02846 - Reserved word VARIABLE can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02846arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2847.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2847.vhd
new file mode 100644
index 0000000..d17c0c0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2847.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2847.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity WAIT is
+end WAIT;
+
+ENTITY c13s09b00x00p99n01i02847ent IS
+END c13s09b00x00p99n01i02847ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02847arch OF c13s09b00x00p99n01i02847ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02847 - Reserved word WAIT can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02847arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2848.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2848.vhd
new file mode 100644
index 0000000..036e4f2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2848.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2848.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity WHEN is
+end WHEN;
+
+ENTITY c13s09b00x00p99n01i02848ent IS
+END c13s09b00x00p99n01i02848ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02848arch OF c13s09b00x00p99n01i02848ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02848 - Reserved word WHEN can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02848arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2849.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2849.vhd
new file mode 100644
index 0000000..0f35b37
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2849.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2849.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity WHILE is
+       end WHILE;
+
+       ENTITY c13s09b00x00p99n01i02849ent IS
+       END c13s09b00x00p99n01i02849ent;
+
+       ARCHITECTURE c13s09b00x00p99n01i02849arch OF c13s09b00x00p99n01i02849ent IS
+
+       BEGIN
+         TESTING: PROCESS
+         BEGIN
+           assert FALSE 
+             report "***FAILED TEST: c13s09b00x00p99n01i02849 - Reserved word WHILE can not be used as an entity name."
+             severity ERROR;
+           wait;
+         END PROCESS TESTING;
+
+       END c13s09b00x00p99n01i02849arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2850.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2850.vhd
new file mode 100644
index 0000000..653690b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2850.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2850.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity WITH is
+end WITH;
+
+ENTITY c13s09b00x00p99n01i02850ent IS
+END c13s09b00x00p99n01i02850ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02850arch OF c13s09b00x00p99n01i02850ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02850 - Reserved word WITH can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02850arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2851.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2851.vhd
new file mode 100644
index 0000000..7c9eedb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2851.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2851.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity XOR is
+end XOR;
+
+ENTITY c13s09b00x00p99n01i02851ent IS
+END c13s09b00x00p99n01i02851ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02851arch OF c13s09b00x00p99n01i02851ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02851 - Reserved word XOR can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02851arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2852.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2852.vhd
new file mode 100644
index 0000000..7100550
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2852.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2852.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity REGISTER is
+end REGISTER;
+
+ENTITY c13s09b00x00p99n01i02852ent IS
+END c13s09b00x00p99n01i02852ent;
+
+ARCHITECTURE c13s09b00x00p99n01i02852arch OF c13s09b00x00p99n01i02852ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s09b00x00p99n01i02852 - Reserved word REGISTER can not be used as an entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s09b00x00p99n01i02852arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2855.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2855.vhd
new file mode 100644
index 0000000..9493075
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2855.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2855.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p03n01i02855ent IS
+END c13s10b00x00p03n01i02855ent;
+
+ARCHITECTURE c13s10b00x00p03n01i02855arch OF c13s10b00x00p03n01i02855ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable based_int : integer := 3#12:;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s10b00x00p03n01i02855 - The sharp character (#) of a based literal can be replaced by colons (:), the replacement is done for both occurences.(Here left hand side # sign did not be replaced)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p03n01i02855arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2856.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2856.vhd
new file mode 100644
index 0000000..591a9a0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2856.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2856.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p03n01i02856ent IS
+END c13s10b00x00p03n01i02856ent;
+
+ARCHITECTURE c13s10b00x00p03n01i02856arch OF c13s10b00x00p03n01i02856ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable based_int : integer := 3:12#;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s10b00x00p03n01i02856 - The sharp character (#) of a based literal can be replaced by colons (:), the replacement is done for both occurences.(Here right hand side # sign did not be replaced)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p03n01i02856arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2857.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2857.vhd
new file mode 100644
index 0000000..f31b6be
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2857.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2857.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p04n01i02857ent IS
+END c13s10b00x00p04n01i02857ent;
+
+ARCHITECTURE c13s10b00x00p04n01i02857arch OF c13s10b00x00p04n01i02857ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector(0 to 7) := %01010101";
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s10b00x00p04n01i02857 - Only left hand side quotation mark ("") is replaced by percent character (%)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p04n01i02857arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2858.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2858.vhd
new file mode 100644
index 0000000..b3f7ad8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2858.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2858.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p04n01i02858ent IS
+END c13s10b00x00p04n01i02858ent;
+
+ARCHITECTURE c13s10b00x00p04n01i02858arch OF c13s10b00x00p04n01i02858ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable bit_str : bit_vector(0 to 7) := "01010101%;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c13s10b00x00p04n01i02858 - Only right hand side quotation mark ("") is replaced by percent character (%)."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c13s10b00x00p04n01i02858arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2859.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2859.vhd
new file mode 100644
index 0000000..61da9ec
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2859.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2859.vhd,v 1.1.1.1 2001-08-22 18:20:50 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c13s10b00x00p04n01i02859ent IS
+END c13s10b00x00p04n01i02859ent;
+
+ARCHITECTURE c13s10b00x00p04n01i02859arch OF c13s10b00x00p04n01i02859ent IS
+
+BEGIN
+   TESTING: PROCESS
+   BEGIN
+        assert false
+            report %This string is illegal because of this character ".%
+            severity note ;
+   assert FALSE 
+      report "***FAILED TEST: c13s10b00x00p04n01i02859 - Enclosed sequence of characters contains quotation character." 
+      severity ERROR;
+   wait;
+   END PROCESS TESTING;
+
+END c13s10b00x00p04n01i02859arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2867.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2867.vhd
new file mode 100644
index 0000000..bacaf07
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2867.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2867.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s01b00x00p03n01i02867pkg is
+  function testp (I1:Bit) return bit  --- Failure_here
+end c02s01b00x00p03n01i02867pkg;
+
+package body c02s01b00x00p03n01i02867pkg is
+  function testp(I1:Bit) return bit is
+  begin
+    if (I1 = '1') then
+      return '1';
+    else
+      return '0';
+    end if;
+  end testp;
+end c02s01b00x00p03n01i02867pkg;
+
+
+ENTITY c02s01b00x00p03n01i02867ent IS
+END c02s01b00x00p03n01i02867ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02867arch OF c02s01b00x00p03n01i02867ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b00x00p03n01i02867 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02867arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2869.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2869.vhd
new file mode 100644
index 0000000..aa6c061
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2869.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2869.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02869ent IS
+END c02s01b00x00p03n01i02869ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02869arch OF c02s01b00x00p03n01i02869ent IS
+  procedure (I1:Bit);   --Failure here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b00x00p03n01i02869 - Missing designator." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02869arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2871.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2871.vhd
new file mode 100644
index 0000000..a290c24
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2871.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2871.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p03n01i02871ent IS
+END c02s01b00x00p03n01i02871ent;
+
+ARCHITECTURE c02s01b00x00p03n01i02871arch OF c02s01b00x00p03n01i02871ent IS
+  function testp (I1:Bit) return;  --- Failure_here 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b00x00p03n01i02871 - Missing type mark."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p03n01i02871arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2872.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2872.vhd
new file mode 100644
index 0000000..d4bb2f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2872.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2872.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p06n04i02872ent IS
+END c02s01b00x00p06n04i02872ent;
+
+ARCHITECTURE c02s01b00x00p06n04i02872arch OF c02s01b00x00p06n04i02872ent IS
+  procedure "+" (x: in integer; y: out boolean);  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b00x00p06n04i02872 - A procedure designator must always be an identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p06n04i02872arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2873.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2873.vhd
new file mode 100644
index 0000000..ec59c62
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2873.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2873.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p06n04i02873ent IS
+  -- Failure_here: Illegal procedure.
+  procedure "and";
+  procedure "and" is
+  begin
+  end;
+END c02s01b00x00p06n04i02873ent;
+
+ARCHITECTURE c02s01b00x00p06n04i02873arch OF c02s01b00x00p06n04i02873ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b00x00p06n04i02873 - A procedure designator must always be an identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p06n04i02873arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2875.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2875.vhd
new file mode 100644
index 0000000..b5c87b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2875.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2875.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p06n08i02875ent IS
+  -- Failure_here: Embedded spaces in string_literal of the overloaded operator
+  function "abs " return real is
+  begin
+    return 1.0;
+  end;
+END c02s01b00x00p06n08i02875ent;
+
+ARCHITECTURE c02s01b00x00p06n08i02875arch OF c02s01b00x00p06n08i02875ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b00x00p06n08i02875 - Extra spaces are not allowed in an operator symbol."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p06n08i02875arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2877.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2877.vhd
new file mode 100644
index 0000000..2afb035
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2877.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2877.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p06n05i02877ent IS
+  -- Failure_here
+  function "an" & "d" return BOOLEAN;
+END c02s01b00x00p06n05i02877ent;
+
+ARCHITECTURE c02s01b00x00p06n05i02877arch OF c02s01b00x00p06n05i02877ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b00x00p06n05i02877 - Illegal function designator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p06n05i02877arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2878.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2878.vhd
new file mode 100644
index 0000000..11b7168
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2878.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2878.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b00x00p06n07i02878ent IS
+  -- Failure_here : Overloading of a non-existant operator
+  function "eor" (k,m:real) return real is
+  begin
+  end;
+END c02s01b00x00p06n07i02878ent;
+
+ARCHITECTURE c02s01b00x00p06n07i02878arch OF c02s01b00x00p06n07i02878ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b00x00p06n07i02878 - The operator symbol used is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b00x00p06n07i02878arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2884.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2884.vhd
new file mode 100644
index 0000000..8d2c060
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2884.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2884.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p04n03i02884ent IS
+  procedure proc1 (sig1: out real) is
+  begin
+    -- Failure_here: Out parameters are assumed to be object class VARIABLE
+    sig1 <= 27.3;
+  end proc1;
+END c02s01b01x00p04n03i02884ent;
+
+ARCHITECTURE c02s01b01x00p04n03i02884arch OF c02s01b01x00p04n03i02884ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p04n03i02884 - The target of a signal assignment statement cannot be a variable."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p04n03i02884arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2885.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2885.vhd
new file mode 100644
index 0000000..4137555
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2885.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2885.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p04n02i02885ent IS
+  procedure howe (k:in real; v:out real) is
+  begin
+    -- ERROR: k is assumed to be a constant
+    k := 27.3;
+    v := 35.7;
+  end howe;
+END c02s01b01x00p04n02i02885ent;
+
+ARCHITECTURE c02s01b01x00p04n02i02885arch OF c02s01b01x00p04n02i02885ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p04n02i02885 - The target of a variable assignment statement cannot be a constant."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p04n02i02885arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2886.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2886.vhd
new file mode 100644
index 0000000..7c64a62
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2886.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2886.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY ch020101_p00401_01_ent IS
+  PORT ( d  : IN  bit;
+         q  : OUT bit);
+END ch020101_p00401_01_ent;
+
+ARCHITECTURE ch020101_p00401_01_arch OF ch020101_p00401_01_ent IS
+  procedure proc1 (signal p1 : inout bit);
+  procedure proc2 (signal p1 : buffer bit);
+
+  procedure proc1 (signal p1 : inout bit) is
+    variable v1 : bit;
+  begin
+    v1 := p1;
+  end;
+
+  procedure proc2 (signal p1 : buffer bit) is
+    variable v1 : bit;
+  begin
+    v1 := p1;
+  end;
+BEGIN
+  proc1 (d);
+  q <= d;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: /src/ch02/sc01/sb01/p004/s010101.vhd - Buffer is not an allowed mode for formal parameter of a procedure."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END ch020101_p00401_01_arch;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2887.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2887.vhd
new file mode 100644
index 0000000..2519633
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2887.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2887.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p04n01i02887ent IS
+  PORT ( d  : IN  bit;
+         q  : OUT bit);
+END c02s01b01x00p04n01i02887ent;
+
+ARCHITECTURE c02s01b01x00p04n01i02887arch OF c02s01b01x00p04n01i02887ent IS
+  procedure proc1 (variable p1 : in bit);
+  procedure proc2 (variable p1 : buffer bit);
+
+  procedure proc1 (variable p1 : in bit) is
+    variable v1 : bit;
+  begin
+    v1 := p1;
+  end;
+
+  procedure proc2 (variable p1 : buffer bit) is
+    variable v1 : bit;
+  begin
+    v1 := p1;
+  end;
+BEGIN
+  proc1 (d);
+  proc2 (d);
+  q <= d;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p04n01i02887 - Buffer is not an allowed mode for formal parameter of a procedure."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p04n01i02887arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2888.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2888.vhd
new file mode 100644
index 0000000..d2bc378
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2888.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2888.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p04n01i02888ent IS
+END c02s01b01x00p04n01i02888ent;
+
+ARCHITECTURE c02s01b01x00p04n01i02888arch OF c02s01b01x00p04n01i02888ent IS
+  procedure exp_type_check (c1: out    integer;
+                            c2: in     integer;
+                            c3: inout    integer;
+                            c5: linkage    integer);  -- Failure_here
+  procedure exp_type_check (c1: out    integer;
+                            c2: in     integer;
+                            c3: inout    integer;
+                            c5: linkage    integer) is
+  begin
+    null;
+  end exp_type_check;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p04n01i02888 - Linkage is not an allowed mode for formal parameter of a procedure."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p04n01i02888arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2889.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2889.vhd
new file mode 100644
index 0000000..bcdd29f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2889.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2889.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p04n03i02889ent IS
+  procedure proc1 (sig1 : inout real) is
+  begin
+    -- Failure_here: Inout parameters are assumed to be object class VARIABLE
+    sig1 <= 27.3;
+  end proc1;
+END c02s01b01x00p04n03i02889ent;
+
+ARCHITECTURE c02s01b01x00p04n03i02889arch OF c02s01b01x00p04n03i02889ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p04n03i02889 - The target of a signal assignment statement cannot be a variable."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p04n03i02889arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc289.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc289.vhd
new file mode 100644
index 0000000..acb1f99
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc289.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc289.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x00p13n01i00289ent IS
+END c03s01b03x00p13n01i00289ent;
+
+ARCHITECTURE c03s01b03x00p13n01i00289arch OF c03s01b03x00p13n01i00289ent IS
+  type T is
+    range 1 to 100
+    units
+      I ;  
+      J = 2 I;
+      K = 2 J;
+      L = 10 K;
+    end units;
+  signal S1 : T;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= 10 * L;
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x00p13n01i00289 - Value doesn't belong to the physical type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x00p13n01i00289arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2890.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2890.vhd
new file mode 100644
index 0000000..9919ef9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2890.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2890.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p05n03i02890ent IS
+END c02s01b01x00p05n03i02890ent;
+
+ARCHITECTURE c02s01b01x00p05n03i02890arch OF c02s01b01x00p05n03i02890ent IS
+  function F1 ( A,B : integer) return integer;
+  function F1 ( A,B : integer ) return integer is
+  begin
+    A := 2 ;  -- Failure_here
+    --ERROR: formal paramters not explicitly given are constant and therfore
+    -- this assignment is illegal.
+
+    B := B * A;  -- Failure_here
+    --ERROR: formal paramters not explicitly given are constant and therfore
+    -- this assignment is illegal.
+    
+    return 3;
+  end F1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p05n03i02890 - Cannot assign a value to a 'constant'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p05n03i02890arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2891.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2891.vhd
new file mode 100644
index 0000000..dbde80e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2891.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2891.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p05n01i02891ent IS
+  PORT ( d  : IN  bit;
+         q  : OUT bit);
+END c02s01b01x00p05n01i02891ent;
+
+ARCHITECTURE c02s01b01x00p05n01i02891arch OF c02s01b01x00p05n01i02891ent IS
+  function func1 (signal p1 : in bit) return bit;
+  function func2 (signal p1 : buffer bit) return bit;
+
+  function func1 (signal p1 : in bit) return bit is
+    variable v1 : bit;
+  begin
+    v1 := p1;
+    return (v1);
+  end;
+
+  function func2 (signal p1 : buffer bit) return bit is
+    variable v1 : bit;
+  begin
+    v1 := p1;
+    return (v1);
+  end;
+BEGIN
+  func1 (d);
+  func2 (d);
+  q <= d;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p05n01i02891 - Buffer is not an allowed mode for formal parameters of a function."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p05n01i02891arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2892.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2892.vhd
new file mode 100644
index 0000000..b1b6ae3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2892.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2892.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p05n01i02892ent IS
+END c02s01b01x00p05n01i02892ent;
+
+ARCHITECTURE c02s01b01x00p05n01i02892arch OF c02s01b01x00p05n01i02892ent IS
+  function F1 ( A : inout integer ) return boolean is -- Failure_here
+    --ERROR: only mode "in" allowed for function formal parameter list
+  begin
+    return false;
+  end F1;
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p05n01i02892 - Only mode in is allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p05n01i02892arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2893.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2893.vhd
new file mode 100644
index 0000000..6c0b46f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2893.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2893.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p05n01i02893ent IS
+END c02s01b01x00p05n01i02893ent;
+
+ARCHITECTURE c02s01b01x00p05n01i02893arch OF c02s01b01x00p05n01i02893ent IS
+  function F1 ( A : out integer ) return boolean is -- Failure_here
+    --ERROR: only mode "in" allowed for function formal parameter list
+  begin
+    return false;
+  end F1;
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p05n01i02893 - Only mode in is allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p05n01i02893arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2894.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2894.vhd
new file mode 100644
index 0000000..ecdf96c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2894.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2894.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p05n01i02894ent IS
+END c02s01b01x00p05n01i02894ent;
+
+ARCHITECTURE c02s01b01x00p05n01i02894arch OF c02s01b01x00p05n01i02894ent IS
+  function F1 ( A : linkage integer ) return boolean is -- Failure_here
+    --ERROR: only mode "in" allowed for function formal parameter list
+  begin
+    return false;
+  end F1;
+BEGIN
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p05n01i02894 - Only mode in is allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p05n01i02894arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2895.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2895.vhd
new file mode 100644
index 0000000..8e77cfc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2895.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2895.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p05n02i02895ent IS
+END c02s01b01x00p05n02i02895ent;
+
+ARCHITECTURE c02s01b01x00p05n02i02895arch OF c02s01b01x00p05n02i02895ent IS
+  function exp_type_check (variable c1: in integer) return integer is
+                                        -- Failure_here
+  begin
+    null;
+  end exp_type_check;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p05n02i02895 - The object class for formal parameters of a function cannot be of object class variable."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p05n02i02895arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2896.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2896.vhd
new file mode 100644
index 0000000..dd47ee1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2896.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2896.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p06n01i02896ent IS
+END c02s01b01x00p06n01i02896ent;
+
+ARCHITECTURE c02s01b01x00p06n01i02896arch OF c02s01b01x00p06n01i02896ent IS
+  function func1 (signal a1 : real) return integer is
+  begin
+    null;
+  end func1;
+BEGIN
+  TESTING: PROCESS
+    variable x: real := 1.2;
+    variable y: integer;
+  BEGIN
+    y := func1 (x); -- Failure_here
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p06n01i02896 - In a subprogram call the actual designator associated with a formal parameter of class signal cannot be of type variable."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p06n01i02896arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2897.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2897.vhd
new file mode 100644
index 0000000..f6f28a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2897.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2897.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p06n01i02897ent IS
+END c02s01b01x00p06n01i02897ent;
+
+ARCHITECTURE c02s01b01x00p06n01i02897arch OF c02s01b01x00p06n01i02897ent IS
+
+BEGIN
+  TESTING: PROCESS
+    procedure check (signal x:in integer; y:in boolean := true) is
+    begin
+      null;
+    end;
+    variable p: integer := 3;
+  BEGIN
+    check (p);
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p06n01i02897 - Class mismatch in procedure call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p06n01i02897arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2898.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2898.vhd
new file mode 100644
index 0000000..5a0014f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2898.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2898.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p06n01i02898ent IS
+END c02s01b01x00p06n01i02898ent;
+
+ARCHITECTURE c02s01b01x00p06n01i02898arch OF c02s01b01x00p06n01i02898ent IS
+  function func1 (signal A:integer) return integer is
+  begin
+    if a > 0 then
+      return 5;
+    else
+      return 0;
+    end if;
+  end func1;
+  constant C1 : integer := 0;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : integer;
+  BEGIN
+    V1 := func1( C1 );  -- Failure_here
+    -- ERROR: Actual corresponding to a formal of class signal must be a signal
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p06n01i02898 - The formal designator of class signal must be associated with an actual of class signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p06n01i02898arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2899.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2899.vhd
new file mode 100644
index 0000000..0d9e92b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2899.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2899.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x00p06n02i02899ent IS
+END c02s01b01x00p06n02i02899ent;
+
+ARCHITECTURE c02s01b01x00p06n02i02899arch OF c02s01b01x00p06n02i02899ent IS
+  signal p: integer := 3;
+BEGIN
+  TESTING: PROCESS
+    procedure check (variable x:in integer; y:in boolean := true) is
+    begin
+    end;
+  BEGIN
+    check (p);
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x00p06n02i02899 - Class mismatch in procudure call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x00p06n02i02899arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2905.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2905.vhd
new file mode 100644
index 0000000..8046c91
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2905.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2905.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02905ent IS
+END c02s01b01x02p03n01i02905ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02905arch OF c02s01b01x02p03n01i02905ent IS
+  procedure proc1 (signal S1: in bit) is
+    variable V2 : boolean;
+  begin
+    -- Failure_here : attribute QUIET may not be read within a procedure
+    V2 := S1'quiet;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02905 - The attribute QUIET of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02905arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2906.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2906.vhd
new file mode 100644
index 0000000..8d567cc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2906.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2906.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02906ent IS
+END c02s01b01x02p03n01i02906ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02906arch OF c02s01b01x02p03n01i02906ent IS
+  procedure proc1 (signal S1: in bit) is
+    variable V2 : boolean;
+  begin
+    -- Failure_here : attribute STABLE may not be read within a procedure
+    V2 := S1'stable;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02906 - The attribute STABLE of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02906arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2907.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2907.vhd
new file mode 100644
index 0000000..d5e3e4b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2907.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2907.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02907ent IS
+END c02s01b01x02p03n01i02907ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02907arch OF c02s01b01x02p03n01i02907ent IS
+  procedure proc1 (signal S1: in bit) is
+    variable V2 : bit;
+  begin
+    -- Failure_here : attribute DELAYED may not be read within a procedure
+    V2 := S1'delayed;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02907 - The attribute DELAYED of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02907arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2908.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2908.vhd
new file mode 100644
index 0000000..f620f0f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2908.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2908.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02908ent IS
+END c02s01b01x02p03n01i02908ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02908arch OF c02s01b01x02p03n01i02908ent IS
+  function func1 (signal S1: in bit) return bit is
+    variable V1 : bit;
+  begin
+    -- Failure_here : attribute DELAYED may not be read within a function
+    V1 := S1'delayed;
+  end func1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02908 - The attribute DELAYED of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02908arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2909.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2909.vhd
new file mode 100644
index 0000000..fb59713
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2909.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2909.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02909ent IS
+END c02s01b01x02p03n01i02909ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02909arch OF c02s01b01x02p03n01i02909ent IS
+  function func1 (signal S1: in bit) return bit is
+    variable V1 : boolean;
+  begin
+    -- Failure_here : attribute STABLE may not be read within a function
+    V1 := S1'STABLE;
+  end func1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02909 - The attribute STABLE of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02909arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2910.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2910.vhd
new file mode 100644
index 0000000..14e32f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2910.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2910.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02910ent IS
+END c02s01b01x02p03n01i02910ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02910arch OF c02s01b01x02p03n01i02910ent IS
+  function func1 (signal S1: in bit) return bit is
+    variable V1 : boolean;
+  begin
+    -- Failure_here : attribute QUIET may not be read within a function
+    V1 := S1'QUIET;
+  end func1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02910 - The attribute QUIET of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02910arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2911.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2911.vhd
new file mode 100644
index 0000000..8bea2ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2911.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2911.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02911ent IS
+END c02s01b01x02p03n01i02911ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02911arch OF c02s01b01x02p03n01i02911ent IS
+  procedure proc1 (signal S1: inout bit) is
+    variable V1 : bit;
+  begin
+    -- Failure_here : attribute DELAYED may not be read within a procedure
+    V1 := S1'DELAYED;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02911 - The attribute DELAYED of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02911arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2912.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2912.vhd
new file mode 100644
index 0000000..e1914f1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2912.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2912.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02912ent IS
+END c02s01b01x02p03n01i02912ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02912arch OF c02s01b01x02p03n01i02912ent IS
+  procedure proc1 (signal S1: inout bit) is
+    variable V1 : boolean;
+  begin
+    -- Failure_here : attribute STABLE may not be read within a procedure
+    V1 := S1'STABLE;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02912 - The attribute STABLE of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02912arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2913.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2913.vhd
new file mode 100644
index 0000000..4edef18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2913.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2913.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02913ent IS
+END c02s01b01x02p03n01i02913ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02913arch OF c02s01b01x02p03n01i02913ent IS
+  procedure proc1 (signal S1: inout bit) is
+    variable V1 : boolean;
+  begin
+    -- Failure_here : attribute QUIET may not be read within a procedure
+    V1 := S1'QUIET;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02913 - The attribute QUIET of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02913arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2914.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2914.vhd
new file mode 100644
index 0000000..8cf1279
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2914.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2914.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02914ent IS
+END c02s01b01x02p03n01i02914ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02914arch OF c02s01b01x02p03n01i02914ent IS
+  procedure proc1 (signal S1: out bit) is
+    variable V1 : bit;
+  begin
+    -- Failure_here : attribute DELAYED may not be read within a procedure
+    V1 := S1'DELAYED;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02914 - The attribute DELAYED of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02914arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2915.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2915.vhd
new file mode 100644
index 0000000..19d8399
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2915.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2915.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02915ent IS
+END c02s01b01x02p03n01i02915ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02915arch OF c02s01b01x02p03n01i02915ent IS
+  procedure proc1 (signal S1: out bit) is
+    variable V1 : boolean;
+  begin
+    -- Failure_here : attribute STABLE may not be read within a procedure
+    V1 := S1'STABLE;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02915 - The attribute STABLE of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02915arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2916.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2916.vhd
new file mode 100644
index 0000000..218ca24
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2916.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2916.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p03n01i02916ent IS
+END c02s01b01x02p03n01i02916ent;
+
+ARCHITECTURE c02s01b01x02p03n01i02916arch OF c02s01b01x02p03n01i02916ent IS
+  procedure proc1 (signal S1: out bit) is
+    variable V1 : boolean;
+  begin
+    -- Failure_here : attribute QUIET may not be read within a procedure
+    V1 := S1'QUIET;
+  end proc1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p03n01i02916 - The attribute QUIET of formal signal parameters can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p03n01i02916arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2919.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2919.vhd
new file mode 100644
index 0000000..ae8c522
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2919.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2919.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p06n01i02919ent IS
+END c02s01b01x02p06n01i02919ent;
+
+ARCHITECTURE c02s01b01x02p06n01i02919arch OF c02s01b01x02p06n01i02919ent IS
+  procedure proc1 (signal x1 : bit; z1 : boolean);
+  procedure proc1 (signal x1 : bit; z1 : boolean) is
+  begin
+    null;
+  end proc1;
+  signal b: bit_vector (4 downto 1);
+BEGIN
+  TESTING: PROCESS
+    variable i : integer := 1;
+  BEGIN
+    proc1 (b(i), true);  -- Failure_here
+    -- b(i) is not a static name.
+    assert FALSE
+      report "***FAILED TEST: c02s01b01x02p06n01i02919 - The actual signal associated with a signal parameter must be denoted by a static name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p06n01i02919arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2920.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2920.vhd
new file mode 100644
index 0000000..54202f4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2920.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2920.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s01b01x02p06n02i02920ent IS
+END c02s01b01x02p06n02i02920ent;
+
+ARCHITECTURE c02s01b01x02p06n02i02920arch OF c02s01b01x02p06n02i02920ent IS
+
+  procedure PX (signal I1 : in Bit; signal I2 : out Bit; signal I3 : inout Integer);
+  procedure PX (signal I1 : in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+  begin
+    assert (I1 /= '1')
+      report "No failure on test" ;
+    assert (I3 /= 5)
+      report "No failure on test" ;
+  end PX;
+
+  signal S1 : Bit    := '1';
+  signal S2 : Integer    := 5;
+  signal S3 : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    PX(S1,S3,Integer(5.3)) ;     --- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c02s01b01x02p06n02i02920 - Type conversion is not allowed to associate an actual signal with a formal signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s01b01x02p06n02i02920arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2921.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2921.vhd
new file mode 100644
index 0000000..dd0beb2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2921.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2921.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p04n01i02921ent IS
+END c02s02b00x00p04n01i02921ent;
+
+ARCHITECTURE c02s02b00x00p04n01i02921arch OF c02s02b00x00p04n01i02921ent IS
+  function G return BOOLEAN;
+  function G return BOOLEAN is
+    generic ( Z : TIME ) ;  -- Failure_here
+
+    -- ERROR : generic declaration not allowed in subprogram declarations
+  begin
+    return 'A'='a';
+  end G;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p04n01i02921 - Generic declarations are not allowed within subprogram declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p04n01i02921arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2922.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2922.vhd
new file mode 100644
index 0000000..70d070f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2922.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2922.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p04n01i02922ent IS
+END c02s02b00x00p04n01i02922ent;
+
+ARCHITECTURE c02s02b00x00p04n01i02922arch OF c02s02b00x00p04n01i02922ent IS
+  function F  return REAL;
+  function F return REAL is
+    port ( X : INTEGER ; Y : STRING ) ; -- Failure_here
+
+    -- ERROR : port declaration is not allowed whithin subprogram declaration
+  begin
+    return 3.5;
+  end F;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p04n01i02922 - Port declarations are not allowed within subprogram declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p04n01i02922arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2923.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2923.vhd
new file mode 100644
index 0000000..d422da8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2923.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2923.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p04n01i02923ent IS
+END c02s02b00x00p04n01i02923ent;
+
+ARCHITECTURE c02s02b00x00p04n01i02923arch OF c02s02b00x00p04n01i02923ent IS
+  function H return CHARACTER;
+  function H return CHARACTER is
+    signal S1 : BIT;  -- Failure_here
+    -- ERROR : signal declaration not allowed in subprogram declaration
+  begin
+    return 'A';
+  end H;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p04n01i02923 - Signal declarations are not allowed within subprogram declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p04n01i02923arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2924.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2924.vhd
new file mode 100644
index 0000000..65ba7ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2924.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2924.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p04n01i02924ent IS
+END c02s02b00x00p04n01i02924ent;
+
+ARCHITECTURE c02s02b00x00p04n01i02924arch OF c02s02b00x00p04n01i02924ent IS
+  function J (Z:BOOLEAN) return INTEGER;
+  function J (Z:BOOLEAN) return INTEGER is
+    entity E (PT:BIT) is   -- Failure_here
+      -- ERROR : interface declaration not allowed in subprogram declarations
+    end E;
+    begin
+      return 10;
+    end J;
+    BEGIN
+      TESTING: PROCESS
+      BEGIN
+        assert FALSE
+          report "***FAILED TEST: c02s02b00x00p04n01i02924 - Interface declarations are not allowed within subprogram declaration."
+          severity ERROR;
+        wait;
+      END PROCESS TESTING;
+
+    END c02s02b00x00p04n01i02924arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2925.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2925.vhd
new file mode 100644
index 0000000..1fc9b25
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2925.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2925.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p04n01i02925ent IS
+END c02s02b00x00p04n01i02925ent;
+
+ARCHITECTURE c02s02b00x00p04n01i02925arch OF c02s02b00x00p04n01i02925ent IS
+  function L return POSITIVE;
+  function L return POSITIVE is
+    architecture AB of E is   -- Failure_here
+      -- ERROR : body declaration not allowed in subprogram declarations
+      signal S : REAL;
+    begin
+      S <= 2.4;
+    end AB;
+    end L;
+    BEGIN
+      TESTING: PROCESS
+      BEGIN
+        assert FALSE
+          report "***FAILED TEST: c02s02b00x00p04n01i02925 - Body declarations are not allowed within subprogram declaration."
+          severity ERROR;
+        wait;
+      END PROCESS TESTING;
+
+    END c02s02b00x00p04n01i02925arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2926.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2926.vhd
new file mode 100644
index 0000000..77a95f5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2926.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2926.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p04n01i02926ent IS
+END c02s02b00x00p04n01i02926ent;
+
+ARCHITECTURE c02s02b00x00p04n01i02926arch OF c02s02b00x00p04n01i02926ent IS
+  function M return BOOLEAN;
+  function M return BOOLEAN is
+    component C  -- Failure_here
+      -- ERROR : component declaration not allowed in subprogram declarations
+      port ( I : out REAL ) ;
+    end component ;
+  begin
+    return FALSE;
+  end M;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p04n01i02926 - Component declarations are not allowed within subprogram declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p04n01i02926arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2927.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2927.vhd
new file mode 100644
index 0000000..5545eb4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2927.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2927.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p04n01i02927ent IS
+END c02s02b00x00p04n01i02927ent;
+
+ARCHITECTURE c02s02b00x00p04n01i02927arch OF c02s02b00x00p04n01i02927ent IS
+  function N return REAL;
+  function N return REAL is
+    package ch0202_p00401_07_pkg is   -- Failure_here
+      -- ERROR : package declaration not allowed in subprogram declarations
+      type T is range 10 to 20;
+    end ch0202_p00401_07_pkg;
+    begin
+      return -5.5;
+    end N;
+    BEGIN
+      TESTING: PROCESS
+      BEGIN
+        assert FALSE
+          report "***FAILED TEST: c02s02b00x00p04n01i02927 - Package declarations are not allowed within subprogram declaration."
+          severity ERROR;
+        wait;
+      END PROCESS TESTING;
+
+    END c02s02b00x00p04n01i02927arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2928.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2928.vhd
new file mode 100644
index 0000000..b9f25ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2928.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2928.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p04n01i02928ent IS
+END c02s02b00x00p04n01i02928ent;
+
+ARCHITECTURE c02s02b00x00p04n01i02928arch OF c02s02b00x00p04n01i02928ent IS
+  function O return STRING;
+  function O return STRING is
+    assert CHARACTER'('1')/=BIT'('1') report "oops"; -- Failure_here
+    -- ERROR : assert directive not allowed in subprogram declarations
+  begin
+    return "OKAY";
+  end O;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p04n01i02928 - Assert declarations are not allowed within subprogram declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p04n01i02928arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2929.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2929.vhd
new file mode 100644
index 0000000..990daed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2929.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2929.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p04n01i02929ent IS
+END c02s02b00x00p04n01i02929ent;
+
+ARCHITECTURE c02s02b00x00p04n01i02929arch OF c02s02b00x00p04n01i02929ent IS
+  function Q return BIT;
+  function Q return BIT is
+    for all : COMP_NAME use entity (open) architecture(open);
+  end for;   -- Failure_here
+  -- ERROR : configuration specification not allowed in subprogram declarations
+begin
+  return '0';
+end Q;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p04n01i02929 - Configuration declarations are not allowed within subprogram declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p04n01i02929arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2930.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2930.vhd
new file mode 100644
index 0000000..707151a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2930.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2930.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p07n03i02930ent IS
+END c02s02b00x00p07n03i02930ent;
+
+ARCHITECTURE c02s02b00x00p07n03i02930arch OF c02s02b00x00p07n03i02930ent IS
+  function  func1 (i,l:integer) return boolean;
+  -- ERROR: non-existent body for function func1
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n03i02930 - Every subprogram declaration has to have a corresponding body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n03i02930_arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2931.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2931.vhd
new file mode 100644
index 0000000..584a89f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2931.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2931.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p07n05i02931ent IS
+END c02s02b00x00p07n05i02931ent;
+
+ARCHITECTURE c02s02b00x00p07n05i02931arch OF c02s02b00x00p07n05i02931ent IS
+  procedure PX (signal I1: in bit; signal I2: out bit);  -- Failure_here
+BEGIN
+
+  BBB: block
+    procedure PX (signal I1: in bit; signal I2: out bit) is
+    begin
+      I2 <= I1;
+    end PX;
+    signal s1,s2: bit;
+  begin
+    PX(S1,S2);
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n05i02931 - Subprogram body and subprogram declaration must occur in the same declarative region."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n05i02931arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2933.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2933.vhd
new file mode 100644
index 0000000..5dda91a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2933.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2933.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p07n04i02933pkg is
+  procedure proc1 (x, y : integer);
+end c02s02b00x00p07n04i02933pkg;
+
+package body c02s02b00x00p07n04i02933pkg is
+  procedure proc1 (x, y :in integer) is -- Failure_here
+  begin
+  end proc1;
+end c02s02b00x00p07n04i02933pkg;
+
+ENTITY c02s02b00x00p07n04i02933ent IS
+END c02s02b00x00p07n04i02933ent;
+
+ARCHITECTURE c02s02b00x00p07n04i02933arch OF c02s02b00x00p07n04i02933ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n04i02933 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n04i02933arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2934.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2934.vhd
new file mode 100644
index 0000000..51a535a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2934.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2934.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p07n03i02934ent IS
+END c02s02b00x00p07n03i02934ent;
+
+ARCHITECTURE c02s02b00x00p07n03i02934arch OF c02s02b00x00p07n03i02934ent IS
+  procedure PROC;    -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n03i02934 - Every subprogram declaration has to have a corresponding body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n03i02934arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2935.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2935.vhd
new file mode 100644
index 0000000..add10b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2935.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2935.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p07n03i02935pkg is
+  procedure proc1 (i,l:integer; res: boolean);
+end c02s02b00x00p07n03i02935pkg;
+
+package body c02s02b00x00p07n03i02935pkg is
+  --ERROR : non-existent body for procedure proc1
+end c02s02b00x00p07n03i02935pkg;
+
+
+ENTITY c02s02b00x00p07n03i02935ent IS
+END c02s02b00x00p07n03i02935ent;
+
+ARCHITECTURE c02s02b00x00p07n03i02935arch OF c02s02b00x00p07n03i02935ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n03i02935 - Every subprogram declaration has to have a corresponding body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n03i02935arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2936.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2936.vhd
new file mode 100644
index 0000000..ac7ab04
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2936.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2936.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p07n03i02936pkg is
+  function  func1 (i,l:integer) return boolean;
+end c02s02b00x00p07n03i02936pkg;
+
+package body c02s02b00x00p07n03i02936pkg is
+  -- ERROR: non-existent body for function func1
+end c02s02b00x00p07n03i02936pkg;
+
+
+ENTITY c02s02b00x00p07n03i02936ent IS
+END c02s02b00x00p07n03i02936ent;
+
+ARCHITECTURE c02s02b00x00p07n03i02936arch OF c02s02b00x00p07n03i02936ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n03i02936 - Every subprogram declaration has to have a corresponding body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n03i02936arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2937.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2937.vhd
new file mode 100644
index 0000000..9852edd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2937.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2937.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p07n03i02937pkg is
+end c02s02b00x00p07n03i02937pkg;
+
+package body c02s02b00x00p07n03i02937pkg is
+  procedure proc1 (i,l:integer; res: boolean);
+  -- ERROR: non-existent body for procedure proc1
+end c02s02b00x00p07n03i02937pkg;
+
+
+ENTITY c02s02b00x00p07n03i02937ent IS
+END c02s02b00x00p07n03i02937ent;
+
+ARCHITECTURE c02s02b00x00p07n03i02937arch OF c02s02b00x00p07n03i02937ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n03i02937 - Every subprogram declaration has to have a corresponding body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n03i02937arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2938.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2938.vhd
new file mode 100644
index 0000000..ed83264
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2938.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2938.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p07n03i02938pkg is
+end c02s02b00x00p07n03i02938pkg;
+
+package body c02s02b00x00p07n03i02938pkg is
+  function  func1 (i,l:integer) return boolean;
+  -- ERROR: non-existent body for function func1
+end c02s02b00x00p07n03i02938pkg;
+
+
+ENTITY c02s02b00x00p07n03i02938ent IS
+END c02s02b00x00p07n03i02938ent;
+
+ARCHITECTURE c02s02b00x00p07n03i02938arch OF c02s02b00x00p07n03i02938ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n03i02938 - Every subprogram declaration has to have a corresponding body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n03i02938arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2939.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2939.vhd
new file mode 100644
index 0000000..0c2f38c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2939.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2939.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p07n03i02939ent IS
+  procedure proc1 (i,l:integer; res: boolean);
+  EEND c02s02b00x00p07n03i02939ent;
+
+  ARCHITECTURE c02s02b00x00p07n03i02939arch OF c02s02b00x00p07n03i02939ent IS
+    -- ERROR: non-existent body for procedure proc1
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE
+        report "***FAILED TEST: c02s02b00x00p07n03i02939 - Every subprogram declaration has to have a corresponding body."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c02s02b00x00p07n03i02939arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2940.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2940.vhd
new file mode 100644
index 0000000..8e9822c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2940.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2940.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p07n03i02940ent IS
+  function  func1 (i,l:integer) return boolean;
+END c02s02b00x00p07n03i02940ent;
+
+ARCHITECTURE c02s02b00x00p07n03i02940arch OF c02s02b00x00p07n03i02940ent IS
+  -- ERROR: non-existent body for function func1
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n03i02940 - Every subprogram declaration has to have a corresponding body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n03i02940arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2941.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2941.vhd
new file mode 100644
index 0000000..35ecda6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2941.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2941.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p07n04i02941pkg is
+  procedure proc1 (x, y : integer);
+end c02s02b00x00p07n04i02941pkg;
+
+package body c02s02b00x00p07n04i02941pkg is
+  procedure proc1 (x : integer; y :integer) is --Failure_here    
+  begin
+  end proc1;
+end c02s02b00x00p07n04i02941pkg;
+
+ENTITY c02s02b00x00p07n04i02941ent IS
+END c02s02b00x00p07n04i02941ent;
+
+ARCHITECTURE c02s02b00x00p07n04i02941arch OF c02s02b00x00p07n04i02941ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n04i02941 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n04i02941arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2942.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2942.vhd
new file mode 100644
index 0000000..9aebf57
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2942.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2942.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s02b00x00p07n04i02942pkg is
+  procedure proc1 (x:integer; y : integer);
+end c02s02b00x00p07n04i02942pkg;
+
+package body c02s02b00x00p07n04i02942pkg is
+  procedure proc1 (x, y :in integer) is  --Failure_here
+  begin
+  end proc1;
+end c02s02b00x00p07n04i02942pkg;
+
+ENTITY c02s02b00x00p07n04i02942ent IS
+END c02s02b00x00p07n04i02942ent;
+
+ARCHITECTURE c02s02b00x00p07n04i02942arch OF c02s02b00x00p07n04i02942ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n04i02942 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n04i02942arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2943.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2943.vhd
new file mode 100644
index 0000000..20385ed
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2943.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2943.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p07n04i02943ent IS
+  function F (i,j : integer) return integer;
+  -- Failure_here: Function body spec does not conform to declaration spec.
+  function F (i : integer; j : integer) return integer is
+  begin
+    return (i + j);
+  end;
+END c02s02b00x00p07n04i02943ent;
+
+ARCHITECTURE c02s02b00x00p07n04i02943arch OF c02s02b00x00p07n04i02943ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n04i02943 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n04i02943arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2944.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2944.vhd
new file mode 100644
index 0000000..e91329e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2944.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2944.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p07n04i02944ent IS
+  procedure P (i,j : inout integer);
+
+  -- Failure_here: Procedure body spec does not conform to declaration spec.
+  procedure P (i : inout integer; j : inout integer) is
+  begin
+    j := i;
+  end;
+END c02s02b00x00p07n04i02944ent;
+
+ARCHITECTURE c02s02b00x00p07n04i02944arch OF c02s02b00x00p07n04i02944ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p07n04i02944 - Subprogram specification in package body does not conform to the subprogram specification of the declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p07n04i02944arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2946.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2946.vhd
new file mode 100644
index 0000000..3528215
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2946.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2946.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p08n02i02946ent IS
+END c02s02b00x00p08n02i02946ent;
+
+ARCHITECTURE c02s02b00x00p08n02i02946arch OF c02s02b00x00p08n02i02946ent IS
+  function func1 (a1 : real; b1 : integer:= 12) return integer;
+  function func1 (a1 : real; b1 : integer:= 12) return integer is
+  begin
+  end func2;   -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p08n02i02946 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p08n02i02946arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2947.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2947.vhd
new file mode 100644
index 0000000..0a259e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2947.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2947.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p08n02i02947ent IS
+END c02s02b00x00p08n02i02947ent;
+
+ARCHITECTURE c02s02b00x00p08n02i02947arch OF c02s02b00x00p08n02i02947ent IS
+  procedure proc1 (A:bit; B: out boolean) is
+  begin
+    if A = '1' then 
+      B := TRUE;
+    else    
+      B := FALSE;
+    end if;
+    -- Failure_here : label must be the same as subprogram identifier
+  end proc;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p08n02i02947 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p08n02i02947arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2953.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2953.vhd
new file mode 100644
index 0000000..8eaf9de
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2953.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2953.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p24n01i02953ent IS
+END c02s02b00x00p24n01i02953ent;
+
+ARCHITECTURE c02s02b00x00p24n01i02953arch OF c02s02b00x00p24n01i02953ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable a1 : integer := func1 (1);       --Failure_here
+    function func1 (x: in integer) return integer is
+    begin
+      return 12;
+    end;
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p24n01i02953 - Subprogram declaration should appear before call of subprogram."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p24n01i02953arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2954.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2954.vhd
new file mode 100644
index 0000000..feedf79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2954.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2954.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p02n01i02954ent IS
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
+
+  procedure  is   --- Failure_here ; Missing subprogram specification
+begin
+  assert (I1 /= '1')
+    report "No failure on test" ;
+  assert (I3 /= 5)
+    report "No failure on test" ;
+end;
+END c02s02b00x00p02n01i02954ent;
+
+ARCHITECTURE c02s02b00x00p02n01i02954arch OF c02s02b00x00p02n01i02954ent IS
+  signal S1 : Bit := '1';
+  signal S2 : Integer := 5;
+  signal S3 : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    PX(S1,S3,S2);
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p02n01i02954 - Missing subprogram specification."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p02n01i02954arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2956.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2956.vhd
new file mode 100644
index 0000000..1e0d0a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2956.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2956.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p02n01i02956ent IS
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
+
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+    --- Failure_here
+    assert (I1 /= '1')
+      report "No failure on test" ;
+    assert (I3 /= 5)
+      report "No failure on test" ;
+  end;
+END c02s02b00x00p02n01i02956ent;
+
+ARCHITECTURE c02s02b00x00p02n01i02956arch OF c02s02b00x00p02n01i02956ent IS
+  signal S1 : Bit    := '1';
+  signal S2 : Integer    := 5;
+  signal S3 : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    PX(S1,S3,S2);
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p02n01i02956 - Missing keyword begin."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p02n01i02956arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2957.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2957.vhd
new file mode 100644
index 0000000..24dc01c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2957.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2957.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p02n01i02957ent IS
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
+
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+  begin
+    assert (I1 /= '1')
+      report "No failure on test" ;
+    assert (I3 /= 5)
+      report "No failure on test" ;
+    ; --Failure here
+  END c02s02b00x00p02n01i02957ent;
+
+  ARCHITECTURE c02s02b00x00p02n01i02957arch OF c02s02b00x00p02n01i02957ent IS
+    signal S1 : Bit    := '1';
+    signal S2 : Integer    := 5;
+    signal S3 : Bit;
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      PX(S1,S3,S2);
+      wait for 5 ns;
+      assert FALSE
+        report "***FAILED TEST: c02s02b00x00p02n01i02957 - Missing keyword end."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c02s02b00x00p02n01i02957arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2958.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2958.vhd
new file mode 100644
index 0000000..351ea0f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2958.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2958.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s02b00x00p02n01i02958ent IS
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
+
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+  begin
+    assert (I1 /= '1')
+      report "No failure on test" ;
+    assert (I3 /= 5)
+      report "No failure on test" ;
+  end   --Failure here
+END c02s02b00x00p02n01i02958ent;
+
+ARCHITECTURE c02s02b00x00p02n01i02958arch OF c02s02b00x00p02n01i02958ent IS
+  signal S1 : Bit    := '1';
+  signal S2 : Integer    := 5;
+  signal S3 : Bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    PX(S1,S3,S2);
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c02s02b00x00p02n01i02958 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s02b00x00p02n01i02958arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc296.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc296.vhd
new file mode 100644
index 0000000..81baab0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc296.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc296.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b03x01p01n04i00296ent IS
+END c03s01b03x01p01n04i00296ent;
+
+ARCHITECTURE c03s01b03x01p01n04i00296arch OF c03s01b03x01p01n04i00296ent IS
+  type some_time is range 1 to 100
+    units
+      fs;   -- base unit
+      x  = 10 fs;
+      y  = 10 x;
+    end units;
+  constant z : some_time := 10 y;
+  signal S : integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S <= 10 after z;   
+    wait for 20 ns;
+    assert FALSE 
+      report "***FAILED TEST: c03s01b03x01p01n04i00296 - The delay specification is not of type TIME."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b03x01p01n04i00296arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2963.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2963.vhd
new file mode 100644
index 0000000..e31dd15
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2963.vhd
@@ -0,0 +1,119 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2963.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s03b00x00p03n01i02963pkg is
+  FUNCTION boo (P1:integer;X:bit:='1') RETURN integer;
+  FUNCTION boo (P2:integer;X:bit_vector:="1010") RETURN integer;
+  FUNCTION boo (P3:integer;X:boolean:=TRUE) RETURN integer;
+  FUNCTION boo (P4:integer;X:character:='Z') RETURN integer;
+  FUNCTION boo (P5:integer;X:integer:=55) RETURN integer;
+  FUNCTION boo (P6:integer;X:real:=10.01) RETURN integer;
+  FUNCTION boo (P7:integer;X:string:="STRING") RETURN integer;
+  FUNCTION boo (P8:integer;X:time:=10 ns) RETURN integer;
+end c02s03b00x00p03n01i02963pkg;
+
+package bodyc02s03b00x00p03n01i02963pkg is
+  FUNCTION boo (P1:integer;X:bit:='1') RETURN integer IS
+  BEGIN
+    assert false report "boo with BIT param" severity note;
+    RETURN 1;
+  END;
+
+  FUNCTION boo (P2:integer;X:bit_vector:="1010") RETURN integer IS    
+  BEGIN
+    assert false report "boo with BIT_VECTOR param" severity note;
+    RETURN 2;
+  END;
+
+  FUNCTION boo (P3:integer;X:boolean:=TRUE) RETURN integer IS
+  BEGIN
+    assert false report "boo with BOOLEAN param" severity note;
+    RETURN 3;
+  END;
+
+  FUNCTION boo (P4:integer;X:character:='Z') RETURN integer IS
+  BEGIN
+    assert false report "boo with CHARACTER param" severity note;
+    RETURN 4;
+  END;
+
+  FUNCTION boo (P5:integer;X:integer:=55) RETURN integer IS
+  BEGIN
+    assert false report "boo with INTEGER param" severity note;
+    RETURN 5;
+  END;
+
+  FUNCTION boo (P6:integer;X:real:=10.01) RETURN integer IS
+  BEGIN
+    assert false report "boo with REAL param" severity note;
+    RETURN 6;
+  END;
+  
+  FUNCTION boo (P7:integer;X:string:="STRING") RETURN integer IS
+  BEGIN
+    assert false report "boo with STRING param" severity note;
+    RETURN 7;
+  END;
+  
+  FUNCTION boo (P8:integer;X:time:=10 ns) RETURN integer IS
+  BEGIN
+    assert false report "boo with TIME param" severity note;
+    RETURN 8;
+  END;
+end c02s03b00x00p03n01i02963pkg;
+
+ENTITY c02s03b00x00p03n01i02963ent IS
+  PORT (b1,b2,b3,b4,b5,b6,b7,b8: INOUT integer);
+END c02s03b00x00p03n01i02963ent;
+
+use work.c02s03b00x00p03n01i02963pkg.all;
+ARCHITECTURE c02s03b00x00p03n01i02963arch OF c02s03b00x00p03n01i02963ent IS
+  SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    WAIT FOR 1 ns;
+    c1 <= boo(b1);
+    c2 <= boo(b2);
+    c3 <= boo(b3);
+    c4 <= boo(b4);
+    c5 <= boo(b5);
+    c6 <= boo(b6);
+    c7 <= boo(b7);
+    c8 <= boo(b8);
+    wait for 5 ns;
+
+    assert FALSE
+      report "***FAILED TEST: c02s03b00x00p03n01i02963 - A call to an overloaded subprogram is ambiguous."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p03n01i02963arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2965.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2965.vhd
new file mode 100644
index 0000000..f3a70c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2965.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2965.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s03b00x00p03n01i02965pkg is
+  procedure proc1 (x:integer);
+  procedure proc1 (x:integer);  -- Failure_here
+end c02s03b00x00p03n01i02965pkg;
+
+package body c02s03b00x00p03n01i02965pkg is
+  procedure proc1 (x:integer) is
+  begin
+  end proc1;
+end c02s03b00x00p03n01i02965pkg;
+
+
+ENTITY c02s03b00x00p03n01i02965ent IS
+END c02s03b00x00p03n01i02965ent;
+
+ARCHITECTURE c02s03b00x00p03n01i02965arch OF c02s03b00x00p03n01i02965ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+
+    assert FALSE
+      report "***FAILED TEST: c02s03b00x00p03n01i02965 - A call to an overloaded subprogram is ambiguous."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b00x00p03n01i02965
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2970.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2970.vhd
new file mode 100644
index 0000000..c7e37bc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2970.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2970.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p02n01i02970ent IS
+END c02s03b01x00p02n01i02970ent;
+
+ARCHITECTURE c02s03b01x00p02n01i02970arch OF c02s03b01x00p02n01i02970ent IS
+  function "not" (a1 : real; b1 : integer:= 12) return integer is --Failure_here
+  begin
+    return 12;
+  end "not";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s03b01x00p02n01i02970 - The subprogram specification of a unary operator must have only a single parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p02n01i02970arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2971.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2971.vhd
new file mode 100644
index 0000000..1bd6f11
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2971.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2971.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c02s03b01x00p02n02i02971ent IS
+END c02s03b01x00p02n02i02971ent;
+
+ARCHITECTURE c02s03b01x00p02n02i02971arch OF c02s03b01x00p02n02i02971ent IS
+  function "and" (a1 : real) return integer is --Failure here
+  begin
+    return 12;  
+  end "and";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s03b01x00p02n02i02971 - The subprogram specification of a binary operator must have two parameters."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s03b01x00p02n02i02971arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2983.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2983.vhd
new file mode 100644
index 0000000..b8326a7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2983.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2983.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p02n01i02983pkg is   
+  
+  ;      --Failure here
+
+  ENTITY c02s05b00x00p02n01i02983ent IS
+  END c02s05b00x00p02n01i02983ent;
+
+  ARCHITECTURE c02s05b00x00p02n01i02983arch OF c02s05b00x00p02n01i02983ent IS
+
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE
+        report "***FAILED TEST: c02s05b00x00p02n01i02983 - Missing keyword end."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c02s05b00x00p02n01i02983arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2984.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2984.vhd
new file mode 100644
index 0000000..325c11a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2984.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2984.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package is   --Failure here
+  
+end;
+
+ENTITY c02s05b00x00p02n01i02984ent IS
+END c02s05b00x00p02n01i02984ent;
+
+ARCHITECTURE c02s05b00x00p02n01i02984arch OF c02s05b00x00p02n01i02984ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s05b00x00p02n01i02984 - Missing identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p02n01i02984arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2985.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2985.vhd
new file mode 100644
index 0000000..30acfe5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2985.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2985.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p02n01i02985pkg is   
+  
+end         --Failure here
+
+  ENTITY c02s05b00x00p02n01i02985ent IS
+END c02s05b00x00p02n01i02985ent;
+
+ARCHITECTURE c02s05b00x00p02n01i02985arch OF c02s05b00x00p02n01i02985ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s05b00x00p02n01i02985 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p02n01i02985arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2986.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2986.vhd
new file mode 100644
index 0000000..b1d6961
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2986.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2986.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p05n01i02986ent is
+end c02s05b00x00p05n01i02986en;
+
+ENTITY c02s05b00x00p05n01i02986ent IS
+END c02s05b00x00p05n01i02986ent;
+
+ARCHITECTURE c02s05b00x00p05n01i02986arch OF c02s05b00x00p05n01i02986ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s05b00x00p05n01i02986 - The simple name at the end of package declaration does not repeat the identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p05n01i02986arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2991.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2991.vhd
new file mode 100644
index 0000000..1a2d9cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2991.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2991.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p02n01i02991pkg is
+  generic ( N : Natural := 2 ) ;  -- Failure_here
+  -- ERROR: GENERIC DECLARATIONS NOT ALLOWED IN PACKAGES
+end c02s05b00x00p02n01i02991pkg;
+
+ENTITY c02s05b00x00p02n01i02991ent IS
+END c02s05b00x00p02n01i02991ent;
+
+ARCHITECTURE c02s05b00x00p02n01i02991arch OF c02s05b00x00p02n01i02991ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s05b00x00p02n01i02991 - Generic declarations are not allowed in package declarations."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p02n01i02991arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2992.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2992.vhd
new file mode 100644
index 0000000..c782240
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2992.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2992.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p02n01i02992pkg is
+  architecture AB of E is   -- Failure_here
+    -- ERROR: BODY DECLARATIONS ARE NOT ALLOWED IN PACKAGES
+  begin
+    process
+    begin
+      null;
+    end process;
+  end AB;
+  end c02s05b00x00p02n01i02992pkg;
+
+  ENTITY c02s05b00x00p02n01i02992ent IS
+  END c02s05b00x00p02n01i02992ent;
+
+  ARCHITECTURE c02s05b00x00p02n01i02992arch OF c02s05b00x00p02n01i02992ent IS
+
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE
+        report "***FAILED TEST: c02s05b00x00p02n01i02992 - Body declarations are not allowed within package declaration."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c02s05b00x00p02n01i02992arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2993.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2993.vhd
new file mode 100644
index 0000000..d30c9b3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2993.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2993.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p02n01i02993pkg is
+  package P2 is  -- Failure_here
+    -- ERROR: PACKAGE DECLARATIONS ARE NOT ALLOWED IN PACKAGES
+    type INIT_1 is RANGE 1 to 10;
+  end P2;
+  end c02s05b00x00p02n01i02993pkg;
+
+  ENTITY c02s05b00x00p02n01i02993ent IS
+  END c02s05b00x00p02n01i02993ent;
+
+  ARCHITECTURE c02s05b00x00p02n01i02993arch OF c02s05b00x00p02n01i02993ent IS
+
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE
+        report "***FAILED TEST: c02s05b00x00p02n01i02993 - Package declarations are not allowed within packages."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c02s05b00x00p02n01i02993arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2994.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2994.vhd
new file mode 100644
index 0000000..b11880e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2994.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2994.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p02n01i02994pkg is
+  assert V2 >= 10;  -- failure_here
+  -- ERROR: ASSERT DIRECTIVES ARE NOT ALLOWED IN PACKAGES
+end c02s05b00x00p02n01i02994pkg;
+
+ENTITY c02s05b00x00p02n01i02994ent IS
+END c02s05b00x00p02n01i02994ent;
+
+ARCHITECTURE c02s05b00x00p02n01i02994arch OF c02s05b00x00p02n01i02994ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s05b00x00p02n01i02994 - Package declarations are not allowed within packages."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p02n01i02994arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2995.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2995.vhd
new file mode 100644
index 0000000..8b89300
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2995.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2995.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p02n01i02995pkg is
+  for BLOCK_LABEL1   -- Failure_here
+-- ERROR: CONFIGURATION SPECIFICATIONS NOT ALLOWED IN PACKAGES
+end for;
+end c02s05b00x00p02n01i02995pkg;
+
+ENTITY c02s05b00x00p02n01i02995ent IS
+END c02s05b00x00p02n01i02995ent;
+
+ARCHITECTURE c02s05b00x00p02n01i02995arch OF c02s05b00x00p02n01i02995ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s05b00x00p02n01i02995 - Configuration Specifications are not allowed in packages."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p02n01i02995arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2996.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2996.vhd
new file mode 100644
index 0000000..2bb016f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2996.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2996.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p02n01i02996pkg is
+  port (PT : BOOLEAN); -- Failure_here
+  -- ERROR: PORT DECLARATIONS ARE NOT ALLOWED IN PACKAGES
+  type INIT_2 is range 1 to 10;
+end c02s05b00x00p02n01i02996pkg;
+
+ENTITY c02s05b00x00p02n01i02996ent IS
+END c02s05b00x00p02n01i02996ent;
+
+ARCHITECTURE c02s05b00x00p02n01i02996arch OF c02s05b00x00p02n01i02996ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s05b00x00p02n01i02996 - Port declarations are not allowed in packages."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s05b00x00p02n01i02996arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2997.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2997.vhd
new file mode 100644
index 0000000..4191aae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2997.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2997.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s05b00x00p02n01i02997pkg is
+  entity E  is     -- Failure_here
+    -- ERROR: INTERFACE DECLARATIONS ARE NOT ALLOWED IN PACKAGES
+    port (PT: BOOLEAN) ;
+  end E;
+  end c02s05b00x00p02n01i02997pkg;
+
+  ENTITY c02s05b00x00p02n01i02997ent IS
+  END c02s05b00x00p02n01i02997ent;
+
+  ARCHITECTURE c02s05b00x00p02n01i02997arch OF c02s05b00x00p02n01i02997ent IS
+
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE
+        report "***FAILED TEST: c02s05b00x00p02n01i02997 - Interface declarations are not allowed within package declarations."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c02s05b00x00p02n01i02997arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2998.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2998.vhd
new file mode 100644
index 0000000..6861fef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2998.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2998.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p02n01i02998pkg is
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
+end c02s06b00x00p02n01i02998pkg;
+
+package body c02s06b00x00p02n01i02998pkg is
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+  begin
+    assert (I1 /= '1')
+      report "No failure on test" ;
+    assert (I3 /= 5)
+      report "No failure on test" ;
+  end PX;
+  ;
+
+  ENTITY c02s06b00x00p02n01i02998ent IS
+  END c02s06b00x00p02n01i02998ent;
+
+  ARCHITECTURE c02s06b00x00p02n01i02998arch OF c02s06b00x00p02n01i02998ent IS
+
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c02s06b00x00p02n01i02998 - Missing keyword end."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c02s06b00x00p02n01i02998arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2999.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2999.vhd
new file mode 100644
index 0000000..c58f152
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2999.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc2999.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p02n01i02999pkg is
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
+end c02s06b00x00p02n01i02999pkg;
+
+package body   is   --Failure here
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+  begin
+    assert (I1 /= '1')
+      report "No failure on test" ;
+    assert (I3 /= 5)
+      report "No failure on test" ;
+  end PX;
+end;
+
+ENTITY c02s06b00x00p02n01i02999ent IS
+END c02s06b00x00p02n01i02999ent;
+
+ARCHITECTURE c02s06b00x00p02n01i02999arch OF c02s06b00x00p02n01i02999ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c02s06b00x00p02n01i02999 - Missing pcakage simple name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p02n01i02999arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3.vhd
new file mode 100644
index 0000000..1ea0a99
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s01b00x00p03n01i00003ent IS
+END c04s01b00x00p03n01i00003ent;
+
+ARCHITECTURE c04s01b00x00p03n01i00003arch OF c04s01b00x00p03n01i00003ent IS
+  type t1  (l,m,n);  -- Error: missing 'is'
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s01b00x00p03n01i00003 - The reserved word 'is' is missing in the type declaration." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s01b00x00p03n01i00003arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc300.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc300.vhd
new file mode 100644
index 0000000..30ba17c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc300.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc300.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p03n01i00300ent IS
+END c03s01b04x00p03n01i00300ent;
+
+ARCHITECTURE c03s01b04x00p03n01i00300arch OF c03s01b04x00p03n01i00300ent IS
+  type REAL1 is range REAL'LOW-1.0 to REAL'HIGH+1.0;
+BEGIN
+  TESTING: PROCESS
+    variable temp : REAL1 := REAL'LOW - 1.0;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b04x00p03n01i00300 - Range exceeds implementation."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p03n01i00300arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3000.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3000.vhd
new file mode 100644
index 0000000..d064262
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3000.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3000.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p02n01i03000pkg is
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
+end c02s06b00x00p02n01i03000pkg;
+
+package body c02s06b00x00p02n01i03000pkg is
+  procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
+  begin
+    assert (I1 /= '1')
+      report "No failure on test" ;
+    assert (I3 /= 5)
+      report "No failure on test" ;
+  end PX;
+end      --Failure here
+
+  ENTITY c02s06b00x00p02n01i03000ent IS
+END c02s06b00x00p02n01i03000ent;
+
+ARCHITECTURE c02s06b00x00p02n01i03000arch OF c02s06b00x00p02n01i03000ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c02s06b00x00p02n01i03000 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p02n01i03000arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3002.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3002.vhd
new file mode 100644
index 0000000..716e839
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3002.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3002.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p05n02i03002pkg is
+end c02s06b00x00p05n02i03002pkg;
+
+package body c02s06b00x00p05n02i03002pkg is
+end c02s06b00x00p05n02i03002;   --Failure here
+
+ENTITY c02s06b00x00p05n02i03002ent IS
+END c02s06b00x00p05n02i03002ent;
+
+ARCHITECTURE c02s06b00x00p05n02i03002arch OF c02s06b00x00p05n02i03002ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s06b00x00p05n02i03002- The simple name at the end of a package body must be the same as the package identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p05n02i03002arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3003.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3003.vhd
new file mode 100644
index 0000000..fe57710
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3003.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3003.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p05n01i03003pkg is
+end c02s06b00x00p05n01i03003pkg;
+
+package body c02s06b00x00p05n01i03003 is   --Failure here
+end c02s06b00x00p05n01i03003;
+
+
+ENTITY c02s06b00x00p05n01i03003ent IS
+END c02s06b00x00p05n01i03003ent;
+
+ARCHITECTURE c02s06b00x00p05n01i03003arch OF c02s06b00x00p05n01i03003ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s06b00x00p05n01i03003 - The simple name at the start of a package body must repeat the package identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p05n01i03003arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3004.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3004.vhd
new file mode 100644
index 0000000..38b223e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3004.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3004.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p06n02i03004pkg is
+  constant C1 : integer := 10;
+end c02s06b00x00p06n02i03004pkg;
+
+package body c02s06b00x00p06n02i03004pkg is
+  constant C2 : integer := 0;
+end;
+
+use work.c02s06b00x00p06n02i03004pkg.all;
+ENTITY c02s06b00x00p06n02i03004ent IS
+END c02s06b00x00p06n02i03004ent;
+
+ARCHITECTURE c02s06b00x00p06n02i03004arch OF c02s06b00x00p06n02i03004ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable A1 : integer := work.c02s06b00x00p06n02i03004pkg.C1;
+    variable A2 : integer := workc02s06b00x00p06n02i03004pkg.C2; -- Failure_here
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s06b00x00p06n02i03004 - Items declared in the body of the package cannot be made visible outside the package body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p06n02i03004arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3006.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3006.vhd
new file mode 100644
index 0000000..1edffb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3006.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3006.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p07n01i03006pkg is
+  constant X : real;
+end c02s06b00x00p07n01i03006pkg;
+
+package bodyc02s06b00x00p07n01i03006pkg is
+  constant X1: real := 1.0;   --Failure_here
+end c02s06b00x00p07n01i03006pkg;
+
+ENTITY c02s06b00x00p07n01i03006ent IS
+END c02s06b00x00p07n01i03006ent;
+
+ARCHITECTURE c02s06b00x00p07n01i03006arch OF c02s06b00x00p07n01i03006ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s06b00x00p07n01i03006 - The deferred constant X does not have a full declaration in the package body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p07n01i03006arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3007.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3007.vhd
new file mode 100644
index 0000000..353cfc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3007.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3007.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p07n01i03007pkg is
+  constant X : real;
+end c02s06b00x00p07n01i03007pkg;
+
+package body c02s06b00x00p07n01i03007pkg is
+  constant X: integer := 1;  --Failure_here
+end c02s06b00x00p07n01i03007pkg;
+
+ENTITY c02s06b00x00p07n01i03007ent IS
+END c02s06b00x00p07n01i03007ent;
+
+ARCHITECTURE c02s06b00x00p07n01i03007arch OF c02s06b00x00p07n01i03007ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s06b00x00p07n01i03007 - The subtype of constant in the full declaratio does not conform to that given in the deferred constant declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p07n01i03007arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3008.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3008.vhd
new file mode 100644
index 0000000..8c002d5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3008.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3008.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p07n01i03008pkg is
+  constant C : integer;
+end c02s06b00x00p07n01i03008pkg;
+
+package body c02s06b00x00p07n01i03008pkg is
+  subtype    S1 is Integer;
+  constant    C : S1 := 0;    --Failure_here
+end c02s06b00x00p07n01i03008pkg;
+
+ENTITY c02s06b00x00p07n01i03008ent IS
+END c02s06b00x00p07n01i03008ent;
+
+ARCHITECTURE c02s06b00x00p07n01i03008arch OF c02s06b00x00p07n01i03008ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s06b00x00p07n01i03008 - The subtype of deferred constant C does not conform to that given in the full declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p07n01i03008arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3009.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3009.vhd
new file mode 100644
index 0000000..399042a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3009.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3009.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p07n01i03009pkg is
+  subtype    S1 is Integer;
+  subtype    S2 is Integer;
+  constant    C  :  S1;
+end c02s06b00x00p07n01i03009pkg;
+
+package body c02s06b00x00p07n01i03009pkg is
+  constant C : S2 := 0;  --Failure_here
+end c02s06b00x00p07n01i03009pkg;
+
+ENTITY c02s06b00x00p07n01i03009ent IS
+END c02s06b00x00p07n01i03009ent;
+
+ARCHITECTURE c02s06b00x00p07n01i03009arch OF c02s06b00x00p07n01i03009ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s06b00x00p07n01i03009 - The subtype of deferred constant does not conform to that given in the deferred constant declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p07n01i03009arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3011.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3011.vhd
new file mode 100644
index 0000000..74b90d7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3011.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3011.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p08n01i03011pkg is
+  constant X1 : real;
+end c02s06b00x00p08n01i03011pkg;
+
+package body c02s06b00x00p08n01i03011pkg is
+  constant X1 : real := X1;   --Failure here
+end c02s06b00x00p08n01i03011pkg;
+
+
+ENTITY c02s06b00x00p08n01i03011ent IS
+END c02s06b00x00p08n01i03011ent;
+
+ARCHITECTURE c02s06b00x00p08n01i03011arch OF c02s06b00x00p08n01i03011ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s06b00x00p08n01i03011 - A name that denotes the name of a deferred constant can appear, before the full declaration only in the default expression for a local generic, local port, or a formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p08n01i03011arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3012.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3012.vhd
new file mode 100644
index 0000000..e993d82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3012.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3012.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c02s06b00x00p08n01i03012pkg is
+  constant X1 : integer;
+  constant X2 : integer;
+end c02s06b00x00p08n01i03012pkg;
+
+package body c02s06b00x00p08n01i03012pkg is
+  constant X1: integer := X2;  --Failure_here
+  constant X2: integer := 1;
+end c02s06b00x00p08n01i03012pkg;
+
+
+ENTITY c02s06b00x00p08n01i03012ent IS
+END c02s06b00x00p08n01i03012ent;
+
+ARCHITECTURE c02s06b00x00p08n01i03012arch OF c02s06b00x00p08n01i03012ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c02s06b00x00p08n01i03012 - A name that denotes the name of a deferred constant can appear, before the full declaration only in the default expression for a local generic, local port, or a formal parameter."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c02s06b00x00p08n01i03012arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3013.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3013.vhd
new file mode 100644
index 0000000..9809109
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3013.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3013.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+use work.all;
+ENTITY c11s01b00x00p07n01i03013ent IS
+END c11s01b00x00p07n01i03013ent;
+use work.c11s01b00x00p07n01i03013pkg.all;
+ARCHITECTURE c11s01b00x00p07n01i03013arch OF c11s01b00x00p07n01i03013ent IS
+  signal S1 : MVL;    -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s01b00x00p07n01i03013 - Symbol not defined."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+END c11s01b00x00p07n01i03013arch;
+
+
+package c11s01b00x00p07n01i03013pkg is
+  type MVL is ('0', '1', 'X', 'Z');
+end c11s01b00x00p07n01i03013pkg;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3014.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3014.vhd
new file mode 100644
index 0000000..4433afc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3014.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3014.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c11s01b00x00p08n03i03014ent is
+  procedure test;
+end c11s01b00x00p08n03i03014ent;
+
+package body c11s01b00x00p08n03i03014ent is
+  procedure test  is
+  begin
+    assert false
+      report "Duplicate primary unit name allowed in same library -- test fails."
+      severity note ;
+  end test;
+end c11s01b00x00p08n03i03014ent;
+
+use work.c11s01b00x00p08n03i03014ent.all;
+ENTITY c11s01b00x00p08n03i03014ent IS
+END c11s01b00x00p08n03i03014ent;
+
+ARCHITECTURE c11s01b00x00p08n03i03014arch OF c11s01b00x00p08n03i03014ent IS
+
+BEGIN
+  c11s01b00x00p08n03i03014ent.test;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s01b00x00p08n03i03014d - Duplicate primary unit name is not allowed in same library."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s01b00x00p08n03i03014arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3015.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3015.vhd
new file mode 100644
index 0000000..7bce48a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3015.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3015.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c11s02b00x00p05n02i03015ent IS
+  library work;      -- ERROR:
+  -- failure_here.
+END c11s02b00x00p05n02i03015ent;
+
+ARCHITECTURE c11s02b00x00p05n02i03015arch OF c11s02b00x00p05n02i03015ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s02b00x00p05n02i03015 - Library clause should appear as part of a context clause at the beginning of a design unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s02b00x00p05n02i03015arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3017.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3017.vhd
new file mode 100644
index 0000000..19489bd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3017.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3017.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library lib01;
+use lib01.c11s02b00x00p05n03i03017pkg.all;
+
+ENTITY c11s02b00x00p05n03i03017ent IS
+  assert my_bool
+    report "Library clause preceeding entity is valid in entity scope."
+    severity note;
+END c11s02b00x00p05n03i03017ent;
+
+
+use lib01.c11s02b00x00p05n03i03017pkg.all;         -- lib01 unknown Failed_here
+ENTITY c11s02b00x00p05n03i03017ent IS
+  assert my_bool
+    report "Library clause is valid outside entity scope - test fails."
+    severity note ;
+END c11s02b00x00p05n03i03017ent;
+
+ARCHITECTURE c11s02b00x00p05n03i03017arch OF c11s02b00x00p05n03i03017ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s02b00x00p05n03i03017 - Library clause only extends to the end of the declatative region associated with the design unit"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s02b00x00p05n03i03017arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3019.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3019.vhd
new file mode 100644
index 0000000..26e01d4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3019.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3019.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package body c11s02b00x00p14n01i03019pkg is                   --- Failure_here
+  type MVL2 is ('0','1','X','Z') ;
+end c11s02b00x00p14n01i03019pkg;
+
+ENTITY c11s02b00x00p14n01i03019ent IS
+END c11s02b00x00p14n01i03019ent;
+
+ARCHITECTURE c11s02b00x00p14n01i03019arch OF c11s02b00x00p14n01i03019ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s02b00x00p14n01i03019 - Secondary unit must reside in the same library as the primary unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s02b00x00p14n01i03019arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc302.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc302.vhd
new file mode 100644
index 0000000..3c16e1d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc302.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc302.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p04n01i00302ent IS
+END c03s01b04x00p04n01i00302ent;
+
+ARCHITECTURE c03s01b04x00p04n01i00302arch OF c03s01b04x00p04n01i00302ent IS
+  type REAL1 is range 1.0 to 9;  -- Failure_here
+  -- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
+  -- DEFINITION MUST BE OF FLOATING POINT TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b04x00p04n01i00302 - Range constraint must be floating point."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p04n01i00302arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3020.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3020.vhd
new file mode 100644
index 0000000..d8fbae0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3020.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3020.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library  ;     --- Failure_here
+
+ENTITY c11s02b00x00p02n01i03020ent IS
+END c11s02b00x00p02n01i03020ent;
+
+ARCHITECTURE c11s02b00x00p02n01i03020arch OF c11s02b00x00p02n01i03020ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s02b00x00p02n01i03020 - Missing library logical name list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s02b00x00p02n01i03020arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3021.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3021.vhd
new file mode 100644
index 0000000..789ec3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3021.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3021.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+library STANDARD, "-" ;     --- Failure_here
+use STD.STANDARD.all;
+
+ENTITY c11s02b00x00p02n01i03021ent IS
+END c11s02b00x00p02n01i03021ent;
+
+ARCHITECTURE c11s02b00x00p02n01i03021arch OF c11s02b00x00p02n01i03021ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s02b00x00p02n01i03021 - Improper logical name list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s02b00x00p02n01i03021arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3025.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3025.vhd
new file mode 100644
index 0000000..319fb83
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3025.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3025.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c11s04b00x00p07n03i03025pkg_p is
+end c11s04b00x00p07n03i03025p;
+
+use work.c11s04b00x00p07n03i03025pkg_p.all;
+package c11s04b00x00p07n03i03025pkg_pp is
+end c11s04b00x00p07n03i03025pkg_pp;
+
+use work.c11s04b00x00p07n03i03025pkg_pp.all;
+package c11s04b00x00p07n03i03025pkg_ppp is
+end c11s04b00x00p07n03i03025pkg_ppp;
+
+
+package c11s04b00x00p07n03i03025pkg_p is
+end c11s04b00x00p07n03i03025pkg_p;
+
+use work.c11s04b00x00p07n03i03025pkg_pp.all;   -- Failure_here
+package c11s04b00x00p07n03i03025pkg_ppp is
+end c11s04b00x00p07n03i03025pkg_ppp;
+
+ENTITY c11s04b00x00p07n03i03025ent IS
+END c11s04b00x00p07n03i03025ent;
+
+ARCHITECTURE c11s04b00x00p07n03i03025arch OF c11s04b00x00p07n03i03025ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s04b00x00p07n03i03025 - Package ch1104_p00703_01_pkg_pp has been changed since last analysis."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s04b00x00p07n03i03025arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3026.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3026.vhd
new file mode 100644
index 0000000..d4239f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3026.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3026.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c11s04b00x00p02n01i03026ent IS
+END c11s04b00x00p02n01i03026ent;
+
+
+configuration c11s04b00x00p02n01i03026cfg of c11s04b00x00p02n01i03026ent is
+  for c11s04b00x00p02n01i03026arch
+  end for;
+end c11s04b00x00p02n01i03026cfg;
+
+ARCHITECTURE c11s04b00x00p02n01i03026arch OF c11s04b00x00p02n01i03026ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s04b00x00p02n01i03026 - Architecture body must be analyzed before the configuration body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s04b00x00p02n01i03026arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3027.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3027.vhd
new file mode 100644
index 0000000..f602922
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3027.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3027.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c11s04b00x00p02n01i03027ent IS
+END c11s04b00x00p02n01i03027ent;
+
+ARCHITECTURE c11s04b00x00p02n01i03027arch OF c11s04b00x00p02n01i03027ent IS
+  use work.unknown.all;   -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s04b00x00p02n01i03027 - Unknown entity."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s04b00x00p02n01i03027arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3028.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3028.vhd
new file mode 100644
index 0000000..ca9f8d2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3028.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3028.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+use work.c11s04b00x00p02n01i03028pkg_a.all;
+ENTITY c11s04b00x00p02n01i03028ent IS
+END c11s04b00x00p02n01i03028ent;
+
+package c11s04b00x00p02n01i03028pkg_a is
+end c11s04b00x00p02n01i03028pkg_a;
+
+ARCHITECTURE c11s04b00x00p02n01i03028arch OF c11s04b00x00p02n01i03028ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s04b00x00p02n01i03028 - Primary unit must be analyzed before the analysis of the unit that references it."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s04b00x00p02n01i03028arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc303.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc303.vhd
new file mode 100644
index 0000000..9aef03f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc303.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc303.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p04n01i00303ent IS
+END c03s01b04x00p04n01i00303ent;
+
+ARCHITECTURE c03s01b04x00p04n01i00303arch OF c03s01b04x00p04n01i00303ent IS
+  type REAL2 is range 0.0 to TRUE;  -- Failure_here
+  -- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
+  -- DEFINITION MUST BE OF FLOATING POINT TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b04x00p04n01i00303 - Range constraint must be floating point."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p04n01i00303arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3030.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3030.vhd
new file mode 100644
index 0000000..797f57d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3030.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3030.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package body c11s04b00x00p02n01i03030pkg is
+end c11s04b00x00p02n01i03030pkg;
+
+ENTITY c11s04b00x00p02n01i03030ent IS
+END c11s04b00x00p02n01i03030ent;
+
+ARCHITECTURE c11s04b00x00p02n01i03030arch OF c11s04b00x00p02n01i03030ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s04b00x00p02n01i03030 - A primary unit must be analyzed prior to the analysis of any corresponding secondary unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s04b00x00p02n01i03030arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3031.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3031.vhd
new file mode 100644
index 0000000..70d369a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3031.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3031.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ARCHITECTURE c11s04b00x00p02n01i03031arch OF c11s04b00x00p02n01i03031ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c11s04b00x00p02n01i03031 - A primary unit must be analyzed prior to the analysis of any corresponding secondary unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c11s04b00x00p02n01i03031arch;
+
+ENTITY c11s04b00x00p02n01i03031ent IS
+END c11s04b00x00p02n01i03031ent;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc304.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc304.vhd
new file mode 100644
index 0000000..b9bfb3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc304.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc304.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p04n01i00304ent IS
+END c03s01b04x00p04n01i00304ent;
+
+ARCHITECTURE c03s01b04x00p04n01i00304arch OF c03s01b04x00p04n01i00304ent IS
+  type REAL3 is range "0" to 9.0 ;  -- Failure_here
+  -- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
+  -- DEFINITION MUST BE OF FLOATING POINT TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b04x00p04n01i00304 - Range constraint must be floating point."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p04n01i00304arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc305.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc305.vhd
new file mode 100644
index 0000000..1d9f031
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc305.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc305.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p04n01i00305ent IS
+END c03s01b04x00p04n01i00305ent;
+
+ARCHITECTURE c03s01b04x00p04n01i00305arch OF c03s01b04x00p04n01i00305ent IS
+  type REAL4 is range 0.00 to "999";  -- Failure_here
+  -- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
+  -- DEFINITION MUST BE OF FLOATING POINT TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b04x00p04n01i00305 - Range constraint must be floating point."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p04n01i00305arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3058.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3058.vhd
new file mode 100644
index 0000000..655f09f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3058.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3058.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b01x05p01n02i03058ent IS
+END c12s03b01x05p01n02i03058ent;
+
+ARCHITECTURE c12s03b01x05p01n02i03058arch OF c12s03b01x05p01n02i03058ent IS
+  signal R_NUM : BIT_VECTOR(0 to 31);
+  alias  NUMB  : BIT_VECTOR(21 downto 0) is R_NUM(8 to 31);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c12s03b01x05p01n02i03058 - Alias for an array object does not have a matching element for each element of the named object."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b01x05p01n02i03058arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc306.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc306.vhd
new file mode 100644
index 0000000..821fce3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc306.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc306.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p04n01i00306ent IS
+END c03s01b04x00p04n01i00306ent;
+
+ARCHITECTURE c03s01b04x00p04n01i00306arch OF c03s01b04x00p04n01i00306ent IS
+  type REAL5 is range B"000" to B"111";  -- Failure_here
+  -- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
+  -- DEFINITION MUST BE OF FLOATING POINT TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b04x00p04n01i00306 - Range constraint must be floating point."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p04n01i00306arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3064.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3064.vhd
new file mode 100644
index 0000000..0aee677
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3064.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3064.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s03b02x02p05n01i03064ent IS
+  port(con : in BIT := '1'; clk : out BIT);
+END c12s03b02x02p05n01i03064ent;
+
+ARCHITECTURE c12s03b02x02p05n01i03064arch OF c12s03b02x02p05n01i03064ent IS
+
+BEGIN
+  TESTING: PROCESS
+  begin
+    clk <= con;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b02x02p05n01i03064arch_a;
+
+
+ENTITY c12s03b02x02p05n01i03064ent IS
+  port (C : out bit);
+END c12s03b02x02p05n01i03064ent;
+
+ARCHITECTURE c12s03b02x02p05n01i03064arch OF c12s03b02x02p05n01i03064ent IS
+  component c12s03b02x02p05n01i03064ent_aa 
+    port(con : in bit:='1'; clk : out bit);
+  end component;
+  for all: c12s03b02x02p05n01i03064ent_aa use entity work.fail(c12s03b02x02p05n01i03064arch_a);       -- Failure_here
+BEGIN
+  T1: test port map(open,C);
+  TESTING: PROCESS
+  BEGIN
+    assert FAILED
+      report "***FAILED TEST: c12s03b02x02p05n01i03064 - Entity declaration and the corresponding body implied by the binding indication do not exist within the specified library."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b02x02p05n01i03064arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc307.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc307.vhd
new file mode 100644
index 0000000..c79ac0c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc307.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc307.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p04n01i00307ent IS
+END c03s01b04x00p04n01i00307ent;
+
+ARCHITECTURE c03s01b04x00p04n01i00307arch OF c03s01b04x00p04n01i00307ent IS
+  type ENUM1 is (ONE, TWO, THREE);
+  type REAL6 is range TWO to 3.0;  -- Failure_here
+  -- ERROR - SEMANTIC ERROR: RANGE CONSTRAINT IN FLOATING POINT TYPE
+  -- DEFINITION MUST BE OF FLOATING POINT TYPE
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s01b04x00p04n01i00307 - Range constraint must be floating point."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p04n01i00307arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3087.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3087.vhd
new file mode 100644
index 0000000..52fdd01
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3087.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3087.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p01n01i03087ent IS
+END c05s01b00x00p01n01i03087ent;
+
+ARCHITECTURE c05s01b00x00p01n01i03087arch OF c05s01b00x00p01n01i03087ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c05s01b00x00p01n01i03087"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c05s01b00x00p01n01i03087"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c05s01b00x00p01n01i03087arch;
+
+-- CONFIGURATION c05s01b00x00p01n01i03087cfg OF c05s01b00x00p01n01i03087ent IS
+--     FOR c05s01b00x00p01n01i03087arch
+--     END FOR;
+-- END c05s01b00x00p01n01i03087cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3088.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3088.vhd
new file mode 100644
index 0000000..126410a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3088.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3088.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p01n01i03088ent IS
+  attribute   ill1    : real;
+  signal       s1, s2   : integer;
+  attribute    ill1 of s1 : signal is 10.0;
+  attribute LAST_EVENT of s2 : signal is 20;  -- Failure_here
+END c05s01b00x00p01n01i03088ent;
+
+ARCHITECTURE c05s01b00x00p01n01i03088arch OF c05s01b00x00p01n01i03088ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p01n01i03088 - The attribute must be declared before."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p01n01i03088arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3089.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3089.vhd
new file mode 100644
index 0000000..551ab4f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3089.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3089.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p02n01i03089ent IS
+END c05s01b00x00p02n01i03089ent;
+
+ARCHITECTURE c05s01b00x00p02n01i03089arch OF c05s01b00x00p02n01i03089ent IS
+  type       a    is range 1 to 10;
+  attribute    left   : integer;
+  attribute     of    a : type is 5;   --- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p02n01i03089 - Missing attribute designator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p02n01i03089arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3091.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3091.vhd
new file mode 100644
index 0000000..1e2aaba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3091.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3091.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p02n01i03091ent IS
+END c05s01b00x00p02n01i03091ent;
+
+ARCHITECTURE c05s01b00x00p02n01i03091arch OF c05s01b00x00p02n01i03091ent IS
+  type       a    is range 1 to 10;
+  attribute    left   : integer;
+  attribute    left    of : type is 5;   --- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p02n01i03091 - Missing entity specification."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p02n01i03091arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3092.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3092.vhd
new file mode 100644
index 0000000..b5dacfe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3092.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3092.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p02n01i03092ent IS
+END c05s01b00x00p02n01i03092ent;
+
+ARCHITECTURE c05s01b00x00p02n01i03092arch OF c05s01b00x00p02n01i03092ent IS
+  type       a    is    range 1 to 10;
+  attribute    left   :    integer;
+  attribute    left    of    a : type is 5   --- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p02n01i03092 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p02n01i03092arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3093.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3093.vhd
new file mode 100644
index 0000000..0064423
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3093.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3093.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p02n01i03093ent IS
+END c05s01b00x00p02n01i03093ent;
+
+ARCHITECTURE c05s01b00x00p02n01i03093arch OF c05s01b00x00p02n01i03093ent IS
+  type       a    is range 1 to 10;
+  attribute    left   : integer;
+  attribute    left    of a : is 5;   --- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p02n01i03093 - Missing entity class."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p02n01i03093arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3094.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3094.vhd
new file mode 100644
index 0000000..341218f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3094.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3094.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c05s01b00x00p02n01i03094pkg is
+  type a1 is range 1 to 20;
+end c05s01b00x00p02n01i03094pkg;
+
+
+ENTITY c05s01b00x00p02n01i03094ent IS
+END c05s01b00x00p02n01i03094ent;
+
+ARCHITECTURE c05s01b00x00p02n01i03094arch OF c05s01b00x00p02n01i03094ent IS
+  type       a    is range 1 to 10;
+  attribute    left   : integer;
+  attribute    left    of work.c05s01b00x00p02n01i03094pkg.a1 : type is 5;   --- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p02n01i03094 - Expanded name can not be used as an entity designator."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p02n01i03094arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3095.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3095.vhd
new file mode 100644
index 0000000..9070f16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3095.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3095.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p08n01i03095ent IS
+END c05s01b00x00p08n01i03095ent;
+
+ARCHITECTURE c05s01b00x00p08n01i03095arch OF c05s01b00x00p08n01i03095ent IS
+  attribute    A1 : INTEGER;
+  signal       S1 : BOOLEAN;
+  attribute    A2 of S1 : signal is 9;  -- Failure_here
+  -- ERROR : no preceding user-defined attribute declaration for A2
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p08n01i03095 - User defined attribute has to be predefined."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p08n01i03095arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3096.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3096.vhd
new file mode 100644
index 0000000..18c8f26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3096.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3096.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p08n01i03096ent IS
+END c05s01b00x00p08n01i03096ent;
+
+ARCHITECTURE c05s01b00x00p08n01i03096arch OF c05s01b00x00p08n01i03096ent IS
+  attribute    ill1      : real;
+  signal       s1, s2      : integer;
+  attribute    notdesig of s1   : signal is 10.0; -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p08n01i03096 - The attribute designator does not denote an attribute."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p08n01i03096arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3097.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3097.vhd
new file mode 100644
index 0000000..6abd184
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3097.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3097.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p09n02i03097ent IS
+END c05s01b00x00p09n02i03097ent;
+
+ARCHITECTURE c05s01b00x00p09n02i03097arch OF c05s01b00x00p09n02i03097ent IS
+  attribute    ill1   : real;
+  signal       s1, s2   : integer;
+  attribute    ill1 of s1, s2: constant is 10.0; -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p09n02i03097 - The class of those names used in the entity name list in the entity specification in an attribute specification is not the same as that denoted by the entity class."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p09n02i03097arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3098.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3098.vhd
new file mode 100644
index 0000000..5b15dd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3098.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3098.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p09n02i03098ent IS
+END c05s01b00x00p09n02i03098ent;
+
+ARCHITECTURE c05s01b00x00p09n02i03098arch OF c05s01b00x00p09n02i03098ent IS
+
+BEGIN
+  TESTING: PROCESS
+    attribute    ATT    : integer;
+    type       T1    is range 1 to 100000 ;
+    variable    V1    : Integer := 0 ;
+    attribute    Att    of T1,V1 : type is 2 ;  -- Failure_here
+    -- ERROR: only name which belong to the entity class are permitted in an entity name list.
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p09n02i03098 - Entity name does not belong to entity name list."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p09n02i03098arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc310.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc310.vhd
new file mode 100644
index 0000000..39ff89f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc310.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc310.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b04x00p06n01i00310ent IS
+END c03s01b04x00p06n01i00310ent;
+
+ARCHITECTURE c03s01b04x00p06n01i00310arch OF c03s01b04x00p06n01i00310ent IS
+  type R1 is range -10.0 to 10.0;
+  constant C1 : R1 := 2.0 ;
+  signal S1 : R1;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 <= C1 * 6.0 after 5 ns;
+    wait for 10 ns;
+    assert NOT(S1 = 12.0)
+      report "***PASSED TEST: c03s01b04x00p06n01i00310"
+      severity NOTE;
+    assert ( S1=12.0)
+      report "***FAILED TEST: c03s01b04x00p06n01i00310 - Value not within bounds." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b04x00p06n01i00310arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3103.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3103.vhd
new file mode 100644
index 0000000..1c1e12c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3103.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3103.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p12n01i03103ent IS
+END c05s01b00x00p12n01i03103ent;
+
+ARCHITECTURE c05s01b00x00p12n01i03103arch OF c05s01b00x00p12n01i03103ent IS
+  attribute    ill1   : real;
+  signal       s1, s2   : integer;
+  attribute    ill1 of s1    : signal is 10.0;
+  attribute    ill1 of others    : signal is 10.0;
+  attribute    ill1 of s2    : signal is 10.0;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p12n01i03103 - The attribute specification with the entity name list others must be the last such specification."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p12n01i03103arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3104.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3104.vhd
new file mode 100644
index 0000000..8f57a95
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3104.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3104.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p16n02i03104ent IS
+  port    (PT:BOOLEAN);
+  attribute AT1 : integer;
+  attribute AT1 of ch0501_P01602_02_ent : entity is 1.2;  --  Failure_here
+  --ERROR:  Specification expression is not the same type as attribute declaration
+END c05s01b00x00p16n02i03104ent;
+
+ARCHITECTURE c05s01b00x00p16n02i03104arch OF c05s01b00x00p16n02i03104ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p16n02i03104 - Specification expression is not of the same type as attribute specification."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p16n02i03104arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3105.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3105.vhd
new file mode 100644
index 0000000..f83b41d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3105.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3105.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c05s01b00x00p16n02i03105ent IS
+END c05s01b00x00p16n02i03105ent;
+
+ARCHITECTURE c05s01b00x00p16n02i03105arch OF c05s01b00x00p16n02i03105ent IS
+  attribute    ill1      : real;
+  signal       s1, s2      : integer;
+  attribute    ill1 of s1    : signal is 10.0;
+  attribute    ill1 of others    : signal is 10;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p16n02i03105 - The type of the expression in the attribute specification is not the same as (or implicitly convertible to) the type mark in the corresponding attribute declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p16n02i03105arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3106.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3106.vhd
new file mode 100644
index 0000000..baddad5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3106.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3106.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c05s01b00x00p17n01i03106pkg is
+  attribute p: POSITIVE;
+  attribute p of c05s01b00x00p17n01i03106pkg : package   is 10;
+end c05s01b00x00p17n01i03106pkg;
+
+
+use work.c05s01b00x00p17n01i03106pkg.all;
+ENTITY c05s01b00x00p17n01i03106ent IS
+END c05s01b00x00p17n01i03106ent;
+
+ARCHITECTURE c05s01b00x00p17n01i03106arch OF c05s01b00x00p17n01i03106ent IS
+
+BEGIN
+  blk : block
+    attribute p of c05s01b00x00p17n01i03106arch : architecture is 10; -- Failure_here
+  begin
+  end block blk;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p17n01i03106 - The attribute specification for an attribute of a design unit does not appear immediately within the declarative part of that design unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p17n01i03106arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3107.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3107.vhd
new file mode 100644
index 0000000..6078c1c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3107.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3107.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c05s01b00x00p17n01i03107pkg is
+  attribute p: POSITIVE;
+  attribute p of c05s01b00x00p17n01i03107pkg : package   is 10;
+end c05s01b00x00p17n01i03107pkg;
+
+
+use work.c05s01b00x00p17n01i03107pkg.all;
+ENTITY c05s01b00x00p17n01i03107ent IS
+END c05s01b00x00p17n01i03107ent;
+
+ARCHITECTURE c05s01b00x00p17n01i03107arch OF c05s01b00x00p17n01i03107ent IS
+  attribute p of c05s01b00x00p17n01i03107ent : entity is 10;       -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p17n01i03107 - The attribute specification for an attribute of a design unit does not appear immediately within the declarative part of that design unit."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p17n01i03107arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3108.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3108.vhd
new file mode 100644
index 0000000..e8b9282
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3108.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3108.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c05s01b00x00p17n01i03108pkg is
+  attribute A1 : INTEGER;
+end c05s01b00x00p17n01i03108pkg;
+
+
+use work.c05s01b00x00p17n01i03108pkg.all;
+ENTITY c05s01b00x00p17n01i03108ent IS
+END c05s01b00x00p17n01i03108ent;
+
+ARCHITECTURE c05s01b00x00p17n01i03108arch OF c05s01b00x00p17n01i03108ent IS
+  attribute A1 of c05s01b00x00p17n01i03108pkg : package is 9 ;  -- Failure_here
+  -- ERROR: package attribute specification can appear only immediatly
+  -- within the declarative region of a package
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c05s01b00x00p17n01i03108 - Package attribute specification can appear only immediately in package declarative part."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c05s01b00x00p17n01i03108arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc315.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc315.vhd
new file mode 100644
index 0000000..1e2c96f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc315.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc315.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b00x00p03n02i00315ent IS
+END c03s02b00x00p03n02i00315ent;
+
+ARCHITECTURE c03s02b00x00p03n02i00315arch OF c03s02b00x00p03n02i00315ent IS
+  type FT is file of integer;
+  type a12 is array (1 to 10) of FT;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b00x00p03n02i00315 - Elements of file types are not allowed in a composite type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b00x00p03n02i00315arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc316.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc316.vhd
new file mode 100644
index 0000000..297b388
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc316.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc316.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b00x00p03n02i00316ent IS
+END c03s02b00x00p03n02i00316ent;
+
+ARCHITECTURE c03s02b00x00p03n02i00316arch OF c03s02b00x00p03n02i00316ent IS
+  type FT is file of integer;
+  type rec_type is
+    record
+      x : bit;
+      y : integer;
+      z : FT;      -- Failure_here
+    end record;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b00x00p03n02i00316 - Elements of file types are not allowed in a composite type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b00x00p03n02i00316arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3161.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3161.vhd
new file mode 100644
index 0000000..4034e91
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3161.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3161.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c14s01b00x00p07n01i03161ent IS
+END c14s01b00x00p07n01i03161ent;
+
+ARCHITECTURE c14s01b00x00p07n01i03161arch OF c14s01b00x00p07n01i03161ent IS
+  type T1 is (A,B,C,D,E);
+  type T2 is (A,B,C,D,E);
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T1;
+    variable V2 : T2;
+  BEGIN
+    if (T2'BASE'LEFT = T1'BASE'LEFT) then   --- Failure_here
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c14s01b00x00p07n01i03161 - Type mismatch."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c14s01b00x00p07n01i03161arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3207.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3207.vhd
new file mode 100644
index 0000000..e670d9e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3207.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3207.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x01p04n04i03207ent IS
+END c01s01b01x01p04n04i03207ent;
+
+ARCHITECTURE c01s01b01x01p04n04i03207arch OF c01s01b01x01p04n04i03207ent IS
+  -- architecture declaration section
+BEGIN
+  -- architecture statement part
+  TESTING: PROCESS
+  BEGIN
+    -- testcase code
+    Assert FALSE
+      Report "***PASSED TEST: c01s01b01x01p04n04i03207"
+      Severity NOTE;
+    -- testcase code
+    Assert FALSE
+      Report "***FAILED TEST: c01s01b01x01p04n04i03207"
+      Severity ERROR;
+    wait; -- forever
+  END PROCESS TESTING;
+END c01s01b01x01p04n04i03207arch;
+
+-- CONFIGURATION c01s01b01x01p04n04i03207cfg OF c01s01b01x01p04n04i03207ent IS
+--     FOR c01s01b01x01p04n04i03207arch
+--     END FOR;
+-- END c01s01b01x01p04n04i03207cfg;
+
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc321.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc321.vhd
new file mode 100644
index 0000000..c5239ca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc321.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc321.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p03n01i00321ent IS
+END c03s02b01x00p03n01i00321ent;
+
+ARCHITECTURE c03s02b01x00p03n01i00321arch OF c03s02b01x00p03n01i00321ent IS
+-- Failure_here : missing type_mark
+  type er1 is array(range <>) of integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p03n01i00321 - The type mark in the index subtype definition is absent." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p03n01i00321arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc324.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc324.vhd
new file mode 100644
index 0000000..931df2a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc324.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc324.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p04n01i00324ent IS
+END c03s02b01x00p04n01i00324ent;
+
+ARCHITECTURE c03s02b01x00p04n01i00324arch OF c03s02b01x00p04n01i00324ent IS
+  type bit_vctor is array (integer => 1 to 8) of integer; --Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p04n01i00324 - The index constraint is not valid." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p04n01i00324arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc325.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc325.vhd
new file mode 100644
index 0000000..43d27a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc325.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc325.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p04n01i00325ent IS
+END c03s02b01x00p04n01i00325ent;
+
+ARCHITECTURE c03s02b01x00p04n01i00325arch OF c03s02b01x00p04n01i00325ent IS
+  type  it is  array (character, positive range <>) of bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p04n01i00325 - The index constraint is not valid." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p04n01i00325arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc327.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc327.vhd
new file mode 100644
index 0000000..2d01ce2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc327.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc327.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p04n01i00327ent IS
+END c03s02b01x00p04n01i00327ent;
+
+ARCHITECTURE c03s02b01x00p04n01i00327arch OF c03s02b01x00p04n01i00327ent IS
+-- Failure_here: bad index format; need ranges, not constants.  
+  type er1 is array(5,2) of integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p04n01i00327 - The index constraint in the constrained array definition is invalid." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p04n01i00327arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc328.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc328.vhd
new file mode 100644
index 0000000..7b8bd42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc328.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc328.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p04n01i00328ent IS
+END c03s02b01x00p04n01i00328ent;
+
+ARCHITECTURE c03s02b01x00p04n01i00328arch OF c03s02b01x00p04n01i00328ent IS
+  constant pi:real:=3.1415;
+-- -- Failure_here: index constraint cannot be a real
+  type test is array(0 to pi) of bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p04n01i00328 - The index constraint in the constrained array definition is invalid." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p04n01i00328arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc329.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc329.vhd
new file mode 100644
index 0000000..2e4137c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc329.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc329.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p05n01i00329ent IS
+END c03s02b01x00p05n01i00329ent;
+
+ARCHITECTURE c03s02b01x00p05n01i00329arch OF c03s02b01x00p05n01i00329ent IS
+  type bit_vctor is array ( range <>) of bit;  -- Failure_here
+  type str_vctor is array (natural range <>) of character;
+  type matrix    is array (integer range <>) of real;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p05n01i00329 -  The type mark in the unconstrained array definition is missing."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p05n01i00329arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc330.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc330.vhd
new file mode 100644
index 0000000..f3de1db
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc330.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc330.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p05n01i00330ent IS
+END c03s02b01x00p05n01i00330ent;
+
+ARCHITECTURE c03s02b01x00p05n01i00330arch OF c03s02b01x00p05n01i00330ent IS
+  type bit_vctor is array (natural range <>) of bit;
+  type str_vctor is array (natural <>) of character;  -- Failure_here
+  type matrix    is array (integer range <>) of real;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p05n01i00330 - The reserved word range in the unconstrained array definition is missing." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p05n01i00330arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc331.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc331.vhd
new file mode 100644
index 0000000..e67d8fa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc331.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc331.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p05n01i00331ent IS
+END c03s02b01x00p05n01i00331ent;
+
+ARCHITECTURE c03s02b01x00p05n01i00331arch OF c03s02b01x00p05n01i00331ent IS
+  type bit_vctor is array (natural range <>) of bit;
+  type str_vctor is array (natural range <>) of character;
+  type matrix    is array (integer range ) of real; -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p05n01i00331 - The box (<>) in the unconstrained array definition is missing." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p05n01i00331arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc332.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc332.vhd
new file mode 100644
index 0000000..bc644ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc332.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc332.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p06n01i00332ent IS
+END c03s02b01x00p06n01i00332ent;
+
+ARCHITECTURE c03s02b01x00p06n01i00332arch OF c03s02b01x00p06n01i00332ent IS
+  -- a constrained array declaration
+  type my_word is array (one => 0 to 31) of bit;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p06n01i00332 - Syntax error in discrete range definition for the type declaration of 'my_word'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p06n01i00332arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc336.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc336.vhd
new file mode 100644
index 0000000..5919db5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc336.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc336.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p06n01i00336ent IS
+END c03s02b01x00p06n01i00336ent;
+
+ARCHITECTURE c03s02b01x00p06n01i00336arch OF c03s02b01x00p06n01i00336ent IS
+  type bit_vctor is array 1 to 8 of integer;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p06n01i00336 - The index constraint is a list of discrete ranges enclosed within parentheses." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p06n01i00336arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc338.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc338.vhd
new file mode 100644
index 0000000..fe45b94
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc338.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc338.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p07n01i00338ent IS
+END c03s02b01x00p07n01i00338ent;
+
+ARCHITECTURE c03s02b01x00p07n01i00338arch OF c03s02b01x00p07n01i00338ent IS
+  type bit_vctor is array (1 to 8, positive range <>) of integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p07n01i00338 - The discrete range is neither a valid discrete subtype indication nor a valid range." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p07n01i00338arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc34.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc34.vhd
new file mode 100644
index 0000000..ffbe544
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc34.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc34.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p01n01i00034ent IS
+END c04s03b01x01p01n01i00034ent;
+
+ARCHITECTURE c04s03b01x01p01n01i00034arch OF c04s03b01x01p01n01i00034ent IS
+  constant  INDEX : integer range 0 to 99 := 1000;   --Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c04s03b01x01p01n01i00034- Constant declaration sets value of constant outside subtype indication range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p01n01i00034arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc340.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc340.vhd
new file mode 100644
index 0000000..52b2b70
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc340.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc340.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p08n01i00340ent IS
+  PORT ( ii: INOUT integer);
+  TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
+  TYPE Z IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>,NATURAL RANGE <>) OF INTEGER;
+  SUBTYPE A8 IS A (1 TO 8,1 TO 8,1 TO 8);
+  SUBTYPE Z3 IS Z (1 TO 3,1 TO 3);
+  SUBTYPE Z6 IS Z (1 TO 6,1 TO 6,1 TO 6);
+  FUNCTION func1 (a,b : INTEGER := 3) RETURN Z6 IS
+  BEGIN
+    RETURN (OTHERS=>(OTHERS=>(1,2,3,4,5,6)));
+  END;
+END c03s02b01x00p08n01i00340ent;
+
+ARCHITECTURE c03s02b01x00p08n01i00340arch OF c03s02b01x00p08n01i00340ent IS
+
+BEGIN
+  TESTING: PROCESS
+    VARIABLE q : A8;
+    VARIABLE r : Z3;
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c03s02b01x00p08n01i00340 - Array subtype has fewer dimensions than base type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p08n01i00340arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc342.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc342.vhd
new file mode 100644
index 0000000..604674d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc342.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc342.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p09n03i00342ent IS
+END c03s02b01x00p09n03i00342ent;
+
+ARCHITECTURE c03s02b01x00p09n03i00342arch OF c03s02b01x00p09n03i00342ent IS
+  type array_type is array (1 to 10) of boolean;
+BEGIN
+  TESTING: PROCESS
+    variable k : array_type;
+  BEGIN
+    k(12) := true;
+    assert NOT(k(12)=true)
+      report "***PASSED TEST: c03s02b01x00p09n03i00342"
+      severity NOTE;
+    assert ( k(12)=true )
+      report "***FAILED TEST: c03s02b01x00p09n03i00342 - The values in the given index range are not the values that belong to the corresponding range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p09n03i00342arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc345.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc345.vhd
new file mode 100644
index 0000000..fed2fd1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc345.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc345.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p10n04i00345ent IS
+END c03s02b01x00p10n04i00345ent;
+
+ARCHITECTURE c03s02b01x00p10n04i00345arch OF c03s02b01x00p10n04i00345ent IS
+  constant C1 : BIT_VECTOR(-1 to 2) := "0011" ;   -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p10n04i00345 - Left bound doesn't belong to the corresponding index subtype"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p10n04i00345arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc348.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc348.vhd
new file mode 100644
index 0000000..7031e42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc348.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc348.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x00p15n01i00348ent IS
+END c03s02b01x00p15n01i00348ent;
+
+ARCHITECTURE c03s02b01x00p15n01i00348arch OF c03s02b01x00p15n01i00348ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function WIRED_OR ( Inputs: BIT_VECTOR ) return BIT is
+      constant Floatvalue : BIT := '0' ;
+    begin
+      if Inputs'Length = 0 then
+        -- this is a bus whose drivers are all off.
+        return FloatValue ;
+      else
+        for I in Inputs'Range loop
+          if Inputs(I) = '1' then
+            return '1' ;
+          end if ;
+        end loop ;
+        return '0' ;
+      end if ;
+    end;
+    type bad_array_type is array (WIRED_OR INTEGER range 12 to 22) of BIT; 
+    -- Failure_here         
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x00p15n01i00348 - Resolution function cannot be present." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x00p15n01i00348arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc352.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc352.vhd
new file mode 100644
index 0000000..e7bb9cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc352.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc352.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00352ent IS
+END c03s02b01x01p02n01i00352ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00352arch OF c03s02b01x01p02n01i00352ent IS
+  type bit_vctor is array (0 to 'B') of integer;  --Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p02n01i00352 - Both bounds in the constrained array definition must have the same discrete type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00352arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc353.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc353.vhd
new file mode 100644
index 0000000..5c9159a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc353.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc353.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00353ent IS
+END c03s02b01x01p02n01i00353ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00353arch OF c03s02b01x01p02n01i00353ent IS
+  type bit_vctor is array (0.0 to 7) of real; --Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p02n01i00353 - Both bounds in the constrained array definition must have the same discrete type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00353arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc354.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc354.vhd
new file mode 100644
index 0000000..3de2d5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc354.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc354.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00354ent IS
+END c03s02b01x01p02n01i00354ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00354arch OF c03s02b01x01p02n01i00354ent IS
+  type b1 is array (0 to 'B') of integer;
+  type b2 is array (0.0 to 7) of real;
+  type days is (mon, tue, wed, thu, fri, sat, sun);
+  type weekdays is (mon, tue, wed, thu, fri);
+  type startdays is array (mon to wed) of integer;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p02n01i00354 - Both bounds in the constrained array definition must have the same discrete type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00354arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc356.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc356.vhd
new file mode 100644
index 0000000..64f4653
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc356.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc356.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00356ent IS
+END c03s02b01x01p02n01i00356ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00356arch OF c03s02b01x01p02n01i00356ent IS
+  type days is (mon, tue, wed, thu, fri, sat, sun);
+  type weekdays is (mon, tue, wed, thu, fri);
+  type startdays is array (mon to wed) of integer;  --Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p02n01i00356 - Both bounds in the constrained array definition must have the same discrete type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00356arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc357.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc357.vhd
new file mode 100644
index 0000000..9eb309d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc357.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc357.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00357ent IS
+END c03s02b01x01p02n01i00357ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00357arch OF c03s02b01x01p02n01i00357ent IS
+  type page is array (0 to X"FFF") of bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p02n01i00357 - Both bounds in the constrained array definition must have the same discrete type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00357arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc358.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc358.vhd
new file mode 100644
index 0000000..1af8a9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc358.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc358.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00358ent IS
+END c03s02b01x01p02n01i00358ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00358arch OF c03s02b01x01p02n01i00358ent IS
+  type MVL1 is ('0', '1');
+  type MVL2 is ('X', 'Z');
+  type MVL3 is array(MVL1'LOW to MVL2'HIGH) of Integer; -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p02n01i00358 - Bounds are of different discrete types." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00358arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc360.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc360.vhd
new file mode 100644
index 0000000..8ba71cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc360.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc360.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00360ent IS
+END c03s02b01x01p02n01i00360ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00360arch OF c03s02b01x01p02n01i00360ent IS
+  type bit_vctor is array (positive to 7) of integer; --Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p02n01i00360 - Both bounds in the constrained array definition must have the same discrete type." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00360arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc362.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc362.vhd
new file mode 100644
index 0000000..a83b332
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc362.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc362.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p02n01i00362ent IS
+END c03s02b01x01p02n01i00362ent;
+
+ARCHITECTURE c03s02b01x01p02n01i00362arch OF c03s02b01x01p02n01i00362ent IS
+  type MVL1 is ('0', '1');
+  type MVL2 is ('X', 'Z');
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := 0;
+  BEGIN
+    for I in MVL1'LOW to MVL2'HIGH loop  -- failure_here
+    end loop;
+    wait for 10 ns;
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p02n01i00362 - Bounds are of different discrete types" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p02n01i00362arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc363.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc363.vhd
new file mode 100644
index 0000000..4eba814
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc363.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc363.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n01i00363ent IS
+END c03s02b01x01p03n01i00363ent;
+
+ARCHITECTURE c03s02b01x01p03n01i00363arch OF c03s02b01x01p03n01i00363ent IS
+  type week    is array (positive range <>) of integer;
+  type a    is access week;
+  subtype weekend1 is week (10 to 20);
+  subtype weekend2 is a (10 to 20);
+  type week2    is array (1 to 10) of integer;
+  type b    is access week2;
+  subtype weekend3 is week2 (1 to 2); -- Failure_here
+  subtype weekend4 is b (1 to 2);     -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n01i00363 - Index constraint not allowed in the subtype declaration of weekend3."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n01i00363arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc367.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc367.vhd
new file mode 100644
index 0000000..fc67a3a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc367.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc367.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n01i00367ent IS
+END c03s02b01x01p03n01i00367ent;
+
+ARCHITECTURE c03s02b01x01p03n01i00367arch OF c03s02b01x01p03n01i00367ent IS
+  type MVL is ('0', '1', 'Z') ;
+  type MVL_vector is array (positive range <>) of MVL;
+
+  function tristate (X:MVL_vector) return MVL;
+  subtype tribit is tristate MVL;
+  type tribit_vector is array (positive range <>) of tribit;    
+  subtype byte is tribit_vector (0 to 7);
+  subtype half_byte is byte (0 to 3); -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n01i00367 - If an index constraint appears after a type mark in a subtype indication, then the type or subtype denoted by the type mark must not already impose an index constraint." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n01i00367arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc368.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc368.vhd
new file mode 100644
index 0000000..8fab61c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc368.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc368.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n02i00368ent IS
+END c03s02b01x01p03n02i00368ent;
+
+ARCHITECTURE c03s02b01x01p03n02i00368arch OF c03s02b01x01p03n02i00368ent IS
+  subtype BFALSE is BOOLEAN range FALSE to FALSE;
+  type ONETWO is range 1 to 2;
+
+  type A1 is array (BFALSE range <>,FALSE to FALSE)
+    of INTEGER range 0 to 0;  -- Failure_here
+  -- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
+  -- CANNOT BE MIXED
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n02i00368 - Unconstrained and constrained index ranges cannot be mixed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n02i00368arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc369.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc369.vhd
new file mode 100644
index 0000000..ed285ee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc369.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc369.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n02i00369ent IS
+END c03s02b01x01p03n02i00369ent;
+
+ARCHITECTURE c03s02b01x01p03n02i00369arch OF c03s02b01x01p03n02i00369ent IS
+  subtype BFALSE is BOOLEAN range FALSE to FALSE;
+  type ONETWO is range 1 to 2;
+
+  type A2 is array (FALSE to FALSE,
+                    BFALSE range <>) of ONETWO;  -- Failure_here
+  -- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
+  -- CANNOT BE MIXED
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n02i00369 - Unconstrained and constrained index ranges cannot be mixed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n02i00369arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc370.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc370.vhd
new file mode 100644
index 0000000..03f5956
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc370.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc370.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n02i00370ent IS
+END c03s02b01x01p03n02i00370ent;
+
+ARCHITECTURE c03s02b01x01p03n02i00370arch OF c03s02b01x01p03n02i00370ent IS
+  subtype BFALSE is BOOLEAN range FALSE to FALSE;
+  type ONETWO is range 1 to 2;
+
+  type A3 is array (1 to 2,
+                    ONETWO range <>) of BFALSE;  -- Failure_here
+  -- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
+  -- CANNOT BE MIXED
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n02i00370 - Unconstrained and constrained index ranges cannot be mixed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n02i00370arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc371.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc371.vhd
new file mode 100644
index 0000000..5b0bc14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc371.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc371.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n02i00371ent IS
+END c03s02b01x01p03n02i00371ent;
+
+ARCHITECTURE c03s02b01x01p03n02i00371arch OF c03s02b01x01p03n02i00371ent IS
+  subtype BFALSE is BOOLEAN range FALSE to FALSE;
+  type ONETWO is range 1 to 2;
+
+  type A4 is array (ONETWO range <>,
+                    1 to 2) of REAL range 0.0 downto -5.5;  -- Failure_here
+  -- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
+  -- CANNOT BE MIXED
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n02i00371 - Unconstrained and constrained index ranges cannot be mixed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n02i00371arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc372.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc372.vhd
new file mode 100644
index 0000000..0852bf0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc372.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc372.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n02i00372ent IS
+END c03s02b01x01p03n02i00372ent;
+
+ARCHITECTURE c03s02b01x01p03n02i00372arch OF c03s02b01x01p03n02i00372ent IS
+  subtype BFALSE is BOOLEAN range FALSE to FALSE;
+  type ONETWO is range 1 to 2;
+
+  type A5 is array (FALSE to FALSE,
+                    BFALSE range <>,
+                    1 to 2) of BIT;  -- Failure_here
+  -- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
+  -- CANNOT BE MIXED
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n02i00372 - Unconstrained and constrained index ranges cannot be mixed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n02i00372arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc373.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc373.vhd
new file mode 100644
index 0000000..031fa78
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc373.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc373.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n02i00373ent IS
+END c03s02b01x01p03n02i00373ent;
+
+ARCHITECTURE c03s02b01x01p03n02i00373arch OF c03s02b01x01p03n02i00373ent IS
+  subtype BFALSE is BOOLEAN range FALSE to FALSE;
+  type ONETWO is range 1 to 2;
+
+  type A6 is array (ONETWO range <>,
+                    FALSE to FALSE,
+                    BFALSE range <>) of REAL;  -- Failure_here
+  -- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
+  -- CANNOT BE MIXED
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n02i00373 - Unconstrained and constrained index ranges cannot be mixed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n02i00373arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc374.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc374.vhd
new file mode 100644
index 0000000..660e4e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc374.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc374.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n03i00374ent IS
+END c03s02b01x01p03n03i00374ent;
+
+ARCHITECTURE c03s02b01x01p03n03i00374arch OF c03s02b01x01p03n03i00374ent IS
+  type bit_vctor is array (character range 1 to 8) of integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n03i00374 - The index constraint must provide a discrete range for each index of the array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n03i00374arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc375.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc375.vhd
new file mode 100644
index 0000000..cbe947b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc375.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc375.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n03i00375ent IS
+END c03s02b01x01p03n03i00375ent;
+
+ARCHITECTURE c03s02b01x01p03n03i00375arch OF c03s02b01x01p03n03i00375ent IS
+  type it is array (bit_vector range bit_vector'range) of bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n03i00375 - The index constraint must provide a discrete range for each index of the array type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n03i00375arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc379.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc379.vhd
new file mode 100644
index 0000000..9e9b36f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc379.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc379.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p03n03i00379ent IS
+END c03s02b01x01p03n03i00379ent;
+
+ARCHITECTURE c03s02b01x01p03n03i00379arch OF c03s02b01x01p03n03i00379ent IS
+  type    M1 is array (positive range <>) of real;
+  subtype M2 is natural range 0 to 5;
+  subtype M3 is M1(M2);  -- failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert  FALSE 
+      report "***FAILED TEST: c03s02b01x01p03n03i00379 - Type of discrete range different from the corresponding index." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p03n03i00379arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc380.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc380.vhd
new file mode 100644
index 0000000..8091d53
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc380.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc380.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n01i00380ent IS
+END c03s02b01x01p04n01i00380ent;
+
+ARCHITECTURE c03s02b01x01p04n01i00380arch OF c03s02b01x01p04n01i00380ent IS
+  type bit_vctor is array (positive range -1 to 8) of integer;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p04n01i00380 - The index constraint values are not compatible with the corresponding subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n01i00380arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc383.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc383.vhd
new file mode 100644
index 0000000..fb0df1d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc383.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc383.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n01i00383ent IS
+END c03s02b01x01p04n01i00383ent;
+
+ARCHITECTURE c03s02b01x01p04n01i00383arch OF c03s02b01x01p04n01i00383ent IS
+  type MVL is ('0', '1', 'Z') ;
+  type MVL_vector is array (positive range <>) of MVL;
+
+  function tristate (X:MVL_vector) return MVL;
+  subtype tribit is tristate MVL;
+  type tribit_vector is array (positive range <>) of tribit;
+  subtype byte is tribit_vector (7 downto 0);  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p04n01i00383 - The index constraint values are not compatible with the corresponding subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n01i00383arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc384.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc384.vhd
new file mode 100644
index 0000000..f7ba432
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc384.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc384.vhd,v 1.1.1.1 2001-08-22 18:20:50 paw Exp $
+-- $Revision: 1.1.1.1 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n01i00384ent IS
+END c03s02b01x01p04n01i00384ent;
+
+ARCHITECTURE c03s02b01x01p04n01i00384arch OF c03s02b01x01p04n01i00384ent IS
+        type A1 is array (positive range <>, positive range <>) of bit;
+        subtype byte is A1 (0 to 7, -10 to 7); -- Failure_here
+BEGIN
+   TESTING: PROCESS
+   BEGIN
+   assert FALSE 
+      report "***FAILED TEST: ENTITY c03s02b01x01p04n01i00384ent IS
+END c03s02b01x01p04n01i00384ent;
+
+ARCHITECTURE c03s02b01x01p04n01i00384arch OF c03s02b01x01p04n01i00384ent IS - The index constraint values are not compatible with the corresponding subtype."
+      severity ERROR;
+   wait;
+   END PROCESS TESTING;
+
+END ENTITY c03s02b01x01p04n01i00384ent IS
+END c03s02b01x01p04n01i00384ent;
+
+ARCHITECTURE c03s02b01x01p04n01i00384arch OF c03s02b01x01p04n01i00384ent ISarch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc389.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc389.vhd
new file mode 100644
index 0000000..77a1978
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc389.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc389.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p04n03i00389ent IS
+END c03s02b01x01p04n03i00389ent;
+
+ARCHITECTURE c03s02b01x01p04n03i00389arch OF c03s02b01x01p04n03i00389ent IS
+  type M1 is array (0 to 1, 0 to 2) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable M2 : M1 := (('1','0'),('1','0','1'));
+  BEGIN
+    assert FALSE    
+      report "***FAILED TEST: c03s02b01x01p04n03i00389 - Different index ranges" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p04n03i00389arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc390.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc390.vhd
new file mode 100644
index 0000000..5ea5d06
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc390.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc390.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n01i00390ent IS
+END c03s02b01x01p06n01i00390ent;
+
+ARCHITECTURE c03s02b01x01p06n01i00390arch OF c03s02b01x01p06n01i00390ent IS
+  type I1 is range 1 to 1;
+  type A1 is array (integer range <>) of bit;
+  signal V3: A1;    -- Failure_here
+  -- ERROR - SEMANTIC ERROR: SUBTYPE INDICATION OF ARRAY OBJECT DECLARATION
+  -- MUST DENOTE A CONSTRAINED ARRAY
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p06n01i00390 - Subtype indication of array object declaration must denote a constrained array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n01i00390arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc391.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc391.vhd
new file mode 100644
index 0000000..02f950f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc391.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc391.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n01i00391ent IS
+END c03s02b01x01p06n01i00391ent;
+
+ARCHITECTURE c03s02b01x01p06n01i00391arch OF c03s02b01x01p06n01i00391ent IS
+  type I1 is range 1 to 1;
+  type A1 is array (integer range <>) of bit;
+BEGIN
+  TESTING: PROCESS
+    variable V2: A1 := B"00";  -- Failure_here
+    -- ERROR - SEMANTIC ERROR: SUBTYPE INDICATION OF ARRAY OBJECT DECLARATION
+    -- MUST DENOTE A CONSTRAINED ARRAY
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p06n01i00391 - Subtype indication of array object declaration must denote a constrained array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n01i00391arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc394.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc394.vhd
new file mode 100644
index 0000000..d40991e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc394.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc394.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n02i00394ent IS
+END c03s02b01x01p06n02i00394ent;
+
+ARCHITECTURE c03s02b01x01p06n02i00394arch OF c03s02b01x01p06n02i00394ent IS
+  type I1 is range 1 to 1;
+  type A1 is array (I1 range <>) of BOOLEAN;
+  
+  type R1 is record
+               RE1: A1;  -- failure_here
+               -- ERROR - SEMANTIC ERROR: TYPE OF RECORD ELEMENT CANNOT BE AN
+               -- UNCONSTRAINED ARRAY
+             end record;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p06n02i00394 - Record element cannot be an unconstrained array."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n02i00394arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc396.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc396.vhd
new file mode 100644
index 0000000..0074222
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc396.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc396.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p06n02i00396ent IS
+END c03s02b01x01p06n02i00396ent;
+
+ARCHITECTURE c03s02b01x01p06n02i00396arch OF c03s02b01x01p06n02i00396ent IS
+  type I1 is range 1 to 1;
+  type A1 is array (I1 range <>) of BOOLEAN;
+  type A2 is array (I1'(1) to I1'(1)) of A1;  -- Failure_here
+  -- ERROR - SEMANTIC ERROR: ARRAY ELEMENT CANNOT BE AN UNCONSTRAINED ARRAY
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p06n02i00396 - Array element cannot be an unconstrained array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p06n02i00396arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc4.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc4.vhd
new file mode 100644
index 0000000..a6c17a9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc4.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc4.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s01b00x00p04n01i00004ent IS
+END c04s01b00x00p04n01i00004ent;
+
+ARCHITECTURE c04s01b00x00p04n01i00004arch OF c04s01b00x00p04n01i00004ent IS
+  -- a constrained array declaration
+  type my_word is array (one => 0 to 31) of bit;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s01b00x00p04n01i00004 - Syntax error in type declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s01b00x00p04n01i00004arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc405.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc405.vhd
new file mode 100644
index 0000000..55ce9ca
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc405.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc405.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b01x01p19n01i00405ent IS
+END c03s02b01x01p19n01i00405ent;
+
+ARCHITECTURE c03s02b01x01p19n01i00405arch OF c03s02b01x01p19n01i00405ent IS
+  type MEM is array (positive range <>) of BIT;
+  type ME1 is array (positive range <>) of Integer;
+  subtype ME2 is ME1(1 to 3);
+  subtype M1 is MEM (1 to 5);
+  function WR_OR(Input : ME1) return M1 is
+  begin
+    for I in Input'Range loop
+      if Input(I) = 2 then
+        return "11111" ;
+      end if;
+    end loop;
+  end WR_OR;
+  procedure F2 (X1 : in MEM; WR_OR: out M1) is
+  begin
+  end F2;
+BEGIN
+  TESTING: PROCESS
+    variable V1 :ME2 := (20, 30, 40, 50);
+  BEGIN
+    F2(WR_OR(V1),WR_OR(V1)) ;  -- failure_here
+    wait for 10 ns;
+    assert FALSE 
+      report "***FAILED TEST: c03s02b01x01p19n01i00405 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b01x01p19n01i00405arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc42.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc42.vhd
new file mode 100644
index 0000000..70ff8a3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc42.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc42.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00042ent IS
+END c04s03b01x01p02n01i00042ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00042arch OF c04s03b01x01p02n01i00042ent IS
+  -- this is an error because "integer" and "i" should be switched.
+  constant integer: i := 7;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST:c04s03b01x01p02n01i00042- Identifier list expected in constant declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00042arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc44.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc44.vhd
new file mode 100644
index 0000000..0a3bc8d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc44.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc44.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p02n01i00044ent IS
+END c04s03b01x01p02n01i00044ent;
+
+ARCHITECTURE c04s03b01x01p02n01i00044arch OF c04s03b01x01p02n01i00044ent IS
+  constant c: integer   (2+3);  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c04s03b01x01p02n01i00044 - Syntactic error in constant declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p02n01i00044arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc46.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc46.vhd
new file mode 100644
index 0000000..57d4259
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc46.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc46.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p03n02i00046ent IS
+END c04s03b01x01p03n02i00046ent;
+
+ARCHITECTURE c04s03b01x01p03n02i00046arch OF c04s03b01x01p03n02i00046ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant CC1 : integer := 4;
+    variable AA1 : integer := 87;
+    variable BB1 : integer := 20 ;
+  BEGIN
+    CC1 :=  AA1 * BB1;   -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x01p03n02i00046- The value of a constant cannot be changed after the declartion elaboration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x01p03n02i00046arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc47.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc47.vhd
new file mode 100644
index 0000000..10b05e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc47.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc47.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p03n02i00047ent IS
+END c04s03b01x01p03n02i00047ent;
+
+ARCHITECTURE c04s03b01x01p03n02i00047arch OF c04s03b01x01p03n02i00047ent IS
+  function retrieve (VM:integer) return integer is
+    constant pi : real := 3.142;
+  begin
+    pi := 45.00;    -- Failure_here - pi is a constant
+    return 12;
+  end retrieve;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x01p03n02i00047- The value of a constant cannot be changed after the declartion elaboration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x01p03n02i00047arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc48.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc48.vhd
new file mode 100644
index 0000000..3c62362
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc48.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc48.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p03n02i00048ent IS
+END c04s03b01x01p03n02i00048ent;
+
+ARCHITECTURE c04s03b01x01p03n02i00048arch OF c04s03b01x01p03n02i00048ent IS
+  constant test: integer := 10; -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x01p03n02i00048 - The value of a constant cannot be changed after the declartion elaboration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p03n02i00048arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc49.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc49.vhd
new file mode 100644
index 0000000..7cc87f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc49.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc49.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p04n01i00049ent IS
+END c04s03b01x01p04n01i00049ent;
+
+ARCHITECTURE c04s03b01x01p04n01i00049arch OF c04s03b01x01p04n01i00049ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant x: bit; --Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x01p04n01i00049- Deferred constant declaration can not appear in a process statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p04n01i00049arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc5.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc5.vhd
new file mode 100644
index 0000000..30d7ff6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc5.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc5.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s01b00x00p08n01i00005ent IS
+END c04s01b00x00p08n01i00005ent;
+
+ARCHITECTURE c04s01b00x00p08n01i00005arch OFc04s01b00x00p08n01i00005ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type I1 is range 1 to 1;
+    type I2 is range 1 to 1;
+    variable V1: I1;
+    variable V2: I2;
+  BEGIN
+
+    if V1 = V2 then  -- Failure_here
+      -- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
+      null ;
+    end if;
+    
+    assert FALSE 
+      report "***FAILED TEST: c04s01b00x00p08n01i00005 - Types are different and hence incompatible."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s01b00x00p08n01i00005arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc50.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc50.vhd
new file mode 100644
index 0000000..a867f12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc50.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc50.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p04n01i00050ent IS
+END c04s03b01x01p04n01i00050ent;
+
+ARCHITECTURE c04s03b01x01p04n01i00050arch OF c04s03b01x01p04n01i00050ent IS
+  constant A1 : bit;   -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x01p04n01i00050 - Deferred constant declaration can not appear in an architecture body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x01p04n01i00050arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc502.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc502.vhd
new file mode 100644
index 0000000..0126ec5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc502.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc502.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p02n01i00502ent IS
+END c03s02b02x00p02n01i00502ent;
+
+ARCHITECTURE c03s02b02x00p02n01i00502arch OF c03s02b02x00p02n01i00502ent IS
+  type R1 is record
+             end record;  -- Failure_here
+  -- ERROR - SYNTAX ERROR: RECORD TYPE DECLARATION MUST
+  -- CONTAIN AT LEAST ONE ELEMENT
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b02x00p02n01i00502 - At least one element should be present in the record type definition." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p02n01i00502arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc504.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc504.vhd
new file mode 100644
index 0000000..19fb6dd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc504.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc504.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p03n01i00504ent IS
+END c03s02b02x00p03n01i00504ent;
+
+ARCHITECTURE c03s02b02x00p03n01i00504arch OF c03s02b02x00p03n01i00504ent IS
+  type DATE is
+    record
+      DAY  : Integer range 1 to 31;
+      MONTH : Integer range 1 to 12;
+      YEAR : Integer range 0 to 1000;
+    end record               --- Failure_here ; Missing semicolon
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b02x00p03n01i00504 -Missing semicolon" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p03n01i00504arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc506.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc506.vhd
new file mode 100644
index 0000000..c7140e8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc506.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc506.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p06n02i00506ent IS
+END c03s02b02x00p06n02i00506ent;
+
+ARCHITECTURE c03s02b02x00p06n02i00506arch OF c03s02b02x00p06n02i00506ent IS
+  type rec_type is
+    record
+      x : bit;
+      y : integer;
+      x : boolean;   -- Failure_here
+    end record;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b02x00p06n02i00506 -dentifiers of all elements of a record type must be distinct. "
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p06n02i00506arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc507.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc507.vhd
new file mode 100644
index 0000000..5c56c92
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc507.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc507.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p06n02i00507ent IS
+END c03s02b02x00p06n02i00507ent;
+
+ARCHITECTURE c03s02b02x00p06n02i00507arch OF c03s02b02x00p06n02i00507ent IS
+  type R1 is record
+               RE1: INTEGER;
+               RE2: BIT;
+               RE3: BOOLEAN;
+               RE1: REAL;  -- Failure_here
+               -- ERROR - SEMANTIC ERROR: IDENTIFIERS OF ELEMENTS OF
+               -- A RECORD TYPE MUST BE DISTINCT
+             end record;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b02x00p06n02i00507 - Identifiers of elements of record type must be distinct."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p06n02i00507arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc508.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc508.vhd
new file mode 100644
index 0000000..87f7bd4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc508.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc508.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p06n02i00508ent IS
+END c03s02b02x00p06n02i00508ent;
+
+ARCHITECTURE c03s02b02x00p06n02i00508arch OF c03s02b02x00p06n02i00508ent IS
+  type date is
+    record
+      day       : integer range 1 to 31;
+      month      : integer range 1 to 12;
+      -- -- Failure_here: duplicate record field declaration
+      day      : integer range -6000 to 6000;
+    end record;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b02x00p06n02i00508 -The identifiers of all elements of a record type must be distinct." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p06n02i00508arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc509.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc509.vhd
new file mode 100644
index 0000000..e99a49e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc509.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc509.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p06n03i00509ent IS
+END c03s02b02x00p06n03i00509ent;
+
+ARCHITECTURE c03s02b02x00p06n03i00509arch OF c03s02b02x00p06n03i00509ent IS
+  type date is
+    record
+      day    :integer range 1 to 31;
+
+--  Failure_here: cannot use element name of record as part of definition of
+--  another field of same record.
+      
+      month   : day range 1 to 12;
+      year   : integer range -6000 to 6000;
+    end record;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b02x00p06n03i00509 - The use of a name that denotes a record element is not allowed within the record type definition that declares the element." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p06n03i00509arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc51.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc51.vhd
new file mode 100644
index 0000000..f8c3f16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc51.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc51.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b01x01p04n03i00051pkg is
+  constant PI : Real;
+  constant g : real;
+end c04s03b01x01p04n03i00051pkg;
+
+package body c04s03b01x01p04n03i00051pkg is
+  constant g : Real := 9.8;           -- full declaration for 'g'
+  -- The full declaration for PI is missing.
+end c04s03b01x01p04n03i00051pkg;  -- Failure_here
+
+
+ENTITY c04s03b01x01p04n03i00051ent IS
+END c04s03b01x01p04n03i00051ent;
+
+ARCHITECTURE c04s03b01x01p04n03i00051arch OF c04s03b01x01p04n03i00051ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x01p04n03i00051 - Declaration for deferred constant is missing in the package body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x01p04n03i00051arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc510.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc510.vhd
new file mode 100644
index 0000000..830b761
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc510.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc510.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p06n03i00510ent IS
+END c03s02b02x00p06n03i00510ent;
+
+ARCHITECTURE c03s02b02x00p06n03i00510arch OF c03s02b02x00p06n03i00510ent IS
+  type x is (one,two);
+  
+  type rec_type is
+    record
+      x : bit;
+      y : integer;
+      z : x;  -- Failure_here
+      -- ERROR: The use of a name that denotes a record element
+      -- is not allowed within the record type definition that declares the element.
+    end record;
+BEGIN
+  TESTING: PROCESS
+    variable k : rec_type;
+  BEGIN
+    k.x = '0';
+    k.y = 123;
+    k.z = one;
+    assert FALSE 
+      report "***FAILED TEST: c03s02b02x00p06n03i00510 - The use of a name that denotes a record element is not allowed within the record type definition that declares the element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p06n03i00510arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc511.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc511.vhd
new file mode 100644
index 0000000..637dc5c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc511.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc511.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s02b02x00p06n03i00511ent IS
+END c03s02b02x00p06n03i00511ent;
+
+ARCHITECTURE c03s02b02x00p06n03i00511arch OF c03s02b02x00p06n03i00511ent IS
+  type R1 is record
+               RE1: I1;
+               RE2: RE1;  -- Failure_here
+               -- ERROR - SEMANTIC ERROR: NAME OF RECORD ELEMENT CANNOT BE USED
+               -- WITHIN THE RECORD TYPE DEFINITION
+             end record;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s02b02x00p06n03i00511 - Name of record element cannot be used in the record type definition." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s02b02x00p06n03i00511arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc514.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc514.vhd
new file mode 100644
index 0000000..8ee2f9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc514.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc514.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p02n01i00514ent IS
+END c03s03b00x00p02n01i00514ent;
+
+ARCHITECTURE c03s03b00x00p02n01i00514arch OF c03s03b00x00p02n01i00514ent IS
+  type MY_WORD is array (0 to 31) of BIT;
+  type MEMORY  is array (Integer range <>) of MY_WORD;
+  type ADDRESS is access ; --- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s03b00x00p02n01i00514 - Missing subtype indication" 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p02n01i00514arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc518.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc518.vhd
new file mode 100644
index 0000000..a29520f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc518.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc518.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p03n06i00518ent IS
+END c03s03b00x00p03n06i00518ent;
+
+ARCHITECTURE c03s03b00x00p03n06i00518arch OF c03s03b00x00p03n06i00518ent IS
+  type FT is file of integer;
+  type b is access FT;  -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s03b00x00p03n06i00518 - The designated type must not be a file type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p03n06i00518arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc532.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc532.vhd
new file mode 100644
index 0000000..f39ef61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc532.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc532.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p04n01i00532ent IS
+END c03s03b00x00p04n01i00532ent;
+
+ARCHITECTURE c03s03b00x00p04n01i00532arch OF c03s03b00x00p04n01i00532ent IS
+  type T is
+    record
+      a:integer;
+      b:integer;
+    end record;
+  type A is access T;
+  signal B1, B2: A := new T'(0, 0); -- Failure_here
+  signal C     : T;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    C   <= B1.all;
+    assert NOT(C.a=0 and C.b=0)
+      report "***PASSED TEST: c03s03b00x00p04n01i00532"
+      severity NOTE;
+    assert (C.a=0 and C.b=0)
+      report "***FAILED TEST: c03s03b00x00p04n01i00532 - The object declared to be of an access type must be an object of class variable."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p04n01i00532arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc533.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc533.vhd
new file mode 100644
index 0000000..cdbd6e6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc533.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc533.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p04n01i00533ent IS
+END c03s03b00x00p04n01i00533ent;
+
+ARCHITECTURE c03s03b00x00p04n01i00533arch OF c03s03b00x00p04n01i00533ent IS
+  type T is
+    record
+      a:integer;
+      b:integer;
+    end record;
+  type A is access T;
+  constant B1, B2: A := new T'(0, 0);
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s03b00x00p04n01i00533 - The object declared to be of an access type must be an object of class variable."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p04n01i00533arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc540.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc540.vhd
new file mode 100644
index 0000000..96f19ef
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc540.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc540.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b01x00p02n01i00540ent IS
+END c03s03b01x00p02n01i00540ent;
+
+ARCHITECTURE c03s03b01x00p02n01i00540arch OF c03s03b01x00p02n01i00540ent IS
+  type ARR        -- Failure_here
+    type L1    is access ARR;
+  type ARR    is array (positive range <>) of BIT;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE
+      report "***FAILED TEST: c03s03b01x00p02n01i00540 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b01x00p02n01i00540arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc543.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc543.vhd
new file mode 100644
index 0000000..81cb995
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc543.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc543.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p02n01i00543ent IS
+END c03s04b00x00p02n01i00543ent;
+
+ARCHITECTURE c03s04b00x00p02n01i00543arch OF c03s04b00x00p02n01i00543ent IS
+  type ARR is
+    record
+      V1 : Integer;
+      V2 : Integer;
+    end record;
+
+  type A1 is file ARR;     -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s04b00x00p02n01i00543 - Missing reserved word 'OF'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p02n01i00543arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc547.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc547.vhd
new file mode 100644
index 0000000..f24b980
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc547.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc547.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n03i00547ent IS
+END c03s04b00x00p03n03i00547ent;
+
+ARCHITECTURE c03s04b00x00p03n03i00547arch OF c03s04b00x00p03n03i00547ent IS
+  type TM is
+    file of integer;
+
+  type FT is                          -- file decl
+    file of TM;             -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s04b00x00p03n03i00547 - Subtype denoted by a filetype cannot have a base type of a file or access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n03i00547arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc548.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc548.vhd
new file mode 100644
index 0000000..6fd9393
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc548.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc548.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n03i00548ent IS
+END c03s04b00x00p03n03i00548ent;
+
+ARCHITECTURE c03s04b00x00p03n03i00548arch OF c03s04b00x00p03n03i00548ent IS
+  type v is record
+              a : integer;
+              b : bit;
+            end record;
+  type TM is
+    access v;
+  type FT is                              -- file decl
+    file of TM;            -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s04b00x00p03n03i00548 - Subtype denoted by a filetype cannot have a base type of a file or access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n03i00548arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc549.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc549.vhd
new file mode 100644
index 0000000..6fcaf26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc549.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc549.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n03i00549ent IS
+END c03s04b00x00p03n03i00549ent;
+
+ARCHITECTURE c03s04b00x00p03n03i00549arch OF c03s04b00x00p03n03i00549ent IS
+  type FT1 is file of Bit_Vector;
+  type FT3 is file of FT1;            -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s04b00x00p03n03i00549 - Subtype denoted by a filetype cannot have a base type of a file or access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n03i00549arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc55.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc55.vhd
new file mode 100644
index 0000000..756c279
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc55.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc55.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p05n02i00055ent IS
+END c04s03b01x01p05n02i00055ent;
+
+ARCHITECTURE c04s03b01x01p05n02i00055arch OF c04s03b01x01p05n02i00055ent IS
+
+BEGIN
+  G1 : for I in 1 to 3 generate
+    I <= I + 1 ;                     -- Failure_here
+  end generate;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x01p05n02i00055 - Generate index can not be modified."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p05n02i00055arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc550.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc550.vhd
new file mode 100644
index 0000000..d9ea39e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc550.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc550.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n03i00550ent IS
+END c03s04b00x00p03n03i00550ent;
+
+ARCHITECTURE c03s04b00x00p03n03i00550arch OF c03s04b00x00p03n03i00550ent IS
+  type A is access integer;
+  type FT4 is file of A;              -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s04b00x00p03n03i00550d - Subtype denoted by a filetype cannot have a base type of a file or access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n03i00550arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc551.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc551.vhd
new file mode 100644
index 0000000..02ec292
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc551.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc551.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n03i00551ent IS
+END c03s04b00x00p03n03i00551ent;
+
+ARCHITECTURE c03s04b00x00p03n03i00551arch OF c03s04b00x00p03n03i00551ent IS
+  type A is access integer;
+  type R is
+    record
+      E: A;
+    end record;
+  type FT5 is file of R;              -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s04b00x00p03n03i00551 - Subtype denoted by a filetype cannot have a base type of a file or access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n03i00551arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc552.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc552.vhd
new file mode 100644
index 0000000..4856ffc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc552.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc552.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n04i00552ent IS
+END c03s04b00x00p03n04i00552ent;
+
+ARCHITECTURE c03s04b00x00p03n04i00552arch OF c03s04b00x00p03n04i00552ent IS
+  type ARR ;
+  type LINK is access ARR;
+
+  type ARR is
+    record
+      V1 : Integer;
+      V2 : Integer;
+      V3 : LINK ;
+    end record;
+
+  type A1 is file of ARR;     -- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s04b00x00p03n04i00552 - Subelement of an access type not allowed here."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n04i00552arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc553.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc553.vhd
new file mode 100644
index 0000000..03ebad9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc553.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc553.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s04b00x00p03n05i00553ent IS
+END c03s04b00x00p03n05i00553ent;
+
+ARCHITECTURE c03s04b00x00p03n05i00553arch OF c03s04b00x00p03n05i00553ent IS
+  type TM is    -- unconstrained array decl
+    array (Integer range <>, Integer range <>) of Integer;
+
+  type FT is    -- file decl
+    file of TM;      --  Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c03s04b00x00p03n05i00553 - A file may not be declared to contain multi dimensional arrays."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s04b00x00p03n05i00553arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc57.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc57.vhd
new file mode 100644
index 0000000..1324f2d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc57.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc57.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p05n02i00057ent IS
+END c04s03b01x01p05n02i00057ent;
+
+ARCHITECTURE c04s03b01x01p05n02i00057arch OF c04s03b01x01p05n02i00057ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable i : integer;       -- loop index
+    variable x : integer;
+  BEGIN
+    i := 10;
+    for i in 1 to 5 loop
+      x := X + 1;
+      i := 5;             -- Failure_here - the loop index is being modified.
+    end loop;
+    assert FALSE 
+      report "***FAILED TEST:c04s03b01x01p05n02i00057 - A loop index may not be altered within the loop."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p05n02i00057arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc58.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc58.vhd
new file mode 100644
index 0000000..03dece5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc58.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc58.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p05n01i00058ent IS
+END c04s03b01x01p05n01i00058ent;
+
+ARCHITECTURE c04s03b01x01p05n01i00058arch OF c04s03b01x01p05n01i00058ent IS
+
+BEGIN
+  TESTING : PROCESS
+  BEGIN
+    T1 := 20 ns;    --- failure_here
+    assert FALSE
+      report "***FAILED TEST: c04s03b01x01p05n01i00058 - Generics cannot be updated."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x01p05n01i00058arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc6.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc6.vhd
new file mode 100644
index 0000000..188571d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc6.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc6.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s01b00x00p08n01i00006ent IS
+END c04s01b00x00p08n01i00006ent;
+
+ARCHITECTURE c04s01b00x00p08n01i00006arch OF c04s01b00x00p08n01i00006ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type REAL1 is range 1.0 to 1.0;
+    type REAL2 is range 1.0 to 1.0;
+    
+    variable V3: REAL1;
+    variable V4: REAL2;
+  BEGIN
+    if V3 = V4 then  -- Failure_here
+      -- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
+      null ;
+    end if;
+    
+    assert FALSE 
+      report "***FAILED TEST:c04s01b00x00p08n01i00006 - Types are different and hence incompatible."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s01b00x00p08n01i00006arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc60.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc60.vhd
new file mode 100644
index 0000000..dcb7304
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc60.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc60.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p05n02i00060ent IS
+END c04s03b01x01p05n02i00060ent;
+
+ARCHITECTURE c04s03b01x01p05n02i00060arch OF c04s03b01x01p05n02i00060ent IS
+  constant C1 : BIT_VECTOR(0 to 7) := "00101011";
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    C1(0 to 3) <= "0011" ;  -- Failure_here
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x01p05n02i00060- Slice of a constant cannot be modified."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p05n02i00060arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc61.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc61.vhd
new file mode 100644
index 0000000..680a122
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc61.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc61.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p06n01i00061ent IS
+END c04s03b01x01p06n01i00061ent;
+
+ARCHITECTURE c04s03b01x01p06n01i00061arch OF c04s03b01x01p06n01i00061ent IS
+  type    integer_file    is file of integer;
+  constant x : integer_file;  -- Failure_here
+  -- error as the constant is file type
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x01p06n01i00061 - A constant declaration may not have an access type or a file type as the subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p06n01i00061arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc62.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc62.vhd
new file mode 100644
index 0000000..a94be3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc62.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc62.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x01p06n01i00062ent IS
+END c04s03b01x01p06n01i00062ent;
+
+ARCHITECTURE c04s03b01x01p06n01i00062arch OF c04s03b01x01p06n01i00062ent IS
+  type       a1 is access integer;
+  constant    x : a1;     -- Failure_here
+  -- error as the constant is access type
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x01p06n01i00062 - A constant declaration may not have an access type or a file type as the subtype indication."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x01p06n01i00062arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc65.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc65.vhd
new file mode 100644
index 0000000..986dac6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc65.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc65.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p02n01i00065ent IS
+END c04s03b01x02p02n01i00065ent;
+
+ARCHITECTURE c04s03b01x02p02n01i00065arch OF c04s03b01x02p02n01i00065ent IS
+  signal S1 Integer:= 10 ;    --- Failure_here
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    assert FALSE
+      report "***FAILED TEST: c04s03b01x02p02n01i00065 - Missing colon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x02p02n01i00065arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc67.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc67.vhd
new file mode 100644
index 0000000..dfde889
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc67.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc67.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p07n01i00067ent IS
+END c04s03b01x02p07n01i00067ent;
+
+ARCHITECTURE c04s03b01x02p07n01i00067arch OF c04s03b01x02p07n01i00067ent IS
+  type xyz is (foo, glitch, foobar);
+  signal dude : xyz := 'a';                      -- Failure_here
+  signal INDEX : INTEGER range 0 to 99 := 1000;  -- Failure_here
+  -- 1000 is not within the given range.
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x02p07n01i00067- Signal expression must be as the same type as the signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p07n01i00067arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc7.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc7.vhd
new file mode 100644
index 0000000..6a695fc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc7.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc7.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s01b00x00p08n01i00007ent IS
+END c04s01b00x00p08n01i00007ent;
+
+ARCHITECTURE c04s01b00x00p08n01i00007arch OF c04s01b00x00p08n01i00007ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type ENUM1 is ('1');
+    type ENUM2 is ('1');
+    
+    variable V5: ENUM1;
+    variable V6: ENUM2;
+  BEGIN
+    if V5 = V6 then  -- Failure_here
+      -- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
+      null ;
+    end if;
+    
+    assert FALSE 
+      report "***FAILED TEST: c04s01b00x00p08n01i00007 - Types are different and hence incompatible."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s01b00x00p08n01i00007arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc71.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc71.vhd
new file mode 100644
index 0000000..5884217
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc71.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc71.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p09n01i00071ent IS
+END c04s03b01x02p09n01i00071ent;
+
+ARCHITECTURE c04s03b01x02p09n01i00071arch OF c04s03b01x02p09n01i00071ent IS
+  type    y  is file of integer;
+  signal    s2 : y;  -- Failure_here
+  -- error as the signal is a file type.
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST:c04s03b01x02p09n01i00071 - Signal can not be declared to be a file type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x02p09n01i00071arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc714.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc714.vhd
new file mode 100644
index 0000000..4575a82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc714.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc714.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b00x00p02n01i00714ent IS
+BEGIN
+  ;
+
+  ARCHITECTURE c01s01b00x00p02n01i00714arch OF c01s01b00x00p02n01i00714ent IS
+
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE
+        report "***FAILED TEST: c01s01b00x00p02n01i00714 - Missing end in entity declaration."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c01s01b00x00p02n01i00714arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc715.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc715.vhd
new file mode 100644
index 0000000..5f40e28
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc715.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc715.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b00x00p02n01i00715ent IS
+END c01s01b00x00p02n01i00715ent;
+
+ARCHITECTURE c01s01b00x00p02n01i00715arch OF c01s01b00x00p02n01i00715ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b00x00p02n01i00715 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b00x00p02n01i00715arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc716.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc716.vhd
new file mode 100644
index 0000000..86b6f9f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc716.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc716.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b00x00p02n01i00716ent IS
+END c01s01b00x00p02n01i00716ent;
+
+ARCHITECTURE c01s01b00x00p02n01i00716arch OF c01s01b00x00p02n01i00716ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b00x00p02n01i00716 - Missing is in entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b00x00p02n01i00716arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc718.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc718.vhd
new file mode 100644
index 0000000..acf97a8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc718.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc718.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY    IS 
+END c01s01b00x00p02n01i00718ent;
+-- missing identifier 
+
+ARCHITECTURE c01s01b00x00p02n01i00718arch OF c01s01b00x00p02n01i00718ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b00x00p02n01i00718 - Missing identifier." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b00x00p02n01i00718arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc72.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc72.vhd
new file mode 100644
index 0000000..be56c13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc72.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc72.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p09n01i00072ent IS
+END c04s03b01x02p09n01i00072ent;
+
+ARCHITECTURE c04s03b01x02p09n01i00072arch OF c04s03b01x02p09n01i00072ent IS
+  type    x is access integer;
+  signal    s1 : x;  -- Failure_here
+  -- error as the signal is an access type.
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x02p09n01i00072 - Signal can not be declared to be an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b01x02p09n01i00072arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc720.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc720.vhd
new file mode 100644
index 0000000..abaeec7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc720.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc720.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b00x00p04n01i00720ent IS
+END c01s01b00x00p04n01i00720ent;
+
+ARCHITECTURE c01s01b00x00p04n01i00720arch OF c01s01b00x00p04n01i00720ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b00x00p04n01i00720 - Entity_simple_name differs from identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b00x00p04n01i00720arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc721.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc721.vhd
new file mode 100644
index 0000000..4a4caf7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc721.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc721.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p02n01i00721ent IS
+  port    (B:BIT);
+  generic (N:natural:= 2);  -- Failure_here
+  -- Generic clause must precede the port clause
+END c01s01b01x00p02n01i00721ent;
+
+ARCHITECTURE c01s01b01x00p02n01i00721arch OF c01s01b01x00p02n01i00721ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b01x00p02n01i00721 - Generic declarations should come before port declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p02n01i00721arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc722.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc722.vhd
new file mode 100644
index 0000000..3592d8c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc722.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc722.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p03n01i00722ent IS
+  generic (( constant i : integer );                           -- extra parenthesis
+           END c01s01b01x00p03n01i00722ent;
+
+           ARCHITECTURE c01s01b01x00p03n01i00722arch OF c01s01b01x00p03n01i00722ent IS
+
+           BEGIN
+             TESTING: PROCESS
+             BEGIN
+               assert FALSE
+                 report "***FAILED TEST: c01s01b01x00p03n01i00722 - Unbalanced parenthesis in generic clause."
+                 severity ERROR;
+               wait;
+             END PROCESS TESTING;
+
+           END c01s01b01x00p03n01i00722arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc723.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc723.vhd
new file mode 100644
index 0000000..469001d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc723.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc723.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p03n01i00723ent IS
+  generic ( constant i : integer
+            ));                           -- extra parenthesis
+END c01s01b01x00p03n01i00723ent;
+
+ARCHITECTURE c01s01b01x00p03n01i00723arch OF c01s01b01x00p03n01i00723ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x00p03n01i00723 - Unbalanced parenthesis in generic clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p03n01i00723arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc724.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc724.vhd
new file mode 100644
index 0000000..c9cc3d3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc724.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc724.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p03n01i00724ent IS
+
+  generic (( constant i : integer       -- extra parenthesis
+             ));                           -- extra parenthesis
+
+END c01s01b01x00p03n01i00724ent;
+
+ARCHITECTURE c01s01b01x00p03n01i00724arch OF c01s01b01x00p03n01i00724ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x00p03n01i00724 - Extra parenthesis in generic clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p03n01i00724arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc725.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc725.vhd
new file mode 100644
index 0000000..2690dee
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc725.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc725.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p03n01i00725ent IS
+  generic ( constant i : integer
+            );
+  generic ( constant j : integer
+            );
+END c01s01b01x00p03n01i00725ent;
+
+ARCHITECTURE c01s01b01x00p03n01i00725arch OF c01s01b01x00p03n01i00725ent IS
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x00p03n01i00725 - Extra generic clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p03n01i00725arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc726.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc726.vhd
new file mode 100644
index 0000000..fe72945
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc726.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc726.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p03n01i00726ent IS
+  generic (T1 : Time;I1 : Integer)    --- Failure_here
+END c01s01b01x00p03n01i00726ent;
+
+ARCHITECTURE c01s01b01x00p03n01i00726arch OF c01s01b01x00p03n01i00726ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x00p03n01i00726 - Missing semicolon." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p03n01i00726arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc727.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc727.vhd
new file mode 100644
index 0000000..4003e38
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc727.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc727.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p04n01i00727ent IS
+  port (( signal s : bit                -- extra parenthesis
+          );
+        END c01s01b01x00p04n01i00727ent;
+
+        ARCHITECTURE c01s01b01x00p04n01i00727arch OF c01s01b01x00p04n01i00727ent IS
+
+        BEGIN
+          TESTING: PROCESS
+          BEGIN
+            assert FALSE
+              report "***FAILED TEST: c01s01b01x00p04n01i00727 - Unbalanced parenthesis in port clause."
+              severity ERROR;
+            wait;
+          END PROCESS TESTING;
+
+        END c01s01b01x00p04n01i00727arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc728.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc728.vhd
new file mode 100644
index 0000000..548e133
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc728.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc728.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p04n01i00728ent IS
+  port ( signal s : bit
+         ));                           -- extra parenthesis
+END c01s01b01x00p04n01i00728ent;
+
+ARCHITECTURE c01s01b01x00p04n01i00728arch OF c01s01b01x00p04n01i00728ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x00p04n01i00728 - Unbalanced parenthesis in port clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p04n01i00728arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc729.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc729.vhd
new file mode 100644
index 0000000..55f7704
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc729.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc729.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p04n01i00729ent IS
+  port (( signal s : bit                -- extra parenthesis
+          ));                           -- extra parenthesis
+END c01s01b01x00p04n01i00729ent;
+
+ARCHITECTURE c01s01b01x00p04n01i00729arch OF c01s01b01x00p04n01i00729ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x00p04n01i00729 - Extra parenthesis in port clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p04n01i00729arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc73.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc73.vhd
new file mode 100644
index 0000000..2522e67
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc73.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc73.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p09n02i00073ent IS
+END c04s03b01x02p09n02i00073ent;
+
+ARCHITECTURE c04s03b01x02p09n02i00073arch OF c04s03b01x02p09n02i00073ent IS
+  signal s1 : bit register; -- Failure_here
+  -- a guarded signal, but is not a resolved signal.
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x02p09n02i00073- Guarded signal should be a resolved signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x02p09n02i00073arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc730.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc730.vhd
new file mode 100644
index 0000000..d6b0e89
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc730.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc730.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p04n01i00730ent IS
+  port ( signal s : bit
+         );
+  port ( signal t : bit                 -- illegal second port clause
+         );
+END c01s01b01x00p04n01i00730ent;
+
+ARCHITECTURE c01s01b01x00p04n01i00730arch OF c01s01b01x00p04n01i00730ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x00p04n01i00730 - Extra port clause."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p04n01i00730arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc732.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc732.vhd
new file mode 100644
index 0000000..3391301
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc732.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc732.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x00p04n01i00732ent IS
+  -- A basic entity with a port
+  port ( signal s : bit)      --Failure_here
+END c01s01b01x00p04n01i00732ent;
+
+ARCHITECTURE c01s01b01x00p04n01i00732arch OF c01s01b01x00p04n01i00732ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x00p04n01i00732 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p04n01i00732arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc733.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc733.vhd
new file mode 100644
index 0000000..d7d8918
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc733.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc733.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s01b01x00p05n01i00733ent_a is
+  generic (
+    constant gc1 : integer;
+    gc2 : natural;
+    constant gc3 : positive
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x00p05n01i00733ent_a;
+
+architecture arch of c01s01b01x00p05n01i00733ent_a is
+begin
+  assert false 
+    report "FAIL: should not compile";
+end arch;
+
+ENTITY c01s01b01x00p05n01i00733ent IS
+  generic ( constant gen_con : natural := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x00p05n01i00733ent;
+
+ARCHITECTURE c01s01b01x00p05n01i00733arch OF c01s01b01x00p05n01i00733ent IS
+
+  signal s1 : integer;
+  signal s2 : natural;
+  signal s3 : positive;
+
+  component comp1
+    generic (
+      constant dgc1 : integer;
+      variable dgc2 : natural;
+      signal dgc3 : positive
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+
+  for u1 : comp1 use
+    entity work.c01s01b01x00p05n01i00733ent_a
+    generic map (dgc1, dgc2, dgc3)
+    port map ( dcent1, dcent2 );
+
+BEGIN
+
+  u1 : comp1
+    generic map (3,3,3)
+    port map (ee1,ee2);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b01x00p05n01i00733 - Variable and signal declaration can not be in local generic clause in component declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p05n01i00733arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc734.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc734.vhd
new file mode 100644
index 0000000..99ba3e4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc734.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc734.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s01b01x00p05n01i00734ent_a is
+  generic (
+    constant gc1 : integer;
+    variable gc2 : natural;
+    signal gc3 : positive
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x00p05n01i00734ent_a;
+
+architecture arch of c01s01b01x00p05n01i00734ent_a is
+begin
+  assert false 
+    report "FAIL: should not compile";
+end arch;
+
+ENTITY c01s01b01x00p05n01i00734ent IS
+  generic ( constant gen_con : natural := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x00p05n01i00734ent;
+
+ARCHITECTURE c01s01b01x00p05n01i00734arch OF c01s01b01x00p05n01i00734ent IS
+
+  signal s1 : integer;
+  signal s2 : natural;
+  signal s3 : positive;
+
+  component comp1
+    generic (
+      constant dgc1 : integer;
+      constant dgc2 : natural;
+      constant dgc3 : positive
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+
+  for u1 : comp1 use
+    entity work.c01s01b01x00p05n01i00734ent_a
+    generic map (dgc1, dgc2, dgc3)
+    port map ( dcent1, dcent2 );
+
+BEGIN
+
+  u1 : comp1
+    generic map (3,3,3)
+    port map (ee1,ee2);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b01x00p05n01i00734 - The generic list in the formal generic clause defines generic constants."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p05n01i00734arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc735.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc735.vhd
new file mode 100644
index 0000000..387522e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc735.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc735.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x00p05n01i00735pkg is
+  type actype is access integer;
+end c01s01b01x00p05n01i00735pkg;
+
+use work.c01s01b01x00p05n01i00735pkg.all;
+entity c01s01b01x00p05n01i00735ent_a is
+  generic (
+    constant gc1 : integer;
+    constant gc2 : actype;
+    constant gc3 : integer
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x00p05n01i00735ent_a;
+
+architecture arch of c01s01b01x00p05n01i00735ent_a is
+begin
+  assert false 
+    report "FAIL: should not compile";
+end arch;
+
+use work.c01s01b01x00p05n01i00735pkg.all;
+ENTITY c01s01b01x00p05n01i00735ent IS
+  generic ( constant gen_con : natural := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x00p05n01i00735ent;
+
+ARCHITECTURE c01s01b01x00p05n01i00735arch OF c01s01b01x00p05n01i00735ent IS
+
+  signal s1 : integer;
+  signal s2 : natural;
+  signal s3 : positive;
+
+  component comp1
+    generic (
+      constant dgc1 : integer;
+      constant dgc2 : actype;
+      constant dgc3 : integer
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+
+  for u1 : comp1 use
+    entity work.c01s01b01x00p05n01i00735ent_a
+    generic map (dgc1, dgc2.all, dgc3)
+    port map ( dcent1, dcent2 );
+
+BEGIN
+
+  u1 : comp1
+    generic map (acint,3,3)
+    port map (ee1,ee2);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b01x00p05n01i00735 - Formal generic can not be of type access." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p05n01i00735arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc736.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc736.vhd
new file mode 100644
index 0000000..4e0e18f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc736.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc736.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Tue Nov  5 16:41:06 1996  --
+--                 ****************************               --
+
+
+
+--                 ****************************                   --
+-- Reversed to VHDL 87 by reverse87.pl - Tue Nov  5 11:27:25 1996  --
+--                 ****************************                    --
+
+
+
+--                 ****************************               --
+-- Ported to VHDL 93 by port93.pl - Mon Nov  4 17:35:44 1996  --
+--                 ****************************               --
+
+
+library STD;
+use STD.textio.all;
+entity c01s01b01x00p05n01i00736ent_a is
+  generic (
+    constant gc1 : text;
+    constant gc2 : natural;
+    constant gc3 : positive
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x00p05n01i00736ent_a;
+
+architecture arch of c01s01b01x00p05n01i00736ent_a is
+begin
+  assert false 
+    report "FAIL: should not compile";
+end arch;
+
+ENTITY c01s01b01x00p05n01i00736ent IS
+  generic ( constant gen_con : natural := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x00p05n01i00736ent;
+
+ARCHITECTURE c01s01b01x00p05n01i00736arch OF c01s01b01x00p05n01i00736ent IS
+
+  signal s1 : integer;
+  signal s2 : natural;
+  signal s3 : positive;
+  file f1   : text open read_mode is "e.in";
+
+  component comp1
+    generic (
+      constant dgc1 : text;
+      constant dgc2 : natural;
+      constant dgc3 : positive
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+
+  for u1 : comp1 use
+    entity work.c01s01b01x00p05n01i00736ent_a
+    generic map (dgc1, dgc2, dgc3)
+    port map ( dcent1, dcent2 );
+
+BEGIN
+
+  u1 : comp1
+    generic map (f1,3,3)
+    port map (ee1,ee2);
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b01x00p05n01i00736 - Formal generic can not be of type FILE." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x00p05n01i00736arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc738.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc738.vhd
new file mode 100644
index 0000000..fedc526
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc738.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc738.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s01b01x01p04n03i00738ent_a is
+  generic (
+    constant gc1 : integer;
+    constant gc2 : natural;
+    constant gc3 : positive
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x01p04n03i00738ent_a;
+
+architecture arch of c01s01b01x01p04n03i00738ent_a is
+begin
+  assert false 
+    report "FAIL: should not compile";
+end arch;
+
+ENTITY c01s01b01x01p04n03i00738ent IS
+  generic ( constant gen_con : natural := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x01p04n03i00738ent;
+
+ARCHITECTURE c01s01b01x01p04n03i00738arch OF c01s01b01x01p04n03i00738ent IS
+
+  signal s1 : integer;
+  signal s2 : natural;
+  signal s3 : positive;
+
+  component comp1
+    generic (
+      constant dgc1 : integer;
+      constant dgc2 : natural;
+      constant dgc3 : positive
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+
+  for u1 : comp1 use entity work.c01s01b01x01p04n03i00738ent_a(arch)
+    generic map (dgc1, dgc2, dgc3)
+    port map ( dcent1, dcent2 );
+
+BEGIN
+
+  u1 : comp1
+    generic map (s1,s2,s3)
+    port map (ee1,ee2);
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c01s01b01x01p04n03i00738 - Formal generic should have actual or default expression."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p04n03i00738arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc739.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc739.vhd
new file mode 100644
index 0000000..93cea6d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc739.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc739.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s01b01x01p04n03i00739ent_a is
+  generic (
+    constant gc1 : integer;
+    constant gc2 : natural;
+    constant gc3 : positive
+    );
+  port ( signal cent1 : in bit;
+         signal cent2 : in bit
+         );
+end c01s01b01x01p04n03i00739ent_a;
+
+architecture arch of c01s01b01x01p04n03i00739ent_a is
+begin
+  assert false 
+    report "FAIL: should not compile";
+end arch;
+
+ENTITY c01s01b01x01p04n03i00739ent IS
+  generic ( constant gen_con : natural := 7 );
+  port ( signal ee1 : in bit;
+         signal ee2 : in bit;
+         signal eo1 : out bit
+         );
+END c01s01b01x01p04n03i00739ent;
+
+ARCHITECTURE c01s01b01x01p04n03i00739arch OF c01s01b01x01p04n03i00739ent IS
+
+  signal s1 : integer;
+  signal s2 : natural;
+  signal s3 : positive;
+
+  component comp1
+    generic (
+      constant dgc1 : integer;
+      constant dgc2 : natural;
+      constant dgc3 : positive
+      );
+    port ( signal dcent1 : in bit;
+           signal dcent2 : in bit
+           );
+  end component;
+
+  for u1 : comp1 use entity work.c01s01b01x01p04n03i00739ent_a(arch)
+    generic map (dgc1, dgc2, dgc3)
+    port map ( dcent1, dcent2 );
+
+BEGIN
+
+  u1 : comp1
+    port map (ee1,ee2);
+
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c01s01b01x01p04n03i00739 - Formal generic should have actual map correspoding to."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x01p04n03i00739arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc74.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc74.vhd
new file mode 100644
index 0000000..2bb2bd0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc74.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc74.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p09n02i00074ent IS
+END c04s03b01x02p09n02i00074ent;
+
+ARCHITECTURE c04s03b01x02p09n02i00074arch OF c04s03b01x02p09n02i00074ent IS
+  signal s1 : bit bus; -- Failure_here
+  -- a guarded signal, but is not a resolved signal.
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x02p09n02i00074 - Guarded signal should be a resolved signal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x02p09n02i00074arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc75.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc75.vhd
new file mode 100644
index 0000000..426814c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc75.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc75.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p10n04i00075ent IS
+END c04s03b01x02p10n04i00075ent;
+
+ARCHITECTURE c04s03b01x02p10n04i00075arch OF c04s03b01x02p10n04i00075ent IS
+  signal X : bit;
+BEGIN
+  TESTING: PROCESS(P)
+  BEGIN
+    X <= P;
+  END PROCESS TESTING;
+
+  TESTING1: PROCESS(Q)
+  BEGIN
+    X <= Q;      --Failure Here
+  END PROCESS TESTING1;
+
+  TEST: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x02p10n04i00075 - A signal with multiple source should be a resolved signal."
+      severity ERROR;
+    wait;
+  END PROCESS TEST;
+
+  ENDc04s03b01x02p10n04i00075arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc764.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc764.vhd
new file mode 100644
index 0000000..bb1f934
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc764.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc764.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c01s01b01x02p04n06i00764pkg is
+  type ar_sig_range    is range 1 to 8;
+  type ar_signal    is array (ar_sig_range) of BIT;
+end c01s01b01x02p04n06i00764pkg;
+
+use WORK.c01s01b01x02p04n06i00764pkg.all;
+ENTITY c01s01b01x02p04n06i00764ent IS
+  port (iface_array : ar_signal;
+        iface_index : ar_sig_range);
+END c01s01b01x02p04n06i00764ent;
+
+ARCHITECTURE c01s01b01x02p04n06i00764arch OF c01s01b01x02p04n06i00764ent IS
+  component COM_1 
+    port ( F1 : in BIT);
+  end component;
+BEGIN
+  CIS1: COM_1 
+    port map ( iface_array (iface_index)); -- Failure_here
+  --  Signal must be denoted by a static name
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b01x02p04n06i00764 - Associated actual does not have a static name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p04n06i00764arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc766.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc766.vhd
new file mode 100644
index 0000000..945ec48
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc766.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc766.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p06n01i00766ent_a IS
+  port ( c1 : in  integer ;
+         c2 : in  integer );
+END c01s01b01x02p06n01i00766ent_a;
+
+ARCHITECTURE c01s01b01x02p06n01i00766arch_a OF c01s01b01x02p06n01i00766ent_a IS
+
+BEGIN
+  test : process
+  begin
+    wait;
+  end process test;
+END c01s01b01x02p06n01i00766arch_a;
+
+
+ENTITY c01s01b01x02p06n01i00766ent IS
+  port ( p1 : out  integer ;
+         p2 : in   integer );
+END c01s01b01x02p06n01i00766ent;
+
+ARCHITECTURE c01s01b01x02p06n01i00766arch OF c01s01b01x02p06n01i00766ent IS
+  component c01s01b01x02p06n01i00766ent_b
+    port (    c1 : in  integer ;
+              c2 : in  integer );
+  end component;
+  for L : c01s01b01x02p06n01i00766ent_b use entity work.c01s01b01x02p06n01i00766ent_a(c01s01b01x02p06n01i00766arch_a);
+BEGIN
+  L: c01s01b01x02p06n01i00766ent_b port map (p1, p2);    -- Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b01x02p06n01i00766 - An actual of mode out can not be associated with a formal of mode in."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p06n01i00766arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc767.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc767.vhd
new file mode 100644
index 0000000..479bfb8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc767.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc767.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p07n01i00767ent_a IS
+  port ( c1 : out    integer ;
+         c2 : in    integer );
+END c01s01b01x02p07n01i00767ent_a;
+
+ARCHITECTURE c01s01b01x02p07n01i00767arch_a OF c01s01b01x02p07n01i00767ent_a IS
+
+BEGIN
+  c1 <= c2;
+END c01s01b01x02p07n01i00767arch_a;
+
+
+ENTITY c01s01b01x02p07n01i00767ent IS
+  port ( p1 : in    integer ;
+         p2 : in    integer );
+END c01s01b01x02p07n01i00767ent;
+
+ARCHITECTURE c01s01b01x02p07n01i00767arch OF c01s01b01x02p07n01i00767ent IS
+  component c01s01b01x02p07n01i00767ent_b
+    port ( c1 : out    integer ;
+           c2 : in    integer );
+  end component;
+  for L : c01s01b01x02p07n01i00767ent_b use entity work.c01s01b01x02p07n01i00767ent_a(c01s01b01x02p07n01i00767arch_a);
+BEGIN
+  L :c01s01b01x02p07n01i00767ent_b port map (p1, p2);
+  -- Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p07n01i00767 - An actual of mode in cannot be associated with a formal of mode out."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p07n01i00767arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc769.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc769.vhd
new file mode 100644
index 0000000..f3257b4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc769.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc769.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p08n01i00769ent_a IS
+  port ( c1 : inout    integer ;
+         c2 : out    integer );
+END c01s01b01x02p08n01i00769ent_a;
+
+ARCHITECTURE c01s01b01x02p08n01i00769arch_a OF c01s01b01x02p08n01i00769ent_a IS
+
+BEGIN
+  c2 <= c1;
+END c01s01b01x02p08n01i00769arch_a;
+
+
+
+ENTITY c01s01b01x02p08n01i00769ent IS
+  port ( p1 : out    integer ;
+         p2 : inout    integer );
+END c01s01b01x02p08n01i00769ent;
+
+ARCHITECTURE c01s01b01x02p08n01i00769arch OF c01s01b01x02p08n01i00769ent IS
+  component c01s01b01x02p08n01i00769ent_b
+    port ( c1 : inout    integer ;
+           c2 : out    integer );
+  end component ;
+  for L : c01s01b01x02p08n01i00769ent_b use entity work.c01s01b01x02p08n01i00769ent_a(c01s01b01x02p08n01i00769arch_a);
+BEGIN
+  L : c01s01b01x02p08n01i00769ent_b port map (p1, p2);
+  --Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p08n01i00769 - An actual of mode out can not be associated with a formal port of mode inout."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p08n01i00769arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc770.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc770.vhd
new file mode 100644
index 0000000..3f17e50
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc770.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc770.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p08n01i00770ent_a IS
+  port ( c1 : inout    integer ;
+         c2 : out    integer );
+END c01s01b01x02p08n01i00770ent_a;
+
+ARCHITECTURE c01s01b01x02p08n01i00770arch_a OF c01s01b01x02p08n01i00770ent_a IS
+
+BEGIN
+  c2 <= c1;
+END c01s01b01x02p08n01i00770arch_a;
+
+
+
+ENTITY c01s01b01x02p08n01i00770ent IS
+  port ( p1 : in       integer ;
+         p2 : inout    integer );
+END c01s01b01x02p08n01i00770ent;
+
+ARCHITECTURE c01s01b01x02p08n01i00770arch OF c01s01b01x02p08n01i00770ent IS
+  component c01s01b01x02p08n01i00770ent_b
+    port ( c1 : inout    integer ;
+           c2 : out    integer );
+  end component ;
+  for L : c01s01b01x02p08n01i00770ent_b use entity work.c01s01b01x02p08n01i00770ent_a(c01s01b01x02p08n01i00770arch_a);
+BEGIN
+  L : c01s01b01x02p08n01i00770ent_b port map (p1, p2);
+  --Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p08n01i00770 - An actual of mode in can not be associated with a formal port of mode inout."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p08n01i00770arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc771.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc771.vhd
new file mode 100644
index 0000000..13e5b21
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc771.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc771.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p08n01i00771ent_a IS
+  port ( c1 : inout    integer ;
+         c2 : out    integer );
+END c01s01b01x02p08n01i00771ent_a;
+
+ARCHITECTURE c01s01b01x02p08n01i00771arch_a OF c01s01b01x02p08n01i00771ent_a IS
+
+BEGIN
+  c2 <= c1;
+END c01s01b01x02p08n01i00771arch_a;
+
+
+
+ENTITY c01s01b01x02p08n01i00771ent IS
+  port ( p1 : buffer    integer ;
+         p2 : inout    integer );
+END c01s01b01x02p08n01i00771ent;
+
+ARCHITECTURE c01s01b01x02p08n01i00771arch OF c01s01b01x02p08n01i00771ent IS
+  component c01s01b01x02p08n01i00771ent_b
+    port ( c1 : inout    integer ;
+           c2 : out    integer );
+  end component ;
+  for L : c01s01b01x02p08n01i00771ent_b use entity work.c01s01b01x02p08n01i00771ent_a(c01s01b01x02p08n01i00771arch_a);
+BEGIN
+  L : c01s01b01x02p08n01i00771ent_b port map (p1, p2);
+  --Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p08n01i00771 - An actual of mode buffer can not be associated with a formal port of mode inout."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p08n01i00771arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc773.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc773.vhd
new file mode 100644
index 0000000..86af30c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc773.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc773.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p09n01i00773ent_a IS
+  port ( c1 : buffer    integer ;
+         c2 : in       integer );
+END c01s01b01x02p09n01i00773ent_a;
+
+ARCHITECTURE c01s01b01x02p09n01i00773arch_a OF c01s01b01x02p09n01i00773ent_a IS
+
+BEGIN
+  c1 <= c2;
+END c01s01b01x02p09n01i00773arch_a;
+
+
+ENTITY c01s01b01x02p09n01i00773ent IS
+  port ( p1 : out    integer ;
+         p2 : in       integer );
+END c01s01b01x02p09n01i00773ent;
+
+ARCHITECTURE c01s01b01x02p09n01i00773arch OF c01s01b01x02p09n01i00773ent IS
+  component c01s01b01x02p09n01i00773ent_b
+    port ( c1 : buffer    integer ;
+           c2 : in       integer );
+  end component;
+  for L : c01s01b01x02p09n01i00773ent_b use entity work.c01s01b01x02p09n01i00773ent_a(c01s01b01x02p09n01i00773arch_a);
+BEGIN
+  L : c01s01b01x02p09n01i00773ent_b port map (p1, p2);
+  --Failure here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p09n01i00773 - An actual of mode out cannot be associated with a formal port of mode buffer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p09n01i00773arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc774.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc774.vhd
new file mode 100644
index 0000000..59f008b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc774.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc774.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p09n01i00774ent_a IS
+  port ( c1 : buffer    integer ;
+         c2 : in       integer );
+END c01s01b01x02p09n01i00774ent_a;
+
+ARCHITECTURE c01s01b01x02p09n01i00774arch_a OF c01s01b01x02p09n01i00774ent_a IS
+
+BEGIN
+  c1 <= c2;
+END c01s01b01x02p09n01i00774arch_a;
+
+
+ENTITY c01s01b01x02p09n01i00774ent IS
+  port ( p1 : in integer ;
+         p2 : in integer );
+END c01s01b01x02p09n01i00774ent;
+
+ARCHITECTURE c01s01b01x02p09n01i00774arch OF c01s01b01x02p09n01i00774ent IS
+  component c01s01b01x02p09n01i00774ent_b
+    port ( c1 : buffer    integer ;
+           c2 : in       integer );
+  end component;
+  for L : c01s01b01x02p09n01i00774ent_b use entity work.c01s01b01x02p09n01i00774ent_a(c01s01b01x02p09n01i00774arch_a);
+BEGIN
+  L : c01s01b01x02p09n01i00774ent_b port map (p1, p2);
+  --Failure here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p09n01i00774 - An actual of mode in cannot be associated with a formal port of mode buffer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p09n01i00774arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc775.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc775.vhd
new file mode 100644
index 0000000..75b02b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc775.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc775.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p09n01i00775ent_a IS
+  port ( c1 : buffer    integer ;
+         c2 : in       integer );
+END c01s01b01x02p09n01i00775ent_a;
+
+ARCHITECTURE c01s01b01x02p09n01i00775arch_a OF c01s01b01x02p09n01i00775ent_a IS
+
+BEGIN
+  c1 <= c2;
+END c01s01b01x02p09n01i00775arch_a;
+
+
+ENTITY c01s01b01x02p09n01i00775ent IS
+  port ( p1 : inout    integer ;
+         p2 : in       integer );
+END c01s01b01x02p09n01i00775ent;
+
+ARCHITECTURE c01s01b01x02p09n01i00775arch OF c01s01b01x02p09n01i00775ent IS
+  component c01s01b01x02p09n01i00775ent_b
+    port ( c1 : buffer    integer ;
+           c2 : in       integer );
+  end component;
+  for L : c01s01b01x02p09n01i00775ent_b use entity work.c01s01b01x02p09n01i00775ent_a(c01s01b01x02p09n01i00775arch_a);
+BEGIN
+  L : c01s01b01x02p09n01i00775ent_b port map (p1, p2);
+  --Failure here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p09n01i00775 - An actual of mode inout cannot be associated with a formal port of mode buffer."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p09n01i00775arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc779.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc779.vhd
new file mode 100644
index 0000000..db64d42
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc779.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc779.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p11n02i00779ent_a IS
+  port (c2 : buffer Bit);
+END c01s01b01x02p11n02i00779ent_a;
+
+ARCHITECTURE c01s01b01x02p11n02i00779arch_a OF c01s01b01x02p11n02i00779ent_a IS
+BEGIN
+END c01s01b01x02p11n02i00779arch_a;
+
+
+
+ENTITY c01s01b01x02p11n02i00779ent IS
+  port(P2 : buffer Bit);
+END c01s01b01x02p11n02i00779ent;
+
+ARCHITECTURE c01s01b01x02p11n02i00779arch OF c01s01b01x02p11n02i00779ent IS
+  component c01s01b01x02p11n02i00779ent_b
+    port (C2 : buffer Bit);
+  end component;
+  for L : c01s01b01x02p11n02i00779ent_b use entity work.c01s01b01x02p11n02i00779ent(c01s01b01x02p11n02i00779arch) port map (C2);
+BEGIN
+
+  L : c01s01b01x02p11n02i00779ent_b port map (C2 => P2);
+
+  TEST : Process
+  begin
+    P2 <= bit'('1');
+    wait for 15 ns;
+  end process TEST;
+
+  TESTING: PROCESS
+  BEGIN
+    P2 <= bit'('0');   -- Failure_here
+    -- This error will be indicated at elaboration time.
+    wait for 11 ns;
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p11n02i00779 - Actual can have at most one source."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p11n02i00779arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc780.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc780.vhd
new file mode 100644
index 0000000..b04af79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc780.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc780.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p11n01i00780ent IS
+  port ( S : buffer bit );
+END c01s01b01x02p11n01i00780ent;
+
+ARCHITECTURE c01s01b01x02p11n01i00780arch OF c01s01b01x02p11n01i00780ent IS
+
+BEGIN
+  TEST : PROCESS
+  BEGIN
+    S <= bit'('1');
+    wait for 15 ns;
+  END PROCESS TEST;
+
+  TESTING: PROCESS
+  BEGIN
+    S <= bit'('0'); -- Failure_here
+    -- signal S of mode buffer is being
+    -- driven by two sources one in each
+    -- process. Signal S can be driven by
+    -- only one source.
+    -- This error will be indicated at elaboration time
+    wait for 11 ns;
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p11n01i00780 - A buffer port can have at most one source."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p11n01i00780arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc781.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc781.vhd
new file mode 100644
index 0000000..f720de0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc781.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc781.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p12n04i00781ent_a IS
+  port (
+    C1 : in         Bit;
+    C2 : inout      Bit;
+    C3 : linkage    Bit;
+    C4 : out        Bit;
+    C5 : Buffer     Bit
+    );
+END c01s01b01x02p12n04i00781ent_a;
+
+ARCHITECTURE c01s01b01x02p12n04i00781arch_a OF c01s01b01x02p12n04i00781ent_a IS
+BEGIN
+END c01s01b01x02p12n04i00781arch_a;
+
+
+
+ENTITY c01s01b01x02p12n04i00781ent IS
+  port (
+    A1 : in         Bit;
+    A2 : inout      Bit;
+    A3 : linkage    Bit;
+    A4 : out        Bit;
+    A5 : Buffer     Bit
+    ) ;
+END c01s01b01x02p12n04i00781ent;
+
+ARCHITECTURE c01s01b01x02p12n04i00781arch OF c01s01b01x02p12n04i00781ent IS
+  component c01s01b01x02p12n04i00781ent_b
+    port (
+      C1 : in         Bit;
+      C2 : inout      Bit;
+      C3 : linkage    Bit;
+      C4 : out        Bit;
+      C5 : Buffer     Bit
+      );
+  end component;
+  for L : c01s01b01x02p12n04i00781ent_b use entity work.c01s01b01x02p12n04i00781ent_a(c01s01b01x02p12n04i00781arch_a);
+BEGIN
+  L : c01s01b01x02p12n04i00781ent_b port map ( C1 => open, C2 => open, C3 => open, C4 => open, C5 => open );
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p12n04i00781 - A port of mode in may not be unconnected."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p12n04i00781arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc783.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc783.vhd
new file mode 100644
index 0000000..a183daa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc783.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc783.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b01x02p12n04i00783a IS
+  port (   c1 : out    bit_vector;
+           c2 : inout    bit_vector;
+           c3 : buffer    bit_vector;
+           c4 : linkage     bit_vector);
+END c01s01b01x02p12n04i00783ent_a;
+
+ARCHITECTURE c01s01b01x02p12n04i00783arch_a OF c01s01b01x02p12n04i00783ent_a IS
+BEGIN
+END c01s01b01x02p12n04i00783arch_a;
+
+
+
+ENTITY c01s01b01x02p12n04i00783ent IS
+END c01s01b01x02p12n04i00783ent;
+
+ARCHITECTURE c01s01b01x02p12n04i00783arch OF c01s01b01x02p12n04i00783ent IS
+  component c01s01b01x02p12n04i00783ent_b
+    port (   c1 : out    bit_vector;
+             c2 : inout    bit_vector;
+             c3 : buffer    bit_vector;
+             c4 : linkage     bit_vector);
+  end component;
+  for L : c01s01b01x02p12n04i00783ent_b use entity work.c01s01b01x02p12n04i00783ent_a(c01s01b01x02p12n04i00783arch_a);
+BEGIN
+  L : ch01010102_p01204_03_ent_b 
+    port map (  OPEN,   -- Failure_here
+                OPEN,   -- Failure_here
+                OPEN,   -- Failure_here
+                OPEN);  -- Failure_here
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b01x02p12n04i00783 - The port which is of mode other than in and whose type is unconstrained may not be unconnected."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b01x02p12n04i00783arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc785.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc785.vhd
new file mode 100644
index 0000000..48f266e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc785.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc785.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b02x00p03n01i00785ent IS
+  configuration C of E is               -- component illegal here
+    for junk
+  end for;
+  end C;
+  END c01s01b02x00p03n01i00785ent;
+
+  ARCHITECTURE c01s01b02x00p03n01i00785arch OF c01s01b02x00p03n01i00785ent IS
+
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c01s01b02x00p03n01i00785 - Configuration declarations are not permitted in an entity declaration."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c01s01b02x00p03n01i00785arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc786.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc786.vhd
new file mode 100644
index 0000000..48c5146
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc786.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc786.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b02x00p03n01i00786ent IS
+  --
+  -- Component declarations are not allowed here
+  --
+  component                             -- component illegal here
+  end component;
+END c01s01b02x00p03n01i00786ent;
+
+ARCHITECTURE c01s01b02x00p03n01i00786arch OF c01s01b02x00p03n01i00786ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b02x00p03n01i00786 - Component declarations are not permitted in an entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b02x00p03n01i00786arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc787.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc787.vhd
new file mode 100644
index 0000000..e7b28a6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc787.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc787.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b02x00p03n01i00787ent IS
+  variable illegal : integer;           -- variable illegal here
+END c01s01b02x00p03n01i00787ent;
+
+ARCHITECTURE c01s01b02x00p03n01i00787arch OF c01s01b02x00p03n01i00787ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b02x00p03n01i00787 - Variable declarations are not permitted in an entity declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b02x00p03n01i00787arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc788.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc788.vhd
new file mode 100644
index 0000000..03ac312
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc788.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc788.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b02x00p03n01i00788ent IS
+  entity illegal is                     -- entity illegal here    
+  end illegal;
+  END c01s01b02x00p03n01i00788ent;
+
+  ARCHITECTURE c01s01b02x00p03n01i00788arch OF c01s01b02x00p03n01i00788ent IS
+
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c01s01b02x00p03n01i00788 - Entity declarations are not permitted in an entity declaration."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c01s01b02x00p03n01i00788arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc789.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc789.vhd
new file mode 100644
index 0000000..6e70cb7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc789.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc789.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b02x00p03n01i00789ent IS
+  package c01s01b02x00p03n01i00789pkg is                          -- package illegal here
+  end c01s01b02x00p03n01i00789pkg;
+  END c01s01b02x00p03n01i00789ent;
+
+  ARCHITECTURE c01s01b02x00p03n01i00789arch OF c01s01b02x00p03n01i00789ent IS
+
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c01s01b02x00p03n01i00789 - Package declarations are not permitted in an entity declaration."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c01s01b02x00p03n01i00789arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc79.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc79.vhd
new file mode 100644
index 0000000..50f6d0e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc79.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc79.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p12n01i00079ent IS
+END c04s03b01x02p12n01i00079ent;
+
+ARCHITECTURE c04s03b01x02p12n01i00079arch OF c04s03b01x02p12n01i00079ent IS
+  type arrbit    is array (1 to 3) of bit;
+  type comp_vect    is array (positive range <>) of arrbit;
+  
+  function F(BB: comp_vect) return arrbit is
+  begin
+    return "111";
+  end;
+  
+  signal X : F arrbit ;
+BEGIN
+  TESTING: PROCESS(P)
+  BEGIN
+    X(1) <= P;  -- Failure_here
+    -- error as only one subelement of X has
+    -- a driver in this process.
+    assert FALSE 
+      report "***FAILED TEST:c04s03b01x02p12n01i00079 - All of the subelements of the signal should have a driver in a process."
+      severity ERROR;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x02p12n01i00079arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc790.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc790.vhd
new file mode 100644
index 0000000..ef76e68
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc790.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc790.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b02x00p03n01i00790ent IS
+  architecture A of E is                -- architecture illegal here
+  begin
+  end A;
+  END c01s01b02x00p03n01i00790ent;
+
+  ARCHITECTURE c01s01b02x00p03n01i00790arch OF c01s01b02x00p03n01i00790ent IS
+
+  BEGIN
+    TESTING: PROCESS
+    BEGIN
+      assert FALSE 
+        report "***FAILED TEST: c01s01b02x00p03n01i00790 - Architecture body are not permitted in an entity declaration."
+        severity ERROR;
+      wait;
+    END PROCESS TESTING;
+
+  END c01s01b02x00p03n01i00790arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc793.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc793.vhd
new file mode 100644
index 0000000..75a7674
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc793.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc793.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p04n01i00793ent IS
+  port (CLK: inout bit);
+begin
+  process
+  begin
+    CLK <= not CLK; --Failure_here. error as process is not passive.
+  end process;
+END c01s01b03x00p04n01i00793ent;
+
+ARCHITECTURE c01s01b03x00p04n01i00793arch OF c01s01b03x00p04n01i00793ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s01b03x00p04n01i00793 - All entity statements must be passive."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p04n01i00793arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc794.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc794.vhd
new file mode 100644
index 0000000..d99de4d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc794.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc794.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00794ent IS
+begin
+  port ( isig : in  bit;
+         osig : out bit );
+END c01s01b03x00p03n01i00794ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00794arch OF c01s01b03x00p03n01i00794ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00794 - Port clause is not permitted as an entity statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00794arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc795.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc795.vhd
new file mode 100644
index 0000000..8d8e3b6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc795.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc795.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00795ent IS
+begin
+  generic ( constant const : boolean );
+END c01s01b03x00p03n01i00795ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00795arch OF c01s01b03x00p03n01i00795ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00795 - Generic clause is not permitted as an entity statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00795arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc796.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc796.vhd
new file mode 100644
index 0000000..2d47bfb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc796.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc796.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00796ent IS
+begin
+  wait 3 ns;   -- illegal location for wait
+END c01s01b03x00p03n01i00796ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00796arch OF c01s01b03x00p03n01i00796ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00796 - Wait statement can not appear in entity statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00796arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc797.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc797.vhd
new file mode 100644
index 0000000..c465d72
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc797.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc797.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00797ent IS
+  signal   err : boolean := false;
+begin
+  err   <= true;   -- illegal location for signal assignment
+END c01s01b03x00p03n01i00797ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00797arch OF c01s01b03x00p03n01i00797ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00797 - Signal assignment statement can not appear in entity statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00797arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc798.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc798.vhd
new file mode 100644
index 0000000..c745eff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc798.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc798.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00798ent IS
+  signal   err : boolean := false;
+begin
+  case err is                           -- illegal location for case statement
+    when true | false =>
+      assert false
+        report "'case' statement accepted in an entity statement."
+        severity note ;
+  end case;
+END c01s01b03x00p03n01i00798ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00798arch OF c01s01b03x00p03n01i00798ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00798 - Case statement can not appear in entity statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00798arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc799.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc799.vhd
new file mode 100644
index 0000000..5f9f037
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc799.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc799.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00799ent IS
+
+begin
+  if TRUE then                           -- illegal location for if statement
+    assert false
+      report "'if' statement accepted in an entity statement."
+      severity note ;
+  end if;
+END c01s01b03x00p03n01i00799ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00799arch OF c01s01b03x00p03n01i00799ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00799 - If statement can not appear in entity statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00799arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc8.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc8.vhd
new file mode 100644
index 0000000..7a26fa8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc8.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc8.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s01b00x00p08n01i00008ent IS
+END c04s01b00x00p08n01i00008ent;
+
+ARCHITECTURE c04s01b00x00p08n01i00008arch OF c04s01b00x00p08n01i00008ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 1) of BOOLEAN;
+    type A2 is array (1 to 1) of BOOLEAN;
+    
+    variable V7: A1;
+    variable V8: A2;
+  BEGIN
+    if V7 = V8 then  -- Failure_here
+      -- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
+      null ;
+    end if;
+    
+    assert FALSE 
+      report "***FAILED TEST: c04s01b00x00p08n01i00008 - Types are different and hence incompatible."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s01b00x00p08n01i00008arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc800.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc800.vhd
new file mode 100644
index 0000000..f0f428e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc800.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc800.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00800ent IS
+
+begin
+  L: loop                               -- illegal location for loop statement
+  end loop L;
+END c01s01b03x00p03n01i00800ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00800arch OF c01s01b03x00p03n01i00800ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00800 - Loop statement can not appear in entity statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00800arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc801.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc801.vhd
new file mode 100644
index 0000000..b41de03
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc801.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc801.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00801ent IS
+
+begin
+  next;                                 -- illegal location for next statement
+END c01s01b03x00p03n01i00801ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00801arch OF c01s01b03x00p03n01i00801ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00801 - Next statement can not appear in entity statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00801arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc802.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc802.vhd
new file mode 100644
index 0000000..0e07875
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc802.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc802.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00802ent IS
+
+begin
+  exit;                                 -- illegal location for exit statement
+END c01s01b03x00p03n01i00802ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00802arch OF c01s01b03x00p03n01i00802ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00802 - Exit statement can not appear in entity statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00802arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc803.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc803.vhd
new file mode 100644
index 0000000..fdab6f6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc803.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc803.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00803ent IS
+begin
+  return;                            -- illegal location for return statement
+END c01s01b03x00p03n01i00803ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00803arch OF c01s01b03x00p03n01i00803ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00803 - Return statement can not appear in entity statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00803arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc804.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc804.vhd
new file mode 100644
index 0000000..ffcc8e0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc804.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc804.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s01b03x00p03n01i00804ent IS
+begin
+  return;                            -- illegal location for return statement
+END c01s01b03x00p03n01i00804ent;
+
+ARCHITECTURE c01s01b03x00p03n01i00804arch OF c01s01b03x00p03n01i00804ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s01b03x00p03n01i00804 - Null statement can not appear in entity statement." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s01b03x00p03n01i00804arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc806.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc806.vhd
new file mode 100644
index 0000000..3218fd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc806.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc806.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b00x00p02n01i00806ent IS
+END c01s02b00x00p02n01i00806ent;
+
+ARCHITECTURE c01s02b00x00p02n01i00806arch OF c01s02b00x00p02n01i00806ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b00x00p02n01i00806 - Missing identifier."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p02n01i00806arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc807.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc807.vhd
new file mode 100644
index 0000000..5570527
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc807.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc807.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b00x00p02n01i00807ent IS
+END c01s02b00x00p02n01i00807ent;
+
+ARCHITECTURE c01s02b00x00p02n01i00807arch OF c01s02b00x00p02n01i00807ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b00x00p02n01i00807 - The name after the reserved word of is not an entity name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p02n01i00807arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc808.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc808.vhd
new file mode 100644
index 0000000..cd07513
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc808.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc808.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b00x00p02n01i00808ent IS
+END c01s02b00x00p02n01i00808ent;
+
+ARCHITECTURE c01s02b00x00p02n01i00808arch OF c01s02b00x00p02n01i00808ent  --failure here 
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b00x00p02n01i00808 - Reserved word is has to follow reserved word for."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p02n01i00808arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc809.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc809.vhd
new file mode 100644
index 0000000..c9149ff
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc809.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc809.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b00x00p02n01i00809ent IS
+END c01s02b00x00p02n01i00809ent;
+
+ARCHITECTURE c01s02b00x00p02n01i00809arch OF c01s02b00x00p02n01i00809ent  --failure here 
+
+  entity B is  -- Failure_here
+-- ERROR - entity not allowed here
+end;
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b00x00p02n01i00809 - Entity declaration is not allowed in an architecture."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p02n01i00809arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc810.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc810.vhd
new file mode 100644
index 0000000..8d3da72
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc810.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc810.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b00x00p02n01i00810ent IS
+END c01s02b00x00p02n01i00810ent;
+
+ARCHITECTURE c01s02b00x00p02n01i00810arch OF c01s02b00x00p02n01i00810ent IS
+  --failure here 
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b00x00p02n01i00810 - Reserved word 'is' is not followed by reserved word 'begin'."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p02n01i00810arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc811.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc811.vhd
new file mode 100644
index 0000000..6e84d90
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc811.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc811.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b00x00p02n01i00811ent IS
+END c01s02b00x00p02n01i00811ent;
+
+ARCHITECTURE c01s02b00x00p02n01i00811arch OF c01s02b00x00p02n01i00811ent IS 
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b00x00p02n01i00811 - Architecture statement part is not followed by the reserved word end."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  c01s02b00x00p02n01i00811arch;   --Failure here
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc812.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc812.vhd
new file mode 100644
index 0000000..034717c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc812.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc812.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b00x00p02n01i00812ent IS
+END c01s02b00x00p02n01i00812ent;
+
+ARCHITECTURE c01s02b00x00p02n01i00812arch OF c01s02b00x00p02n01i00812ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b00x00p02n01i00812 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p02n01i00812arch   --Failure here
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc813.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc813.vhd
new file mode 100644
index 0000000..3c27acd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc813.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc813.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ARCHITECTURE c01s02b00x00p04n02i00813arch OF c01s02b00x00p04n02i00813ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s02b00x00p04n02i00813 - Entity declaration and architecture body must reside in the same library."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p04n02i00813arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc815.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc815.vhd
new file mode 100644
index 0000000..127cbd6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc815.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc815.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b00x00p05n01i00815ent IS
+END c01s02b00x00p05n01i00815ent;
+
+ARCHITECTURE c01s02b00x00p05n01i00815arch OF c01s02b00x00p05n01i00815ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST: c01s02b00x00p05n01i00815 - Simple name at the end of architecture does not repeat the identifier of the architecure."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b00x00p05n01i00815;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc818.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc818.vhd
new file mode 100644
index 0000000..b6a0619
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc818.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc818.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b01x00p03n01i00818ent IS
+END c01s02b01x00p03n01i00818ent;
+
+ARCHITECTURE c01s02b01x00p03n01i00818arch OF c01s02b01x00p03n01i00818ent IS
+  variable err : boolean := true;       -- illegal location for variable declaration 
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b01x00p03n01i00818 - Variable declaration can not appear in the architecture declaration part."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b01x00p03n01i00818arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc819.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc819.vhd
new file mode 100644
index 0000000..4640e10
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc819.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc819.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b01x00p03n01i00819ent IS
+END c01s02b01x00p03n01i00819ent;
+
+ARCHITECTURE c01s02b01x00p03n01i00819arch OF c01s02b01x00p03n01i00819ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b01x00p03n01i00819 - Only concurrent statements allowed in architecture statement part."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  wait;
+
+END c01s02b01x00p03n01i00819arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc821.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc821.vhd
new file mode 100644
index 0000000..8e05c18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc821.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc821.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b02x00p02n01i00821ent IS
+END c01s02b02x00p02n01i00821ent;
+
+ARCHITECTURE c01s02b02x00p02n01i00821arch OF c01s02b02x00p02n01i00821ent IS
+  signal err : boolean := true;
+BEGIN
+
+  case err is                           -- illegal location for case statement
+    when true | false =>
+      assert false
+        report "'case' statement accepted in an entity statement."
+        severity note ;
+  end case;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b02x00p02n01i00821 - Architecture statement can only have concurrent statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b02x00p02n01i00821arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc822.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc822.vhd
new file mode 100644
index 0000000..8ca1721
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc822.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc822.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b02x00p02n01i00822ent IS
+END c01s02b02x00p02n01i00822ent;
+
+ARCHITECTURE c01s02b02x00p02n01i00822arch OF c01s02b02x00p02n01i00822ent IS
+
+BEGIN
+
+  if TRUE then                           -- illegal location for if statement
+  end if;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b02x00p02n01i00822 - Architecture statement can only have concurrent statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b02x00p02n01i00822arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc823.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc823.vhd
new file mode 100644
index 0000000..17b3a23
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc823.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc823.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b02x00p02n01i00823ent IS
+END c01s02b02x00p02n01i00823ent;
+
+ARCHITECTURE c01s02b02x00p02n01i00823arch OF c01s02b02x00p02n01i00823ent IS
+
+BEGIN
+
+  L: loop                               -- illegal location for loop statement
+  end loop L;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b02x00p02n01i00823 - Architecture statement can only have concurrent statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b02x00p02n01i00823arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc824.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc824.vhd
new file mode 100644
index 0000000..7ebe65c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc824.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc824.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b02x00p02n01i00824ent IS
+END c01s02b02x00p02n01i00824ent;
+
+ARCHITECTURE c01s02b02x00p02n01i00824arch OF c01s02b02x00p02n01i00824ent IS
+
+BEGIN
+
+  next;                                 -- illegal location for next statement
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b02x00p02n01i00824 - Architecture statement can only have concurrent statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b02x00p02n01i00824arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc825.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc825.vhd
new file mode 100644
index 0000000..173cc16
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc825.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc825.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b02x00p02n01i00825ent IS
+END c01s02b02x00p02n01i00825ent;
+
+ARCHITECTURE c01s02b02x00p02n01i00825arch OF c01s02b02x00p02n01i00825ent IS
+
+BEGIN
+
+  exit;                                 -- illegal location for exit statement
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b02x00p02n01i00825 - Architecture statement can only have concurrent statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b02x00p02n01i00825arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc826.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc826.vhd
new file mode 100644
index 0000000..10152cb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc826.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc826.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b02x00p02n01i00826ent IS
+END c01s02b02x00p02n01i00826ent;
+
+ARCHITECTURE c01s02b02x00p02n01i00826arch OF c01s02b02x00p02n01i00826ent IS
+
+BEGIN
+
+  return;                            -- illegal location for return statement
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b02x00p02n01i00826 - Architecture statement can only have concurrent statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b02x00p02n01i00826arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc827.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc827.vhd
new file mode 100644
index 0000000..bcf6553
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc827.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc827.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b02x00p02n01i00827ent IS
+END c01s02b02x00p02n01i00827ent;
+
+ARCHITECTURE c01s02b02x00p02n01i00827arch OF c01s02b02x00p02n01i00827ent IS
+
+BEGIN
+
+  null;                                 -- illegal location for null statement
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b02x00p02n01i00827 - Architecture statement can only have concurrent statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b02x00p02n01i00827arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc828.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc828.vhd
new file mode 100644
index 0000000..5ca95c4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc828.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc828.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s02b02x00p02n01i00828ent IS
+END c01s02b02x00p02n01i00828ent;
+
+ARCHITECTURE c01s02b02x00p02n01i00828arch OF c01s02b02x00p02n01i00828ent IS
+
+BEGIN
+
+  wait 3 ns;                        -- illegal location for wait statement
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s02b02x00p02n01i00828 - Architecture statement can only have concurrent statement."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s02b02x00p02n01i00828arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc829.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc829.vhd
new file mode 100644
index 0000000..b762ddd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc829.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc829.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s03b00x00p02n01i00829ent IS
+END c01s03b00x00p02n01i00829ent;
+
+ARCHITECTURE c01s03b00x00p02n01i00829arch OF c01s03b00x00p02n01i00829ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b00x00p02n01i00829- Missing entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b00x00p02n01i00829arch;
+
+use work.all;
+configuration C of  is   --- Failure_here
+  for c01s03b00x00p02n01i00829_arch
+    use WORK.all ;
+  end for ;
+end C;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc830.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc830.vhd
new file mode 100644
index 0000000..e20bafe
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc830.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc830.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s03b00x00p02n01i00830ent IS
+END c01s03b00x00p02n01i00830ent;
+
+ARCHITECTURE c01s03b00x00p02n01i00830arch OF c01s03b00x00p02n01i00830ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b00x00p02n01i00830 - Missing identifier after the reserved word CONFIGURATION in the configuration declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b00x00p02n01i00830arch;
+
+use work.all;
+CONFIGURATION  OF c01s03b00x00p02n01i00830ent IS   --- Failure_here
+  FOR c01s03b00x00p02n01i00830arch
+    use WORK.all ;
+  END FOR;
+END c01s03b00x00p02n01i00830cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc831.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc831.vhd
new file mode 100644
index 0000000..cf2a890
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc831.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc831.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s03b00x00p02n01i00831ent IS
+END c01s03b00x00p02n01i00831ent;
+
+ARCHITECTURE c01s03b00x00p02n01i00831arch OF c01s03b00x00p02n01i00831ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b00x00p02n01i00831 - Missing entity name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b00x00p02n01i00831arch;
+
+use work.all;
+configuration C of c01s03b00x00p02n01i00831ent is   
+  for c01s03b00x00p02n01i00831arch
+    use WORK.all ;
+  end for ;
+  C;   -- Failure_here
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc832.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc832.vhd
new file mode 100644
index 0000000..276d742
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc832.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc832.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s03b00x00p02n01i00832ent IS
+END c01s03b00x00p02n01i00832ent;
+
+ARCHITECTURE c01s03b00x00p02n01i00832arch OF c01s03b00x00p02n01i00832ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b00x00p02n01i00832 - Missing semicolon."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b00x00p02n01i00832arch;
+
+use work.all;
+configuration C of c01s03b00x00p02n01i00832ent is   
+  for c01s03b00x00p02n01i00832arch
+    use WORK.all ;
+  end for ;
+end C   -- Failure_here
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc834.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc834.vhd
new file mode 100644
index 0000000..589f3e2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc834.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc834.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+configuration c01s03b00x00p05n02i00834cfg of c01s03b00x00p05n02i00834ent is   --Failure here
+  for c01s03b00x00p05n02i00834arch
+    use work.all;
+  end for;
+end for;
+
+
+--ENTITY c01s03b00x00p05n02i00834ent IS
+--END c01s03b00x00p05n02i00834ent;
+--
+--ARCHITECTURE c01s03b00x00p05n02i00834arch OF c01s03b00x00p05n02i00834ent IS
+--
+--BEGIN
+--   TESTING: PROCESS
+--   BEGIN
+--   assert FALSE
+--      report "***FAILED TEST: c01s03b00x00p05n02i00834 - Configuration declaration and corresponding entity declaration must reside in the same library."
+--      severity ERROR;
+--   wait;
+--   END PROCESS TESTING;
+--
+--END c01s03b00x00p05n02i00834arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc835.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc835.vhd
new file mode 100644
index 0000000..1556fbd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc835.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc835.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s03b00x00p06n01i00835ent IS
+END c01s03b00x00p06n01i00835ent;
+
+ARCHITECTURE c01s03b00x00p06n01i00835arch OF c01s03b00x00p06n01i00835ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b00x00p06n01i00835 - Simple name at beginning and end of configuration should be the same."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b00x00p06n01i00835arch;
+
+configuration C of c01s03b00x00p06n01i00835ent is
+  for c01s03b00x00p06n01i00835arch
+    use WORK.all ;
+  end for ;
+end C2;   -- Failure_here
+-- ERROR: name given at the end must be the same as that given beginning.
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc836.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc836.vhd
new file mode 100644
index 0000000..72bc17a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc836.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc836.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s03b01x00p02n01i00836ent IS
+END c01s03b01x00p02n01i00836ent;
+
+ARCHITECTURE c01s03b01x00p02n01i00836arch OF c01s03b01x00p02n01i00836ent IS
+
+BEGIN
+  DE : block
+    signal S1 : BOOLEAN;
+  begin
+    S1 <= true;
+  end block DE;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b01x00p02n01i00836 - Binding indications are not allowed in a configuration of a block." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p02n01i00836arch;
+
+configuration c01s03b01x00p02n01i00836cfg of c01s03b01x00p02n01i00836ent  is
+  for c01s03b01x00p02n01i00836arch
+    for DE use   -- Failure_here : binding indications are not allowed in a
+             -- configuration of a block
+             entity work.entity0 open;
+    end for;
+  end c01s03b01x00p02n01i00836cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc838.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc838.vhd
new file mode 100644
index 0000000..333c79d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc838.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc838.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p02n01i00838ent_a is
+end c01s03b01x00p02n01i00838ent_a;
+
+architecture c01s03b01x00p02n01i00838arch_a of c01s03b01x00p02n01i00838ent_a is
+begin
+  AC_BLK : block
+    signal B : BIT;
+  begin
+    B <= '1';
+  end block;
+end;
+
+ENTITY c01s03b01x00p02n01i00838ent IS
+END c01s03b01x00p02n01i00838ent;
+
+ARCHITECTURE c01s03b01x00p02n01i00838arch OF c01s03b01x00p02n01i00838ent IS
+
+BEGIN
+  A_BLK : block
+    component C
+    end component;
+  begin
+    L1 : C;
+    L2 : C;
+    L3 : C;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b01x00p02n01i00838 - Missing semicolon." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p02n01i00838arch;
+
+configuration c01s03b01x00p02n01i00838cfg of c01s03b01x00p02n01i00838ent  is
+  for c01s03b01x00p02n01i00838arch
+    for A_BLK
+      for L1 : C
+        use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ;
+      end for;
+      
+      for L2 : C
+        use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ;
+      end for;
+      
+      for L3 : C
+        use entity work.c01s03b01x00p02n01i00838ent_a (c01s03b01x00p02n01i00838arch_a) ;
+      end for            --- Failure_here
+    end for;
+  end for;
+end c01s03b01x00p02n01i00838cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc839.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc839.vhd
new file mode 100644
index 0000000..022ec29
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc839.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc839.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p03n01i00839ent_a is
+end c01s03b01x00p03n01i00839ent_a;
+
+architecture c01s03b01x00p03n01i00839arch_a of c01s03b01x00p03n01i00839ent_a is
+begin
+  AC_BLK : block
+    signal B : BIT;
+  begin
+    B <= '1';
+  end block;
+end c01s03b01x00p03n01i00839arch_a;
+
+ENTITY c01s03b01x00p03n01i00839ent IS
+END c01s03b01x00p03n01i00839ent;
+
+ARCHITECTURE c01s03b01x00p03n01i00839arch OF c01s03b01x00p03n01i00839ent IS
+
+BEGIN
+
+  A_BLK : block
+    component C
+    end component;
+  begin
+    L1 : C;
+    L2 : C;
+    L3 : C;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***PASSED TEST: c01s03b01x00p03n01i00839"
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p03n01i00839arch;
+
+configuration c01s03b01x00p03n01i00839cfg of c01s03b01x00p03n01i00839ent is
+  --- Failure_here; Missing architecture name
+  for A_BLK
+    for L1 : C
+      use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
+    end for;
+    
+    for L2 : C
+      use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
+    end for;
+    
+    for L3 : C
+      use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
+    end for;
+
+  end for;
+
+end c01s03b01x00p03n01i00839cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc841.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc841.vhd
new file mode 100644
index 0000000..d81760f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc841.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc841.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p04n01i00841ent_a is
+end c01s03b01x00p04n01i00841ent_a;
+
+architecture c01s03b01x00p04n01i00841arch_a of c01s03b01x00p04n01i00841ent_a is
+begin
+end c01s03b01x00p04n01i00841arch_a;
+
+ENTITY c01s03b01x00p04n01i00841ent IS
+  port (N : integer);
+END c01s03b01x00p04n01i00841ent;
+
+ARCHITECTURE c01s03b01x00p04n01i00841arch OF c01s03b01x00p04n01i00841ent IS
+
+BEGIN
+  
+  AA_BLK : block
+    component FOUR
+    end component;
+  begin
+    LH : FOUR;
+    LR : FOUR;
+    aaa_blk: block
+    begin
+    end block;
+    L1: for I in 1 to 3 generate
+    end generate;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b01x00p04n01i00841 - Index specification is not locally static."
+      severity NOTE;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p04n01i00841arch;
+
+configuration c01s03b01x00p04n01i00841cfg of c01s03b01x00p04n01i00841ent is
+  for c01s03b01x00p04n01i00841arch
+    for AA_BLK
+      for LH, LR : FOUR
+        use entity work.c01s03b01x00p04n01i00841ent_a(c01s03b01x00p04n01i00841_arch_a);
+      end for;
+      for aaa_blk
+      end for;
+      for L1 (1 to N)                 --- No_failure_here
+      end for;
+      for L1 (3)
+      end for;
+    end for;
+  end for;
+end c01s03b01x00p04n01i00841cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc845.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc845.vhd
new file mode 100644
index 0000000..e5285df
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc845.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc845.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b01x00p07n01i00845ent_a is
+end c01s03b01x00p07n01i00845ent_a;
+
+architecture c01s03b01x00p07n01i00845arch_a of c01s03b01x00p07n01i00845ent_a is
+begin
+  AC_BLK : block
+    signal B : BIT;
+  begin
+    B <= '1';
+  end block;
+end;
+
+ENTITY c01s03b01x00p07n01i00845ent IS
+END c01s03b01x00p07n01i00845ent;
+
+ARCHITECTURE c01s03b01x00p07n01i00845arch OF c01s03b01x00p07n01i00845ent IS
+
+BEGIN
+
+  A_BLK : block
+    component C
+    end component;
+  begin
+    L1 : C;
+    L2 : C;
+    L3 : C;
+  end block;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b01x00p07n01i00845 - Block configuration must be an architecture name."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p07n01i00845arch;
+
+configuration c01s03b01x00p07n01i00845cfg of c01s03b01x00p07n01i00845ent  is
+  for PQ                      -- Failure_here
+    for A_BLK
+      for L1 : C
+        use entity work.c01s03b01x00p07n01i00845ent_a (c01s03b01x00p07n01i00845arch_a) ;
+      end for;
+      
+      for L2 : C
+        use entity work.c01s03b01x00p07n01i00845ent_a (c01s03b01x00p07n01i00845arch_a) ;
+      end for;
+      
+      for L3 : C
+        use entity work.c01s03b01x00p07n01i00845ent_a (c01s03b01x00p07n01i00845arch_a) ;
+      end for;
+      
+    end for;
+  end for ;
+end c01s03b01x00p07n01i00845cfg ;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc847.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc847.vhd
new file mode 100644
index 0000000..7c606b9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc847.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc847.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity and2g is
+end and2g;
+
+architecture behavior of and2g is
+begin
+end behavior;
+
+entity full_adder is
+end full_adder;
+
+architecture structural of full_adder is
+  component and2
+  end component;
+begin
+  C1: and2;
+end structural;
+
+ENTITY c01s03b01x00p08n01i00847ent IS
+END c01s03b01x00p08n01i00847ent;
+
+ARCHITECTURE c01s03b01x00p08n01i00847arch OF c01s03b01x00p08n01i00847ent IS
+  
+  component adder
+  end component;
+  
+BEGIN
+  A1 : adder;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b01x00p08n01i00847 - Architecture name in block configuration does not match block specification."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p08n01i00847arch;
+
+
+configuration c01s03b01x00p08n01i00847cfg of c01s03b01x00p08n01i00847ent is
+  for c01s03b01x00p08n01i00847arch
+    for A1: adder use                      -- component configuration
+                    entity work.full_adder(structural);
+                  
+                  for bad_block_spec       -- failure_here
+                    for C1: and2 use
+                                   entity work.and2g(behavior);
+                    end for;
+                  end for;
+    end for;
+  end for;
+end c01s03b01x00p08n01i00847cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc848.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc848.vhd
new file mode 100644
index 0000000..855a833
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc848.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc848.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c01s03b01x00p09n01i00848ent IS
+  port ( PT : Boolean );
+END c01s03b01x00p09n01i00848ent;
+
+ARCHITECTURE c01s03b01x00p09n01i00848arch OF c01s03b01x00p09n01i00848ent IS
+
+BEGIN
+
+  BD : block
+    component comp1
+    end component ;
+  begin
+    CIS : comp1;
+    BD_nested : block
+    begin
+      process
+      begin
+        null;
+        wait;
+      End process;
+    end block;
+  end block BD ;
+
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c01s03b01x00p09n01i00848 - Invalid block specification."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c01s03b01x00p09n01i00848arch;
+
+configuration c01s03b01x00p09n01i00848cfg of c01s03b01x00p09n01i00848ent is
+  for c01s03b01x00p09n01i00848arch
+    for CIS  -- Failure_here
+      -- ERROR: the CIS is not a declared block in the declarative region.
+    end for ;
+    for BD_nested  -- failure_here
+      -- ERROR :: BD_nested is not a block label in the related declarative region.
+    end for;
+  end for;
+end c01s03b01x00p09n01i00848cfg;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc85.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc85.vhd
new file mode 100644
index 0000000..da662f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc85.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc85.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x03p04n01i00085ent IS
+END c04s03b01x03p04n01i00085ent;
+
+ARCHITECTURE c04s03b01x03p04n01i00085arch OF c04s03b01x03p04n01i00085ent IS
+BEGIN
+  TESTING: PROCESS
+    variable k : integer := true;   --Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b01x03p04n01i00085 - Type mismatch in variable declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b01x03p04n01i00085arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc875.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc875.vhd
new file mode 100644
index 0000000..5c59700
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc875.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc875.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+entity c01s03b02x00p02n01i00875ent_a  is
+  port (   ia, ib : bit;
+           oc, od : out bit) ;
+end c01s03b02x00p02n01i00875ent_a;
+
+architecture c01s03b02x00p02n01i00875arch_a of c01s03b02x00p02n01i00875ent_a is
+begin
+  A1_BLK : block
+    signal S : INTEGER;
+  begin
+    S <= 1;
+  end block;
+end c01s03b02x00p02n01i00875arch_a;
+
+ENTITY c01s03b02x00p02n01i00875ent IS
+  port (   P3 : out bit;
+           P4 : out bit) ;
+END c01s03b02x00p02n01i00875ent;
+
+ARCHITECTURE c01s03b02x00p02n01i00875arch OF c01s03b02x00p02n01i00875ent IS
+BEGIN
+  BB : block
+    signal S1 : bit;
+    signal S2 : bit;
+    component LOCAL port(   CI, I2    : in BIT;
+                            CO, RES :out BIT);
+    end component ;
+    
+    for         --- Failure_here
+      use entity work.c01s03b02x00p02n01i00875ent_a (c01s03b02x00p02n01i00875arch_a)
+      port map (ia => CI, ib => I2, oc => CO, od => RES);
+  begin
+    L : LOCAL port map (CI =>S1 , I2 =>S2 , CO=>P3 , RES =>P4 );
+    assert FALSE 
+      report "***FAILED TEST: c01s03b02x00p02n01i00875 - Missing component specification."
+      severity ERROR;
+  end block BB;
+
+END c01s03b02x00p02n01i00875arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc89.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc89.vhd
new file mode 100644
index 0000000..bd77e40
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc89.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc89.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p09n01i00089ent IS
+END c04s03b02x00p09n01i00089ent;
+
+ARCHITECTURE c04s03b02x00p09n01i00089arch OF c04s03b02x00p09n01i00089ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type file_type is file of integer;
+    variable x : file_type ;  -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST:c04s03b02x00p09n01i00089 - A variable may not be declared as a file type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+  ENDc04s03b02x00p09n01i00089arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc899.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc899.vhd
new file mode 100644
index 0000000..4c2b248
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc899.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc899.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p04n01i00899pkg_1 is
+  type    T  is (one,two,three,four);
+  subtype    SS is INTEGER;
+  function    F return REAL;
+end c10s03b00x00p04n01i00899pkg_1;
+
+package body c10s03b00x00p04n01i00899pkg_1 is
+  function F return REAL is
+  begin
+    return 0.0;
+  end F;
+end c10s03b00x00p04n01i00899pkg_1;
+
+package c10s03b00x00p04n01i00899pkg_2 is
+  type    T  is (one,two,three,four);
+  subtype    SS is INTEGER;
+  function    F return REAL;
+end c10s03b00x00p04n01i00899pkg_2;
+
+package body c10s03b00x00p04n01i00899pkg_2 is
+  function F return REAL is
+  begin
+    return 0.0;
+  end F;
+end c10s03b00x00p04n01i00899pkg_2;
+
+use work.c10s03b00x00p04n01i00899pkg_1.all,work.c10s03b00x00p04n01i00899_pkg_2.all;
+ENTITY c10s03b00x00p04n01i00899ent IS
+  port (P:BOOLEAN) ;
+  
+  subtype S2 is SS;  -- Failure_here
+  -- SEMANTIC ERROR:  ambiguous reference to subtype SS
+  
+  type R is range F to F;  -- Failure_here
+  -- SEMANTIC ERROR:  ambiguous reference to function F
+END c10s03b00x00p04n01i00899ent;
+
+ARCHITECTURE c10s03b00x00p04n01i00899arch OF c10s03b00x00p04n01i00899ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T;  -- Failure_here
+    -- SEMANTIC ERROR:  ambiguous reference to type T
+    
+    variable V2 : SS;  -- Failure_here
+    -- SEMANTIC ERROR:  ambiguous reference to subtype SS
+  BEGIN
+    V1 := one;  -- Failure_here
+    -- SEMANTIC ERROR:  ambiguous reference to literal "one"
+    assert FALSE
+      report "***FAILED TEST: c10s03b00x00p04n01i00899 - Ambiguous references not permitted."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p04n01i00899arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc9.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc9.vhd
new file mode 100644
index 0000000..7912c26
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc9.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc9.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s01b00x00p08n01i00009ent IS
+END c04s01b00x00p08n01i00009ent;
+
+ARCHITECTURE c04s01b00x00p08n01i00009arch OF c04s01b00x00p08n01i00009ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE: BOOLEAN;
+               end record;
+    type R2 is record
+                 RE: BOOLEAN;
+               end record;
+    
+    variable V9: R1;
+    variable V10: R2;
+  BEGIN
+    if V9 = V10 then  -- Failure_here
+      -- ERROR - SEMANTIC ERROR: OPERANDS OF = INCOMPATIBLE IN TYPE
+      null ;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c04s01b00x00p08n01i00009 - Types are different and hence incompatible."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s01b00x00p08n01i00009arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc901.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc901.vhd
new file mode 100644
index 0000000..97c3105
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc901.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc901.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p05n01i00901ent IS
+  type AR is array (1 to 10) of AR;     -- Failure_here
+  -- entity is not visible until end of declaration
+END c10s03b00x00p05n01i00901ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00901arch OF c10s03b00x00p05n01i00901ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c10s03b00x00p05n01i00901 - Declaration is not visible until the end of the declaration.
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00901arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc903.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc903.vhd
new file mode 100644
index 0000000..347fd5d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc903.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc903.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p05n01i00903ent IS
+  type R is record
+              A : R;     -- Failure_here
+              -- entity is not visible until end of declaration
+            end record;
+END c10s03b00x00p05n01i00903ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00903arch OF c10s03b00x00p05n01i00903ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c10s03b00x00p05n01i00903 - Declaration is not visible until the end of the declaration.
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00903arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc904.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc904.vhd
new file mode 100644
index 0000000..af96a4d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc904.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc904.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p05n01i00904ent IS
+  subtype Q is INTEGER range Q'(3) to Q'(7);     -- Failure_here
+  -- entity is not visible until end of declaration
+END c10s03b00x00p05n01i00904ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00904arch OF c10s03b00x00p05n01i00904ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c10s03b00x00p05n01i00904 - Declaration is not visible until the end of the declaration.
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00904arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc905.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc905.vhd
new file mode 100644
index 0000000..81f4a70
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc905.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc905.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p05n01i00905ent IS
+  constant C : INTEGER := C;     -- Failure_here
+  -- entity is not visible until end of declaration
+END c10s03b00x00p05n01i00905ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00905arch OF c10s03b00x00p05n01i00905ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c10s03b00x00p05n01i00905 - Declaration is not visible until the end of the declaration.
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00905arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc906.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc906.vhd
new file mode 100644
index 0000000..d7e5f85
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc906.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc906.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p05n01i00906ent IS
+  function F(A : INTEGER := F(1)) return INTEGER is  -- Failure_here
+    -- entity is not visible until after reserved word IS.
+  begin
+    return 5;
+  end F;
+END c10s03b00x00p05n01i00906ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00906arch OF c10s03b00x00p05n01i00906ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c10s03b00x00p05n01i00906 - Declaration is not visible until the end of the declaration.
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00906arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc907.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc907.vhd
new file mode 100644
index 0000000..31459f1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc907.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc907.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p05n01i00907pkg is
+  function FA ( B : INTEGER ) return INTEGER;
+  function FB ( B : INTEGER ) return INTEGER;
+end c10s03b00x00p05n01i00907pkg;
+
+package body c10s03b00x00p05n01i00907pkg is
+  function FA ( B : INTEGER ) return INTEGER is
+    constant C : INTEGER := 6;
+  begin
+    return B;
+  end FA;
+  
+  function FB ( B : INTEGER ) return INTEGER is
+  begin
+    return C; -- Failure_here
+    -- error: entity not within the region it is immediately declared
+  end FB;
+end c10s03b00x00p05n01i00907pkg;
+
+
+ENTITY c10s03b00x00p05n01i00907ent IS
+END c10s03b00x00p05n01i00907ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00907arch OF c10s03b00x00p05n01i00907ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c10s03b00x00p05n01i00907 - Entity is not within the region it is immediately declared in."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00907arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc908.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc908.vhd
new file mode 100644
index 0000000..f4fb8b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc908.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc908.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s03b00x00p05n01i00908pkg is
+  function FA ( B : INTEGER ) return INTEGER;
+  function FB ( B : INTEGER ) return INTEGER;
+end c10s03b00x00p05n01i00908pkg;
+
+package body c10s03b00x00p05n01i00908pkg is
+  function FA ( B : INTEGER ) return INTEGER is
+    constant C : INTEGER := 6;
+  begin
+    return B;
+  end FA;
+  
+  function FB ( B : INTEGER ) return INTEGER is
+  begin
+    return C; -- Failure_here
+    -- error: entity not within the region it is immediately declared
+  end FB;
+end c10s03b00x00p05n01i00908pkg;
+
+use work.c10s03b00x00p05n01i00908pkg.all;
+ENTITY c10s03b00x00p05n01i00908ent IS
+END c10s03b00x00p05n01i00908ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00908arch OF c10s03b00x00p05n01i00908ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant D : integer := C;   --Failure_here
+    --Entity not within the region it is immediately declared.
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c10s03b00x00p05n01i00908 - Entity is not within the region it is immediately declared in."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00908arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc909.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc909.vhd
new file mode 100644
index 0000000..2d50624
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc909.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc909.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p05n01i00909ent IS
+END c10s03b00x00p05n01i00909ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00909arch OF c10s03b00x00p05n01i00909ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable QQ : INTEGER;
+  BEGIN
+    for I in 1 to 30 loop
+      null;
+    end loop;
+    QQ := I;     -- Failure_here
+    -- error: entity not within the region it is immediately declared
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c10s03b00x00p05n01i00909- Entity is not within the region it is immediately declared in."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00909arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc910.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc910.vhd
new file mode 100644
index 0000000..af66fa5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc910.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc910.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s03b00x00p05n01i00910ent IS
+END c10s03b00x00p05n01i00910ent;
+
+ARCHITECTURE c10s03b00x00p05n01i00910arch OF c10s03b00x00p05n01i00910ent IS
+
+BEGIN
+
+  B2:block
+    type A is (A1, A2, A3);
+    signal S : A;
+  begin
+    S <= A1;
+  end block B2;
+  
+  B3:block
+    signal S1 : A; -- Failure_here
+    -- error: entity not within the region it is immediately declared
+  begin
+    S1 <= A1;   -- Failure_here
+    -- error: entity nor within the region it is immediately declated
+  end block B3;
+
+  TESTING: PROCESS
+  BEGIN
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: /c10s03b00x00p05n01i00910 - Entity is not within the region it is immediately declared in."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s03b00x00p05n01i00910arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc92.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc92.vhd
new file mode 100644
index 0000000..53eae3d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc92.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc92.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p03n01i00092ent IS
+END c04s03b02x00p03n01i00092ent;
+
+ARCHITECTURE c04s03b02x00p03n01i00092arch OF c04s03b02x00p03n01i00092ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function exp_type_check (constant x : out integer := 3) -- Failure_here
+      return integer is
+    begin
+      return x;
+    end;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p03n01i00092- A constant of mode out cannot be declared in a constant interface declaration."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p03n01i00092arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc928.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc928.vhd
new file mode 100644
index 0000000..0bf0b12
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc928.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc928.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p01n01i00928pkg is
+  -- It is OK to define a type that overrides the name of a library
+  type work is (foo, bar);   -- No_failure_here
+end c10s04b00x00p01n01i00928pkg;
+
+use  work.c10s04b00x00p01n01i00928pkg.all;
+ENTITY c10s04b00x00p01n01i00928ent IS
+  port (P : in  bit);
+END c10s04b00x00p01n01i00928ent;
+
+ARCHITECTURE c10s04b00x00p01n01i00928arch OF c10s04b00x00p01n01i00928ent IS
+
+BEGIN
+  TESTING: PROCESS(P)
+    -- This is an error because the type work defined in work.c10s04b00x00p01n01i00928pkg is
+    -- NOT directly visible, it is overridden by library "work"
+    variable doit : work ;    -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c10s04b00x00p01n01i00928 - Type definition for 'work' does not exist in scope of declaration region for architecture 'blow2' of 'E'."
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c10s04b00x00p01n01i00928arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc929.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc929.vhd
new file mode 100644
index 0000000..4b94975
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc929.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc929.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p01n01i00929pkg is
+  type p2 is (a, b);
+end c10s04b00x00p01n01i00929pkg;
+
+use work.all;
+ENTITY c10s04b00x00p01n01i00929ent IS
+END c10s04b00x00p01n01i00929ent;
+
+ARCHITECTURE c10s04b00x00p01n01i00929arch OF c10s04b00x00p01n01i00929ent IS
+  signal s: p2;   -- Failure_here
+  -- should report an error as the type p2 is not visible.
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c10s04b00x00p01n01i00929 - Type definition does not exist in scope of declaration region for architecture." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s04b00x00p01n01i00929arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc93.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc93.vhd
new file mode 100644
index 0000000..08dc147
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc93.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc93.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p08n01i00093ent IS
+END c04s03b02x00p08n01i00093ent;
+
+ARCHITECTURE c04s03b02x00p08n01i00093arch OF c04s03b02x00p08n01i00093ent IS
+
+  procedure proc1 (x1 : integer; y1 :real; z1 : boolean) is
+    variable x12 : integer;
+    variable z12 : boolean;
+  begin
+    x12    := 12;
+    z12    := (x1 < 2);
+    z1     := z12;
+    y1    := y1 - 1.0;
+    x1    := x12;
+  end proc1;
+  
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p08n01i00093 - Object of mode in may not be updated."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p08n01i00093arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc937.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc937.vhd
new file mode 100644
index 0000000..b78ee9b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc937.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc937.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s04b00x00p06n01i00937pkg_a is
+  type MC is (LOW,HIGH,RISING);
+end c10s04b00x00p06n01i00937pkg_a;
+
+package c10s04b00x00p06n01i00937pkg is
+  function MC return boolean;
+end c10s04b00x00p06n01i00937pkg;
+
+package body c10s04b00x00p06n01i00937pkg is
+  function MC return boolean is
+  begin
+    return false;
+  end;
+end c10s04b00x00p06n01i00937pkg;
+
+use work.c10s04b00x00p06n01i00937pkg_a.all,work.c10s04b00x00p06n01i00937pkg.all;
+ENTITY c10s04b00x00p06n01i00937ent IS
+END c10s04b00x00p06n01i00937ent;
+
+ARCHITECTURE c10s04b00x00p06n01i00937arch OF c10s04b00x00p06n01i00937ent IS
+
+BEGIN
+  TESTING : PROCESS
+    variable S1: MC;     -- Failure_here.
+  BEGIN
+    S1 := Low;
+    assert FALSE 
+      report "***FAILED TEST: c10s04b00x00p06n01i00937 - Ambiguity in usage of potentially visible declarations." 
+      severity ERROR;
+    wait;
+  END PROCESS;
+
+END c10s04b00x00p06n01i00937arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc939.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc939.vhd
new file mode 100644
index 0000000..9166dad
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc939.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc939.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c10s05b00x00p01n01i00939ent IS
+  port (PT:BOOLEAN) ;
+
+  type BITT is ('0','1');
+
+  type DBIT is ('0','1','x');         -- '0' and '1' are overloaded
+
+  attribute AT1 : BITT;
+
+  attribute AT1 : DBIT;  -- Failure_here
+  -- ERROR : Attribute AT1 is overloaded.
+
+  attribute AT1 :  INTEGER;  -- Failure_here
+  -- ERROR : Attribute AT1 is overloaded.
+END c10s05b00x00p01n01i00939ent;
+
+ARCHITECTURE c10s05b00x00p01n01i00939arch OF c10s05b00x00p01n01i00939ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+
+    assert FALSE 
+      report "***FAILED TEST: c10s05b00x00p01n01i00939 - Attributes cannot be overloaded."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s05b00x00p01n01i00939arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc94.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc94.vhd
new file mode 100644
index 0000000..cc7f9d2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc94.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc94.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x00p09n01i00094pkg is
+  type FT is file of integer;
+end c04s03b02x00p09n01i00094pkg;
+
+use work.c04s03b02x00p09n01i00094pkg.all;
+ENTITY c04s03b02x00p09n01i00094ent IS
+  generic ( A1 : FT );
+END c04s03b02x00p09n01i00094ent;
+
+ARCHITECTURE c04s03b02x00p09n01i00094arch OF c04s03b02x00p09n01i00094ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p09n01i00094 - The subtype indication for an interface constant or signal declaration can not be of file type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p09n01i00094arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc941.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc941.vhd
new file mode 100644
index 0000000..446406b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc941.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc941.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c10s05b00x00p03n02i00941pkg1 is
+  type COLOR is (RED,YELLOW,GREEN,BROWN,TAN,WHITE,BLUE);
+end c10s05b00x00p03n02i00941pkg1;
+
+package c10s05b00x00p03n02i00941pkg2 is
+  type LIGHTS is (RED,YELLOW,GREEN,BROWN,TAN,WHITE,BLUE);
+end c10s05b00x00p03n02i00941pkg2;
+
+use work.c10s05b00x00p03n02i00941pkg1.all, work c10s05b00x00p03n02i00941pkg2.all;
+ENTITY c10s05b00x00p03n02i00941ent IS
+END c10s05b00x00p03n02i00941ent;
+
+ARCHITECTURE c10s05b00x00p03n02i00941arch OF c10s05b00x00p03n02i00941ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    if RED > BLUE then  -- Failure_here
+      --ERROR: type cannot be determined from context
+    else
+      case TRUE is
+        when (TAN = TAN) => null;  -- Failure_here
+        --ERROR: type cannot be determined from context
+        when others  => null; -- Failure_here
+      end case;
+    end if;
+    assert FALSE 
+      report "***FAILED TEST: c10s05b00x00p03n02i00941 - Multiple interpretations of constituents of the innermost complete context are not allowed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c10s05b00x00p03n02i00941arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc944.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc944.vhd
new file mode 100644
index 0000000..db4b36a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc944.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc944.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p09n01i00944ent IS
+END c06s01b00x00p09n01i00944ent;
+
+ARCHITECTURE c06s01b00x00p09n01i00944arch OF c06s01b00x00p09n01i00944ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant T: time := 'a'.foo;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s01b00x00p09n01i00944 - Prefix can only be a name or a function_call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p09n01i00944arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc946.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc946.vhd
new file mode 100644
index 0000000..0c446ae
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc946.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc946.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00946ent IS
+END c06s01b00x00p10n01i00946ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00946arch OF c06s01b00x00p10n01i00946ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := (RE1=>TRUE).RE1;
+    -- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s01b00x00p10n01i00946 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00946arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc947.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc947.vhd
new file mode 100644
index 0000000..1ba2e72
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc947.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc947.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00947ent IS
+END c06s01b00x00p10n01i00947ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00947arch OF c06s01b00x00p10n01i00947ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := R1'(RE1=>TRUE).RE1;
+    -- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s01b00x00p10n01i00947 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00947arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc948.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc948.vhd
new file mode 100644
index 0000000..8283b13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc948.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc948.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00948ent IS
+END c06s01b00x00p10n01i00948ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00948arch OF c06s01b00x00p10n01i00948ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+    type R2 is record
+                 RE2: R1;
+               end record;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := R2'(RE2=>R1'(RE1=>TRUE)).RE2.RE1;
+    -- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s01b00x00p10n01i00948 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00948arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc949.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc949.vhd
new file mode 100644
index 0000000..90e0cd7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc949.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc949.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00949ent IS
+END c06s01b00x00p10n01i00949ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00949arch OF c06s01b00x00p10n01i00949ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 2) of BOOLEAN;
+    type R3 is record
+                 RE3: A1;
+               end record;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := (RE3=>(1=>TRUE,2=>TRUE)).RE3(1);
+    -- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s01b00x00p10n01i00949 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00949arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc95.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc95.vhd
new file mode 100644
index 0000000..8ad8b15
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc95.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc95.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c04s03b02x00p09n01i00095pkg is
+  type rec is record
+                ele1: integer;
+                ele2: integer;
+              end record;
+  type at is access rec;
+end c04s03b02x00p09n01i00095pkg;
+
+use work.c04s03b02x00p09n01i00095pkg.all;
+ENTITY c04s03b02x00p09n01i00095ent IS
+  generic ( A2 : at );
+END c04s03b02x00p09n01i00095ent;
+
+ARCHITECTURE c04s03b02x00p09n01i00095arch OF c04s03b02x00p09n01i00095ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p09n01i00095 - The subtype indication for an interface constant or signal declaration can not be of access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p09n01i00095arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc950.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc950.vhd
new file mode 100644
index 0000000..7f1ca5b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc950.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc950.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p10n01i00950ent IS
+END c06s01b00x00p10n01i00950ent;
+
+ARCHITECTURE c06s01b00x00p10n01i00950arch OF c06s01b00x00p10n01i00950ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (1 to 2) of BOOLEAN;
+    type R3 is record
+                 RE3: A1;
+               end record;
+    variable V1: BOOLEAN;
+  BEGIN
+    V1 := (RE3=>(1=>TRUE,2=>TRUE)).RE3(1);
+    -- SYNTAX ERROR: PREFIX OF SELECTED NAME CANNOT BE AN AGGREGATE
+    assert FALSE 
+      report "***FAILED TEST: c06s01b00x00p10n01i00950 - Prefix of a selected name cannot be an aggregate."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p10n01i00950arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc957.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc957.vhd
new file mode 100644
index 0000000..389486e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc957.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc957.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s01b00x00p11n01i00957ent IS
+END c06s01b00x00p11n01i00957ent;
+
+ARCHITECTURE c06s01b00x00p11n01i00957arch OF c06s01b00x00p11n01i00957ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type z is
+      record
+        y   : integer;
+        p,q : boolean;
+      end record;
+    type ptrtype is access z;
+    procedure P ( x : out Ptrtype) is
+    begin
+      x.y := 1;         -- The prefix is of access type of which
+      -- denotes a formal parameter of mode
+    end;
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s01b00x00p11n01i00957 - Prefix of a name cannot be a formal parameter of mode out if the prefix is an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s01b00x00p11n01i00957arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc959.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc959.vhd
new file mode 100644
index 0000000..968c454
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc959.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc959.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p02n01i00959ent IS
+END c06s03b00x00p02n01i00959ent;
+
+ARCHITECTURE c06s03b00x00p02n01i00959arch OF c06s03b00x00p02n01i00959ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T1 is record
+                 S1 : Bit ;
+                 S2 : Integer;
+               end record;
+    type T2 is record
+                 S11 : BIT ;
+                 S12 : T1 ;
+               end record;
+    variable V1 : T2 ;
+  BEGIN
+    V1.S12S2 := 10 ;  -- Failure_here
+    wait for 100 ns;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p02n01i00959 - Missing dot."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p02n01i00959arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc96.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc96.vhd
new file mode 100644
index 0000000..0059c14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc96.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc96.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p12n02i00096ent IS
+  generic ( constant c1 : in integer := true );-- Failure_here
+END c04s03b02x00p12n02i00096ent;
+
+ARCHITECTURE c04s03b02x00p12n02i00096arch OF c04s03b02x00p12n02i00096ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p12n02i00096 - The type of the default object is not the same as the corresponding interface element."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p12n02i00096arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc960.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc960.vhd
new file mode 100644
index 0000000..6d2284d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc960.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc960.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p02n01i00960ent IS
+END c06s03b00x00p02n01i00960ent;
+
+ARCHITECTURE c06s03b00x00p02n01i00960arch OF c06s03b00x00p02n01i00960ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T1 is record
+                 S1 : Bit ;
+                 S2 : Integer;
+               end record;
+    type T2 is record
+                 S11 : BIT ;
+                 S12 : T1 ;
+               end record;
+    variable V1 : T2 ;
+  BEGIN
+    V1.S2 := 10 ;  -- Failure_here
+    wait for 100 ns;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p02n01i00960 - Missing prefix."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p02n01i00960arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc961.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc961.vhd
new file mode 100644
index 0000000..1db40b5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc961.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc961.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p02n01i00961ent IS
+END c06s03b00x00p02n01i00961ent;
+
+ARCHITECTURE c06s03b00x00p02n01i00961arch OF c06s03b00x00p02n01i00961ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T1 is record
+                 S1 : Bit ;
+                 S2 : Integer;
+               end record;
+    type T2 is record
+                 S11 : BIT ;
+                 S12 : T1 ;
+               end record;
+    variable V1 : T2 ;
+  BEGIN
+    V1.S12 := 10 ;  -- Failure_here
+    wait for 100 ns;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p02n01i00961 - Missing suffix."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p02n01i00961arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc963.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc963.vhd
new file mode 100644
index 0000000..4517065
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc963.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc963.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p04n01i00963ent IS
+END c06s03b00x00p04n01i00963ent;
+
+ARCHITECTURE c06s03b00x00p04n01i00963arch OF c06s03b00x00p04n01i00963ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant T: time := boolean.foo;  -- Failure_here
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p04n01i00963 - Selected name doesn't denote an entity."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p04n01i00963arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc967.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc967.vhd
new file mode 100644
index 0000000..a01cf97
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc967.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc967.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00967ent IS
+END c06s03b00x00p05n01i00967ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00967arch OF c06s03b00x00p05n01i00967ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type rec_type is
+      record
+        x : bit;
+        y : integer;
+        z : boolean;
+      end record;
+    variable S1, S2 :rec_type;
+    variable h      :bit;
+  BEGIN
+    S1.h := '1' ; -- h is not a field of the record.
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00967 - Suffix should denote an element of a record object or value."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00967arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc97.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc97.vhd
new file mode 100644
index 0000000..2e3ec56
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc97.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc97.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b02x00p29n02i00097ent IS
+END c04s03b02x00p29n02i00097ent;
+
+ARCHITECTURE c04s03b02x00p29n02i00097arch OF c04s03b02x00p29n02i00097ent IS
+  signal P1 : BIT := '1' ;
+  signal P2 : BIT;
+BEGIN
+  TESTING: PROCESS
+    procedure read_write(signal S1 : in BIT; signal S2 : out BIT) is
+    begin
+      if (S1 = '1' and not S1'STABLE) then
+        S2 <= '1' after 10 ns;
+      end if;
+    end;
+  BEGIN
+    read_write(P1, P2);
+    assert FALSE 
+      report "***FAILED TEST: c04s03b02x00p29n02i00097 - Attribute STABLE can not be read."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c04s03b02x00p29n02i00097arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc970.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc970.vhd
new file mode 100644
index 0000000..18ad860
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc970.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc970.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00970ent IS
+END c06s03b00x00p05n01i00970ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00970arch OF c06s03b00x00p05n01i00970ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type x is
+      record
+        y : integer;
+        z : boolean;
+      end record;
+    type a is
+      record
+        b : real;
+        c : integer;
+      end record;
+    variable r : a;
+    variable p : x;
+  BEGIN
+    p.b := 1;   -- the prefix is not of an appropriate type as the 'p' does
+    a.y := 1;   -- not have field 'b' and 'a' does not have field 'y'.   
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00970 - Prefix is not apropraite for the type of the suffix." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00970arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc971.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc971.vhd
new file mode 100644
index 0000000..b1c2de9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc971.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc971.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00971ent IS
+END c06s03b00x00p05n01i00971ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00971arch OF c06s03b00x00p05n01i00971ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+                 RE2: INTEGER;
+                 RE3: BIT;
+                 RE4: SEVERITY_LEVEL;
+                 RE5: REAL;
+                 RE6: CHARACTER;
+                 RE7: TIME; 
+               end record;
+    variable V1: BOOLEAN;
+    variable V2: INTEGER;
+    variable V3: BIT;
+    variable V4: SEVERITY_LEVEL;
+    variable V5: REAL;
+    variable V6: CHARACTER;
+    variable V7: TIME;
+  BEGIN
+    V1 := RE1;
+    V2 := RE2;
+    V3 := RE3;
+    V4 := RE4;
+    V5 := RE5;
+    V6 := RE6;
+    V7 := RE7;
+    -- ERROR: RECORD ELEMENT NAME CANNOT BE USED BY ITSELF
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00971 - Record element name cannot be used by itself as an expression." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00971arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc972.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc972.vhd
new file mode 100644
index 0000000..06c2ea3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc972.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc972.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00972ent IS
+END c06s03b00x00p05n01i00972ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00972arch OF c06s03b00x00p05n01i00972ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+                 RE2: INTEGER;
+                 RE3: BIT;
+                 RE4: SEVERITY_LEVEL;
+                 RE5: REAL;
+                 RE6: CHARACTER;
+                 RE7: TIME;
+               end record;
+    variable V2 : R1;
+  BEGIN
+    V2.RE1 := RE1;
+    V2.RE2 := RE2;
+    V2.RE3 := RE3;
+    V2.RE4 := RE4;
+    V2.RE5 := RE5;
+    V2.RE6 := RE6;
+    V2.RE7 := RE7;
+    -- ERROR: RECORD ELEMENT NAME CANNOT BE USED BY ITSELF
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00972 - Record element name cannot be used by itself." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00972arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc974.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc974.vhd
new file mode 100644
index 0000000..b0da0d9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc974.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc974.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00974ent IS
+END c06s03b00x00p05n01i00974ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00974arch OF c06s03b00x00p05n01i00974ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+
+    variable V1: R1 ;
+    variable V10: BOOLEAN;
+
+  BEGIN
+    V10 := V1.BOOLEAN;
+    -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00974 - Illegal record element name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00974arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc975.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc975.vhd
new file mode 100644
index 0000000..949b75c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc975.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc975.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00975ent IS
+END c06s03b00x00p05n01i00975ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00975arch OF c06s03b00x00p05n01i00975ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+    type R2 is record
+                 RE2: BOOLEAN;
+               end record;
+    type ONE is range 1 to 1;
+    type A1 is array (ONE) of BOOLEAN;
+
+    variable V1: R1 ;
+    variable V2: R2 ;
+    variable V5: A1 ;
+    variable V10: BOOLEAN;
+  BEGIN
+    V10 := V5.ONE;
+    -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00975 - Illegal record element name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00975arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc976.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc976.vhd
new file mode 100644
index 0000000..e32bbe6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc976.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc976.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00976ent IS
+END c06s03b00x00p05n01i00976ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00976arch OF c06s03b00x00p05n01i00976ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+
+    variable V1: R1 ;
+    constant V3: BOOLEAN := TRUE;
+    variable V10: BOOLEAN;
+  BEGIN
+    V10 := V1.V3;
+    -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00976 - Illegal record element name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00976arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc977.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc977.vhd
new file mode 100644
index 0000000..c4f2bb0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc977.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc977.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00977ent IS
+END c06s03b00x00p05n01i00977ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00977arch OF c06s03b00x00p05n01i00977ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+    type R2 is record
+                 RE2: BOOLEAN;
+               end record;
+    type ONE is range 1 to 1;
+
+    variable V1: R1 ;
+    variable V2: R2 ;
+    variable V10: BOOLEAN;
+
+  BEGIN
+    V10 := V1.RE2;
+    -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00977 - Illegal record element name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00977arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc978.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc978.vhd
new file mode 100644
index 0000000..f24c00e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc978.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc978.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00978ent IS
+END c06s03b00x00p05n01i00978ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00978arch OF c06s03b00x00p05n01i00978ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+    type R2 is record
+                 RE2: BOOLEAN;
+               end record;
+
+    variable V2: R2 ;
+    variable V10: BOOLEAN;
+
+  BEGIN
+    V10 := V2.RE1;
+    -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00978 - Illegal record element name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00978arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc979.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc979.vhd
new file mode 100644
index 0000000..24a0123
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc979.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc979.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00979ent IS
+END c06s03b00x00p05n01i00979ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00979arch OF c06s03b00x00p05n01i00979ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+    type R2 is record
+                 RE2: BOOLEAN;
+               end record;
+
+    function F1 return R1 is
+    begin
+      return (RE1=>TRUE);
+    end F1;
+
+    variable V1: R1 ;
+    variable V2: R2 ;
+    variable V10: BOOLEAN;
+  BEGIN
+    V10 := F1.RE2;
+    -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00979 - Illegal record element name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00979arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc980.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc980.vhd
new file mode 100644
index 0000000..8c26da1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc980.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc980.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00980ent IS
+END c06s03b00x00p05n01i00980ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00980arch OF c06s03b00x00p05n01i00980ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+    type R2 is record
+                 RE2: BOOLEAN;
+               end record;
+    function F2 return R2 is
+    begin
+      return (RE2=>TRUE);
+    end F2;
+
+    variable V1: R1 ;
+    variable V10: BOOLEAN;
+
+  BEGIN
+    V10 := F2.RE1;
+    -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00980 - Illegal record element name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00980arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc981.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc981.vhd
new file mode 100644
index 0000000..c619b6f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc981.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc981.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00981ent IS
+END c06s03b00x00p05n01i00981ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00981arch OF c06s03b00x00p05n01i00981ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type R1 is record
+                 RE1: BOOLEAN;
+               end record;
+    type R2 is record
+                 RE2: BOOLEAN;
+               end record;
+
+    variable V1: R1 ;
+    variable V10: BOOLEAN;
+  BEGIN
+    V10 := V1.TRUE;
+    -- SEMANTIC ERROR: NO SUCH RECORD ELEMENT;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00981 - Illegal record element name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00981arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc982.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc982.vhd
new file mode 100644
index 0000000..7693330
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc982.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc982.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p05n01i00982ent IS
+  port (signal a,b : in integer; c,d : out integer);
+END c06s03b00x00p05n01i00982ent;
+
+ARCHITECTURE c06s03b00x00p05n01i00982arch OF c06s03b00x00p05n01i00982ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type some_record is
+      record
+        x1,x2,x3,x4,x5,x6,x7,x8 : integer;
+        y : boolean;
+      end record;
+
+    variable rec1,rec2,rec3 : some_record;
+  BEGIN
+    rec1.x5 := 5;
+    rec1.x7 := a;
+    rec1.y := true;
+
+    WAIT for 1 ns;
+    rec2 := rec1.all;
+    WAIT for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p05n01i00982 - Illegal record selected name." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p05n01i00982arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc984.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc984.vhd
new file mode 100644
index 0000000..56a245b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc984.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc984.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p06n01i00984ent IS
+END c06s03b00x00p06n01i00984ent;
+
+ARCHITECTURE c06s03b00x00p06n01i00984arch OF c06s03b00x00p06n01i00984ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type some_record is
+      record
+        x : integer;
+        y : boolean;
+      end record;
+
+    type some_ptr is access some_record;
+
+    variable some_var : some_ptr;
+    variable some_rec : some_record;
+  BEGIN
+    some_rec := some_var; --  should be some_rec := some_var.all
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p06n01i00984 - Suffix of a selected name must be the reserved word all." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p06n01i00984arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc985.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc985.vhd
new file mode 100644
index 0000000..e7385c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc985.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc985.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p06n01i00985ent IS
+END c06s03b00x00p06n01i00985ent;
+
+ARCHITECTURE c06s03b00x00p06n01i00985arch OF c06s03b00x00p06n01i00985ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type T is
+      record
+        a:integer;
+        b:integer;
+      end record;
+    type A is access T;
+    variable B1, B2: A := new T'(0, 0);
+    variable C : T;
+  BEGIN
+    C  := B1.all;
+    B1.all := C.all;        -- C.all is illegal
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p06n01i00985 - Prefix of a selected name used to denote an object designated by an access value should be an access type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p06n01i00985arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc989.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc989.vhd
new file mode 100644
index 0000000..f2af0af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc989.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc989.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p07n02i00989pkg is
+  function prefix_check return string;
+end c06s03b00x00p07n02i00989pkg;
+
+package body c06s03b00x00p07n02i00989pkg is
+  use prefix_check.all;       -- not allowed.
+end c06s03b00x00p07n02i00989pkg;
+
+ENTITY c06s03b00x00p07n02i00989ent IS
+END c06s03b00x00p07n02i00989ent;
+
+ARCHITECTURE c06s03b00x00p07n02i00989arch OF c06s03b00x00p07n02i00989ent IS
+
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p07n02i00989 - Prefix of an expanded name may not be a function call.(Expanded name used in use clause)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p07n02i00989arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc990.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc990.vhd
new file mode 100644
index 0000000..8bc0e27
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc990.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc990.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p07n02i00990ent IS
+END c06s03b00x00p07n02i00990ent;
+
+ARCHITECTURE c06s03b00x00p07n02i00990arch OF c06s03b00x00p07n02i00990ent IS
+
+BEGIN
+  TESTING: PROCESS
+    function F return BOOLEAN is
+    begin
+      return TRUE;
+    end F;
+    variable B1 : BOOLEAN;
+    variable V1 : BOOLEAN;
+  BEGIN
+    V1 := F.B1;         -- ERROR: the prefix of an expanded name
+    -- cannot be a function call.
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p07n02i00990 - The prefix of an expanded name cannot be a function call.(Expanded name used as expression)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p07n02i00990arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc991.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc991.vhd
new file mode 100644
index 0000000..0aa8663
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc991.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc991.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p07n02i00991ent IS
+END c06s03b00x00p07n02i00991ent;
+
+ARCHITECTURE c06s03b00x00p07n02i00991arch OF c06s03b00x00p07n02i00991ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type A1 is array (BOOLEAN) of BOOLEAN;
+    function F return BOOLEAN is
+    begin
+      return TRUE;
+    end F;
+    variable B1 : BOOLEAN;
+    variable V1 : BOOLEAN;
+    variable V2 : A1 ;
+  BEGIN
+    V2 := V2(F.B1);     -- ERROR: the prefix of an expanded name
+    -- cannot be a functon call.
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p07n02i00991 - The prefix of an expanded name cannot be a function call.(Expanded name used as array index)"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p07n02i00991arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc994.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc994.vhd
new file mode 100644
index 0000000..8ffe79c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc994.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc994.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s03b00x00p08n03i00994ent IS
+END c06s03b00x00p08n03i00994ent;
+architecture a19a of c06s03b00x00p08n03i00994ent is
+begin
+end;
+
+ARCHITECTURE c06s03b00x00p08n03i00994arch OF c06s03b00x00p08n03i00994ent IS
+  use work.a19a;   --illegal
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p08n03i00994 - Expanded name is not allowed for an architectural body."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p08n03i00994arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc997.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc997.vhd
new file mode 100644
index 0000000..c56eb8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc997.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc997.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i00997pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i00997pkg;
+
+use work.c06s03b00x00p09n01i00997pkg.all;
+ENTITY c06s03b00x00p09n01i00997ent IS
+END c06s03b00x00p09n01i00997ent;
+
+ARCHITECTURE c06s03b00x00p09n01i00997arch OF c06s03b00x00p09n01i00997ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST1 is Q.TWO (1 to 1);
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i00997 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i00997arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc998.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc998.vhd
new file mode 100644
index 0000000..e7c4103
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc998.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc998.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i00998pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i00998pkg;
+
+use work.c06s03b00x00p09n01i00998pkg.all;
+ENTITY c06s03b00x00p09n01i00998ent IS
+END c06s03b00x00p09n01i00998ent;
+
+ARCHITECTURE c06s03b00x00p09n01i00998arch OF c06s03b00x00p09n01i00998ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST2 is c06s03b00x00p09n01i00998ent.TWO (1 to 1);
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i00998 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i00998arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc999.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc999.vhd
new file mode 100644
index 0000000..11aa5ac
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc999.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc999.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c06s03b00x00p09n01i00999pkg is
+  type TWO is range 1 to 2;
+end c06s03b00x00p09n01i00999pkg;
+
+use work.c06s03b00x00p09n01i00999pkg.all;
+ENTITY c06s03b00x00p09n01i00999ent IS
+END c06s03b00x00p09n01i00999ent;
+
+ARCHITECTURE c06s03b00x00p09n01i00999arch OF c06s03b00x00p09n01i00999ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype ST3 is c06s03b00x00p09n01i00999pkg.c06s03b00x00p09n01i00999ent.TWO (1 to 1);
+    -- SEMANTIC ERROR: ILLEGAL EXPANDED NAME
+  BEGIN
+    assert FALSE 
+      report "***FAILED TEST: c06s03b00x00p09n01i00999 - Expanded name is illegal."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s03b00x00p09n01i00999arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/non_compliant.exp b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/non_compliant.exp
new file mode 100644
index 0000000..f3f9bd0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/non_compliant.exp
@@ -0,0 +1,75 @@
+
+# Copyright (C) 2001 Clifton Labs, Inc
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  
+
+# Please email any bugs, comments, and/or additions to this file to:
+# vests@cliftonlabs.com
+
+# Authors: Philip A. Wilsey	philip.wilsey@ieee.org
+# 	   Dale E. Martin	dmartin@cliftonlabs.com
+
+# $Author: paw $
+# $Revision: 1.2 $
+
+# ------------------------------------------------------------------------
+#
+# $Id: non_compliant.exp,v 1.2 2001-10-19 23:29:32 paw Exp $
+#
+# ------------------------------------------------------------------------
+
+setup_test_group "Billowitch:Non-compliant Cases:Simulation Failure" "1076-1993"
+
+run_non_compliant_test tc77.vhd
+run_non_compliant_test tc78.vhd
+
+run_non_compliant_test tc255.vhd
+run_non_compliant_test tc259.vhd
+run_non_compliant_test tc260.vhd
+run_non_compliant_test tc261.vhd
+run_non_compliant_test tc262.vhd
+run_non_compliant_test tc263.vhd
+run_non_compliant_test tc264.vhd
+run_non_compliant_test tc536.vhd
+
+run_non_compliant_test tc1074.vhd
+run_non_compliant_test tc1227.vhd
+run_non_compliant_test tc1336.vhd
+run_non_compliant_test tc1399.vhd
+run_non_compliant_test tc1400.vhd
+run_non_compliant_test tc1401.vhd
+run_non_compliant_test tc1402.vhd
+run_non_compliant_test tc1404.vhd
+run_non_compliant_test tc1707.vhd
+run_non_compliant_test tc1708.vhd
+run_non_compliant_test tc1725.vhd
+run_non_compliant_test tc1951.vhd
+run_non_compliant_test tc3056.vhd
+
+end_test_group
+
+# $Log: non_compliant.exp,v $
+# Revision 1.2  2001-10-19 23:29:32  paw
+# Adding comments for cvs tracking information.
+#
+# Revision 1.1  2001/10/15 16:00:51  paw
+# Updating the compliant.exp script to properly use the functions in the new
+# savant test harness.
+#
+# Adding the scripts for non_compliant testing in the billowitch suite.
+#
+# When properly placed in the testsuite subdirectory of savant, a make check
+# will work.  Documentation will be added to the testsuite to describe how.
+#
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1074.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1074.vhd
new file mode 100644
index 0000000..07c752b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1074.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1074.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c06s04b00x00p03n04i01074ent IS
+END c06s04b00x00p03n04i01074ent;
+
+ARCHITECTURE c06s04b00x00p03n04i01074arch OF c06s04b00x00p03n04i01074ent IS
+BEGIN
+  TESTING: PROCESS
+    constant C1 : STRING    := "ABCDEFGH";
+    variable V1 : CHARACTER;
+    variable q  : integer    := 9;
+  BEGIN
+    V1 := C1(1);
+    assert V1 = 'A' 
+      report "FAIL: first index";
+    V1 := C1(q);                    -- should result in index error
+    assert FALSE 
+      report "***FAILED TEST: c06s04b00x00p03n04i01074- Index value should belong to the range of the corresponding index range of the array." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c06s04b00x00p03n04i01074arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1227.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1227.vhd
new file mode 100644
index 0000000..0bd0af4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1227.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1227.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s01b00x00p29n01i01227ent IS
+END c08s01b00x00p29n01i01227ent;
+
+ARCHITECTURE c08s01b00x00p29n01i01227arch OF c08s01b00x00p29n01i01227ent IS
+
+  procedure call_wait (constant dly : in time) is
+    --
+    -- This procedure simply waits for the time
+    -- specified in its argument.
+    --
+  begin
+    wait for dly;
+  end call_wait;
+
+  procedure indirect_wait (constant dly : in time) is
+    --
+    -- This procedure calls a procedure to wait for the
+    -- time specified in its argument.
+    --
+  begin
+    call_wait (dly);
+  end indirect_wait;
+
+  function call_waiter (constant dly : in time) return time is    
+    --
+    -- This function indirectly calls a procedure to wait
+    -- for the time specified in its argument, then
+    -- returns an incremented delay.
+    --
+    -- This is an illegal operation for a function and
+    -- will probably be caught at runtime.
+    --
+  begin
+    indirect_wait(dly);
+    return dly * 2;
+  end call_waiter;
+
+BEGIN
+  TESTING: PROCESS
+    variable   delay : time := 2 ns;
+  BEGIN
+    delay   := call_waiter(delay);   -- use wait indirectly
+    assert FALSE 
+      report "***FAILED TEST: c08s01b00x00p29n01i01227 - Wait statement appears in a procedure that has a parent that is a function subprogram." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s01b00x00p29n01i01227arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1336.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1336.vhd
new file mode 100644
index 0000000..ebd2b10
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1336.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1336.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b01x00p04n03i01336ent IS
+END c08s04b01x00p04n03i01336ent;
+
+ARCHITECTURE c08s04b01x00p04n03i01336arch OF c08s04b01x00p04n03i01336ent IS
+  signal S : TIME := 1 ns;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    wait for 10 ns;
+    S <= 1 ns after - S;
+    wait for 1 ns;
+    assert FALSE 
+      report "***FAILED TEST: c08s04b01x00p04n03i01336 - Time expression must be positive"
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b01x00p04n03i01336arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1399.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1399.vhd
new file mode 100644
index 0000000..46b4f61
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1399.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1399.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p06n01i01399ent IS
+END c08s05b00x00p06n01i01399ent;
+
+ARCHITECTURE c08s05b00x00p06n01i01399arch OF c08s05b00x00p06n01i01399ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype    ST    is INTEGER range 1 to 10;
+    variable    ILL    : INTEGER := 11;
+
+    variable V : ST;
+  BEGIN
+    V := ILL;                       -- should catch error here
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p06n01i01399 - Variable assignment scalar subtype (integer type) check test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p06n01i01399arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1400.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1400.vhd
new file mode 100644
index 0000000..50f7202
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1400.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1400.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p06n01i01400ent IS
+END c08s05b00x00p06n01i01400ent;
+
+ARCHITECTURE c08s05b00x00p06n01i01400arch OF c08s05b00x00p06n01i01400ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype    ST    is CHARACTER range 'B' to 'C';
+    variable    ILL    : CHARACTER := 'A';
+    
+    variable    V    : ST;
+  BEGIN
+    V := ILL;                       -- should catch error here
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p06n01i01400 - Variable assignment scalar subtype (character type) check test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p06n01i01400arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1401.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1401.vhd
new file mode 100644
index 0000000..e614b31
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1401.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1401.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p06n01i01401ent IS
+END c08s05b00x00p06n01i01401ent;
+
+ARCHITECTURE c08s05b00x00p06n01i01401arch OF c08s05b00x00p06n01i01401ent IS
+
+BEGIN
+  TESTING: PROCESS
+    subtype    ST    is REAL range 1.0 to 10.0;
+    variable    ILL    : REAL := 11.0;
+
+    variable V : ST;
+  BEGIN
+    V := ILL;                       -- should catch error here
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p06n01i01401 - Variable assignment scalar subtype (real type) check test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p06n01i01401arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1402.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1402.vhd
new file mode 100644
index 0000000..0e60312
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1402.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1402.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p06n01i01402ent IS
+END c08s05b00x00p06n01i01402ent;
+
+ARCHITECTURE c08s05b00x00p06n01i01402arch OF c08s05b00x00p06n01i01402ent IS
+
+BEGIN
+  TESTING: PROCESS
+    type PT is range INTEGER'LOW to INTEGER'HIGH
+      units
+        sbu;
+      end units;
+    subtype ST is PT range 1 sbu to 10 sbu;
+    variable ILL : PT := 11 sbu;
+
+    variable V : ST;
+  BEGIN
+    V := ILL;                       -- should catch error here
+    assert FALSE 
+      report "***FAILED TEST: c08s05b00x00p06n01i01402 - Variable assignment scalar subtype (physical type) check test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p06n01i01402arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1404.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1404.vhd
new file mode 100644
index 0000000..6aee464
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1404.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1404.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s05b00x00p06n01i01404ent IS
+END c08s05b00x00p06n01i01404ent;
+
+ARCHITECTURE c08s05b00x00p06n01i01404arch OF c08s05b00x00p06n01i01404ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V : INTEGER range 1 to 10;
+  BEGIN
+    V := 1;
+    V := V - 1;                     -- scalar variable subtype check error
+    wait for 5 ns;
+    assert FALSE
+      report "***FAILED TEST: c08s05b00x00p06n01i01404 - Scalar variable subtype check test failed."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s05b00x00p06n01i01404arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1707.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1707.vhd
new file mode 100644
index 0000000..1df3a0a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1707.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1707.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p07n01i01707ent IS
+END c09s02b00x00p07n01i01707ent;
+
+ARCHITECTURE c09s02b00x00p07n01i01707arch OF c09s02b00x00p07n01i01707ent IS
+  procedure call_wait (variable dly    : in    time;
+                       variable bool    : out    boolean) is
+    --
+    -- This procedure simply waits for the time specified in its argument.
+    --
+  begin
+    wait for dly;
+    bool := false;
+  end call_wait;
+
+  signal trigger : bit;
+BEGIN
+
+  trigger <= '1' after 5 ns;
+
+  TESTING: PROCESS( trigger )
+    variable delay : time    := 2 ns;
+    variable bool  : boolean := true;
+  BEGIN
+
+    call_wait(delay, bool);   -- use wait indirectly
+
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p07n01i01707 - Procedure with an indirect wait was illegal to be placed in a process with an explicit sensitivity list." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s02b00x00p07n01i01707arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1708.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1708.vhd
new file mode 100644
index 0000000..f4b1773
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1708.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1708.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c09s02b00x00p07n01i01708ent IS
+END c09s02b00x00p07n01i01708ent;
+
+ARCHITECTURE c09s02b00x00p07n01i01708arch OF c09s02b00x00p07n01i01708ent IS
+  procedure call_wait (variable dly : inout time) is
+    --
+    -- This procedure simply waits for the time
+    -- specified in its argument.
+    --
+  begin
+    wait for dly;
+    dly := dly + 1 ns;
+  end call_wait;
+  
+  procedure call_waiter (variable dly_time : inout time) is
+    --
+    -- This procedure just provides an extra level of indirection
+    --
+  begin
+    call_wait(dly_time);
+  end call_waiter;
+  
+  signal trigger : bit;                 -- inter-process communication signal
+
+BEGIN
+  TESTING: PROCESS( trigger )
+    variable delay : time := 2 ns;
+  BEGIN
+
+    call_waiter(delay);       -- use wait indirectly
+
+    assert FALSE 
+      report "***FAILED TEST: c09s02b00x00p07n01i01708 - Procedure with an indirect wait was illegal to be placed in a process with an explicit sensitivity list." 
+      severity ERROR;
+  END PROCESS TESTING;
+
+END c09s02b00x00p07n01i01708arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1725.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1725.vhd
new file mode 100644
index 0000000..34c1f6e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1725.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1725.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c12s06b01x00p04n01i01725ent IS
+END c12s06b01x00p04n01i01725ent;
+
+ARCHITECTURE c12s06b01x00p04n01i01725arch OF c12s06b01x00p04n01i01725ent IS
+  signal clk : bit;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    --
+    -- The signal assignment below tries to make two
+    -- assignments at the same (current) time.
+    --
+    clk <= '0', '1';
+    assert FALSE 
+      report "***FAILED TEST: c12s06b01x00p04n01i01725 - The signal assignment can not make two assignment at the same (current) time."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s06b01x00p04n01i01725arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1951.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1951.vhd
new file mode 100644
index 0000000..2b308d1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc1951.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1951.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c07s02b01x00p01n05i01951ent IS
+END c07s02b01x00p01n05i01951ent;
+
+ARCHITECTURE c07s02b01x00p01n05i01951arch OF c07s02b01x00p01n05i01951ent IS
+
+BEGIN
+  TESTING: PROCESS
+    constant C1 : BIT_VECTOR(1 to 4) := "0110";
+    constant C2 : BIT_VECTOR         := not C1;
+    constant C3 : BIT_VECTOR(1 TO 4) := not C1;
+  BEGIN
+    assert C1(1) = '0';
+    assert C2(0) = '1';
+    assert FALSE
+      report "***FAILED TEST: c07s02b01x00p01n05i01951 - Value is outside the range."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c07s02b01x00p01n05i01951arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc255.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc255.vhd
new file mode 100644
index 0000000..90728ba
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc255.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc255.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p07n01i00255ent IS
+END c03s01b02x00p07n01i00255ent;
+
+ARCHITECTURE c03s01b02x00p07n01i00255arch OF c03s01b02x00p07n01i00255ent IS
+  subtype T1 is integer range 1 to 10;
+  subtype T2 is integer range 1 to 100;
+BEGIN
+  TESTING: PROCESS
+    variable V1 : T1;
+    variable V2 : T1 := 4;
+    variable V3 : T1 := 9;
+  BEGIN
+    V1 := V2 * V3;   -- failure_here
+    assert FALSE 
+      report "***FAILED TEST: c03s01b02x00p07n01i00255 - Result of mathematical operation is not of integer type."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p07n01i00255arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc259.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc259.vhd
new file mode 100644
index 0000000..88faf2c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc259.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc259.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p08n01i00259ent IS
+END c03s01b02x00p08n01i00259ent;
+
+ARCHITECTURE c03s01b02x00p08n01i00259arch OF c03s01b02x00p08n01i00259ent IS
+BEGIN
+  TESTING: PROCESS
+    variable V : INTEGER := INTEGER'HIGH;
+    variable R : REAL    := 0.0;
+  BEGIN
+    R := 2.0 * REAL(V);
+    V := INTEGER(R);
+    assert FALSE
+      report "***FAILED TEST: c03s01b02x00p08n01i00259 - Number is out of integer bounds."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p08n01i00259arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc260.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc260.vhd
new file mode 100644
index 0000000..04d2380
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc260.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc260.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p08n01i00260ent IS
+END c03s01b02x00p08n01i00260ent;
+
+ARCHITECTURE c03s01b02x00p08n01i00260arch OF c03s01b02x00p08n01i00260ent IS
+BEGIN
+  TESTING: PROCESS
+    variable V : INTEGER := INTEGER'LOW;
+    variable R : REAL    := 0.0;
+  BEGIN
+    R := 2.0 * REAL(V);
+    V := INTEGER(R);
+    assert FALSE
+      report "***FAILED TEST: c03s01b02x00p08n01i00260 - Number is out of integer bounds."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p08n01i00260arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc261.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc261.vhd
new file mode 100644
index 0000000..ac83631
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc261.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc261.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p08n01i00261ent IS
+END c03s01b02x00p08n01i00261ent;
+
+ARCHITECTURE c03s01b02x00p08n01i00261arch OF c03s01b02x00p08n01i00261ent IS
+BEGIN
+  TESTING: PROCESS
+    variable V : INTEGER := INTEGER'HIGH / 2;
+  BEGIN
+    V := V * 3;             -- operation should overflow
+    assert FALSE
+      report "***FAILED TEST: c03s01b02x00p08n01i00261 - Number is out of integer bounds."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p08n01i00261arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc262.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc262.vhd
new file mode 100644
index 0000000..b325729
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc262.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc262.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p08n01i00262ent IS
+END c03s01b02x00p08n01i00262ent;
+
+ARCHITECTURE c03s01b02x00p08n01i00262arch OF c03s01b02x00p08n01i00262ent IS
+BEGIN
+  TESTING: PROCESS
+    variable V : INTEGER := INTEGER'LOW + 1;
+  BEGIN
+    V := V - 2;             -- operation should overflow
+    assert FALSE
+      report "***FAILED TEST: c03s01b02x00p08n01i00262 - Number is out of integer bounds."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p08n01i00262arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc263.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc263.vhd
new file mode 100644
index 0000000..94a7720
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc263.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc263.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p08n01i00263ent IS
+END c03s01b02x00p08n01i00263ent;
+
+ARCHITECTURE c03s01b02x00p08n01i00263arch OF c03s01b02x00p08n01i00263ent IS
+BEGIN
+  TESTING: PROCESS
+    variable V : INTEGER := INTEGER'HIGH / 2 + 1;
+  BEGIN
+    V := V + V;             -- operation should overflow
+    assert FALSE
+      report "***FAILED TEST: c03s01b02x00p08n01i00263 - Number is out of integer bounds."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p08n01i00263arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc264.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc264.vhd
new file mode 100644
index 0000000..50c7f82
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc264.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc264.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s01b02x00p08n01i00264ent IS
+END c03s01b02x00p08n01i00264ent;
+
+ARCHITECTURE c03s01b02x00p08n01i00264arch OF c03s01b02x00p08n01i00264ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable V : INTEGER := 100;
+  BEGIN
+    V := V ** V;            -- operation should overflow
+    assert FALSE
+      report "***FAILED TEST: c03s01b02x00p08n01i00264 - Number is out of integer bounds."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s01b02x00p08n01i00264arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc3056.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc3056.vhd
new file mode 100644
index 0000000..54cae99
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc3056.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc3056.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package c12s03b01x00p02n03i03056pkg is
+  subtype BYTE is BIT_VECTOR(7 downto 0);
+  function BIN_TO_INTG (IN_DATA : BYTE) return INTEGER;
+end c12s03b01x00p02n03i03056pkg;
+
+use WORK.c12s03b01x00p02n03i03056pkg.all;
+ENTITY c12s03b01x00p02n03i03056ent IS
+END c12s03b01x00p02n03i03056ent;
+
+ARCHITECTURE c12s03b01x00p02n03i03056arch OF c12s03b01x00p02n03i03056ent IS
+
+BEGIN
+  TESTING: PROCESS
+    variable S1 : BYTE := "00001111";
+    variable X  : INTEGER;
+  BEGIN
+    X := BIN_TO_INTG(S1) ;
+    assert FALSE
+      report "***FAILED TEST: c12s03b01x00p02n03i03056 - Subprogram Body should be elaaborated before subprogram call."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c12s03b01x00p02n03i03056arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc536.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc536.vhd
new file mode 100644
index 0000000..3be5882
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc536.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc536.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c03s03b00x00p05n02i00536ent IS
+  port (a,b: in integer; c,d: out integer);
+END c03s03b00x00p05n02i00536ent;
+
+ARCHITECTURE c03s03b00x00p05n02i00536arch OF c03s03b00x00p05n02i00536ent IS
+  type    typer is array (integer range <>) of integer;
+  subtype suber is typer (1 to 10);
+  type    arst  is access typer;
+BEGIN
+  TESTING: PROCESS
+    variable correct    : boolean;
+    variable varst       : arst;
+  BEGIN
+    varst       := new typer (1 to 10);
+    varst(1)    := 1;
+    varst(2)    := 2;
+    varst(12)    := 3; -- illegal (LRM 3.3)
+    wait for 1 ns;
+    assert FALSE
+      report "***FAILED TEST: c03s03b00x00p05n02i00536 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c03s03b00x00p05n02i00536arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc77.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc77.vhd
new file mode 100644
index 0000000..de9c5b1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc77.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc77.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p10n04i00077ent IS
+END c04s03b01x02p10n04i00077ent;
+
+ARCHITECTURE c04s03b01x02p10n04i00077arch OF c04s03b01x02p10n04i00077ent IS
+  type    int_array is array(1 to 1) of integer;
+  signal    s : int_array := (1 => 0);
+BEGIN
+
+  s <= (1 => 1);
+  s <= (1 => 21); s <= (1 => 22);
+  s <= (1 => 31); s <= (1 => 32); s <= (1 => 33);
+
+  TEST: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST:c04s03b01x02p10n04i00077- Signal has multiple sources but is not a resolved signal."
+      severity ERROR;
+    wait;
+  END PROCESS TEST;
+
+END c04s03b01x02p10n04i00077arch;
diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc78.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc78.vhd
new file mode 100644
index 0000000..88d0059
--- /dev/null
+++ b/testsuite/vests/vhdl-93/billowitch/non_compliant/simulator_failure/tc78.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc78.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c04s03b01x02p10n04i00078ent IS
+END c04s03b01x02p10n04i00078ent;
+
+ARCHITECTURE c04s03b01x02p10n04i00078arch OF c04s03b01x02p10n04i00078ent IS
+  type    int_array is array(1 to 1) of integer;
+  signal    s : int_array := (others => 0);
+BEGIN
+
+  s <= (others => 1);
+  s <= (others => 2);
+
+  TEST: PROCESS
+  BEGIN
+    assert FALSE
+      report "***FAILED TEST:c04s03b01x02p10n04i00078 - Signal has multiple sources but is not a resolved signal."
+      severity ERROR;
+    wait;
+  END PROCESS TEST;
+
+END c04s03b01x02p10n04i00078arch;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/compliant.exp b/testsuite/vests/vhdl-93/clifton-labs/compliant/compliant.exp
new file mode 100644
index 0000000..ba835c1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/compliant.exp
@@ -0,0 +1,58 @@
+
+# Copyright (C) Clifton Labs, Inc.  All rights reserved.
+
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation; either version 2 of the License, or (at your
+# option) any later version.
+# 
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General
+# Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 675 Mass Ave, Cambridge, MA 02139, USA.
+
+setup_test_group "Clifton Labs:Compliant Cases" "1076-1993"
+
+set dir_prefix_length [expr [string length ${subdir}] + 3]
+
+foreach local_test_name [find ${subdir} *\.vhd*] {
+    # look for input files that might be needed
+    regsub {\.vhd|\.vhdl} ${local_test_name} "\*.in" input_files_glob
+    set input_files [glob -nocomplain ${input_files_glob}]
+    set input_files_argument ""
+    if {${input_files} != ""} {
+	regsub "^.*vhdl-93/clifton-labs/compliant/" ${input_files} "" input_files
+	set input_file_name [split ${input_files} "/"]
+	set input_file_name [lindex ${input_file_name} [expr [llength ${input_file_name}] - 1]]
+#	set input_files_argument "INPUT=${input_file_name}:[pwd]/${input_files}"
+	set input_files_argument "INPUT=${input_file_name}:${input_files}"
+	verbose "Input files glob: ${input_files_glob}, files found: ${input_files}, argument generated ${input_files_argument}" 2
+    }
+
+    # look for output files that might be needed
+    regsub {\.vhd|\.vhdl} ${local_test_name} "\*.out" output_files_glob
+    set output_files [glob -nocomplain ${output_files_glob}]
+    set output_files_argument ""
+    if {${output_files} != ""} {
+	regsub "^.*vhdl-93/clifton-labs/compliant/" ${output_files} "" output_files
+	set output_file_name [split ${output_files} "/"]
+	set output_file_name [lindex ${output_file_name} [expr [llength ${output_file_name}] - 1]]
+#	set output_files_argument "INPUT=${output_file_name}:[pwd]/${output_files}"
+	set output_files_argument "INPUT=${output_file_name}:${output_files}"
+	verbose "Ouput files glob: ${output_files_glob}, files found: ${output_files}, argument generated ${output_files_argument}" 2
+    }
+
+    verbose "Running test at ./[string range ${local_test_name} [expr ${dir_prefix_length} - 2] end]  ${input_files_argument} ${output_files_argument}" 2
+    if {${input_files_argument} == "" && ${output_files_argument} == ""} {
+	run_compliant_test ./[string range ${local_test_name} [expr ${dir_prefix_length} - 2] end] 
+    } else {
+	run_compliant_test ./[string range ${local_test_name} [expr ${dir_prefix_length} - 2] end] "${input_files_argument} ${output_files_argument}"
+    }
+    delete_lib work
+}
+
+end_test_group
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/aggregates/simple-aggregate-lvalue.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/aggregates/simple-aggregate-lvalue.vhdl
new file mode 100644
index 0000000..2f338a2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/aggregates/simple-aggregate-lvalue.vhdl
@@ -0,0 +1,19 @@
+entity test is
+end test;
+
+architecture only of test is
+  type int_array is array (3 downto 0) of integer;
+begin  -- only
+  p: process
+    variable w, x, y, z : integer := 0;
+    variable q : int_array := (3, 2, 1, 0);
+  begin  -- process p
+    (w, x, y, z) := q;
+    assert w = 3 report "TEST FAILED" severity FAILURE;
+    assert x = 2 report "TEST FAILED" severity FAILURE;
+    assert y = 1 report "TEST FAILED" severity FAILURE;
+    assert z = 0 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/aggregates/simple-integer-aggregate.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/aggregates/simple-integer-aggregate.vhdl
new file mode 100644
index 0000000..a98cbbc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/aggregates/simple-integer-aggregate.vhdl
@@ -0,0 +1,17 @@
+entity test is
+end test;
+
+architecture only of test is
+  type integer_array is array (0 to 2) of integer;
+begin  -- only
+  p: process
+    variable x : integer_array;
+  begin  -- process p
+    x := (0, 1, 2);
+    assert x(0) = 0 report "TEST FAILED - 0" severity FAILURE;
+    assert x(1) = 1 report "TEST FAILED - 1" severity FAILURE;  
+    assert x(2) = 2 report "TEST FAILED - 2" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/aliases/objects/simple-string-alias.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/aliases/objects/simple-string-alias.vhdl
new file mode 100644
index 0000000..372f315
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/aliases/objects/simple-string-alias.vhdl
@@ -0,0 +1,14 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  only: process
+    variable string_variable : string(1 to 5) := "Hello";
+    alias string_alias : string(1 to 5) is string_variable;
+  begin  -- process
+    assert string_alias = "Hello" report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED";
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-ascending-attribute.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-ascending-attribute.vhdl
new file mode 100644
index 0000000..d1df1c8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-ascending-attribute.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  type my_type is array(0 to 3) of integer;
+begin  -- only
+  p: process
+  begin  -- process p
+    assert (my_type'ascending) report "TEST FAILED ascending" severity failure;
+    report "TEST PASSED ascending";
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-high-attribute.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-high-attribute.vhdl
new file mode 100644
index 0000000..18f508b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-high-attribute.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  type my_type is array(0 to 3) of integer;
+begin  -- only
+  p: process
+  begin  -- process p
+    assert my_type'high = 3 report "TEST FAILED high = 3" severity failure;
+    report "TEST PASSED high = 3";
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-left-attribute.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-left-attribute.vhdl
new file mode 100644
index 0000000..9c7f3b0
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-left-attribute.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  type my_type is array(0 to 3) of integer;
+begin  -- only
+  p: process
+  begin  -- process p
+    assert my_type'left = 0 report "TEST FAILED left = 0" severity failure;
+    report "TEST PASSED left = 0";
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-length-attribute.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-length-attribute.vhdl
new file mode 100644
index 0000000..add2c6c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-length-attribute.vhdl
@@ -0,0 +1,15 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : string(1 to 4) := "1234";
+  begin  -- process
+    assert x'length = 4 report "TEST FAILED - x'length does not equal 4" severity failure;
+    assert x'length /= 4 report "TEST PASSED" severity note;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-low-attribute.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-low-attribute.vhdl
new file mode 100644
index 0000000..bbec013
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-low-attribute.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  type my_type is array(0 to 3) of integer;
+begin  -- only
+  p: process
+  begin  -- process p
+    assert my_type'low = 0 report "TEST FAILED low = 0" severity failure;
+    report "TEST PASSED low = 0";
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-right-attribute.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-right-attribute.vhdl
new file mode 100644
index 0000000..d73f082
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/array/simple-right-attribute.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  type my_type is array(0 to 3) of integer;
+begin  -- only
+  p: process
+  begin  -- process p
+    assert my_type'right = 3 report "TEST FAILED right = 3" severity failure;
+    report "TEST PASSED right = 3";
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-event-attribute.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-event-attribute.vhdl
new file mode 100644
index 0000000..e3c5d30
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-event-attribute.vhdl
@@ -0,0 +1,22 @@
+entity test is
+end test;
+
+architecture only of test is
+  signal s : bit;
+begin
+  s  <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
+  p: process
+  begin
+    wait for 1 ns;
+    assert not(s'event) report "TEST FAILED - 'event active" severity failure;
+   wait for 25 ns;
+ --   s <= '1';
+--    wait for 0 ns;
+    assert s = '0' report "TEST FAILED - s has not changed  to 0 yet!" severity failure;
+     wait for 10 ns;
+    assert s = '1' report "TEST FAILED - s has not changed  to 1 yet!" severity failure;
+    assert (s'event) report "TEST FAILED - 'event not tripped" severity failure;
+    report "TEST PASSED";
+    wait;
+  end process;
+end architecture only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last-value.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last-value.vhdl
new file mode 100644
index 0000000..a2e0133
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last-value.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+  signal s : bit := '0';
+begin
+  p : process
+  begin
+    s <= '1';
+    wait for 0 fs;
+    assert s'last_value = '0' report "TEST FAILED" severity failure;
+    report "TEST PASSED";
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last_event-attribute.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last_event-attribute.vhdl
new file mode 100644
index 0000000..dfe1f22
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last_event-attribute.vhdl
@@ -0,0 +1,21 @@
+entity test is
+end test;
+
+architecture only of test is
+  signal s : bit;
+begin
+  s  <= '1' after 5 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
+  p: process
+   variable v: time;
+  begin
+   wait for 15 ns;
+    v:=s'last_event;
+    assert v = 10 ns report "TEST FAILED - s previous value incorrect!" severity failure;
+    report "TEST PASSED elapsed time is 10 ns" ;
+   wait for 14 ns;
+    v:=s'last_event;
+    assert v = 9 ns report "TEST FAILED - s previous value incorrect!" severity failure;
+    report "TEST PASSED elapsed time is 9 ns" ;
+    wait;
+  end process;
+end architecture only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last_value-attribute.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last_value-attribute.vhdl
new file mode 100644
index 0000000..eafaf40
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/signal/simple-last_value-attribute.vhdl
@@ -0,0 +1,18 @@
+entity test is
+end test;
+
+architecture only of test is
+  signal s : bit;
+begin
+  s  <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0' after 40 ns;
+  p: process
+   variable v: bit;
+  begin
+    wait for 1 ns;
+   wait for 25 ns;
+    v:=s'last_value;
+    assert v = '1' report "TEST FAILED - s previous value incorrect!" severity failure;
+    report "TEST PASSED v = 1" ;
+    wait;
+  end process;
+end architecture only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/base/simple-integer-test.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/base/simple-integer-test.vhdl
new file mode 100644
index 0000000..a47da0b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/base/simple-integer-test.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  subtype small is integer range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+ assert small'base'left = integer'left report "TEST FAILED" severity FAILURE;
+  report "TEST PASSED" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/left/simple-integer-test.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/left/simple-integer-test.vhdl
new file mode 100644
index 0000000..34b52d6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/left/simple-integer-test.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'left = 1 report "TEST FAILED" severity FAILURE;
+  report "TEST PASSED" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/range/simple-range-attribute.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/range/simple-range-attribute.vhdl
new file mode 100644
index 0000000..b3692a5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/range/simple-range-attribute.vhdl
@@ -0,0 +1,14 @@
+entity test is
+end test;
+
+architecture only of test is
+  type my_type is array(0 to 3) of integer;
+begin  -- only
+  p: process
+  begin  -- process p
+    assert my_type'range'left = 0 report "TEST FAILED" severity failure;
+    assert my_type'range'right = 3 report "TEST FAILED" severity failure;
+    report "TEST PASSED";
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/right/simple-integer-test.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/right/simple-integer-test.vhdl
new file mode 100644
index 0000000..4ebe8a1
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/right/simple-integer-test.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'right = 3 report "TEST FAILED" severity FAILURE;
+  report "TEST PASSED" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-ascending.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-ascending.vhdl
new file mode 100644
index 0000000..d5dc982
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-ascending.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert (small'ascending)  report "TEST FAILED ascending" severity FAILURE;
+  report "TEST PASSED ascending" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-high.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-high.vhdl
new file mode 100644
index 0000000..86f478a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-high.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'high = 3 report "TEST FAILED T high" severity FAILURE;
+  report "TEST PASSED T high" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-image.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-image.vhdl
new file mode 100644
index 0000000..0b62a3e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-image.vhdl
@@ -0,0 +1,17 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'image(1) = "1" report "TEST FAILED image 1" severity FAILURE;
+  report "TEST PASSED image 1" severity NOTE;
+  assert small'image(2) = "2" report "TEST FAILED image 2" severity FAILURE;
+  report "TEST PASSED image 2" severity NOTE;
+  assert small'image(3) = "3" report "TEST FAILED image 3" severity FAILURE;
+  report "TEST PASSED image 3" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-leftof.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-leftof.vhdl
new file mode 100644
index 0000000..b82884a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-leftof.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'leftof(2) = 1  report "TEST FAILED. leftof 2 = 1" severity FAILURE;
+  report "TEST PASSED leftof 2 = 1" severity NOTE;
+  assert small'leftof(3) = 2  report "TEST FAILED. leftof 3 = 2" severity FAILURE;
+  report "TEST PASSED leftof 3 = 2" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-low.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-low.vhdl
new file mode 100644
index 0000000..8499963
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-low.vhdl
@@ -0,0 +1,13 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'low = 1 report "TEST FAILED T low" severity FAILURE;
+  report "TEST PASSED T low" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-pred.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-pred.vhdl
new file mode 100644
index 0000000..03aebd7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-pred.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'pred(2) = 1  report "TEST FAILED. pred 2 = 1" severity FAILURE;
+  report "TEST PASSED pred 2 = 1" severity NOTE;
+  assert small'pred(3) = 2  report "TEST FAILED. pred 3 = 2" severity FAILURE;
+  report "TEST PASSED pred 3 = 2" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-rightof.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-rightof.vhdl
new file mode 100644
index 0000000..de11c66
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-rightof.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'rightof(1) = 2  report "TEST FAILED. rightof 1 = 2" severity FAILURE;
+  report "TEST PASSED rightof 1 = 2" severity NOTE;
+  assert small'rightof(2) = 3  report "TEST FAILED. rightof 2 = 3" severity FAILURE;
+  report "TEST PASSED rightof 2 = 3" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-succ.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-succ.vhdl
new file mode 100644
index 0000000..3f27b00
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-succ.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'succ(1) = 2  report "TEST FAILED. succ 1 = 2" severity FAILURE;
+  report "TEST PASSED succ 1 = 2" severity NOTE;
+  assert small'succ(2) = 3  report "TEST FAILED. succ 2 = 3" severity FAILURE;
+  report "TEST PASSED succ 2 = 3" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-val.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-val.vhdl
new file mode 100644
index 0000000..db5064b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-val.vhdl
@@ -0,0 +1,17 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'val(1) = 1 report "TEST FAILED val pos 1" severity FAILURE;
+  report "TEST PASSED val pos 1" severity NOTE;
+  assert small'val(2) = 2 report "TEST FAILED val pos 2" severity FAILURE;
+  report "TEST PASSED val pos 2" severity NOTE;
+  assert small'val(3) = 3 report "TEST FAILED val pos 3" severity FAILURE;
+  report "TEST PASSED val pos 3" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-value.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-value.vhdl
new file mode 100644
index 0000000..97b6cd2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/attributes/type/simple-integer-test-value.vhdl
@@ -0,0 +1,17 @@
+entity test is
+end test;
+
+architecture only of test is
+  type small is range 1 to 3;
+begin  -- only
+p: process
+begin  -- process p
+  assert small'value("1") = 1 report "TEST FAILED value 1" severity FAILURE;
+  report "TEST PASSED value 1" severity NOTE;
+  assert small'value("2") = 2 report "TEST FAILED value 2" severity FAILURE;
+  report "TEST PASSED value 2" severity NOTE;
+  assert small'value("3") = 3 report "TEST FAILED value 3" severity FAILURE;
+  report "TEST PASSED value 3" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/.cvsignore b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/.cvsignore
new file mode 100644
index 0000000..681ae24
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/.cvsignore
@@ -0,0 +1 @@
+work._savant_lib
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl
new file mode 100644
index 0000000..d162a11
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl
@@ -0,0 +1,41 @@
+entity forty_two is
+  port (
+    int_out : out integer);
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    int_out <= 42;
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two
+    port (
+      int_out : out integer);
+  end component;
+  
+  signal int_signal : integer;
+
+begin  -- only
+
+  ft0 : component forty_two
+    port map (
+      int_out => int_signal );
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert int_signal = 42 report "TEST FAILED" severity ERROR;
+    assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-config-spec.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-config-spec.vhdl
new file mode 100644
index 0000000..c43c3e2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-config-spec.vhdl
@@ -0,0 +1,46 @@
+entity forty_two is
+  port (
+    int_out : out integer);
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    int_out <= 42;
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two
+    port (
+      int_out : out integer);
+  end component;
+
+  for ft0 : forty_two
+    use entity work.forty_two(only)
+      port map ( int_out => int_out );
+  
+  signal int_signal : integer;
+
+begin  -- only
+
+  ft0 : component forty_two
+    port map (
+      int_out => int_signal );
+
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert int_signal = 42 report "TEST FAILED" severity ERROR;
+    assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-port-map.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-port-map.vhdl
new file mode 100644
index 0000000..60695f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-port-map.vhdl
@@ -0,0 +1,47 @@
+entity forty_two is
+  port (
+    int_out : out integer);
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    int_out <= 42;
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two_component
+    port (
+      c_int_out : out integer);
+  end component;
+
+  for ft0 : forty_two_component
+    use entity work.forty_two(only)
+      port map (
+        int_out => c_int_out);
+  
+  signal int_signal : integer;
+
+begin  -- only
+
+  ft0 : component forty_two_component
+    port map (
+      c_int_out => int_signal );
+
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert int_signal = 42 report "TEST FAILED" severity ERROR;
+    assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/simple-array-example.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/simple-array-example.vhdl
new file mode 100644
index 0000000..aa08f64
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/simple-array-example.vhdl
@@ -0,0 +1,47 @@
+entity forty_two is
+  port (
+    bv4_out : out bit_vector( 3 downto 0 ));
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    bv4_out <= "0110";
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two_component
+    port (
+      c_bv4_out : out bit_vector( 3 downto 0 ));
+  end component;
+
+  for ft0 : forty_two_component
+    use entity work.forty_two(only)
+      port map (
+        bv4_out => c_bv4_out );
+  
+  signal bv4_signal : bit_vector( 3 downto 0 );
+
+begin  -- only
+
+  ft0 : component forty_two_component
+    port map (
+      c_bv4_out => bv4_signal );
+
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert bv4_signal = "0110" report "TEST FAILED" severity ERROR;
+    assert not(bv4_signal = "0110") report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl
new file mode 100644
index 0000000..1a021e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl
@@ -0,0 +1,47 @@
+entity forty_two is
+  port (
+    bv_out : out bit_vector );
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    bv_out <= "0110";
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two_component
+    port (
+      c_bv_out : out bit_vector );
+  end component;
+
+  for ft0 : forty_two_component
+    use entity work.forty_two(only)
+      port map (
+        bv_out => c_bv_out );
+  
+  signal bv_signal : bit_vector( 3 downto 0 );
+
+begin  -- only
+
+  ft0 : component forty_two_component
+    port map (
+      c_bv_out => bv_signal );
+
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert bv_signal = "0110" report "TEST FAILED" severity ERROR;
+    assert not(bv_signal = "0110") report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/constants/simple-string-constant.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/constants/simple-string-constant.vhdl
new file mode 100644
index 0000000..88b3d13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/constants/simple-string-constant.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  doit: process
+    constant string_constant : string := "init";
+  begin  -- process
+    assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
+    assert string_constant(2) = 'n' REPORT "string_constant(2) not properly intialized" SEVERITY FAILURE;
+    assert string_constant(3) = 'i' REPORT "string_constant(3) not properly intialized" SEVERITY FAILURE;
+    assert string_constant(4) = 't' REPORT "string_constant(4) not properly intialized" SEVERITY FAILURE;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-array-type-through-inout-port.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-array-type-through-inout-port.vhdl
new file mode 100644
index 0000000..819c592
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-array-type-through-inout-port.vhdl
@@ -0,0 +1,15 @@
+entity test_output is
+  port (
+    output : inout bit_vector( 1 downto 0 ) := "10"
+    );
+end test_output;
+
+architecture only of test_output is
+begin  -- test_output
+  test: process
+  begin  -- process test
+    assert output = "10" report "test failed" severity error;
+    assert output /= "10" report "test passed" severity note;
+    wait;
+  end process test;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl
new file mode 100644
index 0000000..294ddda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/entities/pass-integer-through-inout-port.vhdl
@@ -0,0 +1,15 @@
+entity test_output is
+  port (
+    output : inout integer := 10
+    );
+end test_output;
+
+architecture only of test_output is
+begin  -- test_output
+  test: process
+  begin  -- process test
+    assert output = 10 report "test failed" severity error;
+    assert output /= 10 report "test passed" severity note;
+    wait;
+  end process test;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/integer-type-overload.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/integer-type-overload.vhdl
new file mode 100644
index 0000000..3809b2d
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/integer-type-overload.vhdl
@@ -0,0 +1,28 @@
+entity test is
+end test;
+
+architecture only of test is
+  type integer_t1 is range 0 to 2;
+  type integer_t2 is range 2 to 4;
+  function test_function ( constant param : integer_t1 )
+    return boolean is
+  begin
+    return true;
+  end function;
+  
+  function test_function ( constant param : integer_t2 )
+    return boolean is
+  begin
+    return true;
+  end function;
+begin  -- only
+  test: process
+    variable result : boolean;
+    variable param1 : integer_t1 := 3;
+    variable param2 : integer_t2 := 5;
+  begin  -- process
+    result := test_function( param1 );
+    result := test_function( param2 );
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-out-parameter.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-out-parameter.vhdl
new file mode 100644
index 0000000..7131e45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-out-parameter.vhdl
@@ -0,0 +1,18 @@
+entity test is
+end test;
+
+architecture only of test is
+  procedure out_param ( one : out integer ) is
+  begin
+    one := 1;
+  end out_param;
+begin  -- only
+  doit: process
+    variable one : integer := 0;
+  begin  -- process doit
+    out_param( one );
+    assert one = 1 report "TEST FAILED" severity failure;
+    report "TEST PASSED";
+    wait;
+  end process doit;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-procedure-call.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-procedure-call.vhdl
new file mode 100644
index 0000000..16068cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-procedure-call.vhdl
@@ -0,0 +1,16 @@
+entity test is
+end test;
+
+architecture only of test is
+  procedure doit is
+  begin
+    report "PROCEDURE CALLED!";
+  end procedure;
+begin  -- only
+  process
+  begin  -- process doit
+    doit;
+    report "TEST PASSED";
+    wait;    
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-resolution-function.vhd b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-resolution-function.vhd
new file mode 100644
index 0000000..249b1dc
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/simple-resolution-function.vhd
@@ -0,0 +1,38 @@
+entity test is
+end test;
+
+architecture only of test is
+  -- forward declaration of the function.
+  function wired_or( s : bit_vector ) return bit;
+  -- declare the subtype.
+  subtype rbit is wired_or bit;
+
+  -- declare the actual function.
+  function wired_or( s : bit_vector ) return bit is
+  begin
+      report "resolution function called!" severity note;
+    if  ( (s(0) = '1') or (s(1) = '1')) then
+      return '1';
+    end if;
+    return '0';
+  end wired_or;
+
+  -- declare a signal of that type.  a resolved signal.
+  signal s : rbit;
+
+begin
+
+  -- a concurrent signal assignment.  driver # 1.
+  s <= '1';
+
+  testing: process
+  begin
+    -- verify that resolution function getting called.
+    s <= '1' after 10 ns;
+    wait on s;
+    assert ( s = '1' ) report "TEST FAILED" severity failure;
+    report "TEST PASSED";
+    wait;
+  end process testing;
+
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/unconstrained_parameter.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/unconstrained_parameter.vhdl
new file mode 100644
index 0000000..38a9f9a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/functions/unconstrained_parameter.vhdl
@@ -0,0 +1,18 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- onlty
+  doit: process
+    function returns_last( p : bit_vector )
+      return bit is
+    begin
+      return p( p'length - 1 );
+    end function;
+  begin  -- process doit
+    assert returns_last( "00" ) = '0' report "TEST FAILED" severity failure;
+    assert returns_last( "11" ) = '1' report "TEST FAILED" severity failure;
+    report "TEST PASSED";
+    wait;
+  end process doit;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/generics/entity-generic-defines-port-type.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/generics/entity-generic-defines-port-type.vhdl
new file mode 100644
index 0000000..297cbd3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/generics/entity-generic-defines-port-type.vhdl
@@ -0,0 +1,40 @@
+entity test_bench is
+end test_bench;
+
+entity generic_defines_port_type is
+  generic( width : natural );
+  port( input : in bit_vector( width - 1 downto 0 );
+        finished : in boolean );
+end entity;
+
+architecture only of generic_defines_port_type is
+
+begin  -- only
+  p: process( finished )
+  begin  -- process p
+    if finished = true then
+      for i in input'range loop
+        assert input(i) = '1' report "TEST FAILED" severity FAILURE;
+      end loop;  -- i
+    end if;
+  end process p;
+end only;
+
+architecture only of test_bench is
+  signal gdpt1_input : bit_vector( 3 downto 0 ) := "0000";
+  signal gdpt1_finished : boolean := false;
+begin  -- only
+  gdpt1: entity generic_defines_port_type
+    generic map ( width => 4 )
+    port    map ( input => gdpt1_input, finished => gdpt1_finished );
+
+  doit: process
+  begin  -- process doit
+    gdpt1_input <= "1111";
+    wait for 1 fs;
+    gdpt1_finished <= true;
+    wait for 1 fs;
+    report "TEST PASSED";
+  end process doit;
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/generics/simple-entity-generic.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/generics/simple-entity-generic.vhdl
new file mode 100644
index 0000000..707646c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/generics/simple-entity-generic.vhdl
@@ -0,0 +1,13 @@
+entity test is
+  generic ( int_generic : integer := 10);
+end test;
+
+architecture only of test is
+begin  -- only
+  p: process
+  begin  -- process p
+    assert int_generic = 10 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/constants/simple-string-constant.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/constants/simple-string-constant.vhdl
new file mode 100644
index 0000000..88b3d13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/constants/simple-string-constant.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  doit: process
+    constant string_constant : string := "init";
+  begin  -- process
+    assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
+    assert string_constant(2) = 'n' REPORT "string_constant(2) not properly intialized" SEVERITY FAILURE;
+    assert string_constant(3) = 'i' REPORT "string_constant(3) not properly intialized" SEVERITY FAILURE;
+    assert string_constant(4) = 't' REPORT "string_constant(4) not properly intialized" SEVERITY FAILURE;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl
new file mode 100644
index 0000000..1e479aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl
@@ -0,0 +1,35 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+  signal sig : integer := 0;
+begin  -- only
+  assign: process
+  begin  -- process p
+    sig <= 1;
+    wait;
+  end process assign;
+
+  check1: process
+  begin  -- process check1
+    wait for 1 fs;
+    assert sig = 1 report "TEST FAILED" severity FAILURE;
+    wait;
+  end process check1;
+
+  check2: process
+  begin  -- process check1
+    wait for 1 fs;
+    assert sig = 1 report "TEST FAILED" severity FAILURE;
+    wait;
+  end process check2;
+
+  check3: process
+  begin  -- process check1
+    wait for 2 fs;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process check3;
+
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl
new file mode 100644
index 0000000..3efa37b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl
@@ -0,0 +1,23 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+  signal sig : integer := 0;
+begin  -- only
+  p: process
+  begin  -- process p
+    sig <= 1;
+    wait for 1 fs;
+    assert sig = 1 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+
+  r: process (sig)
+  begin  -- process r
+    if sig'event then
+      report "Event on sig, new value = " & integer'image( sig );
+    end if;
+  end process r;
+    
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl
new file mode 100644
index 0000000..91e45eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl
@@ -0,0 +1,13 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+  signal sig : integer := 0;
+begin  -- only
+  p: process
+  begin  -- process p
+    assert sig = 0 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/integer-variable-persist-across-activations.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/integer-variable-persist-across-activations.vhdl
new file mode 100644
index 0000000..1f7e65f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/integer-variable-persist-across-activations.vhdl
@@ -0,0 +1,26 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+  signal clock : bit;
+begin  -- only
+  process (clock)
+    variable x : integer := 0;
+    variable l : line;
+  begin  -- process
+    write( l, string'( "x = " ) );
+    write( l, x );
+    writeline( output, l );
+    x := x + 1;
+  end process;
+
+  process
+  begin  -- process
+    clock <= '1' after 1 ns,
+             '0' after 2 ns,
+             '1' after 3 ns;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-enumeration-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-enumeration-assign.vhdl
new file mode 100644
index 0000000..e324a39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-enumeration-assign.vhdl
@@ -0,0 +1,16 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : boolean := false;
+  begin  -- process
+    x := true;
+    assert x = true report "TEST FAILED - x does not equal true" severity failure;
+    assert x /= true report "TEST PASSED" severity note;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-assign.vhdl
new file mode 100644
index 0000000..265cadb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-assign.vhdl
@@ -0,0 +1,16 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : integer := 0;
+  begin  -- process
+    x := 1;
+    assert x = 1 report "TEST FAILED - x does not equal 1" severity failure;
+    assert x /= 1 report "TEST PASSED" severity note;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-initialize.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-initialize.vhdl
new file mode 100644
index 0000000..fc2ded3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-initialize.vhdl
@@ -0,0 +1,15 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : integer := 0;
+  begin  -- process
+    assert x = 0 report "TEST FAILED - x does not equal 1" severity failure;
+    report "TEST PASSED" severity note;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/addition/add-two-integers.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/addition/add-two-integers.vhdl
new file mode 100644
index 0000000..0d3c3a4
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/addition/add-two-integers.vhdl
@@ -0,0 +1,16 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : integer := 0;
+  begin  -- process
+    x := 1 + 2;
+    assert x = 3 report "TEST FAILED - x does not equal 1" severity failure;
+    assert x /= 3 report "TEST PASSED" severity NOTE;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/addition/variable-plus-int.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/addition/variable-plus-int.vhdl
new file mode 100644
index 0000000..18943e7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/addition/variable-plus-int.vhdl
@@ -0,0 +1,16 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : integer := 1;
+  begin  -- process
+    x := x + 2;
+    assert x = 3 report "TEST FAILED - x does not equal 1" severity failure;
+    assert x /= 3 report "TEST PASSED" severity NOTE;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/addition/variable-plus-variable.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/addition/variable-plus-variable.vhdl
new file mode 100644
index 0000000..cf19b32
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/addition/variable-plus-variable.vhdl
@@ -0,0 +1,17 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : integer := 1;
+    variable y : integer := 2;
+  begin  -- process
+    x := x + y;
+    assert x = 3 report "TEST FAILED - x does not equal 1" severity failure;
+    assert x /= 3 report "TEST PASSED" severity NOTE;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/concatenation/concatenate-string-character.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/concatenation/concatenate-string-character.vhdl
new file mode 100644
index 0000000..c626d1e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/concatenation/concatenate-string-character.vhdl
@@ -0,0 +1,18 @@
+entity test is
+end test;
+
+architecture only of test is
+
+begin  -- only
+
+  doit: process
+    variable concatted : string(1 to 4);
+  begin  -- process doit
+    concatted := "foo" & 'l';
+
+    assert concatted = "fool" report "TEST FAILED - concatted was not 'fool'" severity failure;
+    assert not(concatted = "fool") report "TEST PASSED" severity note;
+    
+    wait;
+  end process doit;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/concatenation/concatenate-two-strings.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/concatenation/concatenate-two-strings.vhdl
new file mode 100644
index 0000000..aab8f63
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/concatenation/concatenate-two-strings.vhdl
@@ -0,0 +1,18 @@
+entity test is
+end test;
+
+architecture only of test is
+
+begin  -- only
+
+  doit: process
+    variable concatted : string(1 to 6);
+  begin  -- process doit
+    concatted := "foo" & "bar";
+
+    assert concatted = "foobar" report "TEST FAILED - concatted was not 'foobar'" severity failure;
+    assert not(concatted = "foobar") report "TEST PASSED" severity note;
+    
+    wait;
+  end process doit;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/division/integer-division.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/division/integer-division.vhdl
new file mode 100644
index 0000000..3124df8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/operators/division/integer-division.vhdl
@@ -0,0 +1,16 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : integer := 0;
+  begin  -- process
+    x := 4/2;
+    assert x = 2 report "TEST FAILED - x does not equal 2" severity failure;
+    assert x /= 2 report "TEST PASSED" severity note;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/packages/simple_package_body_test.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/packages/simple_package_body_test.vhdl
new file mode 100644
index 0000000..205cb35
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/packages/simple_package_body_test.vhdl
@@ -0,0 +1,28 @@
+package test_pkg is
+  function return_one
+    return integer;
+end test_pkg;
+
+package body test_pkg is
+  function return_one
+    return integer is
+  begin  -- return_one
+    return 1;
+  end return_one;
+end test_pkg;
+
+
+use work.test_pkg.all;
+
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  p: process
+  begin  -- process p
+    assert ( return_one = 1 ) report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/packages/simple_package_test.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/packages/simple_package_test.vhdl
new file mode 100644
index 0000000..c7f0f2e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/packages/simple_package_test.vhdl
@@ -0,0 +1,20 @@
+package test_pkg is
+  type small_int is range -5 to 5;
+end test_pkg;
+
+use work.test_pkg.all;
+
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  p: process
+    variable x : small_int;
+  begin  -- process p
+    x := 3;
+    assert ( x = 3 ) report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl
new file mode 100644
index 0000000..d3809c5
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-array-assign.vhdl
@@ -0,0 +1,16 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+  signal sig : bit_vector( 3 downto 0 );
+begin  -- only
+  p: process
+  begin  -- process p
+    sig <= "1001";
+    wait for 1 fs;
+    assert sig = "1001" report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+    
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-assign.vhdl
new file mode 100644
index 0000000..c233fdf
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-assign.vhdl
@@ -0,0 +1,16 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+  signal sig : integer := 0;
+begin  -- only
+  p: process
+  begin  -- process p
+    sig <= 1;
+    wait for 1 fs;
+    assert sig = 1 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+    
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-initialize.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-initialize.vhdl
new file mode 100644
index 0000000..91e45eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple-integer-initialize.vhdl
@@ -0,0 +1,13 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+  signal sig : integer := 0;
+begin  -- only
+  p: process
+  begin  -- process p
+    assert sig = 0 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple/.cvsignore b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple/.cvsignore
new file mode 100644
index 0000000..19eb705
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/signals/assign/simple/.cvsignore
@@ -0,0 +1,2 @@
+work._savant_lib
+work.sym
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/slices/simple-slice.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/slices/simple-slice.vhdl
new file mode 100644
index 0000000..626fc79
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/slices/simple-slice.vhdl
@@ -0,0 +1,14 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  doit: process
+    constant string_constant : string := "foobar";
+  begin  -- process
+    assert string_constant( 1 to 3 ) = "foo" report "TEST FAILED" severity FAILURE;
+    assert string_constant( 4 to 6 ) = "bar" report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED";
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/slices/slice-lvalue.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/slices/slice-lvalue.vhdl
new file mode 100644
index 0000000..3c5f750
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/slices/slice-lvalue.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  doit: process
+    variable string_var : string( 1 to 6 );
+  begin  -- process
+    string_var( 1 to 3 ) := "foo";
+    string_var( 4 to 6 ) := "bar";
+    assert string_var = "foobar" report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED";
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/block-statements/simple-grouping-block.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/block-statements/simple-grouping-block.vhdl
new file mode 100644
index 0000000..c10bd22
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/block-statements/simple-grouping-block.vhdl
@@ -0,0 +1,26 @@
+entity test is
+end test;
+
+architecture only of test is
+  signal delay_line_in : bit := '0';
+  signal delay_line_out : bit := '0';
+begin  -- only
+  delay: block
+  begin  -- block delay
+    delay_line_out <= delay_line_in after 1 ns;
+  end block delay;
+
+  start: process
+  begin  -- process
+    delay_line_in <= '1';
+    wait;
+  end process;
+
+  check: process( delay_line_out )
+  begin
+    if delay_line_out = '1' then
+      assert now = 1 ns report "TEST FAILED - delay did not happen as expected!" severity FAILURE;
+      assert not(now = 1 ns) report "TEST PASSED" severity FAILURE;
+    end if;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/dynamic_package_procedure_for_loop.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/dynamic_package_procedure_for_loop.vhdl
new file mode 100644
index 0000000..48d810f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/dynamic_package_procedure_for_loop.vhdl
@@ -0,0 +1,30 @@
+package pkg is
+  procedure iterate (
+    input : in bit_vector);
+end pkg;
+
+package body pkg is
+  procedure iterate (
+    input : in bit_vector) is
+    variable j : integer := input'range'left;
+  begin  -- iterate
+    for i in input'range loop
+      assert i = j report "TEST FAILED" severity failure;
+      j := j + 1;
+    end loop;  -- i in 1 to 10
+    assert j = input'range'right + 1 report "TEST FAILED" severity failure;
+  end iterate;
+end pkg;
+
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  doit: process
+  begin  -- process doit
+    work.pkg.iterate("0000");
+    report "TEST PASSED";
+    wait;
+  end process doit;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/dynamic_procedure_for_loop.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/dynamic_procedure_for_loop.vhdl
new file mode 100644
index 0000000..0ce8eda
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/dynamic_procedure_for_loop.vhdl
@@ -0,0 +1,22 @@
+entity test is
+end test;
+
+architecture only of test is
+  procedure iterate (
+    input : in bit_vector) is
+    variable j : integer := input'range'left;
+  begin  -- iterate
+    for i in input'range loop
+      assert i = j report "TEST FAILED" severity failure;
+      j := j + 1;
+    end loop;  -- i in 1 to 10
+    assert j = input'range'right + 1 report "TEST FAILED" severity failure;
+  end iterate;
+begin  -- only
+  doit: process
+  begin  -- process doit
+    iterate("0000");
+    report "TEST PASSED";
+    wait;
+  end process doit;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/enumeration-for-loop-constrained.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/enumeration-for-loop-constrained.vhdl
new file mode 100644
index 0000000..647642e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/enumeration-for-loop-constrained.vhdl
@@ -0,0 +1,17 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+p: process
+  type color is ( red, blue, green );
+  variable x : color;
+begin  -- process p
+  for i in red to blue loop
+    x := i;
+  end loop;  -- i
+  assert x = blue report "TEST FAILED x was " & color'image(x) severity ERROR;
+  report "TEST PASSED" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/enumeration-for-loop.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/enumeration-for-loop.vhdl
new file mode 100644
index 0000000..2330e18
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/enumeration-for-loop.vhdl
@@ -0,0 +1,17 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+p: process
+  type color is ( red, blue, green );
+  variable x : color;
+begin  -- process p
+  for i in red to green loop
+    x := i;
+  end loop;  -- i
+  assert x = green report "TEST FAILED x was " & color'image(x) severity ERROR;
+  report "TEST PASSED" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/integer-for-loop.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/integer-for-loop.vhdl
new file mode 100644
index 0000000..1a7db2f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/for-loops/integer-for-loop.vhdl
@@ -0,0 +1,16 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+p: process
+  variable x : integer;
+begin  -- process p
+  for i in 1 to 10 loop
+    x := i;
+  end loop;  -- i
+  assert x = 10 report "TEST FAILED x was " & integer'image(x) severity ERROR;
+  report "TEST PASSED" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/if-statements/simple-if-statement.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/if-statements/simple-if-statement.vhdl
new file mode 100644
index 0000000..d84b85f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/statements/if-statements/simple-if-statement.vhdl
@@ -0,0 +1,37 @@
+entity test is
+end test;
+
+architecture only of test is
+
+begin  -- only
+  doit: process
+    variable one, two, three : boolean := false;
+  begin  -- process doit
+    if true then
+      one := true;
+    else
+      
+    end if;
+    
+    if false then
+      one := false;
+    else
+      two := true;
+    end if;
+
+    if false then
+      one := false;
+    elsif true then
+      three := true;
+    else
+      two := false;
+    end if;
+    
+    assert one report "TEST FAILED - first if test failed" severity failure;
+    assert two report "TEST FAILED - second if test failed" severity failure;
+    assert three report "TEST FAILED - third if test failed" severity failure;
+    report "TEST PASSED" severity note;
+    
+    wait;
+  end process doit;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_and_table.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_and_table.vhdl
new file mode 100644
index 0000000..ba58cb6
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_and_table.vhdl
@@ -0,0 +1,48 @@
+entity test is
+end test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package foo is
+  TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
+    CONSTANT and_table : stdlogic_table := (
+    --      ----------------------------------------------------
+    --      |  U    X    0    1    Z    W    L    H    -         |   |
+    --      ----------------------------------------------------
+            ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ),  -- | U |
+            ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),  -- | X |
+            ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ),  -- | 0 |
+            ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),  -- | 1 |
+            ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),  -- | Z |
+            ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ),  -- | W |
+            ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ),  -- | L |
+            ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),  -- | H |
+            ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' )   -- | - |
+    );
+end foo;
+
+use work.foo.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture only of test is
+
+begin  -- only
+  process
+  begin  -- process
+    assert and_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU";
+    assert and_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX";
+    assert and_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-";
+    assert and_table( '0', '1' ) = '0' report "TEST FAILED-0x1";
+    assert and_table( 'H', 'Z' ) = 'X' report "TEST FAILED-HxZ";
+    assert and_table( 'Z', 'W' ) = 'X' report "TEST FAILED-ZxW";
+    assert and_table( 'L', '1' ) = '0' report "TEST FAILED-Lx1";
+    assert and_table( 'H', '1' ) = '1' report "TEST FAILED-Hx1";
+    assert and_table( '0', 'L' ) = '0' report "TEST FAILED-0xL";
+    assert and_table( 'Z', 'L' ) = '0' report "TEST FAILED-ZxL";
+    assert and_table( 'Z', 'H' ) = 'X' report "TEST FAILED-ZxH";
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_or_table.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_or_table.vhdl
new file mode 100644
index 0000000..4a2f186
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_or_table.vhdl
@@ -0,0 +1,49 @@
+entity test is
+end test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package foo is
+  TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
+    -- truth table for "or" function
+    CONSTANT or_table : stdlogic_table := (
+    --      ----------------------------------------------------
+    --      |  U    X    0    1    Z    W    L    H    -         |   |
+    --      ----------------------------------------------------
+            ( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ),  -- | U |
+            ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ),  -- | X |
+            ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),  -- | 0 |
+            ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ),  -- | 1 |
+            ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ),  -- | Z |
+            ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ),  -- | W |
+            ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),  -- | L |
+            ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ),  -- | H |
+            ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' )   -- | - |
+    );
+end foo;
+
+use work.foo.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture only of test is
+
+begin  -- only
+  process
+  begin  -- process
+    assert or_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU";
+    assert or_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX";
+    assert or_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-";
+    assert or_table( '0', '1' ) = '1' report "TEST FAILED-0x1";
+    assert or_table( 'H', 'Z' ) = '1' report "TEST FAILED-HxZ";
+    assert or_table( 'Z', 'W' ) = 'X' report "TEST FAILED-ZxW";
+    assert or_table( 'L', '1' ) = '1' report "TEST FAILED-Lx1";
+    assert or_table( 'H', '1' ) = '1' report "TEST FAILED-Hx1";
+    assert or_table( '0', 'L' ) = '0' report "TEST FAILED-0xL";
+    assert or_table( 'Z', 'L' ) = 'X' report "TEST FAILED-ZxL";
+    assert or_table( 'Z', 'H' ) = '1' report "TEST FAILED-ZxH";
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_resolution_table.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_resolution_table.vhdl
new file mode 100644
index 0000000..a873967
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_resolution_table.vhdl
@@ -0,0 +1,47 @@
+entity test is
+end test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package foo is
+  TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
+  CONSTANT resolution_table : stdlogic_table := (
+--  ---------------------------------------------------------
+--  |  U    X    0    1    Z    W    L    H    -        |   |
+--  ---------------------------------------------------------
+    ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
+    ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
+    ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
+    ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
+    ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
+    ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
+    ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
+    ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
+    ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )  -- | - |
+    );
+end foo;
+
+use work.foo.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture only of test is
+
+begin  -- only
+  process
+  begin  -- process
+    assert resolution_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU";
+    assert resolution_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX";
+    assert resolution_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-";
+    assert resolution_table( '0', '1' ) = 'X' report "TEST FAILED-0x1";
+    assert resolution_table( 'H', 'Z' ) = 'H' report "TEST FAILED-HxZ";
+    assert resolution_table( 'Z', 'W' ) = 'W' report "TEST FAILED-ZxW";
+    assert resolution_table( 'L', '1' ) = '1' report "TEST FAILED-Lx1";
+    assert resolution_table( '0', 'L' ) = '0' report "TEST FAILED-0xL";
+    assert resolution_table( 'Z', 'L' ) = 'L' report "TEST FAILED-ZxL";
+    assert resolution_table( 'Z', 'H' ) = 'H' report "TEST FAILED-ZxH";
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_resolution_function.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_resolution_function.vhdl
new file mode 100644
index 0000000..97bc985
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_resolution_function.vhdl
@@ -0,0 +1,24 @@
+entity test is
+end test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture only of test is
+  signal x, y, result : std_logic := '1';
+begin  -- only
+  result <= x;
+  result <= y;
+
+  process
+  begin  -- process
+    assert x = '1' report "TEST FAILED" severity failure;
+    assert y = '1' report "TEST FAILED" severity failure;
+    assert result = '1' report "TEST FAILED" severity failure;
+
+    report "TEST PASSED";
+--    x <= 'U';
+--    y <= 'U';
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_type.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_type.vhdl
new file mode 100644
index 0000000..a633463
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_type.vhdl
@@ -0,0 +1,43 @@
+entity test is
+end test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture only of test is
+
+begin  -- only
+  process
+    variable x : std_logic;
+  begin  -- process
+    assert std_logic'pos('U') = 0 report "TEST FAILED" severity FAILURE;
+    assert std_logic'pos('X') = 1 report "TEST FAILED" severity FAILURE;
+    assert std_logic'pos('0') = 2 report "TEST FAILED" severity FAILURE;
+    assert std_logic'pos('1') = 3 report "TEST FAILED" severity FAILURE;
+    assert std_logic'pos('Z') = 4 report "TEST FAILED" severity FAILURE;
+    assert std_logic'pos('W') = 5 report "TEST FAILED" severity FAILURE;
+    assert std_logic'pos('L') = 6 report "TEST FAILED" severity FAILURE;
+    assert std_logic'pos('H') = 7 report "TEST FAILED" severity FAILURE;
+    assert std_logic'pos('-') = 8 report "TEST FAILED" severity FAILURE;
+
+    assert x'left = 'U' report "TEST FAILED" severity FAILURE;
+    assert x'right = '-' report "TEST FAILED" severity FAILURE;
+    assert x'high = '-' report "TEST FAILED" severity FAILURE;
+    assert x'low = 'U' report "TEST FAILED" severity FAILURE;
+    assert x'ascending = true report "TEST FAILED" severity FAILURE;
+
+    assert std_logic'image('U') = "'U'" report "TEST FAILED" severity FAILURE;
+    assert std_logic'value("'U'") = 'U' report "TEST FAILED" severity FAILURE;
+
+    assert std_logic'val(0) = 'U' report "TEST FAILED" severity FAILURE;
+
+    assert std_logic'succ('U') = 'X' report "TEST FAILED" severity FAILURE;
+    assert std_logic'pred('-') = 'H' report "TEST FAILED" severity FAILURE;
+
+    assert std_logic'leftof('-') = 'H' report "TEST FAILED" severity FAILURE;
+    assert std_logic'rightof('U') = 'X' report "TEST FAILED" severity FAILURE;
+    
+    report "TEST PASSED" severity note;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_xor_table.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_xor_table.vhdl
new file mode 100644
index 0000000..32e55cd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_xor_table.vhdl
@@ -0,0 +1,49 @@
+entity test is
+end test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package foo is
+  TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
+    -- truth table for "xor" function
+    CONSTANT xor_table : stdlogic_table := (
+    --      ----------------------------------------------------
+    --      |  U    X    0    1    Z    W    L    H    -         |   |
+    --      ----------------------------------------------------
+            ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ),  -- | U |
+            ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),  -- | X |
+            ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),  -- | 0 |
+            ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ),  -- | 1 |
+            ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),  -- | Z |
+            ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),  -- | W |
+            ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),  -- | L |
+            ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ),  -- | H |
+            ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )   -- | - |
+    );
+end foo;
+
+use work.foo.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture only of test is
+
+begin  -- only
+  process
+  begin  -- process
+    assert xor_table( 'U', 'U' ) = 'U' report "TEST FAILED-UxU";
+    assert xor_table( 'U', 'X' ) = 'U' report "TEST FAILED-UxX";
+    assert xor_table( 'X', '-' ) = 'X' report "TEST FAILED-Xx-";
+    assert xor_table( '0', '1' ) = '1' report "TEST FAILED-0x1";
+    assert xor_table( 'H', 'Z' ) = 'X' report "TEST FAILED-HxZ";
+    assert xor_table( 'Z', 'W' ) = 'X' report "TEST FAILED-ZxW";
+    assert xor_table( 'L', '1' ) = '1' report "TEST FAILED-Lx1";
+    assert xor_table( 'H', '1' ) = '0' report "TEST FAILED-Hx1";
+    assert xor_table( '0', 'L' ) = '0' report "TEST FAILED-0xL";
+    assert xor_table( 'Z', 'L' ) = 'X' report "TEST FAILED-ZxL";
+    assert xor_table( 'Z', 'H' ) = 'X' report "TEST FAILED-ZxH";
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_standard/simple-now-test.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_standard/simple-now-test.vhdl
new file mode 100644
index 0000000..9b6db14
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_standard/simple-now-test.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  p: process
+  begin  -- process p
+    wait for 1 ns;
+    assert now = 1 ns report "TEST FAILED" severity FAILURE;
+    wait for 10 ns;
+    assert now = 11 ns report "TEST FAILED" severity FAILURE;
+    report "PASSED TEST" severity NOTE;
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/subtypes/modified-character-subtype.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/subtypes/modified-character-subtype.vhdl
new file mode 100644
index 0000000..c64b80b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/subtypes/modified-character-subtype.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  doit: process
+    subtype sub_character is character range 'A' to 'Z';
+    constant x : sub_character;
+  begin
+    assert x = sub_character'left report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED";
+    wait;
+  end process;   
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/subtypes/modified-integer-subtype.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/subtypes/modified-integer-subtype.vhdl
new file mode 100644
index 0000000..4cb4e7c
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/subtypes/modified-integer-subtype.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  doit: process
+    subtype sub_integer is integer range 42 to 69;
+    constant x : sub_integer;
+  begin
+    assert x = sub_integer'left report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED";
+    wait;
+  end process;   
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/subtypes/simple-enumeration-subtype.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/subtypes/simple-enumeration-subtype.vhdl
new file mode 100644
index 0000000..7466658
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/subtypes/simple-enumeration-subtype.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  doit: process
+    subtype sub_boolean is boolean range false to true;
+    constant x : sub_boolean;
+  begin
+    assert x = sub_boolean'left report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED";
+    wait;
+  end process;   
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_array_read.in b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_array_read.in
new file mode 100644
index 0000000..6292c45
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_array_read.in
@@ -0,0 +1 @@
+'1', 'A', '$', '+'
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_array_read.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_array_read.vhdl
new file mode 100644
index 0000000..1358d40
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_array_read.vhdl
@@ -0,0 +1,58 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity character_array_read is
+end character_array_read;
+
+architecture test0 of character_array_read is
+  type character_array      is array (natural range <>) of character;
+  type character_array_file is file of character_array;
+  signal    k : integer := 0;
+begin
+  doit: process
+    file filein    : character_array_file open read_mode is "character_array_read.in";
+    variable  v    : character_array(0 to 3);
+    variable  len   : natural;
+  begin
+    assert(endfile(filein) = false)
+      report "End of file reached before expected."
+      severity failure;
+
+    read(filein,v,len);
+
+    assert(len = 4)
+      report "FAILED TEST: character_array_read.  Wrong length."
+      severity failure;
+
+    assert (v = ('1','a','$','+'))
+      report "FAILED TEST: character_array_read.  Incorrect characters read."
+      severity failure;
+
+    assert(endfile(filein))
+      severity failure;
+
+    report "PASSED TEST: character_array_read."
+      severity note;
+    wait;
+  end process;
+
+end test0;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_read.in b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_read.in
new file mode 100644
index 0000000..f3727af
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_read.in
@@ -0,0 +1,4 @@
+'1'
+'A'
+'$'
+'+'
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_read.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_read.vhdl
new file mode 100644
index 0000000..7acb135
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/character_read.vhdl
@@ -0,0 +1,58 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity character_read is
+end character_read;
+
+architecture test0 of character_read is
+  type character_file is file of character;
+  signal k : integer := 0;
+begin
+  doit: process
+    file filein : character_file open read_mode is "character_read.in";
+    variable  v : character;
+  begin
+    assert(endfile(filein) = false)
+      report "End of file reached before expected."
+      severity failure;
+
+    read(filein,v); 
+
+    assert(v = '1') severity failure;
+
+    read(filein,v); 
+    assert(v = 'A') severity failure;
+
+    read(filein,v); 
+    assert(v = '$') severity failure;
+
+    read(filein,v); 
+    assert(v = '+') severity failure;
+
+    assert(endfile(filein));
+
+    report "PASSED TEST: character_read."
+      severity NOTE;
+    wait;
+  end process;
+
+end test0;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/simple-read.in b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/simple-read.in
new file mode 100644
index 0000000..94ebaf9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/simple-read.in
@@ -0,0 +1,4 @@
+1
+2
+3
+4
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/simple-read.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/simple-read.vhdl
new file mode 100644
index 0000000..0ce2968
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/read/simple-read.vhdl
@@ -0,0 +1,57 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity simple_read is
+end simple_read;
+
+use std.textio.all;
+
+architecture only of simple_read is
+  type integer_file is file of integer;
+begin  -- only
+  doit: process
+    file infile : integer_file open read_mode is "simple-read.in";
+    variable v : integer;
+  begin  -- process
+
+    assert( not(endfile( infile )) );
+
+    read( infile, v );
+    assert( v = 1 );
+
+    read( infile, v );
+    assert( v = 2 );
+
+    read( infile, v );
+    assert( v = 3 );
+
+    read( infile, v );
+    assert( v = 4 );
+
+    assert( endfile( infile ) );
+
+    report "PASSED"
+      severity NOTE;
+    
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/character_array_write.vhd b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/character_array_write.vhd
new file mode 100644
index 0000000..1774062
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/character_array_write.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity character_array_write is
+end character_array_write;
+
+architecture test0 of character_array_write is
+  type character_array  is array (natural range <>) of character;
+  type character_array_file is file of character_array;
+begin
+  doit: process
+    file fileout : character_array_file open write_mode is "character_array_write.out";
+  begin
+    write(fileout,('1','a','$','+'));
+
+    assert false
+      report "PASSED TEST: character_array_write."
+      severity note;
+    wait;
+  end process;
+
+end test0;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/character_write.vhd b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/character_write.vhd
new file mode 100644
index 0000000..fab261a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/character_write.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity character_write is
+end character_write;
+
+architecture test0 of character_write is
+  type character_file is file of character;
+begin
+  doit: process
+    file fileout : character_file open write_mode is "character_write.out";
+  begin
+    write(fileout, '1');
+    write(fileout, 'a');
+    write(fileout, '$');
+    write(fileout, '+');
+
+    assert false
+      report "PASSED TEST: character_write."
+      severity note;
+    wait;
+  end process;
+
+end test0;
+
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_1.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_1.vhdl
new file mode 100644
index 0000000..c06ac1a
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_1.vhdl
@@ -0,0 +1,57 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity fopen_test_3 is
+end fopen_test_3;
+
+architecture test0 of fopen_test_3 is
+
+  constant StringLength: integer := 16;
+  constant NumOfStrings: integer := 5;
+  
+  subtype str16 is string (1 to StringLength);
+  type string_table is array (1 to NumOfStrings) of str16;
+
+  constant string_array: string_table :=
+    ( "This is string 1"
+      ,"__Hello  World__"
+      ,"This is string " & "3"
+      ,"_Bird is a word_"
+      ,"_Goodbye (ciao)_"
+      );
+
+  type ft is file of string;
+
+begin
+  doit: process
+    file file_desc : ft;
+  begin
+    file_open(file_desc, "fopen_test_1.out", write_mode);
+    for i in NumOfStrings downto 1 loop
+      write(file_desc, string_array(i));
+    end loop;
+    file_close(file_desc);
+
+    wait;
+  end process; 
+
+end test0;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_2.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_2.vhdl
new file mode 100644
index 0000000..2ef6a13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_2.vhdl
@@ -0,0 +1,63 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity fopen_test_3 is
+end fopen_test_3;
+
+architecture test0 of fopen_test_3 is
+
+  constant StringLength: integer := 16;
+  constant NumOfStrings: integer := 5;
+  
+  subtype str16 is string (1 to StringLength);
+  type string_table is array (1 to NumOfStrings) of str16;
+
+  constant string_array: string_table :=
+    ( "This is string 1"
+      ,"__Hello  World__"
+      ,"This is string " & "3"
+      ,"_Bird is a word_"
+      ,"_Goodbye (ciao)_"
+      );
+
+  type ft is file of string;
+
+begin
+  doit: process
+    file file_desc : ft;
+  begin
+    file_open(file_desc, "fopen_test_2.out", write_mode);
+    for i in NumOfStrings downto 1 loop
+      write(file_desc, string_array(i));
+    end loop;
+    file_close(file_desc);
+
+    file_open(file_desc, "fopen_test_2.out", append_mode);
+    for i in 1 to NumOfStrings loop
+      write(file_desc, string_array(i));
+    end loop;
+    file_close(file_desc);
+
+    wait;
+  end process; 
+
+end test0;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_3.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_3.vhdl
new file mode 100644
index 0000000..dfcd46f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/fopen_test_3.vhdl
@@ -0,0 +1,63 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity fopen_test_3 is
+end fopen_test_3;
+
+architecture test0 of fopen_test_3 is
+
+  constant StringLength: integer := 16;
+  constant NumOfStrings: integer := 5;
+  
+  subtype str16 is string (1 to StringLength);
+  type string_table is array (1 to NumOfStrings) of str16;
+
+  constant string_array: string_table :=
+    ( "This is string 1"
+      ,"__Hello  World__"
+      ,"This is string " & "3"
+      ,"_Bird is a word_"
+      ,"_Goodbye (ciao)_"
+      );
+
+  type ft is file of string;
+
+begin
+  doit: process
+    file file_desc : ft;
+  begin
+    file_open(file_desc, "fopen_test_3.out", write_mode);
+    for i in NumOfStrings downto 1 loop
+      write(file_desc, string_array(i));
+    end loop;
+    file_close(file_desc);
+
+    file_open(file_desc, "fopen_test_3.out", write_mode);
+    for i in 1 to NumOfStrings loop
+      write(file_desc, string_array(i));
+    end loop;
+    file_close(file_desc);
+
+    wait;
+  end process; 
+
+end test0;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/integer_array_write.vhd b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/integer_array_write.vhd
new file mode 100644
index 0000000..37cbfe7
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/integer_array_write.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity integer_array_write is
+end integer_array_write;
+
+architecture test0 of integer_array_write is
+
+  type integer_array_type is array (0 to 9) of integer;
+
+  constant integer_array : integer_array_type := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
+  type integer_array_file is file of integer_array_type;
+
+begin
+  doit: process
+    file fileout : integer_array_file open write_mode is "integer_array_write.out";
+  begin
+    write(fileout, integer_array);
+
+    assert false
+      report "PASSED TEST: integer_array_write."
+      severity note;
+    wait;
+  end process;
+
+end test0;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/record_write.vhd b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/record_write.vhd
new file mode 100644
index 0000000..4b05363
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/record_write.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity record_write is
+end record_write;
+
+architecture test0 of record_write is
+
+  type record_structure is record
+    a_boolean : boolean;
+    a_bit : bit;
+    a_character : character;
+    a_severity : severity_level;
+    a_string : string(0 to 10);
+    a_integer : integer;
+    a_real : real;
+  end record;
+
+  constant test_record : record_structure :=
+    ( false,
+      '1',
+      'T',
+      note,
+      "Hello World",
+      45,
+      10.5
+      );
+
+  type record_file is file of record_structure;
+
+begin
+  doit: process
+    file fileout : record_file open write_mode is "record_write.out";
+  begin
+    write(fileout,test_record);
+
+    assert false
+      report "PASSED TEST: record_write."
+      severity note;
+    wait;
+  end process;
+
+end test0;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/string_array_write.vhd b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/string_array_write.vhd
new file mode 100644
index 0000000..f6ffd7f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/string_array_write.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity string_array_write is
+end string_array_write;
+
+architecture test0 of string_array_write is
+  subtype str16 is string (1 to 16);
+  type string_table is array (natural range <>) of str16;
+  constant string_array : string_table :=
+    ( "This is string 1"
+      ,"__Hello  World__"
+      ,"This is string 3"
+      ,"_Bird is a word_"
+      ,"_Goodbye (ciao)_"
+      );
+
+  type string_array_file is file of string_table;
+begin
+  doit: process
+    file fileout : string_array_file open write_mode is "string_array_write.out";
+  begin
+    write(fileout,string_array);
+
+    assert false
+      report "PASSED TEST: string_array_write."
+      severity note;
+    wait;
+  end process;
+
+end test0;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/write_bit_vector.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/write_bit_vector.vhdl
new file mode 100644
index 0000000..0165795
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/textio/write/write_bit_vector.vhdl
@@ -0,0 +1,43 @@
+
+-- Copyright (C) Clifton Labs.  All rights reserved.
+
+-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
+-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
+-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT.  CLIFTON LABS SHALL NOT BE
+-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
+-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the GNU General Public License as published
+-- by the Free Software Foundation; version 2 of the License.
+
+-- You should have received a copy of the GNU General Public License along
+-- with this software; if not, write to the Free Software Foundation, Inc.,
+-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+entity write_bit_vector_test is
+end write_bit_vector_test;
+
+use std.textio.all;
+
+architecture test0 of write_bit_vector_test is
+
+begin 
+  doit: process
+    variable outline : line;
+  begin  
+    write( outline, bit_vector'("1010") );
+    writeline( output, outline );
+
+    report "PASSED TEST: write_bit_vector."
+      severity NOTE;
+
+    wait;
+  end process;
+  
+end test0;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/character-index-constant.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/character-index-constant.vhdl
new file mode 100644
index 0000000..6c031dd
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/character-index-constant.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+  type     int_array_char_index_unconstrained is array (character range <>) of integer;
+  subtype  int_array_char_index_constrained   is int_array_char_index_unconstrained('0' to '9');
+  CONSTANT my_constant : int_array_char_index_constrained := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 );
+begin  -- only
+  p: process
+  begin  -- process p
+    assert my_constant('0') = 0 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+  wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/colors_2d_array.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/colors_2d_array.vhdl
new file mode 100644
index 0000000..c3da438
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/colors_2d_array.vhdl
@@ -0,0 +1,29 @@
+entity test is
+end test;
+
+architecture only of test is
+  type colors is ( 'R', 'O', 'Y', 'G', 'B', 'I', 'V', 'X' );
+  type color_table_t is array ( 1 to 3, 1 to 3 ) of colors;
+  CONSTANT primary_table : color_table_t := (
+    -- 'R' 'B' 'Y'
+    ( 'R', 'V', 'O' ),  -- 'R'
+    ( 'V', 'B', 'G' ),  -- 'B'
+    ( 'O', 'G', 'Y' )   -- 'Y'
+  );
+begin  -- only
+  test: process
+  begin  -- process test
+    assert primary_table( 1, 1 ) = 'R' report "TEST FAILED" severity failure;
+    assert primary_table( 1, 2 ) = 'V' report "TEST FAILED" severity failure;
+    assert primary_table( 1, 3 ) = 'O' report "TEST FAILED" severity failure;
+    assert primary_table( 2, 1 ) = 'V' report "TEST FAILED" severity failure;
+    assert primary_table( 2, 2 ) = 'B' report "TEST FAILED" severity failure;
+    assert primary_table( 2, 3 ) = 'G' report "TEST FAILED" severity failure;
+    assert primary_table( 3, 1 ) = 'O' report "TEST FAILED" severity failure;
+    assert primary_table( 3, 2 ) = 'G' report "TEST FAILED" severity failure;
+    assert primary_table( 3, 3 ) = 'Y' report "TEST FAILED" severity failure;
+
+    report "TEST PASSED";
+    wait;
+  end process test;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/integer-array-using-tick-range.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/integer-array-using-tick-range.vhdl
new file mode 100644
index 0000000..1e8b0ab
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/integer-array-using-tick-range.vhdl
@@ -0,0 +1,21 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+p: process
+  type integerArray is array (0 to 9) of integer;
+  variable myArray : integerArray;
+begin  -- process p
+  for i in myArray'range loop
+    myArray(i) := i;
+  end loop;  -- i
+  for i in myArray'range loop
+    assert myArray(i) = i report "TEST FAILED myArray(i) = " &
+      integer'image(myArray(i)) & " - was supposed to be " &
+      integer'image(i) severity FAILURE;
+  end loop;  -- i
+  report "TEST PASSED" severity NOTE;
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/simple-integer-array.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/simple-integer-array.vhdl
new file mode 100644
index 0000000..f5bc596
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/simple-integer-array.vhdl
@@ -0,0 +1,22 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+p: process
+  type integerArray is array (0 to 2) of integer;
+  variable myArray : integerArray;
+begin  -- process p
+  myArray(0) := 0;
+  myArray(1) := 1;    
+  myArray(2) := 2;
+
+  assert myArray(0) = 0 report "TEST FAILED" severity FAILURE;
+  assert myArray(1) = 1 report "TEST FAILED" severity FAILURE;
+  assert myArray(2) = 2 report "TEST FAILED" severity FAILURE;
+
+  report "TEST PASSED" severity NOTE;
+  
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/subprogram-dynamic-type.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/subprogram-dynamic-type.vhdl
new file mode 100644
index 0000000..a2f5371
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/subprogram-dynamic-type.vhdl
@@ -0,0 +1,20 @@
+entity test is
+end test;
+
+architecture only of test is
+  procedure proc (
+    constant a : in bit_vector;
+    constant l : in integer ) is
+    type dyn is range a'left downto 0;
+  begin
+    assert dyn'left = l report "TEST FAILED" severity FAILURE;
+  end proc;
+begin  -- only
+  doit: process
+  begin  -- process doit
+    proc( "0000", 3 );
+    proc( "00000", 4 );
+    report "TEST PASSED";
+    wait;
+  end process doit;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/unconstrained_argument.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/unconstrained_argument.vhdl
new file mode 100644
index 0000000..d530af9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/array-types/unconstrained_argument.vhdl
@@ -0,0 +1,21 @@
+entity test is
+end test;
+
+architecture only of test is
+  function get_left (
+    constant input_array : bit_vector)
+    return bit is
+  begin
+    return input_array(input_array'left);
+  end get_left;
+begin  -- only
+  process
+    constant argument1 : bit_vector( 0 to 3 ) := "0000";    
+    constant argument2 : bit_vector( 0 to 4 ) := "11111";
+  begin  -- process
+    assert get_left( argument1 ) = '0' report "TEST FAILED" severity failure;
+    assert get_left( argument2 ) = '1' report "TEST FAILED" severity failure;
+    report "TEST PASSED";
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/enumeration-types/std-enums-test.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/enumeration-types/std-enums-test.vhdl
new file mode 100644
index 0000000..9350a98
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/enumeration-types/std-enums-test.vhdl
@@ -0,0 +1,151 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+  doit: process
+  begin  -- process
+    assert( character'pos(NUL) = 0 ) report "TEST FAILED" severity failure;
+    assert ( character'pos(SOH) = 1)  report "TEST FAILED" severity failure;
+    assert ( character'pos(STX) = 2)  report "TEST FAILED" severity failure;
+    assert ( character'pos(ETX) = 3)  report "TEST FAILED" severity failure;
+    assert ( character'pos(EOT) = 4)  report "TEST FAILED" severity failure;
+    assert ( character'pos(ENQ) = 5)  report "TEST FAILED" severity failure;
+    assert ( character'pos(ACK) = 6)  report "TEST FAILED" severity failure;
+    assert ( character'pos(BEL) = 7)  report "TEST FAILED" severity failure;
+    assert ( character'pos(BS ) = 8)  report "TEST FAILED" severity failure;
+    assert ( character'pos(HT ) = 9)  report "TEST FAILED" severity failure;
+    assert ( character'pos(LF ) = 10)  report "TEST FAILED" severity failure;
+    assert ( character'pos(VT ) = 11)  report "TEST FAILED" severity failure;
+    assert ( character'pos(FF ) = 12)  report "TEST FAILED" severity failure;
+    assert ( character'pos(CR ) = 13)  report "TEST FAILED" severity failure;
+    assert ( character'pos(SO ) = 14)  report "TEST FAILED" severity failure;
+    assert ( character'pos(SI ) = 15)  report "TEST FAILED" severity failure;
+    assert ( character'pos(DLE) = 16)  report "TEST FAILED" severity failure;
+    assert ( character'pos(DC1) = 17)  report "TEST FAILED" severity failure;
+    assert ( character'pos(DC2) = 18)  report "TEST FAILED" severity failure;
+    assert ( character'pos(DC3) = 19)  report "TEST FAILED" severity failure;
+    assert ( character'pos(DC4) = 20)  report "TEST FAILED" severity failure;
+    assert ( character'pos(NAK) = 21)  report "TEST FAILED" severity failure;
+    assert ( character'pos(SYN) = 22)  report "TEST FAILED" severity failure;
+    assert ( character'pos(ETB) = 23)  report "TEST FAILED" severity failure;
+    assert ( character'pos(CAN) = 24)  report "TEST FAILED" severity failure;
+    assert ( character'pos(EM ) = 25)  report "TEST FAILED" severity failure;
+    assert ( character'pos(SUB) = 26)  report "TEST FAILED" severity failure;
+    assert ( character'pos(ESC) = 27)  report "TEST FAILED" severity failure;
+    assert ( character'pos(FSP) = 28)  report "TEST FAILED" severity failure;
+    assert ( character'pos(GSP) = 29)  report "TEST FAILED" severity failure;
+    assert ( character'pos(RSP) = 30)  report "TEST FAILED" severity failure;
+    assert ( character'pos(USP) = 31)  report "TEST FAILED" severity failure;
+    assert ( character'pos(' ') = 32)  report "TEST FAILED" severity failure;
+    assert ( character'pos('!') = 33)  report "TEST FAILED" severity failure;
+    assert ( character'pos('"') = 34)  report "TEST FAILED" severity failure;
+    assert ( character'pos('#') = 35)  report "TEST FAILED" severity failure;
+    assert ( character'pos('$') = 36)  report "TEST FAILED" severity failure;
+    assert ( character'pos('%') = 37)  report "TEST FAILED" severity failure;
+    assert ( character'pos('&') = 38)  report "TEST FAILED" severity failure;
+    assert ( character'pos(''') = 39)  report "TEST FAILED" severity failure;
+    assert ( character'pos('(') = 40)  report "TEST FAILED" severity failure;
+    assert ( character'pos(')') = 41)  report "TEST FAILED" severity failure;
+    assert ( character'pos('*') = 42)  report "TEST FAILED" severity failure;
+    assert ( character'pos('+') = 43)  report "TEST FAILED" severity failure;
+    assert ( character'pos(',') = 44)  report "TEST FAILED" severity failure;
+    assert ( character'pos('-') = 45)  report "TEST FAILED" severity failure;
+    assert ( character'pos('.') = 46)  report "TEST FAILED" severity failure;
+    assert ( character'pos('/') = 47)  report "TEST FAILED" severity failure;
+    assert ( character'pos('0') = 48)  report "TEST FAILED" severity failure;
+    assert ( character'pos('1') = 49)  report "TEST FAILED" severity failure;
+    assert ( character'pos('2') = 50)  report "TEST FAILED" severity failure;
+    assert ( character'pos('3') = 51)  report "TEST FAILED" severity failure;
+    assert ( character'pos('4') = 52)  report "TEST FAILED" severity failure;
+    assert ( character'pos('5') = 53)  report "TEST FAILED" severity failure;
+    assert ( character'pos('6') = 54)  report "TEST FAILED" severity failure;
+    assert ( character'pos('7') = 55)  report "TEST FAILED" severity failure;
+    assert ( character'pos('8') = 56)  report "TEST FAILED" severity failure;
+    assert ( character'pos('9') = 57)  report "TEST FAILED" severity failure;
+    assert ( character'pos(':') = 58)  report "TEST FAILED" severity failure;
+    assert ( character'pos(';') = 59)  report "TEST FAILED" severity failure;
+    assert ( character'pos('<') = 60)  report "TEST FAILED" severity failure;
+    assert ( character'pos('=') = 61)  report "TEST FAILED" severity failure;
+    assert ( character'pos('>') = 62)  report "TEST FAILED" severity failure;
+    assert ( character'pos('?') = 63)  report "TEST FAILED" severity failure;
+    assert ( character'pos('@') = 64)  report "TEST FAILED" severity failure;
+    assert ( character'pos('A') = 65)  report "TEST FAILED" severity failure;
+    assert ( character'pos('B') = 66)  report "TEST FAILED" severity failure;
+    assert ( character'pos('C') = 67)  report "TEST FAILED" severity failure;
+    assert ( character'pos('D') = 68)  report "TEST FAILED" severity failure;
+    assert ( character'pos('E') = 69)  report "TEST FAILED" severity failure;
+    assert ( character'pos('F') = 70)  report "TEST FAILED" severity failure;
+    assert ( character'pos('G') = 71)  report "TEST FAILED" severity failure;
+    assert ( character'pos('H') = 72)  report "TEST FAILED" severity failure;
+    assert ( character'pos('I') = 73)  report "TEST FAILED" severity failure;
+    assert ( character'pos('J') = 74)  report "TEST FAILED" severity failure;
+    assert ( character'pos('K') = 75)  report "TEST FAILED" severity failure;
+    assert ( character'pos('L') = 76)  report "TEST FAILED" severity failure;
+    assert ( character'pos('M') = 77)  report "TEST FAILED" severity failure;
+    assert ( character'pos('N') = 78)  report "TEST FAILED" severity failure;
+    assert ( character'pos('O') = 79)  report "TEST FAILED" severity failure;
+    assert ( character'pos('P') = 80)  report "TEST FAILED" severity failure;
+    assert ( character'pos('Q') = 81)  report "TEST FAILED" severity failure;
+    assert ( character'pos('R') = 82)  report "TEST FAILED" severity failure;
+    assert ( character'pos('S') = 83)  report "TEST FAILED" severity failure;
+    assert ( character'pos('T') = 84)  report "TEST FAILED" severity failure;
+    assert ( character'pos('U') = 85)  report "TEST FAILED" severity failure;
+    assert ( character'pos('V') = 86)  report "TEST FAILED" severity failure;
+    assert ( character'pos('W') = 87)  report "TEST FAILED" severity failure;
+    assert ( character'pos('X') = 88)  report "TEST FAILED" severity failure;
+    assert ( character'pos('Y') = 89)  report "TEST FAILED" severity failure;
+    assert ( character'pos('Z') = 90)  report "TEST FAILED" severity failure;
+    assert ( character'pos('[') = 91)  report "TEST FAILED" severity failure;
+    assert ( character'pos('\') = 92)  report "TEST FAILED" severity failure;
+    assert ( character'pos(']') = 93)  report "TEST FAILED" severity failure;
+    assert ( character'pos('^') = 94)  report "TEST FAILED" severity failure;
+    assert ( character'pos('_') = 95)  report "TEST FAILED" severity failure;
+    assert ( character'pos('`') = 96)  report "TEST FAILED" severity failure;
+    assert ( character'pos('a') = 97)  report "TEST FAILED" severity failure;
+    assert ( character'pos('b') = 98)  report "TEST FAILED" severity failure;
+    assert ( character'pos('c') = 99)  report "TEST FAILED" severity failure;
+    assert ( character'pos('d') = 100)  report "TEST FAILED" severity failure;
+    assert ( character'pos('e') = 101)  report "TEST FAILED" severity failure;
+    assert ( character'pos('f') = 102)  report "TEST FAILED" severity failure;
+    assert ( character'pos('g') = 103)  report "TEST FAILED" severity failure;
+    assert ( character'pos('h') = 104)  report "TEST FAILED" severity failure;
+    assert ( character'pos('i') = 105)  report "TEST FAILED" severity failure;
+    assert ( character'pos('j') = 106)  report "TEST FAILED" severity failure;
+    assert ( character'pos('k') = 107)  report "TEST FAILED" severity failure;
+    assert ( character'pos('l') = 108)  report "TEST FAILED" severity failure;
+    assert ( character'pos('m') = 109)  report "TEST FAILED" severity failure;
+    assert ( character'pos('n') = 110)  report "TEST FAILED" severity failure;
+    assert ( character'pos('o') = 111)  report "TEST FAILED" severity failure;
+    assert ( character'pos('p') = 112)  report "TEST FAILED" severity failure;
+    assert ( character'pos('q') = 113)  report "TEST FAILED" severity failure;
+    assert ( character'pos('r') = 114)  report "TEST FAILED" severity failure;
+    assert ( character'pos('s') = 115)  report "TEST FAILED" severity failure;
+    assert ( character'pos('t') = 116)  report "TEST FAILED" severity failure;
+    assert ( character'pos('u') = 117)  report "TEST FAILED" severity failure;
+    assert ( character'pos('v') = 118)  report "TEST FAILED" severity failure;
+    assert ( character'pos('w') = 119)  report "TEST FAILED" severity failure;
+    assert ( character'pos('x') = 120)  report "TEST FAILED" severity failure;
+    assert ( character'pos('y') = 121)  report "TEST FAILED" severity failure;
+    assert ( character'pos('z') = 122)  report "TEST FAILED" severity failure;
+    assert ( character'pos('{') = 123)  report "TEST FAILED" severity failure;
+    assert ( character'pos('|') = 124)  report "TEST FAILED" severity failure;
+    assert ( character'pos('}') = 125)  report "TEST FAILED" severity failure;
+    assert ( character'pos('~') = 126)  report "TEST FAILED" severity failure;
+    assert ( character'pos(DEL) = 127)  report "TEST FAILED" severity failure;
+    assert ( character'pos(character'right) = 255)  report "TEST FAILED" severity failure;
+    assert (bit'pos('0') = 0)  report "TEST FAILED" severity failure;
+    assert (bit'pos('1') = 1)  report "TEST FAILED" severity failure;
+    assert (bit'pos(bit'right) = 1)  report "TEST FAILED" severity failure;
+    assert (boolean'pos(false) = 0)  report "TEST FAILED" severity failure;
+    assert (boolean'pos(true)  = 1)  report "TEST FAILED" severity failure;
+    assert (boolean'pos(boolean'right) = 1)  report "TEST FAILED" severity failure;
+    assert (severity_level'pos(NOTE)    = 0)  report "TEST FAILED" severity failure;
+    assert (severity_level'pos(WARNING) = 1)  report "TEST FAILED" severity failure;
+    assert (severity_level'pos(ERROR)   = 2)  report "TEST FAILED" severity failure;
+    assert (severity_level'pos(FAILURE) = 3)  report "TEST FAILED" severity failure;
+    assert ( severity_level'pos(severity_level'right) = 3 ) report "TEST FAILED" severity failure;
+    report "TEST PASSED";
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/integer-types/resolved-integer-type.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/integer-types/resolved-integer-type.vhdl
new file mode 100644
index 0000000..2a55fe2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/integer-types/resolved-integer-type.vhdl
@@ -0,0 +1,44 @@
+entity test is
+end test;
+
+architecture only of test is
+  type integer_array is array ( natural range <> ) of integer;
+  
+  function return_biggest ( inputs : integer_array )
+    return integer is
+    variable retval : integer := integer'left;
+  begin
+    for i in inputs'range loop
+      if inputs(i) > retval then
+        retval := inputs(i);
+      end if;
+    end loop;  -- i
+    return retval;
+  end return_biggest;
+    
+  subtype biggest_wins is return_biggest integer;
+
+  signal common : biggest_wins;
+  
+begin  -- only
+
+  p1 : process
+  begin
+    common <= 1 after 1 ns;
+    wait;
+  end process;    
+
+  p2 : process
+  begin
+    common <= 1 after 1 ns;
+    wait;
+  end process;
+
+  test: process
+  begin
+    wait for 2 ns;
+    assert common = 1 report "TEST FAILED" severity failure;
+    wait;
+  end process;    
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/integer-types/subprogram-dynamic-type.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/integer-types/subprogram-dynamic-type.vhdl
new file mode 100644
index 0000000..92f5347
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/integer-types/subprogram-dynamic-type.vhdl
@@ -0,0 +1,26 @@
+entity test is
+end test;
+
+architecture only of test is
+  procedure proc ( constant l : in integer;
+                   constant r : in integer ) is
+    type dyn is range l to r;
+    constant x : dyn;
+  begin
+    
+  if r = 3 then
+    assert x = 1 report "TEST FAILED" severity FAILURE;
+  elsif r = 42 then
+    assert x = 0 report "TEST FAILED" severity FAILURE;
+  end if;
+    
+  end proc;
+begin  -- only
+  doit: process
+  begin  -- process doit
+    proc( 1, 3 );
+    proc( 0, 42 );
+    report "TEST PASSED";
+    wait;
+  end process doit;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/date-record.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/date-record.vhdl
new file mode 100644
index 0000000..ea7b089
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/date-record.vhdl
@@ -0,0 +1,25 @@
+entity test is
+end test;
+
+
+architecture only of test is
+
+  type month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
+  type date IS
+    record
+      day   : integer range 1 to 31;
+      month : month_name;
+      year  : integer range 0 to 4000;
+    end record;
+
+begin  -- only
+  p: process
+    constant christmas : date := ( 25, Dec, 0 );
+  begin  -- process p
+    assert christmas.day = 25 report "TEST FAILED" severity FAILURE;
+    assert christmas.month = Dec report "TEST FAILED" severity FAILURE;
+    assert christmas.year = 0 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+    wait;
+  end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/integer-record-aggregate-init.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/integer-record-aggregate-init.vhdl
new file mode 100644
index 0000000..dbd5170
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/integer-record-aggregate-init.vhdl
@@ -0,0 +1,21 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+p: process
+  type integerRecord is record
+                           foo : integer;
+                           bar : integer;
+                         end record;
+  variable myRecord : integerRecord;
+begin  -- process p
+  myRecord := ( 0, 1 );
+
+  assert myRecord.foo = 0 report "TEST FAILED - 0" severity FAILURE;
+  assert myRecord.bar = 1 report "TEST FAILED - 1" severity FAILURE;
+  report "TEST PASSED" severity NOTE;
+  
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/simple-integer-record.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/simple-integer-record.vhdl
new file mode 100644
index 0000000..b040eb8
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/record-types/simple-integer-record.vhdl
@@ -0,0 +1,22 @@
+entity test is
+end test;
+
+architecture only of test is
+begin  -- only
+p: process
+  type integerRecord is record
+                           foo : integer;
+                           bar : integer;
+                         end record;
+  variable myRecord : integerRecord;
+begin  -- process p
+  myRecord.foo := 0;
+  myRecord.bar := 1;    
+
+  assert myRecord.foo = 0 report "TEST FAILED" severity FAILURE;
+  assert myRecord.bar = 1 report "TEST FAILED" severity FAILURE;
+  report "TEST PASSED" severity NOTE;
+  
+  wait;
+end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/simple-subtypes.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/simple-subtypes.vhdl
new file mode 100644
index 0000000..a3e127e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/types/simple-subtypes.vhdl
@@ -0,0 +1,41 @@
+entity test is
+end test;
+
+architecture only of test is
+
+begin  -- only
+  doit: process
+    subtype tboolean        is boolean        range FALSE to TRUE;
+    subtype tbit            is bit            range '0'   to '1';   
+    subtype tcharacter      is character      range 'A'   to 'Z';
+    subtype tseverity_level is severity_level range NOTE  to ERROR;
+    subtype tinteger        is integer        range 1111  to 2222;
+    subtype treal           is real           range 1.11  to 2.22;
+    subtype ttime           is time           range 1 ns  to 1 hr;
+    subtype tnatural        is natural        range 100   to 200;
+    subtype tpositive       is positive       range 1000  to 2000;
+
+    variable k1  : tboolean;
+    variable k2  : tbit;
+    variable k3  : tcharacter;
+    variable k4  : tseverity_level;
+    variable k5  : tinteger;
+    variable k6  : treal;
+    variable k7  : ttime;
+    variable k8  : tnatural;
+    variable k9  : tpositive;
+    
+  begin  -- process doit
+    assert( k1 = tboolean'left        ) report "TEST FAILED" severity failure;
+    assert( k2 = tbit'left            ) report "TEST FAILED" severity FAILURE;
+    assert( k3 = tcharacter'left      ) report "TEST FAILED" severity FAILURE;
+    assert( k4 = tseverity_level'left ) report "TEST FAILED" severity FAILURE;
+    assert( k5 = tinteger'left        ) report "TEST FAILED" severity FAILURE;
+    assert( k6 = treal'left           ) report "TEST FAILED" severity FAILURE;
+    assert( k7 = ttime'left           ) report "TEST FAILED" severity FAILURE;
+    assert( k8 = tnatural'left        ) report "TEST FAILED" severity FAILURE;
+    assert( k9 = tpositive'left       ) report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED";
+    wait;
+  end process doit;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/integer-variable-persist-across-activations.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/integer-variable-persist-across-activations.vhdl
new file mode 100644
index 0000000..4cccc08
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/integer-variable-persist-across-activations.vhdl
@@ -0,0 +1,28 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+  signal clock : bit;
+  signal last_x : integer := 0;
+begin  -- only
+  process (clock)
+    variable x : integer := 0;
+  begin  -- process
+    last_x <= x;
+    x := x + 1;
+    wait for 1 fs;
+    assert x > last_x report "TEST FAILED" severity FAILURE;
+    assert x > 0 report "TEST FAILED" severity FAILURE;
+    report "TEST PASSED" severity NOTE;
+  end process;
+
+  process
+  begin  -- process
+    clock <= '1' after 1 ns,
+             '0' after 2 ns,
+             '1' after 3 ns;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-enumeration-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-enumeration-assign.vhdl
new file mode 100644
index 0000000..e324a39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-enumeration-assign.vhdl
@@ -0,0 +1,16 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : boolean := false;
+  begin  -- process
+    x := true;
+    assert x = true report "TEST FAILED - x does not equal true" severity failure;
+    assert x /= true report "TEST PASSED" severity note;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-integer-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-integer-assign.vhdl
new file mode 100644
index 0000000..265cadb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-integer-assign.vhdl
@@ -0,0 +1,16 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : integer := 0;
+  begin  -- process
+    x := 1;
+    assert x = 1 report "TEST FAILED - x does not equal 1" severity failure;
+    assert x /= 1 report "TEST PASSED" severity note;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-integer-initialize.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-integer-initialize.vhdl
new file mode 100644
index 0000000..fc2ded3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-integer-initialize.vhdl
@@ -0,0 +1,15 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin  -- only
+  process
+    variable x : integer := 0;
+  begin  -- process
+    assert x = 0 report "TEST FAILED - x does not equal 1" severity failure;
+    report "TEST PASSED" severity note;
+    wait;
+  end process;
+end only;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/compliant.exp b/testsuite/vests/vhdl-ams/ad-hoc/compliant.exp
new file mode 100644
index 0000000..6ad511e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/compliant.exp
@@ -0,0 +1,31 @@
+
+# Copyright (C) Clifton Labs, Inc  All rights reserved.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  
+
+# Please email any bugs, comments, and/or additions to this file to:
+# vests@cliftonlabs.com
+
+setup_test_group "Ad-hoc:VHDL-AMS Compliant Cases" "vhdl-ams"
+
+set dir_prefix_length [expr [string length ${subdir}] + 3]
+
+foreach local_test_name [find ${subdir} *.ams] {
+    verbose "Running test at ./[string range ${local_test_name} [expr ${dir_prefix_length} - 2] end]" 2
+    run_compliant_test ./[string range ${local_test_name} [expr [${dir_prefix_length} - 2] end]
+    delete_lib work
+}
+
+end_test_group
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_npn_gen.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_npn_gen.ams
new file mode 100644
index 0000000..c00e105
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_npn_gen.ams
@@ -0,0 +1,143 @@
+
+-- Copyright (C) 1999-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bjt_npn_gen.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+--------------------------------------------------------------------
+--  Ebers-moll Model for a transistor                             --
+--  VHDL-AMS Implementation                                       --
+--  Developed at the Distributed Processing Lab at the University --
+--  of Cincinnati                                                 --
+--  by VishwaShanth Kasula on May 10, 1999                        --
+--------------------------------------------------------------------
+--  Circuit Topology                                              --
+--  BJT Ebers-Moll static model
+--  Testbench Ckt to evaluate the DC operatioing point of an npn BJT,
+--  Sedra smith page no. 152, fig 4.9
+--------------------------------------------------------------------
+-- Three regions are simulated
+-- Active region, vbb = 4.0 V
+-- Saturation region, vbb = 6.0 V
+-- Cutoff region, vbb = 0.0;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+
+use work.electricalsystem.all;
+
+entity bjt_npn is
+  generic(isat : real := 1.0e-16;         -- Saturation Current
+          bf : real := 100.0;           -- Ideal maximus forward current
+          br : real := 1.0;             -- ideal maximum reverse current
+          rb : real := 1.0e-5;          -- Base resistance
+          rc : real := 1.0e-5;          -- collector resistance
+          re : real := 1.0e-5;          -- emmiter resistance
+          vaf : real := 100.0);         -- Forward Early Voltage
+  port(terminal e,b,c : electrical);
+end bjt_npn;
+
+architecture structure of bjt_npn is
+  terminal b1, c1, e1 : electrical;
+  quantity vbo across ib through b to b1;
+  quantity vco across ic through c to c1;
+  quantity veo across ie through e to e1;
+  quantity vct across Ict through c1 to e1;--current source
+  quantity vbe across ibe through b1 to e1;
+  quantity vbc across ibc through b1 to c1;
+  quantity vce : real := 1.0;           -- used to calculate VCE
+  constant gmin : real := 1.0e-12;      -- condutsnce in parallel with every pn junction
+  constant vt : real := 0.02589; -- thermal voltage
+ 
+begin
+  brk : break vbe => 1.0, vbc => -1.0;
+
+  diodecond1 : if(vbe > -5.0*vt) use
+    diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf;
+  elsif(vbe <= -5.0*vt ) use
+    diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf;
+  end use;
+  diodecond2 : if(vbc > -5.0*vt) use
+    diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br;
+  elsif(vbc <= -5.0*vt) use
+    diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br;
+  end use;
+  bres : vbo == ib * 1.0e-6;
+  cres : vco == ic * 1.0e-6;
+  eres : veo == ie * 1.0e-6;
+  kcl_eqn : ie == -1.0*(ib + ic);
+  vcevolt : vce == vbe - vbc;
+  ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf));
+  
+end architecture structure;
+
+
+--*****************************************************
+--TEST BENCH
+use std.textio.all;
+use work.electricalsystem.all;
+
+entity bjt_testbench is
+end bjt_testbench;
+
+architecture structure of bjt_testbench is
+  terminal t1, t2, t3, t4 : electrical ;
+  component bjt_npn_comp
+    generic(isat : real := 1.0e-16;         -- Saturation Current
+            bf : real := 100.0;           -- Ideal maximus forward current
+            br : real := 1.0;             -- ideal maximum reverse current
+            rb : real := 1.0e-5;          -- Base resistance
+            rc : real := 1.0e-5;          -- collector resistance
+            re : real := 1.0e-5;          -- emmiter resistance
+            vaf : real := 100.0);         -- Forward Early Voltage
+    port(terminal e,b,c : electrical);	  
+  end component;
+  for all : bjt_npn_comp use entity work.bjt_npn(structure);
+  
+  quantity vcc across icc through t1 to electrical'reference;
+  quantity vrc across irc through t1 to t2;
+  quantity vbb across ibb through t3 to electrical'reference;
+  quantity vre across ire through t4 to electrical'reference;
+  
+begin
+   
+   bjt : bjt_npn_comp
+     generic map (isat => 1.8104e-15, vaf => 100.0)
+     port map(t4,t3,t2);
+   emres : vre == ire * 3.3e3;
+   ccurr : vcc == 10.0;
+   ecurr : vbb == 6.0;
+   cores : vrc == irc * 4.7e3;
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_pnp_gen.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_pnp_gen.ams
new file mode 100644
index 0000000..a6a97c5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/bjt_pnp_gen.ams
@@ -0,0 +1,139 @@
+
+-- Copyright (C) 1999-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bjt_pnp_gen.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-----------------------------------------------------------------------------
+--  Ebers-moll Model for a transistor                             --
+--  VHDL-AMS Implementation                                       --
+--  Developed at the Distributed Processing Lab at the University --
+--  of Cincinnati                                                 --
+--  by VishwaShanth Kasula on May 10, 1999                        --
+--------------------------------------------------------------------
+--  Circuit Topology                                              --
+--  BJT Ebers-Moll static model
+--  Testbench Ckt to evaluate the DC operatioing point of an pnp BJT,
+--  Sedra smith page no. 155, fig 4.11
+--------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+
+use work.electricalsystem.all;
+
+entity bjt_pnp is
+  generic(isat : real := 1.0e-16;         -- Saturation Current
+          bf : real := 100.0;           -- Ideal maximus forward current
+          br : real := 1.0;             -- ideal maximum reverse current
+          rb : real := 1.0e-5;          -- Base resistance
+          rc : real := 1.0e-5;          -- collector resistance
+          re : real := 1.0e-5;          -- emmiter resistance
+          vaf : real := 100.0);         -- Forward Early Voltage
+  port(terminal e,b,c : electrical);
+end bjt_pnp;
+
+architecture structure of bjt_pnp is
+  terminal b1, c1, e1 : electrical;
+  quantity vbo across ib through b1 to b;
+  quantity vco across ic through c1 to c;
+  quantity veo across ie through e1 to e;
+  quantity vct across Ict through e1 to c1;--current source
+  quantity vbe across ibe through e1 to b1;
+  quantity vbc across ibc through c1 to b1;
+  quantity vce : real := 1.0;           -- used to calculate VCE
+  constant gmin : real := 1.0e-12;      -- condutsnce in parallel with every pn junction
+  constant vt : real := 0.02589; -- thermal voltage
+ 
+begin
+  brk : break vbe => 1.0, vbc => -1.0;
+
+  diodecond1 : if(vbe > -5.0*vt) use
+    diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf;
+  elsif(vbe <= -5.0*vt ) use
+    diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf;
+  end use;
+  diodecond2 : if(vbc > -5.0*vt) use
+    diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br;
+  elsif(vbc <= -5.0*vt) use
+    diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br;
+  end use;
+  bres : vbo == ib * 1.0e-6;
+  cres : vco == ic * 1.0e-6;
+  eres : veo == ie * 1.0e-6;
+  kcl_eqn : ie == -1.0*(ib + ic);
+  vcevolt : vce == vbe - vbc;
+  ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf));
+  
+end architecture structure;
+
+
+--*****************************************************
+--TEST BENCH
+use std.textio.all;
+use work.electricalsystem.all;
+
+entity bjt_testbench is
+end bjt_testbench;
+
+architecture structure of bjt_testbench is
+  terminal t1, t2, t3, t4 : electrical ;
+  component bjt_pnp_comp
+    generic(isat : real := 1.0e-16;         -- Saturation Current
+            bf : real := 100.0;           -- Ideal maximus forward current
+            br : real := 1.0;             -- ideal maximum reverse current
+            rb : real := 1.0e-5;          -- Base resistance
+            rc : real := 1.0e-5;          -- collector resistance
+            re : real := 1.0e-5;          -- emmiter resistance
+            vaf : real := 100.0);         -- Forward Early Voltage
+    port(terminal e,b,c : electrical);	  
+  end component;
+  for all : bjt_pnp_comp use entity work.bjt_pnp(structure);
+  
+  quantity vcc across icc through t4 to electrical'reference;
+  quantity vrc across irc through t3 to t4;
+  quantity vee across iee through t1 to electrical'reference;
+  quantity vre across ire through t1 to t2;
+  
+begin
+   
+   bjt : bjt_pnp_comp
+     generic map (isat => 1.8104e-15)
+     port map(t2,ground,t3);
+   emres : vre == ire * 2.0e3;
+   ccurr : vcc == -10.0;
+   ecurr : vee == 10.0;
+   cores : vrc == irc * 1.0e3;
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams
new file mode 100644
index 0000000..5aeb07b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_ramp.ams
@@ -0,0 +1,516 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: static_cmos_inv_ramp.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This ckt is used to find the output characteristics of a cmos inverter
+-- The ckt used here is from sedra and smith's page no. 565, fig  13.13
+-- The mos W/L are according to the model specified in spice using the deck
+-- provided in the book. 
+-- The vgs, resistance is now removed, to avoid the RC effect on the imput.
+-- the ramp input is used 
+
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION POW(X,Y: real) RETURN real;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+
+-----------------------------------------------------------------------
+--                       G        B            D1    1.0 ohm          D
+--                        o      o-----|>|--o---o----/\/\---------o  /\
+--                        |      |          |   |                     |+
+--                   Vgs  <      -     Idsg( )  >                    Vdso
+--                        >      V          |   <                     |-
+--                        |      -          |   |                     |
+--                     S1 o------o--o------------------------------o S1V
+--                                  |
+--                                  >
+--                                  < rs= 1.0 ohm
+--                                  |
+--                                  0 S
+-----------------------------------------------------------------------
+
+----- NMOS 
+--use std.textio.all;
+use work.electricalsystem.all;
+
+entity nmos is
+    generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos
+	    T : real := 300.0;
+	    W : real := 1.0;
+	    L : real := 1.0;
+	    vto : real := 1.0; -- Zero-bais threshold voltage
+	    kp : real := 2.0e-5; -- transcondiuctanec parameter
+	    gamma : real := 0.0; -- body-effect parameter
+	    phi : real := 0.6; -- surface inversion potential
+	    lambda : real := 0.02; -- channel lenght modulation
+	    tox : real := 1.0e-7; -- thin oxide thickness
+	    nsub : real := 0.0; -- Substrate doping
+	    nss : real := 0.0; -- Surface STate density
+	    ld : real := 0.0; -- lateral diffusion;
+	    tpg : real := 1.0; -- Type of Gate material
+	    uo : real := 600.0; -- Surface mobility
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- fliccker noise coefficient
+	    iss : real := 1.0e-14; -- bulk junction saturation current
+	    js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter
+	    pb : real := 0.80; -- bulk junction potential
+	    cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter
+	    mj : real := 0.5; -- bulk junctioin grading coefficient
+	    cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter
+	    mjsw : real := 0.33; -- Perimiter capacitance rading coefficient
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+--  	    cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter
+--  	    cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter
+--  	    cgso : real := 1.5e-10; -- gate-source overlap cap / meter
+	    cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter
+	    cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter
+	    cgso : real := 4.0e-11; -- gate-source overlap cap / meter
+	    rd : real := 1.0; -- drain ohmic resistance
+	    rs : real := 1.0; -- source ohmic resistance
+	    rsh : real := 0.0); -- source and drain sheet resistance
+    port (terminal g,s,d,b : electrical);
+end entity nmos;
+
+architecture behav of nmos is
+  terminal d1, s1 : electrical;
+  quantity vds across idsg through d1 to s1;
+  quantity vdsr across idsr through d1 to d;
+  quantity vgs across igs through g to s1;
+  quantity vbs across ibs through b to s1;
+  quantity vbd across ibd through b to d1;
+-- new quantities added for source resistance
+  quantity vsr across isr through s1 to s;
+  quantity iss, isd : real := 1.0e-12;
+  quantity beta : real := 8.85e-05; -- gain
+  quantity leff : real := 1.0; -- effective length
+  constant gmin : real := 1.0e-12;
+  quantity vth : real := 0.5; -- threshold voltage
+  quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K 
+  --constant k : real := 1.38e-23; -- J/K ..... boltzman constant 
+  -- T = 300 K ............ Absolute temperature
+  --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge
+  constant cox_prime : real := 3.4515e-8; -- oxide capacitance per unit area F/cm2. cox_prime = EOX/TOX
+  quantity cox : real := 3.4515e-8;
+  quantity vds_free : real := 5.0;
+  quantity vgs_free : real := 0.0;
+  constant as : real := 15.0e-12; -- source area
+  constant ad : real := 15.0e-12; -- drain area
+  
+begin
+  ------ Setting initial conditions
+  initreg : break vgs => 0.0, vds => 5.0, vth => 0.5;
+
+  thres_volt : vth == vto + (gamma *(sqrt((2.0*phi)-vbs) - sqrt(phi)));
+  eff_length : leff == L - (2.0*ld);
+  therm_volt : ktq == 2.586e-2 * (T/300.0);
+  sat_scurr : iss == js*as;
+  sat_dcurr : isd == js*ad;
+--  gn : beta == 8.85e-05 * (W/L);
+  gn : beta == kp * ( w/leff);
+--  opn : vdsg == 1.0e9 * idsgi; -- almost open
+  d12_res : vdsr == idsr * rd;
+--  g12res : vgsr == igsr * rs;
+--  g_oup : vgs == igs * 1.0e9;
+--  oup_res : vds == ids * 1.0e9;
+  oup_res : vds_free == vds;
+  inp_res : vgs_free == vgs;
+  gre : vgs == igs * 1.0e9;
+  capeqn : cox == cox_prime * W * Leff; -- cox_prime * W * Leff
+  src_res : isr == vsr * rs;
+
+---- Current is in Micro Amps.
+-- Normal mode
+  ------ Cut off Region
+  regions : if((vgs < vth) and (vds >= 0.0))use
+	gncn : idsg == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif((vds <= (vgs-vth)) and (vgs >= vth) and (vds >= 0.0)) use
+      	gnln : idsg == vds*beta*((vgs_free-vth) - (vds_free/2.0))*(1.0 + lambda*vds_free);
+  ------ Saturation Region
+  elsif((vds > vgs-vth) and (vgs >= vth) and (vds >= 0.0)) use
+     	gnsn : idsg == (beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 + lambda*vds_free);
+
+-- Inversion mode
+  ------ Cut off Region
+  elsif((vgs < vth) and (vds < 0.0))use
+	gnci : idsg == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif(((-1.0*vds) <= (vgs-vth)) and (vgs >= vth) and (vds < 0.0)) use
+      	gnli : idsg == vds*beta*((vgs_free-vth) + (vds_free/2.0))*(1.0 - lambda*vds_free);
+  ------ Saturation Region
+  elsif(((-1.0*vds) > vgs-vth) and (vgs >= vth) and (vds < 0.0)) use
+     	gnsi : idsg == -1.0*(beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 - lambda*vds_free);
+  end use;
+  
+----- Substrate diode equations 
+  initsub : break vbd => 0.0, vbs => 0.0, ibs => 0.0, ibd => 0.0;
+  
+   ----- Substrate to source
+   subcond1 : if(vbs > 0.0) use
+	bulk1 : ibs == ((iss*(exp(vbs/ktq) - 1.0)) + (gmin*vbs));
+   elsif(vbs <= 0.0 ) use
+   	bulk2 : ibs == ((iss*(vbs/ktq)) + (gmin*vbs));
+   end use;
+   ----- Substrate to drain
+   subcond2 : if(vbd > 0.0) use
+	bulk3 : ibd == ((isd*(exp(vbd/ktq) - 1.0)) + (gmin*vbd));
+   elsif(vbd <= 0.0 ) use
+    	bulk4 : ibd == ((isd*(vbd/ktq)) + (gmin*vbd));
+   end use;
+
+end architecture behav; --- of nmos;
+
+
+-----------------------------------------------------------------------
+--                       G        B            D1    1.0 ohm          D
+--                        o      o-----|>|--o---o----/\/\---------o  /\
+--                        |      |          |   |                     |+
+--                   Vgs  <      -     Idsg( )  >                    Vdso
+--                        >      V          |   <                     |-
+--                        |      -          |   |                     |
+--                     S1 o------o--o------------------------------o S1V
+--                                  |
+--                                  >
+--                                  < rs= 1.0 ohm
+--                                  |
+--                                  0 S
+-----------------------------------------------------------------------
+
+----- PMOS 
+--use std.textio.all;
+use work.electricalsystem.all;
+
+entity pmos is
+    generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos
+	    T : real := 300.0;
+	    W : real := 1.0;
+	    L : real := 1.0;
+	    vto : real := 1.0; -- Zero-bais threshold voltage
+	    kp : real := 2.0e-5; -- transcondiuctanec parameter
+	    gamma : real := 0.0; -- body-effect parameter
+	    phi : real := 0.6; -- surface inversion potential
+	    lambda : real := 0.02; -- channel lenght modulation
+	    tox : real := 1.0e-7; -- thin oxide thickness
+	    nsub : real := 0.0; -- Substrate doping
+	    nss : real := 0.0; -- Surface STate density
+	    ld : real := 0.0; -- lateral diffusion;
+	    tpg : real := 1.0; -- Type of Gate material
+	    uo : real := 600.0; -- Surface mobility
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- fliccker noise coefficient
+	    iss : real := 1.0e-14; -- bulk junction saturation current
+	    js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter
+	    pb : real := 0.80; -- bulk junction potential
+	    cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter
+	    mj : real := 0.5; -- bulk junctioin grading coefficient
+	    cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter
+	    mjsw : real := 0.33; -- Perimiter capacitance rading coefficient
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+--  	    cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter
+--  	    cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter
+--  	    cgso : real := 1.5e-10; -- gate-source overlap cap / meter
+	    cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter
+	    cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter
+	    cgso : real := 4.0e-11; -- gate-source overlap cap / meter
+	    rd : real := 1.0; -- drain ohmic resistance
+	    rs : real := 1.0; -- source ohmic resistance
+	    rsh : real := 0.0); -- source and drain sheet resistance
+    port (terminal g,s,d,b : electrical);
+end entity pmos;
+
+architecture behav of pmos is
+  terminal d1, s1 : electrical;
+  quantity vds across idsg through d1 to s1;
+  quantity vdsr across idsr through d1 to d;
+  quantity vgs across igs through g to s1;
+  quantity vbs across ibs through s1 to b;
+  quantity vbd across ibd through d1 to b;
+-- new quantities added for source resistance
+  quantity vsr across isr through s1 to s;
+  quantity iss, isd : real := 1.0e-12;
+  quantity beta : real := 8.85e-05; -- gain
+  quantity leff : real := 1.0; -- effective length
+  constant gmin : real := 1.0e-12;
+  quantity vth : real := 0.5; -- threshold voltage
+  quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K 
+  --constant k : real := 1.38e-23; -- J/K ..... boltzman constant 
+  -- T = 300 K ............ Absolute temperature
+  --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge
+  constant cox_prime : real := 3.4515e-8; -- oxide capacitance per unit area F/cm2. cox_prime = EOX/TOX
+  quantity cox : real := 3.4515e-8;
+  quantity vds_free : real := 5.0;
+  quantity vgs_free : real := 0.0;
+  constant as : real := 15.0e-12; -- source area
+  constant ad : real := 15.0e-12; -- drain area
+  
+begin
+  ------ Setting initial conditions
+  initreg : break vgs => 0.0, vds => 0.0, vth => 0.5;
+
+  thres_volt : vth == vto + (gamma *(sqrt((2.0*phi)-vbs) - sqrt(phi)));
+  eff_length : leff == L - (2.0*ld);
+  therm_volt : ktq == 2.586e-2 * (T/300.0);
+  sat_scurr : iss == js*as;
+  sat_dcurr : isd == js*ad;
+--  gn : beta == 8.85e-05 * (W/L);
+  gn : beta == kp * ( w/leff);
+--  opn : vdsg == 1.0e9 * idsgi; -- almost open
+  d12_res : vdsr == idsr * rd;
+--  g12res : vgsr == igsr * rs;
+--  g_oup : vgs == igs * 1.0e9;
+--  oup_res : vds == ids * 1.0e9;
+  oup_res : vds_free == vds;
+  inp_res : vgs_free == vgs;
+  gre : vgs == igs * 1.0e9;
+  capeqn : cox == cox_prime * W * Leff; -- cox_prime * W * Leff
+  src_res : isr == vsr * rs;
+
+---- Current is in Micro Amps.
+-- Normal mode
+  ------ Cut off Region
+  regions : if((vgs > vth) and (vds <= 0.0))use
+	gncn : idsg == 1.0e-8 * vds;
+  ------ Linear Region
+  elsif((vds >= (vgs-vth)) and (vgs <= vth) and (vds <= 0.0)) use
+      	gnln : idsg == -1.0*vds*beta*((vgs_free-vth) - (vds_free/2.0))*(1.0 - lambda*vds_free);
+  ------ Saturation Region
+  elsif((vds < vgs-vth) and (vgs <= vth) and (vds <= 0.0)) use
+     	gnsn : idsg == -1.0*(beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 - lambda*vds_free);
+
+-- Inversion mode
+  ------ Cut off Region
+  elsif((vgs > vth) and (vds > 0.0))use
+	gnci : idsg == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif(((-1.0*vds) >= (vgs-vth)) and (vgs <= vth) and (vds > 0.0)) use
+      	gnli : idsg == -1.0*vds*beta*((vgs_free-vth) + (vds_free/2.0))*(1.0 + lambda*vds_free);
+  ------ Saturation Region
+  elsif(((-1.0*vds) < vgs-vth) and (vgs >= vth) and (vds > 0.0)) use
+     	gnsi : idsg == (beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 + lambda*vds_free);
+  end use;
+  
+----- Substrate diode equations 
+  initsub : break vbd => 0.0, vbs => 0.0, ibs => 0.0, ibd => 0.0;
+  
+   ----- Substrate to source
+   subcond1 : if(vbs > 0.0) use
+	bulk1 : ibs == ((iss*(exp(vbs/ktq) - 1.0)) + (gmin*vbs));
+   elsif(vbs <= 0.0 ) use
+   	bulk2 : ibs == ((iss*(vbs/ktq)) + (gmin*vbs));
+   end use;
+   ----- Substrate to drain
+   subcond2 : if(vbd > 0.0) use
+	bulk3 : ibd == ((isd*(exp(vbd/ktq) - 1.0)) + (gmin*vbd));
+   elsif(vbd <= 0.0 ) use
+    	bulk4 : ibd == ((isd*(vbd/ktq)) + (gmin*vbd));
+   end use;
+
+end architecture behav; --- of pmos;
+
+
+---- DC Voltage source
+
+use work.electricalsystem.all;
+
+entity DCVSrc is
+	generic (v : real := 10.0); -- voltage
+	port (terminal pos, neg : electrical);
+end entity DCVSrc;
+
+architecture behav of DCVSrc is
+  terminal temp : electrical;
+  quantity vdc across idc through temp to neg;
+  quantity vtemp across itemp through pos to temp;
+
+begin
+
+  VSrc : vdc == v;
+  temp_volt : vtemp == itemp * 1.0e-03;
+
+end architecture behav; --- of DCVSrc
+
+--- ramp source
+
+use work.electricalSystem.all;
+
+ENTITY rampSource IS
+  GENERIC( amp : real := 1.0);
+  PORT( TERMINAL ta2,tb2 : electrical);--Interface ports.
+END rampSource;
+
+--architecture declaration.
+ARCHITECTURE rampbehavior OF rampSource IS
+--quantity declarations.  
+  quantity Vramp across Iramp through ta2 to tb2; 
+
+BEGIN
+
+  -- The sinusoidal voltage source equation.
+  vsource: Vramp == (amp * real(time'pos(now)) * 1.0e-15) ;
+
+END ARCHITECTURE rampbehavior;
+
+
+------ inverter circuit
+
+use std.textio.all;
+use work.electricalsystem.all;
+
+entity inv is
+end entity;
+
+architecture test of inv is
+  terminal inv_in, inv_src, inv_out : electrical;
+  quantity vrout across irout through inv_out to electrical'reference;
+  quantity icout through inv_out to electrical'reference;
+--  quantity vin across iin through inv_in to electrical'reference;
+-- signal vgs_sig : real := 0.0; 
+--quantity vdd across asource to electrical'reference;
+
+  component nmos_comp is
+    generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos
+	    T : real := 300.0;
+	    W : real := 1.0;
+	    L : real := 1.0;
+	    vto : real := 1.0; -- Zero-bais threshold voltage
+	    kp : real := 2.0e-5; -- transcondiuctanec parameter
+	    gamma : real := 0.0; -- body-effect parameter
+	    phi : real := 0.6; -- surface inversion potential
+	    lambda : real := 0.02; -- channel lenght modulation
+	    tox : real := 1.0e-7; -- thin oxide thickness
+	    nsub : real := 0.0; -- Substrate doping
+	    nss : real := 0.0; -- Surface STate density
+	    ld : real := 0.0; -- lateral diffusion;
+	    tpg : real := 1.0; -- Type of Gate material
+	    uo : real := 600.0; -- Surface mobility
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- fliccker noise coefficient
+	    iss : real := 1.0e-14; -- bulk junction saturation current
+	    js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter
+	    pb : real := 0.80; -- bulk junction potential
+	    cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter
+	    mj : real := 0.5; -- bulk junctioin grading coefficient
+	    cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter
+	    mjsw : real := 0.33; -- Perimiter capacitance rading coefficient
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+--  	    cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter
+--  	    cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter
+--  	    cgso : real := 1.5e-10; -- gate-source overlap cap / meter
+	    cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter
+	    cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter
+	    cgso : real := 4.0e-11; -- gate-source overlap cap / meter
+	    rd : real := 1.0; -- drain ohmic resistance
+	    rs : real := 1.0; -- source ohmic resistance
+	    rsh : real := 0.0); -- source and drain sheet resistance
+     port (terminal g,s,d,b : electrical);
+  end component;
+  for all :nmos_comp use entity work.nmos(behav);
+
+  component pmos_comp is
+    generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos
+	    T : real := 300.0;
+	    W : real := 1.0;
+	    L : real := 1.0;
+	    vto : real := 1.0; -- Zero-bais threshold voltage
+	    kp : real := 2.0e-5; -- transcondiuctanec parameter
+	    gamma : real := 0.0; -- body-effect parameter
+	    phi : real := 0.6; -- surface inversion potential
+	    lambda : real := 0.02; -- channel lenght modulation
+	    tox : real := 1.0e-7; -- thin oxide thickness
+	    nsub : real := 0.0; -- Substrate doping
+	    nss : real := 0.0; -- Surface STate density
+	    ld : real := 0.0; -- lateral diffusion;
+	    tpg : real := 1.0; -- Type of Gate material
+	    uo : real := 600.0; -- Surface mobility
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- fliccker noise coefficient
+	    iss : real := 1.0e-14; -- bulk junction saturation current
+	    js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter
+	    pb : real := 0.80; -- bulk junction potential
+	    cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter
+	    mj : real := 0.5; -- bulk junctioin grading coefficient
+	    cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter
+	    mjsw : real := 0.33; -- Perimiter capacitance rading coefficient
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+--  	    cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter
+--  	    cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter
+--  	    cgso : real := 1.5e-10; -- gate-source overlap cap / meter
+	    cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter
+	    cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter
+	    cgso : real := 4.0e-11; -- gate-source overlap cap / meter
+	    rd : real := 1.0; -- drain ohmic resistance
+	    rs : real := 1.0; -- source ohmic resistance
+	    rsh : real := 0.0); -- source and drain sheet resistance
+     port (terminal g,s,d,b : electrical);
+  end component;
+  for all :pmos_comp use entity work.pmos(behav);
+  
+  component DCVSrc
+    generic (v : real := 10.0); -- voltage
+    port (terminal pos, neg : electrical);
+  end component;
+  for all : DCVSrc
+    use entity work.DCVSrc(behav);
+
+  component rampSource
+    GENERIC( amp : real := 1.0);
+    PORT( TERMINAL ta2,tb2 : electrical);--Interface ports.
+  END component;
+  for all : rampsource use entity work.rampsource(rampbehavior);
+  
+begin
+  inpramp : rampsource generic map(5.0e+7)
+           port map(inv_in, electrical'reference);
+  
+  inpdc : DCVSrc generic map (5.0)
+           port map(inv_src, electrical'reference);
+                           
+  
+  nm : nmos_comp
+    generic map(vto => 0.7, w => 3.0e-6, l => 3.0e-6, cj => 0.00044, cjsw => 4.0e-4, mj => 0.5, mjsw => 0.3, pb => 0.7, js => 1.0e-5)
+--       generic map(mos_type => 1.0, vto => 0.7, w => 3.0e-6, l => 3.0e-6, kp => 4.0e-5, gamma => 1.1, phi => 0.6, lambda => 0.01, cgso => 3.0e-10, cgdo => 3.0e-10, cgbo => 5.0e-10, cj => 0.00044, cjsw => 4.0e-4, mj => 0.5, mjsw => 0.3, pb => 0.7, js => 1.0e-5, ld => 3.5e-7)
+    port map(inv_in, electrical'reference, inv_out, electrical'reference);
+
+  pm : pmos_comp
+    generic map(vto => -0.7, w => 9.0e-6, l => 3.0e-6, cj => 0.00015, cjsw => 4.0e-4, mj => 0.6, mjsw => 0.6, pb => 0.6, js => 1.0e-5)
+--       generic map(mos_type => -1.0, vto => -0.8, w => 9.0e-6, l => 3.0e-6, kp => 1.2e-5, gamma => 0.6, phi => 0.6, lambda => 0.03, cgso => 2.5e-10, cgdo => 2.5e-10, cgbo => 5.0e-10, cj => 0.00015, cjsw => 4.0e-4, mj => 0.6, mjsw => 0.6, pb => 0.6, js => 1.0e-5, ld => 2.5e-7)
+    port map(inv_in, inv_src, inv_out, inv_src);	  
+
+  oupres : vrout == irout * 1.0e9;
+  oupcap : icout == 1.0e-13 * vrout'dot;
+  brkcap : break vrout => 5.0;
+end architecture test; -- inv
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_sqr.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_sqr.ams
new file mode 100644
index 0000000..ad3fdca
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_cmos_inv_sqr.ams
@@ -0,0 +1,531 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: static_cmos_inv_sqr.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This ckt is used to find the output characteristics of a cmos inverter
+-- The ckt used here is from sedra and smith's page no. 565, fig  13.13
+-- The mos W/L are according to the model specified in spice using the deck
+-- provided in the book. 
+-- The vgs, resistance is now removed, to avoid the RC effect on the imput.
+-- the square input is used 
+
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION POW(X,Y: real) RETURN real;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+
+-----------------------------------------------------------------------
+--                       G        B            D1    1.0 ohm          D
+--                        o      o-----|>|--o---o----/\/\---------o  /\
+--                        |      |          |   |                     |+
+--                   Vgs  <      -     Idsg( )  >                    Vdso
+--                        >      V          |   <                     |-
+--                        |      -          |   |                     |
+--                     S1 o------o--o------------------------------o S1V
+--                                  |
+--                                  >
+--                                  < rs= 1.0 ohm
+--                                  |
+--                                  0 S
+-----------------------------------------------------------------------
+
+----- NMOS 
+--use std.textio.all;
+use work.electricalsystem.all;
+
+entity nmos is
+    generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos
+	    T : real := 300.0;
+	    W : real := 1.0;
+	    L : real := 1.0;
+	    vto : real := 1.0; -- Zero-bais threshold voltage
+	    kp : real := 2.0e-5; -- transcondiuctanec parameter
+	    gamma : real := 0.0; -- body-effect parameter
+	    phi : real := 0.6; -- surface inversion potential
+	    lambda : real := 0.02; -- channel lenght modulation
+	    tox : real := 1.0e-7; -- thin oxide thickness
+	    nsub : real := 0.0; -- Substrate doping
+	    nss : real := 0.0; -- Surface STate density
+	    ld : real := 0.0; -- lateral diffusion;
+	    tpg : real := 1.0; -- Type of Gate material
+	    uo : real := 600.0; -- Surface mobility
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- fliccker noise coefficient
+	    iss : real := 1.0e-14; -- bulk junction saturation current
+	    js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter
+	    pb : real := 0.80; -- bulk junction potential
+	    cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter
+	    mj : real := 0.5; -- bulk junctioin grading coefficient
+	    cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter
+	    mjsw : real := 0.33; -- Perimiter capacitance rading coefficient
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+--  	    cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter
+--  	    cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter
+--  	    cgso : real := 1.5e-10; -- gate-source overlap cap / meter
+	    cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter
+	    cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter
+	    cgso : real := 4.0e-11; -- gate-source overlap cap / meter
+	    rd : real := 1.0; -- drain ohmic resistance
+	    rs : real := 1.0; -- source ohmic resistance
+	    rsh : real := 0.0); -- source and drain sheet resistance
+    port (terminal g,s,d,b : electrical);
+end entity nmos;
+
+architecture behav of nmos is
+  terminal d1, s1 : electrical;
+  quantity vds across idsg through d1 to s1;
+  quantity vdsr across idsr through d1 to d;
+  quantity vgs across igs through g to s1;
+  quantity vbs across ibs through b to s1;
+  quantity vbd across ibd through b to d1;
+-- new quantities added for source resistance
+  quantity vsr across isr through s1 to s;
+  quantity iss, isd : real := 1.0e-12;
+  quantity beta : real := 8.85e-05; -- gain
+  quantity leff : real := 1.0; -- effective length
+  constant gmin : real := 1.0e-12;
+  quantity vth : real := 0.5; -- threshold voltage
+  quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K 
+  --constant k : real := 1.38e-23; -- J/K ..... boltzman constant 
+  -- T = 300 K ............ Absolute temperature
+  --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge
+  constant cox_prime : real := 3.4515e-8; -- oxide capacitance per unit area F/cm2. cox_prime = EOX/TOX
+  quantity cox : real := 3.4515e-8;
+  quantity vds_free : real := 5.0;
+  quantity vgs_free : real := 0.0;
+  constant as : real := 15.0e-12; -- source area
+  constant ad : real := 15.0e-12; -- drain area
+  
+begin
+  ------ Setting initial conditions
+  initreg : break vgs => 0.0, vds => 5.0, vth => 0.5;
+
+  thres_volt : vth == vto + (gamma *(sqrt((2.0*phi)-vbs) - sqrt(phi)));
+  eff_length : leff == L - (2.0*ld);
+  therm_volt : ktq == 2.586e-2 * (T/300.0);
+  sat_scurr : iss == js*as;
+  sat_dcurr : isd == js*ad;
+--  gn : beta == 8.85e-05 * (W/L);
+  gn : beta == kp * ( w/leff);
+--  opn : vdsg == 1.0e9 * idsgi; -- almost open
+  d12_res : vdsr == idsr * rd;
+--  g12res : vgsr == igsr * rs;
+--  g_oup : vgs == igs * 1.0e9;
+--  oup_res : vds == ids * 1.0e9;
+  oup_res : vds_free == vds;
+  inp_res : vgs_free == vgs;
+  gre : vgs == igs * 1.0e9;
+  capeqn : cox == cox_prime * W * Leff; -- cox_prime * W * Leff
+  src_res : isr == vsr * rs;
+
+---- Current is in Micro Amps.
+-- Normal mode
+  ------ Cut off Region
+  regions : if((vgs < vth) and (vds >= 0.0))use
+	gncn : idsg == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif((vds <= (vgs-vth)) and (vgs >= vth) and (vds >= 0.0)) use
+      	gnln : idsg == vds*beta*((vgs_free-vth) - (vds_free/2.0))*(1.0 + lambda*vds_free);
+  ------ Saturation Region
+  elsif((vds > vgs-vth) and (vgs >= vth) and (vds >= 0.0)) use
+     	gnsn : idsg == (beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 + lambda*vds_free);
+
+-- Inversion mode
+  ------ Cut off Region
+  elsif((vgs < vth) and (vds < 0.0))use
+	gnci : idsg == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif(((-1.0*vds) <= (vgs-vth)) and (vgs >= vth) and (vds < 0.0)) use
+      	gnli : idsg == vds*beta*((vgs_free-vth) + (vds_free/2.0))*(1.0 - lambda*vds_free);
+  ------ Saturation Region
+  elsif(((-1.0*vds) > vgs-vth) and (vgs >= vth) and (vds < 0.0)) use
+     	gnsi : idsg == -1.0*(beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 - lambda*vds_free);
+  end use;
+  
+----- Substrate diode equations 
+  initsub : break vbd => 0.0, vbs => 0.0, ibs => 0.0, ibd => 0.0;
+  
+   ----- Substrate to source
+   subcond1 : if(vbs > 0.0) use
+	bulk1 : ibs == ((iss*(exp(vbs/ktq) - 1.0)) + (gmin*vbs));
+   elsif(vbs <= 0.0 ) use
+   	bulk2 : ibs == ((iss*(vbs/ktq)) + (gmin*vbs));
+   end use;
+   ----- Substrate to drain
+   subcond2 : if(vbd > 0.0) use
+	bulk3 : ibd == ((isd*(exp(vbd/ktq) - 1.0)) + (gmin*vbd));
+   elsif(vbd <= 0.0 ) use
+    	bulk4 : ibd == ((isd*(vbd/ktq)) + (gmin*vbd));
+   end use;
+
+end architecture behav; --- of nmos;
+
+
+-----------------------------------------------------------------------
+--                       G        B            D1    1.0 ohm          D
+--                        o      o-----|>|--o---o----/\/\---------o  /\
+--                        |      |          |   |                     |+
+--                   Vgs  <      -     Idsg( )  >                    Vdso
+--                        >      V          |   <                     |-
+--                        |      -          |   |                     |
+--                     S1 o------o--o------------------------------o S1V
+--                                  |
+--                                  >
+--                                  < rs= 1.0 ohm
+--                                  |
+--                                  0 S
+-----------------------------------------------------------------------
+
+----- PMOS 
+--use std.textio.all;
+use work.electricalsystem.all;
+
+entity pmos is
+    generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos
+	    T : real := 300.0;
+	    W : real := 1.0;
+	    L : real := 1.0;
+	    vto : real := 1.0; -- Zero-bais threshold voltage
+	    kp : real := 2.0e-5; -- transcondiuctanec parameter
+	    gamma : real := 0.0; -- body-effect parameter
+	    phi : real := 0.6; -- surface inversion potential
+	    lambda : real := 0.02; -- channel lenght modulation
+	    tox : real := 1.0e-7; -- thin oxide thickness
+	    nsub : real := 0.0; -- Substrate doping
+	    nss : real := 0.0; -- Surface STate density
+	    ld : real := 0.0; -- lateral diffusion;
+	    tpg : real := 1.0; -- Type of Gate material
+	    uo : real := 600.0; -- Surface mobility
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- fliccker noise coefficient
+	    iss : real := 1.0e-14; -- bulk junction saturation current
+	    js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter
+	    pb : real := 0.80; -- bulk junction potential
+	    cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter
+	    mj : real := 0.5; -- bulk junctioin grading coefficient
+	    cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter
+	    mjsw : real := 0.33; -- Perimiter capacitance rading coefficient
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+	    cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter
+	    cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter
+	    cgso : real := 4.0e-11; -- gate-source overlap cap / meter
+	    rd : real := 1.0; -- drain ohmic resistance
+	    rs : real := 1.0; -- source ohmic resistance
+	    rsh : real := 0.0); -- source and drain sheet resistance
+    port (terminal g,s,d,b : electrical);
+end entity pmos;
+
+architecture behav of pmos is
+  terminal d1, s1 : electrical;
+  quantity vds across idsg through d1 to s1;
+  quantity vdsr across idsr through d1 to d;
+  quantity vgs across igs through g to s1;
+  quantity vbs across ibs through s1 to b;
+  quantity vbd across ibd through d1 to b;
+-- new quantities added for source resistance
+  quantity vsr across isr through s1 to s;
+  quantity iss, isd : real := 1.0e-12;
+  quantity beta : real := 8.85e-05; -- gain
+  quantity leff : real := 1.0; -- effective length
+  constant gmin : real := 1.0e-12;
+  quantity vth : real := 0.5; -- threshold voltage
+  quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K 
+  --constant k : real := 1.38e-23; -- J/K ..... boltzman constant 
+  -- T = 300 K ............ Absolute temperature
+  --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge
+  constant cox_prime : real := 3.4515e-8; -- oxide capacitance per unit area F/cm2. cox_prime = EOX/TOX
+  quantity cox : real := 3.4515e-8;
+  quantity vds_free : real := 5.0;
+  quantity vgs_free : real := 0.0;
+  constant as : real := 15.0e-12; -- source area
+  constant ad : real := 15.0e-12; -- drain area
+  
+begin
+  ------ Setting initial conditions
+  initreg : break vgs => 0.0, vds => 0.0, vth => 0.5;
+
+  thres_volt : vth == vto + (gamma *(sqrt((2.0*phi)-vbs) - sqrt(phi)));
+  eff_length : leff == L - (2.0*ld);
+  therm_volt : ktq == 2.586e-2 * (T/300.0);
+  sat_scurr : iss == js*as;
+  sat_dcurr : isd == js*ad;
+  gn : beta == kp * ( w/leff);
+  d12_res : vdsr == idsr * rd;
+  oup_res : vds_free == vds;
+  inp_res : vgs_free == vgs;
+  gre : vgs == igs * 1.0e9;
+  capeqn : cox == cox_prime * W * Leff; -- cox_prime * W * Leff
+  src_res : isr == vsr * rs;
+
+---- Current is in Micro Amps.
+-- Normal mode
+  ------ Cut off Region
+  regions : if((vgs > vth) and (vds <= 0.0))use
+	gncn : idsg == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif((vds >= (vgs-vth)) and (vgs <= vth) and (vds <= 0.0)) use
+      	gnln : idsg == -1.0*vds*beta*((vgs_free-vth) - (vds_free/2.0))*(1.0 - lambda*vds_free);
+  ------ Saturation Region
+  elsif((vds < vgs-vth) and (vgs <= vth) and (vds <= 0.0)) use
+     	gnsn : idsg == -1.0*(beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 - lambda*vds_free);
+
+-- Inversion mode
+  ------ Cut off Region
+  elsif((vgs > vth) and (vds > 0.0))use
+	gnci : idsg == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif(((-1.0*vds) >= (vgs-vth)) and (vgs <= vth) and (vds > 0.0)) use
+      	gnli : idsg == -1.0*vds*beta*((vgs_free-vth) + (vds_free/2.0))*(1.0 + lambda*vds_free);
+  ------ Saturation Region
+  elsif(((-1.0*vds) < vgs-vth) and (vgs >= vth) and (vds > 0.0)) use
+     	gnsi : idsg == (beta/2.0)*(pow((vgs_free-vth),2.0))*(1.0 + lambda*vds_free);
+  end use;
+  
+----- Substrate diode equations 
+  initsub : break vbd => 0.0, vbs => 0.0, ibs => 0.0, ibd => 0.0;
+  
+   ----- Substrate to source
+   subcond1 : if(vbs > 0.0) use
+	bulk1 : ibs == ((iss*(exp(vbs/ktq) - 1.0)) + (gmin*vbs));
+   elsif(vbs <= 0.0 ) use
+   	bulk2 : ibs == ((iss*(vbs/ktq)) + (gmin*vbs));
+   end use;
+   ----- Substrate to drain
+   subcond2 : if(vbd > 0.0) use
+	bulk3 : ibd == ((isd*(exp(vbd/ktq) - 1.0)) + (gmin*vbd));
+   elsif(vbd <= 0.0 ) use
+    	bulk4 : ibd == ((isd*(vbd/ktq)) + (gmin*vbd));
+   end use;
+
+end architecture behav; --- of pmos;
+
+
+---- DC Voltage source
+
+use work.electricalsystem.all;
+
+entity DCVSrc is
+	generic (v : real := 10.0); -- voltage
+	port (terminal pos, neg : electrical);
+end entity DCVSrc;
+
+architecture behav of DCVSrc is
+  terminal temp : electrical;
+  quantity vdc across idc through temp to neg;
+  quantity vtemp across itemp through pos to temp;
+
+begin
+
+  VSrc : vdc == v;
+  temp_volt : vtemp == itemp * 1.0e-03;
+
+end architecture behav; --- of DCVSrc
+
+------- Square wave generator
+
+use work.electricalsystem.all;
+
+entity sqr_gen is
+	generic (vlo : real := 0.0;
+	        vhi : real := 10.0;
+	        ped : time := 1 ns);
+	port (terminal pos, neg : electrical);
+end entity sqr_gen;
+
+architecture behav of sqr_gen is
+  quantity vsqr across isqr through pos to neg;
+  signal vsig : real := 0.0;
+  signal clk : bit := '0';
+begin
+
+  vsqr == vsig;
+  break on vsig;
+
+  clock : process
+  begin
+     clk <= '0';
+     wait for ped;
+     clk <= '1';
+     wait for ped;
+  end process; --- clock
+     
+
+  generator : process
+     variable xv : real := 0.0;
+  begin
+	if(clk = '1') then
+    	   xv := vhi;
+	elsif(clk = '0') then
+	   xv := vlo;
+   	end if;
+        vsig <= xv;
+	wait on clk;
+  end process; --- generator;
+
+end architecture behav; --- of sqr_gen
+
+
+------ inverter circuit
+
+use std.textio.all;
+use work.electricalsystem.all;
+
+entity inv is
+end entity;
+
+architecture test of inv is
+  terminal inv_in1, inv_in2, inv_src, inv_out : electrical;
+  quantity vrin across irin through inv_in1 to inv_in2;
+  quantity vcin across icin through inv_in2 to electrical'reference;
+  quantity vrout across irout through inv_out to electrical'reference;
+  quantity icout through inv_out to electrical'reference;
+
+  component nmos_comp is
+    generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos
+	    T : real := 300.0;
+	    W : real := 1.0;
+	    L : real := 1.0;
+	    vto : real := 1.0; -- Zero-bais threshold voltage
+	    kp : real := 2.0e-5; -- transcondiuctanec parameter
+	    gamma : real := 0.0; -- body-effect parameter
+	    phi : real := 0.6; -- surface inversion potential
+	    lambda : real := 0.02; -- channel lenght modulation
+	    tox : real := 1.0e-7; -- thin oxide thickness
+	    nsub : real := 0.0; -- Substrate doping
+	    nss : real := 0.0; -- Surface STate density
+	    ld : real := 0.0; -- lateral diffusion;
+	    tpg : real := 1.0; -- Type of Gate material
+	    uo : real := 600.0; -- Surface mobility
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- fliccker noise coefficient
+	    iss : real := 1.0e-14; -- bulk junction saturation current
+	    js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter
+	    pb : real := 0.80; -- bulk junction potential
+	    cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter
+	    mj : real := 0.5; -- bulk junctioin grading coefficient
+	    cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter
+	    mjsw : real := 0.33; -- Perimiter capacitance rading coefficient
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+--  	    cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter
+--  	    cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter
+--  	    cgso : real := 1.5e-10; -- gate-source overlap cap / meter
+	    cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter
+	    cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter
+	    cgso : real := 4.0e-11; -- gate-source overlap cap / meter
+	    rd : real := 1.0; -- drain ohmic resistance
+	    rs : real := 1.0; -- source ohmic resistance
+	    rsh : real := 0.0); -- source and drain sheet resistance
+     port (terminal g,s,d,b : electrical);
+  end component;
+  for all :nmos_comp use entity work.nmos(behav);
+
+  component pmos_comp is
+    generic(mos_type : real := 1.0; -- +1.0 for nmos , -1.0 for pmos
+	    T : real := 300.0;
+	    W : real := 1.0;
+	    L : real := 1.0;
+	    vto : real := 1.0; -- Zero-bais threshold voltage
+	    kp : real := 2.0e-5; -- transcondiuctanec parameter
+	    gamma : real := 0.0; -- body-effect parameter
+	    phi : real := 0.6; -- surface inversion potential
+	    lambda : real := 0.02; -- channel lenght modulation
+	    tox : real := 1.0e-7; -- thin oxide thickness
+	    nsub : real := 0.0; -- Substrate doping
+	    nss : real := 0.0; -- Surface STate density
+	    ld : real := 0.0; -- lateral diffusion;
+	    tpg : real := 1.0; -- Type of Gate material
+	    uo : real := 600.0; -- Surface mobility
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- fliccker noise coefficient
+	    iss : real := 1.0e-14; -- bulk junction saturation current
+	    js : real := 0.0; -- bulk junctioin saturatioin current/ sqr meter
+	    pb : real := 0.80; -- bulk junction potential
+	    cj : real := 0.0; -- Zero-bias bulk capacitance/ sqr meter
+	    mj : real := 0.5; -- bulk junctioin grading coefficient
+	    cjsw : real := 0.0; -- Zero bias perimeter capacitance / sqr meter
+	    mjsw : real := 0.33; -- Perimiter capacitance rading coefficient
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+--  	    cgbo : real := 4.0e-10; -- gate-bulk overlap cap / meter
+--  	    cgdo : real := 1.5e-10; -- gate-drain overlap cap / meter
+--  	    cgso : real := 1.5e-10; -- gate-source overlap cap / meter
+	    cgbo : real := 2.0e-10; -- gate-bulk overlap cap / meter
+	    cgdo : real := 4.0e-11; -- gate-drain overlap cap / meter
+	    cgso : real := 4.0e-11; -- gate-source overlap cap / meter
+	    rd : real := 1.0; -- drain ohmic resistance
+	    rs : real := 1.0; -- source ohmic resistance
+	    rsh : real := 0.0); -- source and drain sheet resistance
+     port (terminal g,s,d,b : electrical);
+  end component;
+  for all :pmos_comp use entity work.pmos(behav);
+  
+  component DCVSrc
+    generic (v : real := 10.0); -- voltage
+    port (terminal pos, neg : electrical);
+  end component;
+  for all : DCVSrc
+    use entity work.DCVSrc(behav);
+
+  component sqr_comp is
+     generic(vlo : real := 0.0;
+             vhi : real := 10.0;
+	     ped : time := 1 ns);
+     port (terminal pos, neg : electrical); 
+  end component;
+  for all : sqr_comp use entity work.sqr_gen(behav);
+  
+begin
+  sqr : sqr_comp  
+	generic map(0.0, 5.0,  50 ns)
+	port map(inv_in1, electrical'reference);
+  
+  inpdc : DCVSrc generic map (5.0)
+           port map(inv_src, electrical'reference);
+                           
+  resin : vrin == irin * 1.0e3;
+  capin : icin == 4.0e-12 * vcin'dot;
+  oup : vrout == irout * 1.0e9;
+  capbrk : break vcin => 5.0, vrout => 0.0;
+  capout : icout == 1.0e-13 * vrout'dot;
+  nm : nmos_comp
+    generic map(vto => 0.7, w => 3.0e-6, l => 3.0e-6, cj => 0.00044, cjsw => 4.0e-4, mj => 0.5, mjsw => 0.3, pb => 0.7, js => 1.0e-5)
+    port map(inv_in2, electrical'reference, inv_out, electrical'reference);
+
+  pm : pmos_comp
+    generic map(vto => -0.7, w => 9.0e-6, l => 3.0e-6, cj => 0.00015, cjsw => 4.0e-4, mj => 0.6, mjsw => 0.6, pb => 0.6, js => 1.0e-5)
+    port map(inv_in2, inv_src, inv_out, inv_src);	  
+
+end architecture test; -- inv
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_njfet.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_njfet.ams
new file mode 100644
index 0000000..b43318f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_njfet.ams
@@ -0,0 +1,219 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: static_njfet.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This ckt is used to find the output and transfer characteristics of an
+-- n-channel JFET model. 
+-- The model is Spice2 model, taken from the SPICE book, pg 142, fig 3.7
+------------------------------------------------------------------------
+-- The ckt used here is from sedra and smith's page no. 215, fig  5.18
+------------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION POW(X,Y: real) RETURN real;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+
+-----------------------------------------------------------------------
+--                              G            D1      rd         D
+--                              o-----|>|--o-------/\/\---------o  
+--                              |          |                       
+--                              -      Id ( )                      
+--                              V          |                       
+--                              -          |                       
+--                           S1 o----------o
+--                              |
+--                              >
+--                              < rs
+--                              |
+--                              0 S
+-----------------------------------------------------------------------
+
+----- NMOS 
+--use std.textio.all;
+use work.electricalsystem.all;
+
+entity njfet is
+    generic(T : real := 300.0;
+	    vto : real := -2.0; -- Zero-bais threshold voltage
+	    beta : real := 1.0e-4; -- transconductance parameter
+	    lambda : real := 0.0; -- channel lenght modulation
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- flicker noise coefficient
+	    iss : real := 1.0e-14; -- gate junction saturation current
+	    pb : real := 1.0; -- gate junction potential
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+	    cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap
+	    cgs : real := 4.0e-11; -- zero-bias gate-source junction cap
+	    rd : real := 1.0e-6; -- drain ohmic resistance
+	    rs : real := 1.0e-6); -- source ohmic resistance
+    port (terminal g,s,d : electrical);
+end entity njfet;
+
+architecture behav of njfet is
+  terminal d1, s1 : electrical;
+  quantity vds across id through d1 to s1;
+  quantity vrd across ird through d to d1;
+  quantity vrs across irs through s1 to s;
+  quantity vgs across igs through g to s1;
+  quantity vgd across igd through g to d1;
+  constant gmin : real := 1.0e-12;
+  quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K 
+  --constant k : real := 1.38e-23; -- J/K ..... boltzman constant 
+  -- T = 300 K ............ Absolute temperature
+  --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge
+  quantity vds_free : real := 2.0;
+  quantity vgs_free : real := 0.0;
+  quantity vgd_free : real := 2.0;
+  
+begin
+  ------ Setting initial conditions
+  initreg : break vgs => 0.0, vds => 2.0, vgd => 2.0;
+  therm_volt : ktq == 2.586e-2 * (T/300.0);
+  dres : vrd == ird * rd;
+  oup_res : vds_free == vds;
+  inp_res : vgs_free == vgs;
+  vgdf : vgd_free == vgd;
+  sres : vrs == irs * rs;
+
+---- Current is in Amps.
+-- Normal mode
+  ------ Cut off Region
+  regions : if((vgs <= vto) and (vds >= 0.0))use
+	gncn : id == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif((vds < (vgs-vto)) and (vgs > vto) and (vds >= 0.0)) use
+      	gnln : id == vds*beta*((2.0*(vgs_free-vto)) - vds_free)*(1.0 + lambda*vds_free);
+  ------ Saturation Region
+  elsif((vds >= vgs-vto) and (vgs > vto) and (vds >= 0.0)) use
+     	gnsn : id == beta*(pow((vgs_free-vto),2.0))*(1.0 + lambda*vds_free);
+
+-- Inversted mode
+  ------ Cut off Region
+  elsif((vgd <= vto) and (vds < 0.0))use
+	gnci : id == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif(((-1.0*vds) < (vgd-vto)) and (vgd > vto) and (vds < 0.0)) use
+      	gnli : id == vds*beta*((2.0*(vgd_free-vto)) + vds_free)*(1.0 - lambda*vds_free);
+  ------ Saturation Region
+  elsif(((-1.0*vds) >= vgd-vto) and (vgd > vto) and (vds < 0.0)) use
+     	gnsi : id == -1.0*(beta)*(pow((vgd_free-vto),2.0))*(1.0 - lambda*vds_free);
+  end use;
+  
+----- Gate diode equations 
+  initsub : break vgd => 0.0, vgs => 0.0, igs => 0.0, igd => 0.0;
+  
+   ----- Gate to source
+   subcond1 : if(vgs > -5.0*ktq) use
+	gsf : igs == ((iss*(exp(vgs/ktq) - 1.0)) + (gmin*vgs));
+   elsif(vgs <= -5.0*ktq ) use
+   	gsr : igs == -1.0*iss + (gmin*vgs);
+   end use;
+   ----- Gate to drain
+   subcond2 : if(vgd > -5.0*ktq) use
+	gdf : igd == ((iss*(exp(vgd/ktq) - 1.0)) + (gmin*vgd));
+   elsif(vgd <= -5.0*ktq ) use
+    	gdr : igd == -1.0*iss + (gmin*vgd);
+   end use;
+
+end architecture behav; --- of njfet;
+
+---- DC Voltage source
+
+use work.electricalsystem.all;
+
+entity DCVSrc is
+	generic (v : real := 10.0); -- voltage
+	port (terminal pos, neg : electrical);
+end entity DCVSrc;
+
+architecture behav of DCVSrc is
+  terminal temp : electrical;
+  quantity vdc across idc through temp to neg;
+  quantity vtemp across itemp through pos to temp;
+
+begin
+
+  VSrc : vdc == v;
+  temp_volt : vtemp == itemp * 1.0e-03;
+
+end architecture behav; --- of DCVSrc
+
+
+------ njfet amplifier circuit
+
+use std.textio.all;
+use work.electricalsystem.all;
+
+entity njfet_ckt is
+end entity;
+
+architecture test of njfet_ckt is
+  terminal t1, t2, t3: electrical;
+  quantity vrd1 across ird1 through t1 to t2;
+  quantity vrs1 across irs1 through t3 to electrical'reference;
+  quantity vdd across idd through t1 to electrical'reference;
+
+
+  component njfet_comp is
+    generic(T : real := 300.0;
+	    vto : real := -2.0; -- Zero-bais threshold voltage
+	    beta : real := 1.0e-4; -- transconductance parameter
+	    lambda : real := 0.0; -- channel lenght modulation
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- flicker noise coefficient
+	    iss : real := 1.0e-14; -- gate junction saturation current
+	    pb : real := 1.0; -- gate junction potential
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+	    cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap
+	    cgs : real := 4.0e-11; -- zero-bias gate-source junction cap
+	    rd : real := 1.0e-6; -- drain ohmic resistance
+	    rs : real := 1.0e-6); -- source ohmic resistance
+    port (terminal g,s,d : electrical);                         
+  end component;
+  for all :njfet_comp use entity work.njfet(behav);
+
+begin
+
+  jn1 : njfet_comp 
+       generic map(vto => -4.0, beta => 1.0e-3, lambda => 0.0)
+       port map(ground, t3, t2);	
+
+  rd1 : vrd1 == ird1 * 1.0e3;
+  rs1 : vrs1 == irs1 * 0.5e3;
+  src : vdd == 10.0;
+  
+end architecture test; -- njfet_ckt
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_pjfet.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_pjfet.ams
new file mode 100644
index 0000000..f707a96
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/analog_models/static_pjfet.ams
@@ -0,0 +1,250 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: static_pjfet.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This ckt is used to find the output and transfer characteristics of an
+-- p-channel JFET model. 
+-- The model is Spice2 model, taken from the SPICE book, pg 142, fig 3.7
+------------------------------------------------------------------------
+-- The ckt used here is from sedra and smith's page no. 216, fig  5.20
+------------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION POW(X,Y: real) RETURN real;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+
+-----------------------------------------------------------------------
+--                              G            D1      rd         D
+--                              o-----|>|--o-------/\/\---------o  
+--                              |          |                       
+--                              -      Id ( )                      
+--                              V          |                       
+--                              -          |                       
+--                           S1 o----------o
+--                              |
+--                              >
+--                              < rs
+--                              |
+--                              0 S
+-----------------------------------------------------------------------
+
+----- P-JFET
+--use std.textio.all;
+use work.electricalsystem.all;
+
+entity pjfet is
+    generic(T : real := 300.0;
+	    vto : real := -2.0; -- Zero-bais threshold voltage
+	    beta : real := 1.0e-4; -- transconductance parameter
+	    lambda : real := 0.0; -- channel lenght modulation
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- flicker noise coefficient
+	    iss : real := 1.0e-14; -- gate junction saturation current
+	    pb : real := 1.0; -- gate junction potential
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+	    cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap
+	    cgs : real := 4.0e-11; -- zero-bias gate-source junction cap
+	    rd : real := 1.0e-6; -- drain ohmic resistance
+	    rs : real := 1.0e-6); -- source ohmic resistance
+    port (terminal g,s,d : electrical);
+end entity pjfet;
+
+architecture behav of pjfet is
+  terminal d1, s1 : electrical;
+  quantity vds across id through s1 to d1;
+  quantity vrd across ird through d1 to d;
+  quantity vrs across irs through s to s1;
+  quantity vgs across igs through s1 to g;
+  quantity vgd across igd through d1 to g;
+  constant gmin : real := 1.0e-12;
+  quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K 
+  --constant k : real := 1.38e-23; -- J/K ..... boltzman constant 
+  -- T = 300 K ............ Absolute temperature
+  --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge
+  quantity vds_free : real := 2.0;
+  quantity vgs_free : real := 0.0;
+  quantity vgd_free : real := 2.0;
+  
+begin
+  ------ Setting initial conditions
+  initreg : break vgs => 0.0, vds => 2.0, vgd => 2.0;
+  therm_volt : ktq == 2.586e-2 * (T/300.0);
+  dres : vrd == ird * rd;
+  oup_res : vds_free == vds;
+  inp_res : vgs_free == vgs;
+  vgdf : vgd_free == vgd;
+  sres : vrs == irs * rs;
+
+---- Current is in Amps.
+-- Normal mode
+  ------ Cut off Region
+  regions : if((vgs <= vto) and (vds >= 0.0))use
+	gncn : id == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif((vds < (vgs-vto)) and (vgs > vto) and (vds >= 0.0)) use
+      	gnln : id == vds*beta*((2.0*(vgs_free-vto)) - vds_free)*(1.0 + lambda*vds_free);
+  ------ Saturation Region
+  elsif((vds >= vgs-vto) and (vgs > vto) and (vds >= 0.0)) use
+     	gnsn : id == beta*(pow((vgs_free-vto),2.0))*(1.0 + lambda*vds_free);
+
+-- Inversted mode
+  ------ Cut off Region
+  elsif((vgd <= vto) and (vds < 0.0))use
+	gnci : id == 1.0e-9 * vds;
+  ------ Linear Region
+  elsif(((-1.0*vds) < (vgd-vto)) and (vgd > vto) and (vds < 0.0)) use
+      	gnli : id == vds*beta*((2.0*(vgd_free-vto)) + vds_free)*(1.0 - lambda*vds_free);
+  ------ Saturation Region
+  elsif(((-1.0*vds) >= vgd-vto) and (vgd > vto) and (vds < 0.0)) use
+     	gnsi : id == -1.0*(beta)*(pow((vgd_free-vto),2.0))*(1.0 - lambda*vds_free);
+  end use;
+  
+----- Gate diode equations 
+  initsub : break vgd => 0.0, vgs => 0.0, igs => 0.0, igd => 0.0;
+  
+   ----- Gate to source
+   subcond1 : if(vgs > -5.0*ktq) use
+	gsf : igs == ((iss*(exp(vgs/ktq) - 1.0)) + (gmin*vgs));
+   elsif(vgs <= -5.0*ktq ) use
+   	gsr : igs == -1.0*iss + (gmin*vgs);
+   end use;
+   ----- Gate to drain
+   subcond2 : if(vgd > -5.0*ktq) use
+	gdf : igd == ((iss*(exp(vgd/ktq) - 1.0)) + (gmin*vgd));
+   elsif(vgd <= -5.0*ktq ) use
+    	gdr : igd == -1.0*iss + (gmin*vgd);
+   end use;
+
+end architecture behav; --- of pjfet;
+
+---- DC Voltage source
+
+use work.electricalsystem.all;
+
+entity DCVSrc is
+	generic (v : real := 10.0); -- voltage
+	port (terminal pos, neg : electrical);
+end entity DCVSrc;
+
+architecture behav of DCVSrc is
+  terminal temp : electrical;
+  quantity vdc across idc through temp to neg;
+  quantity vtemp across itemp through pos to temp;
+
+begin
+
+  VSrc : vdc == v;
+  temp_volt : vtemp == itemp * 1.0e-03;
+
+end architecture behav; --- of DCVSrc
+
+
+------ pjfet amplifier circuit
+
+use std.textio.all;
+use work.electricalsystem.all;
+
+entity pjfet_ckt is
+end entity;
+
+architecture test of pjfet_ckt is
+  terminal t1, t2, t3, t4: electrical;
+--  quantity vin across iin through ain to electrical'reference;
+--  quantity vout across iout through t2 to electrical'reference;
+  quantity vb across ib through t1 to t2;
+--  quantity ibt through t1 to t2;
+  quantity vrd1 across ird1 through t3 to t4;
+  quantity vdd across idd through t1 to electrical'reference;
+  quantity vss across iss through t4 to electrical'reference;
+  
+
+  -- signal vds_sig, vgs_sig : real := 0.0;
+
+  component pjfet_comp is
+    generic(T : real := 300.0;
+	    vto : real := -2.0; -- Zero-bais threshold voltage
+	    beta : real := 1.0e-4; -- transconductance parameter
+	    lambda : real := 0.0; -- channel lenght modulation
+	    af : real := 1.0; -- flicker noise exponent
+	    kf : real := 0.0; -- flicker noise coefficient
+	    iss : real := 1.0e-14; -- gate junction saturation current
+	    pb : real := 1.0; -- gate junction potential
+	    fc : real := 0.5; -- forward-bais depletion capacitance coeff
+	    cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap
+	    cgs : real := 4.0e-11; -- zero-bias gate-source junction cap
+	    rd : real := 1.0e-6; -- drain ohmic resistance
+	    rs : real := 1.0e-6); -- source ohmic resistance
+    port (terminal g,s,d : electrical);                         
+  end component;
+  for all :pjfet_comp use entity work.pjfet(behav);
+
+begin
+
+  jn1 : pjfet_comp 
+       generic map(vto => -2.0, beta => 1.0e-3, lambda => 0.04)
+       port map(ground, t2, t3);	
+
+--  brk :  break on vgs_sig,vds_sig;
+--  inp :  vin == vgs_sig;
+--  oup :  vout == vds_sig;
+--  oup : vout == iout * 1.0e8;
+--  cap : icout == 1.0e-13 * vcout'dot;
+--  capbrk : break vcout => 0.0;
+  rd1 : vrd1 == ird1 * 2.0e3;
+  src1 : vdd == 5.0;
+  src2 : vss == -5.0;
+  curr : ib == 1.0e-3;
+--  curt : vb == ibt * 1.0e6;
+  
+--  inputtestbench:PROCESS
+--    FILE test_IN : text OPEN READ_MODE IS "pjfet_anal.in";
+--    VARIABLE linebuf : line;
+--    VARIABLE xds, xgs : real := 0.0;
+--  BEGIN
+    
+--    WHILE(NOT(endfile(test_IN))) LOOP
+--      readline(test_IN,linebuf);
+--      read(linebuf,xgs);
+--      read(linebuf,xds);
+--      vgs_sig <= xgs;
+--      vds_sig <= xds;
+--      WAIT FOR 1 ns;
+--    END LOOP;
+--    WAIT;
+--  END process; --- inputtestbench
+
+end architecture test; -- pjfet_ckt
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/cap_array.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/cap_array.ams
new file mode 100644
index 0000000..6b88cf4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/cap_array.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: cap_array.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- A simple RC circuit but both R & C are in between
+-- array terminals.
+
+PACKAGE electricalSystem IS
+    subtype voltage is real ;
+    subtype current is real ;
+
+   NATURE electrical IS real ACROSS real THROUGH ground REFERENCE;
+   NATURE electrical_vector is array(natural range<>) of electrical ;
+   subnature el_vect4 is electrical_vector(1 to 2);
+   FUNCTION SIN(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+
+   terminal n1: electrical;
+   terminal n2: el_vect4;
+
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2;
+   quantity vs across n1 ;
+   constant r1 : REAL := 1000.0;
+   constant cap : REAL := 100.0e-9;
+
+
+BEGIN 
+
+res11 : vr1(1) == ir1(1) * r1;
+res12 : vr1(2) == ir1(2) * r1;
+cap11 : ir2(1) == vr2(1)'dot * cap;
+cap12 : ir2(2) == cap * vr2(2)'dot;
+
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 15.0 --sine source
+                              * real(time'pos(now)) * 1.0e-13);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_array.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_array.ams
new file mode 100644
index 0000000..4804590
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_array.ams
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: res_array.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    subtype voltage is real ;
+    subtype current is real ;
+
+   NATURE electrical IS voltage ACROSS current THROUGH Ground reference;
+   NATURE electrical_vector is array(natural range<>) of electrical ;
+   subnature el_vect4 is electrical_vector(1 to 4);
+   FUNCTION SIN(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+
+   terminal n1 : electrical;
+   terminal n2: el_vect4;
+
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2 ;
+   quantity vs across n1 ;
+   constant r1 : REAL := 20.0;
+   constant r2 : REAL := 10.0;
+
+
+BEGIN 
+
+-- this will no longer work
+-- * should be overloaded to support such a statement.
+--res1 : vr1 == ir1 * r1;
+res11 : vr1(1) == ir1(1) * r1;
+res12 : vr1(2) == ir1(2) * r1;
+res13 : vr1(3) == ir1(3) * r1;
+res14 : vr1(4) == ir1(4) * r1;
+res21 : vr2(1) == ir2(1) * r2;
+res22 : vr2(2) == ir2(2) * r2;
+res23 : vr2(3) == ir2(3) * r2;
+res24 : vr2(4) == ir2(4) * r2;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                              * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_index.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_index.ams
new file mode 100644
index 0000000..aaff3aa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_models/res_index.ams
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: res_index.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    subtype voltage is real ;
+    subtype current is real ;
+
+   NATURE electrical IS voltage ACROSS current THROUGH Ground reference;
+   NATURE electrical_vector is array(natural range<>) of electrical ;
+   type real_vector is array(natural range<>) of voltage ;
+	subtype real_vec4 is real_vector(0 to 3);
+   subnature el_vect4 is electrical_vector(0 to 3);
+   FUNCTION SIN(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+
+   terminal n1, n4 : electrical;
+   terminal n2 , n3: el_vect4;
+
+  --quantity V across I through n1(0 to 2) to n1(1 to 3);
+  quantity V1 across I1 through n1 to n2;
+  quantity V2 across I2 through n2 to n3;
+  quantity V3 across I3 through n3 to n4;
+  quantity Vout across Iout through n4;
+  --quantity vs across n1(0) ;
+  quantity vs across n1 ;
+   constant r1 : REAL := 200.0;
+   constant r2 : REAL := 200.0;
+   constant r3 : REAL := 200.0;
+   constant r4 : REAL := 200.0;
+
+	signal my_sig : real_vec4 ;
+
+BEGIN 
+-- the below statement parses but seems like 'delayed is not
+-- there in VHDL.
+--my_sig(2) <= my_sig(1)'delayed(5 ns) * 10.0;
+--my_sig(3) <= my_sig(2) * 10.0;
+-- the four statement are equivalent to 
+-- V == I * r1 ;
+-- also the operator * should be overloaded
+
+--res0:	 V1 == I1 * r1;
+--res1:	 V == I * r1;
+--res1:	 V(0) ==  5.0 ;
+res1 :   V1(0) == I1(0) * r1;
+res2 :   V1(1) == I1(1) * r1;
+res3 :   V1(2) == I1(2) * r1;
+res4 :   V1(3) == I1(3) * r1;
+res11 :   V2(0) == I2(0) * r1;
+res21 :   V2(1) == I2(1) * r1;
+res31 :   V2(2) == I2(2) * r1;
+res41 :   V2(3) == I2(3) * r1;
+res111 :   V3(0) == I3(0) * r1;
+res211 :   V3(1) == I3(1) * r1;
+res311 :   V3(2) == I3(2) * r1;
+res411 :   V3(3) == I3(3) * r1;
+res641 :   Vout == Iout * r1;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                           * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test107.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test107.ams
new file mode 100644
index 0000000..1c9b85e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test107.ams
@@ -0,0 +1,152 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test107.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test107.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correct impelmentation of the port terminal
+-- decl. signal decl. of type real, type array decl. 
+-- the test performs a 4 bit digital to analog conversion.
+----------------------------------------------------------------------
+
+PACKAGE electricalsystem IS
+  NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+END electricalsystem;
+
+USE work.electricalsystem.all;
+ENTITY dac is
+  port(inputvector : in bit_vector(3 downto 0); --inputvector is an array of 16 bits
+       terminal T1, T2: electrical);	--terminal declarations
+END dac;
+
+ARCHITECTURE behavior OF dac IS
+
+  type temp_array is array(0 to 3) of integer; -- temp to store the array values
+  quantity vout across T1 to T2;	--output of the dac
+  
+  signal vout_sig, vcopy : real;	
+BEGIN
+
+  dac_process: PROCESS(inputvector) 
+    variable a : temp_array := (0,0,0,0);
+    variable tmp : real;
+    
+  BEGIN
+    for index in 3 downto 0 loop
+      if inputvector(index) = '0' then
+	a(index) := 0;			--bit to integer conversion done here
+      else a(index) := 1; 
+      end if;
+    end loop;
+
+    tmp := real(a(3)*8) + real(a(2)*4) + real(a(1)*2 + a(0)); --find the corresponding value of the binary 
+    vout_sig <= tmp;		
+
+  END PROCESS dac_process;
+
+  -- digital to analog conversion is done here
+  vout == vcopy;
+
+  convert: process(vout_sig)
+  begin
+    vcopy <= TRANSPORT vout_sig;
+  end process;
+
+END behavior;
+use work.electricalsystem.all;
+ENTITY tb_dac is
+end tb_dac;
+
+architecture stimuli of tb_dac is
+  signal myinputvector : bit_vector(3 downto 0);
+  terminal tout : electrical;
+  component dac port( inputvector : in bit_vector(3 downto 0);
+                      terminal T1, T2: electrical);
+  end component;
+  for all: dac use entity work.dac(behavior);
+  
+BEGIN
+  
+  unit:dac port map (myinputvector, tout, electrical'reference);
+
+  stimuli_process: process
+  BEGIN
+    
+    myinputvector <= "0000";
+    wait for 10 ns;
+
+   myinputvector <= "0001";
+    wait for 10 ns;
+
+  myinputvector <= "0010";
+    wait for 10 ns;
+
+    myinputvector <= "0100";
+    wait for 10 ns;
+
+    myinputvector <= "1000";
+    wait for 10 ns;
+
+    myinputvector <= "1100";
+    wait for 10 ns;
+
+    myinputvector <= "1110";    
+    wait for 10 ns;
+
+    myinputvector <= "1101"; 
+    wait for 10 ns;
+
+    myinputvector <= "1111"; 
+    wait for 10 ns;
+    myinputvector <= "0000";
+    wait for 10 ns;
+  
+    myinputvector <= "1100";
+    wait for 10 ns;
+    
+    myinputvector <= "1010";
+    wait for 10 ns;
+  
+    wait;
+  end process;
+end stimuli;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test129.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test129.ams
new file mode 100644
index 0000000..d59b2de
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test129.ams
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test129.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+     NATURE electrical IS real ACROSS real THROUGH ground reference; 
+    FUNCTION POW(X,Y: real) RETURN real;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    nature electrical_vector is array(natural range<>) of electrical;
+    subnature el_vec is electrical_vector(0 to 3);
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is
+generic( a: real);
+port( terminal ip: el_vec;
+      terminal op:electrical);
+end entity;
+
+architecture atest of test is
+variable a:real:=5.0;
+variable output:real:=0.0;
+quantity vin across ip ;
+quantity vout across iout through ip to op;
+begin
+
+   for i in 0 to 3 loop
+	output:=output + vin(i)*a;
+   end loop;
+vout:=output;
+
+end architecture atest;
+
+use work.electricalSystem.all;
+entity tb is
+end entity;
+
+architecture atb of tb is
+quantity  myvector : el_vec(0 to 3);
+terminal top:electrical;
+component test 
+	port(terminal ip, op: electrical);
+end component;
+for all: test use entity work.test(atest);
+begin
+
+unit: test port map(tip, top, ground);
+
+a_process: process
+begin
+
+myvector == 1.0;
+wait for 10 ns;
+myvector  == 2.0;
+wait for 10 ns;
+myvector  == 2.0;
+wait for 10 ns;
+myvector  ==1.0;
+wait for 10 ns;
+
+wait;
+
+end process;
+
+end atb;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test130.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test130.ams
new file mode 100644
index 0000000..c92b11b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test130.ams
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test130.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+    NATURE electrical IS real ACROSS real THROUGH ground reference; 
+    FUNCTION POW(X,Y: real) RETURN real;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    nature electrical_vector is array(natural range<>) of electrical;
+    subnature el_vec is electrical_vector(0 to 3);
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is
+generic( a: real);
+port( terminal ip: el_vec;
+      terminal op:electrical);
+end entity;
+
+architecture atest of test is
+variable a:real:=5.0;
+variable output:real:=0.0;
+quantity vin0 across ip(0) to op;
+quantity vin1 across ip(1) to op;
+quantity vin2 across ip(2) to op;
+quantity vin3 across ip(3) to op;
+quantity vout across iout through op;
+
+begin
+
+e1: vin0 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9);
+e2: vin1 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9);
+e3: vin2 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9);
+e4: vin3 == 5.0* sin(2.0*3.14*10.0*real(time'pos(now))*1.0e-9);
+
+vout == (vin0+vin1+vin2+vin3)*a;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test139.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test139.ams
new file mode 100644
index 0000000..8d81345
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test139.ams
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test139.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+-----------------------------------------------------------------------
+-- File          : test139.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+-----------------------------------------------------------------------
+-- Description :
+-----------------------------------------------------------------------
+-- this test checks the correctness of the record declaration as a type
+-- it also checks for the usage of the record element declarations.
+-- the assert statement is also checked.
+-- the record is declared within a package
+-- the test also checks the correctness of the function impelmentation.
+-- the function accepts the record parameters and returns the result of 
+-- type real.
+-----------------------------------------------------------------------
+
+PACKAGE electricalsystem IS
+ 
+    SUBTYPE voltage IS real;
+    SUBTYPE current IS real;
+ 
+    NATURE electrical IS
+        voltage ACROSS
+        current THROUGH ground reference;
+ 
+END PACKAGE electricalsystem;
+ 
+PACKAGE types IS
+ 
+    TYPE cmodel IS RECORD
+        cj     : real;    
+        cjsw   : real;    
+        defw   : real;    
+        narrow : real;    
+    END RECORD;
+ 
+END PACKAGE types;
+ 
+USE work.electricalsystem.all;
+USE work.types.all;
+ 
+ENTITY test IS
+    GENERIC (cnom : real := 0.0;
+             model : cmodel := (0.0, 0.0, 1.0e-6, 0.0);
+             l : real := 0.0;
+             w : real := 0.0;
+             ic : real := 0.0 );
+    PORT (TERMINAL t1,t2 : electrical);
+END ENTITY test;
+ 
+ARCHITECTURE atest OF test IS
+    	FUNCTION c_init (	cnom : real;
+             		model : cmodel;
+             		l, w : real)
+        RETURN real IS
+        VARIABLE ceff : real;  -- effective capacitance value
+        VARIABLE weff : real;  -- effective channel width
+ 	BEGIN
+ 
+        IF cnom /= 0.0 THEN
+            ASSERT (model.cj = 0.0 AND model.cjsw = 0.0)
+                    REPORT "Both cnom and model specified";
+            ceff := cnom;
+        ELSE
+            ASSERT (l > 0.0)
+                    REPORT "Channel length not specified";
+            IF w = 0.0 THEN
+                weff := model.defw;
+            ELSE
+                weff := w;
+            END IF;
+            ASSERT (weff > 0.0) 
+                    REPORT "Channel width not specified";
+            ceff := model.cj*(l-model.narrow)*(weff-model.narrow) +
+                        model.cjsw*(l+weff-2.0*model.narrow);
+        END IF;
+        RETURN (ceff);
+    	END FUNCTION c_init;
+ 
+    	CONSTANT ceff : real := c_init(cnom, model, l, w);
+    	QUANTITY v ACROSS i THROUGH t1 TO t2;
+BEGIN
+    i == ceff * v'dot;
+END ARCHITECTURE atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test186.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test186.ams
new file mode 100644
index 0000000..fd22b2a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/array_tests/test186.ams
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test186.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    subtype voltage is real ;
+    subtype current is real ;
+
+   NATURE electrical IS voltage ACROSS current THROUGH Ground reference;
+   --NATURE electrical IS real ACROSS real THROUGH Ground reference;
+   NATURE electrical_vector is array(natural range<>) of electrical ;
+   --type real_vector is array(natural range<>) of voltage ;
+   subnature el_vec is electrical_vector(0 to 100);
+   FUNCTION SIN(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+  
+--entity declaration
+
+ENTITY RLC IS
+   
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+    
+   terminal n1 : electrical; 
+   terminal n2: el_vec;
+   
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2 to ground;
+   quantity vs across n1 ;
+   constant r1 : REAL := 20.0;
+   constant r2 : REAL := 10.0;
+
+
+BEGIN
+
+res1 : vr1 == ir1 * r1;
+res2 : vr2 == ir2 * r2;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                              * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/across.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/across.ams
new file mode 100644
index 0000000..be1ba84
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/across.ams
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: across.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   terminal n1,n2: electrical;
+   constant r1 : real := 10.0;
+   constant r2 : real := 20.0;
+   constant r3 : real := 20.0;
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through Ground;
+   quantity vr3 across ir3 through n2;
+   quantity vs across n1 to ground;
+   quantity contrib: electrical'across;
+BEGIN 
+
+v1:     vr1 == ir1 *r1;
+v2:     vr2 == ir2 *r2;
+v3:     vr3 == ir3 *r3;
+fr: contrib == n1'contribution;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/step_limit.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/step_limit.ams
new file mode 100644
index 0000000..71f416e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/step_limit.ams
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: step_limit.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  COS (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+USE work.electricalSystem.all;
+
+--entity declaration
+ENTITY hwr IS
+END hwr;
+
+--architecture declaration
+ARCHITECTURE behavior  OF hwr IS
+
+    terminal t1, t2 : electrical;
+    constant step : real := 5.0e12;
+    quantity v2 across i2 through t1 ;
+    quantity vs across t1 ;
+    limit vs:real with step/1000.0;
+    quantity vikram:real;
+    limit v2,vs:real with 2.0e9;
+BEGIN  -- behavior 
+
+      eqn1: v2 == 100.0 * i2;
+    
+      --voltage source equation
+      eqn2: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 *
+                            real(time'pos(now)) * 1.0e-12 );
+    
+END behavior ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/through.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/through.ams
new file mode 100644
index 0000000..305b7da
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/through.ams
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: through.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   terminal n1,n2: electrical;
+   constant r1 : real := 10.0;
+   constant r2 : real := 20.0;
+   constant r3 : real := 20.0;
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through ground;
+   quantity vr3 across ir3 through n2;
+   quantity vs across n1 to ground;
+   quantity contrib: electrical'through;
+BEGIN 
+
+v1:     vr1 == ir1 *r1;
+v2:     vr2 == ir2 *r2;
+v3:     vr3 == ir3 *r3;
+fr: contrib == n1'reference;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_contribution.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_contribution.ams
new file mode 100644
index 0000000..b82427e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_contribution.ams
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tick_contribution.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   terminal n1,n2: electrical;
+   constant r1 : real := 10.0;
+   constant r2 : real := 20.0;
+   constant r3 : real := 20.0;
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2;
+   quantity vr3 across ir3 through n2;
+   quantity vs across n1;
+   quantity contrib:real;
+BEGIN 
+
+v1:    vr1 == ir1 *r1;
+v2:    vr2 == ir2 *r2;
+v3:    vr3 == ir3 *r3;
+fr:  contrib == n2'contribution;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams
new file mode 100644
index 0000000..bb2cf7d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_left.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tick_left.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- A simple RC circuit but both R & C are in between array terminals.
+-- trying to use 'left, 'right, 'low, 'high attributes.
+
+PACKAGE electricalSystem IS
+    subtype voltage is real ;
+    subtype current is real ;
+
+   NATURE electrical IS real ACROSS real THROUGH ground REFERENCE;
+   NATURE electrical_vector is array(natural range<>) of electrical ;
+   subnature el_vect4 is electrical_vector(1 to 2);
+   
+   FUNCTION SIN(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+
+   terminal n1: electrical;
+   terminal n2: el_vect4;
+
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2 to Ground;
+   quantity vs across n1 ;
+   constant r1 : REAL := 1000.0;
+   constant cap : REAL := 100.0e-9;
+
+BEGIN 
+
+res11 : vr1(n2'left) == ir1(n2'left) * r1;
+res12 : vr1(el_vect4'right) == ir1(el_vect4'right) * r1;
+cap11 : ir2(el_vect4'low) == vr2(1)'dot * cap;
+cap12 : ir2(el_vect4'high) == cap * vr2(2)'dot;
+
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 15.0 --sine source
+                              * real(time'pos(now)) * 1.0e-13);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_reference.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_reference.ams
new file mode 100644
index 0000000..563dddd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/attribute/tick_reference.ams
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tick_reference.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   terminal n1,n2: electrical;
+   constant r1 : real := 10.0;
+   constant r2 : real := 20.0;
+   quantity ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2;
+   quantity vs across n1;
+BEGIN 
+
+i1 : ir1 == (n1'reference - n2'reference)/ r1 ;
+v1 : vr2 == ir2*r2;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/bouncing_ball.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/bouncing_ball.ams
new file mode 100644
index 0000000..b646742
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/bouncing_ball.ams
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: bouncing_ball.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY bouncing_ball IS 
+END ENTITY bouncing_ball; 
+
+ARCHITECTURE simple OF bouncing_ball IS 
+
+    QUANTITY v: real; 
+    QUANTITY s: real; 
+    CONSTANT G: real := 9.81; 
+
+    CONSTANT Air_Res: real := 0.1; 
+
+BEGIN 
+
+    b1:BREAK v => 0.0, s => 30.0; -- announce discontinuity and reset
+
+   b2:BREAK v => -0.7*v  WHEN NOT(s'above(0.0));
+
+    velocity:  v == s'dot ; 
+
+    acceleration: v'dot == -G;  
+
+END ARCHITECTURE simple;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/lorenz_chaos.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/lorenz_chaos.ams
new file mode 100644
index 0000000..97b3bcc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/lorenz_chaos.ams
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: lorenz_chaos.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity LorenzChaos is 
+end entity LorenzChaos; 
+
+architecture Chaotic of LorenzChaos is 
+
+    constant s: real := 10.0;    -- define equation parameters s,b,r 
+    constant b: real := 8.0/3.0; 
+    constant r: real := 28.0; 
+    quantity x: real;
+    quantity y: real;
+    quantity z: real;
+    
+begin 
+    -- set an initial condition to guarantee chaotic behaviour: 
+   br:break x=> y , y => 5.0, z => 25.0; 
+   br1:break when y'above(25.0);
+   
+    -- equation set: 
+    eq1:x == y-(x'dot/s); 
+    eq2:y == r*x-x*z-y'dot; 
+    eq3:z == (x*y -z'dot)/b;
+ 
+end architecture Chaotic; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/precharged_capacitor.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/precharged_capacitor.ams
new file mode 100644
index 0000000..d62c63a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/precharged_capacitor.ams
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: precharged_capacitor.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This is a model of discharging of a precharged capacitor
+-- Break statement has been used here to set the initial 
+-- value of the voltage to which the capacotor was charged
+-- authors: Shishir Agrawal
+--          Vikram
+--          Sanjiv Pandey
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+ENTITY RC IS
+END;
+
+ARCHITECTURE behav OF RC IS
+    TERMINAL n1,n2: ELECTRICAL;
+    QUANTITY v_in ACROSS i_in THROUGH  n1;
+    QUANTITY u_r ACROSS i_r THROUGH n1 TO n2;
+    QUANTITY u_c ACROSS i_c THROUGH n2;
+BEGIN
+
+
+    b1: BREAK  u_c => 0.5;       	--initvalue
+
+    e1: v_in == 0.0;      			--constant  voltage source
+    e2: i_r  == u_r  / 1000.0;      --resistor  equation
+    e3: i_c  == 1.0e-6 * u_c'dot;   --capacitor equation
+END;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams
new file mode 100644
index 0000000..9d3e53e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test123.ams
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test123.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test113.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- to check the correct implementation of the simultaneous if statement
+-- break and 'above is also used. it checks for the eqns v'=g*v**2 for 
+-- +g and -g.
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+--    alias ground is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity test is
+end entity test;
+
+architecture atest of test is
+quantity v : real;
+quantity s: real;
+constant g : real :=9.81;
+constant r : real:=1.02;
+
+begin
+
+break v=>0.0, s=>100.0;
+
+break v=>-v when not s'above(0.0);
+
+s'dot==v;
+
+if v>0.0 use
+   v'dot == -g+v*v*r;
+else
+   v'dot == -g-v*v*r;
+end use;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test133.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test133.ams
new file mode 100644
index 0000000..e97d77b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test133.ams
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test133.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test133.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+
+--this test checks the correctness of the break statement for a 
+-- quantity port declaration.
+-- LRM ref: 8.14
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+        subtype voltage is real;
+
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is 
+    generic (m: real := 1.0); 
+    port (quantity x: out voltage);  
+end entity test; 
+
+architecture atest of test is 
+--quantity x: real;
+quantity q: real;
+begin 
+    break x => 0.0, x'dot => 0.1; 
+    e1: q== x'dot;
+    x'dot'dot == -1.0*( m*(x*x - 1.0)* x'dot); 
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams
new file mode 100644
index 0000000..0f80d28
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test134.ams
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test134.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test151.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this is a test to check the corretness of the implemntation of the break
+-- statement and also the use of quantity port of type voltage.
+-- this is a vco model which first sets the initial condition
+-- using a break statement. Then again, a break statement is applied to keep 
+-- the phase within 0-2pi. Thr output voltage eqn is obtained as vout and the 
+-- phase eqn as phase'dot.
+-- LRM ref: 8.14, 4.3.2.
+---------------------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    SUBTYPE voltage is real;
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity vco is 
+  generic( 
+          fc: real := 1.0e6;    -- VCO frequency at Vc 
+          df: real := 0.5e6;  -- [Hz/V], frequency characteristic slope 
+          Vc: voltage := 0.0 --  centre frequency input voltage 
+         ); 
+  port( quantity Vin: in voltage; 
+        terminal OutTerminal: electrical); 
+end entity VCO; 
+
+architecture avco of vco is 
+    constant TwoPi: real := 6.283118530718; -- 2pi 
+
+    quantity Phase : real; 
+
+    -- define a branch for the output voltage source 
+
+    quantity Vout across Iout through OutTerminal to electrical'reference; 
+
+begin 
+   -- use break to set the phase initial condition 
+   break Phase => 0.0; 
+
+   -- another break statement keeps the phase within 0.. 2pi 
+   break Phase => Phase mod TwoPi on Phase'above(TwoPi); 
+
+   -- phase equation 
+   Phase'dot == TwoPi*realmax(0.5E6, fc+(Vin-Vc)*df); 
+
+     -- output voltage source equation 
+     Vout == 2.5*(1.0+sin(Phase)); 
+
+end architecture avco; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test158.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test158.ams
new file mode 100644
index 0000000..f96b6f4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test158.ams
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test158.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test134.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : June 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this is a test to check the corretness of the implemntation of the break
+-- statement and also the use of quantity port of type voltage.
+-- this is a vco model which first sets the initial condition
+-- using a break statement. Then again, a break statement is applied to keep 
+-- the phase within 0-2pi. Thr output voltage eqn is obtained as vout and the 
+-- phase eqn as phase'dot.
+-- LRM ref: 8.14, 4.3.2.
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+   -- SUBTYPE voltage is real;
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity vco is 
+  generic( 
+          fc: real := 1.0e6;    -- VCO frequency at Vc 
+          df: real := 0.5e6;  -- [Hz/V], frequency characteristic slope 
+          Vc: voltage := 0.0 --  centre frequency input voltage 
+         ); 
+  port( quantity Vin: in real; 
+        terminal OutTerminal: electrical); 
+end entity VCO; 
+
+architecture avco of vco is 
+    constant TwoPi: real := 6.283118530718; -- 2pi 
+
+    quantity Phase : real; 
+
+    -- define a branch for the output voltage source 
+
+    quantity Vout across Iout through OutTerminal to electrical'reference; 
+
+begin 
+   -- use break to set the phase initial condition 
+   break Phase => 0.0; 
+
+   -- another break statement keeps the phase within 0.. 2pi 
+   break Phase => Phase mod TwoPi on Phase'above(TwoPi); 
+
+   -- phase equation 
+   Phase'dot == TwoPi*realmax(0.5E6, fc+(Vin-Vc)*df); 
+
+     -- output voltage source equation 
+     Vout == 2.5*(1.0+sin(Phase)); 
+
+end architecture avco; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams
new file mode 100644
index 0000000..3e33069
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test180.ams
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test180.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test180.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the break statement.it checks simple break and break on
+-- codition.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH; -- GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity VCO is
+  port(terminal InTerminal,OutTerminal: electrical);
+end VCO; 
+ 
+architecture PhaseIntegrator of VCO is
+
+  quantity Vin across Iin through InTerminal to OutTerminal;
+  constant TwoPi: real := 6.283118530718; -- 2pi
+  quantity Phase : real; -- phase is a free quantity:
+  quantity Vout across Iout through OutTerminal;
+
+begin
+
+  break Phase => TwoPi;
+  Vout == 2.5*(sin(Phase)); -- output statement
+
+end PhaseIntegrator; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams
new file mode 100644
index 0000000..4c7caf4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/test181.ams
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test181.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test181.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the break statement.it checks simple break and break on
+-- codition.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH; -- GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity VCO is
+  port(terminal InTerminal,OutTerminal: electrical);
+end VCO; 
+ 
+architecture PhaseIntegrator of VCO is
+  quantity Vin across Iin through InTerminal to OutTerminal;
+  constant TwoPi: real := 6.283118530718; -- 2pi
+  quantity Phase : real; -- phase is a free quantity:
+  quantity Vout across Iout through OutTerminal;
+begin
+  break Phase => TwoPi;
+  -- break allows to define the initial conditions
+  break Phase => 0.0 on Phase'above(TwoPi);
+  Vout == 2.5*(sin(Phase)); -- output statement
+end PhaseIntegrator; 
+
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/torsional_oscillator.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/torsional_oscillator.ams
new file mode 100644
index 0000000..084f90c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/break_stmt/torsional_oscillator.ams
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: torsional_oscillator.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+--Torsional oscillator
+ENTITY bouncer IS
+END ENTITY bouncer;
+
+ARCHITECTURE simple OF bouncer IS
+	CONSTANT m1 : REAL := 0.0;
+	CONSTANT md : REAL := 0.0;
+	CONSTANT mc : REAL := 1.0;
+	QUANTITY om : REAL;
+    QUANTITY ph : REAL;
+	
+BEGIN	 
+	    --Initvalues
+	    BREAK om => 0.0, ph => 0.0;
+	
+        (om'dot) == 10000.0*(1.0 - 1000.0 * ph);
+        (ph'dot) == om;    
+        
+END ARCHITECTURE simple;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/2nd_order_ode.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/2nd_order_ode.ams
new file mode 100644
index 0000000..88b5c9a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/2nd_order_ode.ams
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: 2nd_order_ode.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+entity VanDerPol is 
+    generic (m: real := 1.0); 
+end entity VanDerPol; 
+
+architecture SecondOrderODE of VanDerPol is 
+quantity x:real;
+begin 
+    -- the break statement sets the initial conditions 
+    break x => 0.0, x'dot => 0.1; 
+
+    -- second-order Van Der Pol ODE 
+    x'dot'dot == -x -m*(x*x - 1.0)*x'dot;
+end architecture SecondOrderODE; 
+
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test1.ams
new file mode 100644
index 0000000..ec89623
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test1.ams
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test1.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+--   terminal n1,n2,n3: electrical;
+
+--   quantity vl1 across il1 through n1 ;
+--   quantity vl2 across il2 through n2 ;
+--   quantity vl3 across il3 through n2 ;
+
+--   quantity vs across n1 ;
+
+   quantity x:real;
+   quantity y:real;
+   quantity z:real;
+
+--   constant l : REAL := 0.01;
+
+BEGIN 
+
+--r1 : vl1 == il1'dot * l;
+--r2 : vl2 == il2'dot * l;
+--r3 : vl3 == il3'dot * l;
+
+e1 : x == (16.00 - (6.00 * y)) / 4.00;
+e2 : y == (5.00 - x)/2.00;
+e3 : z == x+y;
+
+--eqn4:vs == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+--                                * real(time'pos(now)) * 1.0e-15);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test2.ams
new file mode 100644
index 0000000..40e1a6e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/free_equations/test2.ams
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test2.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION TAN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   quantity qfree:real:=0.0;
+   quantity qdot : real ;
+   quantity comp : real ;
+BEGIN 
+
+e1 : qdot  == qfree'dot;
+
+
+e2:qfree == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                                * real(time'pos(now)) * 1.0e-15);
+
+e3 : if (qfree <= 0.0) use
+         comp == -1.00;
+     else
+         comp == 1.00;
+     end use; 
+        
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
new file mode 100644
index 0000000..c3bf7ab
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: above_attr.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+   -- NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+entity test is
+end entity;
+
+architecture atest of test is
+  constant R1: real :=10.0;
+  constant R2: real :=5.0;
+  terminal T1,T2:electrical;
+  quantity V1 across I1 through T1 to T2;
+  quantity V2 across I2 through T2;
+  quantity VS across T1;
+  quantity rt:real;
+  signal ABSIG,o:boolean;
+  --signal y:bit;
+
+begin
+
+
+ABSIG<=V1'above(V2+1.0);
+            
+ testbench:PROCESS
+        VARIABLE outline : LINE;
+        VARIABLE Headline   : string(1 TO 33) :=
+            "time ABSIG";
+        VARIABLE   seperator    : string(1 TO 1) := " ";
+        VARIABLE   flag     : bit := '0';
+        VARIABLE tmp:bit;
+        FILE outfile: text OPEN WRITE_MODE IS "above_attr.out";
+    BEGIN
+        IF (flag = '0') THEN
+            flag := '1';
+            WRITE(outline,Headline);
+            WRITELINE(outfile,outline);
+        ELSE
+            WRITE(outline, now);
+            WRITE(outline,seperator);
+            IF (ABSIG = true) THEN
+            tmp:='1';
+            ELSE
+            tmp:='0';
+            WRITE(outline,tmp);
+            END IF;
+            WRITE(outline,seperator);
+            writeline(outfile,outline);
+        END IF;
+        WAIT ON ABSIG;
+    END PROCESS;
+
+e1:      V1 == I1*R1;
+e2:      V2 == I2*R2;
+esource: VS == 5.0 * sin(2.0 * 3.141592 *100.0 * real(time'pos(now))*1.0e-15);
+
+END ARCHITECTURE atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/am_modulation.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/am_modulation.ams
new file mode 100644
index 0000000..cd49b93
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/am_modulation.ams
@@ -0,0 +1,135 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: am_modulation.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+--Package defining eleectrical nature and some functions...
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+USE work.electricalSystem.ALL;
+----------------------------------------------------------------------  
+-- The sinusoidal voltage source definition begins.....  
+----------------------------------------------------------------------  
+-- Schematic of the sinusoidal voltage source:  
+-- -------------------------------------------  
+--  
+--        p o----(~)----o m a sinusoidal voltage of amplitude ampl  
+--                  Vs          and frequency 'freq'.  
+----------------------------------------------------------------------  
+ 
+--entity declaration.  
+ENTITY sineSource IS    
+    generic (ampl,freq : REAL);  
+    PORT(TERMINAL p,m: ELECTRICAL); --Interface ports.  
+END;  
+ 
+--architecture declaration.  
+ARCHITECTURE behav OF sineSource IS  
+    --quantity declarations.  
+    quantity v_in across i_out through p to m;  
+BEGIN  
+     -- The sinusoidal voltage source equation.        
+     v_in==ampl * sin (2.0*3.14* freq *  real(time'pos(now)) * 1.0e-15); --input sinusoidal source  
+END;  
+   
+USE work.electricalSystem.ALL; 
+----------------------------------------------------------------------  
+-- The resistor definition begins.....  
+----------------------------------------------------------------------  
+-- Schematic of the resistor component:  
+--  
+--        p o----/\/\/\----o m  
+--          
+----------------------------------------------------------------------  
+ 
+ENTITY resistor IS  
+    GENERIC  (resistance    : REAL);        --resistance value given as a generic parameter.
+ 
+    PORT     (TERMINAL p,m  : ELECTRICAL);    --Interface ports.  
+END resistor;  
+ 
+ARCHITECTURE behav OF resistor IS  
+    quantity r_e across r_i through p to m;  
+BEGIN  
+    r_i == r_e/resistance;  -- The ohmic resistance equation.  
+END behav;  
+----------------------------------------------------------------  
+ 
+ 
+USE work.electricalSystem.ALL;
+-----------------------------------------------------------------     
+--testbench  
+-- ==============================================================  
+--  n1                    R2 1k                     n2  
+--  o __________________/\/\/\__________________o                    
+--  |             |               |        |                    
+--  | T1          |               |        |  
+--  |             <               <        |  
+-- (~)modulation  < R1            <    R3 (~) basiswave  
+--  | 100(sinwt)  < 1k            <    1k    |  320(sinwt)   
+--  |              |               |        |  
+--  |             |               |        |  
+--  o___________________________________________o  
+--                        | gnd          
+--                      -----      
+ 
+ENTITY network IS  
+END;  
+                                                 
+ARCHITECTURE behav OF network IS 
+component sineSource IS
+    generic (ampl,freq : REAL);
+    PORT(TERMINAL p,m: ELECTRICAL); --Interface ports.
+END component;
+
+component resistor IS
+    GENERIC  (resistance    : REAL);        --resistance value given as a generic parameter.
+    
+    PORT     (TERMINAL p,m  : ELECTRICAL);    --Interface ports.
+END component;
+     
+    terminal n1,n2: ELECTRICAL;  
+BEGIN  
+    Modulation  : sineSource  generic MAP(100.0,5000.0) PORT MAP(n1,ground);
+ 
+    R1   : Resistor    generic MAP(1000.0)       PORT MAP(n1,ground);
+ 
+    Groundwave  : sineSource  generic MAP(320.0,500.0)  PORT MAP(n2,ground);
+ 
+    R3   : Resistor    generic MAP(1000.0)       PORT MAP (n2,ground);
+ 
+    R2   : Resistor    generic MAP(1000.0)       PORT MAP (n1, n2);
+ 
+END;              
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams
new file mode 100644
index 0000000..eb636b5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/generic_model.ams
@@ -0,0 +1,145 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: generic_model.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- trying to check both ports and generics.
+-- resistor component below has both port and generic.
+-- same example as in mixed_mode_1 with ports
+-- simulate for 2e10
+-- end comments by shishir.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use std.textio.all ;
+
+entity NOT_GATE is
+  generic ( delay : TIME := 100 ns ) ; 
+  port (
+    C : in bit;
+    Cbar : out bit);
+ 
+end NOT_GATE;
+ 
+architecture dataflow  of NOT_GATE is
+ --signal my : bit := '0'; 
+begin  -- dataflow
+ 
+  Cbar <= not C after delay ;
+ 
+end dataflow ;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+
+entity resistor is
+        generic ( resvalue : real := 100.0 ) ;
+        port (terminal P, N : electrical );
+end resistor;
+ 
+architecture behav of resistor is
+   quantity VPTON across IPTON through P to N;
+begin
+        res1 : VPTON == IPTON * resvalue ;
+end behav;
+
+use work.electricalSystem.all;
+use std.textio.all;
+
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+  component NOT_GATE is
+  generic ( delay : TIME := 100 ns) ; 
+  port (
+    C : in bit;
+    Cbar : out bit);
+        end component ;
+   for all : NOT_GATE use entity work.NOT_GATE(dataflow) ;
+
+   component resistor is
+           generic ( resvalue : real := 100.0 ) ;
+           port (terminal P, N : electrical );
+        end component;
+        for all : resistor use entity work.resistor(behav);
+ 
+  terminal n1,n2 : electrical;
+  QUANTITY vIn ACROSS iIn THROUGH n1 ;
+  --QUANTITY vr1 ACROSS ir1 THROUGH n1 to n2;
+  --QUANTITY vr2 ACROSS ir2 THROUGH n2 ;
+
+  signal y:bit:='0';
+
+BEGIN
+
+-- digital component instantiation.
+   D2 : NOT_GATE generic map ( delay => 1000 ns) port map(C=>y, Cbar=>y);       
+
+ testbench:PROCESS
+        VARIABLE outline : LINE;
+        VARIABLE Headline   : string(1 TO 8) :=
+            "time y ";
+        VARIABLE   seperator    : string(1 TO 1) := " ";
+        VARIABLE   flag     : bit := '0';
+        FILE outfile: text OPEN WRITE_MODE IS "generic_model.out";
+    BEGIN
+        IF (flag = '0') THEN
+            flag := '1';
+            WRITE(outline,Headline);
+            WRITELINE(outfile,outline);
+        ELSE
+            WRITE(outline, now);
+            WRITE(outline,seperator);
+            WRITE(outline,y);
+            WRITE(outline,seperator);
+            writeline(outfile,outline); 
+        END IF;
+        WAIT ON y;
+    END PROCESS;
+
+-- analog  component instantiation.
+-- for some strange reason if i put it above the process, it does not work.
+
+  R1 : resistor generic map ( resvalue => 500.0) port map (P => n1, N => n2); 
+  --R1 : resistor port map (P => n1, N => n2); 
+  R2 : resistor port map (P => n2, N => ground); 
+--    R1 : vr1 == ir1 * 100.0 ;
+ --   R2 : vr2 == ir2 * 100.0 ;
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/above_attr.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/above_attr.out
new file mode 100644
index 0000000..34d04f6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/above_attr.out
@@ -0,0 +1,21 @@
+time ABSIGtestbenchwork_Dte
+1098543.277411 NS  
+4034001.034625 NS 0 
+11029402.988035 NS  
+14000633.820645 NS 0 
+21180065.574642 NS  
+24074961.958137 NS 0 
+31051068.654154 NS  
+34010938.898262 NS 0 
+41184808.429215 NS  
+44077392.700384 NS 0 
+51052348.254524 NS  
+54011554.141123 NS 0 
+61185092.495303 NS  
+64077540.337822 NS 0 
+71052427.799030 NS  
+74011594.434932 NS 0 
+81185113.202536 NS  
+84077552.980693 NS 0 
+91052436.416308 NS  
+94011600.731912 NS 0 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/generic_model.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/generic_model.out
new file mode 100644
index 0000000..5e1e142
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/generic_model.out
@@ -0,0 +1,21 @@
+time y 
+1000 NS 1 
+2000 NS 0 
+3000 NS 1 
+4000 NS 0 
+5000 NS 1 
+6000 NS 0 
+7000 NS 1 
+8000 NS 0 
+9000 NS 1 
+10000 NS 0 
+11000 NS 1 
+12000 NS 0 
+13000 NS 1 
+14000 NS 0 
+15000 NS 1 
+16000 NS 0 
+17000 NS 1 
+18000 NS 0 
+19000 NS 1 
+20000 NS 0 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_1.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_1.out
new file mode 100644
index 0000000..5530249
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_1.out
@@ -0,0 +1,21 @@
+time y
+1000 NS 1 
+2000 NS 0 
+3000 NS 1 
+4000 NS 0 
+5000 NS 1 
+6000 NS 0 
+7000 NS 1 
+8000 NS 0 
+9000 NS 1 
+10000 NS 0 
+11000 NS 1 
+12000 NS 0 
+13000 NS 1 
+14000 NS 0 
+15000 NS 1 
+16000 NS 0 
+17000 NS 1 
+18000 NS 0 
+19000 NS 1 
+20000 NS 0 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_2.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_2.out
new file mode 100644
index 0000000..5530249
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/iofiles/mixed_model_2.out
@@ -0,0 +1,21 @@
+time y
+1000 NS 1 
+2000 NS 0 
+3000 NS 1 
+4000 NS 0 
+5000 NS 1 
+6000 NS 0 
+7000 NS 1 
+8000 NS 0 
+9000 NS 1 
+10000 NS 0 
+11000 NS 1 
+12000 NS 0 
+13000 NS 1 
+14000 NS 0 
+15000 NS 1 
+16000 NS 0 
+17000 NS 1 
+18000 NS 0 
+19000 NS 1 
+20000 NS 0 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mesh.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mesh.ams
new file mode 100644
index 0000000..f0e4f12
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mesh.ams
@@ -0,0 +1,143 @@
+
+-- Copyright (C) 1998-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: mesh.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- /**************************************************************************/
+-- /* File: mesh.ams                                                         */
+-- /**************************************************************************/
+-- /* Author:           Venkateswaran Krishna                                */
+-- /* Date of creation: Dec 1 1998                                           */
+-- /* Last changed by:  Venkateswaran Krishna                                */
+-- /**************************************************************************/
+-- Roadmap
+----------
+--While it might look like a trivial circuit this model actually
+--managed to find a breach in seams!! Specifically with the code
+--generation of generics... so it is important to have it as part
+--of the test suite. The model is a small mesh ckt with 3 resistors
+--and 2 voltage sources.. simple nodal soln of the mesh is all that
+--seams has to do
+--
+--
+--    t1    1      t2    3      t3
+--    o---/\/\/\---o---/\/\/\---o
+--    |            |            |
+--    |            <            |
+--   ( )5v         <2          ( )10v
+--    |            <            |
+--    |            |            |
+--    o------------o------------o
+--                 |
+--                _|
+--                \/
+
+--package definition
+PACKAGE electricalSystem IS
+    
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+    
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity resistor is
+   generic(r: real := 10000.0 );  --- resistance
+   port( terminal tr1,tr2 : electrical); --- interface ports
+end resistor;
+
+architecture rbehavior of resistor is
+   quantity Vr across Ir through tr1 to tr2;
+begin
+   Vr == Ir*r;
+end architecture rbehavior; --- of resisitor
+
+
+use work.electricalSystem.all;
+ENTITY constVSource IS
+    GENERIC (voltage : real := 10.0);
+    PORT (TERMINAL ta4, tb4 : electrical );
+END constVSource;
+
+ARCHITECTURE behavioral OF constVSource IS
+    quantity vsource across isource through ta4 TO tb4;
+BEGIN  -- behavior
+    constSource_equation: vsource == voltage;
+END behavioral;
+
+
+use work.electricalSystem.all;
+
+entity mesh is
+end mesh;
+
+architecture struc of mesh is
+
+  terminal t1, t2, t3  : electrical;
+
+  component resComp
+    generic(r: real := 10000.0 );  --- resistance
+    port( terminal tr1,tr2 : electrical); --- interface ports
+  end component;
+
+  for all : rescomp use entity work.resistor(rbehavior);
+
+  component source
+    GENERIC (voltage : real := 10.0);
+    PORT (TERMINAL ta4, tb4 : electrical );
+  END component;
+
+  for all : source use entity work.constVSource(behavioral);
+
+begin
+
+  voltage_source1: source
+    generic map(5.0)
+    port map(t1, ground);
+
+  voltage_source2: source
+    port map(t3, ground);
+
+  r1: resComp
+    generic map(1.0)
+    port map(t1, t2);
+
+  r2: resComp
+    generic map(2.0)
+    port map(t2, ground);
+
+  r3: resComp
+    generic map(3.0)
+    port map(t2, t3);
+
+end;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams
new file mode 100644
index 0000000..10fd3bb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_1.ams
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: mixed_model_1.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- an example of a model having both a signal assignment statement
+-- as well as a simple simultaneous statement.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+    CONSTANT resistance1 : real := 100.0;        -- value of R1
+    terminal n1 : electrical;
+  QUANTITY vIn ACROSS n1;
+  QUANTITY vR ACROSS iR THROUGH n1 ;
+  signal y:bit:='0';
+BEGIN
+
+process(y)
+begin
+  y <= not(y) after 1000 ns;
+ 
+end process;
+
+ testbench:PROCESS
+        VARIABLE outline : LINE;
+        VARIABLE Headline   : string(1 TO 8) :=
+            "time y";
+        VARIABLE   seperator    : string(1 TO 1) := " ";
+        VARIABLE   flag     : bit := '0';
+        FILE outfile: text OPEN WRITE_MODE IS "mixed_model_1.out";
+    BEGIN
+        IF (flag = '0') THEN
+            flag := '1';
+            WRITE(outline,Headline);
+            WRITELINE(outfile,outline);
+        ELSE
+            WRITE(outline, now);
+            WRITE(outline,seperator);
+            WRITE(outline,y);
+            WRITE(outline,seperator);
+            writeline(outfile,outline); 
+        END IF;
+        WAIT ON y;
+    END PROCESS;
+  res_stmt1: vR == iR * resistance1 ;
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams
new file mode 100644
index 0000000..dd80c23
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/mixed_model_2.ams
@@ -0,0 +1,143 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: mixed_model_2.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This is a model that has both a signal assignment statement as well as a
+-- simple simultaneous statement.  So supposedly uses both digital and
+-- analog kernel but does not have any interaction between digital and
+-- analog portion.  Also there is a port declaration to check whether
+-- addition of code for terminals in ports has not affected the digital
+-- part.  same example as in mixed_mode_1 with ports simulate for 2e10 end
+-- comments by shishir.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use std.textio.all ;
+
+entity NOT_GATE is
+ 
+  port (
+    C : in bit;
+    Cbar : out bit);
+ 
+end NOT_GATE;
+ 
+architecture dataflow  of NOT_GATE is
+ 
+begin  -- dataflow
+ 
+  Cbar <= not C after 1000 ns;
+ 
+end dataflow ;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+
+entity resistor is
+        port (terminal P, N : electrical );
+end resistor;
+ 
+architecture behav of resistor is
+   quantity VPTON across IPTON through P to N;
+begin
+        res1 : VPTON == IPTON * 100.0 ;
+end behav;
+
+use work.electricalSystem.all;
+use std.textio.all;
+
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+  component NOT_GATE is
+  port (
+    C : in bit;
+    Cbar : out bit);
+        end component ;
+   for all : NOT_GATE use entity work.NOT_GATE(dataflow) ;
+
+   component resistor is
+           port (terminal P, N : electrical );
+        end component;
+        for all : resistor use entity work.resistor(behav);
+ 
+  terminal n1,n2 : electrical;
+  QUANTITY vIn ACROSS iIn THROUGH n1 ;
+  QUANTITY vr1 ACROSS ir1 THROUGH n1 to n2;
+  QUANTITY vr2 ACROSS ir2 THROUGH n2 ;
+
+  signal y:bit:='0';
+
+BEGIN
+
+-- digital component instantiation.
+   D2 : NOT_GATE port map(C=>y, Cbar=>y);       
+
+ testbench:PROCESS
+        VARIABLE outline : LINE;
+        VARIABLE Headline   : string(1 TO 8) :=
+            "time y";
+        VARIABLE   seperator    : string(1 TO 1) := " ";
+        VARIABLE   flag     : bit := '0';
+        FILE outfile: text OPEN WRITE_MODE IS "mixed_model_2.out";
+    BEGIN
+        IF (flag = '0') THEN
+            flag := '1';
+            WRITE(outline,Headline);
+            WRITELINE(outfile,outline);
+        ELSE
+            WRITE(outline, now);
+            WRITE(outline,seperator);
+            WRITE(outline,y);
+            WRITE(outline,seperator);
+            writeline(outfile,outline); 
+        END IF;
+        WAIT ON y;
+    END PROCESS;
+
+-- analog  component instantiation.
+-- for some strange reason if i put it above the process, it does not work.
+
+  R1 : resistor port map (P => n1, N => n2); 
+  R2 : resistor port map (P => n2, N => ground); 
+--    R1 : vr1 == ir1 * 100.0 ;
+ --   R2 : vr2 == ir2 * 100.0 ;
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/multiple_res_comp.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/multiple_res_comp.ams
new file mode 100644
index 0000000..c09cd0f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/multiple_res_comp.ams
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: multiple_res_comp.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity bad_resistor is
+	port (terminal P, N : electrical );
+end bad_resistor;
+
+architecture behav of bad_resistor is 
+   quantity VPTON across IPTON through P to N;
+begin
+	res1 : VPTON == IPTON * 100.0 ;
+end behav;
+
+use work.electricalsystem.all;
+entity good_resistor is
+	port (terminal P, N : electrical );
+end good_resistor;
+
+architecture behav of good_resistor is 
+   quantity VP across IP through P to N;
+begin
+	res1 : VP == IP * 1000.0 ;
+end behav;
+
+
+use work.electricalsystem.all;
+
+entity resistor_ckt is 
+end resistor_ckt;
+
+architecture structure of resistor_ckt is
+
+	component bad_resistor is 
+           port (terminal P, N : electrical );
+	end component;
+
+	component good_resistor is 
+           port (terminal P, N : electrical );
+	end component;
+
+        for all : good_resistor use entity work.good_resistor(behav);  
+        for all : bad_resistor use entity work.bad_resistor(behav);  
+
+	terminal X,Y,Z,t1,t2 : electrical;
+	quantity vout across iout through t2 to electrical'reference;
+	quantity vs across X to electrical'reference;
+
+begin
+	R1 : bad_resistor port map (P => X, N => Y);
+	R2 : bad_resistor port map (P => Y, N => Z);
+ 	R3 : vout == iout * 1200.0;
+	R4 : good_resistor port map (P => Z, N => t1);
+	R5 : good_resistor port map (P => t1, N => t2);
+      vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+end structure;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plate.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plate.ams
new file mode 100644
index 0000000..5ceeaf0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plate.ams
@@ -0,0 +1,117 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: parallel-plate.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This model was tested and compared with SPICE.
+-- The results match with SPICE
+-- The model implements a simple parallel place cap with just 
+-- one top and one bottom  plate.
+-- simulation time 2e11.
+-- Initially proposed by Dr. Carter.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity plate is 
+	generic (
+		cell_resistance : real := 1000.0 
+		);
+
+	port ( 
+		terminal up, down, left, right, top : electrical 
+	    );
+end entity plate;
+
+architecture behav of plate is 
+
+quantity Vup across Iup through up to top ;
+quantity Vdown across Idown through down to top ;
+quantity Vleft across Ileft through left to top ;
+quantity Vright across Iright through right to top ;
+
+begin
+
+	Rup : Vup == Iup * cell_resistance ; 
+	Rdown : Vdown == Idown * cell_resistance ; 
+	Rleft : Vleft == Ileft * cell_resistance ; 
+	Rright : Vright == Iright * cell_resistance ; 
+end behav ;
+
+
+use work.electricalSystem.all;
+
+entity parallel_plate_cap is
+end entity;
+
+architecture struc of parallel_plate_cap is
+	component plate is 
+        generic (
+                cell_resistance : real := 1000.0
+                );
+	    port (
+		   terminal up, down, left, right, top : electrical
+                 );
+	end component ;
+        for all : plate use entity work.plate(behav);    
+
+	terminal up1, up2, down1, down2, left1, left2, right1, right2, top1, top2 : electrical ;
+
+	quantity vcap across icap through top1 to top2 ;
+	quantity vrgnd across irgnd through top2 ;
+	quantity vs1 across left1 to left2;
+	quantity vs2 across right1 to right2;
+	quantity vs3 across up1 to up2;
+	quantity vs4 across down1 to down2;
+
+	constant cell_cap : real := 1.0e-6;
+	
+begin
+	plate1 : plate port map ( up1, down1, left1, right1, top1) ;
+        plate2 : plate port map ( up2, down2, left2, right2, top2) ;
+	--plate2 : plate port map ( up2, down2, left2, right2, ground) ;
+	
+	capeqn : icap == cell_cap * vcap'dot;
+	-- there should be some ground
+	resgnd : vrgnd == irgnd * 1000.0 ;
+        vsrc1 : vs1  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                               * real(time'pos(now)) * 1.0e-15);
+        vsrc2 : vs2  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                               * real(time'pos(now)) * 1.0e-15);
+        vsrc3 : vs3  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                               * real(time'pos(now)) * 1.0e-15);
+        vsrc4 : vs4  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                               * real(time'pos(now)) * 1.0e-15);
+
+end struc ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plates4.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plates4.ams
new file mode 100644
index 0000000..a4ebbe2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/parallel-plates4.ams
@@ -0,0 +1,161 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: parallel-plates4.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- This model was tested and compared with SPICE.
+-- The results match with SPICE
+-- The model implements a simple parallel plate cap with just 
+-- one top and one bottom  plate.
+-- The top and bottom plates have been divided into 4 sub plates.
+-- Actually its like 4 parallel-plate subsections have been connected
+-- to form the capacitor.
+-- simulation time 2e11.
+-- Initially proposed by Dr. Carter.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity plate is 
+	generic (
+		cell_resistance : real := 1000.0 
+		);
+
+	port ( 
+		terminal up, down, left, right, top : electrical 
+	    );
+end entity plate;
+
+architecture behav of plate is 
+
+quantity Vup across Iup through up to top ;
+quantity Vdown across Idown through down to top ;
+quantity Vleft across Ileft through left to top ;
+quantity Vright across Iright through right to top ;
+
+begin
+
+	Rup : Vup == Iup * cell_resistance ; 
+	Rdown : Vdown == Idown * cell_resistance ; 
+	Rleft : Vleft == Ileft * cell_resistance ; 
+	Rright : Vright == Iright * cell_resistance ; 
+end behav ;
+
+
+use work.electricalSystem.all;
+
+entity parallel_plate_cap is
+	port ( 
+	     terminal up1, up2, down1, down2, left1, left2, right1, right2, top1, top2: electrical 
+	    );
+end entity;
+
+architecture struc of parallel_plate_cap is
+	component plate is 
+        generic (
+                cell_resistance : real := 1000.0
+                );
+	    port (
+		   terminal up, down, left, right, top : electrical
+                 );
+	end component ;
+        for all : plate use entity work.plate(behav);    
+
+	-- this need not be in the port list but i am adding it
+	-- to observe vcap uniquely.
+	--terminal top1, top2 : electrical ;
+	quantity vcap across icap through top1 to top2 ;
+	quantity vrgnd across irgnd through top2 ;
+--	quantity vs1 across left1 to left2;
+--	quantity vs2 across right1 to right2;
+--	quantity vs3 across up1 to up2;
+--	quantity vs4 across down1 to down2;
+
+	constant cell_cap : real := 1.0e-8;
+	
+begin
+	plate1 : plate port map ( up1, down1, left1, right1, top1) ;
+        plate2 : plate port map ( up2, down2, left2, right2, top2) ;
+	--plate2 : plate port map ( up2, down2, left2, right2, ground) ;
+	
+	capeqn : icap == cell_cap * vcap'dot;
+	-- there should be some ground
+	resgnd : vrgnd == irgnd * 1000.0 ;
+--        vsrc1 : vs1  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                   --            * real(time'pos(now)) * 1.0e-15);
+ --       vsrc2 : vs2  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+ --                              * real(time'pos(now)) * 1.0e-15);
+  --      vsrc3 : vs3  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+   --                            * real(time'pos(now)) * 1.0e-15);
+    --    vsrc4 : vs4  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+     --                          * real(time'pos(now)) * 1.0e-15);
+
+end struc ;
+
+use work.electricalSystem.all;
+
+entity real_cap is 
+end entity ;
+
+architecture struct of real_cap is 
+	component parallel_plate_cap is
+	port ( 
+	     terminal up1, up2, down1, down2, left1, left2, right1, right2, top1, top2: electrical 
+	    );
+	end component ;
+
+	for all : parallel_plate_cap use entity work.parallel_plate_cap(struc);
+
+	terminal u1, u2, u3 , u4, d1, d2, d3, d4, l1, l2 , r1, r2, r3, r4 , t1, t2, t3, t4: electrical ;
+	terminal d11, d21, d31, d41, l11, l21 , r11, r21, r31, r41 , t11, t21, t31, t41: electrical ;
+	-- not needed.
+	--terminal l3 , l4 : electrical ;
+
+	quantity vs across l1 to l2 ;
+	quantity vs1 across l11 to l21 ;
+
+
+begin
+
+	p1 : parallel_plate_cap port map (u1, u2, d1, d2, l1, l2, r1, r2, t1, t2);
+	p2 : parallel_plate_cap port map (u3, u4, d3, d4, r1, r2, r3, r4, t3, t4);
+	p3 : parallel_plate_cap port map (d1, d2, d11, d21, l11, l21, r11, r21, t11, t21);
+	p4 : parallel_plate_cap port map (d3, d4, d31, d41, r11, r21, r31, r41, t31, t41);
+
+        vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                              * real(time'pos(now)) * 1.0e-15);
+        vsrc1 : vs1  == 5.0 * sin(2.0 * 3.1415 * 10.0e3 --sine source
+                              * real(time'pos(now)) * 1.0e-15);
+
+end ;	
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/res_component.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/res_component.ams
new file mode 100644
index 0000000..32f8762
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/res_component.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: res_component.ams,v 1.1 2002-03-27 22:11:17 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity resistor is
+	port (terminal P, N : electrical );
+end resistor;
+
+architecture behav of resistor is 
+   quantity VPTON across IPTON through P to N;
+begin
+	res1 : VPTON == IPTON * 100.0 ;
+end behav;
+
+
+use work.electricalsystem.all;
+
+entity resistor_ckt is 
+end resistor_ckt;
+
+architecture structure of resistor_ckt is
+
+	component resistor is 
+           port (terminal P, N : electrical );
+	end component;
+        for all : resistor use entity work.resistor(behav);  
+	terminal X,Y,Z,t1,t2 : electrical;
+	quantity vout across iout through t2 to electrical'reference;
+	quantity vs across X to electrical'reference;
+
+begin
+	R1 : resistor port map (P => X, N => Y);
+	R2 : resistor port map (P => Y, N => Z);
+ 	--R3 : vout == iout * 200.0;
+	R3 : resistor port map (P => t2, N => ground);
+	R4 : resistor port map (P => Z, N => t1);
+	R5 : resistor port map (P => t1, N => t2);
+      vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+end structure;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/inverter_model/inverter.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/inverter_model/inverter.ams
new file mode 100644
index 0000000..ae9e5be
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/inverter_model/inverter.ams
@@ -0,0 +1,431 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: inverter.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- /**************************************************************************/
+-- /* File: inverter.ams                                                     */
+-- /**************************************************************************/
+-- /* Author(s):        Vishwashanth Kasula Reddy & Venkateswaran Krishna    */
+-- /* Date of creation: Mon Nov 30th 1998                                    */
+-- /**************************************************************************/
+--Roadmap:
+----------
+--This is a mixed signal model of an inverter... The input is a bit signal
+-- which is converted to a 5/0 value realSignal. This signal is then given
+-- to the input of the cmos inverter and the output of the cmos inverter is
+-- then given to a atod... the final output is then a bit signal which is
+-- the inverse of the input bit signal...
+
+------------------------------------------------------------------------
+--                             /\ Vdd
+--                              | 
+--                              o S
+--                              |
+--                             --
+--                     -----<-|p
+--                     |       --
+--                     |        |
+--          --0--/\/\--0      D 0--------o--------o----------
+--         + /\        |        |        |        |        /\ +
+--            |        |       --        >        |         |
+--  vin is    |        ----->-|n         <       ---       Vout ==> atod ==> op
+-- atod(inp)  Vin              --        >       ---        |
+--            |                 |        <        |         |
+--            |                 o S      |        |         |
+--         - \/                 |        |        |        \/ -
+--          -------------------------------------------------
+--                                       |
+--                                      ---
+--                                       -
+------------------------------------------------------------------------
+
+-------*****************************************************************
+--                   Package definition Begins 
+-------*****************************************************************
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+--    ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+------- Square wave generator
+
+-------*****************************************************************
+--                   New Entity Begins : 1 BIT A/D CONVERTER
+-------*****************************************************************
+
+use work.electricalsystem.all;
+
+entity a2d1bit is
+	generic (vlo : real := 0.0;
+	        vhi : real := 10.0;
+	        ped : time := 1 ns);
+	port (signal input : in bit;
+	      terminal pos, neg : electrical);
+end entity a2d1bit;
+
+architecture behav of a2d1bit is
+  quantity vsqr across isqr through pos to neg;
+  signal vsig : real := 0.0;
+begin
+
+  vsqr == vsig;
+  break on vsig;
+
+  bit2real : process
+  begin
+    if(input = '0') then
+      vsig <= vlo;
+    else
+      vsig <= vhi;
+    end if;
+    wait on input;
+  end process; --- generator;
+
+end architecture behav; 
+
+-------*****************************************************************
+--                   New Entity Begins : RESISTOR       
+-------*****************************************************************
+use work.electricalSystem.all;
+
+entity resistor is
+   generic(r: real := 1.0 );  --- resistance
+   port( terminal tr1,tr2 : electrical); --- interface ports
+end resistor;
+
+architecture rbehavior of resistor is
+   quantity Vr across Ir through tr1 to tr2;
+begin
+   Vr == Ir*r;
+end architecture rbehavior; --- of resistor
+
+-------*****************************************************************
+--                   New Entity Begins : PMOS TRANSISTOR
+-------*****************************************************************
+
+----- PMOS 
+--use std.textio.all;
+use work.electricalsystem.all;
+
+entity pmos is
+    port (terminal g,s,d : electrical);
+end entity pmos;
+
+architecture behav of pmos is
+  terminal g2, d1 : electrical;
+  quantity vdsg across idsgi through d1 to s;
+  quantity idsg through d1 to s;
+  quantity vdsr across idsr through d1 to d;
+  quantity vds across d to s;
+  quantity vgs_in across g to s;
+  quantity vgsr across igsr through g to g2;
+  quantity vgs across igs through g2 to s;
+  constant vth : real := 0.5;
+  constant hfe : real := 3.54e-03;
+--  quantity flag : real := 1.0; 
+--    quantity vgs : real;
+--  signal vgs_sig,vds_sig : real := 0.0;
+
+begin
+  ------ Setting initial conditions
+--  init : break vds => 1.0;
+
+  opn : vdsg == 1.0e+06 * idsgi ; -- almost 
+  d12_res : vdsr == idsr * 1.0;
+  g12res : vgsr == igsr * 1.0;
+  g_oup : vgs == igs * 1.0;
+  
+--  flag == 1.0;
+ 
+---- Current is in Micro Amps.
+
+  ------ Cut OffRegion
+    if((vgs <= 0.0) and (vgs >= vth)) use
+	gnc :    idsg == 0.0;
+
+  ------ Linear Region
+  elsif((vds >= (vgs-vth)) and (vds < 0.0)) use
+      	gnl :    idsg == -1.0*hfe*(((vgs-vth)*vds) - (pow(vds,2.0)/2.0));
+ 
+  ------ Saturation Region
+  elsif((vds < (vgs-vth)) and (vgs < vth)) use
+      gns2 : idsg == -1.0*(hfe/2.0)*(pow((vgs-vth),2.0));
+
+  ------ Other conditions
+ -- elsif(vgs < 0.0 or vds <= 0.0) use
+  elsif(1.0 = 1.0) use
+      temp : idsg == 0.0;
+  end use;
+
+end architecture behav; --- of pmos;
+
+
+-------*****************************************************************
+--                   New Entity Begins : NMOS TRANSISTOR
+-------*****************************************************************
+
+----- NMOS 
+--use std.textio.all;
+use work.electricalsystem.all;
+
+entity nmos is
+    port (terminal g,s,d : electrical);
+end entity nmos;
+
+architecture behav of nmos is
+  terminal g2, d1 : electrical;
+  quantity vdsg across idsgi through d1 to s;
+  quantity idsg through d1 to s;
+  quantity vdsr across idsr through d1 to d;
+  quantity vds across d to s;
+  quantity vgs_in across g to s;
+  quantity vgsr across igsr through g to g2;
+  quantity vgs across igs through g2 to s;
+  constant vth : real := 0.5;
+  constant hfe : real := 8.85e-03;
+--  quantity flag : real := 1.0; 
+--    quantity vgs : real;
+--  signal vgs_sig,vds_sig : real := 0.0;
+
+begin
+  ------ Setting initial conditions
+--  init : break vds => 1.0;
+
+  opn : vdsg == 1.0* idsgi ; -- almost 
+  d12_res : vdsr == idsr * 1.0e-3;
+  g12res : vgsr == igsr * 1.0;
+  g_oup : vgs == igs * 1.0;
+  
+--  flag == 1.0;
+ 
+---- Current is in Micro Amps.
+
+  ------ Cut OffRegion
+    if((vgs >= 0.0) and (vgs <= vth)) use
+	gnc :    idsg == 0.0;
+
+  ------ Linear Region
+  elsif((vds <= (vgs-vth)) and (vds > 0.0)) use
+      	gnl :    idsg == hfe*(((vgs-vth)*vds) - (pow(vds,2.0)/2.0));
+ 
+  ------ Saturation Region
+  elsif((vds > (vgs-vth)) and (vgs > vth)) use
+      gns2 : idsg == (hfe/2.0)*(pow((vgs-vth),2.0));
+
+  ------ Other conditions
+ -- elsif(vgs < 0.0 or vds <= 0.0) use
+  elsif(1.0 = 1.0) use
+      temp : idsg == 0.0;
+  end use;
+
+end architecture behav; --- of nmos;
+
+--------- Inverter Test Bench
+
+-------*****************************************************************
+--                   New Entity Begins : CMOS INVERTER
+-------*****************************************************************
+
+use work.electricalsystem.all;
+
+entity inverter is
+  port(inv_inp : in bit;
+       inv_op : out bit);
+end entity inverter;
+
+architecture behav of inverter is
+
+  terminal iin, iout, idd : electrical;
+  quantity vdd across idd to electrical'reference;
+  quantity vin across iin to electrical'reference;
+  quantity vout across irout through iout to electrical'reference;
+  
+  constant power : real := 5.0;
+
+  component nmos is
+    port (terminal g,s,d : electrical);
+  end component;
+  for all : nmos use entity work.nmos(behav);
+
+  component pmos is
+    port (terminal g,s,d : electrical);
+  end component;
+  for all : pmos use entity work.pmos(behav);
+
+  component a2d_comp is
+     generic(vlo : real := 0.0;
+             vhi : real := 10.0;
+	     ped : time := 1 ns);
+     port (signal input : in bit;
+	   terminal pos, neg : electrical); 
+  end component;
+  for all : a2d_comp use entity work.a2d1bit(behav);
+
+  component resistor_comp 
+    generic ( r : real := 1.0);
+    port ( terminal tr1, tr2 : electrical );
+  end component;
+  for all : resistor_comp use entity work.resistor(rbehavior);
+
+begin
+  
+  vdd == power;
+
+  sqr : a2d_comp  
+	generic map(0.0, 10.0,  500 ps)
+	port map(inv_inp, iin, electrical'reference);
+
+  nm : nmos port map(iin, electrical'reference, iout);
+  pm : pmos port map(iin, idd, iout);
+
+  res_out : resistor_comp 
+    generic map(5000000.0)
+    port map(iout,electrical'reference);
+
+  a2d: process 
+  begin
+    if(vout'above(0.003) = true) then
+      inv_op <= '1';
+    else
+      inv_op <= '0';
+    end if;
+  end process;
+
+end architecture behav; ---- of inverter 
+
+-------*****************************************************************
+--                   New Entity Begins : TESTBENCH
+-------*****************************************************************
+
+use std.textio.all;
+
+entity test_bench is
+end test_bench;
+
+architecture tb_arch of test_bench is
+
+component inverter_comp
+  port(inv_inp : in bit;
+       inv_op : out bit);
+end component;
+
+for all : inverter_comp use entity work.inverter(behav);
+
+signal ip, op : bit;
+
+begin
+
+  i1 : inverter_comp
+    port map(ip, op);
+
+  inputtestbench:PROCESS
+  begin
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    ip <= '0';
+    wait for 100 NS;
+    ip <= '1';
+    wait for 100 NS;
+    
+    END process;
+
+  testbench:PROCESS
+    VARIABLE outline : LINE;
+    VARIABLE Headline   : string(1 TO 54) :=
+      "time inv_input inv_output";
+    VARIABLE   seperator    : string(1 TO 1) := " ";
+    VARIABLE   flag     : bit := '0';
+    FILE outfile: text OPEN WRITE_MODE IS "Output.out";
+  BEGIN
+    IF (flag = '0') THEN
+      flag := '1';
+      WRITE(outline,Headline);
+      WRITELINE(outfile,outline);
+    ELSE
+      WRITE(outline, now);
+      WRITE(outline,seperator);
+      WRITE(outline,ip);
+      WRITE(outline,seperator);
+      WRITE(outline,op);
+      WRITELINE(outfile,outline);
+    END IF;
+    WAIT ON ip, op;
+  END PROCESS;
+
+end;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_1.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_1.out
new file mode 100644
index 0000000..58c2c98
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_1.out
@@ -0,0 +1,6 @@
+time  ytestbenchwork_Drlc_Dbehavior_state::locateSi
+300 NS 1 
+600 NS 0 
+900 NS 1 
+1200 NS 0 
+1500 NS 1 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_2.out b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_2.out
new file mode 100644
index 0000000..2968583
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/iofiles/mixed_2.out
@@ -0,0 +1,8 @@
+time  y xtestbenchwork_Drlc_Dbehavior_state::
+30 NS 1 0 
+50 NS 1 1 
+60 NS 0 1 
+90 NS 1 1 
+100 NS 1 0 
+120 NS 0 0 
+150 NS 1 1 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams
new file mode 100644
index 0000000..37cd128
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_1.ams
@@ -0,0 +1,105 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: mixed_1.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+--This model basically consists of an analog and a single digital process 
+--and this tests the simulators capability of synchronization between the 
+--analog and the digital model
+--Partha
+ 
+   PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+USE std.textio.ALL;
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+
+   terminal n1, n2, n3 : electrical;
+
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2 to n3;
+   quantity vr3 across ir3 through n3;
+   quantity vs across n1;
+   constant r1 : REAL := 10.0;
+   constant r2 : REAL := 20.0;
+   constant r3 : REAL := 50.0;
+   signal y:bit := '0';
+
+BEGIN 
+
+  process(y)
+  begin
+  y <= not(y) after 300 ns;
+  end process;
+
+testbench:PROCESS(y)
+    VARIABLE outline : LINE;
+    VARIABLE Headline   : string(1 TO 52) :=
+      "time  y";
+    VARIABLE   seperator    : string(1 TO 1) := " ";
+    VARIABLE   flag     : bit := '0';
+    FILE outfile: text OPEN WRITE_MODE IS "mixed_1.out";
+  BEGIN
+    IF (flag = '0') THEN
+      flag := '1';
+      WRITE(outline,Headline);
+      WRITELINE(outfile,outline);
+    ELSE
+      WRITE(outline, now);
+      WRITE(outline,seperator);  
+      WRITE(outline, y);
+      WRITE(outline, seperator);
+      WRITELINE(outfile,outline);
+    END IF;
+  END PROCESS;
+
+res1 : vr1 == ir1 * r1;
+res2 : vr2 == ir2 * r2;
+res3 : vr3 == ir3 * r3;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+ 
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams
new file mode 100644
index 0000000..c780057
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/mixed_tests/mixed_2.ams
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: mixed_2.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+USE std.textio.ALL;
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   terminal n1, n2, n3 : electrical;
+
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2 to n3;
+   quantity vr3 across ir3 through n3;
+   quantity vs across n1;
+   constant r1 : REAL := 10.0;
+   constant r2 : REAL := 20.0;
+   constant r3 : REAL := 50.0;
+   signal y,x:bit := '0';
+
+BEGIN 
+
+  process(y)
+  begin
+  y <= not(y) after 30 ns;
+  end process;
+
+  process(x)
+  begin
+  x <= not(x) after 50 ns;
+  end process;
+
+testbench:PROCESS(y,x)
+    VARIABLE outline : LINE;
+    VARIABLE Headline   : string(1 TO 52) :=
+      "time  y x";
+    VARIABLE   seperator    : string(1 TO 1) := " ";
+    VARIABLE   flag     : bit := '0';
+    FILE outfile: text OPEN WRITE_MODE IS "mixed_2.out";
+  BEGIN
+    IF (flag = '0') THEN
+      flag := '1';
+      WRITE(outline,Headline);
+      WRITELINE(outfile,outline);
+    ELSE
+      WRITE(outline, now);
+      WRITE(outline,seperator);  
+      WRITE(outline, y);
+      WRITE(outline, seperator);
+      WRITE(outline, x);
+      WRITE(outline, seperator);
+      WRITELINE(outfile,outline);
+    END IF;
+  END PROCESS;
+                
+res1 : vr1 == ir1 * r1;
+res2 : vr2 == ir2 * r2;
+res3 : vr3 == ir3 * r3;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test100.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test100.ams
new file mode 100644
index 0000000..a3d35b4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test100.ams
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test100.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test100.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation 
+--of the simple simultaneous equation statement.it checks 
+--nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2;
+quantity V3 across I3 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*100.0;
+e2:     V2 == I2*10.0;
+e3:     V3 == I3*10.0;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test101.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test101.ams
new file mode 100644
index 0000000..64a81a4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test101.ams
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test101.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test101.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this test checks teh correctness of the 'integ implementation.
+-- it finds the integral of teh source voltage.
+-- the input is a sine wave.
+---------------------------------------------------------------------
+PACKAGE electricalSystem IS
+
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+end entity test;
+
+architecture atest of test is
+
+  quantity vs : real;
+  quantity vout: real;
+
+begin
+
+  vs== 5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) *
+                 1.0e-15);
+  vout == vs'integ;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test102.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test102.ams
new file mode 100644
index 0000000..430b9b4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test102.ams
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test102.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test102.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the Q'integ usage on the RHS of
+-- the simple simultaneous eqn.
+--------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity tank is
+end tank;
+
+architecture atank of tank is
+
+  terminal t1,t2 : electrical;
+
+  constant r: real :=10.00;
+  constant c: real:=0.00000003;
+
+  quantity vin across t1 to electrical'reference;
+  quantity vr across ir through t1 to t2;
+  quantity vc across ic through t2 to electrical'reference;
+  quantity q : real;
+
+begin
+        vr == ir*r;
+	q==c*vc;
+	ic==q'integ;	
+        vin ==  5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) *
+                1.0e-15);
+end atank;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test103.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test103.ams
new file mode 100644
index 0000000..880ea33
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test103.ams
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test103.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test103.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the simple simultaneous eqn.
+-- implementation. This is also a test for the lexical analysis.
+--------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+end entity;
+
+architecture atest of test is
+
+  terminal T1,T2,T3,T4,T5:electrical;
+  quantity v1 across i1 through T1 to T2;
+  quantity v2 across i2 through T2 to T4;
+  quantity v3 across i3 through T4 to T3;
+  quantity v4 across i4 through T2 to T5;
+  quantity v5 across i5 through T5 to T3;
+  quantity v6 across i6 through T2 to T3;
+  quantity vS across T1 to electrical'reference;
+
+begin
+
+e1:	v1==i1*1.0;
+e2:	v2==i2*1.0;
+e3:	v3==i3*1.0;
+e4:	v4==i4*1.0;
+e5:	v5==i5*1.0;
+e6: 	v6==i6*1.0;
+es:	vS==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test104.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test104.ams
new file mode 100644
index 0000000..d23ea03
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test104.ams
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test104.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test104.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this is a test that checks for the correct implementation of if use 
+--end use. The condition is checked by comparing the quantity against a 
+--known constant value.
+-----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+	generic (vmax :real:=10.0);
+	port(terminal T1:electrical);
+end entity;
+
+architecture atest of test is
+
+quantity vin across T1;
+constant a:real:=1.0;
+constant b:real:=2.0;
+quantity vin1:real;
+quantity vin2:real;
+
+begin
+
+vin == vmax/a;
+
+if (vin==10.0) use
+e1:	vin1==vmax*b;
+else
+e2:	vin2==vmax;
+end use;
+
+
+--if(vin<vmax) use
+--e3:	vin==vmax/b;
+--else
+--e4:	vin==vmax;
+--end use;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test105.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test105.ams
new file mode 100644
index 0000000..d146c52
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test105.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test105.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test105.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of quantity as a port declaration.
+-- the circuit is a simple RC network with vout acting as thge output port.
+-- a sine input is applied to the network.
+-------------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+    FUNCTION COS(X : real) RETURN real;
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+  port(quantity vout:out real);
+end entity;
+
+architecture atest of test is 
+  terminal T1,T2:electrical;
+  quantity VR across IR through T1 to T2;
+  constant R:real:=100.0;
+  constant C:real:=1.0e-9;
+  quantity vout across T2;
+  quantity vin across T1;
+begin
+  vsource: vin==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+  vres: IR== VR/R;
+  cap: vout==C*IR'integ;
+
+end atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test106.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test106.ams
new file mode 100644
index 0000000..c887f76
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test106.ams
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test106.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test106.ams
+-- Author(s)     : Geeta Balarkishnan (gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation 
+--of the simple simultaneous equation statement.it checks 
+--nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+end entity;
+
+architecture atest of test is
+  terminal T1,T2, T3, T4,T5,T6:electrical;
+  quantity VRgen across IRgen  through T1 to T2;
+  quantity VLgen across ILgen through T2 to T3;
+  quantity VRin across IRin through T3; 
+  quantity VR1 across IR1 through T4 to T5;
+  quantity VR1A across IR1A through T4 to T6;
+  quantity VC1A across IC1A through T6 to T5;
+  quantity VC1 across IC1 through T5;
+  quantity VS across T1;
+  constant C1: real:=3.5e-3;
+  constant C1A: real:=0.3e-3;
+begin
+
+  e1:     VRgen == IRgen*10.0;
+  e2:     VLgen == 0.5*ILgen'dot;
+  e3:     VRin == IRin*500.0;
+  e4:	VR1 == IR1*1.0;
+  e5:	VR1A == IR1A*0.2;
+  e6:	IC1 == C1 * VC1'dot;
+  e7:	IC1A == C1A*VC1A'dot;
+
+  esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test107.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test107.ams
new file mode 100644
index 0000000..03d2eaa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test107.ams
@@ -0,0 +1,152 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test107.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test107.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correct impelmentation of the port terminal
+-- decl. signal decl. of type real, type array decl. 
+-- the test performs a 4 bit digital to analog conversion.
+----------------------------------------------------------------------
+
+PACKAGE electricalsystem IS
+  NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+END electricalsystem;
+
+USE work.electricalsystem.all;
+ENTITY dac is
+  port(inputvector : in bit_vector(3 downto 0); --inputvector is an array of 16 bits
+       terminal T1, T2: electrical);	--terminal declarations
+END dac;
+
+ARCHITECTURE behavior OF dac IS
+
+  type temp_array is array(0 to 3) of integer; -- temp to store the array values
+  quantity vout across T1 to T2;	--output of the dac
+  
+  signal vout_sig, vcopy : real;	
+BEGIN
+
+  dac_process: PROCESS(inputvector) 
+    variable a : temp_array := (0,0,0,0);
+    variable tmp : real;
+    
+  BEGIN
+    for index in 3 downto 0 loop
+      if inputvector(index) = '0' then
+	a(index) := 0;			--bit to integer conversion done here
+      else a(index) := 1; 
+      end if;
+    end loop;
+
+    tmp := real(a(3)*8) + real(a(2)*4) + real(a(1)*2 + a(0)); --find the corresponding value of the binary 
+    vout_sig <= tmp;		
+
+  END PROCESS dac_process;
+
+  -- digital to analog conversion is done here
+  vout == vcopy;
+
+  convert: process(vout_sig)
+  begin
+    vcopy <= TRANSPORT vout_sig;
+  end process;
+
+END behavior;
+use work.electricalsystem.all;
+ENTITY tb_dac is
+end tb_dac;
+
+architecture stimuli of tb_dac is
+  signal myinputvector : bit_vector(3 downto 0);
+  terminal tout : electrical;
+  component dac port( inputvector : in bit_vector(3 downto 0);
+                      terminal T1, T2: electrical);
+  end component;
+  for all: dac use entity work.dac(behavior);
+  
+BEGIN
+  
+  unit:dac port map (myinputvector, tout, electrical'reference);
+
+  stimuli_process: process
+  BEGIN
+    
+    myinputvector <= "0000";
+    wait for 10 ns;
+
+   myinputvector <= "0001";
+    wait for 10 ns;
+
+  myinputvector <= "0010";
+    wait for 10 ns;
+
+    myinputvector <= "0100";
+    wait for 10 ns;
+
+    myinputvector <= "1000";
+    wait for 10 ns;
+
+    myinputvector <= "1100";
+    wait for 10 ns;
+
+    myinputvector <= "1110";    
+    wait for 10 ns;
+
+    myinputvector <= "1101"; 
+    wait for 10 ns;
+
+    myinputvector <= "1111"; 
+    wait for 10 ns;
+    myinputvector <= "0000";
+    wait for 10 ns;
+  
+    myinputvector <= "1100";
+    wait for 10 ns;
+    
+    myinputvector <= "1010";
+    wait for 10 ns;
+  
+    wait;
+  end process;
+end stimuli;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test108.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test108.ams
new file mode 100644
index 0000000..d8eb059
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test108.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test108.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test100.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+end entity;
+
+architecture atest of test is
+  terminal t1, t2: electrical;
+  quantity vd across id through T1; -- to T2;
+  quantity charge :real;
+  constant vt:real:=0.02;
+begin
+
+  p1: procedural is
+    begin
+	vd:=1.0*id;
+  end procedural;
+
+end architecture;
+
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test109.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test109.ams
new file mode 100644
index 0000000..3424a2d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test109.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test109.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test109.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of the procedural statements.
+-- multiple terms on the RHS
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+end entity;
+
+architecture atest of test is
+  terminal t1,t2: electrical;
+  quantity vd across id through t1 to t2;
+  quantity charge:real;
+  constant vt:real:=0.0258;
+  constant x:real:=1.0;
+  quantity ic:real;
+
+begin
+  p1: procedural 
+  begin
+    id:=0.1*(exp((vd-1.0*id)/vt)-1.0);
+    charge := x*id;
+    ic:= charge'dot;
+  end procedural;
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test110.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test110.ams
new file mode 100644
index 0000000..359bf84
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test110.ams
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test110.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- an example of a model having both a signal assignment statement
+-- as well as a simple simultaneous statement.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+ENTITY test IS
+END test;
+
+ARCHITECTURE behavior OF test IS
+    CONSTANT r1 : real := 100.0;        -- value of R1
+    terminal t1 : electrical;
+  QUANTITY vIn ACROSS t1;
+  QUANTITY vR ACROSS iR THROUGH t1 ;
+  signal y:bit:='0';
+BEGIN
+
+process(y)
+begin
+  y <= not(y) after 1000 ns;
+ 
+end process;
+
+ testbench:PROCESS
+    BEGIN
+        WAIT ON y;
+    END PROCESS;
+  res_stmt1: vR == iR * r1 ;
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test111.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test111.ams
new file mode 100644
index 0000000..118ec31
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test111.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test111.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : model.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the Q'Tolerance.
+-- the test checks for the simpel diode implementation
+-- wherein the charge is evaluated wrt a relative tolerance value
+----------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+  generic(a:real:=1.0e-10; b:real:=0.0);
+  port (terminal t1: electrical);
+end entity;
+
+architecture atest of test is
+  quantity vd tolerance "reltol=1.0e-2" across id through t1;
+  quantity charge: real;
+  quantity ic : real;
+  constant rd: real:=1.0;
+begin
+  e1:	id== a*(sin((vd-id*rd)/0.5)-1.0);
+  e2:	charge== b*id;
+  e3:	ic==charge'dot;
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test112.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test112.ams
new file mode 100644
index 0000000..b50437f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test112.ams
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test112.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : model.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the subtype declarations for the
+-- through and across quantities.
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is
+
+subtype voltage is real;
+subtype current is real;
+nature electrical is voltage across current through ground reference;
+
+end entity;
+
+architecture atest of test is
+
+constant R1: real :=10.0;
+constant R2: real :=5.0;
+constant R3: real :=1.0;
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2 to electrical'reference;
+quantity V3 across I3 through T2 to electrical'reference;
+quantity VS across T1 to electrical'reference;
+
+begin
+
+e1:     V1 == I1*R1;
+e2:     V2 == I2*R2;
+e3:     V3 == I3*R3;
+    
+esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+    
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test113.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test113.ams
new file mode 100644
index 0000000..81e546e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test113.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test113.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test113.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the Q'Tolerance for across qnty
+-- and for the real quantity.The test checks for the simpel diode 
+-- implementation wherein the charge is evaluated wrt a relative 
+-- tolerance value
+-- the test doesn't seem to take a tolerance associated with a
+-- free quantity. we need to check on this!! (LRM : 4.3.1 spec 
+-- followed.
+----------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+  generic(a:real:=1.0e-10; b:real:=0.0);
+  port (terminal t1: electrical);
+end entity;
+
+architecture atest of test is
+  quantity vd across id through t1; -- to electrical'reference;
+  quantity charge:real tolerance "reltol=1.0e-2";
+  --quantity ic : real;
+  constant rd: real:=1.0;
+begin
+  e1:     id== a*(sin((vd-id*rd)/0.5)-1.0);
+  e2:     charge== b*id; 
+  --e3:     ic==charge'dot;
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test114.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test114.ams
new file mode 100644
index 0000000..1471d82
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test114.ams
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test114.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : model.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the two currents associated 
+-- as through between same terminals.for eg: consider 2 resistors in
+-- parallel.. here vd is same and id and ic are the currents.
+-- the test checks for the simpel diode implementation
+-- wherein the charge is evaluated wrt a relative tolerance value
+----------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+  generic(a:real:=1.0e-10; b:real:=0.0);
+  port (terminal t1: electrical);
+end entity;
+
+architecture atest of test is
+  quantity vd across id, ic through t1;
+  quantity charge: real;
+  --quantity ic : real;
+  constant rd: real:=1.0; 
+begin
+  e1:     id== ((vd-id*rd)/0.5);
+  e2:     charge== b*id;
+  e3:     ic==charge'dot;
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test115.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test115.ams
new file mode 100644
index 0000000..e71523f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test115.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test115.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test115.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of the interface declaration:
+-- quantity : in| out. 
+-- ref LRM 4.3.2
+---------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    subtype voltage is real;
+    subtype current is real;
+    NATURE electrical is voltage across current THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+    port(quantity vout:out electrical);
+end entity test;
+
+architecture atest of test is
+  terminal t1,t2: electrical;
+
+  quantity vin across iin through t1;
+  quantity vr across ir through t1 to t2;
+  quantity vout across t1 to t2;
+
+begin
+
+  e1: vin==  5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15);
+  e2: vr==ir*1.0;
+  e3: vout== vr;
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test116.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test116.ams
new file mode 100644
index 0000000..87032a9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test116.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test116.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test116.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of the interface declaration:
+-- quantity : in| out. A simple R circuit with an ac voltage source 
+-- is used.  
+-- ref LRM 4.3.2
+---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical is real across real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+  port(quantity vout:out voltage);
+end entity test;
+
+architecture atest of test is
+  terminal t1,t2: electrical;
+
+  quantity vin across iin through t1;
+  quantity vr across ir through t1 to t2;
+  quantity vout across t1 to t2;
+
+begin
+
+  e1: vin==  5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15);
+  e2: vr==ir*1.0;
+  e3: vout== vr;
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test117.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test117.ams
new file mode 100644
index 0000000..f9d9933
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test117.ams
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test117.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test117.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the subtype usage and also
+-- checks for the tolerance aspect associated with the subtype.
+----------------------------------------------------------------------
+
+Package electricalsystem is
+ FUNCTION SIN(X : real) RETURN real;
+
+subtype voltage is real tolerance "default_voltage=1.0e-3";
+subtype current is real; -- tolerance "default_current= 1.0e-4";
+subtype resistance is real;
+
+nature electrical is voltage across current through ground reference;
+end package electricalsystem;
+
+use work.electricalsystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+--subtype voltage is real tolerance "default_voltage=1.0e-3";
+--subtype current is real; -- tolerance "default_current= 1.0e-4";
+subtype resistance is real;
+
+nature electrical is voltage across current through;
+
+terminal t1, t2: electrical;
+quantity vr tolerance across ir through t1 to t2;
+quantity vs across t1;
+--quantity vout across t2;
+
+begin
+e1: vs==5.0 *sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+e2: vr==ir*1.0;
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test118.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test118.ams
new file mode 100644
index 0000000..a9831e1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test118.ams
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test118.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test118.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+
+-- the test checks for the correctness of the implemenatation of the case
+-- statement. 
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+end entity test;
+
+architecture atest of test is
+  terminal t1:electrical;
+  signal ison: boolean;
+  quantity vr across ir through t1;
+  constant vt:real:=0.0258;
+begin
+
+process 
+	variable off : boolean:=true;
+begin
+	ison <= not off;
+	case off is
+	   when true=> 
+		ison<= not off;
+	   when false=>
+		ison<=off;
+	end case;
+end process;
+
+source: vr==10.0 * sin(2.0 *(22.0/7.0)*100000.0*real(time'pos(now)) * 1.0e-15);
+if ison use
+	ir== 5.0; --*(exp(vr/vt)-1.0);
+else	
+	ir==0.0;
+end use;
+
+break on ison;
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test119.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test119.ams
new file mode 100644
index 0000000..973d0f2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test119.ams
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test119.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test1.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- This is the simple resistor model that sets the foundation on which 
+-- we build SIERRA, the VHDL AMS simulator. The circuit consists of 3 
+-- resistors connected to a voltage source.
+--   T1        R1    T2
+--     o-----/\/\----o--------       
+--     |             |    |          
+--    ( )            >    >   
+--     |Vs = 5sinwt  >R2  >R3           
+--     |             >    >
+--     |_____________|____|___
+--                   |gnd
+--                 ----
+--------------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+end entity;
+
+architecture atest of test is
+
+  constant R1: real :=10.0;
+  constant R2: real :=5.0;
+  constant R3: real :=1.0;
+  terminal T1,T2:electrical;
+  quantity V1 across I1 through T1 to T2;
+  quantity V2 across I2 through T2 to electrical'reference;
+  quantity V3 across I3 through T2 to electrical'reference;
+  quantity VS across T1 to electrical'reference;
+
+begin
+
+  e1:	V1 == I1*R1;
+  e2:	V2 == I2*R2;
+  e3:	V3 == I3*R3;
+
+  esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test121.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test121.ams
new file mode 100644
index 0000000..8166369
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test121.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test121.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test3.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this is to check the quantity: q'dot in the lhs and rhs of the 
+-- simultaneous statements
+---------------------------------------------------------------------
+PACKAGE electricalSystem is 
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+end entity;
+
+architecture atest of test is
+	quantity x11: real;
+	constant x1:real:=2.0;
+	constant x2:real:=1.0;
+	constant m1 : real:=1.0;
+	quantity f : real;	
+	quantity dx1 : real;
+ 
+begin
+e1:	f == 10.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+e2:	x11 == f*(x1-x2)/m1;
+e3:	dx1 == f'dot;
+
+--	x1'dot == f*(x1-x2)/m1;
+--	x2'dot == f*(x1-x2)/m2;
+--	xs == (m1*x1+m2*x2)/(m1+m2);
+--	m3 == m1*x1'dot+ m2*x2'dot;
+end atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test122.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test122.ams
new file mode 100644
index 0000000..c3f9c09
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test122.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test122.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test122.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- to check for the correct implementation of the simple simultaneous
+-- statements 
+-------------------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity chk is
+
+  generic(i:real:=1.0e-9); 
+  port(terminal t1, t2: electrical);
+
+end chk;
+
+architecture achk of chk is
+	quantity vd across id through t1 to t2;
+	quantity q: real;
+	quantity ic:real;
+	constant vth : real:= 0.025;
+begin
+
+e1:	id == i*(exp(vd/vth)-1.0);
+e2:	q == id*0.25;
+e3:	ic == q'dot;
+
+end achk;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test123.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test123.ams
new file mode 100644
index 0000000..6e26997
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test123.ams
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test123.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test113.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- to check the correct implementation of the simultaneous if statement
+-- break and 'above is also used. it checks for the eqns v'=g*v**2 for 
+-- +g and -g.
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+--    alias ground is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+entity test is
+end entity test;
+
+architecture atest of test is
+
+  quantity v : real;
+  quantity s: real;
+  constant g : real :=9.81;
+  constant r : real:=1.02;
+
+begin
+
+break v=>0.0, s=>100.0;
+
+break v=>-v when not s'above(0.0);
+
+s'dot==v;
+
+if v>0.0 use
+   v'dot == -g+v*v*r;
+else
+   v'dot == -g-v*v*r;
+end use;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test124.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test124.ams
new file mode 100644
index 0000000..ee84d21
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test124.ams
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test124.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test124.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+
+--this test is to chk the support of ALIAS, NATURE in the PACKAGE declaration
+--the test also chks the corrct use of quantity and terminal declarations.
+--------------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+--entity declaration
+
+use work.electricalsystem.all;
+ENTITY Rckt IS
+
+END Rckt;
+
+--architecture declaration
+
+ARCHITECTURE aRckt  OF Rckt IS
+
+
+   terminal T1, T2 : electrical;
+
+   quantity VR across IR through T1 to T2;
+   quantity VR1 across IR1 through T2;
+   quantity VS across T1;
+   constant R : REAL := 10.00;
+
+BEGIN
+
+eqn1    : VR == IR * R;
+e2:	  VR1 == IR1 * R;
+eqn2    : VS == 5.0;
+
+end arckt;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test125.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test125.ams
new file mode 100644
index 0000000..6b82f12
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test125.ams
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test125.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- this model tests for the correst implementation of the 'above 
+-- statement.
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+    alias ground is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity product is 
+generic(bound:real:=1.0);
+port(
+     quantity out1:real);
+end product;
+
+architecture pro of product is
+constant in1:real:=10.0;
+constant in2:real:=1.0;
+signal outofbound:out boolean;
+
+begin
+	outofbound<=true;
+	out1== in1*in2;
+	outofbound<=out1'above(1.0);
+
+end pro;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test126.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test126.ams
new file mode 100644
index 0000000..2c8c320
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test126.ams
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test126.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test8.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the corretness of the 'left 'right 'high 'low 
+-- 'ascending 'length declarations.
+----------------------------------------------------------------------
+entity test is
+port (y: out bit);
+end test;
+
+architecture atest of test is
+type value is range 10 downto 0;
+signal a: bit;
+begin
+
+	y<=a;
+e1:process 	
+begin
+if (value'left=10)then
+		a <='1';
+	else
+		a <='0';
+	end if;
+	assert (value'right=0)
+	    report "pass 'right check"
+	assert(value'high=10)
+	    report "pass 'high check"
+	assert (value'low=0)
+	    report "pass 'low check"
+	assert (value'ascending=false)
+	    report "pass 'ascending check"
+	assert (value'length=11)
+	    report "pass 'length check"
+end process;
+end atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test127.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test127.ams
new file mode 100644
index 0000000..09f2cce
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test127.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test127.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test9.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+
+--this checks the step limit specification incorporated.
+--this gives atleast 20 analog solution points if the 
+--" STEP LIMIT' is implemented correctly.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity source is
+generic (Amplitude :real:=1.0;
+	 frequency:real:=1.0);
+port (quantity sine:out real);
+end entity source;
+
+architecture asource of source is
+  limit sine:real with 0.05/frequency;
+
+begin
+e1:	sine== Amplitude*sin(2*3.14159*frequency*real(time'pos(now))*1.0e-12);
+
+end architecture asource;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test128.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test128.ams
new file mode 100644
index 0000000..760a2c4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test128.ams
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test128.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test104.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this is a test that checks for the correct implementation of if use 
+-- end use. The condition is checked by comparing the quantity against a
+-- known constant value.
+-----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+end entity;
+
+architecture atest of test is
+  terminal T1, T2:electrical;
+
+  quantity vin across T1 to electrical'reference;
+  constant a:real:=1.0;
+  constant b:real:=2.0;
+
+  quantity vin1 across iin1 through T1 to T2;
+  quantity vin2 across iin2 through T2 to electrical'reference;
+begin
+
+eq1: vin==5.0* sin(2.0 * 3.141592 *1000.0 * real(time'pos(now))*1.0e-12);
+eq2: vin1== iin1*a;
+eq3: vin2== iin2*b;
+if (vin1>5.0) and (vin1<10.0) use
+e1:	vin1==vin/a;
+elsif (vin2<5.0) use
+e2:	vin2==vin/b;
+else 
+e3: 	vin1==vin;
+end use;
+end atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test129.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test129.ams
new file mode 100644
index 0000000..052c634
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test129.ams
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test129.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+     NATURE electrical IS real ACROSS real THROUGH ground reference; 
+    FUNCTION POW(X,Y: real) RETURN real;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    type electrical_vector is array(0 to 3) of electrical;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is
+generic( a: real);
+port( terminal ip: electrical_vector;
+      terminal op:electrical);
+end entity;
+
+architecture atest of test is
+type electrical_vector is array(0 to 3) of electrical;
+--variable i: real:=0.0;
+variable a:real:=5.0;
+variable output:real:=0.0;
+quantity vin across ip to electrical'reference;
+quantity vout across iout through ip to op;
+begin
+
+   for i in 0 to 3 loop
+	output:=output + vin(i)*a;
+   end loop;
+vout:=output;
+
+end architecture atest;
+-- test bench needs to be corrected
+
+use work.electricalSystem.all;
+entity tb is
+end entity;
+
+architecture atb of tb is
+signal myvector : electrical_vector(0 to 3);
+terminal tip : electrical_vector;
+terminal top:electrical;
+component test 
+	port(terminal ip, op: electrical);
+end component;
+for all: test use entity work.test(atest);
+begin
+
+unit: test port map(tip, top, electrical'reference);
+
+a_process: process
+begin
+
+myvector == 1.0;
+wait for 10 ns;
+myvector  == 2.0;
+wait for 10 ns;
+myvector  == 2.0;
+wait for 10 ns;
+myvector  ==1.0;
+wait for 10 ns;
+
+wait;
+
+end process;
+
+end atb;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test130.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test130.ams
new file mode 100644
index 0000000..7ac92b5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test130.ams
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test130.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package electricalSystem is
+     NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION POW(X,Y: real) RETURN real;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    type electrical_vector is array(0 to 3) of electrical;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is
+port( terminal ip: electrical_vector;
+      terminal op:electrical);
+end entity;
+
+architecture atest of test is
+type electrical_vector is array(0 to 3) of electrical;
+type t_a is array(0 to 3) of real;
+variable i: real:=0.0;
+variable output:real:=0.0;
+quantity vin across ip to electrical'reference;
+quantity vout across iout through ip to op;
+begin
+t1: process
+   variable a: t_a :=(1.0, 1.2, 1.5, 2.0);
+   for i in 0 to 3 loop
+	output:=output + vin(i)*a(i);
+   end loop;
+vout:=output;
+end architecture atest;
+
+use work.electricalSystem.all;
+entity tb is
+end entity;
+
+architecture atb of tb is
+signal myvector : electrical_vector(0 to 3);
+terminal tip : electrical_vector;
+terminal top:electrical;
+signal myconst : real_vector(0 to 3);
+component test 
+	port(terminal ip, op: electrical);
+end component;
+for all: test use entity work.test(atest);
+begin
+
+unit: test port map(tip, top, electrical'reference);
+
+a_process: process
+begin
+
+myvector == 1.0;
+wait for 10 ns;
+myvector == 2.0;
+wait for 10 ns;
+myvector == 2.0;
+wait for 10 ns;
+myvector==1.0;
+wait for 10 ns;
+wait;
+
+end process;
+
+end atb;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test133.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test133.ams
new file mode 100644
index 0000000..7a0e28b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test133.ams
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test133.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test133.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this test checks the correctness of the break statement for a 
+-- quantity port declaration.
+-- LRM ref: 8.14
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+        subtype voltage is real;
+
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is 
+    generic (m: real := 1.0); 
+    port (quantity x: out voltage);  
+end entity test; 
+
+architecture atest of test is 
+--quantity x: real;
+quantity q: real;
+begin 
+    break x => 0.0, x'dot => 0.1; 
+    e1: q== x'dot;
+    x'dot'dot == -1.0*( m*(x*x - 1.0)* x'dot); 
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test134.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test134.ams
new file mode 100644
index 0000000..de8f2e1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test134.ams
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test134.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test151.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this is a test to check the corretness of the implemntation of the break
+-- statement and also the use of quantity port of type voltage.
+-- this is a vco model which first sets the initial condition
+-- using a break statement. Then again, a break statement is applied to keep 
+-- the phase within 0-2pi. Thr output voltage eqn is obtained as vout and the 
+-- phase eqn as phase'dot.
+-- LRM ref: 8.14, 4.3.2.
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    SUBTYPE voltage is real;
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity vco is 
+  generic( 
+          fc: real := 1.0e6;    -- VCO frequency at Vc 
+          df: real := 0.5e6;  -- [Hz/V], frequency characteristic slope 
+          Vc: voltage := 0.0 --  centre frequency input voltage 
+         ); 
+  port( quantity Vin: in voltage; 
+        terminal OutTerminal: electrical); 
+end entity VCO; 
+
+architecture avco of vco is 
+    constant TwoPi: real := 6.283118530718; -- 2pi 
+
+    quantity Phase : real; 
+
+    -- define a branch for the output voltage source 
+
+    quantity Vout across Iout through OutTerminal to electrical'reference; 
+
+begin 
+   -- use break to set the phase initial condition 
+   break Phase => 0.0; 
+
+   -- another break statement keeps the phase within 0.. 2pi 
+   break Phase => Phase mod TwoPi on Phase'above(TwoPi); 
+
+   -- phase equation 
+   Phase'dot == TwoPi*realmax(0.5E6, fc+(Vin-Vc)*df); 
+
+     -- output voltage source equation 
+     Vout == 2.5*(1.0+sin(Phase)); 
+
+end architecture avco; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test135.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test135.ams
new file mode 100644
index 0000000..d247089
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test135.ams
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test135.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground refernce;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+USE use.electricalSystem.all;
+ENTITY vpwl IS
+    GENERIC (v0 : real := 0.0);
+    PORT (SIGNAL slope : in real;
+          TERMINAL p, m : electrical);
+END ENTITY vpwl;
+
+ARCHITECTURE one OF vpwl IS
+    QUANTITY v  ACROSS i THROUGH p TO m;
+BEGIN
+    v==v0;
+    BREAK WHEN slope'event;
+    v'dot == slope;
+END ARCHITECTURE one;
+
+entity tb is
+end entity;
+architecture atb of tb is
+signal myinput: real;
+
+begin
+	myinput<='1';
+ARCHITECTURE two OF vpwl IS
+    QUANTITY v ACROSS i THROUGH p TO m;
+    SIGNAL startv : voltage := v0;
+BEGIN
+    BREAK WHEN slope'event;
+    startv <= v WHEN slope'event;
+    v == startv + slope'delayed * startv'last_event;
+END ARCHITECTURE two;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test136.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test136.ams
new file mode 100644
index 0000000..09357f0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test136.ams
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test136.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test136.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A resistor bridge network...
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+end entity;
+
+architecture mesh of test is
+
+terminal t1, t2, t4 : electrical;
+quantity v1 across i1 through t1 to t2;
+quantity v2 across i2 through t2;
+quantity v3 across i3 through t4;
+quantity v4 across i4 through t1 to t4;
+quantity v5 across i5 through t1;
+quantity vs across t1;
+
+begin
+
+e1:	v1== i1*10.0;
+e2:	v2== i2*10.0;
+e3:	v3== i3*10.0;
+e4:	v4== i4*10.0;
+e5:	v5== i5*20.0;
+
+esource: vs== 10.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-15);
+
+end architecture mesh;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test137.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test137.ams
new file mode 100644
index 0000000..43c4d6d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test137.ams
@@ -0,0 +1,136 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test137.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------------
+-- File          : test137.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+-----------------------------------------------------------------------------
+-- Description :
+-----------------------------------------------------------------------------
+-- the test cheks the correctness of the electrical_vector.array of terminals
+-- also the use of real vectors.. array of real values.
+-- the circuit is a weighted summer the output is available at the 
+-- ooutput terminal o.
+-- LRM  4.3.2
+-------------------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+    TYPE real_vector is array(0 to 3) of real;
+    TYPE electrical_vector is array(0 to 3) of electrical;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+generic (beta,gamma : real_vector);
+port(terminal inp, inm: electrical_vector;
+     terminal o: electrical);
+end entity;
+architecture atest of test is
+--TYPE real_vector is array(0 to 3) of real;
+--TYPE electrical_vector is array(0 to 3) of electrical;
+quantity vp across ip through inp to electrical'reference;
+quantity vm across inm to electrical'reference;
+quantity vo across io through o to electrical'reference;
+variable bvs, gvs : real:=0.0;
+function "*" (a:real_vector; 
+	      b: electrical_vector'across) 
+return real is
+
+variable result : real:=0.0;
+begin
+
+for i in (0 to 3) loop
+	result:= result+ a(i)*b(i);
+end loop;
+return result;
+end function "*";
+begin
+vo== beta*vp - gamma*vm;
+end architecture atest;
+
+use work.electricalSystem.all;
+
+entity tb is
+end entity;
+
+architecture atb of tb is
+signal myvec1,myvec2:real_vector(0 to 3);
+signal myinput1, myinput2: electrical_vector(0 to 3);
+terminal tinp, tinm: electrical_vector;
+terminal to: electrical;
+
+component test
+        port(terminal inp, inm: electrical_vector;
+	     terminal o: electrical);
+end component test;
+for all: test use entity work.test(atest);
+begin
+unit: test port map(tinp,tinm, to, electrical'reference);
+a_process: process
+begin
+   
+myvec1 == 1.0;
+myinput1 == 1.0;
+myvec2 == 2.0;
+myinput2 == 2.0;
+wait for 10 ns;
+myvec1 == 1.0;
+myinput1 == 1.0;
+myvec2 == 2.0;
+myinput2 == 2.0;
+wait for 10 ns;
+myvec1 == 1.0;
+myinput1 == 2.0;
+myvec2 == 2.0;
+myinput2 == 1.0;
+wait for 10 ns;
+myvec1 == 1.0;
+myinput1 == 2.0;
+myvec2 == 2.0;
+myinput2 == 1.0;
+wait for 10 ns;
+
+end process;
+
+end atb;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test138.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test138.ams
new file mode 100644
index 0000000..4c11b3a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test138.ams
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test138.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+package mosdata is 
+-- 
+ type mosmodel is 
+  record 
+     vt0    : real; 
+     kp     : real; 
+  end record mosmodel;
+
+  nature electrical is real across real through ground reference;
+   FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+end package mosdata;
+
+use work.mosdata.all;
+
+entity test is
+generic (
+	  model: mosmodel:=(
+			    vt0 => 0.7,
+			    kp => 1.0);
+				
+	 constant a: real:=1.0
+	);
+end entity;
+
+architecture atest of test is
+terminal t1, t2: electrical;
+quantity vr across ir through t1 to t2;
+quantity vs across t1;
+
+begin
+e1: vs== 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+e2: vr== ir* model.kp*a  + model.vt0;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test139.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test139.ams
new file mode 100644
index 0000000..16e5a9e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test139.ams
@@ -0,0 +1,122 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test139.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+-----------------------------------------------------------------------
+-- File          : test139.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+-----------------------------------------------------------------------
+-- Description :
+-----------------------------------------------------------------------
+-- this test checks the correctness of the record declaration as a type
+-- it also checks for the usage of the record element declarations.
+-- the assert statement is also checked.
+-- the record is declared within a package
+-- the test also checks the correctness of the function impelmentation.
+-- the function accepts the record parameters and returns the result of 
+-- type real.
+-----------------------------------------------------------------------
+PACKAGE electricalsystem IS
+ 
+    SUBTYPE voltage IS real;
+    SUBTYPE current IS real;
+ 
+    NATURE electrical IS
+        voltage ACROSS
+        current THROUGH ground reference;
+ 
+END PACKAGE electricalsystem;
+ 
+PACKAGE types IS
+ 
+    TYPE cmodel IS RECORD
+        cj     : real;    
+        cjsw   : real;    
+        defw   : real;    
+        narrow : real;    
+    END RECORD;
+ 
+END PACKAGE types;
+ 
+USE work.electricalsystem.all;
+USE work.types.all;
+ 
+ENTITY test IS
+    GENERIC (cnom : real := 0.0;
+             model : cmodel := (0.0, 0.0, 1.0e-6, 0.0);
+             l : real := 0.0;
+             w : real := 0.0;
+             ic : real := 0.0 );
+    PORT (TERMINAL t1,t2 : electrical);
+END ENTITY test;
+ 
+ARCHITECTURE atest OF test IS
+    	FUNCTION c_init (	cnom : real;
+             		model : cmodel;
+             		l, w : real)
+        RETURN real IS
+        VARIABLE ceff : real;  -- effective capacitance value
+        VARIABLE weff : real;  -- effective channel width
+ 	BEGIN
+ 
+        IF cnom /= 0.0 THEN
+            ASSERT (model.cj = 0.0 AND model.cjsw = 0.0)
+                    REPORT "Both cnom and model specified";
+            ceff := cnom;
+        ELSE
+            ASSERT (l > 0.0)
+                    REPORT "Channel length not specified";
+            IF w = 0.0 THEN
+                weff := model.defw;
+            ELSE
+                weff := w;
+            END IF;
+            ASSERT (weff > 0.0) 
+                    REPORT "Channel width not specified";
+            ceff := model.cj*(l-model.narrow)*(weff-model.narrow) +
+                        model.cjsw*(l+weff-2.0*model.narrow);
+        END IF;
+        RETURN (ceff);
+    	END FUNCTION c_init;
+ 
+    	CONSTANT ceff : real := c_init(cnom, model, l, w);
+    	QUANTITY v ACROSS i THROUGH t1 TO t2;
+BEGIN
+    i == ceff * v'dot;
+END ARCHITECTURE atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test140.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test140.ams
new file mode 100644
index 0000000..f43142b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test140.ams
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test140.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test140.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of the quantity, terminal, nature 
+-- and package declarations. the terminals are assigned as terminals.
+-- a simple V-R circuit is considered.
+-----------------------------------------------------------------------
+
+PACKAGE electricalsystem IS
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+--    SUBTYPE voltage IS real;
+--    SUBTYPE current IS real;
+
+NATURE electrical IS real ACROSS real THROUGH ground reference;
+
+END PACKAGE electricalsystem;
+use work.electricalsystem.all;
+
+ENTITY test IS
+    PORT (TERMINAL p: electrical);
+END ENTITY test;
+
+ARCHITECTURE sine OF test IS
+        constant ampl: REAL:=5.0;
+	constant freq: real:=10000.0;
+        QUANTITY v ACROSS i THROUGH p;
+       quantity vr across ir through p;
+BEGIN
+e1:    v == ampl * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12);
+e2:    vr== ir*10.0;
+END ARCHITECTURE sine;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test141.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test141.ams
new file mode 100644
index 0000000..5303951
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test141.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test141.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test141.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+-- this is the behavioral model of a simple error amplifier.
+-- the entity consists of a quatity port and the architecture consists 
+-- of a simple simultaneos statement
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+--    subtype voltage is real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity ErrorAmplifier is 
+  generic( Gain : REAL := 10.0 -- amplifier gain 
+         ); 
+  port( terminal P_T,N_T: electrical; -- analog input pins 
+        quantity Vout : out real      -- analog output 
+      ); 
+end entity ErrorAmplifier; 
+
+architecture Behavior of ErrorAmplifier is 
+
+quantity DeltaV across P_T through N_T; -- differential input voltage 
+begin 
+e1:  DeltaV== 1.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+e2:  Vout == Gain*DeltaV; 
+
+end architecture Behavior; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test143.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test143.ams
new file mode 100644
index 0000000..f83c97a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test143.ams
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test143.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-------------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+-------------------------------------------------------------------------
+-- File          : test143.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+------------------------------------------------------------------------
+-- Description :
+------------------------------------------------------------------------
+-- the test checks for the correctness of the concurrent signal
+-- assignment.  it accepts sine wave as input and the architecture has a
+-- concurrent signal assignment statement that assigns either a 1 or 0
+-- depending on the condition. 
+------------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+    subtype voltage is real;
+    subtype current is real;
+
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity AnaComparator is
+  generic( Vth: voltage := 0.0   -- [V] comparator threshold level
+         );
+  port( terminal P_T: electrical; 
+        signal Out_T: out BIT             
+      );
+end entity AnaComparator;
+
+architecture Behavior of AnaComparator is
+ quantity DeltaV across P_T to electrical'reference; -- differential input voltage
+
+begin
+
+e1: DeltaV== 5.0*sin(2.0*3.14159*10000.0*real(time'pos(now))*1.0e-15);
+
+  out_T <=        '1' when     DeltaV'above(0.0)  -- trigger event when V+>V-
+             else '0' when not DeltaV'above(0.0); -- trigger event when V+<=Vt-
+
+end architecture Behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test144.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test144.ams
new file mode 100644
index 0000000..7fe6c01
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test144.ams
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test144.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-------------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+-------------------------------------------------------------------------
+-- File          : test144.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------------
+-- Description :
+-----------------------------------------------------------------------------
+-- the test checks for the correctness of the ATTRIBUTE declaration
+-- also checks function, real_vector and quantity vector declarations
+-- the integer range<> is used instead of specifying the actaul range 
+-- or size of the matrix.
+-- 1 D and 2 D matrix operations are verified.
+-- the test performs the matrix dot product caluculation and also 
+-- product of a 2 D matrix with a column vector.
+----------------------------------------------------------------------
+
+PACKAGE electrical_system IS
+ 
+    -- declare attribute to hold units
+    ATTRIBUTE unit : string; 
+    NATURE electrical IS
+        real ACROSS
+        real THROUGH;
+    NATURE electrical_vector IS ARRAY(integer range<>)  OF electrical;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+    NATURE real_vector IS ARRAY(integer range<>) of real;
+END PACKAGE electrical_system;
+
+PACKAGE real_aux IS
+    TYPE real_vector IS ARRAY(integer range<>) OF real;
+    TYPE real_matrix IS ARRAY(integer range<>, integer range<>) OF real;
+
+    -- scalar := (row_)vector * (column_)vector
+
+    FUNCTION "*"(v1, v2 : real_vector) RETURN real IS
+        VARIABLE result : real := 0.0;
+    BEGIN
+        ASSERT v1'range = v2'range; -- to ensure correct dot product evaluation
+        FOR i IN v1'range LOOP
+            result := result + v1(i) * v2(i);
+        END LOOP;
+        RETURN result;
+    END FUNCTION "*";
+ 
+    -- (column_)vector := matrix * (column_)vector
+
+    FUNCTION "*"(m : real_matrix; v : real_vector) RETURN real_vector IS
+        VARIABLE result : real_vector(m'range(1));
+    BEGIN
+        ASSERT m'range(2) = v'range;
+        FOR i IN result'range LOOP
+            result(i) = 0.0;
+            FOR j IN v'range LOOP
+                result(i) := result(i) + m(i,j) * v(j);
+            END LOOP;
+        END LOOP;
+        RETURN result;
+    END FUNCTION "*";
+END PACKAGE real_aux;
+ 
+use work.electrical_system.all;
+-- ideal multiplier
+ 
+ENTITY mult IS
+    PORT (TERMINAL in1, in2, output, ref : electrical);
+END ENTITY mult;
+ 
+ARCHITECTURE ideal OF mult IS
+    QUANTITY vout ACROSS iout THROUGH output TO ref;
+    QUANTITY vin1 ACROSS in1 TO ref;
+    QUANTITY vin2 ACROSS in2 TO ref;
+BEGIN
+    vout == vin1 * vin2;
+END ARCHITECTURE ideal;
+
+USE work.electrical_system.all;
+USE work.real_aux.all;
+                
+ENTITY xfrm IS     
+    GENERIC (ml : real_matrix);            -- self/mutual inductances
+    PORT (TERMINAL p, m : electrical_vector);
+END ENTITY xfrm;
+                    
+ARCHITECTURE one OF xfrm IS
+    QUANTITY v ACROSS i THROUGH p TO m;    -- arrays!
+BEGIN
+    v == ml*real_vector(i'dot);
+END ARCHITECTURE one;   
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test145.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test145.ams
new file mode 100644
index 0000000..c27c40f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test145.ams
@@ -0,0 +1,359 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test145.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test145.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : June 2001
+----------------------------------------------------------------------
+-- Description :
+-- this is a mos model. It tests for the correctness of the procedural
+-- statement.
+--
+-- the model accepts the mos data as generic constants. The terminals
+-- are defined as of nature electrical.
+-- it also tests the alias declaration for real'low.
+-- Charges associated with the 4 terminals are declared as quantities.
+-- The voltage associated with each of them is also defined.
+-- a signal is used to drive i.e to carry out a generic initialization.
+-- The various mos equations are evaluated depending on the conditions.
+-- The equations for charges and currents are evaluated.
+----------------------------------------------------------------------
+
+package mosdata is 
+  NATURE electrical is real across real through;
+  FUNCTION SIN(X : real) RETURN real;
+  FUNCTION EXP(X : real) RETURN real;
+  FUNCTION SQRT(X : real) RETURN real;
+  FUNCTION POW(X,Y : real) RETURN real;
+  alias undefined is real'low; 
+  constant Temperature: real:=27.0;
+  constant eps0 : real :=8.85418e-12; 
+  constant Ni : real :=1.45e16; 
+  constant Boltzmann : real :=1.380662e-23; 
+  constant echarge: real :=1.6021892e-19; 
+  constant epsSiO2 : real :=3.9*eps0; 
+  constant epsSi : real :=11.7*eps0; 
+  constant kTQ : real :=Boltzmann*temperature/echarge; 
+  constant pi: real := 3.14159;  
+end package mosdata; 
+
+use work.mosdata.all; 
+entity mos is 
+
+  generic( 
+    width  : real:=1.0E-4; 
+    length : real:=1.0E-4;  
+    channel: real :=1.0;
+    kp :real:= 2.0E-5; 
+    gamma :undefined; 
+    phi   :undefined; 
+    tox   :real:= 1.0E-7;
+    nsub  :real:= 0.0;
+    nss   :real:=0.0; 
+    nfs   :real:= 0.0; 
+    tpg   :real:= 1.0; 
+    xj    :real:=0.0; 
+    ld    :real:= 0.0; 
+    u0    :real:= 600.0; 
+    vmax  :real:=0.0;
+    xqc   :real:= 1.0; 
+    kf    :real:=0.0; 
+    af    :real:=1.0; 
+    fc    :real:=0.5; 
+    delta :real:=0.0; 
+    theta :real:=0.0; 
+    eta   :real:=0.0;
+    Sigma :real:=0.0;
+    kappa :real:=0.2 );
+
+  port ( terminal  drain,  gate,  source,  bulk  : electrical); 
+
+end entity mos; 
+
+architecture amos of mos is 
+  quantity Qc, Qb, Qg: real;
+  quantity Qcq, Qbq, Qgq : real; -- channel, bulk and gate charges 
+  quantity Vdsq across drain to source; 
+  quantity Vgsq across gate to source; 
+  quantity Vbsq across bulk to source; 
+  quantity Idq through drain; 
+  quantity Igq through gate; 
+  quantity Isq through source; 
+  quantity Ibq through bulk; 
+
+  signal Initialized: boolean; -- use a signal as generic initialisation 
+
+begin 
+  MOSeqns: procedural is 
+     variable 
+	cox,vt,beta,sigma,nsub,Phi,Gamma,nss,ngate,A,B,C,D,Vfb,fshort, 
+        wp,wc,sqwpxj,vbulk,delv,vth,Vgstos, Vgst, 
+	Ueff,Tau,Vsat,Vpp,fdrain, 
+        stfct,leff,xd,qnfscox,fn,dcrit,deltal,It,Ids,R,Vds,Vgs,Vbs, 
+        forward ,egfet,fermig, mobdeg: real;
+  begin -- procedural statements 
+
+    if not Initialized then 
+      if tox<=0.0 then 
+        cox:=epsSiO2/1.0e-7; 
+      else 
+        cox:=epsSiO2/tox; 
+      end if; 
+
+      if kp = 0.0 then 
+        beta:=cox*u0; 
+      else 
+        beta:=kp; 
+      end if; 
+
+     nsub := nsub * 1.0e6;  -- scale nsub to SI units 
+  
+      if (phi = undefined) then 
+        if (nsub > 0.0) then
+		if (0.1<2.0*KTQ*(nsub/Ni)) then 
+          	Phi:=(2.0*kTQ*(nsub/Ni));
+		else
+		Phi:=0.1;
+		end if; 
+        else 
+          Phi:=0.6; 
+        end if; 
+      else 
+        Phi:=phi; 
+      end if;
+  
+      if (gamma = undefined) then 
+        if (nsub > 0.0) then 
+          Gamma:=sqrt(2.0*epsSi*echarge*nsub)/cox; 
+        else 
+          Gamma:=0.0; 
+        end if; 
+      else 
+        Gamma:=gamma; 
+      end if;
+
+      nss:=nss*1.0e4;              -- Scale to SI 
+      ngate:=gamma*1.0e4;           -- Scale to SI 
+
+      leff:=length-2.0*ld; 
+      if leff>0.0 then 
+        Sigma:= eta * 8.15e-22/(cox*leff*leff*leff); 
+      else 
+        Sigma:=0.0; 
+      end if; 
+
+      if nsub>0.0 then -- N.B. nsub was scaled, above. 
+        xd:=sqrt(2.0*epsSi/(echarge*nsub)); 
+      else 
+        xd:=0.0; 
+      end if; 
+
+      if (nfs>0.0) and(cox>0.0) then 
+        qnfscox:=echarge*nfs/cox; 
+      else 
+        qnfscox:=0.0; 
+      end if; 
+
+      if cox>0.0 then 
+        fn:=delta*pi*epsSi*0.5/(cox*width); 
+      else 
+        fn:=delta*pi*epsSi*0.5*tox/epsSiO2; 
+      end if; 
+
+      --Scale beta and convert cox from Fm^-2 to F 
+      beta:=beta*width/leff; 
+      cox:=cox*width*leff; 
+
+      Initialized <= true; 
+    end if; -- not initialized 
+
+    Vds:=channel*Vdsq; 
+    if Vds>=0.0 then 
+        Vgs:=channel* Vgsq; 
+        Vbs:=channel* Vbsq; 
+        forward:=1.0; 
+    else 
+        Vds:=-Vds; 
+        Vgs:=channel* Vgsq; 
+        Vbs:=channel* Vbsq; 
+        forward:=-1.0; 
+    end if; 
+
+    if Vbs<=0.0 then 
+        A:=Phi-Vbs; 
+        D:=sqrt(A); 
+    else 
+        D:=2.0*sqrt(Phi)*Phi/(2.0*Phi+Vbs); 
+        A:=D*D; 
+    end if; 
+
+    Vfb:=Vt-Gamma*sqrt(Phi)-Sigma*Vds; 
+    if (xd=0.0) OR (xj=0.0) then 
+        fshort:=1.0; 
+    else 
+        wp:=xd*D; 
+        wc:=0.0631353*xj+0.8013292*wp-0.01110777*wp*wp/xj; 
+        sqwpxj:=sqrt(1.0-(wp*wp/((wp+xj)*(wp+xj)))); 
+        fshort:=1.0-((ld+wc)*sqwpxj-ld)/leff; 
+    end if; 
+
+    vbulk:=Gamma*fshort*D+fn*A; 
+    if nfs=0.0 then 
+        delv:=0.0; 
+    else 
+        delv:=kTQ*(1.0+qnfscox+vbulk*0.5/A); 
+    end if; 
+
+    vth:=Vfb+vbulk; 
+    Vgstos:=Vgs-Vfb;
+
+    if (vgs-vth > delv) then  
+        Vgst:=Vgs-vth;
+    else
+        Vgst:= delv;
+    end if;
+ 
+    if (vgs>=vth) or (delv/=0.0) then 
+
+      if (Vbs<=0.0) or (Phi /= 0.0) then 
+          B:=0.5*Gamma/D+fn; 
+      else 
+          B:=fn; 
+      end if; 
+
+      mobdeg:=1.0/(1.0+theta*Vgst); 
+   
+      if (vmax /=0.0) then 
+         Ueff:=u0*mobdeg; 
+          Tau:=Ueff/Leff*vmax; 
+      else 
+          Tau:=0.0; 
+      end if; 
+
+      Vsat:=Vgst/(1.0+B); 
+      Vsat:=Vsat*(1.0-0.5*Tau*Vsat); -- not quite the same as SPICE 
+      if (vds<Vsat) then
+	Vpp:=vds;
+      else
+	Vpp:= Vsat;
+      end if;
+
+      fdrain:=1.0/(1.0+Tau*Vpp); 
+      if (Vgs<vth+delv) and (nfs>0.0) then 
+        stfct:=exp((Vgs-vth-delv)/delv); 
+      else 
+          stfct:=1.0; 
+      end if; 
+
+      if Vds>=Vsat then 
+        if (kappa>0.0) and (xd>0.0) then 
+
+          if vmax=0.0 then 
+              deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)); 
+          else 
+              dcrit:=(xd*xd*vmax*0.5)/(Ueff*(1.0-fdrain)); 
+              
+	      deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)+dcrit*dcrit)-dcrit; 
+          end if; 
+
+          if deltal<=0.5*Leff then 
+              C:=Leff/(Leff-deltal); 
+          else 
+              C:=4.0*deltal/Leff; 
+          end if; 
+
+        else 
+            C:=1.0; 
+        end if; 
+
+      else 
+          C:=1.0; 
+      end if; 
+
+      It:=Vgst-Vpp*(1.0+B)*0.5; 
+        Beta:=Beta*mobdeg; 
+        Ids:=Beta*Vpp*It*C*fdrain*stfct; 
+    else 
+        -- Cutoff 
+        Ids:=0.0; 
+    end if; -- vgs >= vth 
+
+    if Cox /= 0.0 then 
+        --Charges 
+      if Vgs<=vth then 
+        if Gamma /= 0.0 then 
+          if Vgstos < -A then 
+                Qg:=Cox*(Vgstos+A); -- Accumulation 
+          else 
+                Qg:=0.5*Gamma*Cox*(sqrt(4.0*(Vgstos+A)+Gamma*Gamma-Gamma)); 
+          end if ; -- vgstos <-A 
+        else-- Gamma = 0.0 
+            Qg:=0.0; 
+        end if; -- gamma /= 0 
+          Qb:=-Qg; 
+          Qc:=0.0; 
+      else 
+          -- depletion mode: 
+          R:=(1.0+B)*Vpp*Vpp/(12.0*It); 
+          Qg:=Cox*(Vgstos-Vpp*0.5+R); 
+          Qc:=-Cox*(Vgst+(1.0+B)*(R-Vpp*0.5)); 
+          Qb:=-(Qc+Qg); 
+      end if;
+
+    else 
+        Qg:=0.0; 
+        Qc:=0.0; 
+        Qb:=0.0; 
+    end if; -- cox /= 0 
+
+    -- equations for charges (in a procedural we have assignments to 
+    --quantitites): 
+      Qcq := Qc; 
+      Qgq := Qg; 
+      Qbq := Qb; 
+
+    -- equations for currents: 
+      Idq := channel*forward*Ids+channel*xqc*Qc'dot; 
+      Igq := channel*Qg'dot; 
+      Ibq := channel*Qb'dot; 
+      Isq := -Idq - Igq - Ibq; 
+
+  end procedural; 
+end architecture amos; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test146.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test146.ams
new file mode 100644
index 0000000..0331906
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test146.ams
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test146.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test100.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- half wave Rectifier model ...
+-- the test is done for checking the correct implementation
+--of the simultaneous if statement.it checks
+--nature declaration, terminal and quantity declarations.
+
+
+----------------------------------------------------------------------
+--     T1   diode D  T2    
+--     o-----|>|-----o-------o       The circuit comprises:
+--     |             |               i)  A diode .
+--    ( )            >R=100ohms      ii) A sinusoidal voltage source.
+--     |Vs = 5sinwt  >               iii)A resistor R.
+--     |             >
+--     |_____________|_______o
+--                   |gnd
+--                 -----
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+----------------------------------------------------------------------
+
+USE work.electricalSystem.all;
+
+ENTITY hwr IS
+END hwr;
+
+ARCHITECTURE ahwr OF hwr IS
+
+    terminal T1, T2 : electrical;
+    quantity VDiode across IDiode through T1 to T2;
+    quantity V2 across I2 through T2 to electrical'reference;
+    quantity VS across T1 to electrical'reference;
+
+    CONSTANT saturation_current : real := 0.0000000000001;
+    CONSTANT Vt : real := 0.025;
+        
+    CONSTANT BV : real := 100.0;
+    CONSTANT neg_sat : real := -saturation_current;
+    
+BEGIN  
+
+      --diode equations
+      if( vDiode >= (-1.0 * Vt)) USE
+        eq1: iDiode == saturation_current;
+
+      ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use
+        eq2:  iDiode == neg_sat;
+
+      ELSE
+        eq3: iDiode == neg_sat;
+      END USE ;
+                                                       
+      eqn2: v2 == 100.0 * i2;
+    
+      eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 *
+                            real(time'pos(now)) * 1.0e-15 );
+    
+END ahwr ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test147.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test147.ams
new file mode 100644
index 0000000..59574f4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test147.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test147.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test147.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this checks for the corect implementation of the 'dot'dot  and negation
+-- operator implementation for simple simulataeous statements
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2: real;
+quantity V3: real;
+quantity VS across Isource through T1;
+
+begin
+
+e1:     I1 == V1'dot*1e-15;
+e2:     V2 == VS'dot'dot;
+e3:     V3 == -VS'dot;
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test148.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test148.ams
new file mode 100644
index 0000000..4445de2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test148.ams
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test148.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test148.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of the quantity, terminal, nature
+-- and package declarations. the terminals are assigned as terminals.
+-- a simple V-R circuit is considered.
+-----------------------------------------------------------------------
+
+PACKAGE electricalsystem IS
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+--    SUBTYPE voltage IS real;
+--    SUBTYPE current IS real;
+
+NATURE electrical IS real ACROSS real THROUGH ground reference;
+
+END PACKAGE electricalsystem;
+use work.electricalsystem.all;
+
+ENTITY test IS
+    generic(ampl:real:=5.0);
+    PORT (TERMINAL p: electrical);
+END ENTITY test;
+
+ARCHITECTURE sine OF test IS
+	constant freq: real:=10000.0;
+        QUANTITY v ACROSS i THROUGH p;
+       quantity vr across ir through p;
+BEGIN
+e1:    v == ampl * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12);
+e2:    vr== ir*10.0;
+END ARCHITECTURE sine;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test149.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test149.ams
new file mode 100644
index 0000000..befafb7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test149.ams
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test149.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test149.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation of the 
+-- componet declaration. The model consists of 2 resistor models which are 
+-- instantiated.
+
+package electricalSystem is
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity test1 is
+	port (terminal P, N : electrical );
+end entity test1;
+
+architecture behav of test1 is 
+   quantity Vt1 across It1 through P to N;
+begin
+	res1 : Vt1 == It1 * 10.0 ;
+end architecture behav;
+
+use work.electricalsystem.all;
+entity test2 is
+	port (terminal P, N : electrical );
+end test2;
+
+architecture behav of test2 is 
+   quantity Vt2 across It2 through P to N;
+begin
+	res1 : Vt2 == It2 * 100.0 ;
+end behav;
+
+
+use work.electricalsystem.all;
+
+entity resistor_ckt is 
+end resistor_ckt;
+
+architecture ares_ckt of resistor_ckt is
+
+	component test1 is 
+           port (terminal P, N : electrical );
+	end component;
+
+	component test2 is 
+           port (terminal P, N : electrical );
+	end component;
+
+        for all : test1 use entity work.test1(behav);  
+        for all : test2 use entity work.test2(behav);  
+
+	terminal a,b,c,t1,t2 : electrical;
+	quantity vout across iout through t2 to electrical'reference;
+	quantity vs across a to electrical'reference;
+
+begin
+	e1 : test1 port map (P => a, N => b);
+	e2 : test2 port map (P => b, N => c);
+ 	e3 : vout == iout * 1200.0;
+	e4 : test1 port map (P => c, N => t1);
+	e5 : test1 port map (P => t1, N => t2);
+    source : vs  == 5.0 * sin(2.0 * 3.1415 * 10000.0* real(time'pos(now)) * 1.0e-12);
+end architecture ares_ckt;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test150.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test150.ams
new file mode 100644
index 0000000..d159873
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test150.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test150.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test150.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple RC  model...     
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement with 'dot expression on
+-- RHS.  it checks nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;   
+
+architecture atest of test is
+terminal T1,T2:electrical;   
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*10.0; 
+e2:     I2 == 1.0e-12*V2'dot;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test151.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test151.ams
new file mode 100644
index 0000000..647d8eb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test151.ams
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test151.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test151.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...2 resistors in parallel
+-- the test is done for checking the correct implementation 
+-- of the simple simultaneous equation statement with multiple expressions
+-- RHS.  It checks nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1:electrical;
+quantity V1 across I1 through T1 to electrical'reference;
+quantity V2 across I2 through T1 to electrical'reference;
+quantity VS across T1;
+quantity I12 : real;
+begin
+
+e1:     V1 == I1*10.0;
+e2:     V2 == I2*10.0;
+e3:     I12 == I1+I2;  
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test152.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test152.ams
new file mode 100644
index 0000000..a3a5fd9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test152.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test152.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test150.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple RC  model...     
+-- the test is done for checking the correct implementation of the simple
+-- simultaneous equation statement with 'dot expression on RHS.  it checks
+-- nature declaration, terminal and quantity declarations.  
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;   
+
+architecture atest of test is
+terminal T1,T2:electrical;   
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*10.0; 
+e2:     I2 == V2'dot*1.0e-12;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test153.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test153.ams
new file mode 100644
index 0000000..091e91f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test153.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test153.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test100.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple model which has a voltage source. 
+-- The output voltage Vout is dependent on the value of vS at that point
+-- of time. If the voltage is below Vref, the output is a 1 else output is
+-- a 0.  the test is done for checking the correct implementation of the
+-- simple simultaneous if statement.it checks nature declaration, terminal
+-- and quantity declarations. 
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VS across T1;
+quantity Vout: real;
+constant Vref:real:=5.0;
+begin
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+if (VS <= Vref) use
+e1:	Vout == 1.0;
+else 
+e2:	Vout == 0.0;
+end use;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test154.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test154.ams
new file mode 100644
index 0000000..eb87aee
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test154.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test154.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test154.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple model which has a voltage source. 
+-- The output voltage Vout is dependent on the value of VS wrt Vref 
+-- If the voltage is below Vref, the output is a 0 else output is a 1.
+-- the test is done for checking the correct implementation
+--of the simple simultaneous if statement.it checks
+--nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VS across T1;
+quantity Vout: real;
+constant Vref:real:=5.0;
+begin
+
+esource: VS == 5.0;
+
+if (VS<=Vref) use
+e1:	Vout == 1.0;
+else 
+e2:	Vout == 0.0;
+end use;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test155.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test155.ams
new file mode 100644
index 0000000..56e0adf
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test155.ams
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test155.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test155.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple model which has a voltage source. 
+-- The output voltage Vout is dependent on the value of VS wrt Vref
+-- If the voltage is above/below Vref, the output is a 0 else output is a 1.
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous if statement with multiple if conditions.it
+-- checks nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VS across T1;
+quantity Vout: real;
+constant Vref:real:=5.0;
+begin
+
+esource: VS == 5.0;
+
+if (VS<Vref) use
+e1:	Vout == 0.0;
+elsif (VS=Vref) use  
+e2:	Vout == 1.0;
+else 
+e3:	Vout == 0.0;
+end use;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test156.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test156.ams
new file mode 100644
index 0000000..8837429
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test156.ams
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test156.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- check the implemetatio of ports and generics.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity inv is
+  port (
+    x : in bit;
+    xout : out bit); 
+end inv;
+ 
+architecture inverter  of inv is
+begin 
+ 
+  xout <= not x after 100ns ;
+ 
+end inverter ;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity resistor is
+        generic ( res : real := 10.0 ) ;
+        port (terminal P, N : electrical );
+end resistor;
+ 
+architecture behav of resistor is
+   quantity VPTON across IPTON through P to N;
+begin
+        res1 : VPTON == IPTON * res ;
+end behav;
+
+use work.electricalSystem.all;
+
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+  component inv is
+  port (
+    x : in bit;
+    xout : out bit);
+   end component ;
+   for all : inv use entity work.inv(inverter) ;
+
+   component resistor is
+           generic ( res : real := 10.0 ) ;
+           port (terminal P, N : electrical );
+        end component;
+        for all : resistor use entity work.resistor(behav);
+ 
+  terminal n1,n2 : electrical;
+  QUANTITY vIn ACROSS iIn THROUGH n1 ;
+
+  signal y:bit:='0';
+
+BEGIN
+
+   D2 : inv  port map(x=>y, xout=>y);       
+
+ testbench:PROCESS
+    BEGIN
+        WAIT ON y;
+    END PROCESS;
+
+  R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); 
+  R2 : resistor port map (P => n2, N => ground); 
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test157.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test157.ams
new file mode 100644
index 0000000..d73dadb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test157.ams
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test157.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- check the implemetatio of ports and generics.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+--entity inv is
+--  port (
+--    x : in bit;
+--    xout : out bit); 
+--end inv;
+ 
+--architecture inverter  of inv is
+--begin 
+ 
+--  xout <= not x after 100ns ;
+ 
+--end inverter ;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity resistor is
+        generic ( res : real := 10.0 ) ;
+        port (terminal P, N : electrical );
+end resistor;
+ 
+architecture behav of resistor is
+   quantity VPTON across IPTON through P to N;
+begin
+        res1 : VPTON == IPTON * res ;
+end behav;
+
+use work.electricalSystem.all;
+
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+--  component inv is
+--  port (
+--    x : in bit;
+--    xout : out bit);
+--   end component ;
+--   for all : inv use entity work.inv(inverter) ;
+
+   component resistor is
+           generic ( res : real := 10.0 ) ;
+           port (terminal P, N : electrical );
+        end component;
+        for all : resistor use entity work.resistor(behav);
+ 
+  terminal n1,n2 : electrical;
+  QUANTITY vIn ACROSS iIn THROUGH n1 ;
+
+--  signal y:bit:='0';
+
+BEGIN
+
+--   D2 : inv  port map(x=>y, xout=>y);       
+
+-- testbench:PROCESS
+--   BEGIN
+--        WAIT ON y;
+--    END PROCESS;
+
+  R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); 
+  R2 : resistor port map (P => n2, N => ground); 
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test158.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test158.ams
new file mode 100644
index 0000000..0f80dc6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test158.ams
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test158.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test134.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : June 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this is a test to check the corretness of the implemntation of the break
+-- statement and also the use of quantity port of type voltage.
+-- this is a vco model which first sets the initial condition
+-- using a break statement. Then again, a break statement is applied to keep 
+-- the phase within 0-2pi. Thr output voltage eqn is obtained as vout and the 
+-- phase eqn as phase'dot.
+-- LRM ref: 8.14, 4.3.2.
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+   -- SUBTYPE voltage is real;
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity vco is 
+  generic( 
+          fc: real := 1.0e6;    -- VCO frequency at Vc 
+          df: real := 0.5e6;  -- [Hz/V], frequency characteristic slope 
+          Vc: voltage := 0.0 --  centre frequency input voltage 
+         ); 
+  port( quantity Vin: in real; 
+        terminal OutTerminal: electrical); 
+end entity VCO; 
+
+architecture avco of vco is 
+    constant TwoPi: real := 6.283118530718; -- 2pi 
+
+    quantity Phase : real; 
+
+    -- define a branch for the output voltage source 
+
+    quantity Vout across Iout through OutTerminal to electrical'reference; 
+
+begin 
+   -- use break to set the phase initial condition 
+   break Phase => 0.0; 
+
+   -- another break statement keeps the phase within 0.. 2pi 
+   break Phase => Phase mod TwoPi on Phase'above(TwoPi); 
+
+   -- phase equation 
+   Phase'dot == TwoPi*realmax(0.5E6, fc+(Vin-Vc)*df); 
+
+     -- output voltage source equation 
+     Vout == 2.5*(1.0+sin(Phase)); 
+
+end architecture avco; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test161.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test161.ams
new file mode 100644
index 0000000..f63c380
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test161.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test161.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test150.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple RC  model...     
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement with 'dot expression on
+-- RHS.  it checks nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;   
+
+architecture atest of test is
+terminal T1,T2:electrical;   
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*10.0; 
+e2:     V2 == I1'integ/1.0e-12;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test162.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test162.ams
new file mode 100644
index 0000000..dbc7b3b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test162.ams
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test162.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test147.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this checks for the corect implementation of the 'dot'dot  and negation
+-- operator implementation for simple simulataeous statements
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2: real;
+quantity i2 :real;
+quantity VS across Isource through T1;
+
+begin
+
+e1:     I1 == V1'dot*1.0e-15;
+e2:     V2 == V1'dot;
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test163.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test163.ams
new file mode 100644
index 0000000..3b26a8a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test163.ams
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test163.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test162.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple rc model...with 2 res in parallel connected thru a capacitor
+-- -------------||-----
+--           |        |
+--           | R      | R
+-- --------------------		
+-- the test is done for checking the correct implementation
+--of the simple simultaneous equation statement.it checks
+--nature declaration, terminal, 'dot and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VR1 across IR1 through T1;
+quantity VC across IC through T1 to T2;
+quantity VR2 across IR2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     VR1 == IR1*100.0;
+e2:     IC  == VC'dot *1.0e-12;
+e3:     VR2 == IR2*10.0;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test164.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test164.ams
new file mode 100644
index 0000000..17a0778
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test164.ams
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test164.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test164.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple rc model...with 2 res in parallel connected thru a capacitor
+-- -------------||-----
+--           |        |
+--           | R      | R
+-- --------------------		
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal, 'dot, 'integ and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VR1 across IR1 through T1;
+quantity VC across IC through T1 to T2;
+quantity VR2 across IR2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     VR1 == IR1*100.0;
+e2:     IC  == VC'dot *1.0e-12;
+e3:     VR2 == IR2*10.0;
+e4:     VC == IC'integ/1.0e15
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test165.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test165.ams
new file mode 100644
index 0000000..cf08509
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test165.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test165.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test164.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple rl model...
+-- -----^^^-------------
+--       R   |        >
+--           | L      > R
+-- --------------------		
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal, 'dot, and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VR1 across IR1 through T1 to T2;
+quantity VL across IL through T2;
+quantity VR2 across IR2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     VR1 == IR1*10.0;
+e2:     VL  == IL'dot *1.0;
+e3:     VR2 == IR2*10.0;
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test166.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test166.ams
new file mode 100644
index 0000000..92dc6af
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test166.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test166.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test166.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple rl model...
+-- -----^^^-------------
+--       R   |        >
+--           | L      > R
+-- --------------------		
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal, 'dot,'integ and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VR1 across IR1 through T1 to T2;
+quantity VL across IL through T2;
+quantity VR2 across IR2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     VR1 == IR1*10.0;
+e2:     VL  == IL'dot *1.0;
+e3:     VR2 == IR2*10.0;
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+e4:	IL== 1.0* VL'integ;
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test167.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test167.ams
new file mode 100644
index 0000000..35849f2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test167.ams
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test167.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test167.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- An RC model...
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal, 'dot, 'integ and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2, T3, T4:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2 to T3;
+quantity VC across IC through T3;
+quantity VC1 across IC1 through T2 to T4;
+quantity V3 across I3 through T4;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*1.0;
+e2:     V2 == I2*1.0;
+e3:     V3 == I3*10.0;
+e4:     IC == VC'dot*1.0e-12;
+e5:	IC1 == VC1'dot*1.0e-12;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test168.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test168.ams
new file mode 100644
index 0000000..c78d544
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test168.ams
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test168.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test168.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- An RC model...
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal, 'dot, 'integ and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2, T3, T4:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2 to T3;
+quantity VC across IC through T3;
+quantity VC1 across IC1 through T2 to T4;
+quantity V3 across I3 through T4;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*1.0;
+e2:     V2 == I2*1.0;
+e3:     V3 == I3*10.0;
+e4:     VC == IC'integ*1.0e12;
+e5:	VC1 == IC1'integ*1.0e12;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test169.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test169.ams
new file mode 100644
index 0000000..c0b15e1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test169.ams
@@ -0,0 +1,143 @@
+
+-- Copyright (C) 1999-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test169.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+--------------------------------------------------------------------
+--  Ebers-moll Model for a transistor                             --
+--  VHDL-AMS Implementation                                       --
+--  Developed at the Distributed Processing Lab at the University --
+--  of Cincinnati                                                 -- 
+--  by VishwaShanth Kasula on May 10, 1999                        --
+--------------------------------------------------------------------
+--  Circuit Topology                                              --
+--  BJT Ebers-Moll static model
+--  Testbench Ckt to evaluate the DC operatioing point of an npn BJT,
+--  Sedra smith page no. 152, fig 4.9
+--------------------------------------------------------------------
+
+-- Three regions are simulated
+-- Active region, vbb = 4.0 V
+-- Saturation region, vbb = 6.0 V
+-- Cutoff region, vbb = 0.0;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity bjt_npn is
+  generic(isat : real := 1.0e-16;         -- Saturation Current
+          bf   : real := 100.0;           -- Ideal maximus forward current
+          br   : real := 1.0;             -- ideal maximum reverse current
+          rb   : real := 1.0e-5;          -- Base resistance
+          rc   : real := 1.0e-5;          -- collector resistance
+          re   : real := 1.0e-5;          -- emmiter resistance
+          vaf  : real := 100.0);          -- Forward Early Voltage
+  port(terminal e,b,c : electrical);
+end bjt_npn;
+
+architecture structure of bjt_npn is
+  terminal b1, c1, e1 : electrical;
+  quantity vbo across ib through b to b1;
+  quantity vco across ic through c to c1;
+  quantity veo across ie through e to e1;
+  quantity vct across Ict through c1 to e1;--current source
+  quantity vbe across ibe through b1 to e1;
+  quantity vbc across ibc through b1 to c1;
+  quantity vce : real := 1.0;           -- used to calculate VCE
+  constant gmin : real := 1.0e-12;      -- condutsnce in parallel with every pn junction
+  constant vt : real := 0.02589; -- thermal voltage
+ 
+begin
+  brk : break vbe => 1.0, vbc => -1.0;
+
+  diodecond1 : if(vbe > -5.0*vt) use
+    diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf;
+  elsif (vbe <= -5.0*vt ) use
+    diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf;
+  end use;
+  diodecond2 : if(vbc > -5.0*vt) use
+    diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br;
+  elsif(vbc <= -5.0*vt) use
+    diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br;
+  end use;
+  bres : vbo == ib * 1.0e-6;
+  cres : vco == ic * 1.0e-6;
+  eres : veo == ie * 1.0e-6;
+  kcl_eqn : ie == -1.0*(ib + ic);
+  vcevolt : vce == vbe - vbc;
+  ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf));
+  
+end architecture structure;
+
+
+--*****************************************************
+--TEST BENCH
+use std.textio.all;
+use work.electricalsystem.all;
+
+entity bjt_testbench is
+end bjt_testbench;
+
+architecture structure of bjt_testbench is
+  terminal t1, t2, t3, t4 : electrical ;
+  component bjt_npn_comp
+    generic(isat : real := 1.0e-16;         -- Saturation Current
+            bf : real := 100.0;           -- Ideal maximus forward current
+            br : real := 1.0;             -- ideal maximum reverse current
+            rb : real := 1.0e-5;          -- Base resistance
+            rc : real := 1.0e-5;          -- collector resistance
+            re : real := 1.0e-5;          -- emmiter resistance
+            vaf : real := 100.0);         -- Forward Early Voltage
+    port(terminal e,b,c : electrical);	  
+  end component;
+  for all : bjt_npn_comp use entity work.bjt_npn(structure);
+  
+  quantity vcc across icc through t1 to electrical'reference;
+  quantity vrc across irc through t1 to t2;
+  quantity vbb across ibb through t3 to electrical'reference;
+  quantity vre across ire through t4 to electrical'reference;
+  
+begin
+   
+   bjt : bjt_npn_comp
+     generic map (isat => 1.8104e-15, vaf => 100.0)
+     port map(t4,t3,t2);
+   emres : vre == ire * 3.3e3;
+   ccurr : vcc == 10.0;
+   ecurr : vbb == 6.0;
+   cores : vrc == irc * 4.7e3;
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test170.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test170.ams
new file mode 100644
index 0000000..dff7515
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test170.ams
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test170.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test106.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation 
+-- of the simple simultaneous equation statement.it checks 
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2, T3, T4,T5,T6:electrical;
+quantity VRgen across IRgen  through T1 to T2;
+quantity VLgen across ILgen through T2 to T3;
+quantity VRin across IRin through T3; 
+quantity VR1 across IR1 through T4 to T5;
+quantity VR1A across IR1A through T4 to T6;
+quantity VC1A across IC1A through T6 to T5;
+quantity VC1 across IC1 through T5;
+quantity VS across T1;
+constant C1: real:=3.5e-3;
+constant C1A: real:=0.3e-3;
+begin
+
+e1:     VRgen == IRgen*10.0;
+e2:     VLgen == 0.5*ILgen'dot;
+e3:     VRin == IRin*500.0;
+e4:	VR1 == IR1*1.0;
+e5:	VR1A == IR1A*0.2;
+e6:	VC1 == C1 /IC1'integ;
+e7:	VC1A == C1A/IC1A'integ;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test171.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test171.ams
new file mode 100644
index 0000000..3d0dd76
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test171.ams
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test171.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test171.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation 
+-- of the simultaneous if equation statement.it checks 
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2, T3 :electrical;
+quantity VC1 across IC1 through T1 to T2;
+quantity VC2 across IC2 through T3;
+quantity VD1 across ID1 through T2;
+quantity VD2 across ID2 through T2 to T3;
+quantity VS across T1;
+constant BV: real:=100.0;
+constant satcur: real:=1.0e-12;
+constant negsatcur: real:= -1.0*satcur;
+constant VT: real:=0.025;
+constant C1: real:= 1.0e-12;
+constant C2: real:= 1.0e-12;
+begin
+
+e1:	IC1 == C1 * VC1'dot;
+e2:	IC2 == C2*VC2'dot;
+diode1: if (VD1>=(-3.0*VT)) use
+           ID1 == satcur*(exp(VD1/VT)-1.0);
+        elsif (VD1 < (-3.0*VT) and (VD1 >-BV)) use
+           ID1==negsatcur;
+        else
+           ID1 == negsatcur * (exp(-(BV+ VD1/VT)-1)+satcur);
+        end use;
+
+diode2: if (VD2>=(-3.0*VT)) use
+           ID2 == satcur*(exp(VD2/VT)-1.0);
+        elsif (VD2 < (-3.0*VT) and (VD2 >-BV)) use
+           ID2==negsatcur;
+        else
+           ID2 == negsatcur * (exp(-(BV+ VD2/VT)-1)+satcur);
+        end use;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test172.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test172.ams
new file mode 100644
index 0000000..123b9dd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test172.ams
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test172.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test172.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the simultaneous if equation statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+port (input: in bit;
+      output: out bit);
+end entity;
+
+architecture atest of test is
+terminal t1, t2: electrical;
+quantity v1 across i1 through t1 to t2;
+quantity v2 across t2;
+begin
+
+e1: v1== 1.0;
+e2: v2==0.0;
+
+	if (v1==1.0) use
+	  output <= '1';
+	else
+	  output <='0';
+	end use;
+
+	if (v2==2.0) use
+	   output <='0';
+	else
+	   output <='1';
+	end use;
+end architecture atest;
+use work.electricalSystem.all;
+--entity tb is 
+--port (tinput: in bit;
+--      toutput: out bit);
+--end entity;
+--architecture atb of tb is
+--terminal tt1, tt2: electrical;
+--quantity tv1 across ti1 through tt1 to tt2;
+--quantity tv2 across tt2;
+--begin
+
+--tv1==1.0;
+--tv2==0.0;
+
+--end architecture atb;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test173.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test173.ams
new file mode 100644
index 0000000..c43afe8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test173.ams
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test173.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test173.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the simultaneous if equation statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal t1, t2: electrical;
+quantity v1 across i1 through t1 to t2;
+quantity v2 across t2;
+
+begin
+e1: v1== 1.0;
+e2: v2==0.0;
+
+	if (v1==1.0) use
+	  output <= '1';
+	end use;
+
+	if (v2==2.0) use
+	   output <='1';
+	end use;
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test174.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test174.ams
new file mode 100644
index 0000000..4bf8c01
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test174.ams
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test174.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test174.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation
+-- of the simultaneous case statement.it checks
+-- nature declaration, terminal and quantity declarations
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference ;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+
+USE work.electricalSystem.all;
+
+ENTITY simcase IS
+END simcase;
+
+ARCHITECTURE asimcase OF simcase IS
+
+    terminal T1, T2 : electrical;
+
+    quantity v1 across i1 through T1 ;
+    quantity v2 across i2 through T1 to T2;
+    quantity v3 across i3 through T2 ;
+
+BEGIN  
+
+      eqn1 : v1 == 1.0;
+	     
+c1:	case (v1*2.0) use
+       
+            when (2.0) use 
+                       v2 == i2 * 100.0;
+                       v3 == i3 * 100.0;
+            when (6.0) use
+                       v2 == i2 * 200.0;
+                       v3 == i3 * 200.0;
+            when (10.0) use
+                       v2 == i2 * 300.0;
+                       v3 == i3 * 300.0;
+     end case c1; 
+
+END asimcase ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test175.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test175.ams
new file mode 100644
index 0000000..544527d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test175.ams
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test175.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test175.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+--of the simultaneous case statement.it checks
+--nature declaration, terminal and quantity declarations
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference ;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+USE work.electricalSystem.all;
+
+ENTITY simcase IS
+END simcase;
+
+ARCHITECTURE asimcase OF simcase IS
+
+    terminal T1, T2 : electrical;
+
+    quantity v1 across i1 through T1 ;
+    quantity v2 across i2 through T1 to T2;
+    quantity v3 across i3 through T2 ;
+
+BEGIN  
+
+      eqn1 : v1 == 1.0;
+      eqn2 : v2 == 2.0;	     
+c1:	case (v1*2.0) use
+       
+            when (2.0) use 
+                       if (v2==2.0) use
+			v2 == i2 * 100.0;
+		       else
+			v2 ==i2*10.0;
+            	       end use;
+	    when (6.0) use
+                       v2 == i2 * 200.0;
+            when (10.0) use
+                       v2 == i2 * 300.0;
+	end case c1;
+END asimcase ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test176.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test176.ams
new file mode 100644
index 0000000..dd7f811
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test176.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test176.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test176.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the simultaneous null statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2;
+quantity V3 across I3 through T2;
+quantity VS across T1;
+
+begin
+
+	V1==1.0;
+	if (V1<=1.0) use
+	   NULL;
+	else
+          V2 == V1*1.0;
+        end use;
+
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test177.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test177.ams
new file mode 100644
index 0000000..75b230a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test177.ams
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test177.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test177.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the 'path_name attribute. 
+
+--PACKAGE electricalSystem IS
+--    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+--    FUNCTION  SIN (X : real ) RETURN real;
+--    FUNCTION  EXP  (X : real ) RETURN real;
+--END PACKAGE electricalSystem;
+
+--USE work.electricalSystem.all;
+
+ENTITY Bottom IS
+generic(GBottom:integer);
+--port (PBottom:integer);
+constant SBottom:integer:=4;
+END Bottom;
+
+ARCHITECTURE BottomArch OF Bottom IS
+begin
+	ProcessBottom: process
+		variable V:integer;
+	begin
+		if GBottom=4 then
+		 assert 
+		 V'Path_Name= ":top:b1:b2:g1(4):b3:11:processbottom:v";
+		  -- and GBottom'Path_Name=":top:b1:b2:g1(4):b3:11:gbottom";
+		elsif GBottom=1 then
+		   assert
+		   V'Path_Name= ":top:12:processbottom:v";
+		else
+		   assert
+		   GBottom'Path_Name="top:12:gbottom";
+		end if;
+		wait;
+	end process ProcessBottom;
+end architecture BottomArch;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test178.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test178.ams
new file mode 100644
index 0000000..a3f8ea6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test178.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test178.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test178.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the simultaneous procedural equation statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+
+USE work.electricalSystem.all;
+
+ENTITY simproc IS
+END simproc;
+
+ARCHITECTURE asimproc OF simproc IS
+
+    terminal T1: electrical;
+    quantity vd across id through T1;
+    quantity charge: real;
+    constant vt: real:= 1.0;
+BEGIN
+        eq1: vd==1.0;
+	proc1: procedural is
+	variable vres:real;
+	constant tau:real:=1.0;
+	variable ares: real;
+	begin
+		e1: ares:=vd*1.0;
+		e3: vres:=vt;
+        end procedural;
+
+END asimproc ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test179.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test179.ams
new file mode 100644
index 0000000..1249b06
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test179.ams
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test179.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test179.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation
+-- 'instance_name attribute
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+
+USE work.electricalSystem.all;
+
+ENTITY Bottom IS
+generic(GBottom:integer);
+port (PBottom:integer);
+constant SBottom:integer:=4;
+END Bottom;
+
+ARCHITECTURE BottomArch OF Bottom IS
+begin
+--	SBottom :=4;
+	ProcessBottom: process
+		variable V:integer;
+	begin
+		if GBottom=4 then
+		 assert 
+		 V'Instance_Name=":top(top):b1:b2:g1(4):b3:11@bottom(bottomarch):processbottom:v"
+		 and 
+		 GBottom'Instance_Name=":top(top):b1:b2:g1(4):b3:11@bottom(bottomarch):gbottom";
+		elsif GBottom=1 then
+		   assert 
+                   V'Instance_Name=":top(top):12@bottom(bottomarch):processbottom:v";
+		else
+		   assert
+		   GBottom'Instance_Name= ":top(top):12@bottom(bottomarch):gbottom";
+		end if;
+		wait;
+	end process ProcessBottom;
+end architecture BottomArch;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test180.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test180.ams
new file mode 100644
index 0000000..feae7a6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test180.ams
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test180.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test180.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the break statement.it checks simple break and break on
+-- codition.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity VCO is
+port(terminal InTerminal,OutTerminal: electrical);
+end VCO; 
+ 
+architecture PhaseIntegrator of VCO is
+  quantity Vin across Iin through InTerminal to OutTerminal;
+  constant TwoPi: real := 6.283118530718; -- 2pi
+  quantity Phase : real; -- phase is a free quantity:
+  quantity Vout across Iout through OutTerminal;
+begin
+  break Phase => TwoPi;
+  Vout == 2.5*(sin(Phase)); -- output statement
+end PhaseIntegrator; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test181.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test181.ams
new file mode 100644
index 0000000..873a1f5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test181.ams
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test181.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test181.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the break statement.it checks simple break and break on
+-- codition.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity VCO is
+  port(terminal InTerminal,OutTerminal: electrical);
+end VCO; 
+ 
+architecture PhaseIntegrator of VCO is
+  quantity Vin across Iin through InTerminal to OutTerminal;
+  constant TwoPi: real := 6.283118530718; -- 2pi
+  quantity Phase : real; -- phase is a free quantity:
+  quantity Vout across Iout through OutTerminal;
+begin
+  break Phase => TwoPi;
+  -- break allows to define the initial conditions
+  break Phase => 0.0 on Phase'above(TwoPi);
+  Vout == 2.5*(sin(Phase)); -- output statement
+end PhaseIntegrator; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test182.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test182.ams
new file mode 100644
index 0000000..d945f01
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test182.ams
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test182.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati 
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test182.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001  
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the 'above attribute.
+                   
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+                
+        
+USE work.electricalSystem.all;
+
+entity test is 
+port(signal vout:out boolean);
+end entity;
+
+architecture atest of test is
+
+terminal T1: electrical;
+quantity vin across iin through T1;
+--constant vt: real:=3.0;
+begin
+e2 : vout <= vin'above(0.0);
+e1:  vin == 5.0 * sin(2.0 *3.141592 *100000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test183.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test183.ams
new file mode 100644
index 0000000..9cd07f3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test183.ams
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test183.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+-- this model tests for the correst implementation of the 'above 
+-- statement.
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity product is 
+generic(bound:real:=1.0);
+port(
+     quantity out1:real);
+end product;
+
+architecture pro of product is
+constant in1:real:=10.0;
+constant in2:real:=1.0;
+signal outofbound:out boolean;
+
+begin
+	outofbound<=true;
+	out1== in1*in2;
+	outofbound<=out1'above(bound);
+
+end pro;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams
new file mode 100644
index 0000000..ad706e0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test184.ams
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test184.ams,v 1.2 2003-08-05 15:14:24 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+---------------------------------------------------------------------
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test100.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- half wave Rectifier model ...
+-- the test is done for checking the correct implementation
+-- of the simultaneous if statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+----------------------------------------------------------------------
+--     T1   diode D  T2    
+--     o-----|>|-----o-------o       The circuit comprises:
+--     |             |               i)  A diode .
+--    ( )            >R=100ohms      ii) A sinusoidal voltage source.
+--     |Vs = 5sinwt  >               iii)A resistor R.
+--     |             >
+--     |_____________|_______o
+--                   |gnd
+--                 -----
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+----------------------------------------------------------------------
+
+USE work.electricalSystem.all;
+
+ENTITY hwr IS
+END hwr;
+
+ARCHITECTURE ahwr OF hwr IS
+
+    terminal T1, T2 : electrical;
+    quantity VDiode across IDiode through T1 to T2;
+    quantity V2 across I2 through T2 ;
+    quantity VS across T1 ;
+
+    CONSTANT saturation_current : real := 0.0000000000001;
+    CONSTANT Vt : real := 0.025;
+        
+    CONSTANT BV : real := 100.0;
+    CONSTANT neg_sat : real := -saturation_current;
+    
+BEGIN  
+
+      --diode equations
+      if( vDiode >= (-1.0 * Vt)) USE
+        eq1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0);
+
+      ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use
+        eq2:  iDiode == neg_sat;
+
+      ELSE
+        eq3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 +
+                                    saturation_current);
+      END USE ;
+                                                       
+      eqn2: v2 == 100.0 * i2;
+    
+      eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 *
+                            real(time'pos(now)) * 1.0e-15 );
+    
+END ahwr ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test185.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test185.ams
new file mode 100644
index 0000000..7852499
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/regression_test/test185.ams
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test185.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+USE work.electricalSystem.all;
+
+ENTITY simcase IS
+END simcase;
+
+ARCHITECTURE asimcase OF simcase IS
+
+    terminal T1: electrical;
+
+    quantity v1 across i1 through T1 ;
+
+BEGIN  
+	eq1: v1==1.0;
+	if (v1<=1.0) use	
+		e1: null;
+	end use;
+END asimcase ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/ccvs.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/ccvs.ams
new file mode 100644
index 0000000..65ba60b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/ccvs.ams
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: ccvs.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   terminal n1, n2 : electrical;
+   quantity is1 through n1;
+   quantity vr1 across ir1 through n1;
+   quantity vr2 across ir2 through n2;
+   quantity vs1 across n2;
+   constant r1 : REAL := 20.0;
+   constant r2 : REAL := 10.0;
+   constant r3 : REAL := 5.0;
+
+BEGIN 
+
+res1 : vr1 == ir1 * r1;
+res2 : vs1 == ir1 * r2;
+res3 : vr2 == ir2 * r3;
+vsrc : is1  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-15);
+ 
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/parallel.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/parallel.ams
new file mode 100644
index 0000000..0fbe031
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/parallel.ams
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: parallel.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   terminal n1 : electrical;
+
+   quantity vr1 across ir1 through n1 ;
+   quantity vr2 across ir2 through n1;
+   quantity vr3 across ir3 through n1;
+   quantity vs across n1;
+   constant r1 : REAL := 10.0;
+   constant r2 : REAL := 20.0;
+   constant r3 : REAL := 50.0;
+
+BEGIN 
+
+res1 : vr1 == ir1 * r1;
+res2 : vr2 == ir2 * r2;
+res3 : vr3 == ir3 * r3;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                                * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series-parallel.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series-parallel.ams
new file mode 100644
index 0000000..a5f537f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series-parallel.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: series-parallel.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   terminal n1, n2 : electrical;
+
+   quantity vr1 across ir1 through n1 to n2;
+
+   quantity vr2 across ir2 through n2 to electrical'reference;
+   --supposedly this works !!!! 
+   --quantity vr2 across ir2 through n2 to ground;
+   quantity vr3 across ir3 through n2;
+   quantity vs across n1;
+   constant r1 : REAL := 20.0;
+   constant r2 : REAL := 10.0;
+   constant r3 : REAL := 5.0;
+
+BEGIN 
+
+res1 : vr1 == ir1 * r1;
+res2 : vr2 == ir2 * r2;
+res3 : vr3 == ir3 * r3;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+ 
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series.ams
new file mode 100644
index 0000000..9dbb762
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/series.ams
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: series.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   terminal n1, n2, n3 : electrical;
+
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2 to n3;
+   quantity vr3 across ir3 through n3;
+   quantity vs across n1;
+   constant r1 : REAL := 10.0;
+   constant r2 : REAL := 20.0;
+   constant r3 : REAL := 50.0;
+
+BEGIN 
+
+res1 : vr1 == ir1 * r1;
+res2 : vr2 == ir2 * r2;
+res3 : vr3 == ir3 * r3;
+cons : ir1 == ir2;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vccs.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vccs.ams
new file mode 100644
index 0000000..3c2cc9a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vccs.ams
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: vccs.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+constant R1: real :=20.0;
+constant R2: real :=10.0;
+constant R3: real :=5.0;
+terminal T1,T2,T3:electrical;
+quantity Vs1 across T1;
+quantity Is1 through T2;
+quantity Vr1 across Ir1 through T2 to T3;
+quantity Vr2 across Ir2 through T3;
+
+BEGIN 
+
+
+res1 : vr1 == ir1 * r1;
+res2 : vr2 == ir2 * r2;
+res3 : is1 == vs1 * r3;
+vsrc : vs1  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                                * real(time'pos(now)) * 1.0e-15);
+ 
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vcvs.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vcvs.ams
new file mode 100644
index 0000000..24ee972
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/resistor_models/vcvs.ams
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: vcvs.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+constant R1: real :=20.0;
+constant R3: real :=10.0;
+terminal T1,T2,T3:electrical;
+quantity Vr2 across T2;
+quantity Vr3 across Ir3 through T2;
+quantity Vs across T1;
+
+BEGIN 
+
+vol1 : Vr2 == Vs * r1;
+res3 : vr3 == ir3 * r3;
+vsrc : Vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-15);
+
+END architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/clipper.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/clipper.ams
new file mode 100644
index 0000000..dac8953
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/clipper.ams
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 1998-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: clipper.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+------------------------------------------------------------------------
+-- Title         : Single diode clipper circuit
+-- Project       : Mixed signal simulation
+------------------------------------------------------------------------
+-- File          : diode_clipper1.vhd
+-- Author(s)     : Vasudevan Shanmugasundaram(vasu@ececs.uc.edu)
+-- Created       : jan 16 1998
+------------------------------------------------------------------------
+-- Description : 
+-- Behavioral description of a single diode clipper circuit.
+------------------------------------------------------------------------
+-- circuit diagram for the diode clipper:
+--                                         the circuit comprises:
+--  o______|l______o____|>|______o         i)  a diode D.
+--  |      |l      |   diode D             ii) a constant voltage source vd.
+--  |    const     |                       iii)a sinusoidal voltage source.
+-- ( )    Vsource  >                       iv) a resistor R.
+--  |Vs            >R
+--  |              >
+--  o______________|_____________o
+--  
+------------------------------------------------------------------------
+
+--package definition
+PACKAGE electricalSystem IS
+NATURE electrical IS real ACROSS real THROUGH ground reference;
+FUNCTION  SIN (X : real ) RETURN real;
+FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+-------------------------------------------------------------------------------
+
+USE work.electricalSystem.all;
+
+ENTITY diode_clipper IS
+END diode_clipper;
+
+ARCHITECTURE behav OF diode_clipper IS
+    --terminal declarations
+    terminal t1, t2, t3 : electrical;
+    --quantity declarations
+    quantity vDiode across iDiode through t1 TO t2;
+    quantity v2 across i2 through t2 TO t3;
+    quantity vd across electrical'reference TO t1;
+    quantity vs across electrical'reference TO t3;
+    --constants 
+    CONSTANT saturation_current : real := 0.0000000000001;
+    CONSTANT Vt : real := 0.025;        
+    CONSTANT BV : real := 100.0;
+    CONSTANT neg_sat : real := -saturation_current; 
+
+BEGIN  -- behav
+      if( vDiode >= (-1.0 * Vt)) USE --diode equations
+        eqn1_1: iDiode == saturation_current * ( exp(vDiode/Vt) - 1.0 );
+      ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use
+        eqn1_2:  iDiode == neg_sat;
+      ELSE
+        eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 +
+				     saturation_current);
+      END USE ;
+      
+      eqn2:     v2 == i2 * 100.0;  -- resistor eqn.
+
+      eqn3:     vs == 20.0 * sin(2.0 * 3.1415 * 10000.0 * real(time'pos(now)) *
+                   1.0e-15);  -- source
+
+      eqn4:     vd == 5.0;  -- dc source
+END behav;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/double_tuned.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/double_tuned.ams
new file mode 100644
index 0000000..d76b337
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/double_tuned.ams
@@ -0,0 +1,201 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: double_tuned.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+--************************************************************************
+-- Structural Model of a DOUBLED TUNED TRANSFORMER 
+-- VHDL-AMS implementation
+-- Developed at Distributed Processing Laboratory
+-- University of Cincinnati
+--************************************************************************
+
+--************************************************************************
+--
+--	             ________________________________
+-- 	    V_in    |                                |           
+--	      o-----|--------            ------------|---o  V_out         
+--	            |  |     |          |      |     |	
+--	            |  |     |          |      |     |	
+--	            |  |     |          |      |     |
+--	            |  |     >rp      rs<      |     |
+--	            |  |     >          <     ---    |
+--	      FM    | _|_    | .        |     ---    |  FM & AM Signal
+--	    Signal  | ___   ( )        ( )     |Cs   |
+--	            |  |    ( )  ||    ( )     |     |
+--	            |  |Cp  ( )  ||    ( )     |     |
+--	            |  |     | Lp    Ls |      |     |
+--	      o-----|--------            ------------|---o V_out_gnd      
+--	  Vin_gnd   |________________________________|
+--
+--************************************************************************
+
+PACKAGE electricalSystem IS
+NATURE electrical IS real ACROSS real THROUGH ground reference;
+FUNCTION SIN (X : real ) RETURN real;
+FUNCTION COS (X : real ) RETURN real;
+FUNCTION EXP  (X : real ) RETURN real;
+FUNCTION SQRT (X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+------------------------------------------------------------------------------
+----------------------  TUNED TRANSFORMER ------------------------------------
+------------------------------------------------------------------------------
+
+USE work.electricalSystem.all;
+
+ENTITY FM_2_AM_Converter IS
+generic (freq_fm : real := 1.0);
+port (terminal Signal_in, Signal_out : electrical);
+END FM_2_AM_Converter;
+
+ARCHITECTURE behav OF FM_2_AM_Converter IS
+
+  CONSTANT  k :real:=0.4;
+  CONSTANT lp :real:=1.0e-3;
+  CONSTANT ls :real:=1.0e-3;
+  CONSTANT rp :real:=10.0;	
+  CONSTANT rs :real:=10.0;	
+
+--> Q = 2*PI*Freq*L/R 		: for 10.7 MHz -> q=6723     
+
+  terminal temp1,temp2: electrical;
+
+  quantity v_rp across i_rp through Signal_in to temp1;
+  quantity v_rs across i_rs through temp2     to Signal_out;
+  
+  quantity V_cp across i_cp through Signal_in  to ground;
+  quantity V_cs across i_cs through Signal_out to ground;
+   	
+  QUANTITY V_lp ACROSS i_lp Through temp1 to ground;
+  quantity v_ls across i_ls through temp2 to ground;
+
+  quantity m : real ;         -- mutual inductance;
+
+
+BEGIN    --  behavior
+
+  brk : break i_lp => 0.0, i_ls => 0.0,v_cp=>0.0,v_cs=>0.0;
+
+  mutual : m == k * sqrt(lp*ls);
+  voltp : v_lp == lp * i_lp'dot + m * i_ls'dot;
+  volts : v_ls == ls * i_ls'dot + m * i_lp'dot;
+
+  i_cp == (25.331/(freq_fm*freq_fm))*v_cp'dot;   -- cal. using the value of Inductance
+  i_cs == (25.331/(freq_fm*freq_fm))*v_cs'dot;   -- as 1.0e-3.
+				     	  	 -- modify this if u want to use another	
+  v_rp == rp *i_rp;	              	         -- value of Lp and ls	
+  v_rs == rs *i_rs;				 -- c =1/(2*PI*F)*(2*PI*F)*L
+
+END behav;
+
+------------------------------Test Waveforms-----------------------
+
+--> FM  wave generator 
+----------------------
+
+use work.electricalsystem.all;
+
+ENTITY fm_source IS
+generic(c_freq:real:=100.0e6;		-- carrier frequency
+	s_freq:real:=25.0e3;		-- modulating(signal) frequency 
+	 V_fm :real:=1.0		-- Peak voltage of FM signal
+       );
+PORT(TERMINAL fm_out,fm_gnd : electrical);
+END fm_source;
+
+ARCHITECTURE fm_behavior OF fm_source IS
+
+quantity V_fm_signal across i_fm_signal through fm_out to fm_gnd;
+
+BEGIN
+
+--- the max. freq. deviation is 75.0Khz for FM Signal. 
+
+  V_fm_signal == (V_fm*sin((2.0*22.0/7.0*c_freq*real(time'pos(now))*1.0e-15)+(75.0e3/s_freq*sin(2.0*22.0/7.0*s_freq*real(time'pos(now))*1.0e-15))));
+
+END ARCHITECTURE fm_behavior;
+
+--------------------------------  TEST BENCH --------------------------
+
+use work.electricalSystem.all;
+
+entity test is
+end test;
+
+architecture structure of test is
+
+  terminal t1,t2,t3 : electrical;
+
+--> Component Declarations
+
+component fm_source is
+generic(c_freq:real:=100.0e6;		-- carrier frequency
+	s_freq:real:=25.0e3;		-- modulating(signal) frequency 
+	  V_fm:real:=1.0		-- Peak Voltage of FM Signal	
+       );
+PORT( TERMINAL fm_out,fm_gnd : electrical);
+end component;
+for all: fm_source use entity work.fm_source(fm_behavior);
+
+component FM_2_AM_Converter IS
+generic (freq_fm : real := 1.0);
+port (terminal Signal_in, Signal_out : electrical);
+end component;
+for all : FM_2_AM_Converter use entity work.FM_2_AM_Converter(behav);
+
+quantity v_out across i_out through t2 to ground;
+
+begin  
+
+   FM_AM : FM_2_AM_Converter generic map(freq_fm=>10.7816e6)
+ 		       	     port map(t1,t2);
+
+   fm_ip : fm_source         generic map(10.7e6,10.0e3,1.0)
+			     port map(t1,ground);
+   
+  resout : v_out == i_out * 1.0e6;
+
+end structure;
+
+------------------------------  NOTES -------------------------------------
+--	It is a tuned transformer with the resonant freq. slighty higher 
+--	than the carrier freq.
+--
+--	Q = 2*PI*Freq*L/Rl		BandWidth = F_carrier/Q
+--	F_carrier = 1/2*PI*sqrt(L*C)    
+--
+--	Tune the Transformer to a frequency of   (All quantities in MHz)
+--		( F_carrier + 0.075 + 0.005 + Band_width ) 
+--			       |	
+--			       |	
+-- 			       *-> Max Deviation	
+----------------------------------------------------------------------------
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/hwr_filter.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/hwr_filter.ams
new file mode 100644
index 0000000..ec678f1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/hwr_filter.ams
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 1998-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: hwr_filter.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- Title         : Half Wave Rectifier with capacitor filter
+-- Project       : Mixed signal simulation
+----------------------------------------------------------------------
+-- File          : hwr.vhd (Behavioral)
+-- Author(s)     : Vasudevan Shanmugasundaram(vasu@ececs.uc.edu)
+-- Created       : jan 16 1998
+----------------------------------------------------------------------
+-- Description : 
+-- Behavioral description of a half wave rectifier circuit with a 
+-- capacitor filter.
+----------------------------------------------------------------------
+--     T1   diode D  T2    
+--     o-----|>|-----o----o-------o   The circuit comprises:
+--     |             |    |           i)  A diode .
+--    ( )            |    >R=100ohms  ii) A sinusoidal voltage source
+--     |Vs = 5sinwt  __   >           iii)A resistor R.
+--     |             --   >           iv) A capacitor C.
+--     |             |C   |
+--     |_____________|____|_______o
+--                   |gnd
+--                 -----
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+    
+END PACKAGE electricalSystem;
+
+----------------------------------------------------------------------
+
+USE work.electricalSystem.all;
+
+ENTITY hwr_filter IS    
+END hwr_filter;
+
+-- purpose: a capacitor filtered half wave rectifier
+ARCHITECTURE behav OF hwr_filter IS
+
+    terminal t1, t2 : electrical;
+    quantity vDiode across iDiode through t1 TO t2;
+    quantity v2 across i2 through t2 TO electrical'reference;
+    quantity vc across ic through t2 TO electrical'reference;
+    quantity vs across t1 TO electrical'reference;
+
+    CONSTANT saturation_current : real := 0.0000000000001;
+    CONSTANT Vt : real := 0.025;
+        
+    CONSTANT BV : real := 100.0;
+    CONSTANT neg_sat : real := -saturation_current; 
+    
+BEGIN  -- behav
+
+      -- diode behavior equation
+      if( vDiode >= (-1.0 * Vt)) USE
+        eqn1_1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0);
+      
+      ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use
+        eqn1_2:  iDiode == neg_sat;
+      
+      ELSE
+        eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 +                                          saturation_current);
+        
+      END USE ;
+                            
+      eqn2:  v2 == 100.0 * i2;                   -- resistor
+
+      eqn4:  vs == 5.0 * sin(2.0 * 3.1415 * 10000.0 --sine source
+				* real(time'pos(now)) * 1.0e-15); 
+
+      eqn6:  ic ==  0.000005 * vc'dot;          -- capacitor
+
+END behav;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/limiter.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/limiter.ams
new file mode 100644
index 0000000..3e605b4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/limiter.ams
@@ -0,0 +1,153 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: limiter.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+--
+--	    		R1(10.0)   R2(10.0)	
+--		o----^^^^^^^^------o-^^^--o--------------o 
+--	       V_in		 T1|	  |            V_out		
+--				   |	  |		
+--				   |	  |		
+--			 	  _|_	 ---  
+--			          \ /	 / \
+--				  ---	 ---
+--				   |	  |	
+--				T2 o	  o T3	
+--				   |	  |	
+--				 -----	 ---
+--				  ---   -----	 	
+--  				   |	  |	
+--  				   |	  |	
+--  	    V_in_gnd		   |	  |	     V_out_gnd	
+--		o----------------------------------------o		
+
+
+ PACKAGE electricalsystem IS
+     NATURE electrical IS real ACROSS real THROUGH ground reference;
+     FUNCTION SIN(X:real) RETURN real;
+     FUNCTION EXP(X:real) RETURN real;
+ END PACKAGE electricalsystem;
+
+-------------------------- LIMITER ------------------------------
+use work.electricalsystem.all;
+
+entity limiter is 
+generic (lim:real:=1.0);
+port (terminal v_in,v_out :electrical);
+end entity limiter;
+
+architecture behav of limiter is
+
+terminal t1,t2,t3 :electrical;
+
+constant    k:real := 0.02586; 		-- thermal voltage
+constant  iss:real := 1.8104e-15;	
+constant gmin:real := 1.0e-12;
+
+quantity vd1 across id1 through t1 to t2;
+quantity vd2 across id2 through t3 to v_out;
+quantity V_volt1 across i_volt1 through t2 to ground ;
+quantity V_volt2 across i_volt2 through ground to t3;
+quantity v_r1 across i_r1 through V_in to T1;
+quantity v_r2 across i_r2 through T1 to V_out;
+
+BEGIN
+ 
+	if (vd1 >= (-5.0*k)) use
+		  id1 == iss * (exp(vd1/k)-1.0) + vd1*gmin;
+	elsif (vd1<-5.0*k) use
+		  id1 == -1.0*iss + vd1*gmin;
+	end use;
+
+	if (vd2 >= (-5.0*k)) use
+		  id2 == iss * (exp(vd2/k)-1.0) + vd2*gmin;
+	elsif (vd2<-5.0*k) use
+		  id2 == -1.0*iss + vd2*gmin;
+	end use;
+	V_volt1 == (lim);
+	V_volt2 == (lim);
+        V_r1 == i_r1*10.0;
+        V_r2 == i_r2*10.0;
+
+end architecture behav;
+
+
+--------------------------- Test Waveforms -----------------------------
+
+use work.electricalsystem.all;
+ENTITY sineSource IS
+generic( amp:real:=1.0);
+  PORT( TERMINAL ta2,tb2 : electrical);
+END sineSource;
+
+ARCHITECTURE sinebehavior OF sineSource IS
+quantity Vsine across isine through ta2 to tb2;
+
+BEGIN
+  Vsine == (amp*sin((2.0*22.0/7.0*10.7e6)*real(time'pos(now))*1.0e-15));
+
+END ARCHITECTURE sinebehavior;
+    
+
+------------------------------ Test Case -------------------------------
+use work.electricalsystem.all;
+entity testbench is
+end entity;
+
+architecture basic of testbench is 
+
+
+terminal t1,t2 :electrical;
+
+quantity v_out across i_out through t2 to ground;
+
+component limiter is
+generic (lim:real:=1.0);
+port(terminal v_in,v_out :electrical);
+end component;
+
+component sinesource is
+generic( amp:real:=1.0);
+  PORT( TERMINAL ta2,tb2 : electrical);
+end component;
+
+BEGIN
+
+lim : limiter    generic map(lim=>3.0)
+	         port map(t1,t2);
+
+sine: sinesource generic map(amp=>6.0)
+		 port map(t1,ground);
+
+v_out ==i_out*1.0e3;
+
+end basic;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/peak_detector.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/peak_detector.ams
new file mode 100644
index 0000000..9e23e20
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/peak_detector.ams
@@ -0,0 +1,274 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: peak_detector.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- Change the values of res. and cap for various freq.'s
+
+
+
+--*************************************************************************
+-- Conceptual Level Model of a Peak Detector
+-- VHDL-AMS implementation
+-- Developed at Distributed Processing Laboratory
+-- University of Cincinnati
+-- by Murthy Revanuru on October 27, 2000.
+--*************************************************************************
+
+--#########################################################################
+--			  R2= 10.0e3
+--		 --------/\/\/\----------
+--		|	|\		 |
+--		.-------|-\        Diode |		
+--			|  \________|\___|_____o V_out
+--		    10K	|  /	    |/	 |
+--	V_in	o---^^^-|+/		 |-------- 		
+--		    R1	|/		 |	  |
+--				       _____	  \		
+--				  Cap  _____	  / Res	
+--				 	 |	  \	
+--					 |	  /	
+--					 | 	  |
+--				     ---------  -----
+--					---	  -	 		
+--
+--#########################################################################
+
+ PACKAGE electricalsystem IS
+     NATURE electrical IS real ACROSS real THROUGH ground reference;
+     FUNCTION SIN(X:real) RETURN real;
+     FUNCTION COS(X:real) RETURN real;
+     FUNCTION EXP(X:real) RETURN real;
+     FUNCTION SQRT(X:real) RETURN real;
+ END PACKAGE electricalsystem;
+
+---------------------------- Diode -----------------------------
+use work.electricalsystem.all;
+
+entity diode is 
+port (terminal t21,t22:electrical);
+end diode;
+
+architecture behavior of diode is
+
+quantity vd across id through t21 to t22;
+constant k:real:=0.02586; -- thermal voltage
+constant iss:real:=1.8104e-15;
+constant gmin:real:=1.0e-12;
+
+begin
+
+if (vd >= (-5.0*k)) use
+  id == iss * (exp(vd/k)-1.0) + vd*gmin;
+elsif (vd<-5.0*k) use
+  id == -1.0*iss + vd*gmin;
+end use;
+end architecture behavior;
+
+------------------------ RESISTOR---------------------------
+use work.electricalsystem.all;
+
+entity resistor is
+ generic(res :real:=1.0 );
+  port(terminal r_in,r_out: electrical);
+end entity resistor;
+
+architecture behav of resistor is
+   quantity vr across ir through r_in to r_out;
+
+begin
+  vr==ir*res;
+end architecture behav;
+
+------------------------ CAPACITOR---------------------------
+use work.electricalsystem.all;
+
+entity capacitor is
+ generic(cap :real:=1.0;v_init:real:=0.0);
+ port(terminal c_in,c_out: electrical);
+end entity capacitor;
+
+architecture behav of capacitor is
+
+quantity vc across ic through c_in to c_out;
+
+begin
+  break vc=>v_init;
+  ic==cap*vc'dot;
+end architecture behav;
+
+------------------------- OP AMP -------------------------
+use work.electricalsystem.all;
+
+entity op_amp is
+port(terminal inverting_ip,non_inverting_ip,output :electrical);
+end entity op_amp;
+
+architecture struct of op_amp is
+
+Constant R_in:real:=1.0e6;
+Constant R_out:real:=1.0;
+
+terminal t1:electrical;
+ 
+quantity v_in  across i_in  through non_inverting_ip to inverting_ip;
+quantity v_gain across i_gain through t1 to ground;
+quantity v_drop across i_drop through t1 to output;
+
+BEGIN
+ 
+ V_in==i_in*R_in;
+ V_gain==V_in*(100.0);
+ V_drop==i_drop*R_out;
+ 
+end architecture struct;
+
+---------------------- PEAK  DETECTOR ---------------------
+use work.electricalsystem.all;
+
+entity peak_detector is
+port (terminal v_in,v_out: electrical);
+end entity peak_detector;
+
+architecture struct of peak_detector is
+
+component capacitor is 
+ generic(cap :real:=1.0;v_init:real:=0.0);
+ port(terminal c_in,c_out: electrical);
+end component;
+for all: capacitor use entity work.capacitor(behav);
+ 
+component resistor is
+ generic(res :real:=1.0 );
+  port(terminal r_in,r_out: electrical);
+end component;
+for all: resistor use entity work.resistor(behav);
+ 
+component diode is
+port (terminal t21,t22:electrical);
+end component;
+for all: diode use entity work.diode(behavior);
+
+component op_amp is
+port(terminal inverting_ip,non_inverting_ip,output :electrical);
+end component;
+for all:op_amp use entity work.op_amp(struct);
+
+terminal t11,t12,t13,t14: electrical;
+
+
+begin
+
+ D1: diode     port map(t12,t13);
+
+ R1: resistor  generic map(10.0e3)
+	       port map(v_in,T11);
+ R2: resistor  generic map(10.0e3)
+	       port map(T13,T14);
+ Rs: resistor  generic map(1.0e-3)
+	       port map(T13,V_out);
+
+ C1: capacitor generic map(1.0e-9)
+	       port map(T13,ground);
+
+ op: op_amp    port map(inverting_ip=>T14,non_inverting_ip=>T11,output=>T12);
+
+end struct;
+ 		
+-- ################### TEST WAVE FORMS #######################
+-- Sine Source
+--------------
+use work.electricalsystem.all;
+ENTITY sineSource IS
+generic (amp:real:=1.0; freq:real:=1.0);
+  PORT( TERMINAL ta2,tb2 : electrical);
+END sineSource;
+
+ARCHITECTURE sinebehavior OF sineSource IS
+quantity Vsine across isine through ta2 to tb2;
+
+BEGIN
+  Vsine ==(amp*sin((2.0*22.0/7.0*freq)*real(time'pos(now))*1.0e-15));
+
+END ARCHITECTURE sinebehavior;
+
+-- AM Source
+--------------
+use work.electricalsystem.all;
+ENTITY amSource IS
+generic (amp:real:=1.0; wc:real:=1.0;wm:real:=1.0);
+  PORT( TERMINAL ta2,tb2 : electrical);
+END amSource;
+
+ARCHITECTURE ambehavior OF amSource IS
+quantity V_am across i_am through ta2 to tb2;
+
+BEGIN
+  V_am == (amp*cos((2.0*22.0/7.0*wc)*real(time'pos(now))*1.0e-15)) +(amp/2.0*cos((2.0*22.0/7.0*(wc+wm))*real(time'pos(now))*1.0e-15)) +
+	  (cos((2.0*22.0/7.0*(wc-wm))*real(time'pos(now))*1.0e-15));
+
+END ARCHITECTURE ambehavior;
+
+------------------------- Test bench -------------------------
+
+use work.electricalsystem.all;
+
+entity rf_test_bench is
+end entity rf_test_bench;
+
+architecture basic of rf_test_bench is
+
+terminal t1,t2,t3,t4 : electrical;
+
+----> Components are declared here
+
+component peak_detector is
+port(terminal v_in,v_out :electrical);
+end component;
+for all: peak_detector use entity work.peak_detector(struct);
+
+COMPONENT sineSource IS
+generic (amp:real:=1.0; freq:real:=1.0);
+    PORT( TERMINAL ta2,tb2 : electrical);--Interface ports.
+end COMPONENT;
+for all : sinesource use entity work.sinesource(sinebehavior);
+
+quantity volt_op across i_op through t4 to ground;
+
+begin
+
+      op_1    : volt_op==i_op*10000.0;
+
+   peak_det   : peak_detector port map(t1,t4);	
+   sine_ip    : sinesource    generic map(1.0,455.0e3)
+			      port map(t1,ground);
+
+end architecture basic;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/power_supply.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/power_supply.ams
new file mode 100644
index 0000000..c83db0b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/power_supply.ams
@@ -0,0 +1,138 @@
+
+-- Copyright (C) 1997-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: power_supply.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- Title         : Power supply circuit (Behavioral)
+-- Project       : Mixed signal simulation
+----------------------------------------------------------------------
+-- File          : power_supply.ams
+-- Author        : Kathiresan Nellayappan  <knellaya@ececs.uc.edu>
+--                 Chandrashekar L Chetput <cchetput@ececs.uc.edu>
+-- Created       : 26.11.1997
+----------------------------------------------------------------------
+-- Description :
+-- VHDL-AMS description of a power supply circuit.
+-- BEHAVIORAL DESCRIPTION.
+----------------------------------------------------------------------
+-- The ciruit schematic for the power supply circuit is as below:
+-- ==============================================================
+--                                                     It comprises:
+--             diode D1            inductor            i) a sinusoidal 
+--  T2      _____|\|____     T3      L1       T4        voltage source
+--  o______|     |/|    |____o______()()()____o______o  ii) a diode D1
+--  |      |            |    |       0.1H     |      | iii)3 capacitors
+--  <      |            |    |                |      | iv) inductor L1
+--  < R1   |_____||_____|    |                |      |  v)  source and 
+--  < 5ohms      ||        _____            _____    < load resistances
+--  <            C1        -----            -----    < RL 
+--  |            1microF     |                |      <
+--  o T1                     |                |      <
+--  |                        |C2              |C3    < 1K
+-- ( )Vin                    |1mf             |1mf   <
+--  | 10(sinwt)              |                |      |
+--  o________________________|________________|______|
+--                           |gnd
+--                         -----
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+--Entity declaration:
+ENTITY power_supply IS
+END ENTITY power_supply;
+
+
+--Architecture declaration:
+ARCHITECTURE behavior OF power_supply IS
+
+    CONSTANT Capacitance1 : real := 0.000001;  -- value of C1
+    CONSTANT Capacitance2 : real := 0.001;     -- value of C2
+    CONSTANT resistance1 : real := 5.0;        -- value of R1
+    CONSTANT load_resistance : real := 1000.0; -- value of RL
+    CONSTANT inductance : real := 0.1;         -- value of L1
+    CONSTANT BV : real := 100.0;               -- Diode Breakdown voltage
+    CONSTANT saturation_current : real
+        := 0.0000000000001;       -- Diode saturation current value.
+    CONSTANT Vt : real := 0.025;  -- Vt = KT/q (thermal voltage)     
+    CONSTANT neg_sat : real
+        := -saturation_current;   -- Negative of the saturation current
+    CONSTANT  MATH_PI :  real := 3.14159_26535_89793_23846;  
+
+    terminal t1, t2, t3, t4 : electrical;
+
+    
+--quantity declarations:
+  QUANTITY Vin ACROSS Iin THROUGH T1;
+  QUANTITY vr1 ACROSS ir1 THROUGH T2 TO T1;
+  QUANTITY d1_v ACROSS d1_i THROUGH T2 TO T3;
+  QUANTITY vc1 ACROSS ic1 THROUGH T2 TO T3;
+  QUANTITY vc2 ACROSS ic2 THROUGH T3;
+  QUANTITY vl ACROSS il THROUGH T3 TO T4;
+  QUANTITY vc3 ACROSS ic3 THROUGH T4;
+  QUANTITY vr2 ACROSS ir2 THROUGH T4;
+  QUANTITY phi : real; --free quantity.
+
+
+BEGIN
+
+  C1: ic1 == vc1'dot * Capacitance1;       -- capacitance equation: ic = c*dv/dt.
+  C2: ic2 == vc2'dot * Capacitance2;       -- capacitance equation for C2.
+  C3: ic3 == vc3'dot * Capacitance2;       -- capacitance equation for C3.
+  res_stmt1: vr1 == ir1 * resistance1;     -- resistance equation: v = i*r.
+  res_stmt2: vr2 == ir2 * load_resistance; -- resistance equation.
+  induct_stmt: phi == inductance * il;     -- inductance equation: flux = L*I 
+  aux_stmt:    vl == phi'dot;              -- inductance equation: VL = dflux/dt.
+
+  -- the diode equations:
+  diode1Cond1: IF( d1_V >= (-3.0 * Vt) ) USE 
+		 --active region:
+  diode1St1:   d1_I == saturation_current * (exp(d1_V/Vt) - 1.0);
+              ELSIF( (d1_V < (-3.0 * Vt)) AND (d1_V > -BV)) USE
+		 --
+  diode1St2:    d1_I == neg_sat;
+              ELSE
+  diode1St3:    d1_I == neg_sat * (exp(-(BV + d1_V)/Vt) -1.0 +
+                                   saturation_current);
+              END USE;
+
+  --Sinusoidal voltage source:
+  vsource: Vin == 10.0 * sin(2.0 * 3.14 * 60.0 * real(time'pos(now)) *
+                             1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test100.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test100.ams
new file mode 100644
index 0000000..eba8a87
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test100.ams
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test100.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test100.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation 
+-- of the simple simultaneous equation statement.it checks 
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2;
+quantity V3 across I3 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*100.0;
+e2:     V2 == I2*10.0;
+e3:     V3 == I3*10.0;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test101.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test101.ams
new file mode 100644
index 0000000..daf5ffb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test101.ams
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test101.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test101.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this test checks teh correctness of the 'integ implementation.
+-- it finds the integral of teh source voltage.
+-- the input is a sine wave.
+---------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity test;
+
+architecture atest of test is
+quantity vs : real;
+quantity vout: real;
+begin
+vs== 5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) *
+                1.0e-15);
+vout == vs'integ;
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test102.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test102.ams
new file mode 100644
index 0000000..db2b975
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test102.ams
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test102.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test102.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the Q'integ usage on the RHS of
+-- the simple simultaneous eqn.
+--------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity tank is
+end tank;
+
+architecture atank of tank is
+
+terminal t1,t2 : electrical;
+
+constant r: real :=10.00;
+constant c: real:=0.00000003;
+
+quantity vin across t1 to electrical'reference;
+quantity vr across ir through t1 to t2;
+quantity vc across ic through t2 to electrical'reference;
+quantity q : real;
+begin
+
+        vr == ir*r;
+	q==c*vc;
+	ic==q'integ;	
+        vin ==  5.0 * sin(2.0 * 3.1415 * 10.0 * real(time'pos(now)) *
+                1.0e-15);
+end atank;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test103.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test103.ams
new file mode 100644
index 0000000..805fac6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test103.ams
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test103.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test103.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the simple simultaneous eqn.
+-- implementation. This is also a test for the lexical analysis.
+--------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2,T3,T4,T5:electrical;
+quantity v1 across i1 through T1 to T2;
+quantity v2 across i2 through T2 to T4;
+quantity v3 across i3 through T4 to T3;
+quantity v4 across i4 through T2 to T5;
+quantity v5 across i5 through T5 to T3;
+quantity v6 across i6 through T2 to T3;
+quantity vS across T1 to electrical'reference;
+
+begin
+
+e1:	v1==i1*1.0;
+e2:	v2==i2*1.0;
+e3:	v3==i3*1.0;
+e4:	v4==i4*1.0;
+e5:	v5==i5*1.0;
+e6: 	v6==i6*1.0;
+es:	vS==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test104.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test104.ams
new file mode 100644
index 0000000..72f1b4e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test104.ams
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test104.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test104.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this is a test that checks for the correct implementation of if use 
+-- end use. The condition is checked by comparing the quantity against a 
+-- known constant value.
+-----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+	generic (vmax :real:=10.0);
+end entity;
+
+architecture atest of test is
+terminal T1:electrical;
+quantity vin across T1;
+constant a:real:=1.0;
+constant b:real:=2.0;
+quantity vin1:real;
+quantity vin2:real;
+
+begin
+
+vin == vmax/a;
+
+if (vin==10.0) use
+e1:	vin1==vmax*b;
+else
+e2:	vin2==vmax;
+end use;
+
+
+--if(vin<vmax) use
+--e3:	vin==vmax/b;
+--else
+--e4:	vin==vmax;
+--end use;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test105.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test105.ams
new file mode 100644
index 0000000..7b426ba
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test105.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test105.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test105.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of quantity as a port declaration.
+-- the circuit is a simple RC network with vout acting as thge output port.
+-- a sine input is applied to the network.
+-------------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+    FUNCTION COS(X : real) RETURN real;
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+  port(quantity vout:out real);
+end entity;
+
+architecture atest of test is 
+  terminal T1,T2:electrical;
+  quantity VR across IR through T1 to T2;
+  constant R:real:=100.0;
+  constant C:real:=1.0e-9;
+  quantity vout across T2;
+  quantity vin across T1;
+begin
+  vsource: vin==5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+  vres: IR== VR/R;
+  cap: vout==C*IR'integ;
+
+end atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test106.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test106.ams
new file mode 100644
index 0000000..c548b2b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test106.ams
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test106.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test106.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation 
+-- of the simple simultaneous equation statement.it checks 
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2, T3, T4,T5,T6:electrical;
+quantity VRgen across IRgen  through T1 to T2;
+quantity VLgen across ILgen through T2 to T3;
+quantity VRin across IRin through T3; 
+quantity VR1 across IR1 through T4 to T5;
+quantity VR1A across IR1A through T4 to T6;
+quantity VC1A across IC1A through T6 to T5;
+quantity VC1 across IC1 through T5;
+quantity VS across T1;
+constant C1: real:=3.5e-3;
+constant C1A: real:=0.3e-3;
+begin
+
+e1:     VRgen == IRgen*10.0;
+e2:     VLgen == 0.5*ILgen'dot;
+e3:     VRin == IRin*500.0;
+e4:	VR1 == IR1*1.0;
+e5:	VR1A == IR1A*0.2;
+e6:	IC1 == C1 * VC1'dot;
+e7:	IC1A == C1A*VC1A'dot;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test108.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test108.ams
new file mode 100644
index 0000000..6bfad5b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test108.ams
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test108.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test100.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+architecture atest of test is
+terminal t1, t2: electrical;
+quantity vd across id through T1; -- to T2;
+quantity charge :real;
+constant vt:real:=0.02;
+
+begin
+
+p1: procedural is
+begin
+	vd:=1.0*id;
+end procedural;
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test109.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test109.ams
new file mode 100644
index 0000000..0a2f21a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test109.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test109.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test109.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of the procedural statements.
+-- multiple terms on the RHS
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUD REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal t1,t2: electrical;
+quantity vd across id through t1 to t2;
+quantity charge:real;
+constant vt:real:=0.0258;
+constant x:real:=1.0;
+quantity ic:real;
+
+begin
+p1: procedural 
+begin
+id:=0.1*(exp((vd-1.0*id)/vt)-1.0);
+charge := x*id;
+ic:= charge'dot;
+end procedural;
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test110.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test110.ams
new file mode 100644
index 0000000..96052a1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test110.ams
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test110.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- an example of a model having both a signal assignment statement
+-- as well as a simple simultaneous statement.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+use std.textio.all;
+ENTITY test IS
+END test;
+
+ARCHITECTURE behavior OF test IS
+    CONSTANT r1 : real := 100.0;        -- value of R1
+    terminal t1 : electrical;
+  QUANTITY vIn ACROSS t1;
+  QUANTITY vR ACROSS iR THROUGH t1 ;
+  signal y:bit:='0';
+BEGIN
+
+process(y)
+begin
+  y <= not(y) after 100 ns;
+ 
+end process;
+
+ testbench:PROCESS
+    BEGIN
+        WAIT ON y;
+    END PROCESS;
+  res_stmt1: vR == iR * r1 ;
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test111.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test111.ams
new file mode 100644
index 0000000..4f86612
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test111.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test111.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : model.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the Q'Tolerance.
+-- the test checks for the simpel diode implementation
+-- wherein the charge is evaluated wrt a relative tolerance value
+----------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+  generic(a:real:=1.0e-10; b:real:=0.0);
+  port (terminal t1: electrical);
+end entity;
+
+architecture atest of test is
+  quantity vd tolerance "reltol=1.0e-2" across id through t1;
+  quantity charge: real;
+  quantity ic : real;
+  constant rd: real:=1.0;
+begin
+  e1:	id== a*(sin((vd-id*rd)/0.5)-1.0);
+  e2:	charge== b*id;
+  e3:	ic==charge'dot;
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test113.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test113.ams
new file mode 100644
index 0000000..0e35758
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test113.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test113.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test113.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the Q'Tolerance for across qnty
+-- and for the real quantity.The test checks for the simpel diode 
+-- implementation wherein the charge is evaluated wrt a relative 
+-- tolerance value
+-- the test doesn't seem to take a tolerance associated with a
+-- free quantity. we need to check on this!! (LRM : 4.3.1 spec 
+-- followed.
+----------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+generic(a:real:=1.0e-10; b:real:=0.0);
+port (terminal t1: electrical);
+
+end entity;
+
+architecture atest of test is
+quantity vd across id through t1; -- to electrical'reference;
+quantity charge:real tolerance "reltol=1.0e-2";
+--quantity ic : real;
+constant rd: real:=1.0;
+begin
+e1:     id== a*(sin((vd-id*rd)/0.5)-1.0);
+e2:     charge== b*id; 
+--e3:     ic==charge'dot;
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test114.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test114.ams
new file mode 100644
index 0000000..7bd8078
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test114.ams
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test114.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : model.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the two currents associated 
+-- as through between same terminals.for eg: consider 2 resistors in
+-- parallel.. here vd is same and id and ic are the currents.
+-- the test checks for the simpel diode implementation
+-- wherein the charge is evaluated wrt a relative tolerance value
+----------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+entity test is
+  generic(a:real:=1.0e-10; b:real:=0.0);
+end entity;
+
+architecture atest of test is
+  terminal t1:electrical;
+  quantity vd across id, ic through t1;
+  quantity charge: real;
+  --quantity ic : real;
+  constant rd: real:=1.0; 
+begin
+  e1:     id== ((vd-id*rd)/0.5);
+  e2:     charge== b*id;
+  e3:     ic==charge'dot;
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test115.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test115.ams
new file mode 100644
index 0000000..c0232d0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test115.ams
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test115.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test115.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of the interface declaration:
+-- quantity : in| out. 
+-- ref LRM 4.3.2
+---------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    subtype voltage is real;
+    subtype current is real;
+    NATURE electrical is voltage across current THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is
+
+    port(quantity vout:out electrical);
+
+end entity test;
+
+architecture atest of test is
+terminal t1,t2: electrical;
+
+quantity vin across iin through t1;
+quantity vr across ir through t1 to t2;
+quantity vout across t1 to t2;
+
+begin
+
+e1: vin==  5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15);
+
+e2: vr==ir*1.0;
+
+e3: vout== vr;
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test116.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test116.ams
new file mode 100644
index 0000000..0ce660f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test116.ams
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test116.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test116.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of the interface declaration:
+-- quantity : in| out. A simple R circuit with an ac voltage source 
+-- is used.  
+-- ref LRM 4.3.2
+---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical is real across real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+
+    port(quantity vout:out voltage);
+
+end entity test;
+
+architecture atest of test is
+terminal t1,t2: electrical;
+
+quantity vin across iin through t1;
+quantity vr across ir through t1 to t2;
+quantity vout across t1 to t2;
+
+begin
+
+e1: vin==  5.0 * sin(2.0 * 3.1415 * 10000000.0 * real(time'pos(now)) *1.0e-15);
+
+e2: vr==ir*1.0;
+
+e3: vout== vr;
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test118.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test118.ams
new file mode 100644
index 0000000..7e45298
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test118.ams
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test118.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test118.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+
+-- the test checks for the correctness of the implemenatation of the case statement.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity test is
+end entity test;
+
+architecture atest of test is
+terminal t1:electrical;
+signal ison: boolean;
+quantity vr across ir through t1;
+constant vt:real:=0.0258;
+begin
+
+process 
+	variable off : boolean:=true;
+begin
+	ison <= not off;
+	case off is
+	   when true=> 
+		ison<= not off;
+	   when false=>
+		ison<=off;
+	end case;
+end process;
+source: vr==10.0 * sin(2.0 *(22.0/7.0)*100000.0*real(time'pos(now)) * 1.0e-15);
+if ison use
+	ir== 5.0; --*(exp(vr/vt)-1.0);
+else	
+	ir==0.0;
+end use;
+
+break on ison;
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test119.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test119.ams
new file mode 100644
index 0000000..ee7d1b6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test119.ams
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test119.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test1.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+-- Last modified :
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- This is the simple resistor model that sets the foundation on which 
+-- we build SIERRA, the VHDL AMS simulator. The circuit consists of 3 
+-- resistors connected to a voltage source.
+--   T1        R1    T2
+--     o-----/\/\----o--------       
+--     |             |    |          
+--    ( )            >    >   
+--     |Vs = 5sinwt  >R2  >R3           
+--     |             >    >
+--     |_____________|____|___
+--                   |gnd
+--                 ----
+--------------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+
+constant R1: real :=10.0;
+constant R2: real :=5.0;
+constant R3: real :=1.0;
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2 to electrical'reference;
+quantity V3 across I3 through T2 to electrical'reference;
+quantity VS across T1 to electrical'reference;
+
+begin
+
+e1:	V1 == I1*R1;
+e2:	V2 == I2*R2;
+e3:	V3 == I3*R3;
+
+esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
+
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test121.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test121.ams
new file mode 100644
index 0000000..9da136b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test121.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test121.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test3.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this is to check the quantity: q'dot in the lhs and rhs of the 
+-- simultaneous statements
+---------------------------------------------------------------------
+PACKAGE electricalSystem is 
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+	quantity x11: real;
+	constant x1:real:=2.0;
+	constant x2:real:=1.0;
+	constant m1 : real:=1.0;
+	quantity f : real;	
+	quantity dx1 : real;
+ 
+begin
+e1:	f == 10.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+e2:	x11 == f*(x1-x2)/m1;
+e3:	dx1 == f'dot;
+
+--	x1'dot == f*(x1-x2)/m1;
+--	x2'dot == f*(x1-x2)/m2;
+--	xs == (m1*x1+m2*x2)/(m1+m2);
+--	m3 == m1*x1'dot+ m2*x2'dot;
+end atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test122.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test122.ams
new file mode 100644
index 0000000..ad2ccd3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test122.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test122.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test122.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+
+-- to check for the correct implementation of the simple simultaneous
+-- statements 
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity chk is
+  generic(i:real:=1.0e-9); 
+  port(terminal t1, t2: electrical);
+end chk;
+
+architecture achk of chk is
+	quantity vd across id through t1 to t2;
+	quantity q: real;
+	quantity ic:real;
+	constant vth : real:= 0.025;
+begin
+
+e1:	id == i*(exp(vd/vth)-1.0);
+e2:	q == id*0.25;
+e3:	ic == q'dot;
+
+end achk;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test124.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test124.ams
new file mode 100644
index 0000000..41f8d26
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test124.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test124.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test124.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this test is to chk the support of ALIAS, NATURE in the PACKAGE
+-- declaration the test also chks the corrct use of quantity and terminal
+-- declarations. 
+--------------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+--entity declaration
+
+use work.electricalsystem.all;
+ENTITY Rckt IS
+END Rckt;
+
+--architecture declaration
+
+ARCHITECTURE aRckt  OF Rckt IS
+
+   terminal T1, T2 : electrical;
+
+   quantity VR across IR through T1 to T2;
+   quantity VR1 across IR1 through T2;
+   quantity VS across T1;
+   constant R : REAL := 10.00;
+
+BEGIN
+
+eqn1    : VR == IR * R;
+e2:	  VR1 == IR1 * R;
+eqn2    : VS == 5.0;
+
+end arckt;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test128.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test128.ams
new file mode 100644
index 0000000..c925366
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test128.ams
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test128.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test104.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this is a test that checks for the correct implementation of if use 
+-- end use. The condition is checked by comparing the quantity against a
+-- known constant value.
+-----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+    --ALIAS GND is electrical'reference;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+	terminal T1, T2:electrical;
+
+quantity vin across T1 to electrical'reference;
+constant a:real:=1.0;
+constant b:real:=2.0;
+
+quantity vin1 across iin1 through T1 to T2;
+quantity vin2 across iin2 through T2 to electrical'reference;
+begin
+
+eq1: vin==5.0* sin(2.0 * 3.141592 *1000.0 * real(time'pos(now))*1.0e-12);
+eq2: vin1== iin1*a;
+eq3: vin2== iin2*b;
+if (vin1>5.0) and (vin1<10.0) use
+e1:	vin1==vin/a;
+elsif (vin2<5.0) use
+e2:	vin2==vin/b;
+else 
+e3: 	vin1==vin;
+end use;
+end atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test136.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test136.ams
new file mode 100644
index 0000000..275aa7a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test136.ams
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test136.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test136.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+-- Last modified :
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A resistor bridge network...
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture mesh of test is
+
+terminal t1, t2, t4 : electrical;
+quantity v1 across i1 through t1 to t2;
+quantity v2 across i2 through t2;
+quantity v3 across i3 through t4;
+quantity v4 across i4 through t1 to t4;
+quantity v5 across i5 through t1;
+quantity vs across t1;
+
+begin
+
+e1:	v1== i1*10.0;
+e2:	v2== i2*10.0;
+e3:	v3== i3*10.0;
+e4:	v4== i4*10.0;
+e5:	v5== i5*20.0;
+
+esource: vs== 10.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-15);
+
+end architecture mesh;
+
+
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test141.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test141.ams
new file mode 100644
index 0000000..215384d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test141.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test141.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test141.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+-- this is the behavioral model of a simple error amplifier.
+-- the entity consists of a quatity port and the architecture consists 
+-- of a simple simultaneos statement
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+--    subtype voltage is real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity ErrorAmplifier is 
+  generic( Gain : REAL := 10.0 -- amplifier gain 
+         ); 
+  port( terminal P_T,N_T: electrical; -- analog input pins 
+        quantity Vout : out real      -- analog output 
+      ); 
+end entity ErrorAmplifier; 
+
+architecture Behavior of ErrorAmplifier is 
+
+quantity DeltaV across P_T through N_T; -- differential input voltage 
+begin 
+e1:  DeltaV== 1.0* sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+e2:  Vout == Gain*DeltaV; 
+
+end architecture Behavior; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test145.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test145.ams
new file mode 100644
index 0000000..ff7ecdb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test145.ams
@@ -0,0 +1,359 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test145.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test145.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : June 2001
+----------------------------------------------------------------------
+-- Description :
+--this is a mos model. It tests for the correctness of the procedural
+--statement.
+--
+--the model accepts the mos data as generic constants. The terminals
+--are defined as of nature electrical.
+--it also tests the alias declaration for real'low.
+--Charges associated with the 4 terminals are declared as quantities.
+--The voltage associated with each of them is also defined.
+--a signal is used to drive i.e to carry out a generic initialization.
+--The various mos equations are evaluated depending on the conditions.
+--The equations for charges and currents are evaluated.
+----------------------------------------------------------------------
+
+package mosdata is 
+  NATURE electrical is real across real through;
+  FUNCTION SIN(X : real) RETURN real;
+  FUNCTION EXP(X : real) RETURN real;
+  FUNCTION SQRT(X : real) RETURN real;
+  FUNCTION POW(X,Y : real) RETURN real;
+  alias undefined is real'low; 
+  constant Temperature: real:=27.0;
+  constant eps0 : real :=8.85418e-12; 
+  constant Ni : real :=1.45e16; 
+  constant Boltzmann : real :=1.380662e-23; 
+  constant echarge: real :=1.6021892e-19; 
+  constant epsSiO2 : real :=3.9*eps0; 
+  constant epsSi : real :=11.7*eps0; 
+  constant kTQ : real :=Boltzmann*temperature/echarge; 
+  constant pi: real := 3.14159;  
+end package mosdata; 
+
+use work.mosdata.all; 
+entity mos is 
+
+  generic( 
+    width  : real:=1.0E-4; 
+    length : real:=1.0E-4;  
+    channel: real :=1.0;
+    kp :real:= 2.0E-5; 
+    gamma :undefined; 
+    phi   :undefined; 
+    tox   :real:= 1.0E-7;
+    nsub  :real:= 0.0;
+    nss   :real:=0.0; 
+    nfs   :real:= 0.0; 
+    tpg   :real:= 1.0; 
+    xj    :real:=0.0; 
+    ld    :real:= 0.0; 
+    u0    :real:= 600.0; 
+    vmax  :real:=0.0;
+    xqc   :real:= 1.0; 
+    kf    :real:=0.0; 
+    af    :real:=1.0; 
+    fc    :real:=0.5; 
+    delta :real:=0.0; 
+    theta :real:=0.0; 
+    eta   :real:=0.0;
+    Sigma :real:=0.0;
+    kappa :real:=0.2 );
+
+  port ( terminal  drain,  gate,  source,  bulk  : electrical); 
+
+end entity mos; 
+
+architecture amos of mos is 
+  quantity Qc, Qb, Qg: real;
+  quantity Qcq, Qbq, Qgq : real; -- channel, bulk and gate charges 
+  quantity Vdsq across drain to source; 
+  quantity Vgsq across gate to source; 
+  quantity Vbsq across bulk to source; 
+  quantity Idq through drain; 
+  quantity Igq through gate; 
+  quantity Isq through source; 
+  quantity Ibq through bulk; 
+
+  signal Initialized: boolean; -- use a signal as generic initialisation 
+
+begin 
+  MOSeqns: procedural is 
+     variable 
+	cox,vt,beta,sigma,nsub,Phi,Gamma,nss,ngate,A,B,C,D,Vfb,fshort, 
+        wp,wc,sqwpxj,vbulk,delv,vth,Vgstos, Vgst, 
+	Ueff,Tau,Vsat,Vpp,fdrain, 
+        stfct,leff,xd,qnfscox,fn,dcrit,deltal,It,Ids,R,Vds,Vgs,Vbs, 
+        forward ,egfet,fermig, mobdeg: real;
+  begin -- procedural statements 
+
+    if not Initialized then 
+      if tox<=0.0 then 
+        cox:=epsSiO2/1.0e-7; 
+      else 
+        cox:=epsSiO2/tox; 
+      end if; 
+
+      if kp = 0.0 then 
+        beta:=cox*u0; 
+      else 
+        beta:=kp; 
+      end if; 
+
+     nsub := nsub * 1.0e6;  -- scale nsub to SI units 
+  
+      if (phi = undefined) then 
+        if (nsub > 0.0) then
+		if (0.1<2.0*KTQ*(nsub/Ni)) then 
+          	Phi:=(2.0*kTQ*(nsub/Ni));
+		else
+		Phi:=0.1;
+		end if; 
+        else 
+          Phi:=0.6; 
+        end if; 
+      else 
+        Phi:=phi; 
+      end if;
+  
+      if (gamma = undefined) then 
+        if (nsub > 0.0) then 
+          Gamma:=sqrt(2.0*epsSi*echarge*nsub)/cox; 
+        else 
+          Gamma:=0.0; 
+        end if; 
+      else 
+        Gamma:=gamma; 
+      end if;
+
+      nss:=nss*1.0e4;              -- Scale to SI 
+      ngate:=gamma*1.0e4;           -- Scale to SI 
+
+      leff:=length-2.0*ld; 
+      if leff>0.0 then 
+        Sigma:= eta * 8.15e-22/(cox*leff*leff*leff); 
+      else 
+        Sigma:=0.0; 
+      end if; 
+
+      if nsub>0.0 then -- N.B. nsub was scaled, above. 
+        xd:=sqrt(2.0*epsSi/(echarge*nsub)); 
+      else 
+        xd:=0.0; 
+      end if; 
+
+      if (nfs>0.0) and(cox>0.0) then 
+        qnfscox:=echarge*nfs/cox; 
+      else 
+        qnfscox:=0.0; 
+      end if; 
+
+      if cox>0.0 then 
+        fn:=delta*pi*epsSi*0.5/(cox*width); 
+      else 
+        fn:=delta*pi*epsSi*0.5*tox/epsSiO2; 
+      end if; 
+
+      --Scale beta and convert cox from Fm^-2 to F 
+      beta:=beta*width/leff; 
+      cox:=cox*width*leff; 
+
+      Initialized <= true; 
+    end if; -- not initialized 
+
+    Vds:=channel*Vdsq; 
+    if Vds>=0.0 then 
+        Vgs:=channel* Vgsq; 
+        Vbs:=channel* Vbsq; 
+        forward:=1.0; 
+    else 
+        Vds:=-Vds; 
+        Vgs:=channel* Vgsq; 
+        Vbs:=channel* Vbsq; 
+        forward:=-1.0; 
+    end if; 
+
+    if Vbs<=0.0 then 
+        A:=Phi-Vbs; 
+        D:=sqrt(A); 
+    else 
+        D:=2.0*sqrt(Phi)*Phi/(2.0*Phi+Vbs); 
+        A:=D*D; 
+    end if; 
+
+    Vfb:=Vt-Gamma*sqrt(Phi)-Sigma*Vds; 
+    if (xd=0.0) OR (xj=0.0) then 
+        fshort:=1.0; 
+    else 
+        wp:=xd*D; 
+        wc:=0.0631353*xj+0.8013292*wp-0.01110777*wp*wp/xj; 
+        sqwpxj:=sqrt(1.0-(wp*wp/((wp+xj)*(wp+xj)))); 
+        fshort:=1.0-((ld+wc)*sqwpxj-ld)/leff; 
+    end if; 
+
+    vbulk:=Gamma*fshort*D+fn*A; 
+    if nfs=0.0 then 
+        delv:=0.0; 
+    else 
+        delv:=kTQ*(1.0+qnfscox+vbulk*0.5/A); 
+    end if; 
+
+    vth:=Vfb+vbulk; 
+    Vgstos:=Vgs-Vfb;
+
+    if (vgs-vth > delv) then  
+        Vgst:=Vgs-vth;
+    else
+        Vgst:= delv;
+    end if;
+ 
+    if (vgs>=vth) or (delv/=0.0) then 
+
+      if (Vbs<=0.0) or (Phi /= 0.0) then 
+          B:=0.5*Gamma/D+fn; 
+      else 
+          B:=fn; 
+      end if; 
+
+      mobdeg:=1.0/(1.0+theta*Vgst); 
+   
+      if (vmax /=0.0) then 
+         Ueff:=u0*mobdeg; 
+          Tau:=Ueff/Leff*vmax; 
+      else 
+          Tau:=0.0; 
+      end if; 
+
+      Vsat:=Vgst/(1.0+B); 
+      Vsat:=Vsat*(1.0-0.5*Tau*Vsat); -- not quite the same as SPICE 
+      if (vds<Vsat) then
+	Vpp:=vds;
+      else
+	Vpp:= Vsat;
+      end if;
+
+      fdrain:=1.0/(1.0+Tau*Vpp); 
+      if (Vgs<vth+delv) and (nfs>0.0) then 
+        stfct:=exp((Vgs-vth-delv)/delv); 
+      else 
+          stfct:=1.0; 
+      end if; 
+
+      if Vds>=Vsat then 
+        if (kappa>0.0) and (xd>0.0) then 
+
+          if vmax=0.0 then 
+              deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)); 
+          else 
+              dcrit:=(xd*xd*vmax*0.5)/(Ueff*(1.0-fdrain)); 
+              
+	      deltal:=sqrt(kappa*xd*xd*(Vds-Vsat)+dcrit*dcrit)-dcrit; 
+          end if; 
+
+          if deltal<=0.5*Leff then 
+              C:=Leff/(Leff-deltal); 
+          else 
+              C:=4.0*deltal/Leff; 
+          end if; 
+
+        else 
+            C:=1.0; 
+        end if; 
+
+      else 
+          C:=1.0; 
+      end if; 
+
+      It:=Vgst-Vpp*(1.0+B)*0.5; 
+        Beta:=Beta*mobdeg; 
+        Ids:=Beta*Vpp*It*C*fdrain*stfct; 
+    else 
+        -- Cutoff 
+        Ids:=0.0; 
+    end if; -- vgs >= vth 
+
+    if Cox /= 0.0 then 
+        --Charges 
+      if Vgs<=vth then 
+        if Gamma /= 0.0 then 
+          if Vgstos < -A then 
+                Qg:=Cox*(Vgstos+A); -- Accumulation 
+          else 
+                Qg:=0.5*Gamma*Cox*(sqrt(4.0*(Vgstos+A)+Gamma*Gamma-Gamma)); 
+          end if ; -- vgstos <-A 
+        else-- Gamma = 0.0 
+            Qg:=0.0; 
+        end if; -- gamma /= 0 
+          Qb:=-Qg; 
+          Qc:=0.0; 
+      else 
+          -- depletion mode: 
+          R:=(1.0+B)*Vpp*Vpp/(12.0*It); 
+          Qg:=Cox*(Vgstos-Vpp*0.5+R); 
+          Qc:=-Cox*(Vgst+(1.0+B)*(R-Vpp*0.5)); 
+          Qb:=-(Qc+Qg); 
+      end if;
+
+    else 
+        Qg:=0.0; 
+        Qc:=0.0; 
+        Qb:=0.0; 
+    end if; -- cox /= 0 
+
+    -- equations for charges (in a procedural we have assignments to 
+    --quantitites): 
+      Qcq := Qc; 
+      Qgq := Qg; 
+      Qbq := Qb; 
+
+    -- equations for currents: 
+      Idq := channel*forward*Ids+channel*xqc*Qc'dot; 
+      Igq := channel*Qg'dot; 
+      Ibq := channel*Qb'dot; 
+      Isq := -Idq - Igq - Ibq; 
+
+  end procedural; 
+end architecture amos; 
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test146.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test146.ams
new file mode 100644
index 0000000..b4f95a0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test146.ams
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 1998-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test146.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+---------------------------------------------------------------------
+-- Title         : Half Wave Rectifier (Behavioral)
+-- Project       : Mixed signal simulation
+----------------------------------------------------------------------
+-- File          : hwr.vhd (Behavioral)
+-- Author(s)     : Vasudevan Shanmugasundaram(vasu@ececs.uc.edu)
+-- Created       : jan 16 1998
+-- Last modified : jan 16 1998
+----------------------------------------------------------------------
+-- Description : 
+-- Behavioral description of a half wave rectifier circuit in VHDL-AMS
+----------------------------------------------------------------------
+-- Modification history :
+-- 21.11.1997 : created
+----------------------------------------------------------------------
+--     T1   diode D  T2    
+--     o-----|>|-----o-------o       The circuit comprises:
+--     |             |               i)  A diode .
+--    ( )            >R=100ohms      ii) A sinusoidal voltage source.
+--     |Vs = 5sinwt  >               iii)A resistor R.
+--     |             >
+--     |_____________|_______o
+--                   |gnd
+--                 -----
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  COS (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+----------------------------------------------------------------------
+
+USE work.electricalSystem.all;
+
+--entity declaration
+ENTITY hwr IS
+END hwr;
+
+--architecture declaration
+ARCHITECTURE behavior  OF hwr IS
+
+    terminal t1, t2 : electrical;
+    quantity vDiode across iDiode through t1 TO t2;
+    quantity v2 across i2 through t2 TO electrical'reference;
+    quantity vs across t1 TO electrical'reference;
+
+    CONSTANT saturation_current : real := 0.0000000000001;
+    CONSTANT Vt : real := 0.025;
+        
+    CONSTANT BV : real := 100.0;
+    CONSTANT neg_sat : real := -saturation_current;
+    
+BEGIN  -- behavior 
+
+      --diode equations
+      if( vDiode >= (-1.0 * Vt)) USE
+
+        eqn1_1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0);
+      --eqn1_1: iDiode == 100.0 * exp(vDiode);
+    
+      ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use
+
+        eqn1_2:  iDiode == neg_sat;
+      ELSE
+
+        eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 +
+                                    saturation_current);
+      END USE ;
+                                                       
+      --resistor equation
+      eqn2: v2 == 100.0 * i2;
+    
+      --voltage source equation
+      eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 *
+                            real(time'pos(now)) * 1.0e-15 );
+    
+END behavior ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test147.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test147.ams
new file mode 100644
index 0000000..0e07718
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test147.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test147.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test147.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this checks for the corect implementation of the 'dot'dot  and negation
+-- operator implementation for simple simulataeous statements.
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2: real;
+quantity V3: real;
+quantity VS across Isource through T1;
+
+begin
+
+--e1:     I1 == V1'dot * 1.0;
+--e2:     V2 == VS'dot'dot;
+e3:     V3 == VS'dot;
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+e4:     V2 == -V3;
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test148.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test148.ams
new file mode 100644
index 0000000..4645a85
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test148.ams
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test148.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test148.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+-- Last modified :
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks for the correctness of the quantity, terminal, nature 
+-- and package declarations. the terminals are assigned as terminals.
+-- a simple V-R circuit is considered.
+-----------------------------------------------------------------------
+
+PACKAGE electricalsystem IS
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+
+NATURE electrical IS real ACROSS real THROUGH ; --ground reference;
+
+END PACKAGE electricalsystem;
+use work.electricalsystem.all;
+
+ENTITY test IS
+    PORT (TERMINAL p: electrical);
+END ENTITY test;
+
+architecture atest of test is
+quantity vr across ir through p;
+begin
+e2:    vr== ir*10.0;
+end architecture atest;
+
+use work.electricalsystem.all;
+
+entity res is
+end res;
+
+ARCHITECTURE ares OF res IS
+	component test is
+	  port(terminal p:electrical);
+	end component;
+	for all : test use entity work.test(atest);
+	terminal x:electrical;
+	constant freq: real:=10000.0;
+        quantity v across i through x;
+BEGIN
+r1:    test port map(p => x);
+e1:    v == 5.0 * sin(2.0 * 3.14159 * freq * real(time'pos(now))*1.0e-12);
+END ARCHITECTURE ares;
+
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test149.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test149.ams
new file mode 100644
index 0000000..e2b1211
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test149.ams
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test149.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test149.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation of the 
+-- componet declaration. The model consists of 2 resistor models which are 
+-- instantiated.
+
+package electricalSystem is
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity test1 is
+	port (terminal P, N : electrical );
+end entity test1;
+
+architecture behav of test1 is 
+   quantity Vt1 across It1 through P to N;
+begin
+	res1 : Vt1 == It1 * 10.0 ;
+end architecture behav;
+
+use work.electricalsystem.all;
+entity test2 is
+	port (terminal P, N : electrical );
+end test2;
+
+architecture behav of test2 is 
+   quantity Vt2 across It2 through P to N;
+begin
+	res1 : Vt2 == It2 * 100.0 ;
+end behav;
+
+
+use work.electricalsystem.all;
+
+entity resistor_ckt is 
+end resistor_ckt;
+
+architecture ares_ckt of resistor_ckt is
+
+	component test1 is 
+           port (terminal P, N : electrical );
+	end component;
+
+	component test2 is 
+           port (terminal P, N : electrical );
+	end component;
+
+        for all : test1 use entity work.test1(behav);  
+        for all : test2 use entity work.test2(behav);  
+
+	terminal a,b,c,t1,t2 : electrical;
+	quantity vout across iout through t2 to electrical'reference;
+	quantity vs across a to electrical'reference;
+
+begin
+	e1 : test1 port map (P => a, N => b);
+	e2 : test2 port map (P => b, N => c);
+ 	e3 : vout == iout * 1200.0;
+	e4 : test1 port map (P => c, N => t1);
+	e5 : test1 port map (P => t1, N => t2);
+    source : vs  == 5.0 * sin(2.0 * 3.1415 * 10000.0* real(time'pos(now)) * 1.0e-12);
+end architecture ares_ckt;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test150.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test150.ams
new file mode 100644
index 0000000..e36261f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test150.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test150.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test150.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple RC  model...     
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement with 'dot expression on
+-- RHS.  it checks nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;   
+
+architecture atest of test is
+terminal T1,T2:electrical;   
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*10.0; 
+e2:     I2 == 1.0e-12*V2'dot;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test151.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test151.ams
new file mode 100644
index 0000000..cbdb390
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test151.ams
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test151.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test151.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...2 resistors in parallel
+-- the test is done for checking the correct implementation of the simple
+-- simultaneous equation statement with multiple expressions o RHS. 
+-- It checks nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1:electrical;
+quantity V1 across I1 through T1 to electrical'reference;
+quantity V2 across I2 through T1 to electrical'reference;
+quantity VS across T1;
+quantity I12 : real;
+begin
+
+e1:     V1 == I1*10.0;
+e2:     V2 == I2*10.0;
+e3:     I12 == I1+I2;  
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test152.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test152.ams
new file mode 100644
index 0000000..533f315
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test152.ams
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test152.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test150.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple RC  model...     
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement with 'dot expression on
+-- RHS.  it checks nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;   
+
+architecture atest of test is
+terminal T1,T2:electrical;   
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*10.0; 
+e2:     I2 == V2'dot*1.0e-12;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test153.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test153.ams
new file mode 100644
index 0000000..d7f05e5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test153.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test153.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test153.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple model which has a voltage source. 
+-- The output voltage Vout is dependent on the value of vS at that point
+-- of time. If the voltage is below Vref, the output is a 1 else output is
+-- a 0.  the test is done for checking the correct implementation of the
+-- simple simultaneous if statement.it checks nature declaration, terminal
+-- and quantity declarations. 
+
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VS across T1;
+quantity Vout: real;
+constant Vref:real:=5.0;
+begin
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+if (VS <= Vref) use
+e1:	Vout == 1.0;
+else 
+e2:	Vout == 0.0;
+end use;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test154.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test154.ams
new file mode 100644
index 0000000..2199502
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test154.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test154.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test154.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple model which has a voltage source. 
+-- The output voltage Vout is dependent on the value of VS wrt Vref 
+-- If the voltage is below Vref, the output is a 0 else output is a 1.
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous if statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VS across T1;
+quantity Vout: real;
+constant Vref:real:=5.0;
+begin
+
+esource: VS == 5.0;
+
+if (VS<=Vref) use
+e1:	Vout == 1.0;
+else 
+e2:	Vout == 0.0;
+end use;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test155.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test155.ams
new file mode 100644
index 0000000..9843d2c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test155.ams
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test155.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test155.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple model which has a voltage source. 
+-- The output voltage Vout is dependent on the value of VS wrt Vref
+-- If the voltage is above/below Vref, the output is a 0 else output is a
+-- 1.  the test is done for checking the correct implementation of the
+-- simple simultaneous if statement with multiple if conditions.it checks
+-- nature declaration, terminal and quantity declarations. 
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VS across T1;
+quantity Vout: real;
+constant Vref:real:=5.0;
+begin
+
+esource: VS == 5.0;
+
+if (VS<Vref) use
+e1:	Vout == 0.0;
+elsif (VS=Vref) use  
+e2:	Vout == 1.0;
+else 
+e3:	Vout == 0.0;
+end use;
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test156.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test156.ams
new file mode 100644
index 0000000..8837429
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test156.ams
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test156.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- check the implemetatio of ports and generics.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity inv is
+  port (
+    x : in bit;
+    xout : out bit); 
+end inv;
+ 
+architecture inverter  of inv is
+begin 
+ 
+  xout <= not x after 100ns ;
+ 
+end inverter ;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity resistor is
+        generic ( res : real := 10.0 ) ;
+        port (terminal P, N : electrical );
+end resistor;
+ 
+architecture behav of resistor is
+   quantity VPTON across IPTON through P to N;
+begin
+        res1 : VPTON == IPTON * res ;
+end behav;
+
+use work.electricalSystem.all;
+
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+  component inv is
+  port (
+    x : in bit;
+    xout : out bit);
+   end component ;
+   for all : inv use entity work.inv(inverter) ;
+
+   component resistor is
+           generic ( res : real := 10.0 ) ;
+           port (terminal P, N : electrical );
+        end component;
+        for all : resistor use entity work.resistor(behav);
+ 
+  terminal n1,n2 : electrical;
+  QUANTITY vIn ACROSS iIn THROUGH n1 ;
+
+  signal y:bit:='0';
+
+BEGIN
+
+   D2 : inv  port map(x=>y, xout=>y);       
+
+ testbench:PROCESS
+    BEGIN
+        WAIT ON y;
+    END PROCESS;
+
+  R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); 
+  R2 : resistor port map (P => n2, N => ground); 
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test157.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test157.ams
new file mode 100644
index 0000000..f13d5c4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test157.ams
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test157.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- check the implemetation of ports and generics.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+--entity inv is
+--  port (
+--    x : in bit;
+--    xout : out bit); 
+--end inv;
+ 
+--architecture inverter  of inv is
+--begin 
+ 
+--  xout <= not x after 100ns ;
+ 
+--end inverter ;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND reference;
+    FUNCTION SIN (X : real ) RETURN real;
+    FUNCTION EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalSystem.all;
+
+entity resistor is
+        generic ( res : real := 10.0 ) ;
+        port (terminal P, N : electrical );
+end resistor;
+ 
+architecture behav of resistor is
+   quantity VPTON across IPTON through P to N;
+begin
+        res1 : VPTON == IPTON * res ;
+end behav;
+
+use work.electricalSystem.all;
+
+ENTITY circuit1 IS
+END circuit1;
+
+ARCHITECTURE behavior OF circuit1 IS
+--  component inv is
+--  port (
+--    x : in bit;
+--    xout : out bit);
+--   end component ;
+--   for all : inv use entity work.inv(inverter) ;
+
+   component resistor is
+           generic ( res : real := 10.0 ) ;
+           port (terminal P, N : electrical );
+        end component;
+        for all : resistor use entity work.resistor(behav);
+ 
+  terminal n1,n2 : electrical;
+  QUANTITY vIn ACROSS iIn THROUGH n1 ;
+
+--  signal y:bit:='0';
+
+BEGIN
+
+--   D2 : inv  port map(x=>y, xout=>y);       
+
+-- testbench:PROCESS
+--   BEGIN
+--        WAIT ON y;
+--    END PROCESS;
+
+  R1 : resistor generic map ( res => 500.0) port map (P => n1, N => n2); 
+  R2 : resistor port map (P => n2, N => ground); 
+  vsource: vIn == 5.0 * sin(2.0 * 3.14 * 100000.0 * real(time'pos(now)) *  1.0e-15);
+
+END ARCHITECTURE behavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test161.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test161.ams
new file mode 100644
index 0000000..1a0542e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test161.ams
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test161.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test150.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple RC  model...     
+-- the test is done for checking the correct implementation
+--of the simple simultaneous equation statement with 'dot expression on RHS.
+--it checks nature declaration, terminal and quantity declarations. 
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;   
+
+architecture atest of test is
+terminal T1,T2:electrical;   
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*10.0; 
+e2:     V2 == I1'integ/1.0e-12;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test162.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test162.ams
new file mode 100644
index 0000000..dbc7b3b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test162.ams
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test162.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test147.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- this checks for the corect implementation of the 'dot'dot  and negation
+-- operator implementation for simple simulataeous statements
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2: real;
+quantity i2 :real;
+quantity VS across Isource through T1;
+
+begin
+
+e1:     I1 == V1'dot*1.0e-15;
+e2:     V2 == V1'dot;
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test163.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test163.ams
new file mode 100644
index 0000000..034a02a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test163.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test163.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test162.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple rc model...with 2 res in parallel connected thru a capacitor
+-- -------------||-----
+--           |        |
+--           | R      | R
+-- --------------------		
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal, 'dot and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VR1 across IR1 through T1;
+quantity VC across IC through T1 to T2;
+quantity VR2 across IR2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     VR1 == IR1*100.0;
+e2:     IC  == VC'dot *1.0e-12;
+e3:     VR2 == IR2*10.0;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test164.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test164.ams
new file mode 100644
index 0000000..ca33cd6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test164.ams
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test164.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : test164.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple rc model...with 2 res in parallel connected thru a capacitor
+-- -------------||-----
+--           |        |
+--           | R      | R
+-- --------------------		
+-- the test is done for checking the correct implementation of the simple
+-- simultaneous equation statement.it checks nature declaration, terminal,
+-- 'dot, 'integ and quantity declarations. 
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VR1 across IR1 through T1;
+quantity VC across IC through T1 to T2;
+quantity VR2 across IR2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     VR1 == IR1*100.0;
+e2:     IC  == VC'dot *1.0e-12;
+e3:     VR2 == IR2*10.0;
+e4:     VC == IC'integ/1.0e15
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test165.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test165.ams
new file mode 100644
index 0000000..d3fd1b0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test165.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test165.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distributed Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test164.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple rl model...
+-- -----^^^-------------
+--       R   |        >
+--           | L      > R
+-- --------------------		
+-- the test is done for checking the correct implementation
+-- of the simple simultaneous equation statement.it checks
+-- nature declaration, terminal, 'dot, and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VR1 across IR1 through T1 to T2;
+quantity VL across IL through T2;
+quantity VR2 across IR2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     VR1 == IR1*10.0;
+e2:     VL  == IL'dot *1.0;
+e3:     VR2 == IR2*10.0;
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test166.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test166.ams
new file mode 100644
index 0000000..d84a804
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test166.ams
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test166.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test166.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple rl model...
+-- -----^^^-------------
+--       R   |        >
+--           | L      > R
+-- --------------------		
+-- the test is done for checking the correct implementation
+--of the simple simultaneous equation statement.it checks
+--nature declaration, terminal, 'dot,'integ and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity VR1 across IR1 through T1 to T2;
+quantity VL across IL through T2;
+quantity VR2 across IR2 through T2;
+quantity VS across T1;
+
+begin
+
+e1:     VR1 == IR1*10.0;
+e2:     VL  == IL'dot *1.0;
+e3:     VR2 == IR2*10.0;
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+e4:	IL== 1.0* VL'integ;
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test167.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test167.ams
new file mode 100644
index 0000000..def01db
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test167.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test167.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test167.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- An RC model...
+-- the test is done for checking the correct implementation of the simple
+-- simultaneous equation statement.it checks nature declaration, terminal,
+-- 'dot, 'integ and quantity declarations. 
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2, T3, T4:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2 to T3;
+quantity VC across IC through T3;
+quantity VC1 across IC1 through T2 to T4;
+quantity V3 across I3 through T4;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*1.0;
+e2:     V2 == I2*1.0;
+e3:     V3 == I3*10.0;
+e4:     IC == VC'dot*1.0e-12;
+e5:	IC1 == VC1'dot*1.0e-12;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test168.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test168.ams
new file mode 100644
index 0000000..bf9e9af
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test168.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test168.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test168.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- An RC model...
+-- the test is done for checking the correct implementation
+--of the simple simultaneous equation statement.it checks
+--nature declaration, terminal, 'dot, 'integ and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2, T3, T4:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2 to T3;
+quantity VC across IC through T3;
+quantity VC1 across IC1 through T2 to T4;
+quantity V3 across I3 through T4;
+quantity VS across T1;
+
+begin
+
+e1:     V1 == I1*1.0;
+e2:     V2 == I2*1.0;
+e3:     V3 == I3*10.0;
+e4:     VC == IC'integ*1.0e12;
+e5:	VC1 == IC1'integ*1.0e12;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test169.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test169.ams
new file mode 100644
index 0000000..18804f4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test169.ams
@@ -0,0 +1,143 @@
+
+-- Copyright (C) 1999-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test169.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-----------------------------------------------------------------------------
+--  Ebers-moll Model for a transistor                             --
+--  VHDL-AMS Implementation                                       --
+--  Developed at the Distributed Processing Lab at the University --
+--  of Cincinnati                                                 --
+--  by VishwaShanth Kasula on May 10, 1999                        --
+--------------------------------------------------------------------
+--  Circuit Topology                                              --
+--  BJT Ebers-Moll static model
+--  Testbench Ckt to evaluate the DC operatioing point of an npn BJT,
+--  Sedra smith page no. 152, fig 4.9
+--------------------------------------------------------------------
+
+-- Three regions are simulated
+-- Active region, vbb = 4.0 V
+-- Saturation region, vbb = 6.0 V
+-- Cutoff region, vbb = 0.0;
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity bjt_npn is
+  generic(isat : real := 1.0e-16;         -- Saturation Current
+          bf   : real := 100.0;           -- Ideal maximus forward current
+          br   : real := 1.0;             -- ideal maximum reverse current
+          rb   : real := 1.0e-5;          -- Base resistance
+          rc   : real := 1.0e-5;          -- collector resistance
+          re   : real := 1.0e-5;          -- emmiter resistance
+          vaf  : real := 100.0);          -- Forward Early Voltage
+  port(terminal e,b,c : electrical);
+end bjt_npn;
+
+architecture structure of bjt_npn is
+  terminal b1, c1, e1 : electrical;
+  quantity vbo across ib through b to b1;
+  quantity vco across ic through c to c1;
+  quantity veo across ie through e to e1;
+  quantity vct across Ict through c1 to e1;--current source
+  quantity vbe across ibe through b1 to e1;
+  quantity vbc across ibc through b1 to c1;
+  quantity vce : real := 1.0;           -- used to calculate VCE
+  constant gmin : real := 1.0e-12;      -- condutsnce in parallel with every pn junction
+  constant vt : real := 0.02589; -- thermal voltage
+ 
+begin
+  brk : break vbe => 1.0, vbc => -1.0;
+
+  diodecond1 : if(vbe > -5.0*vt) use
+    diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf;
+  elsif (vbe <= -5.0*vt ) use
+    diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf;
+  end use;
+  diodecond2 : if(vbc > -5.0*vt) use
+    diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br;
+  elsif(vbc <= -5.0*vt) use
+    diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br;
+  end use;
+  bres : vbo == ib * 1.0e-6;
+  cres : vco == ic * 1.0e-6;
+  eres : veo == ie * 1.0e-6;
+  kcl_eqn : ie == -1.0*(ib + ic);
+  vcevolt : vce == vbe - vbc;
+  ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf));
+  
+end architecture structure;
+
+
+--*****************************************************
+--TEST BENCH
+use std.textio.all;
+use work.electricalsystem.all;
+
+entity bjt_testbench is
+end bjt_testbench;
+
+architecture structure of bjt_testbench is
+  terminal t1, t2, t3, t4 : electrical ;
+  component bjt_npn_comp
+    generic(isat : real := 1.0e-16;         -- Saturation Current
+            bf : real := 100.0;           -- Ideal maximus forward current
+            br : real := 1.0;             -- ideal maximum reverse current
+            rb : real := 1.0e-5;          -- Base resistance
+            rc : real := 1.0e-5;          -- collector resistance
+            re : real := 1.0e-5;          -- emmiter resistance
+            vaf : real := 100.0);         -- Forward Early Voltage
+    port(terminal e,b,c : electrical);	  
+  end component;
+  for all : bjt_npn_comp use entity work.bjt_npn(structure);
+  
+  quantity vcc across icc through t1 to electrical'reference;
+  quantity vrc across irc through t1 to t2;
+  quantity vbb across ibb through t3 to electrical'reference;
+  quantity vre across ire through t4 to electrical'reference;
+  
+begin
+   
+   bjt : bjt_npn_comp
+     generic map (isat => 1.8104e-15, vaf => 100.0)
+     port map(t4,t3,t2);
+   emres : vre == ire * 3.3e3;
+   ccurr : vcc == 10.0;
+   ecurr : vbb == 6.0;
+   cores : vrc == irc * 4.7e3;
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test170.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test170.ams
new file mode 100644
index 0000000..ab30845
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test170.ams
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test170.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test106.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation 
+-- of the simple simultaneous equation statement.it checks 
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2, T3, T4,T5,T6:electrical;
+quantity VRgen across IRgen  through T1 to T2;
+quantity VLgen across ILgen through T2 to T3;
+quantity VRin across IRin through T3; 
+quantity VR1 across IR1 through T4 to T5;
+quantity VR1A across IR1A through T4 to T6;
+quantity VC1A across IC1A through T6 to T5;
+quantity VC1 across IC1 through T5;
+quantity VS across T1;
+constant C1: real:=3.5e-3;
+constant C1A: real:=0.3e-3;
+begin
+
+e1:     VRgen == IRgen*10.0;
+e2:     VLgen == 0.5*ILgen'dot;
+e3:     VRin == IRin*500.0;
+e4:	VR1 == IR1*1.0;
+e5:	VR1A == IR1A*0.2;
+e6:	VC1 == C1 /IC1'integ;
+e7:	VC1A == C1A/IC1A'integ;
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test172.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test172.ams
new file mode 100644
index 0000000..d000ef4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test172.ams
@@ -0,0 +1,97 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test172.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test172.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the simultaneous if equation statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+port (input: in bit;
+      output: out bit);
+end entity;
+
+architecture atest of test is
+terminal t1, t2: electrical;
+quantity v1 across i1 through t1 to t2;
+quantity v2 across t2;
+begin
+
+e1: v1== 1.0;
+e2: v2==0.0;
+
+	if (v1==1.0) use
+	  output <= '1';
+	else
+	  output <='0';
+	end use;
+
+	if (v2==2.0) use
+	   output <='0';
+	else
+	   output <='1';
+	end use;
+end architecture atest;
+use work.electricalSystem.all;
+--entity tb is 
+--port (tinput: in bit;
+--      toutput: out bit);
+--end entity;
+--architecture atb of tb is
+--terminal tt1, tt2: electrical;
+--quantity tv1 across ti1 through tt1 to tt2;
+--quantity tv2 across tt2;
+--begin
+
+--tv1==1.0;
+--tv2==0.0;
+
+--end architecture atb;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test173.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test173.ams
new file mode 100644
index 0000000..9dc65ca
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test173.ams
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test173.ams,v 1.1 2002-03-27 22:11:19 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test173.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the simultaneous if equation statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal t1, t2: electrical;
+quantity v1 across i1 through t1 to t2;
+quantity v2 across t2;
+
+begin
+e1: v1== 1.0;
+e2: v2==0.0;
+
+	if (v1==1.0) use
+	  output <= '1';
+	end use;
+
+	if (v2==2.0) use
+	   output <='1';
+	end use;
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test174.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test174.ams
new file mode 100644
index 0000000..a262a8e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test174.ams
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test174.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test174.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation
+--of the simultaneous case statement.it checks
+--nature declaration, terminal and quantity declarations
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference ;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+USE work.electricalSystem.all;
+
+ENTITY simcase IS
+END simcase;
+
+ARCHITECTURE asimcase OF simcase IS
+
+    terminal T1, T2 : electrical;
+
+    quantity v1 across i1 through T1 ;
+    quantity v2 across i2 through T1 to T2;
+    quantity v3 across i3 through T2 ;
+
+BEGIN  
+
+      eqn1 : v1 == 1.0;
+	     
+c1:	case (v1*2.0) use
+       
+            when (2.0) => 
+                       v2 == i2 * 100.0;
+                       v3 == i3 * 100.0;
+            when (6.0) =>
+                       v2 == i2 * 200.0;
+                       v3 == i3 * 200.0;
+            when (10.0) =>
+                       v2 == i2 * 300.0;
+                       v3 == i3 * 300.0;
+            when others =>
+			v2 == i2 * 400.0;
+			v3 == i3 * 400.0;
+     end case c1; 
+
+END asimcase ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test175.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test175.ams
new file mode 100644
index 0000000..4db174b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test175.ams
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test175.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test175.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the simultaneous case statement.it checks
+-- nature declaration, terminal and quantity declarations
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference ;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+
+USE work.electricalSystem.all;
+
+ENTITY simcase IS
+END simcase;
+
+ARCHITECTURE asimcase OF simcase IS
+
+    terminal T1, T2 : electrical;
+
+    quantity v1 across i1 through T1 ;
+    quantity v2 across i2 through T1 to T2;
+    quantity v3 across i3 through T2 ;
+
+BEGIN  
+
+      eqn1 : v1 == 1.0;
+      eqn2 : v2 == 2.0;	     
+c1:	case (v1*2.0) use
+       
+            when (2.0) use 
+                       if (v2==2.0) use
+			v2 == i2 * 100.0;
+		       else
+			v2 ==i2*10.0;
+            	       end use;
+	    when (6.0) use
+                       v2 == i2 * 200.0;
+            when (10.0) use
+                       v2 == i2 * 300.0;
+	end case c1;
+END asimcase ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test176.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test176.ams
new file mode 100644
index 0000000..90fd653
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test176.ams
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test176.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test176.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+--of the simultaneous null statement.it checks
+--nature declaration, terminal and quantity declarations.
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2;
+--quantity V3 across I3 through T2;
+quantity VS across T1;
+
+begin
+
+	V1==1.0;
+	if (V1<=1.1) use
+	   NULL;
+	else
+          V2 == 1.0;
+        end use;
+
+
+esource: VS == 5.0 * sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
+
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test182.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test182.ams
new file mode 100644
index 0000000..ee24ac1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test182.ams
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test182.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati 
+----------------------------------------------------------------------
+-- File          : test182.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001  
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test is done for checking the correct implementation
+-- of the 'above attribute.
+                   
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+                
+        
+USE work.electricalSystem.all;
+
+entity test is 
+port(signal vout:out boolean);
+end entity;
+
+architecture atest of test is
+
+terminal T1: electrical;
+quantity vin across iin through T1;
+--constant vt: real:=3.0;
+begin
+e2 : vout <= vin'above(0.0);
+e1:  vin == 5.0 * sin(2.0 *3.141592 *100000.0 * real(time'pos(now))*1.0e-12);
+
+end architecture atest;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams
new file mode 100644
index 0000000..f0ea59d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test183.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+-- this model tests for the correst implementation of the 'above 
+-- statement.
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION SIN(X : real) RETURN real;
+    alias ground is electrical'reference;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+
+entity product is 
+generic(bound:real:=1.0);
+port(
+     quantity out1:real);
+end product;
+
+architecture pro of product is
+constant in1:real:=10.0;
+constant in2:real:=1.0;
+signal outofbound:out boolean;
+
+begin
+	outofbound<=true;
+	out1== in1*in2;
+	outofbound<=out1'above(bound);
+
+end pro;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test184.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test184.ams
new file mode 100644
index 0000000..300528f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test184.ams
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2001-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test184.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+---------------------------------------------------------------------
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File          : test100.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- half wave Rectifier model ...
+-- the test is done for checking the correct implementation
+-- of the simultaneous if statement.it checks
+-- nature declaration, terminal and quantity declarations.
+
+----------------------------------------------------------------------
+--     T1   diode D  T2    
+--     o-----|>|-----o-------o       The circuit comprises:
+--     |             |               i)  A diode .
+--    ( )            >R=100ohms      ii) A sinusoidal voltage source.
+--     |Vs = 5sinwt  >               iii)A resistor R.
+--     |             >
+--     |_____________|_______o
+--                   |gnd
+--                 -----
+----------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+----------------------------------------------------------------------
+
+USE work.electricalSystem.all;
+
+ENTITY hwr IS
+END hwr;
+
+ARCHITECTURE ahwr OF hwr IS
+
+    terminal T1, T2 : electrical;
+    quantity VDiode across IDiode through T1 to T2;
+    quantity V2 across I2 through T2 to electrical'reference;
+    quantity VS across T1 to electrical'reference;
+
+    CONSTANT saturation_current : real := 0.0000000000001;
+    CONSTANT Vt : real := 0.025;
+        
+    CONSTANT BV : real := 100.0;
+    CONSTANT neg_sat : real := -saturation_current;
+    
+BEGIN  
+
+      --diode equations
+      if( vDiode >= (-1.0 * Vt)) USE
+        eq1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0);
+
+      ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use
+        eq2:  iDiode == neg_sat;
+
+      ELSE
+        eq3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 +
+                                    saturation_current);
+      END USE ;
+                                                       
+      eqn2: v2 == 100.0 * i2;
+    
+      eqn4: vs == 5.0 * sin(2.0 * 3.14 * 100000.0 *
+                            real(time'pos(now)) * 1.0e-15 );
+    
+END ahwr ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test185.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test185.ams
new file mode 100644
index 0000000..6b5abf2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test185.ams
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test185.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH GROUND REFERENCE;
+    FUNCTION  SIN (X : real ) RETURN real;
+    FUNCTION  EXP  (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+USE work.electricalSystem.all;
+
+ENTITY simcase IS
+END simcase;
+
+ARCHITECTURE asimcase OF simcase IS
+
+    terminal T1: electrical;
+
+    quantity v1 across i1 through T1 ;
+
+BEGIN  
+	eq1: v1==1.0;
+	if (v1<=1.0) use	
+		e1: null;
+	end use;
+END asimcase ;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/voltage_doubler.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/voltage_doubler.ams
new file mode 100644
index 0000000..4213dbe
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/voltage_doubler.ams
@@ -0,0 +1,227 @@
+
+-- Copyright (C) 1997-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: voltage_doubler.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- Title         : Voltage doubler circuit 
+-- Project       : Mixed signal simulation
+----------------------------------------------------------------------
+-- File          : voltageDoubler.ams
+-- Author        : Kathiresan Nellayappan  <knellaya@ececs.uc.edu>
+--                 Chandrashekar L Chetput <cchetput@ececs.uc.edu>
+-- Created       : 26.11.1997
+----------------------------------------------------------------------
+-- Description :
+-- VHDL-AMS description of a voltage doubler circuit
+-- STRUCTURAL DESCRIPTION.
+----------------------------------------------------------------------
+--
+-- The ciruit schematic for the voltage doubler circuit is as below:
+-- =================================================================
+--      
+--  T1       C1      T2   diode D2    T3
+--  o_________||_____o_____|<|________o_____o_  The circuit comprises:
+--  |         ||     |                |        i)A sinusoidal voltage
+--  |        1microF |                |                    source.
+-- ( )               __             _____     ii)  2 capacitors.
+--  |Vs              \/diode        ----- C2 = 1microF iii) 2 diodes.
+--  |=10sinwt        -- D1            |                  
+--  |                |                |
+--  |                |                |
+--  o________________|________________|_____o_
+--                           |gnd
+--                         -----
+-- The diode is modelled as a component and then instantiated twice.
+-- The diode model used is a spice behavioral model of a real diode.
+-- 
+----------------------------------------------------------------------
+
+
+--Package defining eleectrical nature and some functions...
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+END PACKAGE electricalSystem;
+
+----------------------------------------------------------------------
+-- The diode component definition.....
+USE work.electricalSystem.ALL;
+
+----------------------------------------------------------------------
+-- Schematic of the diode component:
+-- 
+--        Ta o----|>|----o Tb
+--
+----------------------------------------------------------------------
+
+ENTITY diodeReal IS
+  PORT( TERMINAL ta,tb : electrical);
+END diodeReal;
+
+
+ARCHITECTURE behavior OF diodeReal IS
+  
+  QUANTITY d_V ACROSS d_I THROUGH ta TO tb;
+  CONSTANT saturation_current : real := 0.0000000000001;
+  CONSTANT Vt : real := 0.025;
+  CONSTANT neg_sat : real := -saturation_current; 
+  CONSTANT IBV : real := 0.001;
+  CONSTANT  PI :  real := 3.14159_26535_89793_23846;  
+  CONSTANT BV : real := -100.0;
+
+BEGIN
+
+  IF( d_V >= ((-5.0) * Vt) ) USE 
+    diode1St1:   d_I == saturation_current * (exp(d_V/Vt) - 1.0);
+  ELSIF( (d_V < ((-5.0) * Vt)) AND (d_V > BV)) USE
+    diode1St2:    d_I == neg_sat;
+  ELSIF(d_V = BV) USE
+    diode1St3: d_I == -IBV;
+  ELSE
+    diode1St4: d_I == neg_sat * (exp((BV + d_V)/Vt) -1.0 +((-BV)/Vt));
+  END USE;
+
+END ARCHITECTURE behavior;
+
+----------------------------------------------------------------------
+-- The capacitor definition begins.....
+USE work.electricalSystem.ALL;
+----------------------------------------------------------------------
+-- Schematic of the capacitor component:
+-- 
+--        Ta1 o----||----o Tb1
+--
+----------------------------------------------------------------------
+--entity declaration.
+ENTITY capacitor IS
+     --capacitance value given as a generic parameter.
+  GENERIC( C : real := 1.0e-6);
+  PORT( TERMINAL ta1,tb1 : electrical);--Interface ports.
+END capacitor;
+
+--architecture declaration.
+ARCHITECTURE capbehavior OF capacitor IS
+--quantity declarations.
+-- --voltage across and current through  the capacitor.  
+  quantity Vc across Ic through ta1 to tb1;
+                                        
+BEGIN
+
+  Ic == C*Vc'dot; -- The ohmic resistance equation.
+
+END ARCHITECTURE capbehavior;
+----------------------------------------------------------------------
+-- The sinusoidal voltage source definition begins.....
+USE work.electricalSystem.ALL;
+----------------------------------------------------------------------
+-- Schematic of the sinusoidal voltage source:
+-- -------------------------------------------
+--
+--        Ta2 o----(~)----o Tb2 a sinusoidal voltage of amplitude V
+--                  Vs          and frequency 'f'.
+----------------------------------------------------------------------
+--entity declaration.
+ENTITY sineSource IS
+     --frequency value and voltage value given as generic parameters.
+  GENERIC( f : real := 100000.0; 
+	   v : real := 10.0    );
+  PORT( TERMINAL ta2,tb2 : electrical);--Interface ports.
+END sineSource;
+
+--architecture declaration.
+ARCHITECTURE sinebehavior OF sineSource IS
+--quantity declarations.  
+  quantity Vsine across Isine through ta2 to tb2; 
+
+BEGIN
+
+  -- The sinusoidal voltage source equation.
+  vsource: Vsine == V * sin(2.0 * (22.0/7.0) * f *
+                 real(time'pos(now)) * 1.0e-15);
+
+END ARCHITECTURE sinebehavior;
+
+----------------------------------------------------------------------
+--The description of the voltage doubler begins here.....
+
+USE work.electricalSystem.ALL;
+
+ENTITY voltage_doubler IS
+END voltage_doubler;
+
+ARCHITECTURE vdBehavior OF voltage_doubler IS
+
+  TERMINAL t1, t2, t3 : electrical;
+
+  COMPONENT diodeRealComp 
+      PORT(TERMINAL ta,tb : electrical);
+  END COMPONENT;
+
+  FOR ALL : diodeRealComp USE ENTITY work.diodeReal(behavior);
+
+  COMPONENT capacitorComp IS
+  GENERIC( C : real := 1.0e-6);
+  PORT( TERMINAL ta1,tb1 : electrical);
+  END COMPONENT;
+
+  FOR ALL :  capacitorComp USE ENTITY work.capacitor(capbehavior);
+
+  COMPONENT sineSourceComp IS
+  GENERIC( f : real := 100000.0;  
+	   v : real := 10.0    ); 
+  PORT( TERMINAL ta2,tb2 : electrical);
+  END COMPONENT;
+
+  FOR ALL : sineSourceComp USE ENTITY work.sineSource(sinebehavior);
+
+  CONSTANT C : real := 0.000001;
+  CONSTANT  MATH_PI :  real := 3.14159_26535_89793_23846;  
+  
+BEGIN
+
+  C1: capacitorComp
+    PORT MAP(t1,t2);
+  
+  C2: capacitorComp
+    PORT MAP(t3,ground);
+  
+  d1: diodeRealComp
+    PORT MAP(t2,ground);
+  
+  d2: diodeRealComp
+    PORT MAP(t3,t2);
+  
+  vsource: sineSourceComp
+    PORT MAP(t1,ground);
+  
+END ARCHITECTURE vdBehavior;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/wein_bridge.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/wein_bridge.ams
new file mode 100644
index 0000000..5cf47ba
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/wein_bridge.ams
@@ -0,0 +1,463 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: wein_bridge.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+--				REMARKS	
+--				-------
+--  TESTED   : Works great for freq of 1.0 KHz - 30.0MHz
+--  COMMENTS : The Values of R1_a and R1_b have to be 18.0k & 32.0K resp.
+--             The freq. is given by the equation
+--	 			F = 1/(2*PI*R*C)	  
+--					 where R=R3=R4 and
+--					       C=C3=C4.			
+--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+--*************************************************************************
+-- Structural Level Model of a WEIN BRIDGE OSCILLATOR.
+-- VHDL-AMS implementation
+-- Developed at Distributed Processing Laboratory
+-- University of Cincinnati
+--************************************************************************* 
+
+--#########################################################################
+--				 BLOCK DIAGRAM
+--				 -------------
+--			    o V_out	
+--			    |	       D1  
+--			    |__________|\_______________	
+--		R1_a   R1_b |	       |/    R2=10.0K	|
+--	     -----^^^.^^^---o--------/\/\/\/\-----------|
+--	    |	     | T4   |__________/|_______________|		
+--       -------     | 		       \|		|
+--	   --	     |		     D2			|
+--		     |	   		|\   		|
+--                    ------------------|-\		|
+--		     			|  \____________o T3 
+--					|  / 		|
+--		     -------------------|+/		|
+--		    |  			|/		|
+--		    |T1		    T2			|
+--	   _________o__________||____o_____/\/\/\/\_____|
+--	  |	    |	       || 	  
+--	  |	    |       C4=16.0pF	    R4=10.0K 
+--	  |	    <  
+--     C3 |16.0pF   < R3=10.0K		  	
+--	-----	    <
+--	-----       |
+--	  |         |
+--     -------	 -------
+--	 --	   --	
+--
+--#########################################################################
+
+ PACKAGE electricalsystem IS
+     NATURE electrical IS real ACROSS real THROUGH ground reference;
+     FUNCTION SIN(X:real) RETURN real;
+     FUNCTION COS(X:real) RETURN real;
+     FUNCTION EXP(X:real) RETURN real;
+ END PACKAGE electricalsystem;
+
+------------------------ RESISTOR ---------------------------
+ 
+use work.electricalsystem.all;
+ 
+entity resistor is
+ generic(res :real:=1.0 );
+  port(terminal r_in,r_out: electrical);
+end entity resistor;
+  
+architecture behav of resistor is
+   quantity vr across ir through r_in to r_out;
+ 
+begin
+  vr==ir*res;
+end architecture behav;
+ 
+------------------------ CAPACITOR---------------------------
+use work.electricalsystem.all;
+ 
+entity capacitor is
+ generic(cap :real:=1.0);
+ port(terminal c_in,c_out: electrical);
+end entity capacitor;
+ 
+architecture behav of capacitor is
+ 
+quantity vc across ic through c_in to c_out;
+begin
+    init: break vc=>0.0;
+	
+  ic==cap*vc'dot;
+end architecture behav;
+
+---------------------------- Diode -----------------------------
+use work.electricalsystem.all;
+
+entity diode is  
+generic (
+    Isat : real := 1.0e-14;             -- saturatioin current
+    n : real := 1.0;                    -- emmission coefficient
+    bv : real := 1.0;                   -- reverse breakdown voltage
+    ibv : real := 1.0e-3;               -- Breakdown current
+    rds : real := 1.0                   -- Ohnic resistamce 
+    );
+port (terminal pos, neg : electrical);
+end diode;
+
+architecture behav of diode is
+  terminal td : electrical;
+  quantity vd across id through td to neg;
+  quantity vrd across ird through pos to td;
+  quantity vdiode : real := 2.0;
+  constant gmin : real := 1.0e-12;     -- conductance  
+  constant vt : real := 0.026;         -- thermal voltage
+begin  -- behav
+  brk : break vd => 1.0;
+  diodecondition : if(vd >= -5.0*(vt*n)) use
+    dfow : id == ((isat*(exp(vd/(vt*n)) - 1.0)) + (gmin*vd));
+  elsif(vd < -5.0*(vt*n)  and (vd > -1.0*bv)) use
+    drev: id == ((-1.0*isat) + (gmin*vd));
+  elsif vd = -1.0*bv use
+    dbv : id == -1.0*ibv;
+  elsif vd < -1.0*bv use
+    blbv : id == -1.0*Isat*(exp(-1.0*((bv + vd)/vt)) - 1.0 + (bv/vt));
+  end use;
+  diododeres : vrd == ird * rds;
+  diodevolt : vdiode == vd + vrd;
+
+end behav;
+
+-------------------- NPN transistor  ---------------------------
+use work.electricalsystem.all;
+
+entity trans_npn is
+    port( terminal emitter,base,collector : electrical);
+end trans_npn;
+ 
+architecture trans_behav of trans_npn is
+ 
+terminal t1,t2,t3,t4,t5,e,b :electrical; 
+ 
+constant Lb   :real:=0.5e-9;
+constant rb1  :real:=1.0;
+constant rb2  :real:=3.1;
+constant rb3  :real:=2.7;
+constant r_pi :real:=110.0;
+constant c_pi :real:=18.0e-12;
+constant gm   :real:=0.88;
+constant cc1  :real:=0.091e-12;
+constant cc2  :real:=0.048e-12;
+constant cc3  :real:=0.023e-12;
+constant Le   :real:=0.2e-9;
+constant Rbase:real:=22.0;
+constant Remit:real:=0.6;
+ 
+  
+quantity v1   across i1  through  b to t1;
+quantity v2   across i2  through t1 to t2;
+quantity v3   across i3  through t2 to t3;
+quantity v4   across i4  through t3 to t4;
+quantity v_pi across i5  through t4 to t5;
+quantity i6   		 through t4 to t5;
+quantity v7   across i7  through t1 to collector;
+quantity v8   across i8  through t2 to collector;
+quantity v9   across i9  through t3 to collector;
+quantity v10  across i10 through t5 to e;
+quantity v11  across i11 through  collector to t5;
+quantity v_base  across i_base through base to b;
+quantity v_emit  across i_emit through e to emitter;
+ 
+ 
+BEGIN
+
+  v1  ==Lb*i1'dot;
+  v2  ==i2*rb1;
+  v3  ==i3*rb2;
+  v4  ==i4*rb3;
+  v_pi==i5*r_pi;
+  i6  ==c_pi*v_pi'dot;
+  i7  ==cc1*v7'dot;
+  i8  ==cc2*v8'dot;
+  i9  ==cc3*v9'dot;
+  v10 ==Le*i10'dot; 
+  i11 ==gm*v_pi;
+ v_base==rbase*i_base;
+ v_emit==remit*i_emit;
+ 
+end architecture trans_behav;
+ 
+
+-------------------- PNP transistor  ---------------------------
+use work.electricalsystem.all;
+
+entity trans_pnp is
+    port( terminal emitter,base,collector : electrical);
+end trans_pnp;
+ 
+architecture trans_behav of trans_pnp is
+ 
+terminal t1,t2,t3,t4,t5,e,b :electrical; 
+ 
+constant Lb   :real:=0.5e-9;
+constant rb1  :real:=1.0;
+constant rb2  :real:=3.1;
+constant rb3  :real:=2.7;
+constant r_pi :real:=110.0;
+constant c_pi :real:=18.0e-12;
+constant gm   :real:=0.88;
+constant cc1  :real:=0.091e-12;
+constant cc2  :real:=0.048e-12;
+constant cc3  :real:=0.023e-12;
+constant Le   :real:=0.2e-9;
+constant Rbase:real:=22.0;
+constant Remit:real:=0.6;
+ 
+  
+quantity v1   across i1  through t1 to b;
+quantity v2   across i2  through t2 to t1;
+quantity v3   across i3  through t3 to t2;
+quantity v4   across i4  through t4 to t3;
+quantity v_pi across i5  through t5 to t4;
+quantity i6   		 through t5 to t4;
+quantity v7   across i7  through collector to t1;
+quantity v8   across i8  through collector to t2;
+quantity v9   across i9  through collector to t3;
+quantity v10  across i10 through e to t5;
+quantity v11  across i11 through  t5 to collector;
+quantity v_base  across i_base through b to base;
+quantity v_emit  across i_emit through emitter to e;
+ 
+ 
+BEGIN
+
+  v1  ==Lb*i1'dot;
+  v2  ==i2*rb1;
+  v3  ==i3*rb2;
+  v4  ==i4*rb3;
+  v_pi==i5*r_pi;
+  i6  ==c_pi*v_pi'dot;
+  i7  ==cc1*v7'dot;
+  i8  ==cc2*v8'dot;
+  i9  ==cc3*v9'dot;
+  v10 ==Le*i10'dot; 
+  i11 ==gm*v_pi;
+ v_base==rbase*i_base;
+ v_emit==remit*i_emit;
+ 
+end architecture trans_behav;
+ 
+
+--> Constant Voltage source
+---------------------------
+use work.electricalsystem.all;
+ENTITY voltSource IS
+  generic(amp:real:=22.0);
+  PORT( TERMINAL ta2,tb2 : electrical);
+END voltSource;
+ 
+ARCHITECTURE voltbehavior OF voltSource IS
+
+terminal t1: electrical;
+quantity V_volt across i_volt through t1 to tb2;
+quantity V_drop across i_drop through ta2 to t1;
+ 
+BEGIN
+  V_volt == amp;
+  V_drop == i_drop*100.0;
+
+END ARCHITECTURE voltbehavior;
+
+-- ********* Structural Model Of a simple High Frequency OpAmp *********--
+
+use work.electricalsystem.all;
+entity op_amp is
+port(terminal inverting_ip,non_inverting_ip,output :electrical);
+end entity op_amp;
+
+architecture struct of op_amp is
+
+--> components
+
+COMPONENT trans_pnp is
+    port( terminal emitter,base,collector : electrical);
+end component;
+for all : trans_pnp use entity work.trans_pnp(trans_behav);
+
+COMPONENT trans_npn is
+    port( terminal emitter,base,collector : electrical);
+end component;
+for all : trans_npn use entity work.trans_npn(trans_behav);
+
+component resistor is
+generic(res :real:=1.0 );
+port(terminal r_in,r_out: electrical);
+end component;
+for all: resistor use entity work.resistor(behav);
+
+component voltsource is
+generic(amp:real:=22.0);
+PORT( TERMINAL ta2,tb2 : electrical);
+end component;
+for all: voltsource use entity work.voltsource(voltbehavior);
+
+terminal t1,t2,t3,t4,t5,t6,t7,t8,t9,t10:electrical;
+terminal V_pos,V_neg: electrical;
+
+BEGIN
+   
+  Q01_npn: trans_npn   port map(emitter=>T2    ,base=>T1	      ,collector=>T9);
+  Q02_npn: trans_npn   port map(emitter=>T2    ,base=>T3              ,collector=>T4);
+  Q03_npn: trans_npn   port map(emitter=>T5    ,base=>T6              ,collector=>T2);
+  Q04_npn: trans_pnp   port map(emitter=>T7    ,base=>T4              ,collector=>T8);
+  Q05_npn: trans_npn   port map(emitter=>output,base=>T8              ,collector=>V_pos);
+
+  Res_i1 : resistor    generic map(1.0e3)
+		       port map(inverting_ip,T1);
+  Res_i2 : resistor   generic map(1.0e3)
+		       port map(non_inverting_ip,T3);
+  Res_a  : resistor    generic map(220.0e3)
+		       port map(T6,V_pos);
+  Res_c1 : resistor    generic map(13.0e3)
+		       port map(T9,V_pos);
+  Res_c2 : resistor    generic map(13.0e3)
+		       port map(V_pos,T4);
+  Res_e4 : resistor    generic map(10.0e3)
+		       port map(V_pos,T7);
+  Res_b  : resistor    generic map(20.0e3)
+		       port map(T6,V_neg);
+  Res_e3 : resistor    generic map(1.3e3)
+		       port map(T5,V_neg);
+  Res_c4 : resistor    generic map(21.0e3)
+		       port map(T8,V_neg);
+  Res_e5 : resistor    generic map(12.0e3)
+		       port map(output,V_neg);
+	
+  vpos  : voltsource  generic map(amp=>15.0)    -- test case
+		       port map(V_pos,ground);	 
+  vneg  : voltsource  generic map(amp=>-15.0)    -- test case
+		       port map(V_neg,ground);	 
+
+end architecture struct;
+
+--------------------------------------------------------------------- 
+-------------------   WEIN BRIDGE OSCILLATOR    ---------------------
+--------------------------------------------------------------------- 
+use work.electricalsystem.all;
+ 
+entity wein_bridge_osc  is
+port( terminal signal_out :electrical); 
+end entity wein_bridge_osc;
+
+architecture struct of wein_bridge_osc is
+
+--> components
+component op_amp is
+port(terminal inverting_ip,non_inverting_ip,output :electrical);
+end component;
+for all:op_amp use entity work.op_amp(struct);
+
+component diode
+generic (
+    Isat : real := 1.0e-14;             -- saturatioin current
+    n : real := 1.0;                    -- emmission coefficient
+    bv : real := 1.0;                   -- reverse breakdown voltage
+    ibv : real := 1.0e-3;               -- Breakdown current
+    rds : real := 1.0                   -- Ohnic resistamce 
+    );      
+port (terminal pos, neg : electrical);
+end component;
+for all  : diode use entity work.Diode(behav);
+
+component capacitor is
+generic(cap :real:=1.0);
+port(terminal c_in,c_out: electrical);
+end component;
+for all: capacitor use entity work.capacitor(behav);
+
+component resistor is
+generic(res :real:=1.0 );
+port(terminal r_in,r_out: electrical);
+end component;
+for all: resistor use entity work.resistor(behav);
+
+terminal t1,t2,t3,t4: electrical;
+
+begin
+
+op_amplifier : op_amp    port map(inverting_ip=>t4,non_inverting_ip=>t1,output=>t3);
+
+D1           : diode     port map(t3,signal_out);      
+D2           : diode     port map(signal_out,t3);      
+
+R1_a 	     : resistor  generic map(18.0e3)
+			 port map(t4, ground);
+R1_b 	     : resistor  generic map(32.0e3)
+			 port map(t4,signal_out);
+R2 	     : resistor  generic map(10.0e3)
+			 port map(signal_out,t3);
+R3 	     : resistor  generic map(10.0e3)
+			 port map(t1,ground);
+R4 	     : resistor  generic map(10.0e3)
+			 port map(t2,t3);
+
+C3           : capacitor generic map(16.0e-12)
+			 port map(T1,ground);
+C4           : capacitor generic map(16.0e-12)
+			 port map(T1,T2);
+end struct;
+
+---------------------------- Test Bench ----------------------------- 
+
+use work.electricalsystem.all;
+
+entity testbench is
+end entity;
+
+architecture basic of testbench is
+
+-->components
+component wein_bridge_osc is
+port( terminal signal_out :electrical); 
+end component;
+for all: wein_bridge_osc use entity work.wein_bridge_osc(struct);
+
+terminal t1: electrical;
+
+quantity V_out across i_out through t1 to ground;
+
+BEGIN
+
+osc: wein_bridge_osc port map(T1);
+
+V_out == i_out*1.0e6;
+
+end basic;
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test112.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test112.ams
new file mode 100644
index 0000000..a463e8e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test112.ams
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test112.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of cincinnati
+-- Cincinnati
+----------------------------------------------------------------------
+-- File          : model.ams
+-- Author(s)     : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created       : May 2001
+-- Last modified :
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- the test checks the correctness of the subtype declarations for the
+-- through and across quantities.
+----------------------------------------------------------------------
+PACKAGE electricalSystem IS
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+    subtype voltage is real;
+    subtype current is real;
+    nature electrical is voltage across current through ground reference;
+END PACKAGE electricalSystem;
+use work.electricalSystem.all;
+
+entity test is
+
+end entity;
+
+architecture atest of test is
+
+constant R1: real :=10.0;
+constant R2: real :=5.0;
+constant R3: real :=1.0;
+terminal T1,T2:electrical;
+quantity V1 across I1 through T1 to T2;
+quantity V2 across I2 through T2 to electrical'reference;
+quantity V3 across I3 through T2 to electrical'reference;
+quantity VS across T1 to electrical'reference;
+
+begin
+
+e1:     V1 == I1*R1;
+e2:     V2 == I2*R2;
+e3:     V3 == I3*R3;
+    
+esource:VS == 5.0 * sin(2.0 * 3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+    
+end architecture atest;
+
+
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test117.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test117.ams
new file mode 100644
index 0000000..acff532
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/subtype_test/test117.ams
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test117.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Developed at:
+-- Distributed Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+
+Package electricalsystem is
+ FUNCTION SIN(X : real) RETURN real;
+
+subtype voltage is real tolerance "abstol=1.0e-3";
+subtype current is real; 
+subtype resistance is real;
+
+nature electrical is voltage across current through ground reference;
+end package electricalsystem;
+
+use work.electricalsystem.all;
+
+entity test is
+end entity;
+
+architecture atest of test is
+terminal t1, t2: electrical;
+quantity vr  across ir through t1 ;
+quantity vs across t1;
+constant r:resistance;
+begin
+e1: vs==5.0 *sin(2.0 *3.141592 *10000.0 * real(time'pos(now))*1.0e-12);
+e2: vr==ir*1.0;
+
+end architecture;
diff --git a/testsuite/vests/vhdl-ams/ashenden/README b/testsuite/vests/vhdl-ams/ashenden/README
new file mode 100644
index 0000000..de7180c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/README
@@ -0,0 +1,23 @@
+
+This directory contains copies of the VHDL files from The Designer's Guild
+to VHDL-AMS written by Peter Ashenden, Gregory D. Peterson, and Darrell
+A. Teegarden and published by Morgan Kaufmann Publishers, Inc in 2002.
+Morgan Kaufmann has given the University of Cincinnati permission to
+release these files under the GNU Public License.
+
+In many cases the original figures contained incomplete VHDL.  We have
+added additional VHDL constructs we believed necessary to make the VHDL
+complete and processable by a VHDL-AMS compliant analyzer.  As we made
+changes to the examples, comments were inserted to demarcate the changes
+we made.
+
+If you find errors or corrections to these files, please submit them to
+us at vests@cliftonlabs.com.  Thank you.
+
+------------------------------------------------------------------------
+Philip A. Wilsey 
+The University of Cincinnati
+vests@cliftonlabs.com
+------------------------------------------------------------------------
+Last Revised: November 3, 2003
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/a2d_nbit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/a2d_nbit.vhd
new file mode 100644
index 0000000..3bc693b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/a2d_nbit.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity a2d_nbit is
+  port ( signal start : in std_ulogic; 	                     -- Start signal
+         signal clk : in std_ulogic;   	                     -- Strobe clock
+         terminal ain : electrical;  	                     -- Analog input terminal
+         signal eoc : out std_ulogic := '0';                 -- End of conversion pin
+         signal dout : out std_ulogic_vector(9 downto 0) );  -- Digital output signal
+end entity a2d_nbit;
+
+----------------------------------------------------------------
+
+architecture sar of a2d_nbit is
+  
+  constant Vmax : real := 5.0;   	-- ADC's maximum range
+  constant delay : time := 10 us;	-- ADC's conversion time
+
+  type states is (input, convert); 	-- Two states of A2D Conversion
+  constant bit_range : integer := 9; 	-- Bit range for dtmp and dout
+  
+  quantity Vin across Iin through ain to electrical_ref;     -- ADC's input branch
+
+begin
+
+  sa_adc: process is
+
+    variable thresh : real := Vmax;  -- Threshold to test input voltage against
+    variable Vtmp : real := Vin;     -- Snapshot of input voltage
+                                     -- when conversion starts
+    variable dtmp : std_ulogic_vector(bit_range downto 0);  -- Temp. output data
+    variable status : states := input;                      -- Begin with "input" case 
+    variable bit_cnt : integer := bit_range;
+
+  begin
+    case status is
+      when input => 			-- Read input voltages when start goes high
+        wait on start until start = '1' or start = 'H';
+        bit_cnt := bit_range;           -- Reset bit_cnt for conversion
+        thresh := Vmax;
+        Vtmp := Vin;                    -- Variable to hold input comparison voltage
+        eoc <= '0';                     -- Reset end of conversion
+        status := convert;              -- Go to convert state
+      when convert => 			-- Begin successive approximation conversion
+        wait on clk until clk = '1' or clk = 'H';
+        thresh := thresh / 2.0;         -- Get value of MSB
+        if Vtmp > thresh then
+          dtmp(bit_cnt) := '1';         -- Store '1' in dtmp variable vector
+          Vtmp := Vtmp - thresh;	-- Prepare for next comparison
+        else
+          dtmp(bit_cnt) := '0';         -- Store '0' in dtmp variable vector
+        end if;
+        if bit_cnt > 0 then
+          bit_cnt := bit_cnt - 1;       -- Decrement the bit count
+        else
+          dout <= dtmp;	                -- Put contents of dtmp on output pins
+          eoc <= '1' after delay;       -- Signal end of conversion
+          status := input; 		-- Go to input state
+        end if;
+    end case;
+  end process sa_adc;
+
+  Iin == 0.0;  -- Ideal input draws no current
+
+end architecture sar;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/dac_10_bit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/dac_10_bit.vhd
new file mode 100644
index 0000000..7f2226f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/dac_10_bit.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity dac_10_bit is
+  port ( signal bus_in : in std_ulogic_vector(9 downto 0); 
+         signal clk : in std_ulogic;
+         terminal analog_out :  electrical );
+end entity dac_10_bit;
+
+----------------------------------------------------------------
+
+architecture behavioral of dac_10_bit is
+  
+  constant v_max : real := 5.0;
+  signal s_out : real := 0.0;
+  quantity v_out across i_out through analog_out to electrical_ref;
+        
+begin
+  
+  convert : process is
+    variable v_sum : real;
+    variable delta_v : real;
+  begin
+    wait until clk'event and (clk = '1' or clk = 'H');
+    v_sum  := 0.0;
+    delta_v  := v_max;
+    for i in bus_in'range loop
+      delta_v  := delta_v / 2.0;
+      if bus_in(i) = '1' or bus_in(i) = 'H' then
+        v_sum := v_sum + delta_v;
+      end if;
+    end loop;
+    s_out <= v_sum;
+  end process convert;
+        
+  v_out == s_out'ramp(100.0E-9);
+        
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/index-ams.txt
new file mode 100644
index 0000000..c262df9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/index-ams.txt
@@ -0,0 +1,53 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                   Chapter 8 - Case Study 1: Mixed Signal Focus
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+switch_dig_2in.vhd                              entity switch_dig_2in                   ideal                           Figure 8-6
+a2d_nbit.vhd                                    entity a2d_nbit                         sar                             Figure 8-7
+dac_10_bit.vhd                                  entity dac_10_bit                       behavioral                      Figure 8-12
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_2in_switch.vhd                               entity tb_2in_switch                    TB_2in_switch                   switch_dig_2in.vhd
+tb_a2d_d2a.vhd                                  entity tb_a2d_d2a                       TB_a2d_d2a                      a2d_nbit.vhd, dac_10_bit.vhd
+tb_CS1.vhd                                      entity switch_dig_2in                   ideal                           Case Study 1
+--                                              entity clock                            ideal
+--                                              entity clock_duty                       ideal
+--                                              entity rc_clk                           rc_clk
+--                                              entity bit_cnt                          behavioral
+--                                              entity state_mach1                      state_diagram
+--                                              entity sm_cnt                           sm_cnt
+--                                              entity a2d_nbit                         sar
+--                                              entity shift_reg                        behavioral
+--                                              entity frame_gen                        simple
+--                                              entity xor2                             ideal
+--                                              entity level_set_tri                    ideal
+--                                              entity buffer_tri                       ideal
+--                                              entity d2a_bit                          ideal
+--                                              entity parity_gen                       parity_gen
+--                                              entity tdm_encoder                      tdm_encoder
+--                                              entity Digitize_Encode                  Digitize_Encode
+--                                              entity stick                            ideal
+--                                              entity and2                             ideal
+--                                              entity d_latch_n_edge_rst               behav
+--                                              entity counter_12                       counter_12
+--                                              entity a2d_bit                          ideal
+--                                              entity clock_en                         ideal
+--                                              entity inverter                         ideal
+--                                              entity or2                              ideal
+--                                              entity d2a_nbit                         behavioral
+--                                              entity pw2ana                           pw2ana
+--                                              entity dig_cmp                          simple
+--                                              entity sr_ff                            simple
+--                                              entity state_mach_rcvr                  state_diagram
+--                                              entity sm_cnt_rcvr                      sm_cnt_rcvr
+--                                              entity level_set                        ideal
+--                                              entity ser2par                          a1
+--                                              entity frame_det                        simple
+--                                              entity parity_det                       parity_det
+--                                              entity TDM_Demux_dbg                    TDM_Demux_dbg
+--                                              entity Decode_PW                        Decode_PW
+--                                              entity tb_CS1                           TB_CS1
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/switch_dig_2in.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/switch_dig_2in.vhd
new file mode 100644
index 0000000..3793e19
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/switch_dig_2in.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity switch_dig_2in is
+  port ( sw_state : in std_ulogic;                     -- Digital control input 
+         terminal p_in1, p_in2, p_out : electrical );  -- Analog output
+end entity switch_dig_2in;
+
+----------------------------------------------------------------
+
+architecture ideal of switch_dig_2in is
+  
+  constant r_open : resistance := 1.0e6; 	 -- Open switch resistance
+  constant r_closed : resistance := 0.001;	 -- Closed switch resistance
+  constant trans_time : real := 0.00001;	 -- Transition time to each position
+  
+  signal r_sig1 : resistance := r_closed; 	 -- Closed switch resistance variable
+  signal r_sig2 : resistance := r_open;	 	 -- Open switch resistance variable
+  
+  quantity v1 across i1 through p_in1 to p_out;  -- V & I for in1 to out
+  quantity v2 across i2 through p_in2 to p_out;  -- V & I for in2 to out
+  quantity r1 : resistance; 			 -- Time-varying resistance for in1 to out
+  quantity r2 : resistance; 			 -- Time-varying resistance for in2 to out
+        
+begin
+  
+  process (sw_state) is  -- Sensitivity to digital control input
+  begin
+    if sw_state = '0' or sw_state = 'L' then 	 -- Close sig1, open sig2
+      r_sig1 <= r_closed;
+      r_sig2 <= r_open;
+    elsif sw_state = '1' or sw_state = 'H' then  -- Open sig1, close sig2
+      r_sig1 <= r_open;
+      r_sig2 <= r_closed;
+    end if;
+  end process;
+        
+  r1 == r_sig1'ramp(trans_time, trans_time); 	 -- Ensure resistance continuity
+  r2 == r_sig2'ramp(trans_time, trans_time); 	 -- Ensure resistance continuity
+        
+  v1 == r1 * i1;  -- Apply Ohm's law to in1
+  v2 == r2 * i2;  -- Apply Ohm's law to in2
+        
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_2in_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_2in_switch.vhd
new file mode 100644
index 0000000..89c37df
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_2in_switch.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE; use IEEE.std_logic_1164.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_2in_switch is
+end tb_2in_switch;
+
+architecture TB_2in_switch of tb_2in_switch is
+    -- Component declarations
+    -- Signal declarations
+    terminal p_in1, p_in2, p_out : electrical;
+	signal ctl_ulogic : std_ulogic;
+    signal ctl_logic : std_logic;
+begin
+    -- Signal assignments
+	ctl_ulogic <= To_X01(ctl_logic); -- Convert X01Z to X01
+    -- Component instances
+    vdc1 : entity work.v_constant(ideal)
+        generic map(
+            level => 1.0
+        )
+        port map(
+            pos => p_in1,
+            neg => ELECTRICAL_REF
+        );
+    vdc2 : entity work.v_constant(ideal)
+        generic map(
+            level => 3.0
+        )
+        port map(
+            pos => p_in2,
+            neg => ELECTRICAL_REF
+        );
+    Clk1 : entity work.clock(ideal)
+        generic map(
+            period => 10.0ms
+        )        
+		port map(
+            clk_out => ctl_logic
+        );
+    R1 : entity work.resistor(ideal)
+        generic map(
+            res => 100.0
+        )        
+		port map(
+            p1 => p_out,
+            p2 => electrical_ref
+        );
+    swtch : entity work.switch_dig_2in(ideal)
+        port map(
+            p_in1 => p_in1,
+            p_in2 => p_in2,
+			p_out => p_out,
+			sw_state => ctl_ulogic
+        );
+end TB_2in_switch;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd
new file mode 100644
index 0000000..f18d88b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_CS1.vhd
@@ -0,0 +1,2458 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- Simple Digital-Controlled Two-position Switch Model
+-- Switch position 1 ('0') or switch position 2 ('1')
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY switch_dig_2in is
+	GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
+		 	r_closed : RESISTANCE := 0.001; -- Closed switch resistance
+		 	trans_time : real := 0.00001); -- Transition time to each position
+
+	PORT (sw_state : in std_logic; -- Digital control input 
+    	      TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
+
+END ENTITY switch_dig_2in;
+
+
+ARCHITECTURE ideal OF switch_dig_2in IS
+
+	SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
+	SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
+	QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
+	QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
+	QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
+	QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
+
+BEGIN
+ 
+ PROCESS (sw_state) -- Sensitivity to digital control input
+    BEGIN
+	  IF (sw_state = '0') THEN -- Close sig1, open sig2
+	    r_sig1 <= r_closed;
+	    r_sig2 <= r_open;
+	  ELSIF (sw_state = '1') THEN -- Open sig1, close sig2
+	    r_sig1 <= r_open;
+	    r_sig2 <= r_closed;
+	  END IF;
+    END PROCESS;
+
+	r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
+	r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
+	v1 == r1*i1; -- Apply Ohm's law to in1
+	v2 == r2*i2; -- Apply Ohm's law to in2
+
+END ARCHITECTURE ideal;
+--
+
+-- Digital clock with 50% duty cycle
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock IS
+  GENERIC (
+    period : time);              -- Clock period
+  
+  PORT (
+    clk_out    : OUT std_logic);
+  
+END ENTITY clock;
+
+ARCHITECTURE ideal OF clock IS
+
+BEGIN
+
+-- clock process
+    process
+    begin
+        clk_out <= '0';
+        wait for period/2;
+        clk_out <= '1';
+        wait for period/2;
+    end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- This digital clock allows user to specify the duty cycle using
+-- the parameters "on_time" and "off_time"
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY clock_duty IS
+
+  GENERIC (
+    on_time : time := 20 us;
+	off_time : time := 19.98 ms
+ 	); 
+  
+  PORT (
+    clock_out    : OUT std_logic := '0');
+  
+END ENTITY clock_duty;
+
+ARCHITECTURE ideal OF clock_duty IS
+
+BEGIN
+
+-- clock process
+    process
+    begin
+        clock_out <= '1';
+        wait for on_time;
+        clock_out <= '0';
+        wait for off_time;
+    end process;
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rc_clk is
+    port(
+        clk_100k : out std_logic;
+        clk_6K : out std_logic;
+        clk_50 : out std_logic
+    );
+end rc_clk;
+
+architecture rc_clk of rc_clk is
+    -- Component declarations
+    -- Signal declarations
+begin
+    -- Signal assignments
+    -- Component instances
+    XCMP1 : entity work.clock(ideal)
+        generic map(
+            period => 10us
+        )
+        port map(
+            CLK_OUT => clk_100k
+        );
+    XCMP2 : entity work.clock(ideal)
+        generic map(
+            period => 150us
+        )
+        port map(
+            CLK_OUT => clk_6K
+        );
+    clk_50Hz : entity work.clock_duty(ideal)
+        generic map(
+            on_time => 20 us,
+            off_time => 19.98 ms
+        )
+        port map(
+            CLOCK_OUT => clk_50
+        );
+end rc_clk;
+--
+
+-- This model counts the number of input clock transitions and outputs
+-- a '1' when this number equals the value of the user-defined constant 'count'
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity bit_cnt is
+  generic (
+	count : integer -- User-defined value to count up to
+	);             
+port
+(
+      bit_in : in std_logic ;
+      clk : in std_logic ;
+      dly_out : out std_logic 
+);
+end bit_cnt;
+
+architecture behavioral of bit_cnt is
+begin
+	serial_clock : process is
+	begin
+		wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
+	  	FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
+	  		wait until clk'event AND (clk = '1' OR clk = 'H');
+     	END LOOP ;
+		dly_out <= '1'; -- After count is reached, set output high
+		wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
+		dly_out <= '0'; -- Reset output to '0' on next clock input
+	end process serial_clock;
+end;
+--
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+
+ENTITY state_mach1 IS
+    PORT (
+          a2d_eoc : IN std_logic;
+          clk_50 : IN std_logic;
+          clk_100k : IN std_logic;
+          clk_6k : IN std_logic;
+          ser_done : IN std_logic;
+          ch_sel : OUT std_logic;
+          frm_gen : OUT std_logic;
+          a2d_oe : OUT std_logic;
+          a2d_start : OUT std_logic;
+          p2s_oe : OUT std_logic;
+          p2s_load : OUT std_logic;
+          parity_oe : OUT std_logic;
+          ser_cnt : OUT std_logic;
+          p2s_clr : OUT std_logic);
+
+END state_mach1;
+
+ARCHITECTURE state_diagram OF state_mach1 IS
+
+    ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+    TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
+           , load, ad_ch2, delay);
+    SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
+
+    SIGNAL FB_frm_gen : std_logic;
+    SIGNAL FB_p2s_load : std_logic;
+    SIGNAL FB_ch_sel : std_logic;
+
+BEGIN 
+    frm_gen <= FB_frm_gen ;
+    p2s_load <= FB_p2s_load ;
+    ch_sel <= FB_ch_sel ;
+
+sm1: 
+  PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel) 
+  BEGIN
+
+    CASE CS_state_mach1_sm1 IS
+      WHEN V_begin =>
+        FB_frm_gen <= ('1');
+        a2d_start <= ('0');
+        a2d_oe <= ('0');
+        FB_p2s_load <= ('0');
+        p2s_clr <= ('0');
+        p2s_oe <= ('0');
+        FB_ch_sel <= ('0');
+        parity_oe <= ('0');
+        ser_cnt <= ('0');
+
+        IF ((FB_frm_gen = '1')) THEN
+          NS_state_mach1_sm1 <= frm_rd;
+        ELSE
+          NS_state_mach1_sm1 <= V_begin;
+        END IF;
+
+      WHEN frm_rd =>
+        FB_p2s_load <= ('1');
+
+        IF ((FB_p2s_load = '1')) THEN
+          NS_state_mach1_sm1 <= ser_oe;
+        ELSE
+          NS_state_mach1_sm1 <= frm_rd;
+        END IF;
+
+      WHEN ser_oe =>
+        p2s_oe <= ('1');
+        FB_frm_gen <= ('0');
+        FB_p2s_load <= ('0');
+        ser_cnt <= ('1');
+
+        IF ((ser_done = '1')) THEN
+          NS_state_mach1_sm1 <= ch1;
+        ELSE
+          NS_state_mach1_sm1 <= ser_oe;
+        END IF;
+
+      WHEN ch1 =>
+        p2s_oe <= ('0');
+        FB_ch_sel <= ('0');
+        a2d_start <= ('1');
+        ser_cnt <= ('0');
+
+        IF ((a2d_eoc = '1')) THEN
+          NS_state_mach1_sm1 <= data_en;
+        ELSE
+          NS_state_mach1_sm1 <= ch1;
+        END IF;
+
+      WHEN data_en =>
+        a2d_start <= ('0');
+        a2d_oe <= ('1');
+        parity_oe <= ('1');
+          NS_state_mach1_sm1 <= load;
+
+      WHEN tdm_oe =>
+        a2d_oe <= ('0');
+        parity_oe <= ('0');
+        p2s_oe <= ('1');
+        FB_p2s_load <= ('0');
+        ser_cnt <= ('1');
+
+        IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
+          NS_state_mach1_sm1 <= ch2;
+        ELSE
+          NS_state_mach1_sm1 <= tdm_oe;
+        END IF;
+
+      WHEN ch2 =>
+        p2s_oe <= ('0');
+        ser_cnt <= ('0');
+        FB_ch_sel <= ('1');
+          NS_state_mach1_sm1 <= delay;
+
+      WHEN load =>
+        FB_p2s_load <= ('1');
+          NS_state_mach1_sm1 <= tdm_oe;
+
+      WHEN ad_ch2 =>
+        a2d_start <= ('1');
+
+        IF ((a2d_eoc = '1')) THEN
+          NS_state_mach1_sm1 <= data_en;
+        ELSE
+          NS_state_mach1_sm1 <= ad_ch2;
+        END IF;
+
+      WHEN delay =>
+          NS_state_mach1_sm1 <= ad_ch2;
+
+    END CASE;
+
+  END PROCESS; 
+
+sm1_CTL:
+  PROCESS (clk_100k, clk_50)
+  BEGIN
+
+    IF (clk_100k'event AND clk_100k='1')  THEN 
+        IF (clk_50= '1' ) THEN 
+            CS_state_mach1_sm1 <= V_begin;
+        ELSE
+            CS_state_mach1_sm1 <= NS_state_mach1_sm1;
+        END IF;
+    END IF;
+
+  END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt is
+    port(
+        a2d_eoc : in std_logic;
+        clk_50 : in std_logic;
+        clk_100k : in std_logic;
+        clk_6k : in std_logic;
+        p2s_load : out std_logic;
+        p2s_oe : out std_logic;
+        parity_oe : out std_logic;
+        a2d_start : out std_logic;
+        a2d_oe : out std_logic;
+        frm_gen : out std_logic;
+        ch_sel : out std_logic;
+        p2s_clr : out std_logic
+    );
+end sm_cnt;
+
+architecture sm_cnt of sm_cnt is
+    -- Component declarations
+    -- Signal declarations
+    signal serial_cnt : std_logic;
+    signal XSIG010022 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    bit_cnt1 : entity work.bit_cnt(behavioral)
+        generic map(
+            count => 15
+        )
+        port map(
+            bit_in => serial_cnt,
+            clk => clk_6k,
+            dly_out => XSIG010022
+        );
+    state_mach16 : entity work.state_mach1
+        port map(
+            ser_cnt => serial_cnt,
+            ch_sel => ch_sel,
+            frm_gen => frm_gen,
+            a2d_oe => a2d_oe,
+            a2d_start => a2d_start,
+            parity_oe => parity_oe,
+            p2s_oe => p2s_oe,
+            p2s_load => p2s_load,
+            p2s_clr => p2s_clr,
+            clk_6k => clk_6k,
+            clk_100k => clk_100k,
+            clk_50 => clk_50,
+            a2d_eoc => a2d_eoc,
+            ser_done => XSIG010022
+        );
+end sm_cnt;
+--
+
+--This is a VHDL-AMS model of a simple analog to digital converter. The model
+--describes the general behavior of A/D converters for system level design and
+--verification.
+--The format of the digital output is binary coding.
+--
+--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
+--
+
+-- Use IEEE natures and packages
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity a2d_nbit is
+ generic (
+  Vmax: REAL := 5.0 ;   -- ADC's maximum range
+  Nbits: INTEGER := 10 ;  -- number bits in ADC's output
+  delay: TIME := 10 us    -- ADC's conversion time
+ );
+ 
+port (
+  signal start: in std_logic ; -- Start signal
+  signal clk: in std_logic ;   -- Strobe clock
+  signal oe: in std_logic ; -- Output enable
+  terminal ain: ELECTRICAL ;  -- ADC's analog input terminal
+  signal eoc: out std_logic := '0' ; -- End Of Conversion pin
+  signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
+end entity a2d_nbit;
+
+architecture sar of a2d_nbit is
+
+  type states is (input, convert, output) ; -- Three states of A2D Conversion
+  constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
+  quantity Vin across Iin through ain to electrical_ref;     -- ADC's input branch
+
+begin
+
+ sa_adc: process
+
+  variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
+  variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
+  variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
+  variable status: states := input ; -- Begin with "input" CASE 
+  variable bit_cnt: integer := Nbits -1 ;
+
+ begin
+ CASE status is
+	when input => -- Read input voltages when start goes high
+		wait on start until start = '1' or start = 'H' ;
+  		thresh := Vmax ;
+  		Vtmp := Vin ;
+		eoc <= '0' ;
+		status := convert ; -- Go to convert state
+	when convert => -- Begin successive approximation conversion
+		thresh := thresh / 2.0 ; -- Get value of MSB
+		wait on clk until clk = '1' OR clk = 'H';
+		if Vtmp > thresh then
+			dtmp(bit_cnt) := '1' ;
+			Vtmp := Vtmp - thresh ;
+		else
+			dtmp(bit_cnt) := '0' ;
+		end if ;
+		if bit_cnt < 1 then
+			status := output ; -- Go to output state
+		end if;
+		bit_cnt := bit_cnt - 1 ;
+	when output => -- Wait for output enable, then put data on output pins
+		eoc <= '1' after delay ;
+		wait on oe until oe = '1' OR oe = 'H' ;
+				dout <= dtmp ;
+		wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
+				dout <= (others => 'Z') ;
+		bit_cnt := bit_range ;
+		status := input ; -- Set up for next conversion
+	END CASE ;
+ end process sa_adc ;
+
+ Iin == 0.0 ; -- Ideal input draws no current
+
+end architecture sar ;
+--
+
+-- Parallel input/serial output shift register
+-- With 4 trailing zeros
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity shift_reg is
+generic ( td : time := 0 ns); 
+
+port
+(
+      bus_in : in std_logic_vector ; -- Input bus
+      clk : in std_logic ; -- Shift clock
+      oe : in std_logic ; -- Output enable
+      ser_out : out std_logic := '0'; -- Output port
+      load : in std_logic ; -- Parallel input load
+	clr : in std_logic -- Clear register
+);
+
+end entity shift_reg;
+
+architecture behavioral of shift_reg is
+begin
+
+control_proc : process
+  VARIABLE bit_val : std_logic_vector(11 downto 0);  -- Default 12-bit input
+  begin
+
+	IF (clr = '1' OR clr = 'H') then
+    		bit_val := "000000000000"; -- Set all input bits to zero
+	ELSE
+  		wait until load'event AND (load = '1' OR load = 'H');
+		FOR i IN bus_in'high DOWNTO bus_in'low LOOP
+        		bit_val(i) := bus_in(i) ; -- Transfer input data to variable
+     		END LOOP ;
+	END IF;
+
+	wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
+	FOR i IN bit_val'high DOWNTO bit_val'low LOOP
+		wait until clk'event AND (clk = '1' OR clk = 'H');
+      	ser_out <= bit_val(i) ;
+	END LOOP ;
+
+	  FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros	
+		wait until clk'event AND (clk = '1' OR clk = 'H');
+		ser_out <= '0';
+	  END LOOP;
+
+END process;
+
+end architecture behavioral;
+--
+
+-- This model generates a 12-bit data frame synchronization code
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_gen is
+port
+(
+      oe : in std_logic := '0';
+	sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
+
+end entity frame_gen;
+
+architecture simple of frame_gen is
+begin
+	enbl: PROCESS
+  		BEGIN 
+  			WAIT ON OE;
+			IF OE = '1' THEN
+				sync_out <= "010101010101"; -- Sync code
+			ELSE
+				sync_out <= "ZZZZZZZZZZZZ";
+			END IF;
+  	END PROCESS;
+end architecture simple;
+--
+
+-- Two input XOR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY xor2 IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    in1, in2 : IN  std_logic;
+    output    : OUT std_logic);
+  
+END ENTITY xor2;
+
+ARCHITECTURE ideal OF xor2 IS
+BEGIN
+   output <= in1 XOR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- level_set_tri.vhd 
+-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
+-- If OE = '0' set output to high impedance
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set_tri IS
+
+  GENERIC (
+    logic_val : std_logic := 'Z');     
+
+  PORT (
+  	OE : IN std_logic;
+    level : OUT std_logic := 'Z');
+
+END ENTITY level_set_tri;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set_tri IS
+BEGIN
+  oe_ctl: PROCESS
+  BEGIN
+	WAIT ON OE;
+ 	IF OE = '1' THEN 
+   		level <= logic_val;
+	ELSE
+		level <= 'Z';
+	END IF;
+  END PROCESS;
+  
+END ARCHITECTURE ideal;
+
+--
+
+-- Simple Tri-state Buffer with delay time
+-- If OE = 1, output = input after delay
+-- If OE /= 1, output = Z after delay
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY buffer_tri IS
+  GENERIC (
+    delay : time := 0 ns);  -- Delay time
+  
+  PORT (
+    input : IN  std_logic;
+	OE : IN std_logic;
+    output : OUT std_logic);
+  
+END ENTITY buffer_tri;
+
+ARCHITECTURE ideal OF buffer_tri IS
+BEGIN
+  oe_ctl: PROCESS
+  BEGIN
+	WAIT ON OE, input;
+ 	IF OE = '1' THEN 
+   		output <= input AFTER delay;
+	ELSE
+		output <= 'Z' AFTER delay;
+	END IF;
+  END PROCESS;
+END ARCHITECTURE ideal;
+--
+
+-- ideal one bit D/A converter
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY d2a_bit IS
+  GENERIC (vlow : real :=0.0;           -- output high voltage
+           vhigh : real :=5.0);         -- output low voltage
+  PORT	  (D : IN std_logic;            -- digital (std_logic) intout
+           TERMINAL A : electrical);    -- analog (electrical) output
+END ENTITY d2a_bit;
+
+ARCHITECTURE ideal OF d2a_bit IS
+  QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
+  SIGNAL vin : real := 0.0;
+
+  BEGIN
+    vin <= vhigh WHEN D = '1' ELSE vlow;
+    -- Use 'RAMP for discontinuous signal
+    vout == vin'RAMP(1.0e-9);      
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_gen is
+    port(
+        parity : in std_logic_vector(1 to 10);
+        oe : in std_logic;
+        parity_out : out std_logic_vector(0 to 11)
+    );
+end parity_gen;
+
+architecture parity_gen of parity_gen is
+    -- Component declarations
+    -- Signal declarations
+    terminal par_bit_gen_a : electrical;
+    signal XSIG010002 : std_logic;
+    signal XSIG010003 : std_logic;
+    signal XSIG010004 : std_logic;
+    signal XSIG010005 : std_logic;
+    signal XSIG010006 : std_logic;
+    signal XSIG010007 : std_logic;
+    signal XSIG010008 : std_logic;
+    signal XSIG010009 : std_logic;
+    signal XSIG010098 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    XCMP1 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(1),
+            in2 => parity(2),
+            output => XSIG010002
+        );
+    XCMP2 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(3),
+            in2 => parity(4),
+            output => XSIG010003
+        );
+    XCMP3 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(5),
+            in2 => parity(6),
+            output => XSIG010004
+        );
+    XCMP4 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(7),
+            in2 => parity(8),
+            output => XSIG010005
+        );
+    XCMP5 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(9),
+            in2 => parity(10),
+            output => XSIG010008
+        );
+    XCMP6 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010002,
+            in2 => XSIG010003,
+            output => XSIG010006
+        );
+    XCMP7 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010004,
+            in2 => XSIG010005,
+            output => XSIG010007
+        );
+    XCMP8 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010006,
+            in2 => XSIG010007,
+            output => XSIG010009
+        );
+    XCMP9 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010009,
+            in2 => XSIG010008,
+            output => XSIG010098
+        );
+    XCMP18 : entity work.level_set_tri(ideal)
+        generic map(
+            logic_val => '1'
+        )
+        port map(
+            level => parity_out(11),
+            oe => oe
+        );
+    XCMP19 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(1),
+            output => parity_out(1),
+            oe => oe
+        );
+    XCMP20 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(2),
+            output => parity_out(2),
+            oe => oe
+        );
+    XCMP21 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(3),
+            output => parity_out(3),
+            oe => oe
+        );
+    XCMP22 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(4),
+            output => parity_out(4),
+            oe => oe
+        );
+    XCMP23 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(5),
+            output => parity_out(5),
+            oe => oe
+        );
+    XCMP24 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(6),
+            output => parity_out(6),
+            oe => oe
+        );
+    XCMP25 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(7),
+            output => parity_out(7),
+            oe => oe
+        );
+    XCMP26 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(8),
+            output => parity_out(8),
+            oe => oe
+        );
+    XCMP27 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(9),
+            output => parity_out(9),
+            oe => oe
+        );
+    XCMP28 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(10),
+            output => parity_out(10),
+            oe => oe
+        );
+    XCMP29 : entity work.buffer_tri(ideal)
+        port map(
+            input => XSIG010098,
+            output => parity_out(0),
+            oe => oe
+        );
+    XCMP30 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010098,
+            A => par_bit_gen_a
+        );
+end parity_gen;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tdm_encoder is
+    port(
+        clk : in std_logic;
+        p2s_oe : in std_logic;
+        p2s_load : in std_logic;
+        frm_gen : in std_logic;
+        parity_oe : in std_logic;
+        tdm_out : out std_logic;
+        p2s_clr : in std_logic;
+        a2d_data : in std_logic_vector(1 to 10)
+    );
+end tdm_encoder;
+
+architecture tdm_encoder of tdm_encoder is
+    -- Component declarations
+    -- Signal declarations
+    signal sync_par : std_logic_vector(0 to 11);
+begin
+    -- Signal assignments
+    -- Component instances
+    p2s1 : entity work.shift_reg(behavioral)
+        port map(
+            bus_in => sync_par,
+            clk => clk,
+            oe => p2s_oe,
+            ser_out => tdm_out,
+            load => p2s_load,
+            clr => p2s_clr
+        );
+    sync_gen1 : entity work.frame_gen(simple)
+        port map(
+            oe => frm_gen,
+            sync_out => sync_par
+        );
+    par_gen1 : entity work.parity_gen
+        port map(
+            parity => a2d_data,
+            parity_out => sync_par,
+            oe => parity_oe
+        );
+end tdm_encoder;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Digitize_Encode is
+    port(
+        tdm_out : out std_logic;
+        terminal ch1_in : electrical;
+        terminal ch2_in : electrical
+    );
+end Digitize_Encode;
+
+architecture Digitize_Encode of Digitize_Encode is
+    -- Component declarations
+    -- Signal declarations
+    terminal a2d_ana_in : electrical;
+    signal a2d_oe : std_logic;
+    signal ch_bus : std_logic_vector(1 to 10);
+    signal frm_gen_ctl : std_logic;
+    signal p2s_clr : std_logic;
+    signal p2s_load : std_logic;
+    signal p2s_oe : std_logic;
+    signal par_oe : std_logic;
+    signal start_a2d1 : std_logic;
+    signal sw_ctl : std_logic;
+    signal XSIG010091 : std_logic;
+    signal XSIG010173 : std_logic;
+    signal XSIG010180 : std_logic;
+    signal XSIG010181 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    A_SWITCH1 : entity work.switch_dig_2in(ideal)
+        port map(
+            p_in1 => ch1_in,
+            p_out => a2d_ana_in,
+            sw_state => sw_ctl,
+            p_in2 => ch2_in
+        );
+    rc_clk2 : entity work.rc_clk
+        port map(
+            clk_50 => XSIG010180,
+            clk_6K => XSIG010173,
+            clk_100k => XSIG010181
+        );
+    sm_xmtr1 : entity work.sm_cnt
+        port map(
+            clk_100k => XSIG010181,
+            a2d_start => start_a2d1,
+            a2d_eoc => XSIG010091,
+            p2s_oe => p2s_oe,
+            p2s_load => p2s_load,
+            ch_sel => sw_ctl,
+            frm_gen => frm_gen_ctl,
+            parity_oe => par_oe,
+            a2d_oe => a2d_oe,
+            clk_50 => XSIG010180,
+            clk_6k => XSIG010173,
+            p2s_clr => p2s_clr
+        );
+    a2d1 : entity work.a2d_nbit(sar)
+        generic map(
+            Vmax => 4.8
+        )
+        port map(
+            dout => ch_bus,
+            ain => a2d_ana_in,
+            clk => XSIG010181,
+            start => start_a2d1,
+            eoc => XSIG010091,
+            oe => a2d_oe
+        );
+    tdm_enc1 : entity work.tdm_encoder
+        port map(
+            clk => XSIG010173,
+            p2s_oe => p2s_oe,
+            tdm_out => tdm_out,
+            p2s_load => p2s_load,
+            a2d_data => ch_bus,
+            frm_gen => frm_gen_ctl,
+            parity_oe => par_oe,
+            p2s_clr => p2s_clr
+        );
+end Digitize_Encode;
+--
+
+-- Electrical sinusoidal voltage source (stick.vhd)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+
+ENTITY stick IS
+  
+-- Initialize parameters
+  GENERIC (
+    freq      : real;                     -- frequency,       [Hertz]
+    amplitude : real;                     -- amplitude,       [Volt]
+    phase     : real := 0.0;              -- initial phase,   [Degree]
+    offset    : real := 0.0;              -- DC value,        [Volt]
+    df        : real := 0.0;              -- damping factor,  [1/second]
+    ac_mag    : real := 1.0;              -- AC magnitude,    [Volt]
+    ac_phase  : real := 0.0);             -- AC phase,        [Degree]
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL v_out : ELECTRICAL);
+
+END ENTITY stick;
+
+-- Ideal Architecture
+ARCHITECTURE ideal OF stick IS
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
+-- Declare Quantity for Phase in radians (calculated below)
+  QUANTITY phase_rad : real;          
+-- Declare Quantity in frequency domain for AC analysis
+  QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN  
+-- Convert phase to radians
+  phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+  
+  IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
+    v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+  ELSE 
+    v == ac_spec;    -- used for Frequency (AC) analysis
+  END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-- Two input AND gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY and2 IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    in1, in2 : IN  std_logic;
+    output    : OUT std_logic);
+  
+END ENTITY and2;
+
+ARCHITECTURE ideal OF and2 IS
+BEGIN
+   output <= in1 AND in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- D Flip Flop with reset (negative edge triggered)
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY d_latch_n_edge_rst IS
+	GENERIC (
+		delay : time := 0 ns);  -- Delay time
+  
+	PORT (
+		data, clk 	: IN std_logic;
+		q 	: OUT std_logic := '0';
+		qn	: OUT std_logic := '1';
+		rst	: IN std_logic := '0');  -- reset 
+	   
+END ENTITY d_latch_n_edge_rst ;
+
+ARCHITECTURE behav OF d_latch_n_edge_rst IS
+BEGIN
+ 
+ data_in : PROCESS(clk, rst) IS  
+
+   BEGIN
+     IF clk = '0' AND clk'event AND rst /= '1' THEN
+	     q  <= data     	AFTER delay;
+         qn <= NOT data 	AFTER delay;
+     ELSIF rst = '1' THEN
+         q <= '0';
+         qn <= '1';
+     END IF;
+     
+   END PROCESS data_in;  -- End of process data_in
+
+END ARCHITECTURE behav;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity counter_12 is
+    port(
+        cnt : out std_logic_vector(0 to 11);
+        reset : in std_logic;
+        enable : in std_logic;
+        clk : in std_logic
+    );
+end counter_12;
+
+architecture counter_12 of counter_12 is
+    -- Component declarations
+    -- Signal declarations
+    signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
+    signal XSIG010078 : std_logic;
+    signal XSIG010081 : std_logic;
+    signal XSIG010083 : std_logic;
+    signal XSIG010085 : std_logic;
+    signal XSIG010087 : std_logic;
+    signal XSIG010101 : std_logic;
+    signal XSIG010102 : std_logic;
+    signal XSIG010103 : std_logic;
+    signal XSIG010104 : std_logic;
+    signal XSIG010115 : std_logic;
+    signal XSIG010116 : std_logic;
+    signal XSIG010117 : std_logic;
+    signal XSIG010132 : std_logic;
+begin
+    -- Signal assignments
+    cnt(0) <= cdb2vhdl_tmp_1(0);
+    cnt(1) <= cdb2vhdl_tmp_1(1);
+    cnt(2) <= cdb2vhdl_tmp_1(2);
+    cnt(3) <= cdb2vhdl_tmp_1(3);
+    cnt(4) <= cdb2vhdl_tmp_1(4);
+    cnt(5) <= cdb2vhdl_tmp_1(5);
+    cnt(6) <= cdb2vhdl_tmp_1(6);
+    cnt(7) <= cdb2vhdl_tmp_1(7);
+    cnt(8) <= cdb2vhdl_tmp_1(8);
+    cnt(9) <= cdb2vhdl_tmp_1(9);
+    cnt(10) <= cdb2vhdl_tmp_1(10);
+    cnt(11) <= cdb2vhdl_tmp_1(11);
+    -- Component instances
+    XCMP92 : entity work.and2(ideal)
+        port map(
+            in1 => clk,
+            in2 => enable,
+            output => XSIG010132
+        );
+    XCMP93 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => XSIG010132,
+            DATA => XSIG010078,
+            QN => XSIG010078,
+            Q => cdb2vhdl_tmp_1(0),
+            RST => reset
+        );
+    XCMP94 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(0),
+            DATA => XSIG010081,
+            QN => XSIG010081,
+            Q => cdb2vhdl_tmp_1(1),
+            RST => reset
+        );
+    XCMP95 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(1),
+            DATA => XSIG010083,
+            QN => XSIG010083,
+            Q => cdb2vhdl_tmp_1(2),
+            RST => reset
+        );
+    XCMP96 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(2),
+            DATA => XSIG010085,
+            QN => XSIG010085,
+            Q => cdb2vhdl_tmp_1(3),
+            RST => reset
+        );
+    XCMP97 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(3),
+            DATA => XSIG010087,
+            QN => XSIG010087,
+            Q => cdb2vhdl_tmp_1(4),
+            RST => reset
+        );
+    XCMP98 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(4),
+            DATA => XSIG010101,
+            QN => XSIG010101,
+            Q => cdb2vhdl_tmp_1(5),
+            RST => reset
+        );
+    XCMP99 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(5),
+            DATA => XSIG010102,
+            QN => XSIG010102,
+            Q => cdb2vhdl_tmp_1(6),
+            RST => reset
+        );
+    XCMP100 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(6),
+            DATA => XSIG010103,
+            QN => XSIG010103,
+            Q => cdb2vhdl_tmp_1(7),
+            RST => reset
+        );
+    XCMP101 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(7),
+            DATA => XSIG010104,
+            QN => XSIG010104,
+            Q => cdb2vhdl_tmp_1(8),
+            RST => reset
+        );
+    XCMP102 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(8),
+            DATA => XSIG010115,
+            QN => XSIG010115,
+            Q => cdb2vhdl_tmp_1(9),
+            RST => reset
+        );
+    XCMP103 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(9),
+            DATA => XSIG010116,
+            QN => XSIG010116,
+            Q => cdb2vhdl_tmp_1(10),
+            RST => reset
+        );
+    XCMP104 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(10),
+            DATA => XSIG010117,
+            QN => XSIG010117,
+            Q => cdb2vhdl_tmp_1(11),
+            RST => reset
+        );
+end counter_12;
+--
+
+-- ideal one bit A/D converter
+
+LIBRARY IEEE;
+USE IEEE.math_real.ALL;
+USE IEEE.std_logic_1164.ALL;
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY a2d_bit IS
+  
+  GENERIC (
+    thres : real := 2.5);    -- Threshold to determine logic output
+
+  PORT (
+    TERMINAL a :     electrical;   -- analog input
+    SIGNAL   d : OUT std_logic);   -- digital (std_logic) output
+  
+END ENTITY a2d_bit;
+
+
+ARCHITECTURE ideal OF a2d_bit IS
+
+  QUANTITY vin ACROSS a;
+  
+  BEGIN  -- threshold
+-- Process needed to detect threshold crossing and assign output (d)
+    PROCESS (vin'ABOVE(thres)) IS
+      BEGIN  -- PROCESS
+      IF vin'ABOVE(thres) THEN
+         d <= '1';
+      ELSE
+         d <= '0';  
+      END IF;
+    END PROCESS;
+
+END ideal;
+
+
+-- Digital clock with 50% duty cycle and enable pin
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock_en IS
+  GENERIC (
+    pw : time);              -- Clock pulse width
+  
+  PORT (
+	enable : IN std_logic ;
+	clock_out : INOUT std_logic := '0');
+  
+END ENTITY clock_en;
+
+ARCHITECTURE ideal OF clock_en IS
+
+BEGIN
+
+-- clock process
+    process (clock_out, enable) is
+    begin
+   	if clock_out = '0' AND enable = '1' THEN
+        clock_out <= '1' after pw, '0' after 2*pw;
+	end if;
+    end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- Inverter
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY inverter IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    input : IN  std_logic;
+    output : OUT std_logic);
+  
+END ENTITY inverter;
+
+ARCHITECTURE ideal OF inverter IS
+BEGIN
+   output <= NOT input AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- Two input OR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY or2 IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    in1, in2 : IN  std_logic;
+    output    : OUT std_logic);
+  
+END ENTITY or2;
+
+ARCHITECTURE ideal OF or2 IS
+BEGIN
+   output <= in1 OR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY d2a_nbit IS
+
+  GENERIC (
+    vmax : real := 5.0;	-- High output
+    vmin : real := 0.0;	-- Low output
+    high_bit : integer := 9; -- High end of bit range for D/A
+	low_bit : integer := 0); -- Low end of bit range for D/A
+
+  PORT (
+    SIGNAL   bus_in : IN STD_LOGIC_VECTOR;  -- variable width vector input
+    SIGNAL latch : IN STD_LOGIC;
+    TERMINAL ana_out  :    electrical);      -- analog output
+
+END ENTITY d2a_nbit ;
+
+ARCHITECTURE behavioral OF d2a_nbit IS
+
+  SIGNAL   sout : real := 0.0;
+  QUANTITY vout across iout through ana_out TO electrical_ref;
+
+BEGIN  -- ARCHITECTURE behavioral
+
+  proc : PROCESS
+
+    VARIABLE v_sum  : real; -- Sum of voltage contribution from each bit
+    VARIABLE delt_v : real; -- Represents the voltage value of each bit
+
+  BEGIN
+	WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
+  	v_sum     := vmin;
+    	delt_v    := vmax - vmin;
+
+    FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
+      delt_v  := delt_v / 2.0;
+      IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
+        v_sum := v_sum + delt_v;
+      END IF;
+    END LOOP;
+
+    sout <= v_sum;
+  END PROCESS;
+
+  vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
+
+END ARCHITECTURE behavioral;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pw2ana is
+    port(
+        terminal ana_out : electrical;
+        terminal pw_in : electrical
+    );
+end pw2ana;
+
+architecture pw2ana of pw2ana is
+    -- Component declarations
+    -- Signal declarations
+    signal bus_servo : std_logic_vector(0 to 11);
+    signal XSIG010008 : std_logic;
+    signal XSIG010013 : std_logic;
+    signal XSIG010019 : std_logic;
+    signal XSIG010020 : std_logic;
+    signal XSIG010021 : std_logic;
+    signal XSIG010022 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    counter_rudder : entity work.counter_12
+        port map(
+            enable => XSIG010022,
+            cnt => bus_servo,
+            reset => XSIG010021,
+            clk => XSIG010008
+        );
+    XCMP3 : entity work.a2d_bit(ideal)
+        port map(
+            D => XSIG010022,
+            A => pw_in
+        );
+    clk_en_rudder : entity work.clock_en(ideal)
+        generic map(
+            pw => 500ns
+        )
+        port map(
+            CLOCK_OUT => XSIG010008,
+            enable => XSIG010022
+        );
+    XCMP5 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => XSIG010022,
+            output => XSIG010013
+        );
+    XCMP8 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => XSIG010020,
+            output => XSIG010021
+        );
+    XCMP9 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => XSIG010022,
+            output => XSIG010019
+        );
+    or_rudder : entity work.or2(ideal)
+        port map(
+            in1 => XSIG010022,
+            in2 => XSIG010019,
+            output => XSIG010020
+        );
+    DA1 : entity work.d2a_nbit(behavioral)
+        generic map(
+            vmax => 4.8,
+            high_bit => 9,
+            low_bit => 0
+        )
+        port map(
+            bus_in => bus_servo,
+            ana_out => ana_out,
+            latch => XSIG010013
+        );
+end pw2ana;
+--
+
+-- 12-bit digital comparator model
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+entity dig_cmp is
+port
+(
+      eq : out std_logic := '0';
+	  in1 : in std_logic_vector (0 to 11);
+	  in2 : in std_logic_vector (0 to 11);
+	  latch_in1 : in std_logic := '0'; -- Currently unused
+	  latch_in2 : in std_logic := '0';
+	  cmp : in std_logic := '0';
+	  clk : in std_logic
+	  );
+
+end entity dig_cmp ;
+
+architecture simple of dig_cmp is
+
+begin
+
+	compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
+	variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
+  		BEGIN
+		if latch_in2 = '1' then -- in2 data is latched and stored
+			in2_hold := in2;
+		end if;
+		if cmp = '1' then
+			if in1 = in2_hold then -- latched in2 checked against current in1
+				eq <= '0';
+			else eq <= '1';
+			end if;
+		end if;
+  	END PROCESS;
+end architecture simple;
+
+-- Set/reset flip flop
+-- When S goes high, Q is set high until reset
+-- When R goes high, Q is set low until set
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sr_ff is
+port
+(
+      S : in std_logic ;
+      R : in std_logic ;
+	Q : out std_logic 
+);
+
+end sr_ff ;
+
+architecture simple of sr_ff is
+begin
+
+ set_reset: PROCESS(S, R) IS  
+
+   BEGIN
+--	assert S='1' nand R='1' -- Warning if both inputs are high
+--		report "S and R are both active. Use with caution"
+--		severity warning;
+	if S'event AND S = '1' then
+		Q <= '1';
+	end if;
+	if R'event AND R = '1' then
+		Q <= '0';
+	end if;     
+   END PROCESS set_reset; 
+
+end;
+--
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+
+ENTITY state_mach_rcvr IS
+    PORT (
+          clk_50 : IN std_logic;
+          clk_100k : IN std_logic;
+          ser_done : IN std_logic;
+          par_det : IN std_logic;
+          frm_det : IN std_logic;
+          clk_6k : IN std_logic;
+          start_pulse : IN std_logic;
+          dly_done : IN std_logic;
+          s2p_rst : OUT std_logic;
+          s2p_en : OUT std_logic;
+          cnt1_en : OUT std_logic;
+          cnt1_rst : OUT std_logic;
+          cmp1_ltch1 : OUT std_logic;
+          cmp1_ltch2 : OUT std_logic;
+          cnt2_en : OUT std_logic;
+          cnt2_rst : OUT std_logic;
+          cmp2_ltch1 : OUT std_logic;
+          cmp2_ltch2 : OUT std_logic;
+          da_latch : OUT std_logic;
+          ser_cnt : OUT std_logic;
+          dly_cnt : OUT std_logic;
+          par_oe : OUT std_logic);
+
+END state_mach_rcvr;
+
+ARCHITECTURE state_diagram OF state_mach_rcvr IS
+
+    ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+    TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
+           , s_bit, par1, par2);
+    SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
+
+
+BEGIN 
+
+sm1: 
+  PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det) 
+  BEGIN
+
+    CASE CS_state_mach_rcvr_sm1 IS
+      WHEN V_begin =>
+        cnt1_en <= ('0');
+        cnt1_rst <= ('1');
+        cmp1_ltch1 <= ('0');
+        cmp1_ltch2 <= ('0');
+        cnt2_en <= ('0');
+        cnt2_rst <= ('1');
+        cmp2_ltch1 <= ('0');
+        cmp2_ltch2 <= ('0');
+        s2p_en <= ('1');
+        s2p_rst <= ('0');
+        da_latch <= ('0');
+        ser_cnt <= ('0');
+        dly_cnt <= ('0');
+        par_oe <= ('0');
+
+        IF ((frm_det = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= s_bit;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= V_begin;
+        END IF;
+
+      WHEN cnt =>
+        ser_cnt <= ('1');
+        cnt1_rst <= ('0');
+        cnt2_rst <= ('0');
+
+        IF ((ser_done = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= par1;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= cnt;
+        END IF;
+
+      WHEN ch1 =>
+        cmp1_ltch2 <= ('1');
+        ser_cnt <= ('0');
+        dly_cnt <= ('1');
+
+        IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
+          NS_state_mach_rcvr_sm1 <= rst1;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= ch1;
+        END IF;
+
+      WHEN rst1 =>
+        cmp1_ltch2 <= ('0');
+        ser_cnt <= ('1');
+        dly_cnt <= ('0');
+        par_oe <= ('0');
+
+        IF ((ser_done = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= par2;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= rst1;
+        END IF;
+
+      WHEN ch2 =>
+        cmp2_ltch2 <= ('1');
+        ser_cnt <= ('0');
+        da_latch <= ('1');
+          NS_state_mach_rcvr_sm1 <= rst2;
+
+      WHEN rst2 =>
+        cmp2_ltch2 <= ('0');
+        s2p_en <= ('0');
+        par_oe <= ('0');
+        da_latch <= ('0');
+          NS_state_mach_rcvr_sm1 <= cnt_cmp;
+
+      WHEN cnt_cmp =>
+        cnt1_en <= ('1');
+        cmp1_ltch1 <= ('1');
+        cnt2_en <= ('1');
+        cmp2_ltch1 <= ('1');
+          NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+      WHEN rst_cnt =>
+        cnt1_en <= ('0');
+        cmp1_ltch1 <= ('0');
+        cnt2_en <= ('0');
+        cmp2_ltch1 <= ('0');
+          NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+      WHEN s_bit =>
+
+        IF ((start_pulse = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= cnt;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= s_bit;
+        END IF;
+
+      WHEN par1 =>
+        par_oe <= ('1');
+
+        IF ((par_det = '0')) THEN
+          NS_state_mach_rcvr_sm1 <= ch1;
+        ELSIF ((par_det = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= rst1;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= par1;
+        END IF;
+
+      WHEN par2 =>
+        par_oe <= ('1');
+
+        IF ((par_det = '0')) THEN
+          NS_state_mach_rcvr_sm1 <= ch2;
+        ELSIF ((par_det = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= rst2;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= par2;
+        END IF;
+
+    END CASE;
+
+  END PROCESS; 
+
+sm1_CTL:
+  PROCESS (clk_100k, clk_50)
+  BEGIN
+
+    IF (clk_100k'event AND clk_100k='1')  THEN 
+        IF (clk_50= '1' ) THEN 
+            CS_state_mach_rcvr_sm1 <= V_begin;
+        ELSE
+            CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
+        END IF;
+    END IF;
+
+  END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt_rcvr is
+    port(
+        cmp1_ltch1 : out std_logic;
+        cmp2_ltch1 : out std_logic;
+        s2p_en : out std_logic;
+        s2p_rst : out std_logic;
+        frm_det : in std_logic;
+        par_det : in std_logic;
+        clk_100k : in std_logic;
+        clk_6k : in std_logic;
+        clk_50 : in std_logic;
+        start_pulse : in std_logic;
+        cnt1_en : out std_logic;
+        cnt1_rst : out std_logic;
+        cmp1_ltch2 : out std_logic;
+        cnt2_en : out std_logic;
+        cnt2_rst : out std_logic;
+        cmp2_ltch2 : out std_logic;
+        da_latch : out std_logic;
+        par_oe : out std_logic
+    );
+end sm_cnt_rcvr;
+
+architecture sm_cnt_rcvr of sm_cnt_rcvr is
+    -- Component declarations
+    -- Signal declarations
+    signal ser_cnt : std_logic;
+    signal XSIG010002 : std_logic;
+    signal XSIG010145 : std_logic;
+    signal XSIG010146 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    bit_cnt3 : entity work.bit_cnt(behavioral)
+        generic map(
+            count => 2
+        )
+        port map(
+            bit_in => XSIG010145,
+            clk => clk_6k,
+            dly_out => XSIG010146
+        );
+    bit_cnt4 : entity work.bit_cnt(behavioral)
+        generic map(
+            count => 10
+        )
+        port map(
+            bit_in => ser_cnt,
+            clk => clk_6k,
+            dly_out => XSIG010002
+        );
+    state_mach_rcvr8 : entity work.state_mach_rcvr
+        port map(
+            clk_100k => clk_100k,
+            clk_50 => clk_50,
+            s2p_rst => s2p_rst,
+            s2p_en => s2p_en,
+            cnt1_en => cnt1_en,
+            cnt1_rst => cnt1_rst,
+            cmp1_ltch1 => cmp1_ltch1,
+            cmp1_ltch2 => cmp1_ltch2,
+            cnt2_en => cnt2_en,
+            cnt2_rst => cnt2_rst,
+            cmp2_ltch1 => cmp2_ltch1,
+            cmp2_ltch2 => cmp2_ltch2,
+            da_latch => da_latch,
+            ser_cnt => ser_cnt,
+            ser_done => XSIG010002,
+            par_det => par_det,
+            frm_det => frm_det,
+            clk_6k => clk_6k,
+            start_pulse => start_pulse,
+            dly_done => XSIG010146,
+            dly_cnt => XSIG010145,
+            par_oe => par_oe
+        );
+end sm_cnt_rcvr;
+--
+-- level_set.vhd 
+-- Set digital output "level" with parameter "logic_val" (default is '1')
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set IS
+
+  GENERIC (
+    logic_val : std_logic := '1');     
+
+  PORT (
+    level : OUT std_logic);
+
+END ENTITY level_set;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set IS
+
+BEGIN
+
+  level <= logic_val;
+  
+END ARCHITECTURE ideal;
+
+--
+-- Serial to parallel data converter
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity ser2par is
+port
+(
+      par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
+      clk : in std_logic ;
+      load_en : in std_logic ;
+      ser_in : in std_logic ;
+      reset : in std_logic 
+);
+
+begin
+
+end ser2par;
+
+architecture a1 of ser2par is
+BEGIN 
+	sr_sm: PROCESS (load_en, clk, reset, ser_in)	
+	BEGIN
+		if (reset = '1' and load_en = '1') then
+			par_out <= "000000000000";  -- Reset the parallel data out
+			
+		elsif  (reset = '0' and load_en = '1') then
+			if (clk'event and clk = '1') then 
+				
+				-- The register will shift when load is enabled 
+				-- and will shift at rising edge of clock
+				
+				par_out(0) <= ser_in; -- Input data shifts into bit 0
+				par_out(1) <= par_out(0);
+				par_out(2) <= par_out(1);
+				par_out(3) <= par_out(2);
+				par_out(4) <= par_out(3);
+				par_out(5) <= par_out(4);
+				par_out(6) <= par_out(5);
+				par_out(7) <= par_out(6);
+				par_out(8) <= par_out(7);
+				par_out(9) <= par_out(8);
+				par_out(10) <= par_out(9);
+				par_out(11) <= par_out(10); 
+
+			end if;
+
+		else
+			par_out <= "ZZZZZZZZZZZZ"; -- No change in output. Tri-state if load_en = 0.		
+		end if;			
+	END PROCESS;
+end;
+
+--
+-- This model ouputs a '1' when a specific bit pattern is encountered
+-- Otherwise, it outputs a zero
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_det is
+port
+(
+	  bus_in : in std_logic_vector (0 to 11);
+	  clk : in std_logic;
+	  frm_bit : out std_logic := '0' -- Initialize output to zero
+	  );
+
+end entity frame_det;
+
+architecture simple of frame_det is
+begin
+	enbl: PROCESS (bus_in, clk) -- Sensitivity list
+  		BEGIN 
+		if bus_in = "010101010101" then -- This is the pre-defined bit pattern
+			if clk'event AND clk = '0' then -- Output updated synchronously
+				frm_bit <= '1';
+			end if;
+		else frm_bit <= '0';
+		end if;
+  	END PROCESS;
+end architecture simple;
+
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_det is
+    port(
+        bus_in : in std_logic_vector(0 to 11);
+        par_bit : out std_logic;
+        oe : in std_logic
+    );
+end parity_det;
+
+architecture parity_det of parity_det is
+    -- Component declarations
+    -- Signal declarations
+    signal XSIG010010 : std_logic;
+    signal XSIG010011 : std_logic;
+    signal XSIG010012 : std_logic;
+    signal XSIG010013 : std_logic;
+    signal XSIG010014 : std_logic;
+    signal XSIG010015 : std_logic;
+    signal XSIG010016 : std_logic;
+    signal XSIG010017 : std_logic;
+    signal XSIG010019 : std_logic;
+    signal XSIG010057 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    XCMP1 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(1),
+            in2 => bus_in(2),
+            output => XSIG010010
+        );
+    XCMP2 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(3),
+            in2 => bus_in(4),
+            output => XSIG010011
+        );
+    XCMP3 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(5),
+            in2 => bus_in(6),
+            output => XSIG010012
+        );
+    XCMP4 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(7),
+            in2 => bus_in(8),
+            output => XSIG010013
+        );
+    XCMP5 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(9),
+            in2 => bus_in(10),
+            output => XSIG010016
+        );
+    XCMP6 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010010,
+            in2 => XSIG010011,
+            output => XSIG010014
+        );
+    XCMP7 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010012,
+            in2 => XSIG010013,
+            output => XSIG010015
+        );
+    XCMP8 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010014,
+            in2 => XSIG010015,
+            output => XSIG010017
+        );
+    XCMP9 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010017,
+            in2 => XSIG010016,
+            output => XSIG010019
+        );
+    XCMP10 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010019,
+            in2 => bus_in(0),
+            output => XSIG010057
+        );
+    XCMP12 : entity work.and2(ideal)
+        port map(
+            in1 => oe,
+            in2 => XSIG010057,
+            output => par_bit
+        );
+end parity_det;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TDM_Demux_dbg is
+    port(
+        s2p_en : in std_logic;
+        tdm_in : in std_logic;
+        clk_6k : in std_logic;
+        s2p_rst : in std_logic;
+        par_det : out std_logic;
+        frm_det : out std_logic;
+        da_latch : in std_logic;
+        par_oe : in std_logic;
+        data_bus : out std_logic_vector(1 to 10);
+        start_bit : out std_logic
+    );
+end TDM_Demux_dbg;
+
+architecture TDM_Demux_dbg of TDM_Demux_dbg is
+    -- Component declarations
+    -- Signal declarations
+    terminal d2a_out : electrical;
+    signal rcvr_bus : std_logic_vector(0 to 11);
+begin
+    -- Signal assignments
+    data_bus(1) <= rcvr_bus(1);
+    data_bus(2) <= rcvr_bus(2);
+    data_bus(3) <= rcvr_bus(3);
+    data_bus(4) <= rcvr_bus(4);
+    data_bus(5) <= rcvr_bus(5);
+    data_bus(6) <= rcvr_bus(6);
+    data_bus(7) <= rcvr_bus(7);
+    data_bus(8) <= rcvr_bus(8);
+    data_bus(9) <= rcvr_bus(9);
+    data_bus(10) <= rcvr_bus(10);
+    start_bit <= rcvr_bus(0);
+    -- Component instances
+    s2p1 : entity work.ser2par(a1)
+        port map(
+            par_out => rcvr_bus,
+            clk => clk_6k,
+            load_en => s2p_en,
+            ser_in => tdm_in,
+            reset => s2p_rst
+        );
+    frm_det1 : entity work.frame_det(simple)
+        port map(
+            bus_in => rcvr_bus,
+            frm_bit => frm_det,
+            clk => clk_6k
+        );
+    par_det1 : entity work.parity_det
+        port map(
+            bus_in => rcvr_bus,
+            par_bit => par_det,
+            oe => par_oe
+        );
+    XCMP113 : entity work.d2a_nbit(behavioral)
+        generic map(
+            low_bit => 1,
+            high_bit => 10,
+            vmax => 4.8
+        )
+        port map(
+            bus_in => rcvr_bus(1 to 10),
+            ana_out => d2a_out,
+            latch => da_latch
+        );
+end TDM_Demux_dbg;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Decode_PW is
+    port(
+        bit_stream_in : in std_logic;
+        terminal ch1_pw : electrical;
+        terminal ch2_pw : electrical
+    );
+end Decode_PW;
+
+architecture Decode_PW of Decode_PW is
+    -- Component declarations
+    -- Signal declarations
+    signal cmp_bus : std_logic_vector(0 to 11);
+    signal cnt1 : std_logic_vector(0 to 11);
+    signal cnt2 : std_logic_vector(0 to 11);
+    signal rud_clk : std_logic;
+    signal rud_cmp : std_logic;
+    signal rud_eq : std_logic;
+    signal rud_ff_rst : std_logic;
+    signal rud_ff_set : std_logic;
+    signal rud_ltch1 : std_logic;
+    signal rud_ltch2 : std_logic;
+    signal XSIG010225 : std_logic;
+    signal XSIG010228 : std_logic;
+    signal XSIG010229 : std_logic;
+    signal XSIG010256 : std_logic;
+    signal XSIG010266 : std_logic;
+    signal XSIG010267 : std_logic;
+    signal XSIG010268 : std_logic;
+    signal XSIG010289 : std_logic;
+    signal XSIG010315 : std_logic;
+    signal XSIG010339 : std_logic;
+    signal XSIG010357 : std_logic;
+    signal XSIG010371 : std_logic;
+    signal XSIG010373 : std_logic;
+    signal XSIG010383 : std_logic;
+    signal XSIG010384 : std_logic;
+    signal XSIG010385 : std_logic;
+    signal XSIG010386 : std_logic;
+    signal XSIG010390 : std_logic;
+    signal XSIG010433 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    cntr1 : entity work.counter_12
+        port map(
+            enable => XSIG010384,
+            cnt => cnt1,
+            reset => XSIG010357,
+            clk => XSIG010433
+        );
+    cntr2 : entity work.counter_12
+        port map(
+            enable => rud_cmp,
+            cnt => cnt2,
+            reset => XSIG010385,
+            clk => rud_clk
+        );
+    cmp1 : entity work.dig_cmp(simple)
+        port map(
+            in1 => cnt1,
+            eq => XSIG010371,
+            clk => XSIG010433,
+            in2 => cmp_bus,
+            cmp => XSIG010384,
+            latch_in1 => XSIG010256,
+            latch_in2 => XSIG010383
+        );
+    cmp2 : entity work.dig_cmp(simple)
+        port map(
+            in1 => cnt2,
+            eq => rud_eq,
+            clk => rud_clk,
+            in2 => cmp_bus,
+            cmp => rud_cmp,
+            latch_in1 => rud_ltch1,
+            latch_in2 => rud_ltch2
+        );
+    clk_1M2 : entity work.clock_en(ideal)
+        generic map(
+            pw => 500 ns
+        )
+        port map(
+            CLOCK_OUT => rud_clk,
+            enable => rud_cmp
+        );
+    clk_1M1 : entity work.clock_en(ideal)
+        generic map(
+            pw => 500 ns
+        )
+        port map(
+            CLOCK_OUT => XSIG010433,
+            enable => XSIG010384
+        );
+    XCMP134 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010371,
+            A => ch1_pw
+        );
+    XCMP135 : entity work.d2a_bit(ideal)
+        port map(
+            D => rud_eq,
+            A => ch2_pw
+        );
+    XCMP137 : entity work.SR_FF(simple)
+        port map(
+            S => rud_ff_set,
+            R => rud_ff_rst,
+            Q => rud_cmp
+        );
+    XCMP138 : entity work.inverter(ideal)
+        port map(
+            input => rud_eq,
+            output => rud_ff_rst
+        );
+    XCMP139 : entity work.SR_FF(simple)
+        port map(
+            S => XSIG010373,
+            R => XSIG010339,
+            Q => XSIG010384
+        );
+    XCMP140 : entity work.inverter(ideal)
+        port map(
+            input => XSIG010371,
+            output => XSIG010339
+        );
+    rc_clk2 : entity work.rc_clk
+        port map(
+            clk_50 => XSIG010289,
+            clk_6K => XSIG010225,
+            clk_100k => XSIG010315
+        );
+    sm_rcvr1 : entity work.sm_cnt_rcvr
+        port map(
+            cnt1_en => XSIG010373,
+            cmp1_ltch1 => XSIG010256,
+            cnt2_rst => XSIG010385,
+            clk_100k => XSIG010315,
+            cnt1_rst => XSIG010357,
+            cnt2_en => rud_ff_set,
+            cmp2_ltch1 => rud_ltch1,
+            frm_det => XSIG010229,
+            par_det => XSIG010228,
+            s2p_en => XSIG010266,
+            s2p_rst => XSIG010267,
+            clk_6k => XSIG010225,
+            clk_50 => XSIG010289,
+            da_latch => XSIG010268,
+            cmp1_ltch2 => XSIG010383,
+            cmp2_ltch2 => rud_ltch2,
+            start_pulse => XSIG010390,
+            par_oe => XSIG010386
+        );
+    XCMP155 : entity work.level_set(ideal)
+        generic map(
+            logic_val => '0'
+        )
+        port map(
+            level => cmp_bus(11)
+        );
+    XCMP157 : entity work.TDM_Demux_dbg
+        port map(
+            data_bus => cmp_bus(0 to 9),
+            tdm_in => bit_stream_in,
+            clk_6k => XSIG010225,
+            s2p_en => XSIG010266,
+            s2p_rst => XSIG010267,
+            da_latch => XSIG010268,
+            frm_det => XSIG010229,
+            par_det => XSIG010228,
+            par_oe => XSIG010386,
+            start_bit => XSIG010390
+        );
+    XCMP172 : entity work.level_set(ideal)
+        generic map(
+            logic_val => '1'
+        )
+        port map(
+            level => cmp_bus(10)
+        );
+end Decode_PW;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CS1 is
+end tb_CS1;
+
+architecture TB_CS1 of tb_CS1 is
+    -- Component declarations
+    -- Signal declarations
+    terminal rudder : electrical;
+    terminal rudder_out : electrical;
+    terminal rudder_servo : electrical;
+    signal tdm_stream2 : std_logic;
+    terminal throttle : electrical;
+    terminal throttle_out : electrical;
+    terminal throttle_servo : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    Digitize_Encode1 : entity work.Digitize_Encode
+        port map(
+            ch2_in => rudder,
+            ch1_in => throttle,
+            tdm_out => tdm_stream2
+        );
+    throttle_1 : entity work.stick(ideal)
+        generic map(
+            freq => 1.0,
+            amplitude => 2.397,
+            phase => 0.0,
+            offset => 2.397
+        )
+        port map(
+            v_out => throttle
+        );
+    rudder_1 : entity work.stick(ideal)
+        generic map(
+            offset => 2.397,
+            phase => 90.0,
+            amplitude => 2.397,
+            freq => 1.0
+        )
+        port map(
+            v_out => rudder
+        );
+    pw2ana1 : entity work.pw2ana
+        port map(
+            ana_out => throttle_out,
+            pw_in => throttle_servo
+        );
+    pw2ana2 : entity work.pw2ana
+        port map(
+            ana_out => rudder_out,
+            pw_in => rudder_servo
+        );
+    Decode_PW10 : entity work.Decode_PW
+        port map(
+            bit_stream_in => tdm_stream2,
+            ch2_pw => rudder_servo,
+            ch1_pw => throttle_servo
+        );
+end TB_CS1;
+--
\ No newline at end of file
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_a2d_d2a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_a2d_d2a.vhd
new file mode 100644
index 0000000..0a9d3f7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS1_Mixed_Sig/tb_a2d_d2a.vhd
@@ -0,0 +1,134 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_a2d_d2a is
+
+end tb_a2d_d2a;
+
+architecture TB_a2d_d2a of tb_a2d_d2a is
+    -- Component declarations
+    -- Signal declarations
+	terminal ana_out : electrical;
+	terminal analog_in : electrical;
+	signal clock : std_ulogic;
+	signal start : std_ulogic;
+	signal eoc : std_ulogic;
+	signal eoc_logic: std_logic;
+	signal oe : std_logic;
+	signal data_bus : std_ulogic_vector(0 to 9);
+	signal latch : std_ulogic;
+	signal latch_logic : std_logic;
+	signal nn_eoc : std_logic;
+	signal or_out : std_logic;
+	signal n_eoc : std_logic;
+begin
+    -- Signal assignments
+	eoc_logic <= To_X01Z(eoc);	-- convert std_ulogic to std_logic
+	latch <= To_X01(latch_logic);	-- convert std_logic to std_ulogic
+    -- Component instances
+    ad1 : entity work.a2d_nbit(sar)
+        port map(
+            dout => data_bus,
+            ain => analog_in,
+            clk => clock,
+            start => start,
+            eoc => eoc
+        );
+    v1 : entity work.v_sine(ideal)
+        generic map(
+            freq => 2.5,
+            amplitude => 2.5,
+			offset => 2.5,
+            phase => 0.0
+        )
+        port map(
+            pos => analog_in,
+            neg => ELECTRICAL_REF
+        );
+    inv1 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => or_out,
+            output => oe
+        );
+    inv2 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => n_eoc,
+            output => nn_eoc
+        );
+    or1 : entity work.or2(ideal)
+        port map(
+            in1 => n_eoc,
+            in2 => nn_eoc,
+            output => or_out
+        );
+    inv3 : entity work.inverter(ideal)
+        generic map(
+            delay => 0us
+        )
+        port map(
+            input => eoc_logic,
+            output => n_eoc
+        );
+    U2 : entity work.buff(ideal)
+        generic map(
+            delay => 250ns
+        )
+        port map(
+            input => oe,
+            output => latch_logic
+        );
+    da1 : entity work.dac_10_bit(behavioral)
+        port map(
+            bus_in => data_bus,
+            analog_out => ana_out,
+            clk => latch
+        );
+  -- clock
+    P_clock :
+    process
+    begin
+        clock <= '1';
+        wait for 50.0 us;
+        clock <= '0';
+        wait for 50.0 us;
+    end process P_clock;
+
+  -- start
+    P_start :
+    process
+    begin
+        start <= '0';
+        wait for 2.0 ms;
+        start <= '1';
+        wait for 0.2 ms;
+        start <= '0';
+        wait for 2.0 ms;
+    end process P_start;
+
+
+end TB_a2d_d2a;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/DC_Motor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/DC_Motor.vhd
new file mode 100644
index 0000000..c25cacd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/DC_Motor.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.mechanical_systems.all;
+use ieee_proposed.electrical_systems.all;
+
+entity DC_Motor is
+  generic ( r_wind : resistance;  -- motor winding resistance [ohm]
+            kt : real;		  -- torque coefficient [N*m/amp]
+            l : inductance;	  -- winding inductance [henrys]
+            d : real;		  -- damping coefficient [N*m/(rad/sec)]
+            j : mmoment_i );	  -- moment of inertia [kg*meter**2]
+  port ( terminal p1, p2 : electrical;
+         terminal shaft_rotv : rotational_v);
+end entity DC_Motor;
+
+----------------------------------------------------------------
+
+architecture basic of DC_Motor is
+
+  quantity v across i through p1 to p2;
+  quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+  torq == -1.0 * kt * i + d * w + j * w'dot;
+  v  == kt * w + i * r_wind + l * i'dot;
+
+end architecture basic;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain.vhd
new file mode 100644
index 0000000..90f1f04
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity gain is
+  generic ( k : real := 1.0 );  -- gain multiplier
+  port ( quantity input : in real;
+         quantity output : out real );
+end entity gain;
+
+----------------------------------------------------------------
+
+architecture simple of gain is
+begin
+
+  output == k * input;
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain_e.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain_e.vhd
new file mode 100644
index 0000000..7054f2b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gain_e.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity gain_e is
+  generic ( k : real := 1.0);  -- gain multiplier
+  port ( terminal input : electrical;
+         terminal output : electrical );
+end entity gain_e;
+
+----------------------------------------------------------------
+
+architecture simple of gain_e is
+
+  quantity vin across input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+
+begin
+
+  vout == k * vin;
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gear_rv_r.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gear_rv_r.vhd
new file mode 100644
index 0000000..39ac481
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/gear_rv_r.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.mechanical_systems.all;
+                        
+entity gear_rv_r is
+  generic ( ratio : real := 1.0 );  -- gear ratio (revs of shaft2 for 1 rev of shaft1)
+                            	    -- note: can be negative, if shaft polarity changes
+  port ( terminal rotv1 : rotational_v;  -- rotational velocity terminal
+         terminal rot2 : rotational );	 -- rotational angle terminal
+end entity gear_rv_r;
+
+----------------------------------------------------------------
+
+architecture ideal of gear_rv_r is
+
+  quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+  quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+  theta  == ratio * w1'integ;           -- output is angle (integral of w1)
+  torq_vel == -1.0 * torq_ang * ratio;  -- input torque as function of output angle
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/index-ams.txt
new file mode 100644
index 0000000..241855f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/index-ams.txt
@@ -0,0 +1,77 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                Chapter 14 - Case Study 2: Mixed-Technology Focus
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+gain.vhd                                        entity gain                             simple                          Figure 14-3
+gain_e.vhd                                      entity gain_e                           simple                          Figure 14-4
+sum2.vhd                                        entity sum2                             simple                          Figure 14-6
+limiter.vhd                                     entity limiter                          simple                          Figure 14-7
+lpf_1.vhd                                       entity lpf_1                            simple                          Figure 14-9
+lead_lag.vhd                                    entity lead_lag                         simple                          Figure 14-18
+DC_Motor.vhd                                    entity DC_Motor                         basic                           Figure 14-21
+gear_rv_r.vhd                                   entity gear_rv_r                        ideal                           Figure 14-22
+stop_r.vhd                                      entity stop_r                           ideal                           Fgiure 14-23
+lead_lag_ztf.vhd                                entity lead_lag_ztf                     simple                          Figure 14-27
+lead_lag_diff.vhd                               entity lead_lag_diff                    bhv                             Figure 14-30
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_CS2_Mech_Domain.vhd                          entity sum2_e                           simple
+--                                              entity gain_e                           simple
+--                                              entity lead_lag_e                       simple
+--                                              entity limiter_2_e                      simple 
+--                                              entity rudder_servo                     rudder_servo
+--                                              entity gear_rv_r                        ideal
+--                                              entity rot2v                            bhv
+--                                              entity horn_r2t                         bhv
+--                                              entity horn_t2r                         bhv
+--                                              entity DC_Motor                         basic
+--                                              entity stop_r                           ideal
+--                                              entity tran_linkage                     a1
+--                                              entity rudder                           bhv
+--                                              entity v_sine                           ideal
+--                                              entity TB_CS2_Mech_Domain               TB_CS2_Mech_Domain
+tb_CS2_S_Domain.vhd                             entity v_sine                           ideal
+--                                              entity sum2_e                           simple
+--                                              entity lead_lag_e                       simple
+--                                              entity gain_e                           simple
+--                                              entity limiter_2_e                      simple
+--                                              entity ctl_horn_e                       bhv
+--                                              entity rudder_horn_e                    bhv
+--                                              entity integ_1_e                        simple
+--                                              entity lpf_1_e                          simple
+--                                              entity TB_CS2_S_Domain                  TB_CS2_S_Domain
+tb_CS2_Z_Domain_Diff.vhd                        entity gear_rv_r                        ideal
+--                                              entity rot2v                            bhv
+--                                              entity horn_r2t                         bhv
+--                                              entity horn_t2r                         bhv
+--                                              entity DC_Motor                         basic
+--                                              entity stop_r                           ideal
+--                                              entity tran_linkage                     a1
+--                                              entity rudder                           bhv
+--                                              entity sum2_e                           simple
+--                                              entity gain_e                           simple
+--                                              entity limiter_2_e                      simple
+--                                              entity clock                            ideal
+--                                              entity lead_lag_diff                    bhv
+--                                              entity rudder_servo_z                   rudder_servo_z
+--                                              entity v_sine                           ideal
+--                                              entity TB_CS2_Z_Domain_Diff             TB_CS2_Z_Domain_Diff
+tb_CS2_Z_Domain_ZTF.vhd                         entity gear_rv_r                        ideal
+--                                              entity rot2v                            bhv
+--                                              entity horn_r2t                         bhv
+--                                              entity horn_t2r                         bhv
+--                                              entity DC_Motor                         basic
+--                                              entity stop_r                           ideal
+--                                              entity tran_linkage                     a1
+--                                              entity rudder                           bhv
+--                                              entity sum2_e                           simple
+--                                              entity gain_e                           simple
+--                                              entity limiter_2_e                      simple
+--                                              entity lead_lag_ztf                     simple
+--                                              entity rudder_servo_ztf                 rudder_servo_ztf
+--                                              entity v_sine                           ideal
+--                                              entity TB_CS2_Z_Domain_ZTF              TB_CS2_Z_Domain_ZTF
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag.vhd
new file mode 100644
index 0000000..53c27dc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+
+entity lead_lag is
+  generic ( k : real := 400.0;     -- gain multiplier
+            f1 : real := 5.0;	   -- break frequency (zero)
+            f2 : real := 2000.0);  -- break frequency (pole)
+  port ( quantity input : in real;
+         quantity output : out real);
+end entity lead_lag;
+
+----------------------------------------------------------------
+
+architecture simple of lead_lag is
+
+  constant num : real_vector := (f1 * math_2_pi, 1.0);
+  constant den : real_vector := (f2 * math_2_pi, 1.0);
+
+begin
+
+  output == k * input'ltf(num, den);
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_diff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_diff.vhd
new file mode 100644
index 0000000..8692420
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_diff.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity lead_lag_diff is
+  port ( signal clk : in std_logic;  -- clock
+         quantity input : in real;
+         quantity output : out real );
+end entity lead_lag_diff;
+
+----------------------------------------------------------------
+
+architecture bhv of lead_lag_diff is
+  
+  constant k : real := 400.0;  -- normalize gain
+  signal z_out : real := 0.0;
+        
+begin
+  
+  proc : process (clk)
+    variable zi_dly1 : real := 0.0;  -- input delayed 1 clk cycle
+    variable zo_dly1 : real := 0.0;  -- output delayed 1 clk cycle
+    variable z_new : real := 0.0;    -- new output value this clk cycle
+  begin
+    zo_dly1 := z_out;  -- store previous output value
+    z_new := 0.6163507 * input - 0.6144184 * zi_dly1 + 0.2307692 * zo_dly1;
+    zi_dly1 := input;  -- store previous input value
+    z_out <= z_new;
+  end process;
+        
+  output == k * z_out'ramp(100.0e-9);  -- ensure continuous transitions on output
+        
+end bhv;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd
new file mode 100644
index 0000000..aa4c9b5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity lead_lag_ztf is
+  
+  generic ( a1 : real := 2.003140;
+            a2 : real := -1.996860;
+            b1 : real := 3.250000;
+            b2 : real := -0.750000;
+            k : real := 400.0;		 -- normalizing gain
+            tsampl : real := 0.1e-3;	 -- sample period
+            init_delay : real := 0.0 );  -- optional delay
+        
+  port ( quantity input : in real;
+         quantity output : out real );
+        
+end entity lead_lag_ztf;
+
+----------------------------------------------------------------
+
+architecture simple of lead_lag_ztf is
+
+  constant num: real_vector := (a1, a2);
+  constant den: real_vector := (b1, b2);
+
+begin
+
+  output == k * input'ztf(num, den, tsampl, init_delay);  -- implement transfer function
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd
new file mode 100644
index 0000000..19ed07a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/limiter.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity limiter is
+  generic ( limit_high : real := 4.8;	 -- upper limit
+            limit_low : real := -4.8 );  -- lower limit
+  port ( quantity input : in real;
+         quantity output : out real);					
+end entity limiter;
+
+----------------------------------------------------------------
+
+architecture simple of limiter is
+  constant slope : real := 1.0e-4;
+begin
+
+  if input > limit_high use    -- upper limit exceeded, so limit input signal
+    output == limit_high + slope*(input - limit_high);
+  elsif input < limit_low use  -- lower limit exceeded, so limit input signal
+    output == limit_low + slope*(input - limit_low);
+  else		               -- no limit exceeded, so pass input signal as is
+    output == input;
+  end use;
+
+  break on input'above(limit_high), input'above(limit_low);
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lpf_1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lpf_1.vhd
new file mode 100644
index 0000000..4825ca2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/lpf_1.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity lpf_1 is
+  generic ( fp : real; 		   -- pole freq in hertz
+            gain : real := 1.0 );  -- filter gain
+  port ( quantity input : in real;
+         quantity output : out real);
+end entity lpf_1;
+
+----------------------------------------------------------------
+
+library ieee;  use ieee.math_real.all;
+
+architecture simple of lpf_1 is
+
+  constant wp : real := math_2_pi*fp;
+  constant num : real_vector := (0 => wp * gain);  -- "0 =>" is needed to give
+                                                   -- vector index when only
+                                                   -- a single element is used.
+  constant den : real_vector := (wp, 1.0);
+
+begin
+
+  output == input'ltf(num, den);
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd
new file mode 100644
index 0000000..4a6c037
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/stop_r.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.mechanical_systems.all;
+
+entity stop_r is
+  generic ( k_stop : real := 1.0e6;
+            ang_max : real := 1.05;
+            ang_min : real := -1.05;
+            damp_stop : real := 1.0e2 );
+  port ( terminal ang1, ang2 : rotational );
+end entity stop_r;
+
+----------------------------------------------------------------
+
+architecture ideal of stop_r is
+
+  quantity velocity : velocity;
+  quantity ang across trq through ang1 to ang2;
+
+begin
+
+  velocity == ang'dot;
+
+  if ang > ang_max use	   -- Hit upper stop, generate opposing torque
+    trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+  elsif ang > ang_min use  -- Between stops, no opposing torque
+    trq   == 0.0;
+  else		           -- Hit lower stop, generate opposing torque
+    trq   == k_stop * (ang - ang_min) + (damp_stop * velocity);
+  end use;
+
+  break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/sum2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/sum2.vhd
new file mode 100644
index 0000000..b60cfed
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/sum2.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity sum2 is
+  generic ( k1, k2 : real := 1.0 );  -- optional gain multipliers
+  port ( quantity in1, in2 : in real;
+         quantity output : out real );
+end entity sum2;
+
+----------------------------------------------------------------
+
+architecture simple of sum2 is
+begin
+
+  output == k1 * in1 + k2 * in2;  -- sum of inputs (with optional gain)
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd
new file mode 100644
index 0000000..a8eca95
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd
@@ -0,0 +1,812 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+	generic (k1, k2: real := 1.0);  -- Gain multipliers
+	port 	(	terminal in1, in2: electrical;
+			terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+  QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+  QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+	generic (
+		k: REAL := 1.0);  -- Gain multiplier
+	port 	(	terminal input : electrical;
+			terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+--  Transfer Function:
+--
+--                  (s + w1)         
+--    H(s) =  k *  ----------
+--                  (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lead_lag_e is
+	generic (
+		k: real := 1.0;  			-- Gain multiplier
+		f1: real := 10.0;			-- First break frequency (zero)
+		f2: real := 100.0);		-- Second break frequency (pole)
+	port 	(	terminal input: electrical;
+			terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+	quantity vin_temp : real;
+	constant w1 : real := f1*math_2_pi;
+	constant w2 : real := f2*math_2_pi;
+	constant num : real_vector := (w1, 1.0);                                                    
+	constant den : real_vector := (w2, 1.0);
+begin
+	vin_temp == vin;
+	vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+	generic (
+		limit_high : real := 4.8;	-- upper limit
+		limit_low : real := -4.8); 	-- lower limit
+	port (
+		terminal input: electrical;
+		terminal output: electrical);					
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+  	QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  	QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+	constant slope : real := 1.0e-4;
+begin
+	if vin > limit_high use	-- Upper limit exceeded, so limit input signal
+		vout == limit_high + slope*(vin - limit_high);
+	elsif vin < limit_low use	-- Lower limit exceeded, so limit input signal
+		vout == limit_low + slope*(vin - limit_low);
+	else		-- No limit exceeded, so pass input signal as is
+		vout == vin;
+	end use;
+	break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo is
+    port(
+        terminal servo_in : electrical;
+        terminal pos_fb : electrical;
+        terminal servo_out : electrical
+    );
+end rudder_servo;
+
+architecture rudder_servo of rudder_servo is
+    -- Component declarations
+    -- Signal declarations
+    terminal error : electrical;
+    terminal limit_in : electrical;
+    terminal ll_in : electrical;
+    terminal summer_fb : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    summer : entity work.sum2_e(simple)
+        port map(
+            in1 => servo_in,
+            in2 => summer_fb,
+            output => error
+        );
+    forward_gain : entity work.gain_e(simple)
+        generic map(
+            k => 100.0
+        )
+        port map(
+            input => error,
+            output => ll_in
+        );
+    lead_lag : entity work.lead_lag_e(simple)
+        generic map(
+            f2 => 2000.0,
+            f1 => 5.0,
+            k => 400.0
+        )
+        port map(
+            input => ll_in,
+            output => limit_in
+        );
+    fb_gain : entity work.gain_e(simple)
+        generic map(
+            k => -4.57
+        )
+        port map(
+            input => pos_fb,
+            output => summer_fb
+        );
+    XCMP21 : entity work.limiter_2_e(simple)
+        generic map(
+            limit_high => 4.8,
+            limit_low => -4.8
+        )
+        port map(
+            input => limit_in,
+            output => servo_out
+        );
+end rudder_servo;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : gear_rv_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/10/10  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+  generic(
+    ratio : real := 1.0);   -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+                            -- Note: can be negative, if shaft polarity changes
+
+  port ( terminal rotv1 : rotational_v;
+  		terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+  quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+  quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+  theta == ratio*w1'integ;
+  torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+  
+  generic (
+    k : real := 1.0);                -- optional gain
+
+  port (
+    terminal input   : rotational;  -- input terminal
+    terminal output    : electrical);   -- output terminal
+  
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref;     -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+  begin  -- bhv
+   v_out ==  k*rot_in; 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  tran =   R*sin(rot) 
+--
+-- Where pos = output translational position,
+-- R = horn radius, 
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+  
+  generic (
+    R   : real := 1.0);            		-- horn radius
+
+  port (
+    terminal theta    : ROTATIONAL;   	-- input angular position port
+    terminal pos   : TRANSLATIONAL);  	-- output translational position port
+     
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+  begin			-- bhv
+   tran == R*sin(rot);		-- Convert angle in to translational out
+   tran_frc == -rot_tq/R;	-- Convert torque in to force out 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  theta =   arcsin(pos/R) 
+--
+-- Where pos = input translational position,
+-- R = horn radius, 
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+  
+  generic (
+    R   : real := 1.0);            -- Rudder horn radius
+
+  port (
+    terminal pos    : translational;   -- input translational position port
+    terminal theta   : rotational);  -- output angular position port
+     
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+  begin  -- bhv
+   rot == arcsin(tran/R);	-- Convert translational to angle
+   rot_tq == -tran_frc*R;	-- Convert force to torque
+   
+end bhv;
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : DC_Motor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+  generic (
+    r_wind : resistance;                -- Motor winding resistance [Ohm]
+    kt     : real;                      -- Torque coefficient [N*m/Amp]
+    l      : inductance;                -- Winding inductance [Henrys]
+    d      : real;                      -- Damping coefficient [N*m/(rad/sec)]
+    j      : mmoment_i);                -- Moment of inertia [kg*meter**2]
+
+  port (terminal p1, p2 : electrical;
+        terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations:  V = Kt*W + I*Rwind + L*dI/dt
+--                   T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+  quantity v across i through p1 to p2;
+  quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+  torq == -1.0*kt*i + d*w + j*w'dot;
+  v  == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : stop_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- library IEEE;
+-- use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+  generic (
+    k_stop    : real;
+--    ang_max   : angle;
+--    ang_min   : angle := 0.0;
+	ang_max   : real;
+    ang_min   : real := 0.0;
+    damp_stop : real  := 0.000000001
+    );
+
+  port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+  quantity velocity : velocity;
+  quantity ang across trq through ang1 to ang2;
+
+begin
+
+  velocity == ang'dot;
+
+  if ang > ang_max use
+    trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+  elsif ang > ang_min use
+    trq   == 0.0;
+  else
+    trq   == k_stop * (ang - ang_min) + (damp_stop * velocity);
+  end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+      terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+  QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+  QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+   pos_2 == pos_1;		-- Pass position 
+   frc_2 == -frc_1;	-- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+--  Transfer Function:
+--                            
+--  torq =   -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+  
+  generic (
+    k   : real := 1.0;            -- Spring constant
+	theta_0 : real := 0.0);
+
+  port (
+    terminal rot    : rotational);   -- input rotational angle
+     
+end entity rudder;
+
+architecture bhv of rudder is
+
+  QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+  begin  -- bhv
+
+   torq == k*(theta - theta_0);	-- Convert force to torque
+   
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : v_sine.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/07/03
+-------------------------------------------------------------------------------
+-- Description: Electrical sinusoidal voltage source
+--              Includes frequency domain settings
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created
+-- 2001/07/03  1.1         Mentor Graphics     Changed generics from real to
+--                                             voltage.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity v_sine is
+
+  generic (
+    freq      : real;                   -- frequency [Hertz]
+    amplitude : voltage;                -- amplitude [Volts]
+    phase     : real    := 0.0;         -- initial phase [Degrees]
+    offset    : voltage := 0.0;         -- DC value [Volts]
+    df        : real    := 0.0;         -- damping factor [1/second]
+    ac_mag    : voltage := 1.0;         -- AC magnitude [Volts]
+    ac_phase  : real    := 0.0);        -- AC phase [Degrees]
+
+  port (
+    terminal pos, neg : electrical);
+
+end entity v_sine;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_sine is
+-- Declare Branch Quantities
+  quantity v across i through pos to neg;
+-- Declare Quantity for Phase in radians (calculated below)
+  quantity phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+  quantity ac_spec   : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+-- Convert phase to radians
+  phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+  if domain = quiescent_domain or domain = time_domain use
+    v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+  else
+    v == ac_spec;           -- used for Frequency (AC) analysis
+  end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TB_CS2_Mech_Domain is
+end TB_CS2_Mech_Domain;
+
+architecture TB_CS2_Mech_Domain of TB_CS2_Mech_Domain is
+    -- Component declarations
+    -- Signal declarations
+    terminal gear_out : rotational;
+    terminal link_in : translational;
+    terminal link_out : translational;
+    terminal mot_in : electrical;
+    terminal mot_out : rotational_v;
+    terminal pos_fb_v : electrical;
+    terminal rudder : rotational;
+    terminal src_in : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    rudder_servo1 : entity work.rudder_servo
+        port map(
+            servo_out => mot_in,
+            servo_in => src_in,
+            pos_fb => pos_fb_v
+        );
+    gear3 : entity work.gear_rv_r(ideal)
+        generic map(
+            ratio => 0.01
+        )
+        port map(
+            rotv1 => mot_out,
+            rot2 => gear_out
+        );
+    r2v : entity work.rot2v(bhv)
+        generic map(
+            k => 1.0
+        )
+        port map(
+            output => pos_fb_v,
+            input => gear_out
+        );
+    r2t : entity work.horn_r2t(bhv)
+        port map(
+            theta => gear_out,
+            pos => link_in
+        );
+    t2r : entity work.horn_t2r(bhv)
+        port map(
+            theta => rudder,
+            pos => link_out
+        );
+    motor1 : entity work.DC_Motor(basic)
+        generic map(
+            j => 168.0e-9,
+            d => 5.63e-6,
+            l => 2.03e-3,
+            kt => 3.43e-3,
+            r_wind => 2.2
+        )
+        port map(
+            p1 => mot_in,
+            p2 => ELECTRICAL_REF,
+            shaft_rotv => mot_out
+        );
+    stop1 : entity work.stop_r(ideal)
+        generic map(
+            ang_min => -1.05,
+            ang_max => 1.05,
+            k_stop => 1.0e6,
+            damp_stop => 1.0e2
+        )
+        port map(
+            ang1 => gear_out,
+            ang2 => ROTATIONAL_REF
+        );
+    XCMP35 : entity work.tran_linkage(a1)
+        port map(
+            p2 => link_out,
+            p1 => link_in
+        );
+    XCMP36 : entity work.rudder(bhv)
+        generic map(
+            k => 0.2
+        )
+        port map(
+            rot => rudder
+        );
+    v6 : entity work.v_sine(ideal)
+        generic map(
+            freq => 1.0,
+            amplitude => 4.8
+        )
+        port map(
+            pos => src_in,
+            neg => ELECTRICAL_REF
+        );
+end TB_CS2_Mech_Domain;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd
new file mode 100644
index 0000000..1bd3054
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd
@@ -0,0 +1,527 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity v_sine is
+
+  generic (
+    freq      : real;                   -- frequency [Hertz]
+    amplitude : voltage;                -- amplitude [Volts]
+    phase     : real    := 0.0;         -- initial phase [Degrees]
+    offset    : voltage := 0.0;         -- DC value [Volts]
+    df        : real    := 0.0;         -- damping factor [1/second]
+    ac_mag    : voltage := 1.0;         -- AC magnitude [Volts]
+    ac_phase  : real    := 0.0);        -- AC phase [Degrees]
+
+  port (
+    terminal pos, neg : electrical);
+
+end entity v_sine;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_sine is
+-- Declare Branch Quantities
+  quantity v across i through pos to neg;
+-- Declare Quantity for Phase in radians (calculated below)
+  quantity phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+  quantity ac_spec   : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+-- Convert phase to radians
+  phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+  if domain = quiescent_domain or domain = time_domain use
+    v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+  else
+    v == ac_spec;           -- used for Frequency (AC) analysis
+  end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity sum2_e is
+	generic (k1, k2: real := 1.0);  -- Gain multipliers
+	port 	(	terminal in1, in2: electrical;
+			terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+  QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+  QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+--  Transfer Function:
+--
+--                  (s + w1)         
+--    H(s) =  k *  ----------
+--                  (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE; use ieee.math_real.all;
+
+entity lead_lag_e is
+	generic (
+		k: real := 1.0;  			-- Gain multiplier
+		f1: real := 10.0;			-- First break frequency (zero)
+		f2: real := 100.0);		-- Second break frequency (pole)
+	port 	(	terminal input: electrical;
+			terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+	quantity vin_temp : real;
+	constant w1 : real := f1*math_2_pi;
+	constant w2 : real := f2*math_2_pi;
+	constant num : real_vector := (w1, 1.0);                                                    
+	constant den : real_vector := (w2, 1.0);
+begin
+	vin_temp == vin;
+	vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+	generic (
+		k: REAL := 1.0);  -- Gain multiplier
+	port 	(	terminal input : electrical;
+			terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k*vin;
+end architecture simple;
+--
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity limiter_2_e is
+	generic (
+		limit_high : real := 4.8;	-- upper limit
+		limit_low : real := -4.8); 	-- lower limit
+	port (
+		terminal input: electrical;
+		terminal output: electrical);					
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+  	QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  	QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+	constant slope : real := 1.0e-4;
+begin
+	if vin > limit_high use	-- Upper limit exceeded, so limit input signal
+		vout == limit_high + slope*(vin - limit_high);
+	elsif vin < limit_low use	-- Lower limit exceeded, so limit input signal
+		vout == limit_low + slope*(vin - limit_low);
+	else		-- No limit exceeded, so pass input signal as is
+		vout == vin;
+	end use;
+	break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control
+--
+--  Transfer Function:
+--                            
+--  pos_t_out =   R*sin(theta) 
+--
+-- Where pos_t = output translational position,
+-- R = horn radius, 
+-- theta_in = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity ctl_horn_e is
+  
+  generic (
+    R   : real := 1.0);            -- horn radius
+
+  port (
+    terminal theta_in    : electrical;   -- input port
+    terminal pos_t_out   : electrical);  -- output port
+     
+end entity ctl_horn_e;
+
+architecture bhv of ctl_horn_e is
+  quantity vin across theta_in to electrical_ref;
+  quantity vout across iout through pos_t_out to electrical_ref;
+
+  begin  -- bhv
+   vout == R*sin(vin);
+end bhv;
+--
+-------------------------------------------------------------------------------
+-- Rudder Model
+--
+--  Transfer Function:
+--                            
+--  theta_out =   arcsin(pos_t_in/R) 
+--
+-- Where pos_t_in = input translational position,
+-- R = horn radius, 
+-- theta_out = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+
+entity rudder_horn_e is
+  
+  generic (
+    R   : real := 1.0);            -- Rudder horn radius
+
+  port (
+    terminal pos_t_in    : electrical;   -- input port
+    terminal theta_out   : electrical);  -- output port
+     
+end entity rudder_horn_e;
+
+architecture bhv of rudder_horn_e is
+  quantity vin across pos_t_in to electrical_ref;
+  quantity vout across iout through theta_out to electrical_ref;
+
+  begin  -- bhv
+   vout == arcsin(vin/R);
+end bhv;
+--
+-------------------------------------------------------------------------------
+-- Integrator
+--
+--  Transfer Function:
+--
+--               k         
+--  H(s) =   ---------
+--               s 
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity integ_1_e is
+	generic (
+		k: real := 1.0;		-- Gain
+		init: real := 0.0);  -- Initial value of output
+	port 	(terminal input: electrical;
+		terminal output: electrical);
+end entity integ_1_e;
+
+architecture simple of integ_1_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+  quantity vin_temp : real;
+begin
+  vin_temp == vin;
+  IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE
+  	vout == init;
+  ELSE 
+	vout == k*vin_temp'INTEG;
+
+  END USE;
+
+end architecture simple;
+--
+-------------------------------------------------------------------------------
+-- Second Order Lowpass filter
+--
+--  Transfer Function:
+--
+--                    w1*w2         
+--   H(s) =  k * ----------------
+--               (s + w1)(s + w2)
+--
+-- DC Gain = k
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE; use ieee.math_real.all;
+
+entity lpf_1_e is
+  generic (
+    fp   : real;            -- pole freq
+    gain : real := 1.0);    -- filter gain
+
+    port 	(	terminal input: electrical;
+			terminal output: electrical);
+end entity lpf_1_e;
+
+architecture simple of lpf_1_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+  constant wp : real := math_2_pi*fp;    
+  constant num : real_vector := (0 => wp*gain);  -- 0=> is needed to give
+                                                   -- index when only a single
+                                                   -- element is used.
+  constant den : real_vector := (wp, 1.0);
+  quantity vin_temp : real;  
+
+begin
+	vin_temp == vin;   -- intermediate variable (vin) req'd for now
+	vout == vin_temp'ltf(num, den);
+end architecture simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TB_CS2_S_Domain is
+end TB_CS2_S_Domain;
+
+architecture TB_CS2_S_Domain of TB_CS2_S_Domain is
+    -- Component declarations
+    -- Signal declarations
+    terminal comp_in : electrical;
+    terminal ctl_horn_out : electrical;
+    terminal err_limit_in : electrical;
+    terminal error : electrical;
+    terminal gear_out : electrical;
+    terminal integ_out : electrical;
+    terminal load_trq : electrical;
+    terminal mtr_fb : electrical;
+    terminal mtr_gen_trq : electrical;
+    terminal mtr_in : electrical;
+    terminal mtr_out : electrical;
+    terminal pos_fb : electrical;
+    terminal rudder : electrical;
+    terminal rudder_in : electrical;
+    terminal src_in : electrical;
+    terminal XSIG010043 : electrical;
+    terminal XSIG010044 : electrical;
+    terminal XSIG010046 : electrical;
+    terminal XSIG010050 : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    v_source : entity work.v_sine(ideal)
+        generic map(
+            amplitude => 4.8,
+            freq => 1.0
+        )
+        port map(
+            pos => src_in,
+            neg => ELECTRICAL_REF
+        );
+    sum_pos : entity work.sum2_e(simple)
+        port map(
+            in1 => src_in,
+            in2 => pos_fb,
+            output => error
+        );
+    loop_comp : entity work.lead_lag_e(simple)
+        generic map(
+            f1 => 5.0,
+            k => 4000.0,
+            f2 => 20000.0
+        )
+        port map(
+            input => comp_in,
+            output => err_limit_in
+        );
+    pos_fb_gain : entity work.gain_e(simple)
+        generic map(
+            k => -4.57
+        )
+        port map(
+            input => rudder_in,
+            output => pos_fb
+        );
+    mech_limit : entity work.limiter_2_e(simple)
+       generic map(
+            limit_high => 1.05,
+            limit_low => -1.05
+        )
+        port map(
+            input => integ_out,
+            output => rudder_in
+        );
+    gear_box_horn : entity work.ctl_horn_e(bhv)
+        port map(
+            theta_in => rudder_in,
+            pos_t_out => ctl_horn_out
+        );
+    rudder_horn : entity work.rudder_horn_e(bhv)
+        port map(
+            pos_t_in => ctl_horn_out,
+            theta_out => rudder
+        );
+    mtr_Kt : entity work.gain_e(simple)
+        generic map(
+            k => 3.43e-3
+        )
+        port map(
+            input => XSIG010044,
+            output => mtr_gen_trq
+        );
+    gear_box : entity work.gain_e(simple)
+        generic map(
+            k => 0.01
+        )
+        port map(
+            input => mtr_out,
+            output => gear_out
+        );
+    mtr_Ke : entity work.gain_e(simple)
+        generic map(
+            k => -3.43e-3
+        )
+        port map(
+            input => mtr_out,
+            output => mtr_fb
+        );
+    sum_mtr_in : entity work.sum2_e(simple)
+        port map(
+            in1 => mtr_in,
+            in2 => mtr_fb,
+            output => XSIG010043
+        );
+    sum_load_trq : entity work.sum2_e(simple)
+        port map(
+            in1 => mtr_gen_trq,
+            in2 => load_trq,
+            output => XSIG010046
+        );
+    integrator : entity work.integ_1_e(simple)
+        generic map(
+            k => 1.0
+        )
+        port map(
+            input => gear_out,
+            output => integ_out
+        );
+    rudder_trq : entity work.gain_e(simple)
+        generic map(
+            k => -0.2
+        )
+        port map(
+            input => XSIG010050,
+            output => load_trq
+        );
+    trq_fb_gain : entity work.gain_e(simple)
+        generic map(
+            k => 0.01
+        )
+        port map(
+            input => rudder_in,
+            output => XSIG010050
+        );
+    mtr_elec_pole : entity work.lpf_1_e(simple)
+        generic map(
+            gain => 0.4545,
+            fp => 172.48
+        )
+        port map(
+            input => XSIG010043,
+            output => XSIG010044
+        );
+    mtr_mech_pole : entity work.lpf_1_e(simple)
+        generic map(
+            gain => 177.67e3,
+            fp => 5.33
+        )
+        port map(
+            input => XSIG010046,
+            output => mtr_out
+        );
+    loop_gain : entity work.gain_e(simple)
+        generic map(
+            k => 100.0
+        )
+        port map(
+            input => error,
+            output => comp_in
+        );
+    err_limit : entity work.limiter_2_e(simple)
+       generic map(
+            limit_high => 4.8,
+            limit_low => -4.8
+        )
+        port map(
+            input => err_limit_in,
+            output => mtr_in
+        );
+end TB_CS2_S_Domain;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd
new file mode 100644
index 0000000..aa65125
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd
@@ -0,0 +1,902 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : gear_rv_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/10/10  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+  generic(
+    ratio : real := 1.0);   -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+                            -- Note: can be negative, if shaft polarity changes
+
+  port ( terminal rotv1 : rotational_v;
+  		terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+  quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+--  quantity w2 across torq2 through rotv2 to rotational_v_ref;
+  quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+--  w2  == w1*ratio;
+  theta == ratio*w1'integ;
+  torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+  
+  generic (
+    k : real := 1.0);                -- optional gain
+
+  port (
+    terminal input   : rotational;  -- input terminal
+    terminal output    : electrical);   -- output terminal
+  
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref;     -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+  begin  -- bhv
+   v_out ==  k*rot_in; 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  tran =   R*sin(rot) 
+--
+-- Where pos = output translational position,
+-- R = horn radius, 
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+  
+  generic (
+    R   : real := 1.0);            		-- horn radius
+
+  port (
+    terminal theta    : ROTATIONAL;   	-- input angular position port
+    terminal pos   : TRANSLATIONAL);  	-- output translational position port
+     
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+  begin			-- bhv
+   tran == R*sin(rot);		-- Convert angle in to translational out
+   tran_frc == -rot_tq/R;	-- Convert torque in to force out 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  theta =   arcsin(pos/R) 
+--
+-- Where pos = input translational position,
+-- R = horn radius, 
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+  
+  generic (
+    R   : real := 1.0);            -- Rudder horn radius
+
+  port (
+    terminal pos    : translational;   -- input translational position port
+    terminal theta   : rotational);  -- output angular position port
+     
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+  begin  -- bhv
+   rot == arcsin(tran/R);	-- Convert translational to angle
+   rot_tq == -tran_frc*R;	-- Convert force to torque
+   
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : DC_Motor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+  generic (
+    r_wind : resistance;                -- Motor winding resistance [Ohm]
+    kt     : real;                      -- Torque coefficient [N*m/Amp]
+    l      : inductance;                -- Winding inductance [Henrys]
+    d      : real;                      -- Damping coefficient [N*m/(rad/sec)]
+    j      : mmoment_i);                -- Moment of inertia [kg*meter**2]
+
+  port (terminal p1, p2 : electrical;
+        terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations:  V = Kt*W + I*Rwind + L*dI/dt
+--                   T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+  quantity v across i through p1 to p2;
+  quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+  torq == -1.0*kt*i + d*w + j*w'dot;
+  v  == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : stop_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- library IEEE;
+-- use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+  generic (
+    k_stop    : real;
+--    ang_max   : angle;
+--    ang_min   : angle := 0.0;
+	ang_max   : real;
+    ang_min   : real := 0.0;
+    damp_stop : real  := 0.000000001
+    );
+
+  port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+  quantity velocity : velocity;
+  quantity ang across trq through ang1 to ang2;
+
+begin
+
+  velocity == ang'dot;
+
+  if ang > ang_max use
+    trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+  elsif ang > ang_min use
+    trq   == 0.0;
+  else
+    trq   == k_stop * (ang - ang_min) + (damp_stop * velocity);
+  end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+      terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+  QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+  QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+   pos_2 == pos_1;		-- Pass position 
+   frc_2 == -frc_1;	-- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+--  Transfer Function:
+--                            
+--  torq =   -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+  
+  generic (
+    k   : real := 1.0;            -- Spring constant
+	theta_0 : real := 0.0);
+
+  port (
+    terminal rot    : rotational);   -- input rotational angle
+     
+end entity rudder;
+
+architecture bhv of rudder is
+
+  QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+  begin  -- bhv
+
+   torq == k*(theta - theta_0);	-- Convert force to torque
+   
+end bhv;
+--
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+	generic (k1, k2: real := 1.0);  -- Gain multipliers
+	port 	(	terminal in1, in2: electrical;
+			terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+  QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+  QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+	generic (
+		k: REAL := 1.0);  -- Gain multiplier
+	port 	(	terminal input : electrical;
+			terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+	generic (
+		limit_high : real := 4.8;	-- upper limit
+		limit_low : real := -4.8); 	-- lower limit
+	port (
+		terminal input: electrical;
+		terminal output: electrical);					
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+  	QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  	QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+	constant slope : real := 1.0e-4;
+begin
+	if vin > limit_high use	-- Upper limit exceeded, so limit input signal
+		vout == limit_high + slope*(vin - limit_high);
+	elsif vin < limit_low use	-- Lower limit exceeded, so limit input signal
+		vout == limit_low + slope*(vin - limit_low);
+	else		-- No limit exceeded, so pass input signal as is
+		vout == vin;
+	end use;
+	break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : clock.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Digital clock with 50% duty cycle
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clock is
+  generic (
+    period : time);                     -- Clock period
+
+  port (
+    clk_out : out std_logic);
+
+end entity clock;
+
+architecture ideal of clock is
+
+begin
+  CreateClock: process 
+  begin
+    clk_out <= '0';
+    wait for period/2;
+    clk_out <= '1';
+    wait for period/2;   
+  end process CreateClock;
+
+end architecture ideal;
+
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Z-domain Lead Lag Filter
+--
+--  Z-Domain Transfer Function:
+--
+--  Y(z)         a0(z) - a1(z-1)         
+--  ---- =   k * ---------------
+--  X(z)         b0(z) - b1(z-1) 
+--
+-- Normalizing Gain = k
+--
+-- Difference Equation:
+--
+--	Y(K) = AX(k) - BX(k-1) + CY(k-1)
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity lead_lag_diff is
+  
+  port (
+	signal clk : in std_logic; -- clock
+	terminal input: electrical;
+	terminal output: electrical);
+end entity lead_lag_diff;
+
+architecture bhv of lead_lag_diff is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+  CONSTANT k : real := 400.0; -- Normalize gain
+
+signal z_out : real := 0.0;
+begin
+proc : process (clk)
+
+	variable zi_dly1 : real := 0.0; -- Input delayed 1 clk cycle
+	variable zo_dly1 : real := 0.0; -- Output delayed 1 clk cycle
+	variable z_new : real := 0.0;	-- New output value this clk cycle
+
+ 	begin  -- proc
+		zo_dly1 := z_out; -- Store previous output value
+		z_new := 0.6163507*vin - 0.6144184*zi_dly1 + 0.2307692*zo_dly1;
+		zi_dly1 := vin; -- Store previous input value
+		z_out <= z_new;
+	end process;
+	vout == k*z_out'ramp(100.0e-9); -- Ensure continuous transitions on output
+end bhv;
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo_z is
+    port(
+        terminal servo_in : electrical;
+        terminal pos_fb : electrical;
+        terminal servo_out : electrical
+    );
+end rudder_servo_z;
+
+architecture rudder_servo_z of rudder_servo_z is
+    -- Component declarations
+    -- Signal declarations
+    signal clk : std_logic;
+    terminal error : electrical;
+    terminal limit_in : electrical;
+    terminal ll_in : electrical;
+    terminal summer_fb : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    summer : entity work.sum2_e(simple)
+        port map(
+            in1 => servo_in,
+            in2 => summer_fb,
+            output => error
+        );
+    forward_gain : entity work.gain_e(simple)
+        generic map(
+            k => 100.0
+        )
+        port map(
+            input => error,
+            output => ll_in
+        );
+    fb_gain : entity work.gain_e(simple)
+        generic map(
+            k => -4.57
+        )
+        port map(
+            input => pos_fb,
+            output => summer_fb
+        );
+    XCMP21 : entity work.limiter_2_e(simple)
+         generic map(
+            limit_high => 4.8,
+            limit_low => -4.8
+        )
+        port map(
+            input => limit_in,
+            output => servo_out
+        );
+    clock1 : entity work.clock(ideal)
+        generic map(
+            period => 200us
+        )
+        port map(
+            CLK_OUT => clk
+        );
+    XCMP23 : entity work.lead_lag_diff(bhv)
+        port map(
+            input => ll_in,
+            output => limit_in,
+            clk => clk
+        );
+end rudder_servo_z;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : v_sine.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/07/03
+-------------------------------------------------------------------------------
+-- Description: Electrical sinusoidal voltage source
+--              Includes frequency domain settings
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created
+-- 2001/07/03  1.1         Mentor Graphics     Changed generics from real to
+--                                             voltage.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity v_sine is
+
+  generic (
+    freq      : real;                   -- frequency [Hertz]
+    amplitude : voltage;                -- amplitude [Volts]
+    phase     : real    := 0.0;         -- initial phase [Degrees]
+    offset    : voltage := 0.0;         -- DC value [Volts]
+    df        : real    := 0.0;         -- damping factor [1/second]
+    ac_mag    : voltage := 1.0;         -- AC magnitude [Volts]
+    ac_phase  : real    := 0.0);        -- AC phase [Degrees]
+
+  port (
+    terminal pos, neg : electrical);
+
+end entity v_sine;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_sine is
+-- Declare Branch Quantities
+  quantity v across i through pos to neg;
+-- Declare Quantity for Phase in radians (calculated below)
+  quantity phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+  quantity ac_spec   : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+-- Convert phase to radians
+  phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+  if domain = quiescent_domain or domain = time_domain use
+    v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+  else
+    v == ac_spec;           -- used for Frequency (AC) analysis
+  end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TB_CS2_Z_Domain_Diff is
+end TB_CS2_Z_Domain_Diff;
+
+architecture TB_CS2_Z_Domain_Diff of TB_CS2_Z_Domain_Diff is
+    -- Component declarations
+    -- Signal declarations
+    terminal ctl_horn_in : rotational;
+    terminal fb_rot2v : electrical;
+    terminal gear_in : rotational_v;
+    terminal link_in : translational;
+    terminal link_out : translational;
+    terminal mot_in : electrical;
+    terminal rudder : rotational;
+    terminal src_in : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    gear1 : entity work.gear_rv_r(ideal)
+        generic map(
+            ratio => 0.01
+        )
+        port map(
+            rotv1 => gear_in,
+            rot2 => ctl_horn_in
+        );
+    gain_fb : entity work.rot2v(bhv)
+        generic map(
+            k => 1.0
+        )
+        port map(
+            output => fb_rot2v,
+            input => ctl_horn_in
+        );
+    gear_horn : entity work.horn_r2t(bhv)
+        port map(
+            theta => ctl_horn_in,
+            pos => link_in
+        );
+    rudder_horn : entity work.horn_t2r(bhv)
+        port map(
+            theta => rudder,
+            pos => link_out
+        );
+    motor1 : entity work.DC_Motor(basic)
+        generic map(
+            r_wind => 2.2,
+            kt => 3.43e-3,
+            l => 2.03e-3,
+            d => 5.63e-6,
+            j => 168.0e-9
+        )
+        port map(
+            p1 => mot_in,
+            p2 => ELECTRICAL_REF,
+            shaft_rotv => gear_in
+        );
+    stop1 : entity work.stop_r(ideal)
+        generic map(
+            damp_stop => 1.0e2,
+            k_stop => 1.0e6,
+            ang_max => 1.05,
+            ang_min => -1.05
+        )
+        port map(
+            ang1 => ctl_horn_in,
+            ang2 => ROTATIONAL_REF
+        );
+    \Linkage\ : entity work.tran_linkage(a1)
+        port map(
+            p2 => link_out,
+            p1 => link_in
+        );
+    XCMP5 : entity work.rudder(bhv)
+        generic map(
+            k => 0.2
+        )
+        port map(
+            rot => rudder
+        );
+    rudder_servo_z1 : entity work.rudder_servo_z
+        port map(
+            servo_out => mot_in,
+            servo_in => src_in,
+            pos_fb => fb_rot2v
+        );
+    v3 : entity work.v_sine(ideal)
+        generic map(
+            freq => 1.0,
+            amplitude => 4.8
+        )
+        port map(
+            pos => src_in,
+            neg => ELECTRICAL_REF
+        );
+end TB_CS2_Z_Domain_Diff;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd
new file mode 100644
index 0000000..e9f0346
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd
@@ -0,0 +1,817 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : gear_rv_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/10/10  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+  generic(
+    ratio : real := 1.0);   -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+                            -- Note: can be negative, if shaft polarity changes
+
+  port ( terminal rotv1 : rotational_v;
+  		terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+  quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+--  quantity w2 across torq2 through rotv2 to rotational_v_ref;
+  quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+--  w2  == w1*ratio;
+  theta == ratio*w1'integ;
+  torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+  
+  generic (
+    k : real := 1.0);                -- optional gain
+
+  port (
+    terminal input   : rotational;  -- input terminal
+    terminal output    : electrical);   -- output terminal
+  
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref;     -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+  begin  -- bhv
+   v_out ==  k*rot_in; 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  tran =   R*sin(rot) 
+--
+-- Where pos = output translational position,
+-- R = horn radius, 
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+  
+  generic (
+    R   : real := 1.0);            		-- horn radius
+
+  port (
+    terminal theta    : ROTATIONAL;   	-- input angular position port
+    terminal pos   : TRANSLATIONAL);  	-- output translational position port
+     
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+  begin			-- bhv
+   tran == R*sin(rot);		-- Convert angle in to translational out
+   tran_frc == -rot_tq/R;	-- Convert torque in to force out 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  theta =   arcsin(pos/R) 
+--
+-- Where pos = input translational position,
+-- R = horn radius, 
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+  
+  generic (
+    R   : real := 1.0);            -- Rudder horn radius
+
+  port (
+    terminal pos    : translational;   -- input translational position port
+    terminal theta   : rotational);  -- output angular position port
+     
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+  begin  -- bhv
+   rot == arcsin(tran/R);	-- Convert translational to angle
+   rot_tq == -tran_frc*R;	-- Convert force to torque
+   
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : DC_Motor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+  generic (
+    r_wind : resistance;                -- Motor winding resistance [Ohm]
+    kt     : real;                      -- Torque coefficient [N*m/Amp]
+    l      : inductance;                -- Winding inductance [Henrys]
+    d      : real;                      -- Damping coefficient [N*m/(rad/sec)]
+    j      : mmoment_i);                -- Moment of inertia [kg*meter**2]
+
+  port (terminal p1, p2 : electrical;
+        terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations:  V = Kt*W + I*Rwind + L*dI/dt
+--                   T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+  quantity v across i through p1 to p2;
+  quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+  torq == -1.0*kt*i + d*w + j*w'dot;
+  v  == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : stop_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- library IEEE;
+-- use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+  generic (
+    k_stop    : real;
+--    ang_max   : angle;
+--    ang_min   : angle := 0.0;
+	ang_max   : real;
+    ang_min   : real := 0.0;
+    damp_stop : real  := 0.000000001
+    );
+
+  port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+  quantity velocity : velocity;
+  quantity ang across trq through ang1 to ang2;
+
+begin
+
+  velocity == ang'dot;
+
+  if ang > ang_max use
+    trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+  elsif ang > ang_min use
+    trq   == 0.0;
+  else
+    trq   == k_stop * (ang - ang_min) + (damp_stop * velocity);
+  end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+      terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+  QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+  QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+   pos_2 == pos_1;		-- Pass position 
+   frc_2 == -frc_1;	-- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+--  Transfer Function:
+--                            
+--  torq =   -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+  
+  generic (
+    k   : real := 1.0;            -- Spring constant
+	theta_0 : real := 0.0);
+
+  port (
+    terminal rot    : rotational);   -- input rotational angle
+     
+end entity rudder;
+
+architecture bhv of rudder is
+
+  QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+  begin  -- bhv
+
+   torq == k*(theta - theta_0);	-- Convert force to torque
+   
+end bhv;
+--
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+	generic (k1, k2: real := 1.0);  -- Gain multipliers
+	port 	(	terminal in1, in2: electrical;
+			terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+  QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+  QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+	generic (
+		k: REAL := 1.0);  -- Gain multiplier
+	port 	(	terminal input : electrical;
+			terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+	generic (
+		limit_high : real := 4.8;	-- upper limit
+		limit_low : real := -4.8); 	-- lower limit
+	port (
+		terminal input: electrical;
+		terminal output: electrical);					
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+  	QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  	QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+	constant slope : real := 1.0e-4;
+begin
+	if vin > limit_high use	-- Upper limit exceeded, so limit input signal
+		vout == limit_high + slope*(vin - limit_high);
+	elsif vin < limit_low use	-- Lower limit exceeded, so limit input signal
+		vout == limit_low + slope*(vin - limit_low);
+	else		-- No limit exceeded, so pass input signal as is
+		vout == vin;
+	end use;
+	break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+--
+
+LIBRARY ieee;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY lead_lag_ztf IS
+
+  GENERIC (
+     a1, a2 : real;
+	 b1, b2 : real;
+	 k : real := 1.0;
+	tsampl: real;
+	init_delay: real := 0.0);
+
+  PORT (
+    TERMINAL input   : electrical;
+    TERMINAL output   : electrical);
+
+END ENTITY lead_lag_ztf ;
+
+ARCHITECTURE simple OF lead_lag_ztf IS
+
+  QUANTITY vin across input TO electrical_ref;
+  QUANTITY vout across iout through output TO electrical_ref;
+
+  constant num: real_vector := (a1, a2);
+  constant den: real_vector := (b1, b2);
+
+BEGIN  -- ARCHITECTURE simple
+
+vout == k*vin'ztf(num, den, tsampl, init_delay);
+
+END ARCHITECTURE simple;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo_ztf is
+    port(
+        terminal servo_in : electrical;
+        terminal pos_fb : electrical;
+        terminal servo_out : electrical
+    );
+end rudder_servo_ztf;
+
+architecture rudder_servo_ztf of rudder_servo_ztf is
+    -- Component declarations
+    -- Signal declarations
+    terminal error : electrical;
+    terminal limit_in : electrical;
+    terminal ll_in : electrical;
+    terminal summer_fb : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    summer : entity work.sum2_e(simple)
+        port map(
+            in1 => servo_in,
+            in2 => summer_fb,
+            output => error
+        );
+    forward_gain : entity work.gain_e(simple)
+        generic map(
+            k => 100.0
+        )
+        port map(
+            input => error,
+            output => ll_in
+        );
+    fb_gain : entity work.gain_e(simple)
+        generic map(
+            k => -4.57
+        )
+        port map(
+            input => pos_fb,
+            output => summer_fb
+        );
+    XCMP21 : entity work.limiter_2_e(simple)
+        generic map(
+            limit_high => 4.8,
+            limit_low => -4.8
+        )
+        port map(
+            input => limit_in,
+            output => servo_out
+        );
+    ll_ztf : entity work.lead_lag_ztf(simple)
+        generic map(
+            a1 => 2.003140,
+            a2 => -1.996860,
+            b1 => 3.25000,
+            b2 => -0.75000,
+            k => 400.0,
+            tsampl => 0.0001
+        )
+        port map(
+            input => ll_in,
+            output => limit_in
+        );
+end rudder_servo_ztf;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : v_sine.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/07/03
+-------------------------------------------------------------------------------
+-- Description: Electrical sinusoidal voltage source
+--              Includes frequency domain settings
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created
+-- 2001/07/03  1.1         Mentor Graphics     Changed generics from real to
+--                                             voltage.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity v_sine is
+
+  generic (
+    freq      : real;                   -- frequency [Hertz]
+    amplitude : voltage;                -- amplitude [Volts]
+    phase     : real    := 0.0;         -- initial phase [Degrees]
+    offset    : voltage := 0.0;         -- DC value [Volts]
+    df        : real    := 0.0;         -- damping factor [1/second]
+    ac_mag    : voltage := 1.0;         -- AC magnitude [Volts]
+    ac_phase  : real    := 0.0);        -- AC phase [Degrees]
+
+  port (
+    terminal pos, neg : electrical);
+
+end entity v_sine;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_sine is
+-- Declare Branch Quantities
+  quantity v across i through pos to neg;
+-- Declare Quantity for Phase in radians (calculated below)
+  quantity phase_rad : real;
+-- Declare Quantity in frequency domain for AC analysis
+  quantity ac_spec   : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+-- Convert phase to radians
+  phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+
+  if domain = quiescent_domain or domain = time_domain use
+    v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+  else
+    v == ac_spec;           -- used for Frequency (AC) analysis
+  end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity TB_CS2_Z_Domain_ZTF is
+end TB_CS2_Z_Domain_ZTF ;
+
+architecture TB_CS2_Z_Domain_ZTF of TB_CS2_Z_Domain_ZTF is
+    -- Component declarations
+    -- Signal declarations
+    terminal gear_out : rotational;
+    terminal link_in : translational;
+    terminal link_out : translational;
+    terminal mtr_in : electrical;
+    terminal mtr_out : rotational_v;
+    terminal pot_fb : electrical;
+    terminal rudder : rotational;
+    terminal src_in : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    gear5 : entity work.gear_rv_r(ideal)
+        generic map(
+            ratio => 0.01
+        )
+        port map(
+            rotv1 => mtr_out,
+            rot2 => gear_out
+        );
+    XCMP42 : entity work.rot2v(bhv)
+        generic map(
+            k => 1.0
+        )
+        port map(
+            output => pot_fb,
+            input => gear_out
+        );
+    XCMP43 : entity work.horn_r2t(bhv)
+        port map(
+            theta => gear_out,
+            pos => link_in
+        );
+    XCMP44 : entity work.horn_t2r(bhv)
+        port map(
+            theta => rudder,
+            pos => link_out
+        );
+    motor3 : entity work.DC_Motor(basic)
+        generic map(
+            r_wind => 2.2,
+            kt => 3.43e-3,
+            l => 2.03e-3,
+            d => 5.63e-6,
+            j => 168.0e-9
+        )
+        port map(
+            p1 => mtr_in,
+            p2 => ELECTRICAL_REF,
+            shaft_rotv => mtr_out
+        );
+    stop3 : entity work.stop_r(ideal)
+        generic map(
+            damp_stop => 1.0e2,
+            k_stop => 1.0e6,
+            ang_max => 1.05,
+            ang_min => -1.05
+        )
+        port map(
+            ang1 => gear_out,
+            ang2 => ROTATIONAL_REF
+        );
+    \linkage\ : entity work.tran_linkage(a1)
+        port map(
+            p2 => link_out,
+            p1 => link_in
+        );
+    XCMP46 : entity work.rudder(bhv)
+        generic map(
+            k => 0.2
+        )
+        port map(
+            rot => rudder
+        );
+    rudder_servo_zt1 : entity work.rudder_servo_ztf
+        port map(
+            servo_out => mtr_in,
+            servo_in => src_in,
+            pos_fb => pot_fb
+        );
+    v8 : entity work.v_sine(ideal)
+        generic map(
+            amplitude => 4.8,
+            freq => 1.0
+        )
+        port map(
+            pos => src_in,
+            neg => ELECTRICAL_REF
+        );
+end TB_CS2_Z_Domain_ZTF;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams.vhd
new file mode 100644
index 0000000..176837f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity CalcBuckParams is
+
+  generic ( Vin : voltage range 1.0 to 50.0 := 42.0;  -- input voltage [volts]
+            Vout : voltage := 4.8;		      -- output voltage [volts]
+            Vd : voltage := 0.7;		      -- diode voltage [volts]
+            Imin : current := 15.0e-3;	              -- min output current [amps]
+            Vripple : voltage range 1.0e-6 to 100.0
+                        := 100.0e-3 );                -- output voltage ripple [volts]
+
+  port ( quantity Fsw : in real range 1.0 to 1.0e6
+                          := 2.0;                     -- switching frequency [Hz]
+         quantity Lmin : out inductance;	      -- minimum inductance [henries]
+         quantity Cmin : out capacitance );	      -- minimum capacitance [farads]
+
+end entity CalcBuckParams;
+
+----------------------------------------------------------------
+
+architecture behavioral of CalcBuckParams is
+
+  constant D : real := (Vout + Vd) / Vin;  -- duty cycle
+  quantity Ts : real;		           -- period
+  quantity Ton : real;		           -- on time
+
+begin
+
+    Ts == 1.0 / Fsw;
+
+    Ton == D * Ts;
+
+    Lmin == (Vin - Vout) * Ton / (2.0 * Imin);
+
+    Cmin == (2.0 * Imin) / (8.0 * Fsw * Vripple);
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams_wa.vhd
new file mode 100644
index 0000000..e568a63
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/CalcBuckParams_wa.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity CalcBuckParams_wa is
+  
+  generic ( Vin : voltage := 42.0;           -- input voltage [Volts]
+            Vout : voltage := 4.8;           -- output voltage [Volts]
+            Vd : voltage := 0.7;             -- diode Voltage [Volts]
+            Imin : current := 15.0e-3;       -- min output current [Amps]
+            Vripple : voltage := 100.0e-3;   -- output voltage ripple [Volts]
+            Resr : resistance := 50.0e-3 );
+
+  port ( quantity Fsw : in  real;           -- switching frequency [Hz]
+         quantity Lmin : out inductance;    -- minimum inductance [Henries]
+         quantity Cmin : out capacitance);  -- minimum capacitance [Farads]
+
+end entity CalcBuckParams_wa ;
+
+----------------------------------------------------------------
+
+architecture ideal of CalcBuckParams_wa is
+
+  constant D : real := (Vout + Vd)/(Vin + 1.0e-9);   -- Duty Cycle
+  quantity Ts : real;   -- Period
+  quantity Ton : real;  -- On Time
+
+  quantity Fxo, Fp1, Fp2, Fz : real; 
+
+begin  -- architecture behavioral
+
+  Ts == 1.0/(Fsw+1.0e-9);
+  Ton == D*Ts;
+  Lmin == (Vin - Vout) * Ton/(2.0*Imin);
+  Cmin == (2.0*Imin)/(8.0*Fsw*Vripple+1.0e-9);
+
+  -- Calculate compensator parameters
+  Fxo == Fsw/5.0;  -- desired crossover frequency
+  Fp1 == Fxo * 1.5;
+  Fp2 == 1.0/(math_2_pi*Resr*Cmin*4.0+1.0e-9);
+  Fz == 1.0/(math_2_pi*sqrt(Lmin*Cmin*4.0)+1.0e-9);
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/buck_sw.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/buck_sw.vhd
new file mode 100644
index 0000000..6320e4c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/buck_sw.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity buck_sw is
+  generic ( Vd : voltage := 0.7;       -- diode voltage
+            Vramp : voltage := 2.5 );  -- p-p amplitude of ramp voltage
+  port ( terminal input, output, ref, ctrl: electrical );
+end entity buck_sw;
+
+----------------------------------------------------------------
+
+architecture average of buck_sw is
+
+  quantity Vout across Iout through output to ref;
+  quantity Vin across input to ref;
+  quantity Vctrl across ctrl to ref;
+
+begin
+
+  Vout == Vctrl * Vin / Vramp - Vd;  -- averaged equation
+
+end architecture average;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/capacitor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/capacitor.vhd
new file mode 100644
index 0000000..dd4a3ab
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/capacitor.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity capacitor is
+  generic ( cap : capacitance;
+            r_esr : resistance := 0.0;
+            v_ic : voltage := real'low );
+  port ( terminal p1, p2 : electrical );
+end entity capacitor;
+
+----------------------------------------------------------------
+
+architecture esr of capacitor is
+  
+  quantity v across i through p1 to p2;
+  quantity vc : voltage;  -- Internal voltage across capacitor
+  
+begin
+  
+  if domain = quiescent_domain and v_ic /= real'low use
+    vc == v_ic;
+    i == 0.0;
+  else
+    vc == v - (i * r_esr); 
+    i == cap * vc'dot;
+  end use;
+  
+end architecture esr;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/comp_2p2z.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/comp_2p2z.vhd
new file mode 100644
index 0000000..20d3534
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/comp_2p2z.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity comp_2p2z is
+  generic ( gain : real := 100.0;   -- high DC gain for good load regulation       
+            fp1 : real := 7.5e3;    -- pole location to achieve crossover frequency
+            fp2 : real := 531.0e3;  -- pole location to cancel effect of ESR 
+            fz1 : real := 403.0;    -- zero locations to cancel L-C filter poles
+            fz2 : real := 403.0 );
+  port ( terminal input, output, ref : electrical );
+end entity comp_2p2z;
+
+----------------------------------------------------------------
+
+architecture ltf of comp_2p2z is
+
+  quantity vin across input to ref;
+  quantity vout across iout through output to ref;
+  constant wp1 : real := math_2_pi * fp1;  -- Pole freq (in radians)
+  constant wp2 : real := math_2_pi * fp2;
+  constant wz1 : real := math_2_pi * fz1;  -- Zero freq (in radians)
+  constant wz2 : real := math_2_pi * fz2;
+  constant num : real_vector := ( 1.0,
+                                  (wz1 + wz2) / (wz1 * wz2),
+                                  1.0 / (wz1 * wz2) );
+  constant den : real_vector := ( 1.0e-9, 1.0,
+                                  (wp1 + wp2) / (wp1 * wp2),
+                                  1.0 / (wp1 * wp2) );
+
+begin
+
+  vout == -1.0 * gain * vin'ltf(num, den);
+
+end architecture ltf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/index-ams.txt
new file mode 100644
index 0000000..7470b26
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/index-ams.txt
@@ -0,0 +1,32 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                 Chapter 18 - Case Study 3: DC-DC Power Converter
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+tb_BuckConverter.vhd                            entity tb_BuckConverter                 tb_BuckConverter                Figure 18-7
+capacitor.vhd                                   entity capacitor                        esr                             Figure 18-9
+switch_dig.vhd                                  entity switch_dig                       linear                          Figure 18-10
+buck_sw.vhd                                     entity buck_sw                          average                         Figure 18-13
+sw_LoopCtrl.vhd                                 entity sw_LoopCtrl                      ideal                           Figure 18-16
+sw_LoopCtrl_wa.vhd                              entity sw_LoopCtrl_wa                   ideal                           --
+comp_2p2z.vhd                                   entity comp_2p2z                        ltf                             Figure 18-18
+pwl_load.vhd                                    entity pwl_load                         ideal                           Figure 18-20
+pwl_load_wa.vhd                                 entity pwl_load_wa                      ideal                           --
+CalcBuckParams.vhd                              entity CalcBuckParams                   behavioral                      Figure 18-23
+CalcBuckParams_wa.vhd                           entity CalcBuckParams_wa                ideal                           --
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_CalcBuckParams.vhd                           entity tb_CalcBuckParams                tb_CalcBuckParams               CalcBuckParams.vhd
+tb_CS3_BuckConverter_average.vhd                entity inductor                         ideal
+--                                              entity inductor                         ideal2
+--                                              entity capacitor                        esr
+--                                              entity v_constant                       ideal
+--                                              entity sw_LoopCtrl_wa                   ideal
+--                                              entity pwl_load_wa                      ideal
+--                                              entity v_pulse                          ideal
+--                                              entity buck_sw                          average
+--                                              entity comp_2p2z                        ltf
+--                                              entity TB_CS3_BuckConverter_average     TB_CS3_BuckConverter_average
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd
new file mode 100644
index 0000000..073554d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+entity pwl_load is
+  generic ( load_enable : boolean := true;
+            res_init : resistance;
+            res1 : resistance;                  
+            t1 : time;
+            res2 : resistance;
+            t2 : time );
+  port ( terminal p1, p2 : electrical );
+end entity pwl_load;
+
+----------------------------------------------------------------
+
+architecture ideal of pwl_load is
+
+  quantity v across i through p1 to p2;
+  signal res_signal : resistance := res_init;
+
+begin
+
+  load_present : if load_enable generate
+
+    if domain = quiescent_domain or domain = frequency_domain use
+       v == i * res_init; 
+    else 
+       v == i * res_signal'ramp(1.0e-6, 1.0e-6);
+    end use;
+
+    create_event : process is
+    begin
+      wait for t1;
+      res_signal <= res1;
+      wait for t2 - t1;
+      res_signal <= res2;
+      wait;
+    end process create_event;
+
+  end generate load_present;
+
+  load_absent : if not load_enable generate
+
+    i == 0.0;
+
+  end generate load_absent;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load_wa.vhd
new file mode 100644
index 0000000..b9a0835
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/pwl_load_wa.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity pwl_load_wa is
+  generic ( load_enable : boolean := true;
+            res_init : resistance;
+            res1 : resistance;                  
+            t1 : time;
+            res2 : resistance;
+            t2 : time );
+  port ( terminal p1, p2 : electrical );
+end entity pwl_load_wa;
+
+----------------------------------------------------------------
+
+architecture ideal of pwl_load_wa is
+
+  quantity v across i through p1 to p2;
+  signal res_signal : resistance := res_init;
+
+begin
+
+  if load_enable use
+    if domain = quiescent_domain or domain = frequency_domain use
+       v == i * res_init; 
+    else 
+      v == i * res_signal'ramp(1.0e-6, 1.0e-6);
+    end use;
+  else 
+    i == 0.0;
+  end use;
+
+  create_event: process is
+  begin
+    wait for t1;
+    res_signal <= res1;
+    wait for t2 - t1;
+    res_signal <= res2;
+    wait;
+  end process create_event; 
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl.vhd
new file mode 100644
index 0000000..69c4f17
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity sw_LoopCtrl is
+  generic ( r_open : resistance := 1.0e6;
+            r_closed : resistance := 1.0e-3;
+            sw_state : integer range 1 to 2 := 1 );
+  port ( terminal c, p1, p2 : electrical );
+end entity sw_LoopCtrl;
+
+----------------------------------------------------------------
+
+architecture ideal of sw_LoopCtrl is
+
+  quantity v1 across i1 through c to p1;
+  quantity v2 across i2 through c to p2;
+  quantity r1, r2 : resistance;
+
+begin
+
+  sw1 : if sw_state = 1 generate
+    r1 == r_closed;
+    r2 == r_open;
+  end generate sw1;
+  
+  sw2 : if sw_state = 2 generate
+    r1 == r_open;
+    r2 == r_closed;
+  end generate sw2;
+
+  v1 == r1 * i1;
+  v2 == r2 * i2;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl_wa.vhd
new file mode 100644
index 0000000..cc57a01
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl_wa.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity sw_LoopCtrl_wa is
+  generic ( r_open : resistance := 1.0e6;
+            r_closed : resistance := 1.0e-3;
+            sw_state : integer := 1 );       
+  port ( terminal c, p1, p2 : electrical );
+
+end entity sw_LoopCtrl_wa;
+
+----------------------------------------------------------------
+
+architecture ideal of sw_LoopCtrl_wa is
+
+  quantity v1 across i1 through c to p1;
+  quantity v2 across i2 through c to p2;
+  quantity r1, r2 : resistance;
+
+begin
+
+  if (sw_state = 2) use
+    r1 == r_open;
+    r2 == r_closed;
+  else
+    r1 == r_closed;
+    r2 == r_open; 
+  end use;
+
+  v1 == r1 * i1;
+  v2 == r2 * i2;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/switch_dig.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/switch_dig.vhd
new file mode 100644
index 0000000..5fdd863
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/switch_dig.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity switch_dig is
+  generic ( r_open : resistance := 1.0e6;
+            r_closed : resistance := 1.0e-3;
+            trans_time : real := 1.0e-9 );
+  port ( sw_state : in std_logic;
+         terminal p1, p2 : electrical );
+end entity switch_dig;
+
+----------------------------------------------------------------
+
+architecture linear of switch_dig is
+  
+  signal r_sig : resistance := r_open;
+  quantity v across i through p1 to p2;
+  quantity r : resistance;
+  
+begin
+  
+  -- detect switch state and assign resistance value to r_sig
+  DetectState: process (sw_state)
+  begin
+    if (sw_state'event and sw_state = '0') then
+      r_sig <= r_open;
+    elsif (sw_state'event and sw_state = '1') then
+      r_sig <= r_closed;
+    end if;
+  end process DetectState;
+
+  r == r_sig'ramp(trans_time, trans_time);
+  v == r * i;
+
+end architecture linear;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_BuckConverter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_BuckConverter.vhd
new file mode 100644
index 0000000..7c87c4b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_BuckConverter.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity tb_BuckConverter is
+  port ( ctrl : std_logic );
+end tb_BuckConverter;
+
+----------------------------------------------------------------
+
+architecture tb_BuckConverter of tb_BuckConverter is
+
+  terminal vin : electrical;
+  terminal vmid : electrical;
+  terminal vout : electrical;
+    
+begin
+
+  L1 : entity work.inductor(ideal)
+    generic map ( ind => 6.5e-3 )
+    port map ( p1 => vmid, p2 => vout );
+  
+  C1 : entity work.capacitor(ideal)
+    generic map ( cap => 1.5e-6 )
+    port map ( p1 => vout, p2 => electrical_ref );
+  
+  VinDC : entity work.v_constant(ideal)
+    generic map ( level => 42.0 )
+    port map ( pos => vin, neg => electrical_ref );
+  
+  RLoad : entity work.resistor(ideal)
+    generic map ( res => 2.4 )
+    port map ( p1 => vout, p2 => electrical_ref );
+  
+  D1 : entity work.diode(ideal)
+    port map ( p => electrical_ref, n => vmid );
+  
+  sw1 : entity work.switch_dig(ideal)
+    port map ( sw_state => ctrl, p2 => vmid, p1 => vin );
+
+end architecture tb_BuckConverter;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd
new file mode 100644
index 0000000..161485b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd
@@ -0,0 +1,604 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : inductor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Electrical Inductor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity inductor is
+
+  generic (
+    ind  : inductance;             -- Nominal inductance
+    i_ic : real := real'low);      -- Initial current (use IF statement below
+                                   -- to activate) 
+                                  
+  port (
+    terminal p1, p2 : electrical);
+
+end entity inductor;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture (V = L * di/dt)
+-- Includes initial condition
+-------------------------------------------------------------------------------
+architecture ideal of inductor is
+
+-- Declare Branch Quantities
+  quantity v across i through p1 to p2;
+
+begin
+
+  if domain = quiescent_domain and i_ic /= real'low use
+    i == i_ic;
+  else
+    v   == ind * i'dot;                   -- characteristic equation
+  end use;
+
+end architecture ideal;
+
+architecture ideal2 of inductor is
+
+-- Declare Branch Quantities
+  quantity v across i through p1 to p2;
+
+begin
+
+  if domain = quiescent_domain and i_ic /= real'low use
+    i == i_ic;
+  else
+    v   == ind * i'dot;                   -- characteristic equation
+  end use;
+
+end architecture ideal2;
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : capacitor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Electrical Capacitor 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+entity capacitor is
+	generic ( cap : capacitance;
+				r_esr : resistance := 0.0;
+				v_ic : voltage := real'low );
+		port ( terminal p1, p2 : electrical );
+end entity capacitor;
+
+architecture esr of capacitor is
+  quantity v across i through p1 to p2;
+  quantity vc : voltage;      -- Internal voltage across capacitor
+begin
+  if domain = quiescent_domain and v_ic /= real'low use
+    vc == v_ic;
+    i == 0.0;
+  else
+    vc == v - (i * r_esr); 
+    i == cap * vc'dot;
+  end use;
+end architecture esr;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : v_constant.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/07/03
+-------------------------------------------------------------------------------
+-- Description: Constant Voltage Source
+--              Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_constant is
+
+  generic (
+    level    : voltage;                 -- Constant voltage value [Volts]
+    ac_mag   : voltage := 1.0;          -- AC magnitude [Volts]
+    ac_phase : real    := 0.0);         -- AC phase [Degrees]
+
+  port (
+    terminal pos, neg : electrical);
+
+end entity v_constant;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture (I = constant)
+-------------------------------------------------------------------------------
+architecture ideal of v_constant is
+
+-- Declare Branch Quantities
+  quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis  
+  quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+    v == level;
+  else
+    v   == ac_spec;      -- used for Frequency (AC) analysis
+  end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity sw_LoopCtrl_wa is
+  generic (r_open     : resistance := 1.0e6;
+           r_closed   : resistance := 1.0e-3;
+	     sw_state   : integer    := 1);       
+  port (terminal c, p1, p2 : electrical);
+
+end entity sw_LoopCtrl_wa;
+
+architecture ideal of sw_LoopCtrl_wa is 
+  quantity v1 across i1 through c to p1;
+  quantity v2 across i2 through c to p2;
+  quantity r1, r2 : resistance;  
+begin
+    if (sw_state = 2) use
+      r1 == r_open;
+      r2 == r_closed;
+    else
+      r1 == r_closed;
+      r2 == r_open; 
+    end use;
+
+  v1 == r1*i1;
+  v2 == r2*i2;
+end architecture ideal;
+
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity pwl_load_wa is
+  generic (
+    load_enable: string := "yes";
+    res_init : resistance;
+    res1 : resistance;                  
+    t1 : time;
+    res2 : resistance;
+    t2 : time);
+  port (terminal p1, p2 : electrical);
+end entity pwl_load_wa;
+
+architecture ideal of pwl_load_wa is
+  quantity v across i through p1 to p2;
+  signal res_signal : resistance := res_init;
+begin
+
+  if load_enable = "yes" use
+    if domain = quiescent_domain or domain = frequency_domain use
+       v == i*res_init; 
+    else 
+	   v == i*res_signal'ramp(1.0e-6, 1.0e-6);
+	end use;
+  else 
+    i == 0.0;
+  end use;
+
+ -- purpose: Create Events to change resistance at specified times
+ -- type   : combinational
+ -- inputs :
+ -- outputs: res
+CreateEvent: process is
+ begin  -- process CreateEvent
+   wait for t1;
+   res_signal <= res1;
+   wait for (t2-t1);
+   res_signal <= res2;
+   wait;
+ end process CreateEvent; 
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : v_pulse.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/07/09
+-------------------------------------------------------------------------------
+-- Description:  Voltage Pulse Source
+--               Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created
+-- 2001/07/09  1.1         Mentor Graphics     Changed input parameters to type
+--                                             time.  Uses time2real function.
+--                                             Pulsewidth no longer includes
+--                                             rise and fall times.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_pulse is
+
+  generic (
+    initial  : voltage := 0.0;          -- initial value [Volts]
+    pulse    : voltage;                 -- pulsed value [Volts]
+    ti2p     : time    := 1ns;          -- initial to pulse [Sec]
+    tp2i     : time    := 1ns;          -- pulse to initial [Sec]
+    delay    : time    := 0ms;          -- delay time [Sec]
+    width    : time;                    -- duration of pulse [Sec]
+    period   : time;                    -- period [Sec]
+    ac_mag   : voltage := 1.0;          -- AC magnitude [Volts]
+    ac_phase : real    := 0.0);         -- AC phase [Degrees]
+
+  port (
+    terminal pos, neg : electrical);
+
+end entity v_pulse;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_pulse is
+
+-- Declare Through and Across Branch Quantities
+  quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis 
+  quantity ac_spec      : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+-- Signal used in CreateEvent process below  
+  signal   pulse_signal : voltage := initial;
+  
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+-- Note: these lines gave an error during simulation.  Had to use a
+-- function call instead.
+--  constant ri2p : real := time'pos(ti2p) * 1.0e-15;
+--  constant rp2i : real := time'pos(tp2i) * 1.0e-15;
+  
+-- Function to convert numbers of type TIME to type REAL
+  function time2real(tt : time) return real is
+  begin
+    return time'pos(tt) * 1.0e-15;
+  end time2real;
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+  constant ri2p         : real    := time2real(ti2p);
+  constant rp2i         : real    := time2real(tp2i);
+
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+    v == pulse_signal'ramp(ri2p, rp2i);  -- create rise and fall transitions
+  else
+    v   == ac_spec;    -- used for Frequency (AC) analysis
+  end use;
+
+-- purpose: Create events to define pulse shape
+-- type   : combinational
+-- inputs : 
+-- outputs: pulse_signal
+CreateEvent : process
+begin
+  wait for delay;
+  loop
+    pulse_signal <= pulse;
+    wait for (width + ti2p);
+    pulse_signal <= initial;
+    wait for (period - width - ti2p);
+  end loop;
+end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity buck_sw is  
+  generic (
+	Vd		: voltage := 0.7;		-- Diode Voltage
+	Vramp		: voltage := 2.5);	-- P-P amplitude of ramp voltage
+  port (terminal input, output, ref, ctrl: electrical);
+end entity buck_sw;
+
+architecture average of buck_sw is
+  quantity Vout across Iout through output to ref;
+  quantity Vin across input to ref;
+  quantity Vctrl across ctrl to ref;
+begin  
+   Vout + Vd == Vctrl * Vin / Vramp;    -- Averaged equation
+end architecture average;
+
+library IEEE;
+library IEEE_proposed;
+use ieee.math_real.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity comp_2p2z is
+  generic (
+    gain		: real := 100.0;	-- High DC gain for good load regulation       
+    fp1		: real := 7.5e3;	-- Pole location to achieve crossover frequency
+    fp2		: real := 531.0e3;-- Pole location to cancel effect of ESR 
+    fz1		: real := 403.0;	-- Zero locations to cancel LC filter poles
+    fz2		: real := 403.0);
+  port (terminal input, output, ref : electrical);
+end entity comp_2p2z;
+
+architecture ltf of comp_2p2z is
+  quantity vin across input to ref;
+  quantity vout across iout through output to ref;
+  constant wp1	: real        := math_2_pi*fp1;  -- Pole freq (in radians)
+  constant wp2	: real        := math_2_pi*fp2;
+  constant wz1	: real        := math_2_pi*fz1;  -- Zero freq (in radians)
+  constant wz2	: real        := math_2_pi*fz2;
+  constant num	: real_vector	:= (1.0, (wz1+wz2)/(wz1*wz2), 1.0/(wz1*wz2));
+  constant den	: real_vector	:= (1.0e-9, 1.0, (wp1+wp2)/(wp1*wp2), 1.0/(wp1*wp2));
+begin  
+  vout == -1.0*gain*vin'ltf(num, den);
+end architecture ltf;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TB_CS3_BuckConverter_average is
+end TB_CS3_BuckConverter_average;
+
+architecture TB_CS3_BuckConverter_average of TB_CS3_BuckConverter_average is
+    -- Component declarations
+    -- Signal declarations
+    terminal vcomp_out : electrical;
+    terminal vctrl : electrical;
+    terminal vctrl_init : electrical;
+    terminal vin : electrical;
+    terminal vmid : electrical;
+    terminal vout : electrical;
+    terminal vref : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    L1 : entity work.inductor(ideal)
+        generic map(
+            ind => 6.5e-3
+        )
+        port map(
+            p1 => vmid,
+            p2 => vout
+        );
+    C1 : entity work.capacitor(ESR)
+        generic map(
+            cap => 6.0e-6,
+            r_esr => 50.0e-3
+        )
+        port map(
+            p1 => vout,
+            p2 => ELECTRICAL_REF
+        );
+    Vctrl_1 : entity work.v_constant(ideal)
+        generic map(
+            level => 0.327
+        )
+        port map(
+            pos => vctrl_init,
+            neg => ELECTRICAL_REF
+        );
+    Vref_1 : entity work.v_constant(ideal)
+        generic map(
+            level => 4.8
+        )
+        port map(
+            pos => vref,
+            neg => ELECTRICAL_REF
+        );
+    sw2 : entity work.sw_LoopCtrl_wa(ideal)
+        generic map(
+            sw_state => 1
+        )
+        port map(
+            p2 => vctrl_init,
+            c => vctrl,
+            p1 => vcomp_out
+        );
+    Electrical_Load6 : entity work.pwl_load_wa(ideal)
+        generic map(
+            t2 => 30 ms,
+            res2 => 5.0,
+            t1 => 5ms,
+            res1 => 1.0,
+            res_init => 2.4,
+            load_enable => "yes"
+        )
+        port map(
+            p1 => vout,
+            p2 => ELECTRICAL_REF
+        );
+    Vin_1 : entity work.v_pulse(ideal)
+        generic map(
+            initial => 42.0,
+            pulse => 42.0,
+            delay => 10ms,
+            width => 100ms,
+            period => 1000ms
+        )
+        port map(
+            pos => vin,
+            neg => ELECTRICAL_REF
+        );
+    buck_sw2 : entity work.buck_sw(average)
+        port map(
+            ctrl => vctrl,
+            input => vin,
+            ref => ELECTRICAL_REF,
+            output => vmid
+        );
+    comp_2p2z4 : entity work.comp_2p2z(ltf)
+        generic map(
+            fz1 => 403.0,
+            fz2 => 403.0,
+            gain => 100.0
+        )
+        port map(
+            input => vout,
+            output => vcomp_out,
+            ref => vref
+        );
+end TB_CS3_BuckConverter_average;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CalcBuckParams.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CalcBuckParams.vhd
new file mode 100644
index 0000000..296207c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/tb_CalcBuckParams.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CalcBuckParams is
+end tb_CalcBuckParams;
+
+architecture tb_CalcBuckParams of tb_CalcBuckParams is
+    -- Component declarations
+    -- Signal declarations
+    quantity Cmin : capacitance;
+    quantity freq_in : real;
+    quantity Lmin : inductance;
+begin
+    -- Signal assignments
+    -- Component instances
+    src1 : entity work.src_pulse(ideal)
+        generic map(
+            initial => 25.0e3,
+            pulse => 200.0e3,
+            ti2p => 1ms,
+            tp2i => 1ms,
+            delay => 1ms,
+            width => 100ms,
+            period => 1000ms
+        )
+        port map(
+            output => freq_in
+        );
+    CalcBuckParams1 : entity work.CalcBuckParams_wa(ideal)
+        generic map(
+            Vripple => 100.0e-3,
+            Vin => 42.0,
+            Vout => 4.8,
+            Vd => 0.7,
+            Imin => 15.0e-3,
+            Resr => 50.0e-3
+        )
+        port map(
+            Fsw => freq_in,
+            Lmin => Lmin,
+            Cmin => Cmin
+        );
+end tb_CalcBuckParams;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/MeasFreq.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/MeasFreq.vhd
new file mode 100644
index 0000000..ad51b87
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/MeasFreq.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity MeasFreq is
+  generic ( thres : real := 0.0 );
+  port ( terminal input : electrical;
+         signal f_out : out real := 0.0 );
+end entity MeasFreq;
+
+----------------------------------------------------------------
+
+architecture ThresDetect of MeasFreq is
+
+  quantity vin across input;
+
+begin
+
+  detect : process ( vin'above(thres) ) is
+    variable t_old : real := real'low;
+  begin
+    if vin'above(thres) then
+      f_out <= 1.0 / (now - t_old);
+      t_old := now;
+    end if;
+  end process detect;
+
+end ThresDetect;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/PLL.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/PLL.vhd
new file mode 100644
index 0000000..62a2162
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/PLL.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+library ieee;  use ieee.math_real.all;
+               
+entity PLL is
+
+  generic ( Fp : real := 20.0e3;   -- loop filter pole freq [Hz]
+            Fz : real := 1.0e6;	   -- loop filter zero freq [Hz]
+            Kv : real := 100.0e3;  -- VCO gain [Hz/V]
+            Fc : real := 1.0e6 );  -- VCO center freq [Hz]
+
+  port ( terminal input, lf_out, vco_out : electrical );
+
+end entity PLL;
+
+----------------------------------------------------------------
+
+architecture behavioral of PLL is
+
+  quantity v_in across input to electrical_ref;
+  quantity v_lf across i_lf through lf_out to electrical_ref;
+  quantity v_vco across i_vco through vco_out to electrical_ref;
+
+  -- internal quantities and constants
+
+  -- multiplier 
+  quantity mult : real;
+
+  -- loop filter (Lag) 
+  constant wp : real  := math_2_pi * fp;	  -- pole freq in rad/s
+  constant wz : real  := math_2_pi * fz;	  -- zero freq in rad/s
+  constant num : real_vector := (1.0, 1.0 / wz);  -- numerator array 
+  constant den : real_vector := (1.0, 1.0 / wp);  -- denominator array
+
+  -- VCO
+  quantity phi : real;				  -- used in VCO equation
+  constant Kv_w	: real := math_2_pi * Kv;	  -- change gain to (rad/s)/V
+  constant wc : real := math_2_pi * Fc;		  -- change freq to rad/s
+
+begin
+
+  if domain = quiescent_domain use
+    phi == 0.0;                     -- initialize phi
+  else
+    phi'dot == wc + Kv_w * (v_lf);  -- calculate VCO frequency
+  end use;
+
+  mult == v_in * v_vco;		    -- multiplier output
+
+  v_lf == mult'ltf(num, den);	    -- loop filter output
+
+  v_vco == cos(phi);		    -- VCO output
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk.vhd
new file mode 100644
index 0000000..96cc54e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee, ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee.std_logic_1164.all;
+use ieee.math_real.all;
+
+entity bfsk is
+
+  generic ( fc : real := 1.0e6;		-- mean carrier frequency
+            delta_f : real := 5.0e3;    -- difference between low and high
+                                        --   carrier frequencies
+            amp : voltage := 1.0;	-- amplitude of modulated signal
+            offset : voltage := 0.0 );  -- output offset voltage
+
+  port ( signal d_in : in std_logic;	 -- digital input
+         terminal a_out : electrical );  -- output terminal
+
+end entity bfsk; 
+
+----------------------------------------------------------------
+
+architecture behavioral of bfsk is
+
+  quantity vout across iout through a_out;         -- output branch
+  quantity phi : real; 		                   -- free quantity angle in radians
+  constant wc : real := math_2_pi * fc;		   -- convert fc to rad/s
+  constant delta_w : real := math_2_pi * delta_f;  -- convert delta_f to rad/s
+
+begin
+
+  if To_X01(d_in) = '0' use
+    phi'dot == wc; 		-- set to carrier frequency
+  elsif To_X01(d_in) = '1' use
+    phi'dot == wc + delta_w;	-- set to carrier frequency + delta
+  else
+    phi'dot == 0.0;
+  end use;
+
+  break on d_in;
+
+  vout == offset + amp * sin(phi);  -- create sinusoidal output using phi
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk_wa.vhd
new file mode 100644
index 0000000..3a58538
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/bfsk_wa.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee, ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee.std_logic_1164.all;
+use ieee.math_real.all;
+
+entity bfsk_wa is
+
+  generic ( fc : real := 455.0e3;       -- mean carrier frequency
+            delta_f : real := 5.0e3;    -- difference between low and high
+                                        --   carrier frequency
+            amp : voltage := 1.0;       -- amplitude of modulated signal
+            offset : voltage := 0.0 );  -- output offset voltage
+
+  port ( signal d_in : in std_logic;     -- digital input
+         terminal a_out : electrical );  -- output terminal 
+
+end entity bfsk_wa;
+
+----------------------------------------------------------------
+
+architecture behavioral of bfsk_wa is
+
+  quantity vout across iout through a_out;         -- output branch
+  quantity phi : real;                             -- free quantity angle in radians
+  constant wc : real := math_2_pi * fc;            -- convert fc to rad/s
+  constant delta_w : real := math_2_pi * delta_f;  -- convert delta_f to rad/s
+
+begin
+
+  if To_X01(d_in) = '0' use
+    phi'dot == wc;             -- set to carrier frequency
+  elsif To_X01(d_in) = '1' use
+    phi'dot == wc + delta_w;   -- set to carrier frequency + delta
+  else
+    phi'dot == 0.0;
+  end use;
+
+  vout == offset + amp * sin(phi);  -- create sinusoidal output using phi
+
+end architecture behavioral;
+
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/index-ams.txt
new file mode 100644
index 0000000..d5ec212
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/index-ams.txt
@@ -0,0 +1,37 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                 Chapter 23 - Case Study 4: Communications System
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+bfsk.vhd                                        entity bfsk                             behavioral                      Figure 23-3
+bfsk_wa.vhd                                     entity bfsk_wa                          behavioral                      --
+MeasFreq.vhd                                    entity MeasFreq                         ThresDetect                     Figure 23-5
+v_BPF.vhd                                       entity v_BPF                            behavioral                      Figure 23-8
+v_Sum.vhd                                       entity v_Sum                            behavioral                      Figure 23-9
+PLL.vhd                                         entity PLL                              behavioral                      Figure 23-12
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_pll.vhd                                      entity tb_pll                           tb_pll                          PLL.vhd
+tb_CS4_CommSys_PLL.vhd                          entity VCOAnalog                        behavioral
+--                                              entity vLeadLag                         behavioral
+--                                              entity vMult                            behavioral
+--                                              entity PLL                              PLL
+--                                              entity bfsk                             behavioral
+--                                              entity vLPF_2nd                         behavioral
+--                                              entity MeasFreq                         ThresDetect
+--                                              entity a2d_bit                          ideal
+--                                              entity tb_CS4_CommSys_PLL               TB_CS4_CommSys_PLL
+tb_CS4_CommSys_det.vhd                          entity capacitor                        ideal
+--                                              entity resistor                         ideal
+--                                              entity diode                            ideal
+--                                              entity EnvDetect                        EnvDetect
+--                                              entity bfsk                             behavioral
+--                                              entity vSum                             behavioral
+--                                              entity vLPF_2nd                         behavioral
+--                                              entity vBPF                             behavioral
+--                                              entity MeasFreq                         ThresDetect
+--                                              entity a2d_bit                          ideal
+--                                              entity tb_CS4_CommSys_det               TB_CS4_CommSys_det
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_PLL.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_PLL.vhd
new file mode 100644
index 0000000..4009d13
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_PLL.vhd
@@ -0,0 +1,639 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : VCOAnalog.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/07/11
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Analog Voltage Controlled Oscillator
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/07/11  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity VCOAnalog is
+  generic (
+    Kv          : real := 100.0e3;   -- VCO Gain [Hz/Volt]
+    Fc          : real := 1.0e6;     -- center freq [Hz]
+    Vc          : voltage := 2.5;    -- input voltage that gives fc [Volts] 
+    Vcmin       : voltage := 0.0;    -- control voltage mininum [Volts]
+    Vcmax       : voltage := 5.0;    -- control voltage maximum [Volts]
+    Vout_ampl   : voltage := 1.0;    -- amplitude of output [Volts]
+    Vout_offset : voltage := 0.0     -- offset voltage of output [Volts]
+    );
+  port (
+    terminal v_inp, v_inm, output : electrical);
+end entity VCOAnalog;
+
+-------------------------------------------------------------------------------
+-- VCO Equation:
+-- Fout = Fc + Kv*Vin
+-------------------------------------------------------------------------------
+architecture behavioral of VCOAnalog is
+  quantity vout across iout through output to electrical_ref;
+  quantity vctrl across v_inp to v_inm;
+  quantity phi : real;
+  quantity vtmp : real;
+  constant Kv_w : real := math_2_pi*Kv;    -- convert to (Rad/s)/Volt
+  constant wc : real := math_2_pi*Fc;        -- convert freq to Rad/s
+
+begin  -- ARCHITECTURE behavioral
+
+  if vctrl > Vcmax use                  -- test control voltage for limits
+    vtmp == Vcmax;
+  elsif vctrl < Vcmin use
+    vtmp == Vcmin;
+  else
+    vtmp == vctrl;
+  end use;
+  									       
+  if domain = quiescent_domain use
+    phi     == 0.0;
+  else
+  -- use one of the following equations depending on preference
+  --  phi'dot == Fc + Kv*(vtmp-Vc);     -- Calculate output Freq in Rad/s
+    phi'dot == wc + Kv_w*(vtmp-Vc);     -- Calculate output Freq in Hz
+  end use;
+
+-- Use one of the following equations depending on phi'dot equation above
+--vout == Vout_offset + Vout_ampl*cos(math_2_pi*phi);
+vout == Vout_offset + Vout_ampl*cos(phi);
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : vLeadLag.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/11/09
+-- Last update: 2001/11/27
+-------------------------------------------------------------------------------
+-- Description: Lead-Lag filter with electrical connections
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/11/09  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vLeadLag is
+
+  generic (
+    K    : real := 1.0;                 -- gain
+    Fp   : real := 20.0e3;              -- pole frequency
+    Fz   : real := 1.0e6);              -- zero frequency
+
+  port (
+    terminal input, output : electrical);
+
+end entity vLeadLag;
+
+-------------------------------------------------------------------------------
+-- Transfer Fucntion:
+--
+--              1 + (s/wz)
+--  H(s) = K * ------------
+--              1 + (s/wp)
+-- 
+-------------------------------------------------------------------------------
+
+architecture behavioral of vLeadLag is
+
+  quantity vin across input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+  constant wp  : real        := math_2_pi*Fp;  -- Pole freq (in radians)
+  constant wz  : real        := math_2_pi*Fz;  -- Zero freq (in radians)
+  constant num : real_vector := (1.0, 1.0/wz);
+  constant den : real_vector := (1.0, 1.0/wp);
+
+begin
+
+  vout == K * vin'ltf(num, den);        -- Laplace transform of input
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : vMult.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/11/09
+-- Last update: 2001/11/09
+-------------------------------------------------------------------------------
+-- Description: Two input Multiplier with electrical connections 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/11/09  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vMult is
+
+  generic (K : real := 1.0);            -- Gain
+
+  port (
+    terminal in1, in2 : electrical;
+    terminal output   : electrical);
+
+end entity vMult;
+
+architecture behavioral of vMult is
+
+  quantity vin1 across in1 to electrical_ref;
+  quantity vin2 across in2 to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+
+begin
+
+  vout == k * vin1 * vin2;
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity PLL is
+    port(
+        terminal lf_out : electrical;
+        terminal input : electrical;
+        terminal vco_out : electrical
+    );
+end PLL;
+
+architecture PLL of PLL is
+    -- Component declarations
+    -- Signal declarations
+    terminal pd_out : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    vco2 : entity work.VCOAnalog(behavioral)
+        generic map(
+            Fc => 455.0e3,
+            Vcmax => 5.0,
+            Vcmin => -5.0,
+            Vc => 0.0
+        )
+        port map(
+            v_inp => lf_out,
+            output => vco_out,
+            v_inm => ELECTRICAL_REF
+        );
+    vLeadLag1 : entity work.vLeadLag(behavioral)
+        generic map(
+            Fz => 500.0e3
+        )
+        port map(
+            input => pd_out,
+            output => lf_out
+        );
+    vmult1 : entity work.vMult(behavioral)
+        port map(
+            in1 => input,
+            in2 => vco_out,
+            output => pd_out
+        );
+end PLL;
+--
+
+-- Model of Binary Frequency Shift Keying (BFSK) modulator
+-- with digital input and analog output
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.MATH_REAL.all;
+
+entity bfsk is
+  generic (
+    fc      : real    := 455.0e3;   -- Mean carrier frequency
+    delta_f : real    := 5.0e3;     -- Difference between low and high carrier frequency
+    amp     : voltage := 1.0;       -- Amplitude of modulated signal
+	offset  : voltage := 0.0        -- output offset voltage
+    );
+
+  port (
+    d_in           : in std_logic;       -- digital input
+    terminal a_out :    electrical       -- output terminal 
+    );
+end entity bfsk;
+
+architecture behavioral of bfsk is
+
+  quantity vout across iout through a_out;      -- output branch
+  quantity phi : real;                          -- free quantity for angle in radians
+  constant wc : real := math_2_pi*fc;           -- convert fc to rad/s
+  constant delta_w : real := math_2_pi*delta_f; -- convert delta_f to rad/s
+
+begin
+
+  if (d_in = '0') use
+    phi'dot == wc;               -- set to carrier frequency
+  elsif (d_in = '1') use
+    phi'dot == wc + delta_w;	 -- set to carrier frequency + delta
+  else
+    phi'dot == 0.0;
+  end use;
+
+  vout == offset + amp*sin(phi); -- create sinusoidal output using phi
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : vLPF_2nd.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/11/27
+-- Last update: 2001/11/27
+-------------------------------------------------------------------------------
+-- Description: 2nd order Lowpass Filter with Electrical connections 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/11/27  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.MATH_REAL.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vLPF_2nd is
+  generic ( K  : real := 1.0;     -- Filter Gain
+            Fp : real;            -- Double Pole Frequency [Hz]
+            Q  : real := 0.707    -- Quality factor
+            );
+  port ( terminal input  : electrical; 
+         terminal output : electrical   
+         );
+end entity vLPF_2nd;
+-------------------------------------------------------------------------------
+-- Transfer Function:
+-- 
+--                    wp^2
+-- Vo(s) = K * --------------------- Vin(s)
+--             S^2 + (wp/Q)*s + wp^2
+-------------------------------------------------------------------------------
+architecture behavioral of vLPF_2nd is
+  quantity vin across input;                 
+  quantity vout across iout through output; 
+
+  constant wp  : real        := math_2_pi*Fp;        -- Frequency in Radians
+  constant num : real_vector := (wp*wp, 0.0, 0.0);   -- Numerator array
+  constant den : real_vector := (wp*wp, wp/Q, 1.0);  -- Denominator array
+
+begin
+
+  vout == K * vin'ltf(num, den);        -- Laplace Transform of input
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+
+library ieee_proposed;  
+use ieee_proposed.electrical_systems.all;
+
+entity MeasFreq is
+  generic ( thres : real := 0.0 );    -- threshold crossing
+  port ( terminal input : electrical;
+         signal f_out : out real := 0.0);
+end entity MeasFreq;
+
+architecture ThresDetect of MeasFreq is
+  quantity vin across input;
+--  signal freq : real := 0.0;           
+begin
+--  f_out <= freq; 
+  detect : process (vin'above(thres)) is
+    variable t_old : real := real'low;
+  begin
+    if vin'above(thres) then
+      f_out <= 1.0 / (now - t_old);
+      t_old := now;
+    end if;
+  end process detect;
+end ThresDetect;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : a2d_bit.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Ideal one bit A/D converter
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+use IEEE.std_logic_1164.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity a2d_bit is
+
+  generic (
+    thres : real := 2.5);               -- Threshold to determine logic output
+
+  port (
+    terminal a :     electrical;        -- analog input
+    signal   d : out std_logic);        -- digital (std_logic) output
+
+end entity a2d_bit;
+
+-------------------------------------------------------------------------------
+-- Ideal architecture
+-- Uses 'above operator to detect threshold crossing
+-------------------------------------------------------------------------------
+architecture ideal of a2d_bit is
+
+  quantity vin across a;
+
+begin
+  
+  -- purpose: Detect threshold crossing and assign event on output (d)
+  -- type   : combinational
+  -- inputs : vin'above(thres)
+  -- outputs: pulse_signal  
+  process (vin'above(thres)) is
+  begin  -- PROCESS
+    if vin'above(thres) then
+      d <= '1';
+    else
+      d <= '0';
+    end if;
+  end process;
+
+end ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity tb_CS4_CommSys_PLL is
+end tb_CS4_CommSys_PLL;
+
+architecture TB_CS4_CommSys_PLL of tb_CS4_CommSys_PLL is
+    -- Component declarations
+    -- Signal declarations
+    terminal a_out : electrical;
+    signal baseband : std_logic;
+    terminal fsk_out : electrical;
+    signal fsk_out_f : real;
+    terminal lpf_pll_out : electrical;
+    terminal vco_out : electrical;
+  signal  bitstream : std_logic;
+    signal vco_out_f : real;
+begin
+    -- Signal assignments
+    -- Component instances
+    pll3 : entity work.PLL
+        port map(
+            vco_out => vco_out,
+            input => fsk_out,
+            lf_out => lpf_pll_out
+        );
+    BFSK4 : entity work.bfsk(behavioral)
+        port map(
+            d_in => bitstream,
+            a_out => fsk_out
+        );
+    vLPF1 : entity work.vLPF_2nd(behavioral)
+        generic map(
+            K => 200.0,
+            Fp => 50.0e3
+        )
+        port map(
+            input => lpf_pll_out,
+            output => a_out
+        );
+    MeasFreq8 : entity work.MeasFreq(ThresDetect)
+        port map(
+            input => fsk_out,
+            f_out => fsk_out_f
+        );
+    MeasFreq9 : entity work.MeasFreq(ThresDetect)
+        port map(
+            input => vco_out,
+            f_out => vco_out_f
+        );
+    a4 : entity work.a2d_bit(ideal)
+        port map(
+            D => baseband,
+            A => a_out
+        );
+  -- bitstream
+    P_bitstream :
+    process
+    begin
+      -- 0.000 
+                        wait for 0.000 ns;      bitstream <=  '0';
+      -- 50000.000 
+                        wait for 50000.000 ns;      bitstream <=  '1';
+      -- 100000.000 
+                        wait for 50000.000 ns;      bitstream <=  '0';
+      -- 150000.000 
+                        wait for 50000.000 ns;      bitstream <=  '1';
+      -- 200000.000 
+                        wait for 50000.000 ns;      bitstream <=  '0';
+      -- 300000.000 
+                        wait for 100000.000 ns;      bitstream <=  '1';
+      -- 501000.000 
+                        wait for 201000.000 ns;      bitstream <=  '0';
+      -- 550000.000 
+                        wait for 49000.000 ns;      bitstream <=  '1';
+      -- 600000.000 
+                        wait for 50000.000 ns;      bitstream <=  '0';
+      wait;
+    end process;
+
+end TB_CS4_CommSys_PLL;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_det.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_det.vhd
new file mode 100644
index 0000000..6e989b3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_CS4_CommSys_det.vhd
@@ -0,0 +1,830 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : capacitor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Electrical Capacitor 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity capacitor is
+
+  generic (
+    cap             : capacitance;        -- Capacitance [F]
+    v_ic            : real := real'low);  -- Initial voltage (activated by
+                                          -- IF statement below)
+  
+  port (
+    terminal p1, p2 : electrical);
+
+end entity capacitor;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture  (I = C * dV/dt)
+-- Includes initial condition
+-------------------------------------------------------------------------------
+architecture ideal of capacitor is
+  
+  quantity v across i through p1 to p2;
+
+begin
+
+  if domain = quiescent_domain and v_ic /= real'low use
+    v == v_ic;
+  else
+    i   == cap * v'dot;                  -- characteristic equation
+  end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : resistor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Electrical Resistor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity resistor is
+
+  generic (
+    res : resistance);                  -- resistance (no initial value)
+
+  port (
+    terminal p1, p2 : electrical);
+
+end entity resistor;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture (V = I*R)
+-------------------------------------------------------------------------------
+architecture ideal of resistor is
+
+  quantity v across i through p1 to p2;
+
+begin
+
+-- Characteristic equation
+  v == i*res;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : diode.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/11/07
+-------------------------------------------------------------------------------
+-- Description: Diode model with ideal architecture
+--              Currently no Generics due to bug in DV 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created
+-- 2001/11/07  1.1         Mentor Graphics     Added limit_exp function
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
+use IEEE_proposed.energy_systems.all;
+
+entity diode is
+
+  port (
+    terminal p, n : electrical);
+
+end entity diode;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture: i = is*(exp(v/vt) - 1)
+-------------------------------------------------------------------------------
+architecture ideal of diode is
+  
+-- Declare internal quanties and constants
+  quantity v across i through p to n;
+  constant isat  : current := 1.0e-14;        -- Saturation current [Amps]
+  constant TempC : real    := 27.0;           -- Ambient Temperature [Degrees]
+  constant TempK : real    := 273.0 + TempC;  -- Temperaure [Kelvin] 
+  constant vt    : real    := K*TempK/Q;      -- Thermal Voltage
+
+  -- This function is to limit the exponential function to avoid convergence
+  -- problems due to numerical overflow. At x=100, it becomes a straight line
+  -- with slope matching that at the intercept.  
+  function limit_exp( x : real ) return real is
+    variable abs_x      : real := abs(x);
+    variable result     : real;
+  begin
+    if abs_x < 100.0 then
+      result := exp(abs_x);
+    else
+      result := exp(100.0) * (abs_x - 99.0);
+    end if;
+  -- If exponent is negative, set exp(-x) = 1/exp(x)  
+    if x < 0.0 then
+      result := 1.0 / result;
+    end if;
+    return result;
+  end function limit_exp;
+begin  -- ideal architecture
+
+-- Characteristic equation
+  i == isat*(limit_exp(v/vt) - 1.0);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity EnvDetect is
+    port(
+        terminal input : electrical;
+        terminal output : electrical
+    );
+end EnvDetect;
+
+architecture EnvDetect of EnvDetect is
+    -- Component declarations
+    -- Signal declarations
+    terminal XSIG010001 : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    C1 : entity work.capacitor(ideal)
+        generic map(
+            cap => 0.1e-6
+        )
+        port map(
+            p1 => XSIG010001,
+            p2 => ELECTRICAL_REF
+        );
+    R1 : entity work.resistor(ideal)
+        generic map(
+            res => 1.0e3
+        )
+        port map(
+            p1 => XSIG010001,
+            p2 => ELECTRICAL_REF
+        );
+    D4 : entity work.diode(ideal)
+        port map(
+            p => input,
+            n => XSIG010001
+        );
+    C2 : entity work.capacitor(ideal)
+        generic map(
+            cap => 6.0e-6
+        )
+        port map(
+            p1 => XSIG010001,
+            p2 => output
+        );
+    R6 : entity work.resistor(ideal)
+        generic map(
+            res => 1.0e3
+        )
+        port map(
+            p1 => output,
+            p2 => ELECTRICAL_REF
+        );
+end EnvDetect;
+--
+
+-- Model of Binary Frequency Shift Keying (BFSK) modulator
+-- with digital input and analog output
+
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.MATH_REAL.all;
+
+entity bfsk is
+  generic (
+    fc      : real    := 455.0e3;   -- Mean carrier frequency
+    delta_f : real    := 5.0e3;     -- Difference between low and high carrier frequency
+    amp     : voltage := 1.0;       -- Amplitude of modulated signal
+	offset  : voltage := 0.0        -- output offset voltage
+    );
+
+  port (
+    d_in           : in std_logic;       -- digital input
+    terminal a_out :    electrical       -- output terminal 
+    );
+end entity bfsk;
+
+architecture behavioral of bfsk is
+
+  quantity vout across iout through a_out;      -- output branch
+  quantity phi : real;                          -- free quantity for angle in radians
+  constant wc : real := math_2_pi*fc;           -- convert fc to rad/s
+  constant delta_w : real := math_2_pi*delta_f; -- convert delta_f to rad/s
+
+begin
+
+  if (d_in = '0') use
+    phi'dot == wc;               -- set to carrier frequency
+  elsif (d_in = '1') use
+    phi'dot == wc + delta_w;	 -- set to carrier frequency + delta
+  else
+    phi'dot == 0.0;
+  end use;
+
+  vout == offset + amp*sin(phi); -- create sinusoidal output using phi
+
+end architecture behavioral;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : vSum.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/11/09
+-- Last update: 2001/11/09
+-------------------------------------------------------------------------------
+-- Description: Summing junction with electrical connections
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/11/09  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vSum is
+
+  generic (
+    K1 : real := 1.0;
+    K2 : real := -1.0);
+
+  port (
+    terminal in1, in2 : electrical;
+    terminal output   : electrical);
+
+end entity vSum;
+
+architecture behavioral of vSum is
+
+  quantity vin1 across in1 to electrical_ref;
+  quantity vin2 across in2 to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+
+begin
+
+  vout == K1*vin1 + K2*vin2;
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : vLPF_2nd.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/11/27
+-- Last update: 2001/11/27
+-------------------------------------------------------------------------------
+-- Description: 2nd order Lowpass Filter with Electrical connections 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/11/27  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.MATH_REAL.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vLPF_2nd is
+  generic ( K  : real := 1.0;     -- Filter Gain
+            Fp : real;            -- Double Pole Frequency [Hz]
+            Q  : real := 0.707    -- Quality factor
+            );
+  port ( terminal input  : electrical; 
+         terminal output : electrical   
+         );
+end entity vLPF_2nd;
+-------------------------------------------------------------------------------
+-- Transfer Function:
+-- 
+--                    wp^2
+-- Vo(s) = K * --------------------- Vin(s)
+--             S^2 + (wp/Q)*s + wp^2
+-------------------------------------------------------------------------------
+architecture behavioral of vLPF_2nd is
+  quantity vin across input;                 
+  quantity vout across iout through output; 
+
+  constant wp  : real        := math_2_pi*Fp;        -- Frequency in Radians
+  constant num : real_vector := (wp*wp, 0.0, 0.0);   -- Numerator array
+  constant den : real_vector := (wp*wp, wp/Q, 1.0);  -- Denominator array
+
+begin
+
+  vout == K * vin'ltf(num, den);        -- Laplace Transform of input
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : vBPF.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/11/27
+-- Last update: 2001/11/27
+-------------------------------------------------------------------------------
+-- Description: Bandpass Filter with Electrical connections 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/11/27  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity vBPF is
+  generic ( K  : real := 1.0;       -- Filter Gain
+            Fc : real;              -- Center Frequency [Hz]
+            Q  : real := 0.707      -- Quality factor
+            );
+  port ( terminal input  : electrical;   
+         terminal output : electrical  
+         );
+end entity vBPF;
+-------------------------------------------------------------------------------
+-- Transfer Function:
+-- 
+--                  wc*s
+-- Vo(s) = K * --------------------- Vin(s)
+--             S^2 + (wc/Q)*s + wc^2
+-------------------------------------------------------------------------------
+architecture behavioral of vBPF is
+  quantity vin across input;                        
+  quantity vout across iout through output;          
+  
+  constant wc  : real        := math_2_pi*Fc;       -- Frequency in Radians
+  constant num : real_vector := (0.0, wc);          -- Numerator array
+  constant den : real_vector := (wc*wc, wc/Q, 1.0); -- Denominator array
+
+begin
+
+  vout == K * vin'ltf(num, den);     -- Laplace Transform of output
+
+end architecture behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library ieee_proposed;  
+use ieee_proposed.electrical_systems.all;
+
+entity MeasFreq is
+  generic ( thres : real := 0.0 );    -- threshold crossing
+  port ( terminal input : electrical;
+         signal f_out : out real := 0.0);
+end entity MeasFreq;
+
+architecture ThresDetect of MeasFreq is
+  quantity vin across input;
+--  signal freq : real := 0.0;           
+begin
+--  f_out <= freq; 
+  detect : process (vin'above(thres)) is
+    variable t_old : real := real'low;
+  begin
+    if vin'above(thres) then
+      f_out <= 1.0 / (now - t_old);
+      t_old := now;
+    end if;
+  end process detect;
+end ThresDetect;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : a2d_bit.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Ideal one bit A/D converter
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+use IEEE.std_logic_1164.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity a2d_bit is
+
+  generic (
+    thres : real := 2.5);               -- Threshold to determine logic output
+
+  port (
+    terminal a :     electrical;        -- analog input
+    signal   d : out std_logic);        -- digital (std_logic) output
+
+end entity a2d_bit;
+
+-------------------------------------------------------------------------------
+-- Ideal architecture
+-- Uses 'above operator to detect threshold crossing
+-------------------------------------------------------------------------------
+architecture ideal of a2d_bit is
+
+  quantity vin across a;
+
+begin
+  
+  -- purpose: Detect threshold crossing and assign event on output (d)
+  -- type   : combinational
+  -- inputs : vin'above(thres)
+  -- outputs: pulse_signal  
+  process (vin'above(thres)) is
+  begin  -- PROCESS
+    if vin'above(thres) then
+      d <= '1';
+    else
+      d <= '0';
+    end if;
+  end process;
+
+end ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity tb_CS4_CommSys_det is
+end tb_CS4_CommSys_det;
+
+architecture TB_CS4_CommSys_det of tb_CS4_CommSys_det is
+    -- Component declarations
+    -- Signal declarations
+    signal baseband : std_logic;
+    signal bitstream : std_logic;
+    terminal bp1_out : electrical;
+    terminal bp2_out : electrical;
+    terminal ed1_out : electrical;
+    terminal ed2_out : electrical;
+    terminal fsk_out : electrical;
+    signal fsk_out_f : real;
+    terminal lna_in : electrical;
+    terminal lna_out : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    EnvDetect1 : entity work.EnvDetect
+        port map(
+            output => ed1_out,
+            input => bp1_out
+        );
+    EnvDetect2 : entity work.EnvDetect
+        port map(
+            output => ed2_out,
+            input => bp2_out
+        );
+    BFSK3 : entity work.bfsk(behavioral)
+        generic map(
+            amp => 5.0
+        )
+        port map(
+            d_in => bitstream,
+            a_out => fsk_out
+        );
+    vsum1 : entity work.vSum(behavioral)
+        port map(
+            in1 => ed1_out,
+            in2 => ed2_out,
+            output => lna_in
+        );
+    vLPF2 : entity work.vLPF_2nd(behavioral)
+        generic map(
+            Fp => 20.0e3,
+            K => 10000.0
+        )
+        port map(
+            input => lna_in,
+            output => lna_out
+        );
+    vBPF2 : entity work.vBPF(behavioral)
+        generic map(
+            Fc => 455.0e3
+        )
+        port map(
+            input => fsk_out,
+            output => bp2_out
+        );
+    vBPF3 : entity work.vBPF(behavioral)
+        generic map(
+            Fc => 460.0e3
+        )
+        port map(
+            input => fsk_out,
+            output => bp1_out
+        );
+    MeasFreq6 : entity work.MeasFreq(ThresDetect)
+        port map(
+            input => fsk_out,
+            f_out => fsk_out_f
+        );
+    a2 : entity work.a2d_bit(ideal)
+        generic map(
+            thres => 1.0
+        )
+        port map(
+            D => baseband,
+            A => lna_out
+        );
+ -- bitstream
+    P_bitstream :
+    process
+    begin
+      -- 0.000 
+                        wait for 0.000 ns;      bitstream <=  '0';
+      -- 50000.000 
+                        wait for 50000.000 ns;      bitstream <=  '1';
+      -- 100000.000 
+                        wait for 50000.000 ns;      bitstream <=  '0';
+      -- 150000.000 
+                        wait for 50000.000 ns;      bitstream <=  '1';
+      -- 200000.000 
+                        wait for 50000.000 ns;      bitstream <=  '0';
+      -- 300000.000 
+                        wait for 100000.000 ns;      bitstream <=  '1';
+      -- 501000.000 
+                        wait for 201000.000 ns;      bitstream <=  '0';
+      -- 550000.000 
+                        wait for 49000.000 ns;      bitstream <=  '1';
+      -- 600000.000 
+                        wait for 50000.000 ns;      bitstream <=  '0';
+      wait;
+    end process;
+
+--     KillerProc :
+--     process
+--     begin
+--       wait for 1 ns;
+--       lclclkinitwire <= '1';
+--       wait;
+--     end process;
+end TB_CS4_CommSys_det;
+ 
+ 
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_pll.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_pll.vhd
new file mode 100644
index 0000000..7b23d05
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/tb_pll.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+--
+-- File : C:\VHDL-AMS\CaseStudies\CS4_CommSystem\Default\genhdl\vhdl\tb_pll.vhd
+-- CDB  : C:\VHDL-AMS\CaseStudies\CS4_CommSystem\default\default.cdb
+-- By   : CDB2VHDL Netlister version 16.1.0.2
+-- Time : Fri Apr 05 12:08:46 2002
+
+-- Entity/architecture declarations 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity tb_pll is
+end tb_pll;
+
+architecture tb_pll of tb_pll is
+    -- Component declarations
+    -- Signal declarations
+    signal f_ref : real;
+    terminal lf_out : electrical;
+    terminal v_ref : electrical;
+    signal vco_f : real;
+    terminal vco_out : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    PLL6 : entity work.PLL(behavioral)
+        generic map(
+            Fp => 20.0e3,
+            Fz => 1.0e6,
+            Kv => 100.0e3,
+            Fc => 1.0e6
+        )
+        port map(
+            input => v_ref,
+            lf_out => lf_out,
+            vco_out => vco_out
+        );
+    v1 : entity work.v_SweptSine(bhv)
+        generic map(
+            StartFreq => 900.0e3,
+            SweepRate => 2000.0e6,
+            FinishFreq => 1.1e6,
+            InitDelay => 80.0e-6,
+            PeakAmp => 5.0
+        )
+        port map(
+            pos => v_ref,
+            neg => ELECTRICAL_REF
+        );
+    MeasFreq9 : entity work.MeasFreq(ThresDetect)
+        port map(
+            input => v_ref,
+            f_out => f_ref
+        );
+    MeasFreq10 : entity work.MeasFreq(ThresDetect)
+        port map(
+            input => vco_out,
+            f_out => vco_f
+        );
+end tb_pll;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_BPF.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_BPF.vhd
new file mode 100644
index 0000000..6558c1c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_BPF.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity v_BPF is
+
+  generic ( k : real := 1.0;	   -- filter gain
+            fo : real := 100.0e3;  -- center frequency [Hz]
+            q : real := 0.707 );   -- quality factor
+
+  port ( terminal input	: electrical;   
+         terminal output : electrical );
+
+end entity v_BPF;
+
+----------------------------------------------------------------
+
+architecture behavioral of v_BPF is
+
+  quantity vin across input;                        
+  quantity vout across iout through output;            
+  constant wo : real := math_2_pi * fo;		         -- frequency in radians
+  constant num : real_vector := (0.0, wo);	         -- numerator array
+  constant den : real_vector := (wo * wo, wo / q, 1.0);  -- denominator array
+
+begin
+
+  vout == k * vin'ltf(num, den);     -- Laplace transform of output
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_Sum.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_Sum.vhd
new file mode 100644
index 0000000..e3d4c1e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_Sum.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;  use IEEE_proposed.electrical_systems.all;
+
+entity v_Sum is
+  generic ( k1 : real := 1.0;
+            k2 : real := -1.0 );
+  port ( terminal in1, in2 : electrical;
+         terminal output : electrical );
+end entity v_Sum;
+
+----------------------------------------------------------------
+
+architecture behavioral of v_Sum is
+
+  quantity vin1 across in1 to electrical_ref;
+  quantity vin2 across in2 to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+
+begin
+
+  vout == k1 * vin1 + k2 * vin2;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/amp_lim.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/amp_lim.vhd
new file mode 100644
index 0000000..8c1059d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/amp_lim.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity amp_lim is
+  port ( terminal ps : electrical;               -- positive supply terminal
+         terminal input, output : electrical );
+end entity amp_lim;
+
+----------------------------------------------------------------
+
+architecture simple of amp_lim is
+
+  quantity v_pwr across i_pwr through ps to electrical_ref;
+  quantity vin across iin through input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+  quantity v_amplified : voltage ;
+  constant gain : real := 1.0;
+
+begin
+
+  v_amplified == gain * vin;
+
+  if v_amplified'above(v_pwr) use 
+    vout == v_pwr;
+  else 
+    vout == v_amplified;
+  end use;
+
+  break on v_amplified'above(v_pwr);
+
+  -- ignore loading effects
+  i_pwr == 0.0;
+  iin == 0.0;
+
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/index-ams.txt
new file mode 100644
index 0000000..13d7da7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/index-ams.txt
@@ -0,0 +1,200 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                  Chapter 26 - Case Study 5: RC Airplane System
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+amp_lim.vhd                                     entity amp_lim                          simple                          Figure 26-10
+pwl_functions.vhd                               package pwl_functions                   body                            Figure 26-20
+prop_pwl.vhd                                    entity prop_pwl                         ideal                           Figure 26-20
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_CS5_Amp_Lim.vhd                              entity sum2_e                           simple
+--                                              entity gain_e                           simple
+--                                              entity limiter_2_e                      simple
+--                                              entity lead_lag_e                       simple
+--                                              entity rudder_servo                     rudder_servo
+--                                              entity gear_rv_r                        ideal
+--                                              entity rot2v                            bhv
+--                                              entity horn_r2t                         bhv
+--                                              entity horn_t2r                         bhv
+--                                              entity DC_Motor                         basic
+--                                              entity stop_r                           ideal
+--                                              entity tran_linkage                     a1
+--                                              entity rudder                           bhv
+--                                              entity resistor                         ideal
+--                                              entity amp_lim                          simple
+--                                              entity v_pulse                          ideal
+--                                              entity v_pwl_full                       ideal
+--                                              entity tb_CS5_Amp_Lim                   TB_CS5_Amp_Lim
+tb_CS5_Prop.vhd                                 entity DC_Motor                         basic
+--                                              entity v_constant                       ideal
+--                                              entity switch_dig_log                   linear
+--                                              entity switch_dig_log                   log
+--                                              entity opamp                            basic
+--                                              entity resistor                         ideal
+--                                              entity comparator_d                     behavioral
+--                                              entity v_pulse                          ideal
+--                                              entity pwm_mac                          pwm_mac
+--                                              entity prop_pwl                         ideal
+--                                              entity diode_pwl                        simple
+--                                              entity v_sine                           ideal
+--                                              entity tb_CS5_Prop                      TB_CS5_Prop
+tb_CS5_CC_Rudder.vhd                            entity sum2_e                           simple
+--                                              entity gain_e                           simple
+--                                              entity limiter_2_e                      simple
+--                                              entity lead_lag_e                       simple
+--                                              entity rudder_servo                     rudder_servo
+--                                              entity gear_rv_r                        ideal
+--                                              entity rot2v                            bhv
+--                                              entity horn_r2t                         bhv
+--                                              entity horn_t2r                         bhv
+--                                              entity tran_linkage                     a1
+--                                              entity rudder                           bhv
+--                                              entity v_constant                       ideal
+--                                              entity stick                            ideal
+--                                              entity RF_xmtr_rcvr                     behavioral
+--                                              entity switch_dig_2in                   ideal
+--                                              entity clock                            ideal
+--                                              entity clock_duty                       ideal
+--                                              entity rc_clk                           rc_clk
+--                                              entity bit_cnt                          behavioral
+--                                              entity state_mach1                      state_diagram
+--                                              entity sm_cnt                           sm_cnt
+--                                              entity a2d_nbit                         sar
+--                                              entity shift_reg                        behavioral
+--                                              entity frame_gen                        simple
+--                                              entity xor2                             ideal
+--                                              entity level_set_tri                    ideal
+--                                              entity buffer_tri                       ideal
+--                                              entity d2a_bit                          ideal
+--                                              entity parity_gen                       parity_gen
+--                                              entity tdm_encoder                      tdm_encoder
+--                                              entity menc_rsc                         bhv
+--                                              entity Digitize_Encode_Man              Digitize_Encode_Man
+--                                              entity lpf_2_e                          simple
+--                                              entity and2                             ideal
+--                                              entity d_latch_n_edge_rst               behav
+--                                              entity counter_12                       counter_12
+--                                              entity a2d_bit                          ideal
+--                                              entity clock_en                         ideal
+--                                              entity inverter                         ideal
+--                                              entity or2                              ideal
+--                                              entity d2a_nbit                         behavioral
+--                                              entity pw2ana                           pw2ana
+--                                              entity DC_Motor                         basic
+--                                              entity stop_r                           ideal
+--                                              entity dig_cmp                          simple
+--                                              entity resistor                         ideal
+--                                              entity sr_ff                            simple
+--                                              entity state_mach_rcvr                  state_diagram
+--                                              entity sm_cnt_rcvr                      sm_cnt_rcvr
+--                                              entity level_set                        ideal
+--                                              entity ser2par                          a1
+--                                              entity frame_det                        simple
+--                                              entity parity_det                       parity_det
+--                                              entity TDM_Demux_dbg                    TDM_Demux_dbg
+--                                              entity mdec_rsc                         bhv
+--                                              entity mdec_rsc                         bhv_8
+--                                              entity Decode_PW_Man                    Decode_PW_Man
+--                                              entity tb_CS5_CC_Rudder                 TB_CS5_CC_Rudder
+tb_CS5_Rudder_Power.vhd                         entity sum2_e                           simple
+--                                              entity gain_e                           simple
+--                                              entity limiter_2_e                      simple
+--                                              entity lead_lag_e                       simple
+--                                              entity rudder_servo                     rudder_servo
+--                                              entity gear_rv_r                        ideal
+--                                              entity rot2v                            bhv
+--                                              entity horn_r2t                         bhv
+--                                              entity horn_t2r                         bhv
+--                                              entity DC_Motor                         basic
+--                                              entity stop_r                           ideal
+--                                              entity tran_linkage                     a1
+--                                              entity rudder                           bhv
+--                                              entity switch_dig_log                   linear
+--                                              entity switch_dig_log                   log
+--                                              entity buff                             ideal
+--                                              entity inverter                         ideal
+--                                              entity opamp                            basic
+--                                              entity resistor                         ideal
+--                                              entity v_constant                       ideal
+--                                              entity comparator_d                     behavioral
+--                                              entity v_pulse                          ideal
+--                                              entity pwm_mac                          pwm_mac
+--                                              entity diode_pwl                        simple
+--                                              entity pwm_H_bridge                     pwm_H_bridge
+--                                              entity stick                            ideal
+--                                              entity inductor                         ideal
+--                                              entity capacitor                        ideal
+--                                              entity capacitor                        ESR
+--                                              entity buck_sw                          average
+--                                              entity sw_LoopCtrl                      ideal
+--                                              entity comp_2p2z                        ltf
+--                                              entity ex_buck                          ex_buck
+--                                              entity tb_CS5_Rudder_Power              TB_CS5_Rudder_Power
+tb_CS5_HCL.vhd                                  entity sum2_e                           simple
+--                                              entity gain_e                           simple
+--                                              entity limiter_2_e                      simple
+--                                              entity lead_lag_e                       simple
+--                                              entity rudder_servo                     rudder_servo
+--                                              entity gear_rv_r                        ideal
+--                                              entity rot2v                            bhv
+--                                              entity horn_r2t                         bhv
+--                                              entity horn_t2r                         bhv
+--                                              entity DC_Motor                         basic
+--                                              entity stop_r                           ideal
+--                                              entity tran_linkage                     a1
+--                                              entity rudder                           bhv
+--                                              entity v_constant                       ideal
+--                                              entity stick                            ideal
+--                                              entity RF_xmtr_rcvr                     behavioral
+--                                              entity switch_dig_2in                   ideal
+--                                              entity clock                            ideal
+--                                              entity clock_duty                       ideal
+--                                              entity rc_clk                           rc_clk
+--                                              entity bit_cnt                          behavioral
+--                                              entity state_mach1                      state_diagram
+--                                              entity sm_cnt                           sm_cnt
+--                                              entity a2d_nbit                         sar
+--                                              entity shift_reg                        behavioral
+--                                              entity frame_gen                        simple
+--                                              entity xor2                             ideal
+--                                              entity level_set_tri                    ideal
+--                                              entity buffer_tri                       ideal
+--                                              entity d2a_bit                          ideal
+--                                              entity parity_gen                       parity_gen
+--                                              entity tdm_encoder                      tdm_encoder
+--                                              entity menc_rsc                         bhv
+--                                              entity Digitize_Encode_Man              Digitize_Encode_Man
+--                                              entity and2                             ideal
+--                                              entity d_latch_n_edge_rst               behav
+--                                              entity counter_12                       counter_12
+--                                              entity dig_cmp                          simple
+--                                              entity resistor                         ideal
+--                                              entity clock_en                         ideal
+--                                              entity sr_ff                            simple
+--                                              entity inverter                         ideal
+--                                              entity state_mach_rcvr                  state_diagram
+--                                              entity sm_cnt_rcvr                      sm_cnt_rcvr
+--                                              entity level_set                        ideal
+--                                              entity ser2par                          a1
+--                                              entity frame_det                        simple
+--                                              entity parity_det                       parity_det
+--                                              entity d2a_nbit                         behavioral
+--                                              entity TDM_Demux_dbg                    TDM_Demux_dbg
+--                                              entity mdec_rsc                         bhv
+--                                              entity mdec_rsc                         bhv_8
+--                                              entity Decode_PW_Man                    Decode_PW_Man
+--                                              entity lpf_2_e                          simple
+--                                              entity a2d_bit                          ideal
+--                                              entity or2                              ideal
+--                                              entity pw2ana                           pw2ana
+--                                              entity v_pulse                          ideal
+--                                              entity v_pwl                            ideal
+--                                              entity plane_pos_src                    plane_pos_src
+--                                              entity integ_1_e                        simple
+--                                              entity lpf_1_e                          simple
+--                                              entity hcl                              hcl
+--                                              entity tb_CS5_HCL                       TB_CS5_HCL
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/prop_pwl.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/prop_pwl.vhd
new file mode 100644
index 0000000..739a9c4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/prop_pwl.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.mechanical_systems.all;
+
+entity prop_pwl is
+  generic ( ydata : real_vector;    -- torque data points
+            xdata : real_vector );  -- velocity data points
+  port ( terminal shaft1 : rotational_v );
+end entity prop_pwl;
+
+----------------------------------------------------------------
+
+architecture ideal of prop_pwl is
+
+  use work.pwl_functions.all;
+
+  quantity w across torq through shaft1 to rotational_v_ref;
+
+begin
+
+  torq == pwl_dim1_extrap(w, xdata, ydata);
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd
new file mode 100644
index 0000000..f45a815
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/pwl_functions.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee; use ieee.math_real.all;
+
+package pwl_functions is
+
+  function pwl_dim1_extrap ( x : in real;  xdata, ydata : in real_vector ) 
+	return real;
+
+  function interpolate (x,y2,y1,x2,x1 : in real) 
+	return real;
+  
+  function extrapolate (x,y2,y1,x2,x1 : in real) 
+	return real;
+  
+end package pwl_functions;
+
+
+package body pwl_functions is
+
+  -- code from book  
+
+  function pwl_dim1_extrap ( x : in real;  xdata, ydata : in real_vector ) 
+	                   return real is
+
+    variable xvalue, yvalue, m : real;
+    variable start, fin, mid: integer;
+
+  begin
+    if x <= xdata(0) then
+      yvalue := extrapolate ( x, ydata(1), ydata(0), xdata(1), xdata(0) );
+      return yvalue;
+    end if;
+
+    if x >= xdata(xdata'right) then
+      yvalue := extrapolate( x, ydata(ydata'right), ydata(ydata'right - 1),
+                                xdata(xdata'right), xdata(xdata'right - 1) );
+      return yvalue;
+    end if;
+
+    start := 0;
+    fin := xdata'right;
+    while start <= fin loop
+      mid := (start + fin) / 2; 
+      if xdata(mid) < x then 
+        start := mid + 1;
+      else
+        fin := mid - 1;
+      end if;  
+    end loop; 
+    if xdata(mid) > x then 
+      mid := mid - 1; 
+    end if; 
+    yvalue := interpolate( x, ydata(mid + 1), ydata(mid),
+                              xdata(mid + 1), xdata(mid) );    
+    return yvalue;
+  end function pwl_dim1_extrap;
+
+  -- end code from book
+
+  function interpolate (x,y2,y1,x2,x1 : in real) 
+    return real is 
+    variable m, yvalue : real;
+  begin
+    assert (x1 /= x2)
+      report "interpolate: x1 cannot be equal to x2"
+      severity error;
+    assert (x >= x1) and (x <= x2) 
+      report "interpolate: x must be between x1 and x2, inclusively "
+      severity error;
+    m := (y2 - y1)/(x2 - x1);
+    yvalue := y1 + m*(x - x1);
+    return yvalue;
+  end function interpolate;
+	
+  function extrapolate (x,y2,y1,x2,x1 : in real) 
+    return real is 
+    variable m, yvalue : real;
+  begin
+    assert (x1 /= x2)
+      report "extrapolate: x1 cannot be equal to x2"
+      severity error;
+    assert (x <= x1) or (x >= x2) 
+      report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
+      severity warning;
+    m := (y2 - y1)/(x2 - x1);
+    yvalue := y1 + m*(x - x1);
+    return yvalue;
+  end function extrapolate;
+
+end package body pwl_functions;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
new file mode 100644
index 0000000..41fedb4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
@@ -0,0 +1,1095 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+	generic (k1, k2: real := 1.0);  -- Gain multipliers
+	port 	(	terminal in1, in2: electrical;
+			terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+  QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+  QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+	generic (
+		k: REAL := 1.0);  -- Gain multiplier
+	port 	(	terminal input : electrical;
+			terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+	generic (
+		limit_high : real := 4.8;	-- upper limit
+		limit_low : real := -4.8); 	-- lower limit
+	port (
+		terminal input: electrical;
+		terminal output: electrical);					
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+  	QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  	QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+	constant slope : real := 1.0e-4;
+begin
+	if vin > limit_high use	-- Upper limit exceeded, so limit input signal
+		vout == limit_high + slope*(vin - limit_high);
+	elsif vin < limit_low use	-- Lower limit exceeded, so limit input signal
+		vout == limit_low + slope*(vin - limit_low);
+	else		-- No limit exceeded, so pass input signal as is
+		vout == vin;
+	end use;
+	break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+--  Transfer Function:
+--
+--                  (s + w1)         
+--    H(s) =  k *  ----------
+--                  (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lead_lag_e is
+	generic (
+		k: real := 1.0;  			-- Gain multiplier
+		f1: real := 10.0;			-- First break frequency (zero)
+		f2: real := 100.0);		-- Second break frequency (pole)
+	port 	(	terminal input: electrical;
+			terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+	quantity vin_temp : real;
+	constant w1 : real := f1*math_2_pi;
+	constant w2 : real := f2*math_2_pi;
+	constant num : real_vector := (w1, 1.0);                                                    
+	constant den : real_vector := (w2, 1.0);
+begin
+	vin_temp == vin;
+	vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo is
+    port(
+        terminal servo_in : electrical;
+        terminal pos_fb : electrical;
+        terminal servo_out : electrical
+    );
+end rudder_servo;
+
+architecture rudder_servo of rudder_servo is
+    -- Component declarations
+    -- Signal declarations
+    terminal error : electrical;
+    terminal ll_in : electrical;
+    terminal ll_out : electrical;
+    terminal summer_fb : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    summer : entity work.sum2_e(simple)
+        port map(
+            in1 => servo_in,
+            in2 => summer_fb,
+            output => error
+        );
+    forward_gain : entity work.gain_e(simple)
+        generic map(
+            k => 100.0
+        )
+        port map(
+            input => error,
+            output => ll_in
+        );
+    fb_gain : entity work.gain_e(simple)
+        generic map(
+            k => -4.57
+        )
+        port map(
+            input => pos_fb,
+            output => summer_fb
+        );
+    XCMP21 : entity work.limiter_2_e(simple)
+          generic map(
+            limit_high => 4.8,
+            limit_low => -4.8
+        )
+        port map(
+            input => ll_out,
+            output => servo_out
+        );
+    XCMP22 : entity work.lead_lag_e(simple)
+        generic map(
+            f2 => 2000.0,
+            f1 => 5.0,
+            k => 400.0
+        )
+        port map(
+            input => ll_in,
+            output => ll_out
+        );
+end rudder_servo;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : gear_rv_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/10/10  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+  generic(
+    ratio : real := 1.0);   -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+                            -- Note: can be negative, if shaft polarity changes
+
+  port ( terminal rotv1 : rotational_v;
+  		terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+  quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+--  quantity w2 across torq2 through rotv2 to rotational_v_ref;
+  quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+--  w2  == w1*ratio;
+  theta == ratio*w1'integ;
+  torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+  
+  generic (
+    k : real := 1.0);                -- optional gain
+
+  port (
+    terminal input   : rotational;  -- input terminal
+    terminal output    : electrical);   -- output terminal
+  
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref;     -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+  begin  -- bhv
+   v_out ==  k*rot_in; 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  tran =   R*sin(rot) 
+--
+-- Where pos = output translational position,
+-- R = horn radius, 
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+  
+  generic (
+    R   : real := 1.0);            		-- horn radius
+
+  port (
+    terminal theta    : ROTATIONAL;   	-- input angular position port
+    terminal pos   : TRANSLATIONAL);  	-- output translational position port
+     
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+  begin			-- bhv
+   tran == R*sin(rot);		-- Convert angle in to translational out
+   tran_frc == -rot_tq/R;	-- Convert torque in to force out 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  theta =   arcsin(pos/R) 
+--
+-- Where pos = input translational position,
+-- R = horn radius, 
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+  
+  generic (
+    R   : real := 1.0);            -- Rudder horn radius
+
+  port (
+    terminal pos    : translational;   -- input translational position port
+    terminal theta   : rotational);  -- output angular position port
+     
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+  begin  -- bhv
+   rot == arcsin(tran/R);	-- Convert translational to angle
+   rot_tq == -tran_frc*R;	-- Convert force to torque
+   
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : DC_Motor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+  generic (
+    r_wind : resistance;                -- Motor winding resistance [Ohm]
+    kt     : real;                      -- Torque coefficient [N*m/Amp]
+    l      : inductance;                -- Winding inductance [Henrys]
+    d      : real;                      -- Damping coefficient [N*m/(rad/sec)]
+    j      : mmoment_i);                -- Moment of inertia [kg*meter**2]
+
+  port (terminal p1, p2 : electrical;
+        terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations:  V = Kt*W + I*Rwind + L*dI/dt
+--                   T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+  quantity v across i through p1 to p2;
+  quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+  torq == -1.0*kt*i + d*w + j*w'dot;
+  v  == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : stop_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+  generic (
+    k_stop    : real;
+--    ang_max   : angle;
+--    ang_min   : angle := 0.0;
+	ang_max   : real;
+    ang_min   : real := 0.0;
+    damp_stop : real  := 0.000000001
+    );
+
+  port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+  quantity velocity : velocity;
+  quantity ang across trq through ang1 to ang2;
+
+begin
+
+  velocity == ang'dot;
+
+  if ang'above(ang_max) use
+    trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+  elsif ang'above(ang_min) use
+    trq   == 0.0;
+  else
+    trq   == k_stop * (ang - ang_min) + (damp_stop * velocity);
+  end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+      terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+  QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+  QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+   pos_2 == pos_1;		-- Pass position 
+   frc_2 == -frc_1;	-- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+--  Transfer Function:
+--                            
+--  torq =   -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+  
+  generic (
+    k   : real := 1.0;            -- Spring constant
+	theta_0 : real := 0.0);
+
+  port (
+    terminal rot    : rotational);   -- input rotational angle
+     
+end entity rudder;
+
+architecture bhv of rudder is
+
+  QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+  begin  -- bhv
+
+   torq == k*(theta - theta_0);	-- Convert force to torque
+   
+end bhv;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical Resistor Model
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY resistor IS 
+
+-- Initialize parameters
+  GENERIC (
+    res : RESISTANCE);                 -- resistance (no initial value)
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL p1, p2 : ELECTRICAL);
+
+END ENTITY resistor;
+
+-- Ideal Architecture (V = I*R)
+ARCHITECTURE ideal OF resistor IS
+  
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH p1 TO p2;
+
+BEGIN
+  
+-- Characteristic equations
+  v == i*res;                       
+
+END ARCHITECTURE ideal;
+
+--
+library ieee_proposed;  
+use ieee_proposed.electrical_systems.all;
+
+entity amp_lim is
+		port (terminal ps : electrical; -- positive supply terminal
+			terminal input, output : electrical);
+end entity amp_lim;
+
+
+architecture simple of amp_lim is
+	quantity v_pwr across i_pwr through ps to electrical_ref;
+	quantity vin across iin through input to electrical_ref;
+	quantity vout across iout through output to electrical_ref;
+	quantity v_amplified : voltage ;
+	constant gain : real := 1.0;
+begin
+	v_amplified == gain*vin;
+	
+	if v_amplified > v_pwr use 
+		vout == v_pwr;
+	else 
+		vout == v_amplified;
+	end use;	
+	
+	-- ignore loading effects
+	i_pwr == 0.0;
+	iin  == 0.0;
+
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : v_pulse.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/07/09
+-------------------------------------------------------------------------------
+-- Description:  Voltage Pulse Source
+--               Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created
+-- 2001/07/09  1.1         Mentor Graphics     Changed input parameters to type
+--                                             time.  Uses time2real function.
+--                                             Pulsewidth no longer includes
+--                                             rise and fall times.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_pulse is
+
+  generic (
+    initial  : voltage := 0.0;          -- initial value [Volts]
+    pulse    : voltage;                 -- pulsed value [Volts]
+    ti2p     : time    := 1ns;          -- initial to pulse [Sec]
+    tp2i     : time    := 1ns;          -- pulse to initial [Sec]
+    delay    : time    := 0ms;          -- delay time [Sec]
+    width    : time;                    -- duration of pulse [Sec]
+    period   : time;                    -- period [Sec]
+    ac_mag   : voltage := 1.0;          -- AC magnitude [Volts]
+    ac_phase : real    := 0.0);         -- AC phase [Degrees]
+
+  port (
+    terminal pos, neg : electrical);
+
+end entity v_pulse;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_pulse is
+
+-- Declare Through and Across Branch Quantities
+  quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis 
+  quantity ac_spec      : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+-- Signal used in CreateEvent process below  
+  signal   pulse_signal : voltage := initial;
+  
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+-- Note: these lines gave an error during simulation.  Had to use a
+-- function call instead.
+--  constant ri2p : real := time'pos(ti2p) * 1.0e-15;
+--  constant rp2i : real := time'pos(tp2i) * 1.0e-15;
+  
+-- Function to convert numbers of type TIME to type REAL
+  function time2real(tt : time) return real is
+  begin
+    return time'pos(tt) * 1.0e-15;
+  end time2real;
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+  constant ri2p         : real    := time2real(ti2p);
+  constant rp2i         : real    := time2real(tp2i);
+
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+    v == pulse_signal'ramp(ri2p, rp2i);  -- create rise and fall transitions
+  else
+    v   == ac_spec;                        -- used for Frequency (AC) analysis
+  end use;
+
+-- purpose: Create events to define pulse shape
+-- type   : combinational
+-- inputs : 
+-- outputs: pulse_signal
+CreateEvent : process
+begin
+  wait for delay;
+  loop
+    pulse_signal <= pulse;
+    wait for (width + ti2p);
+    pulse_signal <= initial;
+    wait for (period - width - ti2p);
+  end loop;
+end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.math_real.all;
+package pwl_full_functions is
+
+	function next_increment(x : in real; xdata : in real_vector ) 
+		return real;
+	function interpolate (x,y2,y1,x2,x1 : in real) 
+		return real;
+	function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector ) 
+		return real;
+
+end package pwl_full_functions;
+
+package body pwl_full_functions is
+
+	function next_increment(x : in real; xdata : in real_vector) 
+		return real is 
+		variable i : integer;
+	begin
+		i := 0;
+		while i <= xdata'right loop
+	    	if x >= xdata(i) - 6.0e-15 then   -- The value 6.0e-15 envelopes round-off error 
+			                                  -- of real-to-time conversion in calling model
+				i := i + 1;
+			else
+				return xdata(i) - xdata(i - 1);
+            end if;  
+        end loop;
+ 	    return 1.0;  -- Returns a "large number" relative to expected High-Speed time scale
+	end function next_increment;
+
+	function interpolate (x,y2,y1,x2,x1 : in real) 
+		return real is 
+		variable m, yvalue : real;
+	 begin
+	 	assert (x1 /= x2)
+			report "interpolate: x1 cannot be equal to x2"
+			severity error;
+		assert (x >= x1) and (x <= x2) 
+			report "interpolate: x must be between x1 and x2, inclusively "
+			severity error;
+	
+		m := (y2 - y1)/(x2 - x1);
+		yvalue := y1 + m*(x - x1);
+		return yvalue;
+	end function interpolate;
+
+ 	    --  Created a new pwl_dim1_flat function that returns a constant 
+		-- value of ydata(0) if  x < xdata(0), or ydata(ydata'right) if x > xdata(xdata'right)
+
+	function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector ) 
+		return real is 
+		variable xvalue, yvalue, m : real;
+                variable start, fin, mid: integer; 
+	begin
+		if x >= xdata(xdata'right) then
+			yvalue := ydata(ydata'right);
+			return yvalue;
+		end if;
+		if x <= xdata(0) then
+			yvalue := ydata(0);
+			return yvalue;
+		end if;
+                start:=0;
+                fin:=xdata'right;
+-- I assume that the valid elements are from  xdata(0) to xdata(fin), inclusive. 
+-- so fin==n-1 in C terms (where n is the size of the array). 
+		while  start <=fin  loop
+                        mid:=(start+fin)/2; 
+	                if xdata(mid) < x
+                         then start:=mid+1;
+                         else fin:=mid-1;
+                    end if;  
+                end loop; 
+                                
+                if xdata(mid) > x
+                        then mid:=mid-1; 
+                 end if; 
+                 yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));               
+		
+		return yvalue;
+	end function pwl_dim1_flat;
+
+end package body pwl_full_functions;
+
+-- Not sure the sync_tdata process is necessary. Requires the tdata set contain
+-- a larger value than the actual simulation time.
+--  Piece-wise linear voltage source model
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+Library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all; 
+use work.pwl_full_functions.all;
+ 
+entity v_pwl_full is
+generic (	
+	vdata : real_vector;  -- v-pulse data 
+	tdata : real_vector   -- time-data for v-pulse
+	);
+
+port (	
+	terminal pos, neg :  electrical
+	);
+end entity v_pwl_full;
+
+
+architecture ideal of v_pwl_full is
+
+QUANTITY v across i through pos TO neg;
+signal tick : std_logic := '0';                -- Sync signal for tdata "tracking"
+
+begin
+				
+sync_tdata: process is
+variable next_tick_delay : real := 0.0;  -- Time increment to the next time-point in tdata
+begin	
+	wait until domain = time_domain;
+	loop
+		next_tick_delay := next_increment(NOW,tdata);
+		tick <= (not tick) after (integer(next_tick_delay * 1.0e15) * 1 fs);
+		wait on tick;
+	end loop;
+end process sync_tdata;
+
+break on tick;		-- Forces analog solution point at all tdata time-points
+		
+v == pwl_dim1_flat(NOW, tdata, vdata);
+
+end architecture ideal;
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.fluidic_systems.all;
+use IEEE_proposed.thermal_systems.all;
+use IEEE_proposed.radiant_systems.all;
+
+entity tb_CS5_Amp_Lim is
+end tb_CS5_Amp_Lim;
+
+architecture TB_CS5_Amp_Lim of tb_CS5_Amp_Lim is
+    -- Component declarations
+    -- Signal declarations
+    terminal amp_in : electrical;
+    terminal gear_out : rotational;
+    terminal link_in : translational;
+    terminal link_out : translational;
+    terminal mot_in : electrical;
+    terminal mot_out : rotational_v;
+    terminal pos_fb_v : electrical;
+    terminal power : electrical;
+    terminal rudder_in : rotational;
+    terminal src_in : electrical;
+    terminal XSIG010068 : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    rudder_servo1 : entity work.rudder_servo
+        port map(
+            servo_out => amp_in,
+            servo_in => src_in,
+            pos_fb => pos_fb_v
+        );
+    gear3 : entity work.gear_rv_r(ideal)
+        generic map(
+            ratio => 0.01
+        )
+        port map(
+            rotv1 => mot_out,
+            rot2 => gear_out
+        );
+    r2v : entity work.rot2v(bhv)
+        generic map(
+            k => 1.0
+        )
+        port map(
+            output => pos_fb_v,
+            input => gear_out
+        );
+    r2t : entity work.horn_r2t(bhv)
+        port map(
+            theta => gear_out,
+            pos => link_in
+        );
+    t2r : entity work.horn_t2r(bhv)
+        port map(
+            theta => rudder_in,
+            pos => link_out
+        );
+    motor1 : entity work.DC_Motor(basic)
+        generic map(
+            j => 168.0e-9,
+            d => 5.63e-6,
+            l => 2.03e-3,
+            kt => 3.43e-3,
+            r_wind => 2.2
+        )
+        port map(
+            p1 => mot_in,
+            p2 => ELECTRICAL_REF,
+            shaft_rotv => mot_out
+        );
+    stop1 : entity work.stop_r(ideal)
+        generic map(
+            ang_min => -1.05,
+            ang_max => 1.05,
+            k_stop => 1.0e6,
+            damp_stop => 1.0e2
+        )
+        port map(
+            ang1 => gear_out,
+            ang2 => ROTATIONAL_REF
+        );
+    XCMP35 : entity work.tran_linkage(a1)
+        port map(
+            p2 => link_out,
+            p1 => link_in
+        );
+    XCMP36 : entity work.rudder(bhv)
+        generic map(
+            k => 0.2
+        )
+        port map(
+            rot => rudder_in
+        );
+    R2w : entity work.resistor(ideal)
+        generic map(
+            res => 1000.0
+        )
+        port map(
+            p1 => XSIG010068,
+            p2 => ELECTRICAL_REF
+        );
+    XCMP55 : entity work.amp_lim(simple)
+        port map(
+            input => amp_in,
+            output => mot_in,
+            ps => power
+        );
+    v9 : entity work.v_pulse(ideal)
+        generic map(
+            initial => 0.0,
+            pulse => 4.8,
+            ti2p => 300ms,
+            tp2i => 300ms,
+            delay => 100ms,
+            width => 5ms,
+            period => 605ms
+        )
+        port map(
+            pos => src_in,
+            neg => ELECTRICAL_REF
+        );
+    XCMP57 : entity work.v_pwl_full(ideal)
+        generic map(
+            tdata => (0.0,100.0e-3,400.0e-3,900.0e-3,1300.0e-3,1800.0e-3,2300.0e-3,2600.0e-3, 2900.0e-3),
+            vdata => (0.0,0.0,2.4,2.4,4.7,4.7,1.0,1.0,0.0)
+        )
+        port map(
+            pos => XSIG010068,
+            neg => ELECTRICAL_REF
+        );
+    XCMP60 : entity work.v_pwl_full(ideal)
+        generic map(
+            vdata => (4.8,4.8,4.4,4.4,4.0,4.0,3.6,3.6,3.2,3.2),
+            tdata => (0.0,705.0e-3,706.0e-3,1310.0e-3,1320.0e-3,1915.0e-3,1925.0e-3,2520.0e-3,2530.0e-3,3125.0e-3)
+        )
+        port map(
+            pos => power,
+            neg => ELECTRICAL_REF
+        );
+end TB_CS5_Amp_Lim;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
new file mode 100644
index 0000000..60fdc24
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
@@ -0,0 +1,3668 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+	generic (k1, k2: real := 1.0);  -- Gain multipliers
+	port 	(	terminal in1, in2: electrical;
+			terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+  QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+  QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+	generic (
+		k: REAL := 1.0);  -- Gain multiplier
+	port 	(	terminal input : electrical;
+			terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+	generic (
+		limit_high : real := 4.8;	-- upper limit
+		limit_low : real := -4.8); 	-- lower limit
+	port (
+		terminal input: electrical;
+		terminal output: electrical);					
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+  	QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  	QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+	constant slope : real := 1.0e-4;
+begin
+	if vin > limit_high use	-- Upper limit exceeded, so limit input signal
+		vout == limit_high + slope*(vin - limit_high);
+	elsif vin < limit_low use	-- Lower limit exceeded, so limit input signal
+		vout == limit_low + slope*(vin - limit_low);
+	else		-- No limit exceeded, so pass input signal as is
+		vout == vin;
+	end use;
+	break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+--  Transfer Function:
+--
+--                  (s + w1)         
+--    H(s) =  k *  ----------
+--                  (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lead_lag_e is
+	generic (
+		k: real := 1.0;  			-- Gain multiplier
+		f1: real := 10.0;			-- First break frequency (zero)
+		f2: real := 100.0);		-- Second break frequency (pole)
+	port 	(	terminal input: electrical;
+			terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+	quantity vin_temp : real;
+	constant w1 : real := f1*math_2_pi;
+	constant w2 : real := f2*math_2_pi;
+	constant num : real_vector := (w1, 1.0);                                                    
+	constant den : real_vector := (w2, 1.0);
+begin
+	vin_temp == vin;
+	vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo is
+    port(
+        terminal servo_in : electrical;
+        terminal pos_fb : electrical;
+        terminal servo_out : electrical
+    );
+end rudder_servo;
+
+architecture rudder_servo of rudder_servo is
+    -- Component declarations
+    -- Signal declarations
+    terminal error : electrical;
+    terminal ll_in : electrical;
+    terminal ll_out : electrical;
+    terminal summer_fb : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    summer : entity work.sum2_e(simple)
+        port map(
+            in1 => servo_in,
+            in2 => summer_fb,
+            output => error
+        );
+    forward_gain : entity work.gain_e(simple)
+        generic map(
+            k => 100.0
+        )
+        port map(
+            input => error,
+            output => ll_in
+        );
+    fb_gain : entity work.gain_e(simple)
+        generic map(
+            k => -4.57
+        )
+        port map(
+            input => pos_fb,
+            output => summer_fb
+        );
+    servo_limiter : entity work.limiter_2_e(simple)
+     generic map(
+            limit_high => 4.8,
+            limit_low => -4.8
+        )
+        port map(
+            input => ll_out,
+            output => servo_out
+        );
+    lead_lag : entity work.lead_lag_e(simple)
+        generic map(
+            k => 400.0,
+            f1 => 5.0,
+            f2 => 2000.0
+        )
+        port map(
+            input => ll_in,
+            output => ll_out
+        );
+end rudder_servo;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : gear_rv_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/10/10  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+  generic(
+    ratio : real := 1.0);   -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+                            -- Note: can be negative, if shaft polarity changes
+
+  port ( terminal rotv1 : rotational_v;
+  		terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+  quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+--  quantity w2 across torq2 through rotv2 to rotational_v_ref;
+  quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+--  w2  == w1*ratio;
+  theta == ratio*w1'integ;
+  torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+  
+  generic (
+    k : real := 1.0);                -- optional gain
+
+  port (
+    terminal input   : rotational;  -- input terminal
+    terminal output    : electrical);   -- output terminal
+  
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref;     -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+  begin  -- bhv
+   v_out ==  k*rot_in; 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  tran =   R*sin(rot) 
+--
+-- Where pos = output translational position,
+-- R = horn radius, 
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+  
+  generic (
+    R   : real := 1.0);            		-- horn radius
+
+  port (
+    terminal theta    : ROTATIONAL;   	-- input angular position port
+    terminal pos   : TRANSLATIONAL);  	-- output translational position port
+     
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+  begin			-- bhv
+   tran == R*sin(rot);		-- Convert angle in to translational out
+   tran_frc == -rot_tq/R;	-- Convert torque in to force out 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  theta =   arcsin(pos/R) 
+--
+-- Where pos = input translational position,
+-- R = horn radius, 
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+  
+  generic (
+    R   : real := 1.0);            -- Rudder horn radius
+
+  port (
+    terminal pos    : translational;   -- input translational position port
+    terminal theta   : rotational);  -- output angular position port
+     
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+  begin  -- bhv
+   rot == arcsin(tran/R);	-- Convert translational to angle
+   rot_tq == -tran_frc*R;	-- Convert force to torque
+   
+end bhv;
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+      terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+  QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+  QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+   pos_2 == pos_1;		-- Pass position 
+   frc_2 == -frc_1;	-- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+--  Transfer Function:
+--                            
+--  torq =   -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+  
+  generic (
+    k   : real := 1.0;            -- Spring constant
+	theta_0 : real := 0.0);
+
+  port (
+    terminal rot    : rotational);   -- input rotational angle
+     
+end entity rudder;
+
+architecture bhv of rudder is
+
+  QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+  begin  -- bhv
+
+   torq == k*(theta - theta_0);	-- Convert force to torque
+   
+end bhv;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Constant Voltage Source (Includes Frequency Domain settings)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY v_constant IS
+
+-- Initialize parameters
+  GENERIC (
+    level      : VOLTAGE;		-- Constant voltage value (V)
+    ac_mag     : VOLTAGE := 1.0;	-- AC magnitude (V)
+    ac_phase   : real := 0.0);		-- AC phase (degrees)
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL pos, neg : ELECTRICAL);
+
+END ENTITY v_constant;
+
+-- Ideal Architecture (I = constant)
+ARCHITECTURE ideal OF v_constant IS
+  
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH pos TO neg;
+-- Declare quantity in frequency domain for AC analysis  
+  QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+
+  IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
+	v == level;
+  ELSE	
+  	v == ac_spec;  -- used for Frequency (AC) analysis
+  END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical sinusoidal voltage source (stick.vhd)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+
+ENTITY stick IS
+  
+-- Initialize parameters
+  GENERIC (
+    freq      : real;                     -- frequency,       [Hertz]
+    amplitude : real;                     -- amplitude,       [Volt]
+    phase     : real := 0.0;              -- initial phase,   [Degree]
+    offset    : real := 0.0;              -- DC value,        [Volt]
+    df        : real := 0.0;              -- damping factor,  [1/second]
+    ac_mag    : real := 1.0;              -- AC magnitude,    [Volt]
+    ac_phase  : real := 0.0);             -- AC phase,        [Degree]
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL v_out : ELECTRICAL);
+
+END ENTITY stick;
+
+-- Ideal Architecture
+ARCHITECTURE ideal OF stick IS
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
+-- Declare Quantity for Phase in radians (calculated below)
+  QUANTITY phase_rad : real;          
+-- Declare Quantity in frequency domain for AC analysis
+  QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN  
+-- Convert phase to radians
+  phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+  
+  IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
+    v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+  ELSE 
+    v == ac_spec;    -- used for Frequency (AC) analysis
+  END USE;
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity RF_xmtr_rcvr is
+generic (td : time := 0ns);
+port
+(
+      tdm_in : in std_logic ;
+      tdm_out : out std_logic 
+);
+
+end RF_xmtr_rcvr;
+
+architecture behavioral of RF_xmtr_rcvr is
+begin
+
+tdm_out <= tdm_in after td;
+
+end;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Simple Digital-Controlled Two-position Switch Model
+-- Switch position 1 ('0') or switch position 2 ('1')
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY switch_dig_2in is
+	GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
+		 	r_closed : RESISTANCE := 0.001; -- Closed switch resistance
+		 	trans_time : real := 0.00001); -- Transition time to each position
+
+	PORT (sw_state : in std_logic; -- Digital control input 
+    	      TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
+
+END ENTITY switch_dig_2in;
+
+
+ARCHITECTURE ideal OF switch_dig_2in IS
+
+--	CONSTANT log_r_open : real := log10(r_open);
+--	CONSTANT log_r_closed : real := log10(r_closed);
+--	SIGNAL r_sig1 : RESISTANCE := log_r_closed; -- Variable to accept switch resistance
+--	SIGNAL r_sig2 : RESISTANCE := log_r_open; -- Variable to accept switch resistance
+	SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
+	SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
+	QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
+	QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
+	QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
+	QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
+
+BEGIN
+ 
+ PROCESS (sw_state) -- Sensitivity to digital control input
+    BEGIN
+	  IF (sw_state'event AND sw_state = '0') THEN -- Close sig1, open sig2
+	    r_sig1 <= r_closed;
+	    r_sig2 <= r_open;
+	  ELSIF (sw_state'event AND sw_state = '1') THEN -- Open sig1, close sig2
+	    r_sig1 <= r_open;
+	    r_sig2 <= r_closed;
+	  END IF;
+    END PROCESS;
+
+	r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
+	r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
+	v1 == r1*i1; -- Apply Ohm's law to in1
+	v2 == r2*i2; -- Apply Ohm's law to in2
+
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Digital clock with 50% duty cycle
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock IS
+  GENERIC (
+    period : time);              -- Clock period
+  
+  PORT (
+    clk_out    : OUT std_logic);
+  
+END ENTITY clock;
+
+ARCHITECTURE ideal OF clock IS
+
+BEGIN
+
+-- clock process
+    process
+    begin
+        clk_out <= '0';
+        wait for period/2;
+        clk_out <= '1';
+        wait for period/2;
+    end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- This digital clock allows user to specify the duty cycle using
+-- the parameters "on_time" and "off_time"
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY clock_duty IS
+
+  GENERIC (
+    on_time : time := 20 us;
+	off_time : time := 19.98 ms
+ 	); 
+  
+  PORT (
+    clock_out    : OUT std_logic := '0');
+  
+END ENTITY clock_duty;
+
+ARCHITECTURE ideal OF clock_duty IS
+
+BEGIN
+
+-- clock process
+    process
+    begin
+        clock_out <= '1';
+        wait for on_time;
+        clock_out <= '0';
+        wait for off_time;
+    end process;
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rc_clk is
+    port(
+        clk_100k : out std_logic;
+        clk_6K : out std_logic;
+        clk_50 : out std_logic
+    );
+end rc_clk;
+
+architecture rc_clk of rc_clk is
+    -- Component declarations
+    -- Signal declarations
+begin
+    -- Signal assignments
+    -- Component instances
+    XCMP1 : entity work.clock(ideal)
+        generic map(
+            period => 10us
+        )
+        port map(
+            CLK_OUT => clk_100k
+        );
+    XCMP2 : entity work.clock(ideal)
+        generic map(
+            period => 150us
+        )
+        port map(
+            CLK_OUT => clk_6K
+        );
+    clk_50Hz : entity work.clock_duty(ideal)
+        generic map(
+            on_time => 20 us,
+            off_time => 19.98 ms
+        )
+        port map(
+            CLOCK_OUT => clk_50
+        );
+end rc_clk;
+--
+
+-- This model counts the number of input clock transitions and outputs
+-- a '1' when this number equals the value of the user-defined constant 'count'
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity bit_cnt is
+  generic (
+	count : integer -- User-defined value to count up to
+	);             
+port
+(
+      bit_in : in std_logic ;
+      clk : in std_logic ;
+      dly_out : out std_logic 
+);
+end bit_cnt;
+
+architecture behavioral of bit_cnt is
+begin
+	serial_clock : process is
+	begin
+		wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
+	  	FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
+	  		wait until clk'event AND (clk = '1' OR clk = 'H');
+     	END LOOP ;
+		dly_out <= '1'; -- After count is reached, set output high
+		wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
+		dly_out <= '0'; -- Reset output to '0' on next clock input
+	end process serial_clock;
+end;
+--
+
+--//////////////////////////////////////////////////////////////////
+-- NOTE: This is an intermediate file for HDL inspection only.
+--       Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach1.sdg.
+--       Generated by sde2hdl version 16.1.0.2
+--//////////////////////////////////////////////////////////////////
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+
+ENTITY state_mach1 IS
+    PORT (
+          a2d_eoc : IN std_logic;
+          clk_50 : IN std_logic;
+          clk_100k : IN std_logic;
+          clk_6k : IN std_logic;
+          ser_done : IN std_logic;
+          ch_sel : OUT std_logic;
+          frm_gen : OUT std_logic;
+          a2d_oe : OUT std_logic;
+          a2d_start : OUT std_logic;
+          p2s_oe : OUT std_logic;
+          p2s_load : OUT std_logic;
+          parity_oe : OUT std_logic;
+          ser_cnt : OUT std_logic;
+          p2s_clr : OUT std_logic);
+
+END state_mach1;
+
+ARCHITECTURE state_diagram OF state_mach1 IS
+
+    ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+    TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
+           , load, ad_ch2, delay);
+    SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
+
+    SIGNAL FB_frm_gen : std_logic;
+    SIGNAL FB_p2s_load : std_logic;
+    SIGNAL FB_ch_sel : std_logic;
+
+BEGIN 
+    frm_gen <= FB_frm_gen ;
+    p2s_load <= FB_p2s_load ;
+    ch_sel <= FB_ch_sel ;
+
+sm1: 
+  PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel) 
+  BEGIN
+
+    CASE CS_state_mach1_sm1 IS
+      WHEN V_begin =>
+        FB_frm_gen <= ('1');
+        a2d_start <= ('0');
+        a2d_oe <= ('0');
+        FB_p2s_load <= ('0');
+        p2s_clr <= ('0');
+        p2s_oe <= ('0');
+        FB_ch_sel <= ('0');
+        parity_oe <= ('0');
+        ser_cnt <= ('0');
+
+        IF ((FB_frm_gen = '1')) THEN
+          NS_state_mach1_sm1 <= frm_rd;
+        ELSE
+          NS_state_mach1_sm1 <= V_begin;
+        END IF;
+
+      WHEN frm_rd =>
+        FB_p2s_load <= ('1');
+
+        IF ((FB_p2s_load = '1')) THEN
+          NS_state_mach1_sm1 <= ser_oe;
+        ELSE
+          NS_state_mach1_sm1 <= frm_rd;
+        END IF;
+
+      WHEN ser_oe =>
+        p2s_oe <= ('1');
+        FB_frm_gen <= ('0');
+        FB_p2s_load <= ('0');
+        ser_cnt <= ('1');
+
+        IF ((ser_done = '1')) THEN
+          NS_state_mach1_sm1 <= ch1;
+        ELSE
+          NS_state_mach1_sm1 <= ser_oe;
+        END IF;
+
+      WHEN ch1 =>
+        p2s_oe <= ('0');
+        FB_ch_sel <= ('0');
+        a2d_start <= ('1');
+        ser_cnt <= ('0');
+
+        IF ((a2d_eoc = '1')) THEN
+          NS_state_mach1_sm1 <= data_en;
+        ELSE
+          NS_state_mach1_sm1 <= ch1;
+        END IF;
+
+      WHEN data_en =>
+        a2d_start <= ('0');
+        a2d_oe <= ('1');
+        parity_oe <= ('1');
+          NS_state_mach1_sm1 <= load;
+
+      WHEN tdm_oe =>
+        a2d_oe <= ('0');
+        parity_oe <= ('0');
+        p2s_oe <= ('1');
+        FB_p2s_load <= ('0');
+        ser_cnt <= ('1');
+
+        IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
+          NS_state_mach1_sm1 <= ch2;
+        ELSE
+          NS_state_mach1_sm1 <= tdm_oe;
+        END IF;
+
+      WHEN ch2 =>
+        p2s_oe <= ('0');
+        ser_cnt <= ('0');
+        FB_ch_sel <= ('1');
+          NS_state_mach1_sm1 <= delay;
+
+      WHEN load =>
+        FB_p2s_load <= ('1');
+          NS_state_mach1_sm1 <= tdm_oe;
+
+      WHEN ad_ch2 =>
+        a2d_start <= ('1');
+
+        IF ((a2d_eoc = '1')) THEN
+          NS_state_mach1_sm1 <= data_en;
+        ELSE
+          NS_state_mach1_sm1 <= ad_ch2;
+        END IF;
+
+      WHEN delay =>
+          NS_state_mach1_sm1 <= ad_ch2;
+
+    END CASE;
+
+  END PROCESS; 
+
+sm1_CTL:
+  PROCESS (clk_100k, clk_50)
+  BEGIN
+
+    IF (clk_100k'event AND clk_100k='1')  THEN 
+        IF (clk_50= '1' ) THEN 
+            CS_state_mach1_sm1 <= V_begin;
+        ELSE
+            CS_state_mach1_sm1 <= NS_state_mach1_sm1;
+        END IF;
+    END IF;
+
+  END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt is
+    port(
+        a2d_eoc : in std_logic;
+        clk_50 : in std_logic;
+        clk_100k : in std_logic;
+        clk_6k : in std_logic;
+        p2s_load : out std_logic;
+        p2s_oe : out std_logic;
+        parity_oe : out std_logic;
+        a2d_start : out std_logic;
+        a2d_oe : out std_logic;
+        frm_gen : out std_logic;
+        ch_sel : out std_logic;
+        p2s_clr : out std_logic
+    );
+end sm_cnt;
+
+architecture sm_cnt of sm_cnt is
+    -- Component declarations
+    -- Signal declarations
+    signal ser_done : std_logic;
+    signal serial_cnt : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    bit_cnt1 : entity work.bit_cnt(behavioral)
+        generic map(
+            count => 15
+        )
+        port map(
+            bit_in => serial_cnt,
+            clk => clk_6k,
+            dly_out => ser_done
+        );
+    state_mach16 : entity work.state_mach1
+        port map(
+            ser_cnt => serial_cnt,
+            ch_sel => ch_sel,
+            frm_gen => frm_gen,
+            a2d_oe => a2d_oe,
+            a2d_start => a2d_start,
+            parity_oe => parity_oe,
+            p2s_oe => p2s_oe,
+            p2s_load => p2s_load,
+            p2s_clr => p2s_clr,
+            clk_6k => clk_6k,
+            clk_100k => clk_100k,
+            clk_50 => clk_50,
+            a2d_eoc => a2d_eoc,
+            ser_done => ser_done
+        );
+end sm_cnt;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+--  Analog to Digital Converter (Successive Aproximation Register) model with sar architecture (a2d_nbit.vhd)
+--DESCRIPTION:
+--
+--This is a VHDL-AMS model of a simple analog to digital converter. The model
+--describes the general behavior of A/D converters for system level design and
+--verification.
+--The format of the digital output is binary coding.
+--
+--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
+--
+
+-- Use IEEE natures and packages
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity a2d_nbit is
+ generic (
+  Vmax: REAL := 5.0 ;   -- ADC's maximum range
+  Nbits: INTEGER := 10 ;  -- number bits in ADC's output
+  delay: TIME := 10 us    -- ADC's conversion time
+ );
+ 
+port (
+  signal start: in std_logic ; -- Start signal
+  signal clk: in std_logic ;   -- Strobe clock
+  signal oe: in std_logic ; -- Output enable
+  terminal ain: ELECTRICAL ;  -- ADC's analog input terminal
+  signal eoc: out std_logic := '0' ; -- End Of Conversion pin
+  signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
+end entity a2d_nbit;
+
+architecture sar of a2d_nbit is
+
+  type states is (input, convert, output) ; -- Three states of A2D Conversion
+  constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
+  quantity Vin across Iin through ain to electrical_ref;     -- ADC's input branch
+
+begin
+
+ sa_adc: process
+
+  variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
+  variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
+  variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
+  variable status: states := input ; -- Begin with "input" CASE 
+  variable bit_cnt: integer := Nbits -1 ;
+
+ begin
+ CASE status is
+	when input => -- Read input voltages when start goes high
+		wait on start until start = '1' or start = 'H' ;
+  		thresh := Vmax ;
+  		Vtmp := Vin ;
+		eoc <= '0' ;
+		status := convert ; -- Go to convert state
+	when convert => -- Begin successive approximation conversion
+			thresh := thresh / 2.0 ; -- Get value of MSB
+			wait on clk until clk = '1' OR clk = 'H';
+			if Vtmp > thresh then
+				dtmp(bit_cnt) := '1' ;
+				Vtmp := Vtmp - thresh ;
+			else
+				dtmp(bit_cnt) := '0' ;
+			end if ;
+			bit_cnt := bit_cnt - 1 ;
+			if (bit_cnt + 1) < 1 then
+				status := output ; -- Go to output state
+			end if;
+	when output => -- Wait for output enable, then put data on output pins
+		eoc <= '1' after delay ;
+		wait on oe until oe = '1' OR oe = 'H' ;
+			FOR i in bit_range DOWNTO 0 LOOP
+				dout(i) <= dtmp(i) ;
+			END LOOP ;
+		wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
+			FOR i in bit_range DOWNTO 0 LOOP
+				dout <= "ZZZZZZZZZZ" ;
+			END LOOP ;
+		bit_cnt := bit_range ;
+		status := input ; -- Set up for next conversion
+	END CASE ;
+ end process sa_adc ;
+
+ Iin == 0.0 ; -- Ideal input draws no current
+
+end architecture sar ;
+--
+
+-- Parallel input/serial output shift register
+-- With 4 trailing zeros
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity shift_reg is
+generic ( td : time := 0 ns); 
+
+port
+(
+      bus_in : in std_logic_vector ; -- Input bus
+      clk : in std_logic ; -- Shift clock
+      oe : in std_logic ; -- Output enable
+      ser_out : out std_logic := '0'; -- Output port
+      load : in std_logic ; -- Parallel input load
+	clr : in std_logic -- Clear register
+);
+
+end entity shift_reg;
+
+architecture behavioral of shift_reg is
+begin
+
+control_proc : process
+  VARIABLE bit_val : std_logic_vector(11 downto 0);  -- Default 12-bit input
+  begin
+
+	IF (clr = '1' OR clr = 'H') then
+    		bit_val := "000000000000"; -- Set all input bits to zero
+	ELSE
+  		wait until load'event AND (load = '1' OR load = 'H');
+		FOR i IN bus_in'high DOWNTO bus_in'low LOOP
+        		bit_val(i) := bus_in(i) ; -- Transfer input data to variable
+     		END LOOP ;
+	END IF;
+
+	wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
+	FOR i IN bit_val'high DOWNTO bit_val'low LOOP
+		wait until clk'event AND (clk = '1' OR clk = 'H');
+      	ser_out <= bit_val(i) ;
+	END LOOP ;
+
+	  FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros	
+		wait until clk'event AND (clk = '1' OR clk = 'H');
+		ser_out <= '0';
+	  END LOOP;
+
+END process;
+
+end architecture behavioral;
+--
+
+-- This model generates a 12-bit data frame synchronization code
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_gen is
+port
+(
+      oe : in std_logic := '0';
+	sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
+
+end entity frame_gen;
+
+architecture simple of frame_gen is
+begin
+	enbl: PROCESS
+  		BEGIN 
+  			WAIT ON OE;
+			IF OE = '1' THEN
+				sync_out <= "010101010101"; -- Sync code
+			ELSE
+				sync_out <= "ZZZZZZZZZZZZ";
+			END IF;
+  	END PROCESS;
+end architecture simple;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input XOR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY xor2 IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    in1, in2 : IN  std_logic;
+    output    : OUT std_logic);
+  
+END ENTITY xor2;
+
+ARCHITECTURE ideal OF xor2 IS
+BEGIN
+   output <= in1 XOR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- level_set_tri.vhd 
+-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
+-- If OE = '0' set output to high impedance
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set_tri IS
+
+  GENERIC (
+    logic_val : std_logic := 'Z');     
+
+  PORT (
+  	OE : IN std_logic;
+    level : OUT std_logic := 'Z');
+
+END ENTITY level_set_tri;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set_tri IS
+BEGIN
+  oe_ctl: PROCESS
+  BEGIN
+	WAIT ON OE;
+ 	IF OE = '1' THEN 
+   		level <= logic_val;
+	ELSE
+		level <= 'Z';
+	END IF;
+  END PROCESS;
+  
+END ARCHITECTURE ideal;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Simple Tri-state Buffer with delay time
+-- If OE = 1, output = input after delay
+-- If OE /= 1, output = Z after delay
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY buffer_tri IS
+  GENERIC (
+    delay : time := 0 ns);  -- Delay time
+  
+  PORT (
+    input : IN  std_logic;
+	OE : IN std_logic;
+    output : OUT std_logic);
+  
+END ENTITY buffer_tri;
+
+ARCHITECTURE ideal OF buffer_tri IS
+BEGIN
+  oe_ctl: PROCESS
+  BEGIN
+	WAIT ON OE, input;
+ 	IF OE = '1' THEN 
+   		output <= input AFTER delay;
+	ELSE
+		output <= 'Z' AFTER delay;
+	END IF;
+  END PROCESS;
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- ideal one bit D/A converter
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY d2a_bit IS
+  GENERIC (vlow : real :=0.0;           -- output high voltage
+           vhigh : real :=5.0);         -- output low voltage
+  PORT	  (D : IN std_logic;            -- digital (std_logic) intout
+           TERMINAL A : electrical);    -- analog (electrical) output
+END ENTITY d2a_bit;
+
+ARCHITECTURE ideal OF d2a_bit IS
+  QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
+  SIGNAL vin : real := 0.0;
+
+  BEGIN
+    vin <= vhigh WHEN D = '1' ELSE vlow;
+    -- Use 'RAMP for discontinuous signal
+    vout == vin'RAMP(1.0e-9);      
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_gen is
+    port(
+        parity : in std_logic_vector(1 to 10);
+        oe : in std_logic;
+        parity_out : out std_logic_vector(0 to 11)
+    );
+end parity_gen;
+
+architecture parity_gen of parity_gen is
+    -- Component declarations
+    -- Signal declarations
+    terminal par_bit_gen_a : electrical;
+    signal XSIG010002 : std_logic;
+    signal XSIG010003 : std_logic;
+    signal XSIG010004 : std_logic;
+    signal XSIG010005 : std_logic;
+    signal XSIG010006 : std_logic;
+    signal XSIG010007 : std_logic;
+    signal XSIG010008 : std_logic;
+    signal XSIG010009 : std_logic;
+    signal XSIG010098 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    XCMP1 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(1),
+            in2 => parity(2),
+            output => XSIG010002
+        );
+    XCMP2 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(3),
+            in2 => parity(4),
+            output => XSIG010003
+        );
+    XCMP3 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(5),
+            in2 => parity(6),
+            output => XSIG010004
+        );
+    XCMP4 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(7),
+            in2 => parity(8),
+            output => XSIG010005
+        );
+    XCMP5 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(9),
+            in2 => parity(10),
+            output => XSIG010008
+        );
+    XCMP6 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010002,
+            in2 => XSIG010003,
+            output => XSIG010006
+        );
+    XCMP7 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010004,
+            in2 => XSIG010005,
+            output => XSIG010007
+        );
+    XCMP8 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010006,
+            in2 => XSIG010007,
+            output => XSIG010009
+        );
+    XCMP9 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010009,
+            in2 => XSIG010008,
+            output => XSIG010098
+        );
+    XCMP18 : entity work.level_set_tri(ideal)
+        generic map(
+            logic_val => '1'
+        )
+        port map(
+            level => parity_out(11),
+            oe => oe
+        );
+    XCMP19 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(1),
+            output => parity_out(1),
+            oe => oe
+        );
+    XCMP20 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(2),
+            output => parity_out(2),
+            oe => oe
+        );
+    XCMP21 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(3),
+            output => parity_out(3),
+            oe => oe
+        );
+    XCMP22 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(4),
+            output => parity_out(4),
+            oe => oe
+        );
+    XCMP23 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(5),
+            output => parity_out(5),
+            oe => oe
+        );
+    XCMP24 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(6),
+            output => parity_out(6),
+            oe => oe
+        );
+    XCMP25 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(7),
+            output => parity_out(7),
+            oe => oe
+        );
+    XCMP26 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(8),
+            output => parity_out(8),
+            oe => oe
+        );
+    XCMP27 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(9),
+            output => parity_out(9),
+            oe => oe
+        );
+    XCMP28 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(10),
+            output => parity_out(10),
+            oe => oe
+        );
+    XCMP29 : entity work.buffer_tri(ideal)
+        port map(
+            input => XSIG010098,
+            output => parity_out(0),
+            oe => oe
+        );
+    XCMP30 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010098,
+            A => par_bit_gen_a
+        );
+end parity_gen;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tdm_encoder is
+    port(
+        clk : in std_logic;
+        p2s_oe : in std_logic;
+        p2s_load : in std_logic;
+        frm_gen : in std_logic;
+        parity_oe : in std_logic;
+        tdm_out : out std_logic;
+        p2s_clr : in std_logic;
+        a2d_data : in std_logic_vector(1 to 10)
+    );
+end tdm_encoder;
+
+architecture tdm_encoder of tdm_encoder is
+    -- Component declarations
+    -- Signal declarations
+    signal sync_par : std_logic_vector(0 to 11);
+begin
+    -- Signal assignments
+    -- Component instances
+    p2s1 : entity work.shift_reg(behavioral)
+        port map(
+            bus_in => sync_par,
+            clk => clk,
+            oe => p2s_oe,
+            ser_out => tdm_out,
+            load => p2s_load,
+            clr => p2s_clr
+        );
+    sync_gen1 : entity work.frame_gen(simple)
+        port map(
+            oe => frm_gen,
+            sync_out => sync_par
+        );
+    par_gen1 : entity work.parity_gen
+        port map(
+            parity => a2d_data,
+            parity_out => sync_par,
+            oe => parity_oe
+        );
+end tdm_encoder;
+--
+
+-- Manchester Encoder
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY menc_rsc IS
+	
+	port ( 	dig_in : in STD_LOGIC;  -- digital input
+		clk : in STD_LOGIC;     -- TX internal clock
+		reset: in STD_LOGIC;  -- not reset
+--	       	bit_out : inout real);  -- real output
+		bit_out : out std_logic);  -- real output
+	       
+END ENTITY menc_rsc;
+
+ARCHITECTURE bhv OF menc_rsc IS
+	 
+--	 signal bhigh:real:= 1.0;   -- bit encoding
+--	 signal blow:real:= -1.0;   -- bit encoding
+--	 signal bnormal:real:=0.0;  -- bit encoding
+	 signal bit1:STD_LOGIC;
+	 signal bhigh:std_logic:= '1';   -- bit encoding
+	 signal blow:std_logic:= '0';   -- bit encoding
+	 
+begin
+
+--	proc1: process  (dig_in, clk, bit1,bhigh,blow,bnormal) 
+	proc1: process  (dig_in, clk, bit1,bhigh,blow) 
+	begin
+	 	 	
+	if (reset = '1') then
+	   bit1 <= '0';
+	else
+	   bit1 <= dig_in XOR clk;  -- manchester encoding 
+	end if;
+	
+	if (bit1 = '1') then
+	   bit_out <= bhigh;
+	else 
+		bit_out <= blow;
+--	elsif bit1 = '0' then
+--	   bit_out <= blow;
+--	else
+--	   bit_out <= bnormal;
+	end if;
+	  
+	end process;
+	
+end architecture bhv;
+	
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Digitize_Encode_Man is
+    port(
+        tdm_out : out std_logic;
+        terminal ch1_in : electrical;
+        terminal ch2_in : electrical
+    );
+end Digitize_Encode_Man;
+
+architecture Digitize_Encode_Man of Digitize_Encode_Man is
+    -- Component declarations
+    -- Signal declarations
+    terminal a2d_ana_in : electrical;
+    signal ch_bus : std_logic_vector(1 to 10);
+    signal clk_6K : std_logic;
+    signal dig_in : std_logic;
+    signal frm_gen_ctl : std_logic;
+    signal p2s_clr : std_logic;
+    signal p2s_load : std_logic;
+    signal p2s_oe : std_logic;
+    signal par_oe : std_logic;
+    signal reset : std_logic;
+    signal reset_m : std_logic;
+    signal start_a2d1 : std_logic;
+    signal sw_ctl : std_logic;
+    signal XSIG010091 : std_logic;
+    signal XSIG010190 : std_logic;
+    signal XSIG010196 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    A_SWITCH1 : entity work.switch_dig_2in(ideal)
+        port map(
+            p_in1 => ch1_in,
+            p_out => a2d_ana_in,
+            sw_state => sw_ctl,
+            p_in2 => ch2_in
+        );
+    rc_clk2 : entity work.rc_clk
+        port map(
+            clk_50 => reset,
+            clk_6K => clk_6K,
+            clk_100k => XSIG010190
+        );
+    sm_xmtr1 : entity work.sm_cnt
+        port map(
+            clk_100k => XSIG010190,
+            a2d_start => start_a2d1,
+            a2d_eoc => XSIG010091,
+            p2s_oe => p2s_oe,
+            p2s_load => p2s_load,
+            ch_sel => sw_ctl,
+            frm_gen => frm_gen_ctl,
+            parity_oe => par_oe,
+            a2d_oe => XSIG010196,
+            clk_50 => reset,
+            clk_6k => clk_6K,
+            p2s_clr => p2s_clr
+        );
+    a2d1 : entity work.a2d_nbit(sar)
+        generic map(
+            Vmax => 4.8
+        )
+        port map(
+            dout => ch_bus,
+            ain => a2d_ana_in,
+            clk => XSIG010190,
+            start => start_a2d1,
+            eoc => XSIG010091,
+            oe => XSIG010196
+        );
+    tdm_enc1 : entity work.tdm_encoder
+        port map(
+            clk => clk_6K,
+            p2s_oe => p2s_oe,
+            tdm_out => dig_in,
+            p2s_load => p2s_load,
+            a2d_data => ch_bus,
+            frm_gen => frm_gen_ctl,
+            parity_oe => par_oe,
+            p2s_clr => p2s_clr
+        );
+    menc_rsc3 : entity work.menc_rsc(bhv)
+        port map(
+            dig_in => dig_in,
+            clk => clk_6K,
+            reset => reset_m,
+            bit_out => tdm_out
+        );
+    XCMP90 : entity work.clock_duty(ideal)
+        generic map(
+            off_time => 19.98 sec
+        )
+        port map(
+            CLOCK_OUT => reset_m
+        );
+end Digitize_Encode_Man;
+--
+
+-------------------------------------------------------------------------------
+-- Second Order Lowpass filter
+--
+--  Transfer Function:
+--
+--                    w1*w2         
+--   H(s) =  k * ----------------
+--               (s + w1)(s + w2)
+--
+-- DC Gain = k
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lpf_2_e is
+	generic (
+		k: real := 1.0;  			-- Gain multiplier
+		f1: real := 10.0;			-- First break frequency (pole)
+		f2: real := 100.0);			-- Second break frequency (pole)
+	port 	(	terminal input: electrical;
+			terminal output: electrical);
+end entity lpf_2_e;
+
+architecture simple of lpf_2_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+	quantity vin_temp : real;
+	constant w1 : real := f1*math_2_pi;
+	constant w2 : real := f2*math_2_pi;
+--	constant num : real := k;
+	constant num : real_vector := (0 => w1*w2*k);  -- 0=> is needed to give
+                                                   -- index when only a single
+                                                   -- element is used.
+	constant den : real_vector := (w1*w2, w1+w2, 1.0);
+begin
+	vin_temp == vin;   -- intermediate variable (vin) req'd for now
+	vout == vin_temp'ltf(num, den);
+end architecture simple;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input AND gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY and2 IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    in1, in2 : IN  std_logic;
+    output    : OUT std_logic);
+  
+END ENTITY and2;
+
+ARCHITECTURE ideal OF and2 IS
+BEGIN
+   output <= in1 AND in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- D Flip Flop with reset (negative edge triggered)
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY d_latch_n_edge_rst IS
+	GENERIC (
+		delay : time := 0 ns);  -- Delay time
+  
+	PORT (
+		data, clk 	: IN std_logic;
+		q 	: OUT std_logic := '0';
+		qn	: OUT std_logic := '1';
+		rst	: IN std_logic := '0');  -- reset 
+	   
+END ENTITY d_latch_n_edge_rst ;
+
+ARCHITECTURE behav OF d_latch_n_edge_rst IS
+BEGIN
+ 
+ data_in : PROCESS(clk, rst) IS  
+
+   BEGIN
+     IF clk = '0' AND clk'event AND rst /= '1' THEN
+	     q  <= data     	AFTER delay;
+         qn <= NOT data 	AFTER delay;
+     ELSIF rst = '1' THEN
+         q <= '0';
+         qn <= '1';
+     END IF;
+     
+   END PROCESS data_in;  -- End of process data_in
+
+END ARCHITECTURE behav;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity counter_12 is
+    port(
+        cnt : out std_logic_vector(0 to 11);
+        reset : in std_logic;
+        enable : in std_logic;
+        clk : in std_logic
+    );
+end counter_12;
+
+architecture counter_12 of counter_12 is
+    -- Component declarations
+    -- Signal declarations
+    signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
+    signal XSIG010078 : std_logic;
+    signal XSIG010081 : std_logic;
+    signal XSIG010083 : std_logic;
+    signal XSIG010085 : std_logic;
+    signal XSIG010087 : std_logic;
+    signal XSIG010101 : std_logic;
+    signal XSIG010102 : std_logic;
+    signal XSIG010103 : std_logic;
+    signal XSIG010104 : std_logic;
+    signal XSIG010115 : std_logic;
+    signal XSIG010116 : std_logic;
+    signal XSIG010117 : std_logic;
+    signal XSIG010132 : std_logic;
+begin
+    -- Signal assignments
+    cnt(0) <= cdb2vhdl_tmp_1(0);
+    cnt(1) <= cdb2vhdl_tmp_1(1);
+    cnt(2) <= cdb2vhdl_tmp_1(2);
+    cnt(3) <= cdb2vhdl_tmp_1(3);
+    cnt(4) <= cdb2vhdl_tmp_1(4);
+    cnt(5) <= cdb2vhdl_tmp_1(5);
+    cnt(6) <= cdb2vhdl_tmp_1(6);
+    cnt(7) <= cdb2vhdl_tmp_1(7);
+    cnt(8) <= cdb2vhdl_tmp_1(8);
+    cnt(9) <= cdb2vhdl_tmp_1(9);
+    cnt(10) <= cdb2vhdl_tmp_1(10);
+    cnt(11) <= cdb2vhdl_tmp_1(11);
+    -- Component instances
+    XCMP92 : entity work.and2(ideal)
+        port map(
+            in1 => clk,
+            in2 => enable,
+            output => XSIG010132
+        );
+    XCMP93 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => XSIG010132,
+            DATA => XSIG010078,
+            QN => XSIG010078,
+            Q => cdb2vhdl_tmp_1(0),
+            RST => reset
+        );
+    XCMP94 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(0),
+            DATA => XSIG010081,
+            QN => XSIG010081,
+            Q => cdb2vhdl_tmp_1(1),
+            RST => reset
+        );
+    XCMP95 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(1),
+            DATA => XSIG010083,
+            QN => XSIG010083,
+            Q => cdb2vhdl_tmp_1(2),
+            RST => reset
+        );
+    XCMP96 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(2),
+            DATA => XSIG010085,
+            QN => XSIG010085,
+            Q => cdb2vhdl_tmp_1(3),
+            RST => reset
+        );
+    XCMP97 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(3),
+            DATA => XSIG010087,
+            QN => XSIG010087,
+            Q => cdb2vhdl_tmp_1(4),
+            RST => reset
+        );
+    XCMP98 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(4),
+            DATA => XSIG010101,
+            QN => XSIG010101,
+            Q => cdb2vhdl_tmp_1(5),
+            RST => reset
+        );
+    XCMP99 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(5),
+            DATA => XSIG010102,
+            QN => XSIG010102,
+            Q => cdb2vhdl_tmp_1(6),
+            RST => reset
+        );
+    XCMP100 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(6),
+            DATA => XSIG010103,
+            QN => XSIG010103,
+            Q => cdb2vhdl_tmp_1(7),
+            RST => reset
+        );
+    XCMP101 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(7),
+            DATA => XSIG010104,
+            QN => XSIG010104,
+            Q => cdb2vhdl_tmp_1(8),
+            RST => reset
+        );
+    XCMP102 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(8),
+            DATA => XSIG010115,
+            QN => XSIG010115,
+            Q => cdb2vhdl_tmp_1(9),
+            RST => reset
+        );
+    XCMP103 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(9),
+            DATA => XSIG010116,
+            QN => XSIG010116,
+            Q => cdb2vhdl_tmp_1(10),
+            RST => reset
+        );
+    XCMP104 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(10),
+            DATA => XSIG010117,
+            QN => XSIG010117,
+            Q => cdb2vhdl_tmp_1(11),
+            RST => reset
+        );
+end counter_12;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- ideal one bit A/D converter
+
+LIBRARY IEEE;
+USE IEEE.math_real.ALL;
+USE IEEE.std_logic_1164.ALL;
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY a2d_bit IS
+  
+  GENERIC (
+    thres : real := 2.5);    -- Threshold to determine logic output
+
+  PORT (
+    TERMINAL a :     electrical;   -- analog input
+    SIGNAL   d : OUT std_logic);   -- digital (std_logic) output
+  
+END ENTITY a2d_bit;
+
+
+ARCHITECTURE ideal OF a2d_bit IS
+
+  QUANTITY vin ACROSS a;
+  
+  BEGIN  -- threshold
+-- Process needed to detect threshold crossing and assign output (d)
+    PROCESS (vin'ABOVE(thres)) IS
+      BEGIN  -- PROCESS
+      IF vin'ABOVE(thres) THEN
+         d <= '1';
+      ELSE
+         d <= '0';  
+      END IF;
+    END PROCESS;
+
+END ideal;
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Digital clock with 50% duty cycle and enable pin
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock_en IS
+  GENERIC (
+    pw : time);              -- Clock pulse width
+  
+  PORT (
+	enable : IN std_logic ;
+	clock_out : INOUT std_logic := '0');
+  
+END ENTITY clock_en;
+
+ARCHITECTURE ideal OF clock_en IS
+
+BEGIN
+
+-- clock process
+    process (clock_out, enable) is
+    begin
+   	if clock_out = '0' AND enable = '1' THEN
+        clock_out <= '1' after pw, '0' after 2*pw;
+	end if;
+    end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Inverter
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY inverter IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    input : IN  std_logic;
+    output : OUT std_logic);
+  
+END ENTITY inverter;
+
+ARCHITECTURE ideal OF inverter IS
+BEGIN
+   output <= NOT input AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input OR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY or2 IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    in1, in2 : IN  std_logic;
+    output    : OUT std_logic);
+  
+END ENTITY or2;
+
+ARCHITECTURE ideal OF or2 IS
+BEGIN
+   output <= in1 OR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY d2a_nbit IS
+
+  GENERIC (
+    vmax : real := 5.0;	-- High output
+    vmin : real := 0.0;	-- Low output
+    high_bit : integer := 9; -- High end of bit range for D/A
+	low_bit : integer := 0); -- Low end of bit range for D/A
+
+  PORT (
+    SIGNAL   bus_in : IN STD_LOGIC_VECTOR;  -- variable width vector input
+    SIGNAL latch : IN STD_LOGIC;
+    TERMINAL ana_out  :    electrical);      -- analog output
+
+END ENTITY d2a_nbit ;
+
+ARCHITECTURE behavioral OF d2a_nbit IS
+
+  SIGNAL   sout : real := 0.0;
+  QUANTITY vout across iout through ana_out TO electrical_ref;
+
+BEGIN  -- ARCHITECTURE behavioral
+
+  proc : PROCESS
+
+    VARIABLE v_sum  : real; -- Sum of voltage contribution from each bit
+    VARIABLE delt_v : real; -- Represents the voltage value of each bit
+
+  BEGIN
+	WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
+  	v_sum     := vmin;
+    	delt_v    := vmax - vmin;
+
+    FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
+      delt_v  := delt_v / 2.0;
+      IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
+        v_sum := v_sum + delt_v;
+      END IF;
+    END LOOP;
+
+    sout <= v_sum;
+  END PROCESS;
+
+  vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
+
+END ARCHITECTURE behavioral;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pw2ana is
+    port(
+        terminal ana_out : electrical;
+        terminal pw_in : electrical
+    );
+end pw2ana;
+
+architecture pw2ana of pw2ana is
+    -- Component declarations
+    -- Signal declarations
+    signal bus_servo : std_logic_vector(0 to 11);
+    signal XSIG010008 : std_logic;
+    signal XSIG010013 : std_logic;
+    signal XSIG010019 : std_logic;
+    signal XSIG010020 : std_logic;
+    signal XSIG010021 : std_logic;
+    signal XSIG010022 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    counter_rudder : entity work.counter_12
+        port map(
+            enable => XSIG010022,
+            cnt => bus_servo,
+            reset => XSIG010021,
+            clk => XSIG010008
+        );
+    XCMP3 : entity work.a2d_bit(ideal)
+        port map(
+            D => XSIG010022,
+            A => pw_in
+        );
+    clk_en_rudder : entity work.clock_en(ideal)
+        generic map(
+            pw => 500ns
+        )
+        port map(
+            CLOCK_OUT => XSIG010008,
+            enable => XSIG010022
+        );
+    XCMP5 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => XSIG010022,
+            output => XSIG010013
+        );
+    XCMP8 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => XSIG010020,
+            output => XSIG010021
+        );
+    XCMP9 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => XSIG010022,
+            output => XSIG010019
+        );
+    or_rudder : entity work.or2(ideal)
+        port map(
+            in1 => XSIG010022,
+            in2 => XSIG010019,
+            output => XSIG010020
+        );
+    XCMP11 : entity work.d2a_nbit(behavioral)
+        generic map(
+            vmax => 4.8,
+            high_bit => 9,
+            low_bit => 0
+        )
+        port map(
+            bus_in => bus_servo,
+            ana_out => ana_out,
+            latch => XSIG010013
+        );
+end pw2ana;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : DC_Motor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+  generic (
+    r_wind : resistance;                -- Motor winding resistance [Ohm]
+    kt     : real;                      -- Torque coefficient [N*m/Amp]
+    l      : inductance;                -- Winding inductance [Henrys]
+    d      : real;                      -- Damping coefficient [N*m/(rad/sec)]
+    j      : mmoment_i);                -- Moment of inertia [kg*meter**2]
+
+  port (terminal p1, p2 : electrical;
+        terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations:  V = Kt*W + I*Rwind + L*dI/dt
+--                   T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+  quantity v across i through p1 to p2;
+  quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+  torq == -1.0*kt*i + d*w + j*w'dot;
+  v  == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : stop_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+  generic (
+    k_stop    : real;
+--    ang_max   : angle;
+--    ang_min   : angle := 0.0;
+	ang_max   : real;
+    ang_min   : real := 0.0;
+    damp_stop : real  := 0.000000001
+    );
+
+  port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+  quantity velocity : velocity;
+  quantity ang across trq through ang1 to ang2;
+
+begin
+
+  velocity == ang'dot;
+
+  if ang'above(ang_max) use
+    trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+  elsif ang'above(ang_min) use
+    trq   == 0.0;
+  else
+    trq   == k_stop * (ang - ang_min) + (damp_stop * velocity);
+  end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-- 12-bit digital comparator model
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity dig_cmp is
+port
+(
+      eq : out std_logic := '0';
+	  in1 : in std_logic_vector (0 to 11);
+	  in2 : in std_logic_vector (0 to 11);
+	  latch_in1 : in std_logic := '0'; -- Currently unused
+	  latch_in2 : in std_logic := '0';
+	  cmp : in std_logic := '0';
+	  clk : in std_logic
+	  );
+
+end entity dig_cmp ;
+
+architecture simple of dig_cmp is
+
+begin
+
+	compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
+	variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
+  		BEGIN
+		if latch_in2 = '1' then -- in2 data is latched and stored
+			in2_hold := in2;
+		end if;
+		if cmp = '1' then
+			if in1 = in2_hold then -- latched in2 checked against current in1
+				eq <= '0';
+			else eq <= '1';
+			end if;
+		end if;
+  	END PROCESS;
+end architecture simple;
+
+--
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical Resistor Model
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY resistor IS 
+
+-- Initialize parameters
+  GENERIC (
+    res : RESISTANCE);                 -- resistance (no initial value)
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL p1, p2 : ELECTRICAL);
+
+END ENTITY resistor;
+
+-- Ideal Architecture (V = I*R)
+ARCHITECTURE ideal OF resistor IS
+  
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH p1 TO p2;
+
+BEGIN
+  
+-- Characteristic equations
+  v == i*res;                       
+
+END ARCHITECTURE ideal;
+
+--
+-- Set/reset flip flop
+-- When S goes high, Q is set high until reset
+-- When R goes high, Q is set low until set
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sr_ff is
+port
+(
+      S : in std_logic ;
+      R : in std_logic ;
+	Q : out std_logic 
+);
+
+end sr_ff ;
+
+architecture simple of sr_ff is
+begin
+
+ set_reset: PROCESS(S, R) IS  
+
+   BEGIN
+--	assert S='1' nand R='1' -- Warning if both inputs are high
+--		report "S and R are both active. Use with caution"
+--		severity warning;
+	if S'event AND S = '1' then
+		Q <= '1';
+	end if;
+	if R'event AND R = '1' then
+		Q <= '0';
+	end if;     
+   END PROCESS set_reset; 
+
+end;
+--
+
+--//////////////////////////////////////////////////////////////////
+-- NOTE: This is an intermediate file for HDL inspection only.
+--       Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach_rcvr.sdg.
+--       Generated by sde2hdl version 16.1.0.2
+--//////////////////////////////////////////////////////////////////
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+USE IEEE_proposed.fluidic_systems.all;
+USE IEEE_proposed.thermal_systems.all;
+USE IEEE_proposed.radiant_systems.all;
+ENTITY state_mach_rcvr IS
+    PORT (
+          clk_50 : IN std_logic;
+          clk_100k : IN std_logic;
+          ser_done : IN std_logic;
+          par_det : IN std_logic;
+          frm_det : IN std_logic;
+          clk_6k : IN std_logic;
+          start_pulse : IN std_logic;
+          dly_done : IN std_logic;
+          s2p_rst : OUT std_logic;
+          s2p_en : OUT std_logic;
+          cnt1_en : OUT std_logic;
+          cnt1_rst : OUT std_logic;
+          cmp1_ltch1 : OUT std_logic;
+          cmp1_ltch2 : OUT std_logic;
+          cnt2_en : OUT std_logic;
+          cnt2_rst : OUT std_logic;
+          cmp2_ltch1 : OUT std_logic;
+          cmp2_ltch2 : OUT std_logic;
+          da_latch : OUT std_logic;
+          ser_cnt : OUT std_logic;
+          dly_cnt : OUT std_logic;
+          par_oe : OUT std_logic);
+
+END state_mach_rcvr;
+
+ARCHITECTURE state_diagram OF state_mach_rcvr IS
+
+    ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+    TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
+           , s_bit, par1, par2);
+    SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
+
+
+BEGIN 
+
+sm1: 
+  PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det) 
+  BEGIN
+
+    CASE CS_state_mach_rcvr_sm1 IS
+      WHEN V_begin =>
+        cnt1_en <= ('0');
+        cnt1_rst <= ('1');
+        cmp1_ltch1 <= ('0');
+        cmp1_ltch2 <= ('0');
+        cnt2_en <= ('0');
+        cnt2_rst <= ('1');
+        cmp2_ltch1 <= ('0');
+        cmp2_ltch2 <= ('0');
+        s2p_en <= ('1');
+        s2p_rst <= ('0');
+        da_latch <= ('0');
+        ser_cnt <= ('0');
+        dly_cnt <= ('0');
+        par_oe <= ('0');
+
+        IF ((frm_det = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= s_bit;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= V_begin;
+        END IF;
+
+      WHEN cnt =>
+        ser_cnt <= ('1');
+        cnt1_rst <= ('0');
+        cnt2_rst <= ('0');
+
+        IF ((ser_done = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= par1;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= cnt;
+        END IF;
+
+      WHEN ch1 =>
+        cmp1_ltch2 <= ('1');
+        ser_cnt <= ('0');
+        dly_cnt <= ('1');
+
+        IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
+          NS_state_mach_rcvr_sm1 <= rst1;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= ch1;
+        END IF;
+
+      WHEN rst1 =>
+        cmp1_ltch2 <= ('0');
+        ser_cnt <= ('1');
+        dly_cnt <= ('0');
+        par_oe <= ('0');
+
+        IF ((ser_done = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= par2;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= rst1;
+        END IF;
+
+      WHEN ch2 =>
+        cmp2_ltch2 <= ('1');
+        ser_cnt <= ('0');
+        da_latch <= ('1');
+          NS_state_mach_rcvr_sm1 <= rst2;
+
+      WHEN rst2 =>
+        cmp2_ltch2 <= ('0');
+        s2p_en <= ('0');
+        par_oe <= ('0');
+        da_latch <= ('0');
+          NS_state_mach_rcvr_sm1 <= cnt_cmp;
+
+      WHEN cnt_cmp =>
+        cnt1_en <= ('1');
+        cmp1_ltch1 <= ('1');
+        cnt2_en <= ('1');
+        cmp2_ltch1 <= ('1');
+          NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+      WHEN rst_cnt =>
+        cnt1_en <= ('0');
+        cmp1_ltch1 <= ('0');
+        cnt2_en <= ('0');
+        cmp2_ltch1 <= ('0');
+          NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+      WHEN s_bit =>
+
+        IF ((start_pulse = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= cnt;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= s_bit;
+        END IF;
+
+      WHEN par1 =>
+        par_oe <= ('1');
+
+        IF ((par_det = '0')) THEN
+          NS_state_mach_rcvr_sm1 <= ch1;
+        ELSIF ((par_det = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= rst1;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= par1;
+        END IF;
+
+      WHEN par2 =>
+        par_oe <= ('1');
+
+        IF ((par_det = '0')) THEN
+          NS_state_mach_rcvr_sm1 <= ch2;
+        ELSIF ((par_det = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= rst2;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= par2;
+        END IF;
+
+    END CASE;
+
+  END PROCESS; 
+
+sm1_CTL:
+  PROCESS (clk_100k, clk_50)
+  BEGIN
+
+    IF (clk_100k'event AND clk_100k='1')  THEN 
+        IF (clk_50= '1' ) THEN 
+            CS_state_mach_rcvr_sm1 <= V_begin;
+        ELSE
+            CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
+        END IF;
+    END IF;
+
+  END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt_rcvr is
+    port(
+        cmp1_ltch1 : out std_logic;
+        cmp2_ltch1 : out std_logic;
+        s2p_en : out std_logic;
+        s2p_rst : out std_logic;
+        frm_det : in std_logic;
+        par_det : in std_logic;
+        clk_100k : in std_logic;
+        clk_6k : in std_logic;
+        clk_50 : in std_logic;
+        start_pulse : in std_logic;
+        cnt1_en : out std_logic;
+        cnt1_rst : out std_logic;
+        cmp1_ltch2 : out std_logic;
+        cnt2_en : out std_logic;
+        cnt2_rst : out std_logic;
+        cmp2_ltch2 : out std_logic;
+        da_latch : out std_logic;
+        par_oe : out std_logic
+    );
+end sm_cnt_rcvr;
+
+architecture sm_cnt_rcvr of sm_cnt_rcvr is
+    -- Component declarations
+    -- Signal declarations
+    terminal dly_cnt_a : electrical;
+    terminal dly_done_a : electrical;
+    terminal ser_cnt_a : electrical;
+    terminal ser_done_a : electrical;
+    signal XSIG010001 : std_logic;
+    signal XSIG010002 : std_logic;
+    signal XSIG010145 : std_logic;
+    signal XSIG010146 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    XCMP1 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010001,
+            A => ser_cnt_a
+        );
+    XCMP2 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010002,
+            A => ser_done_a
+        );
+    bit_cnt3 : entity work.bit_cnt(behavioral)
+        generic map(
+            count => 2
+        )
+        port map(
+            bit_in => XSIG010145,
+            clk => clk_6k,
+            dly_out => XSIG010146
+        );
+    bit_cnt4 : entity work.bit_cnt(behavioral)
+        generic map(
+            count => 10
+        )
+        port map(
+            bit_in => XSIG010001,
+            clk => clk_6k,
+            dly_out => XSIG010002
+        );
+    XCMP8 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010145,
+            A => dly_cnt_a
+        );
+    XCMP9 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010146,
+            A => dly_done_a
+        );
+    state_mach_rcvr8 : entity work.state_mach_rcvr
+        port map(
+            clk_100k => clk_100k,
+            clk_50 => clk_50,
+            s2p_rst => s2p_rst,
+            s2p_en => s2p_en,
+            cnt1_en => cnt1_en,
+            cnt1_rst => cnt1_rst,
+            cmp1_ltch1 => cmp1_ltch1,
+            cmp1_ltch2 => cmp1_ltch2,
+            cnt2_en => cnt2_en,
+            cnt2_rst => cnt2_rst,
+            cmp2_ltch1 => cmp2_ltch1,
+            cmp2_ltch2 => cmp2_ltch2,
+            da_latch => da_latch,
+            ser_cnt => XSIG010001,
+            ser_done => XSIG010002,
+            par_det => par_det,
+            frm_det => frm_det,
+            clk_6k => clk_6k,
+            start_pulse => start_pulse,
+            dly_done => XSIG010146,
+            dly_cnt => XSIG010145,
+            par_oe => par_oe
+        );
+end sm_cnt_rcvr;
+--
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- level_set.vhd 
+-- Set digital output "level" with parameter "logic_val" (default is '1')
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set IS
+
+  GENERIC (
+    logic_val : std_logic := '1');     
+
+  PORT (
+    level : OUT std_logic);
+
+END ENTITY level_set;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set IS
+
+BEGIN
+
+  level <= logic_val;
+  
+END ARCHITECTURE ideal;
+
+--
+
+-- Serial to parallel data converter
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity ser2par is
+port
+(
+      par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
+      clk : in std_logic ;
+      load_en : in std_logic ;
+      ser_in : in std_logic ;
+      reset : in std_logic 
+);
+
+begin
+
+end ser2par;
+
+architecture a1 of ser2par is
+BEGIN 
+	sr_sm: PROCESS (load_en, clk, reset, ser_in)	
+	BEGIN
+		if (reset = '1' and load_en = '1') then
+			par_out <= "000000000000";  -- Reset the parallel data out
+			
+		elsif (clk'event and clk = '1') then
+			if (load_en ='1') then 
+				
+				-- The register will shift when load is enabled 
+				-- and will shift at rising edge of clock
+				
+				par_out(0) <= ser_in; -- Input data shifts into bit 0
+				par_out(1) <= par_out(0);
+				par_out(2) <= par_out(1);
+				par_out(3) <= par_out(2);
+				par_out(4) <= par_out(3);
+				par_out(5) <= par_out(4);
+				par_out(6) <= par_out(5);
+				par_out(7) <= par_out(6);
+				par_out(8) <= par_out(7);
+				par_out(9) <= par_out(8);
+				par_out(10) <= par_out(9);
+				par_out(11) <= par_out(10); 
+
+			else
+			      -- The otput data will not change 
+				-- if load_en is not enabled		
+		         	par_out <= "ZZZZZZZZZZZZ";			
+ 			end if;
+		end if;			
+	END PROCESS;
+end;
+--
+
+-- This model ouputs a '1' when a specific bit pattern is encountered
+-- Otherwise, it outputs a zero
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_det is
+port
+(
+	  bus_in : in std_logic_vector (0 to 11);
+	  clk : in std_logic;
+	  frm_bit : out std_logic := '0' -- Initialize output to zero
+	  );
+
+end entity frame_det;
+
+architecture simple of frame_det is
+begin
+	enbl: PROCESS (bus_in, clk) -- Sensitivity list
+  		BEGIN 
+		if bus_in = "010101010101" then -- This is the pre-defined bit pattern
+			if clk'event AND clk = '0' then -- Output updated synchronously
+				frm_bit <= '1';
+			end if;
+		else frm_bit <= '0';
+		end if;
+  	END PROCESS;
+end architecture simple;
+
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_det is
+    port(
+        bus_in : in std_logic_vector(0 to 11);
+        par_bit : out std_logic;
+        oe : in std_logic
+    );
+end parity_det;
+
+architecture parity_det of parity_det is
+    -- Component declarations
+    -- Signal declarations
+    signal cdb2vhdl_tmp_1 : std_logic;
+    terminal par_bit_a : electrical;
+    signal XSIG010010 : std_logic;
+    signal XSIG010011 : std_logic;
+    signal XSIG010012 : std_logic;
+    signal XSIG010013 : std_logic;
+    signal XSIG010014 : std_logic;
+    signal XSIG010015 : std_logic;
+    signal XSIG010016 : std_logic;
+    signal XSIG010017 : std_logic;
+    signal XSIG010019 : std_logic;
+    signal XSIG010057 : std_logic;
+begin
+    -- Signal assignments
+    par_bit <= cdb2vhdl_tmp_1;
+    -- Component instances
+    XCMP1 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(1),
+            in2 => bus_in(2),
+            output => XSIG010010
+        );
+    XCMP2 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(3),
+            in2 => bus_in(4),
+            output => XSIG010011
+        );
+    XCMP3 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(5),
+            in2 => bus_in(6),
+            output => XSIG010012
+        );
+    XCMP4 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(7),
+            in2 => bus_in(8),
+            output => XSIG010013
+        );
+    XCMP5 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(9),
+            in2 => bus_in(10),
+            output => XSIG010016
+        );
+    XCMP6 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010010,
+            in2 => XSIG010011,
+            output => XSIG010014
+        );
+    XCMP7 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010012,
+            in2 => XSIG010013,
+            output => XSIG010015
+        );
+    XCMP8 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010014,
+            in2 => XSIG010015,
+            output => XSIG010017
+        );
+    XCMP9 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010017,
+            in2 => XSIG010016,
+            output => XSIG010019
+        );
+    XCMP10 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010019,
+            in2 => bus_in(0),
+            output => XSIG010057
+        );
+    XCMP11 : entity work.d2a_bit(ideal)
+        port map(
+            D => cdb2vhdl_tmp_1,
+            A => par_bit_a
+        );
+    XCMP12 : entity work.and2(ideal)
+        port map(
+            in1 => oe,
+            in2 => XSIG010057,
+            output => cdb2vhdl_tmp_1
+        );
+end parity_det;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TDM_Demux_dbg is
+    port(
+        s2p_en : in std_logic;
+        tdm_in : in std_logic;
+        clk_6k : in std_logic;
+        s2p_rst : in std_logic;
+        par_det : out std_logic;
+        frm_det : out std_logic;
+        da_latch : in std_logic;
+        par_oe : in std_logic;
+        data_bus : out std_logic_vector(1 to 10);
+        start_bit : out std_logic
+    );
+end TDM_Demux_dbg;
+
+architecture TDM_Demux_dbg of TDM_Demux_dbg is
+    -- Component declarations
+    -- Signal declarations
+    terminal d2a_out : electrical;
+    signal rcvr_bus : std_logic_vector(0 to 11);
+begin
+    -- Signal assignments
+    data_bus(1) <= rcvr_bus(1);
+    data_bus(2) <= rcvr_bus(2);
+    data_bus(3) <= rcvr_bus(3);
+    data_bus(4) <= rcvr_bus(4);
+    data_bus(5) <= rcvr_bus(5);
+    data_bus(6) <= rcvr_bus(6);
+    data_bus(7) <= rcvr_bus(7);
+    data_bus(8) <= rcvr_bus(8);
+    data_bus(9) <= rcvr_bus(9);
+    data_bus(10) <= rcvr_bus(10);
+    start_bit <= rcvr_bus(0);
+    -- Component instances
+    s2p1 : entity work.ser2par(a1)
+        port map(
+            par_out => rcvr_bus,
+            clk => clk_6k,
+            load_en => s2p_en,
+            ser_in => tdm_in,
+            reset => s2p_rst
+        );
+    frm_det1 : entity work.frame_det(simple)
+        port map(
+            bus_in => rcvr_bus,
+            frm_bit => frm_det,
+            clk => clk_6k
+        );
+    par_det1 : entity work.parity_det
+        port map(
+            bus_in => rcvr_bus,
+            par_bit => par_det,
+            oe => par_oe
+        );
+    XCMP113 : entity work.d2a_nbit(behavioral)
+        generic map(
+            low_bit => 1,
+            high_bit => 10,
+            vmax => 4.8
+        )
+        port map(
+            bus_in => rcvr_bus(1 to 10),
+            ana_out => d2a_out,
+            latch => da_latch
+        );
+end TDM_Demux_dbg;
+--
+
+-- Manchester Decoder with clock recovery using 8x referenced clock
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity mdec_rsc is
+--	port (	din: in real;                -- real input
+	port (	din: in std_logic;           -- real input
+		clk16x: in std_logic;	     -- 16x referenced clock
+		reset: in std_logic;       -- not reset
+		bout: out std_logic := '0';         -- digital output
+		clk_out: inout std_logic := '0');   -- recovered clock
+end entity mdec_rsc;
+
+architecture bhv of mdec_rsc is
+--	signal bhigh:real:= 1.0;   	      -- bit decoding 
+--	signal blow:real:= -1.0;	      -- bit decoding
+--	signal bnormal:real:=0.0;      	      -- bit decoding
+	signal bhigh:std_logic:= '1';   	      -- bit decoding 
+	signal blow:std_logic:= '0';	      -- bit decoding
+	signal bout1:std_logic;
+	signal clk_div:std_logic_vector(3 downto 0):="0000";  -- clock counter
+	signal trans:std_logic;              -- transisition trigger
+begin
+	-- bit decoding
+	proc1: process (reset,din,clk16x)
+	begin
+	if (reset = '1') then
+	   bout1 <= 'X';
+	elsif (clk16x'event and clk16x = '1') then
+	   if (din = bhigh) then
+	      bout1 <= '1';
+	   elsif (din = blow) then
+	      bout1 <= '0';
+	   else
+	      bout1 <= 'X';
+	   end if;
+	end if;
+	end process;
+		
+	-- clock counter
+	proc2: process (reset, clk16x, clk_div)
+	begin
+	
+	if (reset = '1') then
+	   clk_div <= "0000";
+	elsif (clk16x'event and clk16x = '1') then
+	   clk_div <= clk_div + "0001";
+	end if;
+	end process;
+	
+	-- recovered clock
+	-- clk_out <= not clk_div(3);  
+	clk_out <= clk_div(3);  
+	
+	-- transition trigger
+trans <= ((not clk_div(3)) and (not clk_div(2)) and clk_div(1) and clk_div(0)) or 
+	          (clk_div(3) and clk_div(2) and (not clk_div(1)) and (not clk_div(0)));
+
+	-- Manchester decoder
+	proc3: process (reset, trans, bout1, clk_out, clk16x)
+	begin
+	if (reset = '1') then
+	   bout <= '0';
+	elsif (clk16x'event and clk16x = '1') then
+	   if  (trans = '1') then
+	      bout <= bout1 XOR clk_out;
+	   end if;
+	end if;
+	end process;
+	     
+end architecture bhv;	
+
+architecture bhv_8 of mdec_rsc is
+--	signal bhigh:real:= 1.0;   	      -- bit decoding 
+--	signal blow:real:= -1.0;	      -- bit decoding
+--	signal bnormal:real:=0.0;      	      -- bit decoding
+	signal bhigh:std_logic:= '1';   	      -- bit decoding 
+	signal blow:std_logic:= '0';	      -- bit decoding
+	signal bout1:std_logic;
+	signal clk_div:std_logic_vector(2 downto 0):="000";  -- clock counter
+	signal trans:std_logic;              -- transisition trigger
+begin
+	-- bit decoding
+	proc1: process (reset,din,clk16x)
+	begin
+	if (reset = '1') then
+	   bout1 <= 'X';
+	elsif (clk16x'event and clk16x = '1') then
+	   if (din = bhigh) then
+	      bout1 <= '1';
+	   elsif (din = blow) then
+	      bout1 <= '0';
+	   else
+	      bout1 <= 'X';
+	   end if;
+	end if;
+	end process;
+		
+	-- clock counter
+	proc2: process (reset, clk16x, clk_div)
+	begin
+	
+	if (reset = '1') then
+	   clk_div <= "000";
+	elsif (clk16x'event and clk16x = '1') then
+	   clk_div <= clk_div + "001";
+	end if;
+	end process;
+	
+	-- recovered clock
+	clk_out <= not clk_div(2);  
+	
+	-- transition trigger
+	trans <= ((not clk_div(1)) and clk_div(0)) or (clk_div(1) and (not clk_div(0)));
+
+	-- Manchester decoder
+	proc3: process (reset, trans, bout1, clk_out, clk16x)
+	begin
+	if (reset = '1') then
+	   bout <= '0';
+	elsif (clk16x'event and clk16x = '1') then
+	   if  (trans = '1') then
+	      bout <= bout1 XOR clk_out;
+	   end if;
+	end if;
+	end process;
+	     
+end architecture bhv_8;	
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Decode_PW_Man is
+    port(
+        terminal power : electrical;
+        terminal ch1_pw : electrical;
+        terminal ch2_pw : electrical;
+        bit_stream_in : in std_logic
+    );
+end Decode_PW_Man;
+
+architecture Decode_PW_Man of Decode_PW_Man is
+    -- Component declarations
+    -- Signal declarations
+    signal bit_stream_in_mdec : std_logic;
+    signal clk16x : std_logic;
+    signal clk6k : std_logic;
+    signal clk_100k : std_logic;
+    signal cmp_bus : std_logic_vector(0 to 11);
+    signal cnt1 : std_logic_vector(0 to 11);
+    signal cnt2 : std_logic_vector(0 to 11);
+    signal mdec_clk : std_logic;
+    signal mdec_out : std_logic;
+    signal reset : std_logic;
+    signal reset_m : std_logic;
+    signal XSIG010228 : std_logic;
+    signal XSIG010229 : std_logic;
+    signal XSIG010256 : std_logic;
+    signal XSIG010263 : std_logic;
+    signal XSIG010264 : std_logic;
+    signal XSIG010266 : std_logic;
+    signal XSIG010267 : std_logic;
+    signal XSIG010268 : std_logic;
+    signal XSIG010320 : std_logic;
+    signal XSIG010330 : std_logic;
+    signal XSIG010334 : std_logic;
+    signal XSIG010339 : std_logic;
+    signal XSIG010349 : std_logic;
+    signal XSIG010357 : std_logic;
+    signal XSIG010371 : std_logic;
+    signal XSIG010372 : std_logic;
+    signal XSIG010373 : std_logic;
+    signal XSIG010383 : std_logic;
+    signal XSIG010384 : std_logic;
+    signal XSIG010385 : std_logic;
+    signal XSIG010386 : std_logic;
+    signal XSIG010390 : std_logic;
+    signal XSIG010433 : std_logic;
+begin
+    -- Signal assignments
+    bit_stream_in_mdec <= bit_stream_in;
+    -- Component instances
+    cntr1 : entity work.counter_12
+        port map(
+            enable => XSIG010384,
+            cnt => cnt1,
+            reset => XSIG010357,
+            clk => XSIG010433
+        );
+    cntr2 : entity work.counter_12
+        port map(
+            enable => XSIG010349,
+            cnt => cnt2,
+            reset => XSIG010385,
+            clk => XSIG010320
+        );
+    cmp1 : entity work.dig_cmp(simple)
+        port map(
+            in1 => cnt1,
+            eq => XSIG010371,
+            clk => XSIG010433,
+            in2 => cmp_bus,
+            cmp => XSIG010384,
+            latch_in1 => XSIG010256,
+            latch_in2 => XSIG010383
+        );
+    cmp2 : entity work.dig_cmp(simple)
+        port map(
+            in1 => cnt2,
+            eq => XSIG010372,
+            clk => XSIG010320,
+            in2 => cmp_bus,
+            cmp => XSIG010349,
+            latch_in1 => XSIG010263,
+            latch_in2 => XSIG010264
+        );
+    XCMP109 : entity work.resistor(ideal)
+        generic map(
+            res => 1000000.0
+        )
+        port map(
+            p1 => power,
+            p2 => ELECTRICAL_REF
+        );
+    clk_1M2 : entity work.clock_en(ideal)
+        generic map(
+            pw => 500 ns
+        )
+        port map(
+            CLOCK_OUT => XSIG010320,
+            enable => XSIG010349
+        );
+    clk_1M1 : entity work.clock_en(ideal)
+        generic map(
+            pw => 500 ns
+        )
+        port map(
+            CLOCK_OUT => XSIG010433,
+            enable => XSIG010384
+        );
+    XCMP134 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010371,
+            A => ch1_pw
+        );
+    XCMP135 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010372,
+            A => ch2_pw
+        );
+    XCMP137 : entity work.SR_FF(simple)
+        port map(
+            S => XSIG010330,
+            R => XSIG010334,
+            Q => XSIG010349
+        );
+    XCMP138 : entity work.inverter(ideal)
+        port map(
+            input => XSIG010372,
+            output => XSIG010334
+        );
+    XCMP139 : entity work.SR_FF(simple)
+        port map(
+            S => XSIG010373,
+            R => XSIG010339,
+            Q => XSIG010384
+        );
+    XCMP140 : entity work.inverter(ideal)
+        port map(
+            input => XSIG010371,
+            output => XSIG010339
+        );
+    rc_clk2 : entity work.rc_clk
+        port map(
+            clk_50 => reset,
+            clk_6K => clk6k,
+            clk_100k => clk_100k
+        );
+    sm_rcvr1 : entity work.sm_cnt_rcvr
+        port map(
+            cnt1_en => XSIG010373,
+            cmp1_ltch1 => XSIG010256,
+            cnt2_rst => XSIG010385,
+            clk_100k => clk_100k,
+            cnt1_rst => XSIG010357,
+            cnt2_en => XSIG010330,
+            cmp2_ltch1 => XSIG010263,
+            frm_det => XSIG010229,
+            par_det => XSIG010228,
+            s2p_en => XSIG010266,
+            s2p_rst => XSIG010267,
+            clk_6k => mdec_clk,
+            clk_50 => reset,
+            da_latch => XSIG010268,
+            cmp1_ltch2 => XSIG010383,
+            cmp2_ltch2 => XSIG010264,
+            start_pulse => XSIG010390,
+            par_oe => XSIG010386
+        );
+    XCMP155 : entity work.level_set(ideal)
+        generic map(
+            logic_val => '0'
+        )
+        port map(
+            level => cmp_bus(11)
+        );
+    XCMP157 : entity work.TDM_Demux_dbg
+        port map(
+            data_bus => cmp_bus(0 to 9),
+            tdm_in => mdec_out,
+            clk_6k => mdec_clk,
+            s2p_en => XSIG010266,
+            s2p_rst => XSIG010267,
+            da_latch => XSIG010268,
+            frm_det => XSIG010229,
+            par_det => XSIG010228,
+            par_oe => XSIG010386,
+            start_bit => XSIG010390
+        );
+    XCMP172 : entity work.level_set(ideal)
+        generic map(
+            logic_val => '1'
+        )
+        port map(
+            level => cmp_bus(10)
+        );
+    clock1 : entity work.clock(ideal)
+        generic map(
+            period => 9.375us
+        )
+        port map(
+            CLK_OUT => clk16x
+        );
+    mdec_rsc7 : entity work.mdec_rsc(bhv)
+        port map(
+            din => bit_stream_in_mdec,
+            clk16x => clk16x,
+            reset => reset_m,
+            bout => mdec_out,
+            clk_out => mdec_clk
+        );
+    XCMP181 : entity work.clock_duty(ideal)
+        generic map(
+            off_time => 19.98 sec
+        )
+        port map(
+            CLOCK_OUT => reset_m
+        );
+end Decode_PW_Man;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CS5_CC_Rudder is
+end tb_CS5_CC_Rudder;
+
+architecture TB_CS5_CC_Rudder of tb_CS5_CC_Rudder is
+    -- Component declarations
+    -- Signal declarations
+    terminal gear_out : rotational;
+    terminal link_in : translational;
+    terminal link_out : translational;
+    terminal pot_fb : electrical;
+    signal rf_in : std_logic;
+    signal rf_out : std_logic;
+    terminal rudder : rotational;
+    terminal rudder_ana : electrical;
+    terminal rudder_cmd : electrical;
+    terminal rudder_mtr_in : electrical;
+    terminal rudder_mtr_out : rotational_v;
+    terminal rudder_pw : electrical;
+    terminal rudder_servo_in : electrical;
+    terminal throttle_ana : electrical;
+    terminal throttle_cmd : electrical;
+    terminal throttle_pw : electrical;
+    terminal XSIG010013 : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    rudder_servo1 : entity work.rudder_servo
+        port map(
+            servo_out => rudder_mtr_in,
+            servo_in => rudder_servo_in,
+            pos_fb => pot_fb
+        );
+    gear1 : entity work.gear_rv_r(ideal)
+        generic map(
+            ratio => 0.01
+        )
+        port map(
+            rotv1 => rudder_mtr_out,
+            rot2 => gear_out
+        );
+    potentiometer : entity work.rot2v(bhv)
+        generic map(
+            k => 1.0
+        )
+        port map(
+            output => pot_fb,
+            input => gear_out
+        );
+    g_horn : entity work.horn_r2t(bhv)
+        port map(
+            theta => gear_out,
+            pos => link_in
+        );
+    r_horn : entity work.horn_t2r(bhv)
+        port map(
+            theta => rudder,
+            pos => link_out
+        );
+    \linkage\ : entity work.tran_linkage(a1)
+        port map(
+            p2 => link_out,
+            p1 => link_in
+        );
+    rudder_1 : entity work.rudder(bhv)
+        generic map(
+            k => 0.2
+        )
+        port map(
+            rot => rudder
+        );
+    XCMP6 : entity work.v_constant(ideal)
+        generic map(
+            level => 5.0
+        )
+        port map(
+            pos => XSIG010013,
+            neg => ELECTRICAL_REF
+        );
+    t_stick : entity work.stick(ideal)
+        generic map(
+            offset => 2.397,
+            phase => 0.0,
+            amplitude => 2.397,
+            freq => 1.0
+        )
+        port map(
+            v_out => throttle_cmd
+        );
+    r_stick : entity work.stick(ideal)
+        generic map(
+            freq => 1.0,
+            amplitude => 2.397,
+            phase => 270.0,
+            offset => 2.397
+        )
+        port map(
+            v_out => rudder_cmd
+        );
+    RF : entity work.rf_xmtr_rcvr(behavioral)
+        port map(
+            tdm_in => rf_in,
+            tdm_out => rf_out
+        );
+    Digitize_Encode1 : entity work.Digitize_Encode_Man
+        port map(
+            ch2_in => rudder_cmd,
+            ch1_in => throttle_cmd,
+            tdm_out => rf_in
+        );
+    filter : entity work.lpf_2_e(simple)
+        generic map(
+            f2 => 10.0,
+            f1 => 10.0
+        )
+        port map(
+            input => rudder_ana,
+            output => rudder_servo_in
+        );
+    t_pw2ana : entity work.pw2ana
+        port map(
+            ana_out => throttle_ana,
+            pw_in => throttle_pw
+        );
+    r_pw2ana : entity work.pw2ana
+        port map(
+            ana_out => rudder_ana,
+            pw_in => rudder_pw
+        );
+    motor2 : entity work.DC_Motor(basic)
+        generic map(
+            r_wind => 2.2,
+            kt => 3.43e-3,
+            l => 2.03e-3,
+            d => 5.63e-6,
+            j => 168.0e-9
+        )
+        port map(
+            p1 => rudder_mtr_in,
+            p2 => ELECTRICAL_REF,
+            shaft_rotv => rudder_mtr_out
+        );
+    stop3 : entity work.stop_r(ideal)
+        generic map(
+            k_stop => 1.0e6,
+            ang_max => 1.05,
+            ang_min => -1.05,
+            damp_stop => 1.0e2
+        )
+        port map(
+            ang1 => gear_out,
+            ang2 => ROTATIONAL_REF
+        );
+    Decode_PW_Man2 : entity work.Decode_PW_Man
+        port map(
+            bit_stream_in => rf_out,
+            ch2_pw => rudder_pw,
+            ch1_pw => throttle_pw,
+            power => XSIG010013
+        );
+end TB_CS5_CC_Rudder;
+--
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd
new file mode 100644
index 0000000..d4d7057
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd
@@ -0,0 +1,4192 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+	generic (k1, k2: real := 1.0);  -- Gain multipliers
+	port 	(	terminal in1, in2: electrical;
+			terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+  QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+  QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+	generic (
+		k: REAL := 1.0);  -- Gain multiplier
+	port 	(	terminal input : electrical;
+			terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+	generic (
+		limit_high : real := 4.8;	-- upper limit
+		limit_low : real := -4.8); 	-- lower limit
+	port (
+		terminal input: electrical;
+		terminal output: electrical);					
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+  	QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  	QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+	constant slope : real := 1.0e-4;
+begin
+	if vin > limit_high use	-- Upper limit exceeded, so limit input signal
+		vout == limit_high + slope*(vin - limit_high);
+	elsif vin < limit_low use	-- Lower limit exceeded, so limit input signal
+		vout == limit_low + slope*(vin - limit_low);
+	else		-- No limit exceeded, so pass input signal as is
+		vout == vin;
+	end use;
+	break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+--  Transfer Function:
+--
+--                  (s + w1)         
+--    H(s) =  k *  ----------
+--                  (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lead_lag_e is
+	generic (
+		k: real := 1.0;  			-- Gain multiplier
+		f1: real := 10.0;			-- First break frequency (zero)
+		f2: real := 100.0);		-- Second break frequency (pole)
+	port 	(	terminal input: electrical;
+			terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+	quantity vin_temp : real;
+	constant w1 : real := f1*math_2_pi;
+	constant w2 : real := f2*math_2_pi;
+	constant num : real_vector := (w1, 1.0);                                                    
+	constant den : real_vector := (w2, 1.0);
+begin
+	vin_temp == vin;
+	vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo is
+    port(
+        terminal servo_in : electrical;
+        terminal pos_fb : electrical;
+        terminal servo_out : electrical
+    );
+end rudder_servo;
+
+architecture rudder_servo of rudder_servo is
+    -- Component declarations
+    -- Signal declarations
+    terminal error : electrical;
+    terminal ll_in : electrical;
+    terminal ll_out : electrical;
+    terminal summer_fb : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    summer : entity work.sum2_e(simple)
+        port map(
+            in1 => servo_in,
+            in2 => summer_fb,
+            output => error
+        );
+    forward_gain : entity work.gain_e(simple)
+        generic map(
+            k => 100.0
+        )
+        port map(
+            input => error,
+            output => ll_in
+        );
+    fb_gain : entity work.gain_e(simple)
+        generic map(
+            k => -4.57
+        )
+        port map(
+            input => pos_fb,
+            output => summer_fb
+        );
+    servo_limiter : entity work.limiter_2_e(simple)
+       generic map(
+            limit_high => 4.8,
+            limit_low => -4.8
+        )
+        port map(
+            input => ll_out,
+            output => servo_out
+        );
+    lead_lag : entity work.lead_lag_e(simple)
+        generic map(
+            k => 400.0,
+            f1 => 5.0,
+            f2 => 2000.0
+        )
+        port map(
+            input => ll_in,
+            output => ll_out
+        );
+end rudder_servo;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : gear_rv_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/10/10  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+  generic(
+    ratio : real := 1.0);   -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+                            -- Note: can be negative, if shaft polarity changes
+
+  port ( terminal rotv1 : rotational_v;
+  		terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+  quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+--  quantity w2 across torq2 through rotv2 to rotational_v_ref;
+  quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+--  w2  == w1*ratio;
+  theta == ratio*w1'integ;
+  torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+  
+  generic (
+    k : real := 1.0);                -- optional gain
+
+  port (
+    terminal input   : rotational;  -- input terminal
+    terminal output    : electrical);   -- output terminal
+  
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref;     -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+  begin  -- bhv
+   v_out ==  k*rot_in; 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  tran =   R*sin(rot) 
+--
+-- Where pos = output translational position,
+-- R = horn radius, 
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+  
+  generic (
+    R   : real := 1.0);            		-- horn radius
+
+  port (
+    terminal theta    : ROTATIONAL;   	-- input angular position port
+    terminal pos   : TRANSLATIONAL);  	-- output translational position port
+     
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+  begin			-- bhv
+   tran == R*sin(rot);		-- Convert angle in to translational out
+   tran_frc == -rot_tq/R;	-- Convert torque in to force out 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  theta =   arcsin(pos/R) 
+--
+-- Where pos = input translational position,
+-- R = horn radius, 
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+  
+  generic (
+    R   : real := 1.0);            -- Rudder horn radius
+
+  port (
+    terminal pos    : translational;   -- input translational position port
+    terminal theta   : rotational);  -- output angular position port
+     
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+  begin  -- bhv
+   rot == arcsin(tran/R);	-- Convert translational to angle
+   rot_tq == -tran_frc*R;	-- Convert force to torque
+   
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : DC_Motor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+  generic (
+    r_wind : resistance;                -- Motor winding resistance [Ohm]
+    kt     : real;                      -- Torque coefficient [N*m/Amp]
+    l      : inductance;                -- Winding inductance [Henrys]
+    d      : real;                      -- Damping coefficient [N*m/(rad/sec)]
+    j      : mmoment_i);                -- Moment of inertia [kg*meter**2]
+
+  port (terminal p1, p2 : electrical;
+        terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations:  V = Kt*W + I*Rwind + L*dI/dt
+--                   T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+  quantity v across i through p1 to p2;
+  quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+  torq == -1.0*kt*i + d*w + j*w'dot;
+  v  == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : stop_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+
+entity stop_r is
+
+  generic (
+    k_stop    : real;
+--    ang_max   : angle;
+--    ang_min   : angle := 0.0;
+	ang_max   : real;
+    ang_min   : real := 0.0;
+    damp_stop : real  := 0.000000001
+    );
+
+  port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+  quantity velocity : velocity;
+  quantity ang across trq through ang1 to ang2;
+
+begin
+
+  velocity == ang'dot;
+
+  if ang'above(ang_max) use
+    trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+  elsif ang'above(ang_min) use
+    trq   == 0.0;
+  else
+    trq   == k_stop * (ang - ang_min) + (damp_stop * velocity);
+  end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+      terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+  QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+  QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+   pos_2 == pos_1;		-- Pass position 
+   frc_2 == -frc_1;	-- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+--  Transfer Function:
+--                            
+--  torq =   -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+  
+  generic (
+    k   : real := 1.0;            -- Spring constant
+	theta_0 : real := 0.0);
+
+  port (
+    terminal rot    : rotational);   -- input rotational angle
+     
+end entity rudder;
+
+architecture bhv of rudder is
+
+  QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+  begin  -- bhv
+
+   torq == k*(theta - theta_0);	-- Convert force to torque
+   
+end bhv;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Constant Voltage Source (Includes Frequency Domain settings)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY v_constant IS
+
+-- Initialize parameters
+  GENERIC (
+    level      : VOLTAGE;		-- Constant voltage value (V)
+    ac_mag     : VOLTAGE := 1.0;	-- AC magnitude (V)
+    ac_phase   : real := 0.0);		-- AC phase (degrees)
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL pos, neg : ELECTRICAL);
+
+END ENTITY v_constant;
+
+-- Ideal Architecture (I = constant)
+ARCHITECTURE ideal OF v_constant IS
+  
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH pos TO neg;
+-- Declare quantity in frequency domain for AC analysis  
+  QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+
+  IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
+	v == level;
+  ELSE	
+  	v == ac_spec;  -- used for Frequency (AC) analysis
+  END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical sinusoidal voltage source (stick.vhd)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+
+ENTITY stick IS
+  
+-- Initialize parameters
+  GENERIC (
+    freq      : real;                     -- frequency,       [Hertz]
+    amplitude : real;                     -- amplitude,       [Volt]
+    phase     : real := 0.0;              -- initial phase,   [Degree]
+    offset    : real := 0.0;              -- DC value,        [Volt]
+    df        : real := 0.0;              -- damping factor,  [1/second]
+    ac_mag    : real := 1.0;              -- AC magnitude,    [Volt]
+    ac_phase  : real := 0.0);             -- AC phase,        [Degree]
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL v_out : ELECTRICAL);
+
+END ENTITY stick;
+
+-- Ideal Architecture
+ARCHITECTURE ideal OF stick IS
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
+-- Declare Quantity for Phase in radians (calculated below)
+  QUANTITY phase_rad : real;          
+-- Declare Quantity in frequency domain for AC analysis
+  QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN  
+-- Convert phase to radians
+  phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+  
+  IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
+    v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+  ELSE 
+    v == ac_spec;    -- used for Frequency (AC) analysis
+  END USE;
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity RF_xmtr_rcvr is
+generic (td : time := 0ns);
+port
+(
+      tdm_in : in std_logic ;
+      tdm_out : out std_logic 
+);
+
+end RF_xmtr_rcvr;
+
+architecture behavioral of RF_xmtr_rcvr is
+begin
+
+tdm_out <= tdm_in after td;
+
+end;
+--
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Simple Digital-Controlled Two-position Switch Model
+-- Switch position 1 ('0') or switch position 2 ('1')
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY switch_dig_2in is
+	GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
+		 	r_closed : RESISTANCE := 0.001; -- Closed switch resistance
+		 	trans_time : real := 0.00001); -- Transition time to each position
+
+	PORT (sw_state : in std_logic; -- Digital control input 
+    	      TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
+
+END ENTITY switch_dig_2in;
+
+
+ARCHITECTURE ideal OF switch_dig_2in IS
+
+--	CONSTANT log_r_open : real := log10(r_open);
+--	CONSTANT log_r_closed : real := log10(r_closed);
+--	SIGNAL r_sig1 : RESISTANCE := log_r_closed; -- Variable to accept switch resistance
+--	SIGNAL r_sig2 : RESISTANCE := log_r_open; -- Variable to accept switch resistance
+	SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
+	SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
+	QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
+	QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
+	QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
+	QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
+
+BEGIN
+ 
+ PROCESS (sw_state) -- Sensitivity to digital control input
+    BEGIN
+	  IF (sw_state'event AND sw_state = '0') THEN -- Close sig1, open sig2
+	    r_sig1 <= r_closed;
+	    r_sig2 <= r_open;
+	  ELSIF (sw_state'event AND sw_state = '1') THEN -- Open sig1, close sig2
+	    r_sig1 <= r_open;
+	    r_sig2 <= r_closed;
+	  END IF;
+    END PROCESS;
+
+	r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
+	r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
+	v1 == r1*i1; -- Apply Ohm's law to in1
+	v2 == r2*i2; -- Apply Ohm's law to in2
+
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Digital clock with 50% duty cycle
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock IS
+  GENERIC (
+    period : time);              -- Clock period
+  
+  PORT (
+    clk_out    : OUT std_logic);
+  
+END ENTITY clock;
+
+ARCHITECTURE ideal OF clock IS
+
+BEGIN
+
+-- clock process
+    process
+    begin
+        clk_out <= '0';
+        wait for period/2;
+        clk_out <= '1';
+        wait for period/2;
+    end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- This digital clock allows user to specify the duty cycle using
+-- the parameters "on_time" and "off_time"
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY clock_duty IS
+
+  GENERIC (
+    on_time : time := 20 us;
+	off_time : time := 19.98 ms
+ 	); 
+  
+  PORT (
+    clock_out    : OUT std_logic := '0');
+  
+END ENTITY clock_duty;
+
+ARCHITECTURE ideal OF clock_duty IS
+
+BEGIN
+
+-- clock process
+    process
+    begin
+        clock_out <= '1';
+        wait for on_time;
+        clock_out <= '0';
+        wait for off_time;
+    end process;
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rc_clk is
+    port(
+        clk_100k : out std_logic;
+        clk_6K : out std_logic;
+        clk_50 : out std_logic
+    );
+end rc_clk;
+
+architecture rc_clk of rc_clk is
+    -- Component declarations
+    -- Signal declarations
+begin
+    -- Signal assignments
+    -- Component instances
+    XCMP1 : entity work.clock(ideal)
+        generic map(
+            period => 10us
+        )
+        port map(
+            CLK_OUT => clk_100k
+        );
+    XCMP2 : entity work.clock(ideal)
+        generic map(
+            period => 150us
+        )
+        port map(
+            CLK_OUT => clk_6K
+        );
+    clk_50Hz : entity work.clock_duty(ideal)
+        generic map(
+            on_time => 20 us,
+            off_time => 19.98 ms
+        )
+        port map(
+            CLOCK_OUT => clk_50
+        );
+end rc_clk;
+--
+
+-- This model counts the number of input clock transitions and outputs
+-- a '1' when this number equals the value of the user-defined constant 'count'
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity bit_cnt is
+  generic (
+	count : integer -- User-defined value to count up to
+	);             
+port
+(
+      bit_in : in std_logic ;
+      clk : in std_logic ;
+      dly_out : out std_logic 
+);
+end bit_cnt;
+
+architecture behavioral of bit_cnt is
+begin
+	serial_clock : process is
+	begin
+		wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
+	  	FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
+	  		wait until clk'event AND (clk = '1' OR clk = 'H');
+     	END LOOP ;
+		dly_out <= '1'; -- After count is reached, set output high
+		wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
+		dly_out <= '0'; -- Reset output to '0' on next clock input
+	end process serial_clock;
+end;
+--
+
+--//////////////////////////////////////////////////////////////////
+-- NOTE: This is an intermediate file for HDL inspection only.
+--       Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach1.sdg.
+--       Generated by sde2hdl version 16.1.0.2
+--//////////////////////////////////////////////////////////////////
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+
+ENTITY state_mach1 IS
+    PORT (
+          a2d_eoc : IN std_logic;
+          clk_50 : IN std_logic;
+          clk_100k : IN std_logic;
+          clk_6k : IN std_logic;
+          ser_done : IN std_logic;
+          ch_sel : OUT std_logic;
+          frm_gen : OUT std_logic;
+          a2d_oe : OUT std_logic;
+          a2d_start : OUT std_logic;
+          p2s_oe : OUT std_logic;
+          p2s_load : OUT std_logic;
+          parity_oe : OUT std_logic;
+          ser_cnt : OUT std_logic;
+          p2s_clr : OUT std_logic);
+
+END state_mach1;
+
+ARCHITECTURE state_diagram OF state_mach1 IS
+
+    ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+    TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
+           , load, ad_ch2, delay);
+    SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
+
+    SIGNAL FB_frm_gen : std_logic;
+    SIGNAL FB_p2s_load : std_logic;
+    SIGNAL FB_ch_sel : std_logic;
+
+BEGIN 
+    frm_gen <= FB_frm_gen ;
+    p2s_load <= FB_p2s_load ;
+    ch_sel <= FB_ch_sel ;
+
+sm1: 
+  PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel) 
+  BEGIN
+
+    CASE CS_state_mach1_sm1 IS
+      WHEN V_begin =>
+        FB_frm_gen <= ('1');
+        a2d_start <= ('0');
+        a2d_oe <= ('0');
+        FB_p2s_load <= ('0');
+        p2s_clr <= ('0');
+        p2s_oe <= ('0');
+        FB_ch_sel <= ('0');
+        parity_oe <= ('0');
+        ser_cnt <= ('0');
+
+        IF ((FB_frm_gen = '1')) THEN
+          NS_state_mach1_sm1 <= frm_rd;
+        ELSE
+          NS_state_mach1_sm1 <= V_begin;
+        END IF;
+
+      WHEN frm_rd =>
+        FB_p2s_load <= ('1');
+
+        IF ((FB_p2s_load = '1')) THEN
+          NS_state_mach1_sm1 <= ser_oe;
+        ELSE
+          NS_state_mach1_sm1 <= frm_rd;
+        END IF;
+
+      WHEN ser_oe =>
+        p2s_oe <= ('1');
+        FB_frm_gen <= ('0');
+        FB_p2s_load <= ('0');
+        ser_cnt <= ('1');
+
+        IF ((ser_done = '1')) THEN
+          NS_state_mach1_sm1 <= ch1;
+        ELSE
+          NS_state_mach1_sm1 <= ser_oe;
+        END IF;
+
+      WHEN ch1 =>
+        p2s_oe <= ('0');
+        FB_ch_sel <= ('0');
+        a2d_start <= ('1');
+        ser_cnt <= ('0');
+
+        IF ((a2d_eoc = '1')) THEN
+          NS_state_mach1_sm1 <= data_en;
+        ELSE
+          NS_state_mach1_sm1 <= ch1;
+        END IF;
+
+      WHEN data_en =>
+        a2d_start <= ('0');
+        a2d_oe <= ('1');
+        parity_oe <= ('1');
+          NS_state_mach1_sm1 <= load;
+
+      WHEN tdm_oe =>
+        a2d_oe <= ('0');
+        parity_oe <= ('0');
+        p2s_oe <= ('1');
+        FB_p2s_load <= ('0');
+        ser_cnt <= ('1');
+
+        IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
+          NS_state_mach1_sm1 <= ch2;
+        ELSE
+          NS_state_mach1_sm1 <= tdm_oe;
+        END IF;
+
+      WHEN ch2 =>
+        p2s_oe <= ('0');
+        ser_cnt <= ('0');
+        FB_ch_sel <= ('1');
+          NS_state_mach1_sm1 <= delay;
+
+      WHEN load =>
+        FB_p2s_load <= ('1');
+          NS_state_mach1_sm1 <= tdm_oe;
+
+      WHEN ad_ch2 =>
+        a2d_start <= ('1');
+
+        IF ((a2d_eoc = '1')) THEN
+          NS_state_mach1_sm1 <= data_en;
+        ELSE
+          NS_state_mach1_sm1 <= ad_ch2;
+        END IF;
+
+      WHEN delay =>
+          NS_state_mach1_sm1 <= ad_ch2;
+
+    END CASE;
+
+  END PROCESS; 
+
+sm1_CTL:
+  PROCESS (clk_100k, clk_50)
+  BEGIN
+
+    IF (clk_100k'event AND clk_100k='1')  THEN 
+        IF (clk_50= '1' ) THEN 
+            CS_state_mach1_sm1 <= V_begin;
+        ELSE
+            CS_state_mach1_sm1 <= NS_state_mach1_sm1;
+        END IF;
+    END IF;
+
+  END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt is
+    port(
+        a2d_eoc : in std_logic;
+        clk_50 : in std_logic;
+        clk_100k : in std_logic;
+        clk_6k : in std_logic;
+        p2s_load : out std_logic;
+        p2s_oe : out std_logic;
+        parity_oe : out std_logic;
+        a2d_start : out std_logic;
+        a2d_oe : out std_logic;
+        frm_gen : out std_logic;
+        ch_sel : out std_logic;
+        p2s_clr : out std_logic
+    );
+end sm_cnt;
+
+architecture sm_cnt of sm_cnt is
+    -- Component declarations
+    -- Signal declarations
+    signal ser_done : std_logic;
+    signal serial_cnt : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    bit_cnt1 : entity work.bit_cnt(behavioral)
+        generic map(
+            count => 15
+        )
+        port map(
+            bit_in => serial_cnt,
+            clk => clk_6k,
+            dly_out => ser_done
+        );
+    state_mach16 : entity work.state_mach1
+        port map(
+            ser_cnt => serial_cnt,
+            ch_sel => ch_sel,
+            frm_gen => frm_gen,
+            a2d_oe => a2d_oe,
+            a2d_start => a2d_start,
+            parity_oe => parity_oe,
+            p2s_oe => p2s_oe,
+            p2s_load => p2s_load,
+            p2s_clr => p2s_clr,
+            clk_6k => clk_6k,
+            clk_100k => clk_100k,
+            clk_50 => clk_50,
+            a2d_eoc => a2d_eoc,
+            ser_done => ser_done
+        );
+end sm_cnt;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+--  Analog to Digital Converter (Successive Aproximation Register) model with sar architecture (a2d_nbit.vhd)
+--DESCRIPTION:
+--
+--This is a VHDL-AMS model of a simple analog to digital converter. The model
+--describes the general behavior of A/D converters for system level design and
+--verification.
+--The format of the digital output is binary coding.
+--
+--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
+--
+
+-- Use IEEE natures and packages
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity a2d_nbit is
+ generic (
+  Vmax: REAL := 5.0 ;   -- ADC's maximum range
+  Nbits: INTEGER := 10 ;  -- number bits in ADC's output
+  delay: TIME := 10 us    -- ADC's conversion time
+ );
+ 
+port (
+  signal start: in std_logic ; -- Start signal
+  signal clk: in std_logic ;   -- Strobe clock
+  signal oe: in std_logic ; -- Output enable
+  terminal ain: ELECTRICAL ;  -- ADC's analog input terminal
+  signal eoc: out std_logic := '0' ; -- End Of Conversion pin
+  signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
+end entity a2d_nbit;
+
+architecture sar of a2d_nbit is
+
+  type states is (input, convert, output) ; -- Three states of A2D Conversion
+  constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
+  quantity Vin across Iin through ain to electrical_ref;     -- ADC's input branch
+
+begin
+
+ sa_adc: process
+
+  variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
+  variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
+  variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
+  variable status: states := input ; -- Begin with "input" CASE 
+  variable bit_cnt: integer := Nbits -1 ;
+
+ begin
+ CASE status is
+	when input => -- Read input voltages when start goes high
+		wait on start until start = '1' or start = 'H' ;
+  		thresh := Vmax ;
+  		Vtmp := Vin ;
+		eoc <= '0' ;
+		status := convert ; -- Go to convert state
+	when convert => -- Begin successive approximation conversion
+			thresh := thresh / 2.0 ; -- Get value of MSB
+			wait on clk until clk = '1' OR clk = 'H';
+			if Vtmp > thresh then
+				dtmp(bit_cnt) := '1' ;
+				Vtmp := Vtmp - thresh ;
+			else
+				dtmp(bit_cnt) := '0' ;
+			end if ;
+			bit_cnt := bit_cnt - 1 ;
+			if (bit_cnt + 1) < 1 then
+				status := output ; -- Go to output state
+			end if;
+	when output => -- Wait for output enable, then put data on output pins
+		eoc <= '1' after delay ;
+		wait on oe until oe = '1' OR oe = 'H' ;
+			FOR i in bit_range DOWNTO 0 LOOP
+				dout(i) <= dtmp(i) ;
+			END LOOP ;
+		wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
+			FOR i in bit_range DOWNTO 0 LOOP
+				dout <= "ZZZZZZZZZZ" ;
+			END LOOP ;
+		bit_cnt := bit_range ;
+		status := input ; -- Set up for next conversion
+	END CASE ;
+ end process sa_adc ;
+
+ Iin == 0.0 ; -- Ideal input draws no current
+
+end architecture sar ;
+--
+
+-- Parallel input/serial output shift register
+-- With 4 trailing zeros
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity shift_reg is
+generic ( td : time := 0 ns); 
+
+port
+(
+      bus_in : in std_logic_vector ; -- Input bus
+      clk : in std_logic ; -- Shift clock
+      oe : in std_logic ; -- Output enable
+      ser_out : out std_logic := '0'; -- Output port
+      load : in std_logic ; -- Parallel input load
+	clr : in std_logic -- Clear register
+);
+
+end entity shift_reg;
+
+architecture behavioral of shift_reg is
+begin
+
+control_proc : process
+  VARIABLE bit_val : std_logic_vector(11 downto 0);  -- Default 12-bit input
+  begin
+
+	IF (clr = '1' OR clr = 'H') then
+    		bit_val := "000000000000"; -- Set all input bits to zero
+	ELSE
+  		wait until load'event AND (load = '1' OR load = 'H');
+		FOR i IN bus_in'high DOWNTO bus_in'low LOOP
+        		bit_val(i) := bus_in(i) ; -- Transfer input data to variable
+     		END LOOP ;
+	END IF;
+
+	wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
+	FOR i IN bit_val'high DOWNTO bit_val'low LOOP
+		wait until clk'event AND (clk = '1' OR clk = 'H');
+      	ser_out <= bit_val(i) ;
+	END LOOP ;
+
+	  FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros	
+		wait until clk'event AND (clk = '1' OR clk = 'H');
+		ser_out <= '0';
+	  END LOOP;
+
+END process;
+
+end architecture behavioral;
+--
+
+-- This model generates a 12-bit data frame synchronization code
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_gen is
+port
+(
+      oe : in std_logic := '0';
+	sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
+
+end entity frame_gen;
+
+architecture simple of frame_gen is
+begin
+	enbl: PROCESS
+  		BEGIN 
+  			WAIT ON OE;
+			IF OE = '1' THEN
+				sync_out <= "010101010101"; -- Sync code
+			ELSE
+				sync_out <= "ZZZZZZZZZZZZ";
+			END IF;
+  	END PROCESS;
+end architecture simple;
+--
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input XOR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY xor2 IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    in1, in2 : IN  std_logic;
+    output    : OUT std_logic);
+  
+END ENTITY xor2;
+
+ARCHITECTURE ideal OF xor2 IS
+BEGIN
+   output <= in1 XOR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- level_set_tri.vhd 
+-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
+-- If OE = '0' set output to high impedance
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set_tri IS
+
+  GENERIC (
+    logic_val : std_logic := 'Z');     
+
+  PORT (
+  	OE : IN std_logic;
+    level : OUT std_logic := 'Z');
+
+END ENTITY level_set_tri;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set_tri IS
+BEGIN
+  oe_ctl: PROCESS
+  BEGIN
+	WAIT ON OE;
+ 	IF OE = '1' THEN 
+   		level <= logic_val;
+	ELSE
+		level <= 'Z';
+	END IF;
+  END PROCESS;
+  
+END ARCHITECTURE ideal;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Simple Tri-state Buffer with delay time
+-- If OE = 1, output = input after delay
+-- If OE /= 1, output = Z after delay
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY buffer_tri IS
+  GENERIC (
+    delay : time := 0 ns);  -- Delay time
+  
+  PORT (
+    input : IN  std_logic;
+	OE : IN std_logic;
+    output : OUT std_logic);
+  
+END ENTITY buffer_tri;
+
+ARCHITECTURE ideal OF buffer_tri IS
+BEGIN
+  oe_ctl: PROCESS
+  BEGIN
+	WAIT ON OE, input;
+ 	IF OE = '1' THEN 
+   		output <= input AFTER delay;
+	ELSE
+		output <= 'Z' AFTER delay;
+	END IF;
+  END PROCESS;
+END ARCHITECTURE ideal;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- ideal one bit D/A converter
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY d2a_bit IS
+  GENERIC (vlow : real :=0.0;           -- output high voltage
+           vhigh : real :=5.0);         -- output low voltage
+  PORT	  (D : IN std_logic;            -- digital (std_logic) intout
+           TERMINAL A : electrical);    -- analog (electrical) output
+END ENTITY d2a_bit;
+
+ARCHITECTURE ideal OF d2a_bit IS
+  QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
+  SIGNAL vin : real := 0.0;
+
+  BEGIN
+    vin <= vhigh WHEN D = '1' ELSE vlow;
+    -- Use 'RAMP for discontinuous signal
+    vout == vin'RAMP(1.0e-9);      
+
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_gen is
+    port(
+        parity : in std_logic_vector(1 to 10);
+        oe : in std_logic;
+        parity_out : out std_logic_vector(0 to 11)
+    );
+end parity_gen;
+
+architecture parity_gen of parity_gen is
+    -- Component declarations
+    -- Signal declarations
+    terminal par_bit_gen_a : electrical;
+    signal XSIG010002 : std_logic;
+    signal XSIG010003 : std_logic;
+    signal XSIG010004 : std_logic;
+    signal XSIG010005 : std_logic;
+    signal XSIG010006 : std_logic;
+    signal XSIG010007 : std_logic;
+    signal XSIG010008 : std_logic;
+    signal XSIG010009 : std_logic;
+    signal XSIG010098 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    XCMP1 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(1),
+            in2 => parity(2),
+            output => XSIG010002
+        );
+    XCMP2 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(3),
+            in2 => parity(4),
+            output => XSIG010003
+        );
+    XCMP3 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(5),
+            in2 => parity(6),
+            output => XSIG010004
+        );
+    XCMP4 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(7),
+            in2 => parity(8),
+            output => XSIG010005
+        );
+    XCMP5 : entity work.xor2(ideal)
+        port map(
+            in1 => parity(9),
+            in2 => parity(10),
+            output => XSIG010008
+        );
+    XCMP6 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010002,
+            in2 => XSIG010003,
+            output => XSIG010006
+        );
+    XCMP7 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010004,
+            in2 => XSIG010005,
+            output => XSIG010007
+        );
+    XCMP8 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010006,
+            in2 => XSIG010007,
+            output => XSIG010009
+        );
+    XCMP9 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010009,
+            in2 => XSIG010008,
+            output => XSIG010098
+        );
+    XCMP18 : entity work.level_set_tri(ideal)
+        generic map(
+            logic_val => '1'
+        )
+        port map(
+            level => parity_out(11),
+            oe => oe
+        );
+    XCMP19 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(1),
+            output => parity_out(1),
+            oe => oe
+        );
+    XCMP20 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(2),
+            output => parity_out(2),
+            oe => oe
+        );
+    XCMP21 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(3),
+            output => parity_out(3),
+            oe => oe
+        );
+    XCMP22 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(4),
+            output => parity_out(4),
+            oe => oe
+        );
+    XCMP23 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(5),
+            output => parity_out(5),
+            oe => oe
+        );
+    XCMP24 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(6),
+            output => parity_out(6),
+            oe => oe
+        );
+    XCMP25 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(7),
+            output => parity_out(7),
+            oe => oe
+        );
+    XCMP26 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(8),
+            output => parity_out(8),
+            oe => oe
+        );
+    XCMP27 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(9),
+            output => parity_out(9),
+            oe => oe
+        );
+    XCMP28 : entity work.buffer_tri(ideal)
+        port map(
+            input => parity(10),
+            output => parity_out(10),
+            oe => oe
+        );
+    XCMP29 : entity work.buffer_tri(ideal)
+        port map(
+            input => XSIG010098,
+            output => parity_out(0),
+            oe => oe
+        );
+    XCMP30 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010098,
+            A => par_bit_gen_a
+        );
+end parity_gen;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tdm_encoder is
+    port(
+        clk : in std_logic;
+        p2s_oe : in std_logic;
+        p2s_load : in std_logic;
+        frm_gen : in std_logic;
+        parity_oe : in std_logic;
+        tdm_out : out std_logic;
+        p2s_clr : in std_logic;
+        a2d_data : in std_logic_vector(1 to 10)
+    );
+end tdm_encoder;
+
+architecture tdm_encoder of tdm_encoder is
+    -- Component declarations
+    -- Signal declarations
+    signal sync_par : std_logic_vector(0 to 11);
+begin
+    -- Signal assignments
+    -- Component instances
+    p2s1 : entity work.shift_reg(behavioral)
+        port map(
+            bus_in => sync_par,
+            clk => clk,
+            oe => p2s_oe,
+            ser_out => tdm_out,
+            load => p2s_load,
+            clr => p2s_clr
+        );
+    sync_gen1 : entity work.frame_gen(simple)
+        port map(
+            oe => frm_gen,
+            sync_out => sync_par
+        );
+    par_gen1 : entity work.parity_gen
+        port map(
+            parity => a2d_data,
+            parity_out => sync_par,
+            oe => parity_oe
+        );
+end tdm_encoder;
+--
+
+-- Manchester Encoder
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY menc_rsc IS
+	
+	port ( 	dig_in : in STD_LOGIC;  -- digital input
+		clk : in STD_LOGIC;     -- TX internal clock
+		reset: in STD_LOGIC;  -- not reset
+--	       	bit_out : inout real);  -- real output
+		bit_out : out std_logic);  -- real output
+	       
+END ENTITY menc_rsc;
+
+ARCHITECTURE bhv OF menc_rsc IS
+	 
+--	 signal bhigh:real:= 1.0;   -- bit encoding
+--	 signal blow:real:= -1.0;   -- bit encoding
+--	 signal bnormal:real:=0.0;  -- bit encoding
+	 signal bit1:STD_LOGIC;
+	 signal bhigh:std_logic:= '1';   -- bit encoding
+	 signal blow:std_logic:= '0';   -- bit encoding
+	 
+begin
+
+--	proc1: process  (dig_in, clk, bit1,bhigh,blow,bnormal) 
+	proc1: process  (dig_in, clk, bit1,bhigh,blow) 
+	begin
+	 	 	
+	if (reset = '1') then
+	   bit1 <= '0';
+	else
+	   bit1 <= dig_in XOR clk;  -- manchester encoding 
+	end if;
+	
+	if (bit1 = '1') then
+	   bit_out <= bhigh;
+	else 
+		bit_out <= blow;
+--	elsif bit1 = '0' then
+--	   bit_out <= blow;
+--	else
+--	   bit_out <= bnormal;
+	end if;
+	  
+	end process;
+	
+end architecture bhv;
+	
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Digitize_Encode_Man is
+    port(
+        tdm_out : out std_logic;
+        terminal ch1_in : electrical;
+        terminal ch2_in : electrical
+    );
+end Digitize_Encode_Man;
+
+architecture Digitize_Encode_Man of Digitize_Encode_Man is
+    -- Component declarations
+    -- Signal declarations
+    terminal a2d_ana_in : electrical;
+    signal ch_bus : std_logic_vector(1 to 10);
+    signal clk_6K : std_logic;
+    signal dig_in : std_logic;
+    signal frm_gen_ctl : std_logic;
+    signal p2s_clr : std_logic;
+    signal p2s_load : std_logic;
+    signal p2s_oe : std_logic;
+    signal par_oe : std_logic;
+    signal reset : std_logic;
+    signal reset_m : std_logic;
+    signal start_a2d1 : std_logic;
+    signal sw_ctl : std_logic;
+    signal XSIG010091 : std_logic;
+    signal XSIG010190 : std_logic;
+    signal XSIG010196 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    A_SWITCH1 : entity work.switch_dig_2in(ideal)
+        port map(
+            p_in1 => ch1_in,
+            p_out => a2d_ana_in,
+            sw_state => sw_ctl,
+            p_in2 => ch2_in
+        );
+    rc_clk2 : entity work.rc_clk
+        port map(
+            clk_50 => reset,
+            clk_6K => clk_6K,
+            clk_100k => XSIG010190
+        );
+    sm_xmtr1 : entity work.sm_cnt
+        port map(
+            clk_100k => XSIG010190,
+            a2d_start => start_a2d1,
+            a2d_eoc => XSIG010091,
+            p2s_oe => p2s_oe,
+            p2s_load => p2s_load,
+            ch_sel => sw_ctl,
+            frm_gen => frm_gen_ctl,
+            parity_oe => par_oe,
+            a2d_oe => XSIG010196,
+            clk_50 => reset,
+            clk_6k => clk_6K,
+            p2s_clr => p2s_clr
+        );
+    a2d1 : entity work.a2d_nbit(sar)
+        generic map(
+            Vmax => 4.8
+        )
+        port map(
+            dout => ch_bus,
+            ain => a2d_ana_in,
+            clk => XSIG010190,
+            start => start_a2d1,
+            eoc => XSIG010091,
+            oe => XSIG010196
+        );
+    tdm_enc1 : entity work.tdm_encoder
+        port map(
+            clk => clk_6K,
+            p2s_oe => p2s_oe,
+            tdm_out => dig_in,
+            p2s_load => p2s_load,
+            a2d_data => ch_bus,
+            frm_gen => frm_gen_ctl,
+            parity_oe => par_oe,
+            p2s_clr => p2s_clr
+        );
+    menc_rsc3 : entity work.menc_rsc(bhv)
+        port map(
+            dig_in => dig_in,
+            clk => clk_6K,
+            reset => reset_m,
+            bit_out => tdm_out
+        );
+    XCMP90 : entity work.clock_duty(ideal)
+        generic map(
+            off_time => 19.98 sec
+        )
+        port map(
+            CLOCK_OUT => reset_m
+        );
+end Digitize_Encode_Man;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input AND gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY and2 IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    in1, in2 : IN  std_logic;
+    output    : OUT std_logic);
+  
+END ENTITY and2;
+
+ARCHITECTURE ideal OF and2 IS
+BEGIN
+   output <= in1 AND in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-- D Flip Flop with reset (negative edge triggered)
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY d_latch_n_edge_rst IS
+	GENERIC (
+		delay : time := 0 ns);  -- Delay time
+  
+	PORT (
+		data, clk 	: IN std_logic;
+		q 	: OUT std_logic := '0';
+		qn	: OUT std_logic := '1';
+		rst	: IN std_logic := '0');  -- reset 
+	   
+END ENTITY d_latch_n_edge_rst ;
+
+ARCHITECTURE behav OF d_latch_n_edge_rst IS
+BEGIN
+ 
+ data_in : PROCESS(clk, rst) IS  
+
+   BEGIN
+     IF clk = '0' AND clk'event AND rst /= '1' THEN
+	     q  <= data     	AFTER delay;
+         qn <= NOT data 	AFTER delay;
+     ELSIF rst = '1' THEN
+         q <= '0';
+         qn <= '1';
+     END IF;
+     
+   END PROCESS data_in;  -- End of process data_in
+
+END ARCHITECTURE behav;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity counter_12 is
+    port(
+        cnt : out std_logic_vector(0 to 11);
+        reset : in std_logic;
+        enable : in std_logic;
+        clk : in std_logic
+    );
+end counter_12;
+
+architecture counter_12 of counter_12 is
+    -- Component declarations
+    -- Signal declarations
+    signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
+    signal XSIG010078 : std_logic;
+    signal XSIG010081 : std_logic;
+    signal XSIG010083 : std_logic;
+    signal XSIG010085 : std_logic;
+    signal XSIG010087 : std_logic;
+    signal XSIG010101 : std_logic;
+    signal XSIG010102 : std_logic;
+    signal XSIG010103 : std_logic;
+    signal XSIG010104 : std_logic;
+    signal XSIG010115 : std_logic;
+    signal XSIG010116 : std_logic;
+    signal XSIG010117 : std_logic;
+    signal XSIG010132 : std_logic;
+begin
+    -- Signal assignments
+    cnt(0) <= cdb2vhdl_tmp_1(0);
+    cnt(1) <= cdb2vhdl_tmp_1(1);
+    cnt(2) <= cdb2vhdl_tmp_1(2);
+    cnt(3) <= cdb2vhdl_tmp_1(3);
+    cnt(4) <= cdb2vhdl_tmp_1(4);
+    cnt(5) <= cdb2vhdl_tmp_1(5);
+    cnt(6) <= cdb2vhdl_tmp_1(6);
+    cnt(7) <= cdb2vhdl_tmp_1(7);
+    cnt(8) <= cdb2vhdl_tmp_1(8);
+    cnt(9) <= cdb2vhdl_tmp_1(9);
+    cnt(10) <= cdb2vhdl_tmp_1(10);
+    cnt(11) <= cdb2vhdl_tmp_1(11);
+    -- Component instances
+    XCMP92 : entity work.and2(ideal)
+        port map(
+            in1 => clk,
+            in2 => enable,
+            output => XSIG010132
+        );
+    XCMP93 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => XSIG010132,
+            DATA => XSIG010078,
+            QN => XSIG010078,
+            Q => cdb2vhdl_tmp_1(0),
+            RST => reset
+        );
+    XCMP94 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(0),
+            DATA => XSIG010081,
+            QN => XSIG010081,
+            Q => cdb2vhdl_tmp_1(1),
+            RST => reset
+        );
+    XCMP95 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(1),
+            DATA => XSIG010083,
+            QN => XSIG010083,
+            Q => cdb2vhdl_tmp_1(2),
+            RST => reset
+        );
+    XCMP96 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(2),
+            DATA => XSIG010085,
+            QN => XSIG010085,
+            Q => cdb2vhdl_tmp_1(3),
+            RST => reset
+        );
+    XCMP97 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(3),
+            DATA => XSIG010087,
+            QN => XSIG010087,
+            Q => cdb2vhdl_tmp_1(4),
+            RST => reset
+
+        );
+    XCMP98 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(4),
+            DATA => XSIG010101,
+            QN => XSIG010101,
+            Q => cdb2vhdl_tmp_1(5),
+            RST => reset
+        );
+    XCMP99 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(5),
+            DATA => XSIG010102,
+            QN => XSIG010102,
+            Q => cdb2vhdl_tmp_1(6),
+            RST => reset
+        );
+    XCMP100 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(6),
+            DATA => XSIG010103,
+            QN => XSIG010103,
+            Q => cdb2vhdl_tmp_1(7),
+            RST => reset
+        );
+    XCMP101 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(7),
+            DATA => XSIG010104,
+            QN => XSIG010104,
+            Q => cdb2vhdl_tmp_1(8),
+            RST => reset
+        );
+    XCMP102 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(8),
+            DATA => XSIG010115,
+            QN => XSIG010115,
+            Q => cdb2vhdl_tmp_1(9),
+            RST => reset
+        );
+    XCMP103 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(9),
+            DATA => XSIG010116,
+            QN => XSIG010116,
+            Q => cdb2vhdl_tmp_1(10),
+            RST => reset
+        );
+    XCMP104 : entity work.d_latch_n_edge_rst(behav)
+        port map(
+            CLK => cdb2vhdl_tmp_1(10),
+            DATA => XSIG010117,
+            QN => XSIG010117,
+            Q => cdb2vhdl_tmp_1(11),
+            RST => reset
+        );
+end counter_12;
+--
+
+-- 12-bit digital comparator model
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity dig_cmp is
+port
+(
+      eq : out std_logic := '0';
+	  in1 : in std_logic_vector (0 to 11);
+	  in2 : in std_logic_vector (0 to 11);
+	  latch_in1 : in std_logic := '0'; -- Currently unused
+	  latch_in2 : in std_logic := '0';
+	  cmp : in std_logic := '0';
+	  clk : in std_logic
+	  );
+
+end entity dig_cmp ;
+
+architecture simple of dig_cmp is
+
+begin
+
+	compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
+	variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
+  		BEGIN
+		if latch_in2 = '1' then -- in2 data is latched and stored
+			in2_hold := in2;
+		end if;
+		if cmp = '1' then
+			if in1 = in2_hold then -- latched in2 checked against current in1
+				eq <= '0';
+			else eq <= '1';
+			end if;
+		end if;
+  	END PROCESS;
+end architecture simple;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical Resistor Model
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY resistor IS 
+
+-- Initialize parameters
+  GENERIC (
+    res : RESISTANCE);                 -- resistance (no initial value)
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL p1, p2 : ELECTRICAL);
+
+END ENTITY resistor;
+
+-- Ideal Architecture (V = I*R)
+ARCHITECTURE ideal OF resistor IS
+  
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH p1 TO p2;
+
+BEGIN
+  
+-- Characteristic equations
+  v == i*res;                       
+
+END ARCHITECTURE ideal;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Digital clock with 50% duty cycle and enable pin
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY clock_en IS
+  GENERIC (
+    pw : time);              -- Clock pulse width
+  
+  PORT (
+	enable : IN std_logic ;
+	clock_out : INOUT std_logic := '0');
+  
+END ENTITY clock_en;
+
+ARCHITECTURE ideal OF clock_en IS
+
+BEGIN
+
+-- clock process
+    process (clock_out, enable) is
+    begin
+   	if clock_out = '0' AND enable = '1' THEN
+        clock_out <= '1' after pw, '0' after 2*pw;
+	end if;
+    end process;
+
+END ARCHITECTURE ideal;
+--
+
+-- Set/reset flip flop
+-- When S goes high, Q is set high until reset
+-- When R goes high, Q is set low until set
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sr_ff is
+port
+(
+      S : in std_logic ;
+      R : in std_logic ;
+	Q : out std_logic 
+);
+
+end sr_ff ;
+
+architecture simple of sr_ff is
+begin
+
+ set_reset: PROCESS(S, R) IS  
+
+   BEGIN
+--	assert S='1' nand R='1' -- Warning if both inputs are high
+--		report "S and R are both active. Use with caution"
+--		severity warning;
+	if S'event AND S = '1' then
+		Q <= '1';
+	end if;
+	if R'event AND R = '1' then
+		Q <= '0';
+	end if;     
+   END PROCESS set_reset; 
+
+end;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Inverter
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY inverter IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    input : IN  std_logic;
+    output : OUT std_logic);
+  
+END ENTITY inverter;
+
+ARCHITECTURE ideal OF inverter IS
+BEGIN
+   output <= NOT input AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+--//////////////////////////////////////////////////////////////////
+-- NOTE: This is an intermediate file for HDL inspection only.
+--       Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach_rcvr.sdg.
+--       Generated by sde2hdl version 16.1.0.2
+--//////////////////////////////////////////////////////////////////
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.all;
+USE IEEE_proposed.mechanical_systems.all;
+
+ENTITY state_mach_rcvr IS
+    PORT (
+          clk_50 : IN std_logic;
+          clk_100k : IN std_logic;
+          ser_done : IN std_logic;
+          par_det : IN std_logic;
+          frm_det : IN std_logic;
+          clk_6k : IN std_logic;
+          start_pulse : IN std_logic;
+          dly_done : IN std_logic;
+          s2p_rst : OUT std_logic;
+          s2p_en : OUT std_logic;
+          cnt1_en : OUT std_logic;
+          cnt1_rst : OUT std_logic;
+          cmp1_ltch1 : OUT std_logic;
+          cmp1_ltch2 : OUT std_logic;
+          cnt2_en : OUT std_logic;
+          cnt2_rst : OUT std_logic;
+          cmp2_ltch1 : OUT std_logic;
+          cmp2_ltch2 : OUT std_logic;
+          da_latch : OUT std_logic;
+          ser_cnt : OUT std_logic;
+          dly_cnt : OUT std_logic;
+          par_oe : OUT std_logic);
+
+END state_mach_rcvr;
+
+ARCHITECTURE state_diagram OF state_mach_rcvr IS
+
+    ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
+
+    TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
+           , s_bit, par1, par2);
+    SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
+
+
+BEGIN 
+
+sm1: 
+  PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det) 
+  BEGIN
+
+    CASE CS_state_mach_rcvr_sm1 IS
+      WHEN V_begin =>
+        cnt1_en <= ('0');
+        cnt1_rst <= ('1');
+        cmp1_ltch1 <= ('0');
+        cmp1_ltch2 <= ('0');
+        cnt2_en <= ('0');
+        cnt2_rst <= ('1');
+        cmp2_ltch1 <= ('0');
+        cmp2_ltch2 <= ('0');
+        s2p_en <= ('1');
+        s2p_rst <= ('0');
+        da_latch <= ('0');
+        ser_cnt <= ('0');
+        dly_cnt <= ('0');
+        par_oe <= ('0');
+
+        IF ((frm_det = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= s_bit;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= V_begin;
+        END IF;
+
+      WHEN cnt =>
+        ser_cnt <= ('1');
+        cnt1_rst <= ('0');
+        cnt2_rst <= ('0');
+
+        IF ((ser_done = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= par1;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= cnt;
+        END IF;
+
+      WHEN ch1 =>
+        cmp1_ltch2 <= ('1');
+        ser_cnt <= ('0');
+        dly_cnt <= ('1');
+
+        IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
+          NS_state_mach_rcvr_sm1 <= rst1;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= ch1;
+        END IF;
+
+      WHEN rst1 =>
+        cmp1_ltch2 <= ('0');
+        ser_cnt <= ('1');
+        dly_cnt <= ('0');
+        par_oe <= ('0');
+
+        IF ((ser_done = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= par2;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= rst1;
+        END IF;
+
+      WHEN ch2 =>
+        cmp2_ltch2 <= ('1');
+        ser_cnt <= ('0');
+        da_latch <= ('1');
+          NS_state_mach_rcvr_sm1 <= rst2;
+
+      WHEN rst2 =>
+        cmp2_ltch2 <= ('0');
+        s2p_en <= ('0');
+        par_oe <= ('0');
+        da_latch <= ('0');
+          NS_state_mach_rcvr_sm1 <= cnt_cmp;
+
+      WHEN cnt_cmp =>
+        cnt1_en <= ('1');
+        cmp1_ltch1 <= ('1');
+        cnt2_en <= ('1');
+        cmp2_ltch1 <= ('1');
+          NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+      WHEN rst_cnt =>
+        cnt1_en <= ('0');
+        cmp1_ltch1 <= ('0');
+        cnt2_en <= ('0');
+        cmp2_ltch1 <= ('0');
+          NS_state_mach_rcvr_sm1 <= rst_cnt;
+
+      WHEN s_bit =>
+
+        IF ((start_pulse = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= cnt;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= s_bit;
+        END IF;
+
+      WHEN par1 =>
+        par_oe <= ('1');
+
+        IF ((par_det = '0')) THEN
+          NS_state_mach_rcvr_sm1 <= ch1;
+        ELSIF ((par_det = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= rst1;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= par1;
+        END IF;
+
+      WHEN par2 =>
+        par_oe <= ('1');
+
+        IF ((par_det = '0')) THEN
+          NS_state_mach_rcvr_sm1 <= ch2;
+        ELSIF ((par_det = '1')) THEN
+          NS_state_mach_rcvr_sm1 <= rst2;
+        ELSE
+          NS_state_mach_rcvr_sm1 <= par2;
+        END IF;
+
+    END CASE;
+
+  END PROCESS; 
+
+sm1_CTL:
+  PROCESS (clk_100k, clk_50)
+  BEGIN
+
+    IF (clk_100k'event AND clk_100k='1')  THEN 
+        IF (clk_50= '1' ) THEN 
+            CS_state_mach_rcvr_sm1 <= V_begin;
+        ELSE
+            CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
+        END IF;
+    END IF;
+
+  END PROCESS;
+
+
+END state_diagram;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sm_cnt_rcvr is
+    port(
+        cmp1_ltch1 : out std_logic;
+        cmp2_ltch1 : out std_logic;
+        s2p_en : out std_logic;
+        s2p_rst : out std_logic;
+        frm_det : in std_logic;
+        par_det : in std_logic;
+        clk_100k : in std_logic;
+        clk_6k : in std_logic;
+        clk_50 : in std_logic;
+        start_pulse : in std_logic;
+        cnt1_en : out std_logic;
+        cnt1_rst : out std_logic;
+        cmp1_ltch2 : out std_logic;
+        cnt2_en : out std_logic;
+        cnt2_rst : out std_logic;
+        cmp2_ltch2 : out std_logic;
+        da_latch : out std_logic;
+        par_oe : out std_logic
+    );
+end sm_cnt_rcvr;
+
+architecture sm_cnt_rcvr of sm_cnt_rcvr is
+    -- Component declarations
+    -- Signal declarations
+    terminal dly_cnt_a : electrical;
+    terminal dly_done_a : electrical;
+    terminal ser_cnt_a : electrical;
+    terminal ser_done_a : electrical;
+    signal XSIG010001 : std_logic;
+    signal XSIG010002 : std_logic;
+    signal XSIG010145 : std_logic;
+    signal XSIG010146 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    XCMP1 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010001,
+            A => ser_cnt_a
+        );
+    XCMP2 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010002,
+            A => ser_done_a
+        );
+    bit_cnt3 : entity work.bit_cnt(behavioral)
+        generic map(
+            count => 2
+        )
+        port map(
+            bit_in => XSIG010145,
+            clk => clk_6k,
+            dly_out => XSIG010146
+        );
+    bit_cnt4 : entity work.bit_cnt(behavioral)
+        generic map(
+            count => 10
+        )
+        port map(
+            bit_in => XSIG010001,
+            clk => clk_6k,
+            dly_out => XSIG010002
+        );
+    XCMP8 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010145,
+            A => dly_cnt_a
+        );
+    XCMP9 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010146,
+            A => dly_done_a
+        );
+    state_mach_rcvr8 : entity work.state_mach_rcvr
+        port map(
+            clk_100k => clk_100k,
+            clk_50 => clk_50,
+            s2p_rst => s2p_rst,
+            s2p_en => s2p_en,
+            cnt1_en => cnt1_en,
+            cnt1_rst => cnt1_rst,
+            cmp1_ltch1 => cmp1_ltch1,
+            cmp1_ltch2 => cmp1_ltch2,
+            cnt2_en => cnt2_en,
+            cnt2_rst => cnt2_rst,
+            cmp2_ltch1 => cmp2_ltch1,
+            cmp2_ltch2 => cmp2_ltch2,
+            da_latch => da_latch,
+            ser_cnt => XSIG010001,
+            ser_done => XSIG010002,
+            par_det => par_det,
+            frm_det => frm_det,
+            clk_6k => clk_6k,
+            start_pulse => start_pulse,
+            dly_done => XSIG010146,
+            dly_cnt => XSIG010145,
+            par_oe => par_oe
+        );
+end sm_cnt_rcvr;
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- level_set.vhd 
+-- Set digital output "level" with parameter "logic_val" (default is '1')
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY level_set IS
+
+  GENERIC (
+    logic_val : std_logic := '1');     
+
+  PORT (
+    level : OUT std_logic);
+
+END ENTITY level_set;
+
+-- Simple architecture
+
+ARCHITECTURE ideal OF level_set IS
+
+BEGIN
+
+  level <= logic_val;
+  
+END ARCHITECTURE ideal;
+
+--
+
+-- Serial to parallel data converter
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity ser2par is
+port
+(
+      par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
+      clk : in std_logic ;
+      load_en : in std_logic ;
+      ser_in : in std_logic ;
+      reset : in std_logic 
+);
+
+begin
+
+end ser2par;
+
+architecture a1 of ser2par is
+BEGIN 
+	sr_sm: PROCESS (load_en, clk, reset, ser_in)	
+	BEGIN
+		if (reset = '1' and load_en = '1') then
+			par_out <= "000000000000";  -- Reset the parallel data out
+			
+		elsif (clk'event and clk = '1') then
+			if (load_en ='1') then 
+				
+				-- The register will shift when load is enabled 
+				-- and will shift at rising edge of clock
+				
+				par_out(0) <= ser_in; -- Input data shifts into bit 0
+				par_out(1) <= par_out(0);
+				par_out(2) <= par_out(1);
+				par_out(3) <= par_out(2);
+				par_out(4) <= par_out(3);
+				par_out(5) <= par_out(4);
+				par_out(6) <= par_out(5);
+				par_out(7) <= par_out(6);
+				par_out(8) <= par_out(7);
+				par_out(9) <= par_out(8);
+				par_out(10) <= par_out(9);
+				par_out(11) <= par_out(10); 
+
+			else
+			      -- The otput data will not change 
+				-- if load_en is not enabled		
+		         	par_out <= "ZZZZZZZZZZZZ";			
+ 			end if;
+		end if;			
+	END PROCESS;
+end;
+--
+
+-- This model ouputs a '1' when a specific bit pattern is encountered
+-- Otherwise, it outputs a zero
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity frame_det is
+port
+(
+	  bus_in : in std_logic_vector (0 to 11);
+	  clk : in std_logic;
+	  frm_bit : out std_logic := '0' -- Initialize output to zero
+	  );
+
+end entity frame_det;
+
+architecture simple of frame_det is
+begin
+	enbl: PROCESS (bus_in, clk) -- Sensitivity list
+  		BEGIN 
+		if bus_in = "010101010101" then -- This is the pre-defined bit pattern
+			if clk'event AND clk = '0' then -- Output updated synchronously
+				frm_bit <= '1';
+			end if;
+		else frm_bit <= '0';
+		end if;
+  	END PROCESS;
+end architecture simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity parity_det is
+    port(
+        bus_in : in std_logic_vector(0 to 11);
+        par_bit : out std_logic;
+        oe : in std_logic
+    );
+end parity_det;
+
+architecture parity_det of parity_det is
+    -- Component declarations
+    -- Signal declarations
+    signal cdb2vhdl_tmp_1 : std_logic;
+    terminal par_bit_a : electrical;
+    signal XSIG010010 : std_logic;
+    signal XSIG010011 : std_logic;
+    signal XSIG010012 : std_logic;
+    signal XSIG010013 : std_logic;
+    signal XSIG010014 : std_logic;
+    signal XSIG010015 : std_logic;
+    signal XSIG010016 : std_logic;
+    signal XSIG010017 : std_logic;
+    signal XSIG010019 : std_logic;
+    signal XSIG010057 : std_logic;
+begin
+    -- Signal assignments
+    par_bit <= cdb2vhdl_tmp_1;
+    -- Component instances
+    XCMP1 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(1),
+            in2 => bus_in(2),
+            output => XSIG010010
+        );
+    XCMP2 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(3),
+            in2 => bus_in(4),
+            output => XSIG010011
+        );
+    XCMP3 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(5),
+            in2 => bus_in(6),
+            output => XSIG010012
+        );
+    XCMP4 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(7),
+            in2 => bus_in(8),
+            output => XSIG010013
+        );
+    XCMP5 : entity work.xor2(ideal)
+        port map(
+            in1 => bus_in(9),
+            in2 => bus_in(10),
+            output => XSIG010016
+        );
+    XCMP6 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010010,
+            in2 => XSIG010011,
+            output => XSIG010014
+        );
+    XCMP7 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010012,
+            in2 => XSIG010013,
+            output => XSIG010015
+        );
+    XCMP8 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010014,
+            in2 => XSIG010015,
+            output => XSIG010017
+        );
+    XCMP9 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010017,
+            in2 => XSIG010016,
+            output => XSIG010019
+        );
+    XCMP10 : entity work.xor2(ideal)
+        port map(
+            in1 => XSIG010019,
+            in2 => bus_in(0),
+            output => XSIG010057
+        );
+    XCMP11 : entity work.d2a_bit(ideal)
+        port map(
+            D => cdb2vhdl_tmp_1,
+            A => par_bit_a
+        );
+    XCMP12 : entity work.and2(ideal)
+        port map(
+            in1 => oe,
+            in2 => XSIG010057,
+            output => cdb2vhdl_tmp_1
+        );
+end parity_det;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+ENTITY d2a_nbit IS
+
+  GENERIC (
+    vmax : real := 5.0;	-- High output
+    vmin : real := 0.0;	-- Low output
+    high_bit : integer := 9; -- High end of bit range for D/A
+	low_bit : integer := 0); -- Low end of bit range for D/A
+
+  PORT (
+    SIGNAL   bus_in : IN STD_LOGIC_VECTOR;  -- variable width vector input
+    SIGNAL latch : IN STD_LOGIC;
+    TERMINAL ana_out  :    electrical);      -- analog output
+
+END ENTITY d2a_nbit ;
+
+ARCHITECTURE behavioral OF d2a_nbit IS
+
+  SIGNAL   sout : real := 0.0;
+  QUANTITY vout across iout through ana_out TO electrical_ref;
+
+BEGIN  -- ARCHITECTURE behavioral
+
+  proc : PROCESS
+
+    VARIABLE v_sum  : real; -- Sum of voltage contribution from each bit
+    VARIABLE delt_v : real; -- Represents the voltage value of each bit
+
+  BEGIN
+	WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
+  	v_sum     := vmin;
+    	delt_v    := vmax - vmin;
+
+    FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
+      delt_v  := delt_v / 2.0;
+      IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
+        v_sum := v_sum + delt_v;
+      END IF;
+    END LOOP;
+
+    sout <= v_sum;
+  END PROCESS;
+
+  vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
+
+END ARCHITECTURE behavioral;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity TDM_Demux_dbg is
+    port(
+        s2p_en : in std_logic;
+        tdm_in : in std_logic;
+        clk_6k : in std_logic;
+        s2p_rst : in std_logic;
+        par_det : out std_logic;
+        frm_det : out std_logic;
+        da_latch : in std_logic;
+        par_oe : in std_logic;
+        data_bus : out std_logic_vector(1 to 10);
+        start_bit : out std_logic
+    );
+end TDM_Demux_dbg;
+
+architecture TDM_Demux_dbg of TDM_Demux_dbg is
+    -- Component declarations
+    -- Signal declarations
+    terminal d2a_out : electrical;
+    signal rcvr_bus : std_logic_vector(0 to 11);
+begin
+    -- Signal assignments
+    data_bus(1) <= rcvr_bus(1);
+    data_bus(2) <= rcvr_bus(2);
+    data_bus(3) <= rcvr_bus(3);
+    data_bus(4) <= rcvr_bus(4);
+    data_bus(5) <= rcvr_bus(5);
+    data_bus(6) <= rcvr_bus(6);
+    data_bus(7) <= rcvr_bus(7);
+    data_bus(8) <= rcvr_bus(8);
+    data_bus(9) <= rcvr_bus(9);
+    data_bus(10) <= rcvr_bus(10);
+    start_bit <= rcvr_bus(0);
+    -- Component instances
+    s2p1 : entity work.ser2par(a1)
+        port map(
+            par_out => rcvr_bus,
+            clk => clk_6k,
+            load_en => s2p_en,
+            ser_in => tdm_in,
+            reset => s2p_rst
+        );
+    frm_det1 : entity work.frame_det(simple)
+        port map(
+            bus_in => rcvr_bus,
+            frm_bit => frm_det,
+            clk => clk_6k
+        );
+    par_det1 : entity work.parity_det
+        port map(
+            bus_in => rcvr_bus,
+            par_bit => par_det,
+            oe => par_oe
+        );
+    XCMP113 : entity work.d2a_nbit(behavioral)
+        generic map(
+            low_bit => 1,
+            high_bit => 10,
+            vmax => 4.8
+        )
+        port map(
+            bus_in => rcvr_bus(1 to 10),
+            ana_out => d2a_out,
+            latch => da_latch
+        );
+end TDM_Demux_dbg;
+--
+
+-- Manchester Decoder with clock recovery using 8x referenced clock
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity mdec_rsc is
+--	port (	din: in real;                -- real input
+	port (	din: in std_logic;           -- real input
+		clk16x: in std_logic;	     -- 16x referenced clock
+		reset: in std_logic;       -- not reset
+		bout: out std_logic := '0';         -- digital output
+		clk_out: inout std_logic := '0');   -- recovered clock
+end entity mdec_rsc;
+
+architecture bhv of mdec_rsc is
+--	signal bhigh:real:= 1.0;   	      -- bit decoding 
+--	signal blow:real:= -1.0;	      -- bit decoding
+--	signal bnormal:real:=0.0;      	      -- bit decoding
+	signal bhigh:std_logic:= '1';   	      -- bit decoding 
+	signal blow:std_logic:= '0';	      -- bit decoding
+	signal bout1:std_logic;
+	signal clk_div:std_logic_vector(3 downto 0):="0000";  -- clock counter
+	signal trans:std_logic;              -- transisition trigger
+begin
+	-- bit decoding
+	proc1: process (reset,din,clk16x)
+	begin
+	if (reset = '1') then
+	   bout1 <= 'X';
+	elsif (clk16x'event and clk16x = '1') then
+	   if (din = bhigh) then
+	      bout1 <= '1';
+	   elsif (din = blow) then
+	      bout1 <= '0';
+	   else
+	      bout1 <= 'X';
+	   end if;
+	end if;
+	end process;
+		
+	-- clock counter
+	proc2: process (reset, clk16x, clk_div)
+	begin
+	
+	if (reset = '1') then
+	   clk_div <= "0000";
+	elsif (clk16x'event and clk16x = '1') then
+	   clk_div <= clk_div + "0001";
+	end if;
+	end process;
+	
+	-- recovered clock
+	-- clk_out <= not clk_div(3);  
+	clk_out <= clk_div(3);  
+	
+	-- transition trigger
+trans <= ((not clk_div(3)) and (not clk_div(2)) and clk_div(1) and clk_div(0)) or 
+	          (clk_div(3) and clk_div(2) and (not clk_div(1)) and (not clk_div(0)));
+
+	-- Manchester decoder
+	proc3: process (reset, trans, bout1, clk_out, clk16x)
+	begin
+	if (reset = '1') then
+	   bout <= '0';
+	elsif (clk16x'event and clk16x = '1') then
+	   if  (trans = '1') then
+	      bout <= bout1 XOR clk_out;
+	   end if;
+	end if;
+	end process;
+	     
+end architecture bhv;	
+
+architecture bhv_8 of mdec_rsc is
+--	signal bhigh:real:= 1.0;   	      -- bit decoding 
+--	signal blow:real:= -1.0;	      -- bit decoding
+--	signal bnormal:real:=0.0;      	      -- bit decoding
+	signal bhigh:std_logic:= '1';   	      -- bit decoding 
+	signal blow:std_logic:= '0';	      -- bit decoding
+	signal bout1:std_logic;
+	signal clk_div:std_logic_vector(2 downto 0):="000";  -- clock counter
+	signal trans:std_logic;              -- transisition trigger
+begin
+	-- bit decoding
+	proc1: process (reset,din,clk16x)
+	begin
+	if (reset = '1') then
+	   bout1 <= 'X';
+	elsif (clk16x'event and clk16x = '1') then
+	   if (din = bhigh) then
+	      bout1 <= '1';
+	   elsif (din = blow) then
+	      bout1 <= '0';
+	   else
+	      bout1 <= 'X';
+	   end if;
+	end if;
+	end process;
+		
+	-- clock counter
+	proc2: process (reset, clk16x, clk_div)
+	begin
+	
+	if (reset = '1') then
+	   clk_div <= "000";
+	elsif (clk16x'event and clk16x = '1') then
+	   clk_div <= clk_div + "001";
+	end if;
+	end process;
+	
+	-- recovered clock
+	clk_out <= not clk_div(2);  
+	
+	-- transition trigger
+	trans <= ((not clk_div(1)) and clk_div(0)) or (clk_div(1) and (not clk_div(0)));
+
+	-- Manchester decoder
+	proc3: process (reset, trans, bout1, clk_out, clk16x)
+	begin
+	if (reset = '1') then
+	   bout <= '0';
+	elsif (clk16x'event and clk16x = '1') then
+	   if  (trans = '1') then
+	      bout <= bout1 XOR clk_out;
+	   end if;
+	end if;
+	end process;
+	     
+end architecture bhv_8;	
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity Decode_PW_Man is
+    port(
+        terminal power : electrical;
+        terminal ch1_pw : electrical;
+        terminal ch2_pw : electrical;
+        bit_stream_in : in std_logic
+    );
+end Decode_PW_Man;
+
+architecture Decode_PW_Man of Decode_PW_Man is
+    -- Component declarations
+    -- Signal declarations
+    signal bit_stream_in_mdec : std_logic;
+    signal clk16x : std_logic;
+    signal clk6k : std_logic;
+    signal clk_100k : std_logic;
+    signal cmp_bus : std_logic_vector(0 to 11);
+    signal cnt1 : std_logic_vector(0 to 11);
+    signal cnt2 : std_logic_vector(0 to 11);
+    signal mdec_clk : std_logic;
+    signal mdec_out : std_logic;
+    signal reset : std_logic;
+    signal reset_m : std_logic;
+    signal XSIG010228 : std_logic;
+    signal XSIG010229 : std_logic;
+    signal XSIG010256 : std_logic;
+    signal XSIG010263 : std_logic;
+    signal XSIG010264 : std_logic;
+    signal XSIG010266 : std_logic;
+    signal XSIG010267 : std_logic;
+    signal XSIG010268 : std_logic;
+    signal XSIG010320 : std_logic;
+    signal XSIG010330 : std_logic;
+    signal XSIG010334 : std_logic;
+    signal XSIG010339 : std_logic;
+    signal XSIG010349 : std_logic;
+    signal XSIG010357 : std_logic;
+    signal XSIG010371 : std_logic;
+    signal XSIG010372 : std_logic;
+    signal XSIG010373 : std_logic;
+    signal XSIG010383 : std_logic;
+    signal XSIG010384 : std_logic;
+    signal XSIG010385 : std_logic;
+    signal XSIG010386 : std_logic;
+    signal XSIG010390 : std_logic;
+    signal XSIG010433 : std_logic;
+begin
+    -- Signal assignments
+    bit_stream_in_mdec <= bit_stream_in;
+    -- Component instances
+    cntr1 : entity work.counter_12
+        port map(
+            enable => XSIG010384,
+            cnt => cnt1,
+            reset => XSIG010357,
+            clk => XSIG010433
+        );
+    cntr2 : entity work.counter_12
+        port map(
+            enable => XSIG010349,
+            cnt => cnt2,
+            reset => XSIG010385,
+            clk => XSIG010320
+        );
+    cmp1 : entity work.dig_cmp(simple)
+        port map(
+            in1 => cnt1,
+            eq => XSIG010371,
+            clk => XSIG010433,
+            in2 => cmp_bus,
+            cmp => XSIG010384,
+            latch_in1 => XSIG010256,
+            latch_in2 => XSIG010383
+        );
+    cmp2 : entity work.dig_cmp(simple)
+        port map(
+            in1 => cnt2,
+            eq => XSIG010372,
+            clk => XSIG010320,
+            in2 => cmp_bus,
+            cmp => XSIG010349,
+            latch_in1 => XSIG010263,
+            latch_in2 => XSIG010264
+        );
+    XCMP109 : entity work.resistor(ideal)
+        generic map(
+            res => 1000000.0
+        )
+        port map(
+            p1 => power,
+            p2 => ELECTRICAL_REF
+        );
+    clk_1M2 : entity work.clock_en(ideal)
+        generic map(
+            pw => 500 ns
+        )
+        port map(
+            CLOCK_OUT => XSIG010320,
+            enable => XSIG010349
+        );
+    clk_1M1 : entity work.clock_en(ideal)
+        generic map(
+            pw => 500 ns
+        )
+        port map(
+            CLOCK_OUT => XSIG010433,
+            enable => XSIG010384
+        );
+    XCMP134 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010371,
+            A => ch1_pw
+        );
+    XCMP135 : entity work.d2a_bit(ideal)
+        port map(
+            D => XSIG010372,
+            A => ch2_pw
+        );
+    XCMP137 : entity work.SR_FF(simple)
+        port map(
+            S => XSIG010330,
+            R => XSIG010334,
+            Q => XSIG010349
+        );
+    XCMP138 : entity work.inverter(ideal)
+        port map(
+            input => XSIG010372,
+            output => XSIG010334
+        );
+    XCMP139 : entity work.SR_FF(simple)
+        port map(
+            S => XSIG010373,
+            R => XSIG010339,
+            Q => XSIG010384
+        );
+    XCMP140 : entity work.inverter(ideal)
+        port map(
+            input => XSIG010371,
+            output => XSIG010339
+        );
+    rc_clk2 : entity work.rc_clk
+        port map(
+            clk_50 => reset,
+            clk_6K => clk6k,
+            clk_100k => clk_100k
+        );
+    sm_rcvr1 : entity work.sm_cnt_rcvr
+        port map(
+            cnt1_en => XSIG010373,
+            cmp1_ltch1 => XSIG010256,
+            cnt2_rst => XSIG010385,
+            clk_100k => clk_100k,
+            cnt1_rst => XSIG010357,
+            cnt2_en => XSIG010330,
+            cmp2_ltch1 => XSIG010263,
+            frm_det => XSIG010229,
+            par_det => XSIG010228,
+            s2p_en => XSIG010266,
+            s2p_rst => XSIG010267,
+            clk_6k => mdec_clk,
+            clk_50 => reset,
+            da_latch => XSIG010268,
+            cmp1_ltch2 => XSIG010383,
+            cmp2_ltch2 => XSIG010264,
+            start_pulse => XSIG010390,
+            par_oe => XSIG010386
+        );
+    XCMP155 : entity work.level_set(ideal)
+        generic map(
+            logic_val => '0'
+        )
+        port map(
+            level => cmp_bus(11)
+        );
+    XCMP157 : entity work.TDM_Demux_dbg
+        port map(
+            data_bus => cmp_bus(0 to 9),
+            tdm_in => mdec_out,
+            clk_6k => mdec_clk,
+            s2p_en => XSIG010266,
+            s2p_rst => XSIG010267,
+            da_latch => XSIG010268,
+            frm_det => XSIG010229,
+            par_det => XSIG010228,
+            par_oe => XSIG010386,
+            start_bit => XSIG010390
+        );
+    XCMP172 : entity work.level_set(ideal)
+        generic map(
+            logic_val => '1'
+        )
+        port map(
+            level => cmp_bus(10)
+        );
+    clock1 : entity work.clock(ideal)
+        generic map(
+            period => 9.375us
+        )
+        port map(
+            CLK_OUT => clk16x
+        );
+    mdec_rsc7 : entity work.mdec_rsc(bhv)
+        port map(
+            din => bit_stream_in_mdec,
+            clk16x => clk16x,
+            reset => reset_m,
+            bout => mdec_out,
+            clk_out => mdec_clk
+        );
+    XCMP181 : entity work.clock_duty(ideal)
+        generic map(
+            off_time => 19.98 sec
+        )
+        port map(
+            CLOCK_OUT => reset_m
+        );
+end Decode_PW_Man;
+--
+
+-------------------------------------------------------------------------------
+-- Second Order Lowpass filter
+--
+--  Transfer Function:
+--
+--                    w1*w2         
+--   H(s) =  k * ----------------
+--               (s + w1)(s + w2)
+--
+-- DC Gain = k
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lpf_2_e is
+	generic (
+		k: real := 1.0;  			-- Gain multiplier
+		f1: real := 10.0;			-- First break frequency (pole)
+		f2: real := 100.0);			-- Second break frequency (pole)
+	port 	(	terminal input: electrical;
+			terminal output: electrical);
+end entity lpf_2_e;
+
+architecture simple of lpf_2_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+	quantity vin_temp : real;
+	constant w1 : real := f1*math_2_pi;
+	constant w2 : real := f2*math_2_pi;
+--	constant num : real := k;
+	constant num : real_vector := (0 => w1*w2*k);  -- 0=> is needed to give
+                                                   -- index when only a single
+                                                   -- element is used.
+	constant den : real_vector := (w1*w2, w1+w2, 1.0);
+begin
+	vin_temp == vin;   -- intermediate variable (vin) req'd for now
+	vout == vin_temp'ltf(num, den);
+end architecture simple;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- ideal one bit A/D converter
+
+LIBRARY IEEE;
+USE IEEE.math_real.ALL;
+USE IEEE.std_logic_1164.ALL;
+
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.electrical_systems.ALL;
+
+ENTITY a2d_bit IS
+  
+  GENERIC (
+    thres : real := 2.5);    -- Threshold to determine logic output
+
+  PORT (
+    TERMINAL a :     electrical;   -- analog input
+    SIGNAL   d : OUT std_logic);   -- digital (std_logic) output
+  
+END ENTITY a2d_bit;
+
+
+ARCHITECTURE ideal OF a2d_bit IS
+
+  QUANTITY vin ACROSS a;
+  
+  BEGIN  -- threshold
+-- Process needed to detect threshold crossing and assign output (d)
+    PROCESS (vin'ABOVE(thres)) IS
+      BEGIN  -- PROCESS
+      IF vin'ABOVE(thres) THEN
+         d <= '1';
+      ELSE
+         d <= '0';  
+      END IF;
+    END PROCESS;
+
+END ideal;
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Two input OR gate
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY or2 IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    in1, in2 : IN  std_logic;
+    output    : OUT std_logic);
+  
+END ENTITY or2;
+
+ARCHITECTURE ideal OF or2 IS
+BEGIN
+   output <= in1 OR in2 AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pw2ana is
+    port(
+        terminal ana_out : electrical;
+        terminal pw_in : electrical
+    );
+end pw2ana;
+
+architecture pw2ana of pw2ana is
+    -- Component declarations
+    -- Signal declarations
+    signal bus_servo : std_logic_vector(0 to 11);
+    signal XSIG010008 : std_logic;
+    signal XSIG010013 : std_logic;
+    signal XSIG010019 : std_logic;
+    signal XSIG010020 : std_logic;
+    signal XSIG010021 : std_logic;
+    signal XSIG010022 : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    counter_rudder : entity work.counter_12
+        port map(
+            enable => XSIG010022,
+            cnt => bus_servo,
+            reset => XSIG010021,
+            clk => XSIG010008
+        );
+    XCMP3 : entity work.a2d_bit(ideal)
+        port map(
+            D => XSIG010022,
+            A => pw_in
+        );
+    clk_en_rudder : entity work.clock_en(ideal)
+        generic map(
+            pw => 500ns
+        )
+        port map(
+            CLOCK_OUT => XSIG010008,
+            enable => XSIG010022
+        );
+    XCMP5 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => XSIG010022,
+            output => XSIG010013
+        );
+    XCMP8 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => XSIG010020,
+            output => XSIG010021
+        );
+    XCMP9 : entity work.inverter(ideal)
+        generic map(
+            delay => 2us
+        )
+        port map(
+            input => XSIG010022,
+            output => XSIG010019
+        );
+    or_rudder : entity work.or2(ideal)
+        port map(
+            in1 => XSIG010022,
+            in2 => XSIG010019,
+            output => XSIG010020
+        );
+    XCMP11 : entity work.d2a_nbit(behavioral)
+        generic map(
+            vmax => 4.8,
+            high_bit => 9,
+            low_bit => 0
+        )
+        port map(
+            bus_in => bus_servo,
+            ana_out => ana_out,
+            latch => XSIG010013
+        );
+end pw2ana;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : v_pulse.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/07/09
+-------------------------------------------------------------------------------
+-- Description:  Voltage Pulse Source
+--               Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created
+-- 2001/07/09  1.1         Mentor Graphics     Changed input parameters to type
+--                                             time.  Uses time2real function.
+--                                             Pulsewidth no longer includes
+--                                             rise and fall times.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_pulse is
+
+  generic (
+    initial  : voltage := 0.0;          -- initial value [Volts]
+    pulse    : voltage;                 -- pulsed value [Volts]
+    ti2p     : time    := 1ns;          -- initial to pulse [Sec]
+    tp2i     : time    := 1ns;          -- pulse to initial [Sec]
+    delay    : time    := 0ms;          -- delay time [Sec]
+    width    : time;                    -- duration of pulse [Sec]
+    period   : time;                    -- period [Sec]
+    ac_mag   : voltage := 1.0;          -- AC magnitude [Volts]
+    ac_phase : real    := 0.0);         -- AC phase [Degrees]
+
+  port (
+    terminal pos, neg : electrical);
+
+end entity v_pulse;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_pulse is
+
+-- Declare Through and Across Branch Quantities
+  quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis 
+  quantity ac_spec      : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+-- Signal used in CreateEvent process below  
+  signal   pulse_signal : voltage := initial;
+  
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+-- Note: these lines gave an error during simulation.  Had to use a
+-- function call instead.
+--  constant ri2p : real := time'pos(ti2p) * 1.0e-15;
+--  constant rp2i : real := time'pos(tp2i) * 1.0e-15;
+  
+-- Function to convert numbers of type TIME to type REAL
+  function time2real(tt : time) return real is
+  begin
+    return time'pos(tt) * 1.0e-15;
+  end time2real;
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+  constant ri2p         : real    := time2real(ti2p);
+  constant rp2i         : real    := time2real(tp2i);
+
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+    v == pulse_signal'ramp(ri2p, rp2i);  -- create rise and fall transitions
+  else
+    v   == ac_spec;                        -- used for Frequency (AC) analysis
+  end use;
+
+-- purpose: Create events to define pulse shape
+-- type   : combinational
+-- inputs : 
+-- outputs: pulse_signal
+CreateEvent : process
+begin
+  wait for delay;
+  loop
+    pulse_signal <= pulse;
+    wait for (width + ti2p);
+    pulse_signal <= initial;
+    wait for (period - width - ti2p);
+  end loop;
+end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library ieee;
+use ieee.math_real.all;
+package pwl_functions is
+
+-- This function returns the incremental value to the next element in a real vector
+	function next_increment(x : in real; xdata : in real_vector ) 
+		return real;
+	function interpolate (x,y2,y1,x2,x1 : in real) 
+		return real;
+	function extrapolate (x,y2,y1,x2,x1 : in real) 
+		return real;
+	function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector ) 
+		return real;
+end package pwl_functions;
+
+package body pwl_functions is
+	function next_increment(x : in real; xdata : in real_vector) 
+		return real is 
+		variable i : integer;
+	begin
+		i := 0;
+		while i <= xdata'right loop
+	    	if x >= xdata(i) - 6.0e-15 then   -- The value 6.0e-15 envelopes round-off error 
+			                                  -- of real-to-time conversion in calling model
+				i := i + 1;
+			else
+				return xdata(i) - xdata(i - 1);
+            end if;  
+        end loop;
+ 	    return 1.0;  -- Returns a "large number" relative to expected High-Speed time scale
+	end function next_increment;
+
+	 function interpolate (x,y2,y1,x2,x1 : in real) 
+		return real is 
+		variable m, yvalue : real;
+	 begin
+	 	assert (x1 /= x2)
+			report "interpolate: x1 cannot be equal to x2"
+			severity error;
+		assert (x >= x1) and (x <= x2) 
+			report "interpolate: x must be between x1 and x2, inclusively "
+			severity error;
+	
+		m := (y2 - y1)/(x2 - x1);
+		yvalue := y1 + m*(x - x1);
+		return yvalue;
+	end function interpolate;
+	
+	 function extrapolate (x,y2,y1,x2,x1 : in real) 
+		return real is 
+		variable m, yvalue : real;
+	begin
+		assert (x1 /= x2)
+			report "extrapolate: x1 cannot be equal to x2"
+			severity error;
+		assert (x <= x1) or (x >= x2) 
+			report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
+			severity warning;
+	
+		m := (y2 - y1)/(x2 - x1);
+		yvalue := y1 + m*(x - x1);
+		return yvalue;
+	end function extrapolate;
+
+ -- Created a new pwl_dim1_flat function that returns a constant 
+		-- value of ydata(0) if  x < xdata(0), or ydata(ydata'right) if x > xdata(xdata'right)
+
+	function pwl_dim1_flat (x : in real; xdata, ydata : in real_vector ) 
+		return real is 
+		variable xvalue, yvalue, m : real;
+                variable start, fin, mid: integer; 
+	begin
+		if x >= xdata(xdata'right) then
+			yvalue := ydata(ydata'right);
+			return yvalue;
+		end if;
+		if x <= xdata(0) then
+			yvalue := ydata(0);
+			return yvalue;
+		end if;
+                start:=0;
+                fin:=xdata'right;
+-- I assume that the valid elements are from  xdata(0) to xdata(fin), inclusive. 
+-- so fin==n-1 in C terms (where n is the size of the array). 
+		while  start <=fin  loop
+                        mid:=(start+fin)/2; 
+	                if xdata(mid) < x
+                         then start:=mid+1;
+                         else fin:=mid-1;
+                    end if;  
+                end loop; 
+                                
+                if xdata(mid) > x
+                        then mid:=mid-1; 
+                 end if; 
+                 yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));               
+		
+		return yvalue;
+	end function pwl_dim1_flat;
+end package body pwl_functions;
+
+-- Not sure the sync_tdata process is necessary. Requires the tdata set contain
+-- a larger value than the actual simulation time.
+
+--  Piece-wise linear voltage source model
+
+library IEEE; use IEEE.std_logic_1164.all;
+Library IEEE_proposed; use IEEE_proposed.electrical_systems.all; 
+use work.pwl_functions.all;
+ 
+entity v_pwl is
+generic (	
+	vdata : real_vector;  -- v-pulse data 
+	tdata : real_vector   -- time-data for v-pulse
+	);
+
+port (	
+	terminal pos, neg :  electrical
+	);
+end entity v_pwl;
+
+architecture ideal of v_pwl is
+
+QUANTITY v across i through pos TO neg;
+signal tick : std_logic := '0';  -- Sync signal for tdata "tracking"
+
+begin
+				
+sync_tdata: process is
+variable next_tick_delay : real := 0.0;  -- Time increment to the next time-point in tdata
+begin	
+	wait until domain = time_domain;
+	loop
+		next_tick_delay := next_increment(NOW,tdata);
+		tick <= (not tick) after (integer(next_tick_delay * 1.0e15) * 1 fs);
+		wait on tick;
+	end loop;
+end process sync_tdata;
+
+break on tick;	-- Forces analog solution point at all tdata time-points		
+	v == pwl_dim1_flat(NOW, tdata, vdata);
+end architecture ideal;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity plane_pos_src is
+    port(
+        terminal plane_pos : electrical;
+        terminal rudder_fb : electrical
+    );
+end plane_pos_src;
+
+architecture plane_pos_src of plane_pos_src is
+    -- Component declarations
+    -- Signal declarations
+    terminal flight_deviation : electrical;
+    terminal plane_sum_out : electrical;
+    terminal wind : electrical;
+    terminal wind_neg : electrical;
+    terminal XSIG010020 : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    sum1 : entity work.sum2_e(simple)
+        generic map(
+            k1 => 1.0
+        )
+        port map(
+            in1 => wind,
+            in2 => rudder_fb,
+            output => plane_sum_out
+        );
+    dir_out : entity work.gain_e(simple)
+        generic map(
+            k => -1.0
+        )
+        port map(
+            input => plane_sum_out,
+            output => plane_pos
+        );
+    wind_neg_gain : entity work.gain_e(simple)
+        generic map(
+            k => -1.0
+        )
+        port map(
+            input => wind,
+            output => wind_neg
+        );
+    sum2 : entity work.sum2_e(simple)
+        generic map(
+            k2 => 1.89,
+            k1 => 1.0
+        )
+        port map(
+            in1 => wind,
+            in2 => rudder_fb,
+            output => flight_deviation
+        );
+    R2 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => ELECTRICAL_REF,
+            p2 => XSIG010020
+        );
+    v3 : entity work.v_pulse(ideal)
+        generic map(
+            period => 3 sec,
+            width => 100 ms,
+            delay => 100 ms,
+            tp2i => 1 sec,
+            ti2p => 1 sec,
+            pulse => -4.8,
+            initial => 0.0
+        )
+        port map(
+            pos => XSIG010020,
+            neg => ELECTRICAL_REF
+        );
+    PWL_Wind : entity work.v_pwl(ideal)
+        generic map(
+            tdata => (0.0,100.0e-3,110.0e-3,500.0e-3,510.0e-3,800.0e-3, 810.0e-3),
+            vdata => (0.0,0.0,-2.4,-2.4,-4.7,-4.7,0.0)
+        )
+        port map(
+            pos => wind,
+            neg => ELECTRICAL_REF
+        );
+end plane_pos_src;
+--
+
+-------------------------------------------------------------------------------
+-- Integrator
+--
+--  Transfer Function:
+--
+--               k         
+--  H(s) =   ---------
+--               s 
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity integ_1_e is
+	generic (
+		k: real := 1.0;		-- Gain
+--		init: real := real'low);  -- Initial value of output
+		init: real := 0.0);  -- Initial value of output
+	port 	(terminal input: electrical;
+		terminal output: electrical);
+end entity integ_1_e;
+
+architecture simple of integ_1_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+  quantity vin_temp : real;
+begin
+  vin_temp == vin;
+--  IF domain = QUIESCENT_DOMAIN AND init /= real'low USE
+  IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE
+  	vout == init;
+  ELSE 
+	vout == k*vin_temp'INTEG;
+
+  END USE;
+
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- First Order Lowpass filter
+--
+--  Transfer Function:
+--
+--                    w1         
+--   H(s) =  k * -----------
+--                  s + w1
+--
+-- DC Gain = k
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lpf_1_e is
+  generic (
+    fp   : real;            -- pole freq in Hertz
+    gain : real := 1.0);    -- filter gain
+
+    port 	(	terminal input: electrical;
+			terminal output: electrical);
+end entity lpf_1_e;
+
+architecture simple of lpf_1_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+  constant wp : real := math_2_pi*fp;    
+  constant num : real_vector := (0 => wp*gain);  -- 0=> is needed to give
+                                                   -- index when only a single
+                                                   -- element is used.
+  constant den : real_vector := (wp, 1.0);
+  quantity vin_temp : real;  
+
+begin
+	vin_temp == vin;   -- intermediate variable (vin) req'd for now
+	vout == vin_temp'ltf(num, den);
+end architecture simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity hcl is
+    port(
+        terminal output : electrical;
+        terminal plane_pos : electrical
+    );
+end hcl;
+
+architecture hcl of hcl is
+    -- Component declarations
+    -- Signal declarations
+    terminal hcl_err_in : electrical;
+    terminal heading : electrical;
+    terminal XSIG010001 : electrical;
+    terminal XSIG010002 : electrical;
+    terminal XSIG010003 : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    prop_gain : entity work.gain_e(simple)
+        generic map(
+            k => 1.0
+        )
+        port map(
+            input => hcl_err_in,
+            output => XSIG010002
+        );
+    integ : entity work.integ_1_e(simple)
+        generic map(
+            init => 0.0,
+            k => 0.1
+        )
+        port map(
+            input => hcl_err_in,
+            output => XSIG010003
+        );
+    lowpass : entity work.lpf_1_e(simple)
+        generic map(
+            fp => 4.0
+        )
+        port map(
+            input => XSIG010001,
+            output => output
+        );
+    sum2 : entity work.sum2_e(simple)
+        port map(
+            in1 => XSIG010002,
+            in2 => XSIG010003,
+            output => XSIG010001
+        );
+    set_src : entity work.v_constant(ideal)
+        generic map(
+            level => 0.0
+        )
+        port map(
+            pos => heading,
+            neg => ELECTRICAL_REF
+        );
+    sum1 : entity work.sum2_e(simple)
+        port map(
+            in1 => heading,
+            in2 => plane_pos,
+            output => hcl_err_in
+        );
+end hcl;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CS5_HCL is
+end tb_CS5_HCL;
+
+architecture TB_CS5_HCL of tb_CS5_HCL is
+    -- Component declarations
+    -- Signal declarations
+    signal bitstream1 : std_logic;
+    signal bitstream2 : std_logic;
+    terminal ch1_in : electrical;
+    terminal ch1_pw_out : electrical;
+    terminal ch2_in : electrical;
+    terminal ch2_pw_out : electrical;
+    terminal gear_hrn_out : translational;
+    terminal gear_in : rotational_v;
+    terminal gear_out : rotational;
+    terminal mtr_in : electrical;
+    terminal plane_dir : electrical;
+    terminal prop_in : electrical;
+    terminal rot2v_out : electrical;
+    terminal rudder : rotational;
+    terminal rudder_fb : electrical;
+    terminal rudder_hrn_in : translational;
+    terminal servo_fltr_in : electrical;
+    terminal servo_in : electrical;
+    terminal XSIG010018 : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    rudder_servo1 : entity work.rudder_servo
+        port map(
+            servo_out => mtr_in,
+            servo_in => servo_in,
+            pos_fb => rot2v_out
+        );
+    gear1 : entity work.gear_rv_r(ideal)
+        generic map(
+            ratio => 0.01
+        )
+        port map(
+            rotv1 => gear_in,
+            rot2 => gear_out
+        );
+    potentiometer1 : entity work.rot2v(bhv)
+        generic map(
+            k => 1.0
+        )
+        port map(
+            output => rot2v_out,
+            input => gear_out
+        );
+    gear_horn : entity work.horn_r2t(bhv)
+        port map(
+            theta => gear_out,
+            pos => gear_hrn_out
+        );
+    rudder_horn : entity work.horn_t2r(bhv)
+        port map(
+            theta => rudder,
+            pos => rudder_hrn_in
+        );
+    motor1 : entity work.DC_Motor(basic)
+        generic map(
+            j => 168.0e-9,
+            d => 5.63e-6,
+            l => 2.03e-3,
+            kt => 3.43e-3,
+            r_wind => 2.2
+        )
+        port map(
+            p1 => mtr_in,
+            p2 => ELECTRICAL_REF,
+            shaft_rotv => gear_in
+        );
+    stop1 : entity work.stop_r(ideal)
+        generic map(
+            ang_min => -1.05,
+            ang_max => 1.05,
+            k_stop => 1.0e6,
+            damp_stop => 1.0e2
+        )
+        port map(
+            ang1 => gear_out,
+            ang2 => ROTATIONAL_REF
+        );
+    \linkage\ : entity work.tran_linkage(a1)
+        port map(
+            p2 => rudder_hrn_in,
+            p1 => gear_hrn_out
+        );
+    rudder_1 : entity work.rudder(bhv)
+        generic map(
+            k => 0.2
+        )
+        port map(
+            rot => rudder
+        );
+    XCMP6 : entity work.v_constant(ideal)
+        generic map(
+            level => 5.0
+        )
+        port map(
+            pos => XSIG010018,
+            neg => ELECTRICAL_REF
+        );
+    Throttle : entity work.stick(ideal)
+        generic map(
+            freq => 1.0,
+            amplitude => 2.397,
+            phase => 0.0,
+            offset => 2.397
+        )
+        port map(
+            v_out => ch1_in
+        );
+    rf_tx_rx : entity work.rf_xmtr_rcvr(behavioral)
+        port map(
+            tdm_in => bitstream1,
+            tdm_out => bitstream2
+        );
+    Digitize_Encode1 : entity work.Digitize_Encode_Man
+        port map(
+            ch2_in => ch2_in,
+            ch1_in => ch1_in,
+            tdm_out => bitstream1
+        );
+    Decode_PW_Man3 : entity work.Decode_PW_Man
+        port map(
+            bit_stream_in => bitstream2,
+            ch2_pw => ch2_pw_out,
+            ch1_pw => ch1_pw_out,
+            power => XSIG010018
+        );
+    lpf2 : entity work.lpf_2_e(simple)
+        generic map(
+            f1 => 10.0,
+            f2 => 10.0
+        )
+        port map(
+            input => servo_fltr_in,
+            output => servo_in
+        );
+    pw2ana_throttle : entity work.pw2ana
+        port map(
+            ana_out => prop_in,
+            pw_in => ch1_pw_out
+        );
+    pw2ana_rudder : entity work.pw2ana
+        port map(
+            ana_out => servo_fltr_in,
+            pw_in => ch2_pw_out
+        );
+    rot2v_rudder : entity work.rot2v(bhv)
+        generic map(
+            k => 4.57
+        )
+        port map(
+            output => rudder_fb,
+            input => rudder
+        );
+    plane11 : entity work.plane_pos_src
+        port map(
+            plane_pos => plane_dir,
+            rudder_fb => rudder_fb
+        );
+    hcl_1 : entity work.hcl
+        port map(
+            output => ch2_in,
+            plane_pos => plane_dir
+        );
+end TB_CS5_HCL;
+--
+
+
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd
new file mode 100644
index 0000000..67db1b9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd
@@ -0,0 +1,990 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : DC_Motor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+  generic (
+    r_wind : resistance;                -- Motor winding resistance [Ohm]
+    kt     : real;                      -- Torque coefficient [N*m/Amp]
+    l      : inductance;                -- Winding inductance [Henrys]
+    d      : real;                      -- Damping coefficient [N*m/(rad/sec)]
+    j      : mmoment_i);                -- Moment of inertia [kg*meter**2]
+
+  port (terminal p1, p2 : electrical;
+        terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations:  V = Kt*W + I*Rwind + L*dI/dt
+--                   T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+  quantity v across i through p1 to p2;
+  quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+  torq == -1.0*kt*i + d*w + j*w'dot;
+  v  == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Constant Voltage Source (Includes Frequency Domain settings)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY v_constant IS
+
+-- Initialize parameters
+  GENERIC (
+    level      : VOLTAGE;		-- Constant voltage value (V)
+    ac_mag     : VOLTAGE := 1.0;	-- AC magnitude (V)
+    ac_phase   : real := 0.0);		-- AC phase (degrees)
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL pos, neg : ELECTRICAL);
+
+END ENTITY v_constant;
+
+-- Ideal Architecture (I = constant)
+ARCHITECTURE ideal OF v_constant IS
+  
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH pos TO neg;
+-- Declare quantity in frequency domain for AC analysis  
+  QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+
+  IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
+	v == level;
+  ELSE	
+  	v == ac_spec;  -- used for Frequency (AC) analysis
+  END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-- C:\Rehan\Cs5\design_definition\hdl\vhdl\switch_dig_log.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity switch_dig_log is
+generic
+(
+	trans_time : real := 1.0e-9;
+	r_closed : resistance := 1.0e-3;
+	r_open : resistance := 1.0e6
+);
+port
+(
+      terminal p1 : electrical ;
+      sw_state : in std_logic ;
+      terminal p2 : electrical 
+);
+
+begin
+
+end switch_dig_log ;
+
+-----------------------------------------------------------------------------------------
+architecture linear of switch_dig_log is
+  signal r_sig : resistance := r_open;   -- create internal signal for CreateState process
+  quantity v across i through p1 to p2;
+  quantity r  : resistance;
+
+begin
+  -- purpose: Detect Switch state and assign resistance value to r_sig
+  -- type   : combinational
+  -- inputs : sw_state
+  -- outputs: r_sig
+  DetectState: process (sw_state)
+  begin  -- process DetectState
+    if (sw_state'event and sw_state = '0') then
+      r_sig <= r_open;
+    elsif (sw_state'event and sw_state = '1') then
+      r_sig <= r_closed;
+    end if;
+  end process DetectState;
+
+-- Characteristic equations
+  r == r_sig'ramp(trans_time, trans_time);
+  v == r*i;
+end architecture linear;
+
+-------------------------------------------------------------------------------------------
+architecture log of switch_dig_log is
+  constant log10_r_open : real := log10(r_open);
+  constant log10_r_closed : real := log10(r_closed);
+  signal log10_r_sig : resistance := log10_r_open;   -- create internal signal for CreateState process
+  quantity v across i through p1 to p2;
+  quantity r : resistance;
+  quantity log10_r  : real;
+
+begin
+  -- purpose: Detect Switch state and assign resistance value to r_sig
+  -- type   : combinational
+  -- inputs : sw_state
+  -- outputs: r_sig
+  DetectState: process (sw_state)
+  begin  -- process DetectState
+    if (sw_state'event and sw_state = '0') then
+      log10_r_sig <= log10_r_open;
+    elsif (sw_state'event and sw_state = '1') then
+      log10_r_sig <= log10_r_closed;
+    end if;
+  end process DetectState;
+
+-- Characteristic equations
+  log10_r == log10_r_sig'ramp(trans_time, trans_time);
+  r == 10**log10_r;
+  v == r*i;
+end architecture log;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : opamp.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: 3-pin OpAmp model with behavioral architecture
+--              Uses Q'LTF function to define open-loop response
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity opamp is
+-- Initialize parameters
+  generic (rin   : resistance := 1.0e6;    -- Input resistance [Ohms]
+           rout  : resistance := 100.0;    -- Output resistance (Ohms]
+           avol  : real       := 100.0e3;  -- Open loop gain
+           f_0dB : real       := 1.0e6     -- Unity Gain Frequency [Hz]
+           );
+-- Define ports as electrical terminals
+  port (
+    terminal in_pos, in_neg, output : electrical);
+
+end entity opamp;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Characteristics modeled:
+--      1. Open loop gain
+--      2. Frequency characteristics (single pole response) 
+--      3. Input and output resistance
+-- Uses Q'Ltf function to create open loop gain and roll off
+-------------------------------------------------------------------------------
+architecture basic of opamp is
+  -- Declare constants
+  constant f_3db : real        := f_0db / avol;     -- -3dB frequency
+  constant w_3dB : real        := math_2_pi*f_3dB;  -- -3dB freq in radians
+  -- Numerator and denominator for Q'LTF function
+  constant num   : real_vector := (0 => avol);
+  constant den   : real_vector := (1.0, 1.0/w_3dB);
+  -- Declare input and output quantities
+  quantity v_in across i_in through in_pos to in_neg;
+  quantity v_out across i_out through output;
+
+begin  -- ARCHITECTURE basic
+
+  i_in  == v_in / rin;                       -- input current
+  v_out == v_in'ltf(num, den) + i_out*rout;  -- output voltage
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical Resistor Model
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY resistor IS 
+
+-- Initialize parameters
+  GENERIC (
+    res : RESISTANCE);                 -- resistance (no initial value)
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL p1, p2 : ELECTRICAL);
+
+END ENTITY resistor;
+
+-- Ideal Architecture (V = I*R)
+ARCHITECTURE ideal OF resistor IS
+  
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH p1 TO p2;
+
+BEGIN
+  
+-- Characteristic equations
+  v == i*res;                       
+
+END ARCHITECTURE ideal;
+
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : comparator_d.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/08/03
+-- Last update: 2001/08/03
+-------------------------------------------------------------------------------
+-- Description: Voltage comparator with digital output
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/08/03  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use IEEE natures and packages
+library IEEE;
+use ieee.std_logic_1164.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+use IEEE_proposed.ENERGY_SYSTEMS.all;
+
+entity comparator_d is
+
+  port (
+    terminal in_pos : electrical;
+    terminal in_neg : electrical;
+    signal output : out std_logic := '1'      -- Digital output
+    );
+
+end comparator_d;
+-------------------------------------------------------------------------------
+-- Behavioral architecture
+-------------------------------------------------------------------------------
+architecture behavioral of comparator_d is
+  quantity Vin across in_pos;
+  quantity Vref across in_neg;
+
+begin  -- behavioral
+
+  -- purpose: Detect threshold crossing and assign event on output
+  -- type   : combinational
+  -- inputs : vin'above(thres)
+  -- outputs: pulse_signal  
+  process (Vin'above(Vref)) is
+  begin  -- PROCESS
+    if Vin'above(Vref) then
+      output <= '1' after 1us;
+    else
+      output <= '0' after 1us;
+    end if;
+  end process;
+
+end behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : v_pulse.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/07/09
+-------------------------------------------------------------------------------
+-- Description:  Voltage Pulse Source
+--               Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created
+-- 2001/07/09  1.1         Mentor Graphics     Changed input parameters to type
+--                                             time.  Uses time2real function.
+--                                             Pulsewidth no longer includes
+--                                             rise and fall times.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_pulse is
+
+  generic (
+    initial  : voltage := 0.0;          -- initial value [Volts]
+    pulse    : voltage;                 -- pulsed value [Volts]
+    ti2p     : time    := 1ns;          -- initial to pulse [Sec]
+    tp2i     : time    := 1ns;          -- pulse to initial [Sec]
+    delay    : time    := 0ms;          -- delay time [Sec]
+    width    : time;                    -- duration of pulse [Sec]
+    period   : time;                    -- period [Sec]
+    ac_mag   : voltage := 1.0;          -- AC magnitude [Volts]
+    ac_phase : real    := 0.0);         -- AC phase [Degrees]
+
+  port (
+    terminal pos, neg : electrical);
+
+end entity v_pulse;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_pulse is
+
+-- Declare Through and Across Branch Quantities
+  quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis 
+  quantity ac_spec      : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+-- Signal used in CreateEvent process below  
+  signal   pulse_signal : voltage := initial;
+  
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+-- Note: these lines gave an error during simulation.  Had to use a
+-- function call instead.
+--  constant ri2p : real := time'pos(ti2p) * 1.0e-15;
+--  constant rp2i : real := time'pos(tp2i) * 1.0e-15;
+  
+-- Function to convert numbers of type TIME to type REAL
+  function time2real(tt : time) return real is
+  begin
+    return time'pos(tt) * 1.0e-15;
+  end time2real;
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+  constant ri2p         : real    := time2real(ti2p);
+  constant rp2i         : real    := time2real(tp2i);
+
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+    v == pulse_signal'ramp(ri2p, rp2i);  -- create rise and fall transitions
+  else
+    v   == ac_spec;                        -- used for Frequency (AC) analysis
+  end use;
+
+-- purpose: Create events to define pulse shape
+-- type   : combinational
+-- inputs : 
+-- outputs: pulse_signal
+CreateEvent : process
+begin
+  wait for delay;
+  loop
+    pulse_signal <= pulse;
+    wait for (width + ti2p);
+    pulse_signal <= initial;
+    wait for (period - width - ti2p);
+  end loop;
+end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pwm_mac is
+    port(
+        terminal inp : electrical;
+        terminal inm : electrical;
+        dig_out : out std_logic
+    );
+end pwm_mac;
+
+architecture pwm_mac of pwm_mac is
+    -- Component declarations
+    -- Signal declarations
+    terminal cmp_in : electrical;
+    terminal plse_in : electrical;
+    terminal XSIG010002 : electrical;
+    terminal XSIG010003 : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    U1 : entity work.opamp(basic)
+        port map(
+            in_neg => XSIG010002,
+            in_pos => inm,
+            output => cmp_in
+        );
+    R1 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => XSIG010002,
+            p2 => cmp_in
+        );
+    v2 : entity work.v_constant(ideal)
+        generic map(
+            level => 0.0
+        )
+        port map(
+            pos => XSIG010003,
+            neg => ELECTRICAL_REF
+        );
+    R2 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => plse_in,
+            p2 => XSIG010002
+        );
+    R3 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => inp,
+            p2 => XSIG010002
+        );
+    XCMP4 : entity work.comparator_d(behavioral)
+        port map(
+            output => dig_out,
+            in_pos => XSIG010003,
+            in_neg => cmp_in
+        );
+    v9 : entity work.v_pulse(ideal)
+        generic map(
+            initial => -4.7,
+            pulse => 4.7,
+            ti2p => 200 us,
+            tp2i => 200 us,
+            delay => 1 us,
+            width => 1 us,
+            period => 405 us
+        )
+        port map(
+            pos => plse_in,
+            neg => ELECTRICAL_REF
+        );
+end pwm_mac;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : prop_pwl.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Propeller Load (Rotational_V domain)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.math_real.all;
+package pwl_functions is
+function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector ) 
+	return real;
+function interpolate (x,y2,y1,x2,x1 : in real) 
+	return real;
+function extrapolate (x,y2,y1,x2,x1 : in real) 
+	return real;
+end package pwl_functions;
+
+package body pwl_functions is
+	 function interpolate (x,y2,y1,x2,x1 : in real) 
+		return real is 
+		variable m, yvalue : real;
+	 begin
+	 	assert (x1 /= x2)
+			report "interpolate: x1 cannot be equal to x2"
+			severity error;
+		assert (x >= x1) and (x <= x2) 
+			report "interpolate: x must be between x1 and x2, inclusively "
+			severity error;
+	
+		m := (y2 - y1)/(x2 - x1);
+		yvalue := y1 + m*(x - x1);
+		return yvalue;
+	end function interpolate;
+	
+	 function extrapolate (x,y2,y1,x2,x1 : in real) 
+		return real is 
+		variable m, yvalue : real;
+	begin
+		assert (x1 /= x2)
+			report "extrapolate: x1 cannot be equal to x2"
+			severity error;
+		assert (x <= x1) or (x >= x2) 
+			report "extrapolate: x is within x1, x2 bounds; interpolation will be performed"
+			severity warning;
+	
+		m := (y2 - y1)/(x2 - x1);
+		yvalue := y1 + m*(x - x1);
+		return yvalue;
+	end function extrapolate;
+
+--  Created a new pwl_dim1_extrap function that returns extrapolated yvalue for "out-of-range" x value.
+
+	function pwl_dim1_extrap (x : in real; xdata, ydata : in real_vector ) 
+		return real is 
+		variable xvalue, yvalue, m : real;
+                variable start, fin, mid: integer; 
+	begin
+		if x <= xdata(0) then
+			yvalue := extrapolate(x,ydata(1),ydata(0),xdata(1),xdata(0));
+			return yvalue;
+		end if;
+		if x >= xdata(xdata'right) then
+			yvalue := extrapolate(x,ydata(ydata'right),ydata(ydata'right-1),xdata(xdata'right),xdata(xdata'right-1));
+			return yvalue;
+		end if;
+                start:=0;
+                fin:=xdata'right;
+-- I assume that the valid elements are from  xdata(0) to xdata(fin), inclusive. 
+-- so fin==n-1 in C terms (where n is the size of the array). 
+		while  start <=fin  loop
+                        mid:=(start+fin)/2; 
+	                if xdata(mid) < x
+                         then start:=mid+1;
+                         else fin:=mid-1;
+                    end if;  
+                end loop; 
+                                
+                if xdata(mid) > x
+                        then mid:=mid-1; 
+                 end if; 
+                 yvalue := interpolate(x,ydata(mid+1),ydata(mid),xdata(mid+1),xdata(mid));               
+		
+		return yvalue;
+	end function pwl_dim1_extrap;
+end package body pwl_functions;
+
+library IEEE_proposed; use IEEE_proposed.mechanical_systems.all;
+library ieee; use ieee.math_real.all;
+use work.pwl_functions.all;
+
+entity prop_pwl is
+generic (	
+	ydata : real_vector;  -- torque data 
+	xdata : real_vector   -- velocity data
+	);
+  port (terminal shaft1 : rotational_v);
+end entity prop_pwl;
+
+architecture ideal of prop_pwl is
+	quantity w across torq through shaft1 to rotational_v_ref;
+begin				
+	torq == pwl_dim1_extrap(w, xdata, ydata);
+end architecture ideal;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : diode_pwl.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Diode model with ideal architecture
+--              Currently no Generics due to bug in DV 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
+use IEEE_proposed.energy_systems.all;
+
+ENTITY diode_pwl IS
+	GENERIC (
+		ron : real;	-- equivalent series resistance
+		roff : real);	-- leakage resistance
+	PORT (
+		TERMINAL 	p,	-- positive pin
+				m : electrical); -- minus pin
+END ENTITY diode_pwl;
+
+ARCHITECTURE simple OF diode_pwl IS
+	QUANTITY v across i through p TO m;
+
+BEGIN			-- simple ARCHITECTURE
+	if v'Above(0.0) use
+		i == v/ron;
+	elsif not v'Above(0.0) use
+		i == v/roff;
+	else
+		i == 0.0;
+	end use;
+	break on v'Above(0.0);
+END ARCHITECTURE simple;
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical sinusoidal voltage source (v_sine.vhd)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+
+ENTITY v_sine IS
+  
+-- Initialize parameters
+  GENERIC (
+    freq      : real;                     -- frequency,       [Hertz]
+    amplitude : real;                     -- amplitude,       [Volt]
+    phase     : real := 0.0;              -- initial phase,   [Degree]
+    offset    : real := 0.0;              -- DC value,        [Volt]
+    df        : real := 0.0;              -- damping factor,  [1/second]
+    ac_mag    : real := 1.0;              -- AC magnitude,    [Volt]
+    ac_phase  : real := 0.0);             -- AC phase,        [Degree]
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL pos, neg : ELECTRICAL);
+
+END ENTITY v_sine;
+
+-- Ideal Architecture
+ARCHITECTURE ideal OF v_sine IS
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH pos TO neg;
+-- Declare Quantity for Phase in radians (calculated below)
+  QUANTITY phase_rad : real;          
+-- Declare Quantity in frequency domain for AC analysis
+  QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN  
+-- Convert phase to radians
+  phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+  
+  IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
+    v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+  ELSE 
+    v == ac_spec;    -- used for Frequency (AC) analysis
+  END USE;
+
+END ARCHITECTURE ideal;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CS5_Prop is
+end tb_CS5_Prop;
+
+architecture TB_CS5_Prop of tb_CS5_Prop is
+    -- Component declarations
+    -- Signal declarations
+    terminal prop : rotational_v;
+    terminal prop_amp_in : electrical;
+    terminal prop_mtr_in : electrical;
+    terminal prop_pwr : electrical;
+    signal pwm_out : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    motor2 : entity work.DC_Motor(basic)
+        generic map(
+            kt => 30.1e-3,
+            l => 40.0e-6,
+            d => 5.63e-12,
+            j => 315.0e-6,
+            r_wind => 0.16
+        )
+        port map(
+            p1 => prop_mtr_in,
+            p2 => ELECTRICAL_REF,
+            shaft_rotv => prop
+        );
+    v4 : entity work.v_constant(ideal)
+        generic map(
+            level => 42.0
+        )
+        port map(
+            pos => prop_pwr,
+            neg => ELECTRICAL_REF
+        );
+    sw2 : entity work.switch_dig_log
+        port map(
+            sw_state => pwm_out,
+            p2 => prop_mtr_in,
+            p1 => prop_pwr
+        );
+    pwm1 : entity work.pwm_mac
+        port map(
+            inp => prop_amp_in,
+            dig_out => pwm_out,
+            inm => ELECTRICAL_REF
+        );
+    XCMP37 : entity work.prop_pwl(ideal)
+        generic map(
+            ydata => (0.233, 0.2865, 0.347, 0.4138, 0.485, 0.563, 0.645, 0.735, 0.830, 0.93, 1.08),
+            xdata => (471.2, 523.6, 576.0, 628.3, 680.7, 733.0, 785.4, 837.7, 890.0, 942.5, 994.8)
+        )
+        port map(
+            shaft1 => prop
+        );
+    D4 : entity work.diode_pwl(simple)
+        generic map(
+            ron => 0.001,
+            roff => 100.0e3
+        )
+        port map(
+            p => ELECTRICAL_REF,
+            m => prop_mtr_in
+        );
+    v8 : entity work.v_sine(ideal)
+        generic map(
+            freq => 1.0,
+            amplitude => 2.3,
+            phase => 0.0,
+            offset => 2.3
+        )
+        port map(
+            pos => prop_amp_in,
+            neg => ELECTRICAL_REF
+        );
+end TB_CS5_Prop;
+--
+
+
+
+
+
+
+
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd
new file mode 100644
index 0000000..c520bf9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd
@@ -0,0 +1,1974 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity sum2_e is
+	generic (k1, k2: real := 1.0);  -- Gain multipliers
+	port 	(	terminal in1, in2: electrical;
+			terminal output: electrical);
+end entity sum2_e;
+
+architecture simple of sum2_e is
+  QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
+  QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k1*vin1 + k2*vin2;
+end architecture simple;
+--
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity gain_e is
+	generic (
+		k: REAL := 1.0);  -- Gain multiplier
+	port 	(	terminal input : electrical;
+			terminal output: electrical);
+end entity gain_e;
+
+architecture simple of gain_e is
+
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+begin
+	vout == k*vin;
+end architecture simple;
+--
+
+-------------------------------------------------------------------------------
+-- S-Domain Limiter Model
+--
+-------------------------------------------------------------------------------
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+entity limiter_2_e is
+	generic (
+		limit_high : real := 4.8;	-- upper limit
+		limit_low : real := -4.8); 	-- lower limit
+	port (
+		terminal input: electrical;
+		terminal output: electrical);					
+end entity limiter_2_e;
+
+architecture simple of limiter_2_e is
+  	QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  	QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+	constant slope : real := 1.0e-4;
+begin
+	if vin > limit_high use	-- Upper limit exceeded, so limit input signal
+		vout == limit_high + slope*(vin - limit_high);
+	elsif vin < limit_low use	-- Lower limit exceeded, so limit input signal
+		vout == limit_low + slope*(vin - limit_low);
+	else		-- No limit exceeded, so pass input signal as is
+		vout == vin;
+	end use;
+	break on vin'above(limit_high), vin'above(limit_low);
+end architecture simple;
+
+--
+
+-------------------------------------------------------------------------------
+-- Lead-Lag Filter
+--
+--  Transfer Function:
+--
+--                  (s + w1)         
+--    H(s) =  k *  ----------
+--                  (s + w2)
+--
+-- DC Gain = k*w1/w2
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+library IEEE;
+use ieee.math_real.all;
+
+entity lead_lag_e is
+	generic (
+		k: real := 1.0;  			-- Gain multiplier
+		f1: real := 10.0;			-- First break frequency (zero)
+		f2: real := 100.0);		-- Second break frequency (pole)
+	port 	(	terminal input: electrical;
+			terminal output: electrical);
+end entity lead_lag_e;
+
+architecture simple of lead_lag_e is
+  QUANTITY vin ACROSS input TO ELECTRICAL_REF;
+  QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
+
+	quantity vin_temp : real;
+	constant w1 : real := f1*math_2_pi;
+	constant w2 : real := f2*math_2_pi;
+	constant num : real_vector := (w1, 1.0);                                                    
+	constant den : real_vector := (w2, 1.0);
+begin
+	vin_temp == vin;
+	vout == k*vin_temp'ltf(num, den);
+end architecture simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder_servo is
+    port(
+        terminal servo_in : electrical;
+        terminal pos_fb : electrical;
+        terminal servo_out : electrical
+    );
+end rudder_servo;
+
+architecture rudder_servo of rudder_servo is
+    -- Component declarations
+    -- Signal declarations
+    terminal error : electrical;
+    terminal ll_in : electrical;
+    terminal ll_out : electrical;
+    terminal summer_fb : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    summer : entity work.sum2_e(simple)
+        port map(
+            in1 => servo_in,
+            in2 => summer_fb,
+            output => error
+        );
+    forward_gain : entity work.gain_e(simple)
+        generic map(
+            k => 100.0
+        )
+        port map(
+            input => error,
+            output => ll_in
+        );
+    fb_gain : entity work.gain_e(simple)
+        generic map(
+            k => -4.57
+        )
+        port map(
+            input => pos_fb,
+            output => summer_fb
+        );
+    servo_limiter : entity work.limiter_2_e(simple)
+      generic map(
+            limit_high => 4.8,
+            limit_low => -4.8
+        )
+        port map(
+            input => ll_out,
+            output => servo_out
+        );
+    lead_lag : entity work.lead_lag_e(simple)
+        generic map(
+            k => 400.0,
+            f1 => 5.0,
+            f2 => 2000.0
+        )
+        port map(
+            input => ll_in,
+            output => ll_out
+        );
+end rudder_servo;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : gear_rv_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2002/05/21
+-------------------------------------------------------------------------------
+-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/10/10  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity gear_rv_r is
+
+  generic(
+    ratio : real := 1.0);   -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
+                            -- Note: can be negative, if shaft polarity changes
+
+  port ( terminal rotv1 : rotational_v;
+  		terminal rot2 : rotational);
+
+end entity gear_rv_r;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of gear_rv_r is
+
+  quantity w1 across torq_vel through rotv1 to rotational_v_ref;
+--  quantity w2 across torq2 through rotv2 to rotational_v_ref;
+  quantity theta across torq_ang through rot2 to rotational_ref;
+
+begin
+
+--  w2  == w1*ratio;
+  theta == ratio*w1'integ;
+  torq_vel == -1.0*torq_ang*ratio;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Rotational to Electrical Converter
+--
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity rot2v is
+  
+  generic (
+    k : real := 1.0);                -- optional gain
+
+  port (
+    terminal input   : rotational;  -- input terminal
+    terminal output    : electrical);   -- output terminal
+  
+end entity rot2v ;
+
+architecture bhv of rot2v is
+quantity rot_in across input to rotational_ref;     -- Converter's input branch
+quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
+
+  begin  -- bhv
+   v_out ==  k*rot_in; 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  tran =   R*sin(rot) 
+--
+-- Where pos = output translational position,
+-- R = horn radius, 
+-- theta = input rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_r2t is
+  
+  generic (
+    R   : real := 1.0);            		-- horn radius
+
+  port (
+    terminal theta    : ROTATIONAL;   	-- input angular position port
+    terminal pos   : TRANSLATIONAL);  	-- output translational position port
+     
+end entity horn_r2t;
+
+architecture bhv of horn_r2t is
+
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+
+  begin			-- bhv
+   tran == R*sin(rot);		-- Convert angle in to translational out
+   tran_frc == -rot_tq/R;	-- Convert torque in to force out 
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Control Horn for Rudder Control (mechanical implementation)
+--
+--  Transfer Function:
+--                            
+--  theta =   arcsin(pos/R) 
+--
+-- Where pos = input translational position,
+-- R = horn radius, 
+-- theta = output rotational angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity horn_t2r is
+  
+  generic (
+    R   : real := 1.0);            -- Rudder horn radius
+
+  port (
+    terminal pos    : translational;   -- input translational position port
+    terminal theta   : rotational);  -- output angular position port
+     
+end entity horn_t2r ;
+
+architecture bhv of horn_t2r is
+
+  QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
+  QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
+
+  begin  -- bhv
+   rot == arcsin(tran/R);	-- Convert translational to angle
+   rot_tq == -tran_frc*R;	-- Convert force to torque
+   
+end bhv;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : DC_Motor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Basic DC Motor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity DC_Motor is
+
+  generic (
+    r_wind : resistance;                -- Motor winding resistance [Ohm]
+    kt     : real;                      -- Torque coefficient [N*m/Amp]
+    l      : inductance;                -- Winding inductance [Henrys]
+    d      : real;                      -- Damping coefficient [N*m/(rad/sec)]
+    j      : mmoment_i);                -- Moment of inertia [kg*meter**2]
+
+  port (terminal p1, p2 : electrical;
+        terminal shaft_rotv : rotational_v);
+
+end entity DC_Motor;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Motor equations:  V = Kt*W + I*Rwind + L*dI/dt
+--                   T = -Kt*I + D*W + J*dW/dt
+-------------------------------------------------------------------------------
+architecture basic of DC_Motor is
+
+  quantity v across i through p1 to p2;
+  quantity w across torq through shaft_rotv to rotational_v_ref;
+
+begin
+
+  torq == -1.0*kt*i + d*w + j*w'dot;
+  v  == kt*w + i*r_wind + l*i'dot;
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : stop_r.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/10/10
+-- Last update: 2001/10/10
+-------------------------------------------------------------------------------
+-- Description: Mechanical Hard Stop (ROTATIONAL domain)
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.MECHANICAL_SYSTEMS.all;
+
+entity stop_r is
+
+  generic (
+    k_stop    : real;
+--    ang_max   : angle;
+--    ang_min   : angle := 0.0;
+	ang_max   : real;
+    ang_min   : real := 0.0;
+    damp_stop : real  := 0.000000001
+    );
+
+  port ( terminal ang1, ang2 : rotational);
+
+end entity stop_r;
+
+architecture ideal of stop_r is
+
+  quantity velocity : velocity;
+  quantity ang across trq through ang1 to ang2;
+
+begin
+
+  velocity == ang'dot;
+
+  if ang'above(ang_max) use
+    trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
+  elsif ang'above(ang_min) use
+    trq   == 0.0;
+  else
+    trq   == k_stop * (ang - ang_min) + (damp_stop * velocity);
+  end use;
+
+break on ang'above(ang_min), ang'above(ang_max);
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+library IEEE;
+use IEEE.std_logic_arith.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tran_linkage is
+port
+(
+      terminal p1, p2 : translational
+);
+
+begin
+
+end tran_linkage;
+
+architecture a1 of tran_linkage is
+
+  QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
+  QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
+
+begin
+
+   pos_2 == pos_1;		-- Pass position 
+   frc_2 == -frc_1;	-- Pass force
+
+end;
+--
+
+-------------------------------------------------------------------------------
+-- Rudder Model (Rotational Spring)
+--
+--  Transfer Function:
+--                            
+--  torq =   -k*(theta - theta_0)
+--
+-- Where theta = input rotational angle,
+-- torq = output rotational angle,
+-- theta_0 = reference angle
+-------------------------------------------------------------------------------
+
+-- Use IEEE_proposed instead of disciplines
+library IEEE;
+use ieee.math_real.all;
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity rudder is
+  
+  generic (
+    k   : real := 1.0;            -- Spring constant
+	theta_0 : real := 0.0);
+
+  port (
+    terminal rot    : rotational);   -- input rotational angle
+     
+end entity rudder;
+
+architecture bhv of rudder is
+
+  QUANTITY theta across torq through rot TO ROTATIONAL_REF;
+
+  begin  -- bhv
+
+   torq == k*(theta - theta_0);	-- Convert force to torque
+   
+end bhv;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.math_real.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity switch_dig_log is
+generic
+(
+	trans_time : real := 1.0e-9;
+	r_closed : resistance := 1.0e-3;
+	r_open : resistance := 1.0e6
+);
+port
+(
+      terminal p1 : electrical ;
+      sw_state : in std_logic ;
+      terminal p2 : electrical 
+);
+
+begin
+
+end switch_dig_log ;
+
+-----------------------------------------------------------------------------------------
+architecture linear of switch_dig_log is
+  signal r_sig : resistance := r_open;   -- create internal signal for CreateState process
+  quantity v across i through p1 to p2;
+  quantity r  : resistance;
+
+begin
+  -- purpose: Detect Switch state and assign resistance value to r_sig
+  -- type   : combinational
+  -- inputs : sw_state
+  -- outputs: r_sig
+  DetectState: process (sw_state)
+  begin  -- process DetectState
+    if (sw_state'event and sw_state = '0') then
+      r_sig <= r_open;
+    elsif (sw_state'event and sw_state = '1') then
+      r_sig <= r_closed;
+    end if;
+  end process DetectState;
+
+-- Characteristic equations
+  r == r_sig'ramp(trans_time, trans_time);
+  v == r*i;
+end architecture linear;
+
+-------------------------------------------------------------------------------------------
+architecture log of switch_dig_log is
+  constant log10_r_open : real := log10(r_open);
+  constant log10_r_closed : real := log10(r_closed);
+  signal log10_r_sig : resistance := log10_r_open;   -- create internal signal for CreateState process
+  quantity v across i through p1 to p2;
+  quantity r : resistance;
+  quantity log10_r  : real;
+
+begin
+  -- purpose: Detect Switch state and assign resistance value to r_sig
+  -- type   : combinational
+  -- inputs : sw_state
+  -- outputs: r_sig
+  DetectState: process (sw_state)
+  begin  -- process DetectState
+    if (sw_state'event and sw_state = '0') then
+      log10_r_sig <= log10_r_open;
+    elsif (sw_state'event and sw_state = '1') then
+      log10_r_sig <= log10_r_closed;
+    end if;
+  end process DetectState;
+
+-- Characteristic equations
+  log10_r == log10_r_sig'ramp(trans_time, trans_time);
+  r == 10**log10_r;
+  v == r*i;
+end architecture log;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : buff.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Simple Buffer with delay time
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity buff is
+  generic (
+    delay : time := 0 ns);              -- Delay time
+
+  port (
+    input  : in  std_logic;
+    output : out std_logic);
+
+end entity buff;
+
+architecture ideal of buff is
+  
+begin
+  output <= input after delay;
+  
+end architecture ideal;
+
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Inverter
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY inverter IS
+  GENERIC (
+    delay : time := 0 ns);              -- Delay time
+  
+  PORT (
+    input : IN  std_logic;
+    output : OUT std_logic);
+  
+END ENTITY inverter;
+
+ARCHITECTURE ideal OF inverter IS
+BEGIN
+   output <= NOT input AFTER delay;
+END ARCHITECTURE ideal;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : opamp.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: 3-pin OpAmp model with behavioral architecture
+--              Uses Q'LTF function to define open-loop response
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity opamp is
+-- Initialize parameters
+  generic (rin   : resistance := 1.0e6;    -- Input resistance [Ohms]
+           rout  : resistance := 100.0;    -- Output resistance (Ohms]
+           avol  : real       := 100.0e3;  -- Open loop gain
+           f_0dB : real       := 1.0e6     -- Unity Gain Frequency [Hz]
+           );
+-- Define ports as electrical terminals
+  port (
+    terminal in_pos, in_neg, output : electrical);
+
+end entity opamp;
+
+-------------------------------------------------------------------------------
+-- Basic Architecture
+-- Characteristics modeled:
+--      1. Open loop gain
+--      2. Frequency characteristics (single pole response) 
+--      3. Input and output resistance
+-- Uses Q'Ltf function to create open loop gain and roll off
+-------------------------------------------------------------------------------
+architecture basic of opamp is
+  -- Declare constants
+  constant f_3db : real        := f_0db / avol;     -- -3dB frequency
+  constant w_3dB : real        := math_2_pi*f_3dB;  -- -3dB freq in radians
+  -- Numerator and denominator for Q'LTF function
+  constant num   : real_vector := (0 => avol);
+  constant den   : real_vector := (1.0, 1.0/w_3dB);
+  -- Declare input and output quantities
+  quantity v_in across i_in through in_pos to in_neg;
+  quantity v_out across i_out through output;
+
+begin  -- ARCHITECTURE basic
+
+  i_in  == v_in / rin;                       -- input current
+  v_out == v_in'ltf(num, den) + i_out*rout;  -- output voltage
+
+end architecture basic;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical Resistor Model
+
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY resistor IS 
+
+-- Initialize parameters
+  GENERIC (
+    res : RESISTANCE);                 -- resistance (no initial value)
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL p1, p2 : ELECTRICAL);
+
+END ENTITY resistor;
+
+-- Ideal Architecture (V = I*R)
+ARCHITECTURE ideal OF resistor IS
+  
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH p1 TO p2;
+
+BEGIN
+  
+-- Characteristic equations
+  v == i*res;                       
+
+END ARCHITECTURE ideal;
+
+--
+
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Constant Voltage Source (Includes Frequency Domain settings)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+ENTITY v_constant IS
+
+-- Initialize parameters
+  GENERIC (
+    level      : VOLTAGE;		-- Constant voltage value (V)
+    ac_mag     : VOLTAGE := 1.0;	-- AC magnitude (V)
+    ac_phase   : real := 0.0);		-- AC phase (degrees)
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL pos, neg : ELECTRICAL);
+
+END ENTITY v_constant;
+
+-- Ideal Architecture (I = constant)
+ARCHITECTURE ideal OF v_constant IS
+  
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH pos TO neg;
+-- Declare quantity in frequency domain for AC analysis  
+  QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN
+
+  IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
+	v == level;
+  ELSE	
+  	v == ac_spec;  -- used for Frequency (AC) analysis
+  END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : comparator_d.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/08/03
+-- Last update: 2001/08/03
+-------------------------------------------------------------------------------
+-- Description: Voltage comparator with digital output
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/08/03  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use IEEE natures and packages
+library IEEE;
+use ieee.std_logic_1164.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+use IEEE_proposed.ENERGY_SYSTEMS.all;
+
+entity comparator_d is
+
+  port (
+    terminal in_pos : electrical;
+    terminal in_neg : electrical;
+    signal output : out std_logic := '1'      -- Digital output
+    );
+
+end comparator_d;
+-------------------------------------------------------------------------------
+-- Behavioral architecture
+-------------------------------------------------------------------------------
+architecture behavioral of comparator_d is
+  quantity Vin across in_pos;
+  quantity Vref across in_neg;
+
+begin  -- behavioral
+
+  -- purpose: Detect threshold crossing and assign event on output
+  -- type   : combinational
+  -- inputs : vin'above(thres)
+  -- outputs: pulse_signal  
+  process (Vin'above(Vref)) is
+  begin  -- PROCESS
+    if Vin'above(Vref) then
+      output <= '1' after 1us;
+    else
+      output <= '0' after 1us;
+    end if;
+  end process;
+
+end behavioral;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : v_pulse.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/07/09
+-------------------------------------------------------------------------------
+-- Description:  Voltage Pulse Source
+--               Includes Frequency Domain settings
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created
+-- 2001/07/09  1.1         Mentor Graphics     Changed input parameters to type
+--                                             time.  Uses time2real function.
+--                                             Pulsewidth no longer includes
+--                                             rise and fall times.
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.MATH_REAL.all;
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity v_pulse is
+
+  generic (
+    initial  : voltage := 0.0;          -- initial value [Volts]
+    pulse    : voltage;                 -- pulsed value [Volts]
+    ti2p     : time    := 1ns;          -- initial to pulse [Sec]
+    tp2i     : time    := 1ns;          -- pulse to initial [Sec]
+    delay    : time    := 0ms;          -- delay time [Sec]
+    width    : time;                    -- duration of pulse [Sec]
+    period   : time;                    -- period [Sec]
+    ac_mag   : voltage := 1.0;          -- AC magnitude [Volts]
+    ac_phase : real    := 0.0);         -- AC phase [Degrees]
+
+  port (
+    terminal pos, neg : electrical);
+
+end entity v_pulse;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture
+-------------------------------------------------------------------------------
+architecture ideal of v_pulse is
+
+-- Declare Through and Across Branch Quantities
+  quantity v across i through pos to neg;
+-- Declare quantity in frequency domain for AC analysis 
+  quantity ac_spec      : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+-- Signal used in CreateEvent process below  
+  signal   pulse_signal : voltage := initial;
+  
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+-- Note: these lines gave an error during simulation.  Had to use a
+-- function call instead.
+--  constant ri2p : real := time'pos(ti2p) * 1.0e-15;
+--  constant rp2i : real := time'pos(tp2i) * 1.0e-15;
+  
+-- Function to convert numbers of type TIME to type REAL
+  function time2real(tt : time) return real is
+  begin
+    return time'pos(tt) * 1.0e-15;
+  end time2real;
+-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
+  constant ri2p         : real    := time2real(ti2p);
+  constant rp2i         : real    := time2real(tp2i);
+
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+    v == pulse_signal'ramp(ri2p, rp2i);  -- create rise and fall transitions
+  else
+    v   == ac_spec;                        -- used for Frequency (AC) analysis
+  end use;
+
+-- purpose: Create events to define pulse shape
+-- type   : combinational
+-- inputs : 
+-- outputs: pulse_signal
+CreateEvent : process
+begin
+  wait for delay;
+  loop
+    pulse_signal <= pulse;
+    wait for (width + ti2p);
+    pulse_signal <= initial;
+    wait for (period - width - ti2p);
+  end loop;
+end process CreateEvent;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pwm_mac is
+    port(
+        terminal inp : electrical;
+        terminal inm : electrical;
+        dig_out : out std_logic
+    );
+end pwm_mac;
+
+architecture pwm_mac of pwm_mac is
+    -- Component declarations
+    -- Signal declarations
+    terminal cmp_in : electrical;
+    terminal plse_in : electrical;
+    terminal XSIG010002 : electrical;
+    terminal XSIG010003 : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    U1 : entity work.opamp(basic)
+        port map(
+            in_neg => XSIG010002,
+            in_pos => inm,
+            output => cmp_in
+        );
+    R1 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => XSIG010002,
+            p2 => cmp_in
+        );
+    v2 : entity work.v_constant(ideal)
+        generic map(
+            level => 0.0
+        )
+        port map(
+            pos => XSIG010003,
+            neg => ELECTRICAL_REF
+        );
+    R2 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => plse_in,
+            p2 => XSIG010002
+        );
+    R3 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => inp,
+            p2 => XSIG010002
+        );
+    XCMP4 : entity work.comparator_d(behavioral)
+        port map(
+            output => dig_out,
+            in_pos => XSIG010003,
+            in_neg => cmp_in
+        );
+    v9 : entity work.v_pulse(ideal)
+        generic map(
+            initial => -4.7,
+            pulse => 4.7,
+            ti2p => 200 us,
+            tp2i => 200 us,
+            delay => 1 us,
+            width => 1 us,
+            period => 405 us
+        )
+        port map(
+            pos => plse_in,
+            neg => ELECTRICAL_REF
+        );
+end pwm_mac;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : diode_pwl.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Diode model with ideal architecture
+--              Currently no Generics due to bug in DV 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.math_real.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+-- energy_systems package needed for Boltzmann constant (K = Joules/Kelvin)
+use IEEE_proposed.energy_systems.all;
+
+ENTITY diode_pwl IS
+	GENERIC (
+		ron : real;	-- equivalent series resistance
+		roff : real);	-- leakage resistance
+	PORT (
+		TERMINAL 	p,	-- positive pin
+				m : electrical); -- minus pin
+END ENTITY diode_pwl;
+
+ARCHITECTURE simple OF diode_pwl IS
+	QUANTITY v across i through p TO m;
+
+BEGIN			-- simple ARCHITECTURE
+	if v'Above(0.0) use
+		i == v/ron;
+	elsif not v'Above(0.0) use
+		i == v/roff;
+	else
+		i == 0.0;
+	end use;
+	break on v'Above(0.0);
+END ARCHITECTURE simple;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity pwm_H_bridge is
+    port(
+        terminal mot_ccw : electrical;
+        terminal pwr_in : electrical;
+        terminal mot_cw : electrical;
+        terminal src_in : electrical
+    );
+end pwm_H_bridge;
+
+architecture pwm_H_bridge of pwm_H_bridge is
+    -- Component declarations
+    -- Signal declarations
+    signal pwm_out : std_logic;
+    signal sw_ccw : std_logic;
+    signal sw_cw : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    sw2 : entity work.switch_dig_log(linear)
+        generic map(
+            trans_time => 1.0e-5,
+            r_closed => 0.1
+        )
+        port map(
+            sw_state => sw_cw,
+            p2 => pwr_in,
+            p1 => mot_cw
+        );
+    sw3 : entity work.switch_dig_log(linear)
+        generic map(
+            trans_time => 1.0e-5,
+            r_closed => 0.1
+        )
+        port map(
+            sw_state => sw_ccw,
+            p2 => mot_cw,
+            p1 => ELECTRICAL_REF
+        );
+    U1 : entity work.buff(ideal)
+        port map(
+            input => pwm_out,
+            output => sw_cw
+        );
+    U2 : entity work.inverter(ideal)
+        port map(
+            input => pwm_out,
+            output => sw_ccw
+        );
+    sw5 : entity work.switch_dig_log(linear)
+        generic map(
+            trans_time => 1.0e-5,
+            r_closed => 0.1
+        )
+        port map(
+            sw_state => sw_ccw,
+            p2 => pwr_in,
+            p1 => mot_ccw
+        );
+    sw6 : entity work.switch_dig_log(linear)
+        generic map(
+            trans_time => 1.0e-5,
+            r_closed => 0.1
+        )
+        port map(
+            sw_state => sw_cw,
+            p2 => mot_ccw,
+            p1 => ELECTRICAL_REF
+        );
+    pwm : entity work.pwm_mac
+        port map(
+            inp => src_in,
+            dig_out => pwm_out,
+            inm => ELECTRICAL_REF
+        );
+    D7 : entity work.diode_pwl(simple)
+        generic map(
+            roff => 100.0e3,
+            ron => 0.001
+        )
+        port map(
+            p => mot_cw,
+            m => pwr_in
+        );
+    D8 : entity work.diode_pwl(simple)
+        generic map(
+            ron => 0.001,
+            roff => 100.0e3
+        )
+        port map(
+            p => mot_ccw,
+            m => pwr_in
+        );
+    D9 : entity work.diode_pwl(simple)
+        generic map(
+            ron => 0.001,
+            roff => 100.0e3
+        )
+        port map(
+            p => ELECTRICAL_REF,
+            m => mot_cw
+        );
+    D10 : entity work.diode_pwl(simple)
+        generic map(
+            ron => 0.001,
+            roff => 100.0e3
+        )
+        port map(
+            p => ELECTRICAL_REF,
+            m => mot_ccw
+        );
+end pwm_H_bridge;
+--
+-- Copyright Mentor Graphics Corporation 2001
+-- Confidential Information Provided Under License Agreement for Internal Use Only
+
+-- Electrical sinusoidal voltage source (stick.vhd)
+
+LIBRARY IEEE;
+USE IEEE.MATH_REAL.ALL;
+-- Use proposed IEEE natures and packages
+LIBRARY IEEE_proposed;
+USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
+
+
+ENTITY stick IS
+  
+-- Initialize parameters
+  GENERIC (
+    freq      : real;                     -- frequency,       [Hertz]
+    amplitude : real;                     -- amplitude,       [Volt]
+    phase     : real := 0.0;              -- initial phase,   [Degree]
+    offset    : real := 0.0;              -- DC value,        [Volt]
+    df        : real := 0.0;              -- damping factor,  [1/second]
+    ac_mag    : real := 1.0;              -- AC magnitude,    [Volt]
+    ac_phase  : real := 0.0);             -- AC phase,        [Degree]
+
+-- Define ports as electrical terminals
+  PORT (
+    TERMINAL v_out : ELECTRICAL);
+
+END ENTITY stick;
+
+-- Ideal Architecture
+ARCHITECTURE ideal OF stick IS
+-- Declare Branch Quantities
+  QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
+-- Declare Quantity for Phase in radians (calculated below)
+  QUANTITY phase_rad : real;          
+-- Declare Quantity in frequency domain for AC analysis
+  QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
+
+BEGIN  
+-- Convert phase to radians
+  phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
+  
+  IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
+    v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
+  ELSE 
+    v == ac_spec;    -- used for Frequency (AC) analysis
+  END USE;
+
+END ARCHITECTURE ideal;
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : inductor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Electrical Inductor
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity inductor is
+
+  generic (
+    ind  : inductance;             -- Nominal inductance
+    i_ic : real := real'low);      -- Initial current (use IF statement below
+                                   -- to activate) 
+                                  
+  port (
+    terminal p1, p2 : electrical);
+
+end entity inductor;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture (V = L * di/dt)
+-- Includes initial condition
+-------------------------------------------------------------------------------
+architecture ideal of inductor is
+
+-- Declare Branch Quantities
+  quantity v across i through p1 to p2;
+
+begin
+
+  if domain = quiescent_domain and i_ic /= real'low use
+    i == i_ic;
+  else
+    v   == ind * i'dot;                   -- characteristic equation
+  end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+--
+-- This model is a component of the Mentor Graphics VHDL-AMS educational open 
+-- source model library, and is covered by this license agreement. This model,
+-- including any updates, modifications, revisions, copies, and documentation 
+-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR 
+-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
+-- IN THIS LICENSE AGREEMENT.  Mentor Graphics grants you a non-exclusive 
+-- license to use, reproduce, modify and distribute this model, provided that:
+-- (a) no fee or other consideration is charged for any distribution except 
+-- compilations distributed in accordance with Section (d) of this license 
+-- agreement; (b) the comment text embedded in this model is included verbatim
+-- in each copy of this model made or distributed by you, whether or not such 
+-- version is modified; (c) any modified version must include a conspicuous 
+-- notice that this model has been modified and the date of modification; and 
+-- (d) any compilations sold by you that include this model must include a 
+-- conspicuous notice that this model is available from Mentor Graphics in its
+-- original form at no charge.
+--
+-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR 
+-- IMPLIED.  MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF 
+-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  MENTOR GRAPHICS SHALL
+-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
+-------------------------------------------------------------------------------
+-- File       : capacitor.vhd
+-- Author     : Mentor Graphics
+-- Created    : 2001/06/16
+-- Last update: 2001/06/16
+-------------------------------------------------------------------------------
+-- Description: Electrical Capacitor 
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version     Author              Description
+-- 2001/06/16  1.0         Mentor Graphics     Created    
+-------------------------------------------------------------------------------
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity capacitor is
+
+  generic (
+    cap             : capacitance;        -- Capacitance [F]
+    v_ic            : real := real'low;   -- Initial voltage (activated by
+                                          -- IF statement below)
+    r_esr            : resistance := 0.0); -- Equivalent Series Capicitance 
+	                                      -- (used only in ESR architecture)
+  
+  port (
+    terminal p1, p2 : electrical);
+
+end entity capacitor;
+
+-------------------------------------------------------------------------------
+-- Ideal Architecture  (I = C * dV/dt)
+-- Includes initial condition
+-------------------------------------------------------------------------------
+architecture ideal of capacitor is
+  
+  quantity v across i through p1 to p2;
+
+begin
+
+  if domain = quiescent_domain and v_ic /= real'low use
+    v == v_ic;
+  else
+    i   == cap * v'dot;                  -- characteristic equation
+  end use;
+
+end architecture ideal;
+
+-------------------------------------------------------------------------------
+-- Architecture includes effects of Equivalent Series Capacitance
+-------------------------------------------------------------------------------
+architecture ESR of capacitor is
+  quantity v across i through p1 to p2;
+  quantity vc   : voltage;              -- Internal voltage across capacitor
+begin
+  if domain = quiescent_domain and v_ic /= real'low use
+    vc == v_ic;
+	i == 0.0;
+  else
+    vc == v - (i * r_esr);
+    i == cap * vc'dot;
+
+  end use;
+end architecture ESR;
+
+-------------------------------------------------------------------------------
+-- Copyright (c) 2001 Mentor Graphics Corporation
+-------------------------------------------------------------------------------
+--
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+
+entity buck_sw is
+  
+  generic (
+	Vd   : voltage := 0.7;             -- Diode Voltage
+	Vramp : voltage := 2.5);           -- P-P amplitude of ramp voltage
+
+  port (
+    terminal input, output, ref, ctrl: electrical);
+  
+end entity buck_sw;
+
+architecture average of buck_sw is
+
+  quantity Vout across Iout through output to ref;
+  quantity Vin across input to ref;
+  quantity Vctrl across ctrl to ref;
+  
+begin  -- bhv
+
+   Vout + Vd == Vctrl * Vin / Vramp; 
+
+end average;
+
+--
+
+-- Loop control switch
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+-- Use proposed IEEE natures and packages
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity sw_LoopCtrl is
+  generic (r_open     : resistance := 1.0e6;
+           r_closed   : resistance := 1.0e-3;
+	   sw_state   : integer    := 1);
+
+  port (terminal c, p1, p2 : electrical);
+end entity sw_LoopCtrl;
+
+architecture ideal of sw_LoopCtrl is 
+  quantity v1 across i1 through c to p1;
+  quantity v2 across i2 through c to p2;
+  quantity r1, r2 : resistance;  
+begin
+    if (sw_state = 1) use
+      r1 == r_closed;
+      r2 == r_open;
+    elsif (sw_state = 2) use
+      r1 == r_open;
+      r2 == r_closed;
+    else
+      r1 == r_closed;
+      r2 == r_open; 
+    end use;
+
+  v1 == r1*i1;
+  v2 == r2*i2;
+end architecture ideal;
+--
+
+library ieee, ieee_proposed;
+use ieee.math_real.all;
+use IEEE_proposed.electrical_systems.all;
+
+entity comp_2p2z is
+  generic (
+    gain : real := 100.0;    -- High DC gain for good load regulation       
+    fp1  : real := 7.5e3;     -- Pole location to achieve crossover frequency
+    fp2  : real := 531.0e3;   -- Pole location to cancel effect of ESR 
+    fz1  : real := 806.0;     -- Zero locations to cancel LC filter poles
+    fz2  : real := 806.0);
+  port (
+    terminal input, output, ref : electrical);
+end entity comp_2p2z;
+
+architecture ltf of comp_2p2z is
+  quantity vin across input to ref;
+  quantity vout across iout through output to ref;
+  constant wp1 : real        := math_2_pi*fp1;  -- Pole freq (in radians)
+  constant wp2 : real        := math_2_pi*fp2;
+  constant wz1 : real        := math_2_pi*fz1;  -- Zero freq (in radians)
+  constant wz2 : real        := math_2_pi*fz2;
+  constant num : real_vector := (1.0, 1.0/wz1 + 1.0/wz2, 1.0/(wz1*wz2));
+  constant den : real_vector := (1.0e-9,1.0,1.0/wp1+1.0/wp2,1.0/(wp1*wp2));
+
+begin
+     vout == -1.0*gain*vin'ltf(num, den);
+end architecture ltf;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity ex_buck is
+    port(
+        terminal pwr_out : electrical
+    );
+end ex_buck;
+
+architecture ex_buck of ex_buck is
+    -- Component declarations
+    -- Signal declarations
+    terminal vcomp_out : electrical;
+    terminal vctrl : electrical;
+    terminal vctrl_init : electrical;
+    terminal vin : electrical;
+    terminal vmid : electrical;
+    terminal XSIG010004 : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    l1 : entity work.inductor(ideal)
+        generic map(
+            ind => 6.5e-3
+        )
+        port map(
+            p1 => vmid,
+            p2 => pwr_out
+        );
+    c1 : entity work.capacitor(ideal)
+        generic map(
+            cap => 6.0e-6,
+            r_esr => 50.0e-3
+        )
+        port map(
+            p1 => pwr_out,
+            p2 => ELECTRICAL_REF
+        );
+    buck_sw1 : entity work.buck_sw(average)
+        port map(
+            output => vmid,
+            ref => ELECTRICAL_REF,
+            ctrl => vctrl,
+            input => vin
+        );
+    sw1 : entity work.sw_LoopCtrl(ideal)
+        generic map(
+            sw_state => 1
+        )
+        port map(
+            p2 => vctrl_init,
+            c => vctrl,
+            p1 => vcomp_out
+        );
+    comp_2p2z1 : entity work.comp_2p2z(ltf)
+        port map(
+            ref => XSIG010004,
+            output => vcomp_out,
+            input => pwr_out
+        );
+    v1 : entity work.v_pulse(ideal)
+        generic map(
+            initial => 42.0,
+            pulse => 42.0,
+            delay => 10ms,
+            width => 100ms,
+            period => 1000ms
+        )
+        port map(
+            pos => vin,
+            neg => ELECTRICAL_REF
+        );
+    v2 : entity work.v_constant(ideal)
+        generic map(
+            level => 0.327
+        )
+        port map(
+            pos => vctrl_init,
+            neg => ELECTRICAL_REF
+        );
+    v3 : entity work.v_constant(ideal)
+        generic map(
+            level => 4.8
+        )
+        port map(
+            pos => XSIG010004,
+            neg => ELECTRICAL_REF
+        );
+end ex_buck;
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_CS5_Rudder_Power is
+end tb_CS5_Rudder_Power ;
+
+architecture TB_CS5_Rudder_Power of tb_CS5_Rudder_Power is
+    -- Component declarations
+    -- Signal declarations
+    terminal buck_out : electrical;
+    terminal gear_out : rotational;
+    terminal link_in : translational;
+    terminal link_out : translational;
+    terminal mot_ccw : electrical;
+    terminal mot_cw : electrical;
+    terminal mot_out : rotational_v;
+    terminal pos_fb_v : electrical;
+    terminal pwm_in : electrical;
+    terminal rudder : rotational;
+    terminal src_in : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    rudder_servo1 : entity work.rudder_servo
+        port map(
+            servo_out => pwm_in,
+            servo_in => src_in,
+            pos_fb => pos_fb_v
+        );
+    gear3 : entity work.gear_rv_r(ideal)
+        generic map(
+            ratio => 0.01
+        )
+        port map(
+            rotv1 => mot_out,
+            rot2 => gear_out
+        );
+    r2v : entity work.rot2v(bhv)
+        generic map(
+            k => 1.0
+        )
+        port map(
+            output => pos_fb_v,
+            input => gear_out
+        );
+    r2t : entity work.horn_r2t(bhv)
+        port map(
+            theta => gear_out,
+            pos => link_in
+        );
+    t2r : entity work.horn_t2r(bhv)
+        port map(
+            theta => rudder,
+            pos => link_out
+        );
+    motor1 : entity work.DC_Motor(basic)
+        generic map(
+            r_wind => 2.2,
+            kt => 3.43e-3,
+            l => 2.03e-3,
+            d => 5.63e-6,
+            j => 168.0e-9
+        )
+        port map(
+            p1 => mot_cw,
+            p2 => mot_ccw,
+            shaft_rotv => mot_out
+        );
+    stop1 : entity work.stop_r(ideal)
+        generic map(
+            damp_stop => 1.0e2,
+            k_stop => 1.0e6,
+            ang_max => 1.05,
+            ang_min => -1.05
+        )
+        port map(
+            ang1 => gear_out,
+            ang2 => ROTATIONAL_REF
+        );
+    \linkage\ : entity work.tran_linkage(a1)
+        port map(
+            p2 => link_out,
+            p1 => link_in
+        );
+    rudder_1 : entity work.rudder(bhv)
+        generic map(
+            k => 0.02
+        )
+        port map(
+            rot => rudder
+        );
+    pwm_H_bridge1 : entity work.pwm_H_bridge
+        port map(
+            src_in => pwm_in,
+            mot_cw => mot_cw,
+            pwr_in => buck_out,
+            mot_ccw => mot_ccw
+        );
+    XCMP65 : entity work.stick(ideal)
+        generic map(
+            freq => 1.0,
+            amplitude => 4.7,
+            phase => 0.0,
+            offset => 0.0
+        )
+        port map(
+            v_out => src_in
+        );
+    ex_buck4 : entity work.ex_buck
+        port map(
+            pwr_out => buck_out
+        );
+end TB_CS5_Rudder_Power;
+--
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/bounded_buffer_adt.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/bounded_buffer_adt.vhd
new file mode 100644
index 0000000..3041d03
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/bounded_buffer_adt.vhd
@@ -0,0 +1,114 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package bounded_buffer_adt is
+
+  subtype byte is bit_vector(0 to 7);
+
+  type bounded_buffer_object;  -- private
+
+  type bounded_buffer is access bounded_buffer_object;
+
+  function new_bounded_buffer ( size : in positive ) return bounded_buffer;
+  -- creates a bounded buffer object with 'size' bytes of storage
+
+  procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
+                         is_empty : out boolean );
+  -- tests whether the bounded buffer is empty (i.e., no data to read)
+
+  procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
+                        is_full : out boolean );
+  -- tests whether the bounded buffer is full (i.e., no data can be written)
+
+  procedure write ( the_bounded_buffer : inout bounded_buffer;  data : in byte );
+  -- if the bounded buffer is not full, writes the data
+  -- if it is full, assertion violation with severity failure
+
+  procedure read ( the_bounded_buffer : inout bounded_buffer;  data : out byte );
+  -- if the bounded buffer is not empty, read the first byte of data
+  -- if it is empty, assertion violation with severity failure
+
+----------------------------------------------------------------
+
+  -- the following types are private to the ADT
+
+  type store_array is array (natural range <>) of byte;
+
+  type store_ptr is access store_array;
+
+  type bounded_buffer_object is record
+      byte_count : natural;
+      head_index, tail_index : natural;
+      store : store_ptr;
+    end record bounded_buffer_object;
+
+end package bounded_buffer_adt;
+
+
+
+package body bounded_buffer_adt is
+
+  function new_bounded_buffer ( size : in positive ) return bounded_buffer is
+  begin
+    return new bounded_buffer_object'(
+             byte_count => 0, head_index => 0, tail_index => 0,
+             store => new store_array(0 to size - 1) );
+  end function new_bounded_buffer;
+
+  procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
+                         is_empty : out boolean ) is
+  begin
+    is_empty := the_bounded_buffer.byte_count = 0;
+  end procedure test_empty;
+
+  procedure test_full ( variable the_bounded_buffer : in bounded_buffer;
+                        is_full : out boolean ) is
+  begin
+    is_full := the_bounded_buffer.byte_count = the_bounded_buffer.store'length;
+  end procedure test_full;
+
+  procedure write ( the_bounded_buffer : inout bounded_buffer;  data : in byte ) is
+    variable buffer_full : boolean;
+  begin
+    test_full(the_bounded_buffer, buffer_full);
+    if buffer_full then
+      report "write to full bounded buffer" severity failure;
+    else
+      the_bounded_buffer.store(the_bounded_buffer.tail_index) := data;
+      the_bounded_buffer.tail_index := (the_bounded_buffer.tail_index + 1)
+                                       mod the_bounded_buffer.store'length;
+      the_bounded_buffer.byte_count := the_bounded_buffer.byte_count + 1;
+    end if;
+  end procedure write;
+
+  procedure read ( the_bounded_buffer : inout bounded_buffer;  data : out byte ) is
+    variable buffer_empty : boolean;
+  begin
+    test_empty(the_bounded_buffer, buffer_empty);
+    if buffer_empty then
+      report "read from empty bounded buffer" severity failure;
+    else
+      data := the_bounded_buffer.store(the_bounded_buffer.head_index);
+      the_bounded_buffer.head_index := (the_bounded_buffer.head_index + 1)
+                                       mod the_bounded_buffer.store'length;
+      the_bounded_buffer.byte_count := the_bounded_buffer.byte_count - 1;
+    end if;
+  end procedure read;
+
+end package body bounded_buffer_adt;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/index-ams.txt
new file mode 100644
index 0000000..6a27774
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/index-ams.txt
@@ -0,0 +1,30 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                Chapter 20 - Access Types and Abstract Data Types
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+list_traversal.vhd                              entity list_traversal                   test                            Figure 20-5
+list_search.vhd                                 entity list_search                      test                            Figure 20-7
+bounded_buffer_adt.vhd                          package bounded_buffer_adt              body                            Figures 20-8, 20-11
+receiver.vhd                                    entity receiver                         test                            Figure 20-9
+ordered_collection_adt.vhd                      package «element_type_simple_name»_ordered_collection_adt
+--                                                                                      body                            Figures 20-12, 20-16
+stimulus_types-1.vhd                            package stimulus_types                  body                            Figure 20-13
+test_bench-1.vhd                                package stimulus_element_ordered_collection_adt
+--                                                                                      body                            --
+--                                              entity test_bench                       initial_test                    Figure 20-14
+inline_01.vhd                                   entity inline_01                        test                            Section 20.1
+inline_02a.vhd                                  entity inline_02a                       test                            Section 20.1
+inline_03.vhd                                   entity inline_03                        test                            Section 20.1
+inline_04a.vhd                                  entity inline_04a                       test                            Section 20.1
+inline_05.vhd                                   entity inline_05                        test                            Section 20.1
+inline_06a.vhd                                  entity inline_06a                       test                            Section 20.2
+inline_07a.vhd                                  entity inline_07a                       test                            Section 20.2
+inline_08.vhd                                   entity inline_08                        test                            Section 20.2
+inline_09.vhd                                   entity inline_09                        test                            Section 20.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_bounded_buffer_adt.vhd                       entity tb_bounded_buffer_adt            test                            bounded_buffer_adt.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_01.vhd
new file mode 100644
index 0000000..2d326bd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_01.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+  process is
+
+    -- code from book:
+
+    type natural_ptr is access natural;
+
+    variable count : natural_ptr;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    count := new natural;
+
+    count.all := 10;
+
+    if count.all = 0 then
+      -- . . .
+      -- not in book
+      report "count.all = 0";
+      -- end not in book
+    end if;
+
+    -- end of code from book
+
+    if count.all /= 0 then
+      report "count.all /= 0";
+    end if;
+
+    -- code from book:
+
+    count := new natural'(10);
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_02a.vhd
new file mode 100644
index 0000000..2a0e4e6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_02a.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02a is
+begin
+
+
+  process is
+
+    -- code from book:
+
+    type stimulus_record is record
+        stimulus_time : time;
+        stimulus_value : real_vector(0 to 3);
+      end record stimulus_record;
+
+    type stimulus_ptr is access stimulus_record;
+
+    variable bus_stimulus : stimulus_ptr;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    bus_stimulus := new stimulus_record'( 20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_03.vhd
new file mode 100644
index 0000000..e4ed824
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_03.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+begin
+
+
+  process is
+
+    type natural_ptr is access natural;
+
+    -- code from book:
+
+    variable count1, count2 : natural_ptr;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    count1 := new natural'(5);
+    count2 := new natural'(10);
+
+    count2 := count1;
+
+    count1.all := 20;
+
+    -- end of code from book
+
+    assert
+    -- code from book:
+    count1 = count2
+    -- end of code from book
+    ;
+
+    -- code from book:
+
+    count1 := new natural'(30);
+    count2 := new natural'(30);
+
+    -- end of code from book
+
+    assert count1 = count2;
+
+    assert
+    -- code from book:
+    count1.all = count2.all
+    -- end of code from book
+    ;
+
+    -- code from book:
+
+    if count1 /= null then
+      count1.all := count1.all + 1;
+    end if;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_04a.vhd
new file mode 100644
index 0000000..82aa944
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_04a.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04a is
+begin
+
+
+  process is
+
+    -- code from book:
+
+    type stimulus_record is record
+        stimulus_time : time;
+        stimulus_value : real_vector(0 to 3);
+      end record stimulus_record;
+
+    type stimulus_ptr is access stimulus_record;
+
+    variable bus_stimulus : stimulus_ptr;
+
+    -- end of code from book
+
+  begin
+
+    bus_stimulus := new stimulus_record;
+
+    bus_stimulus.all := stimulus_record'(20 ns, real_vector'(0.0, 5.0, 0.0, 42.0) );
+
+    report time'image(bus_stimulus.all.stimulus_time);
+
+    report time'image(bus_stimulus.stimulus_time);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_05.vhd
new file mode 100644
index 0000000..8a03a87
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_05.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+begin
+
+
+  process is
+
+    -- code from book:
+
+    type coordinate is array (1 to 3) of real;
+    type coordinate_ptr is access coordinate;
+
+    variable origin : coordinate_ptr := new coordinate'(0.0, 0.0, 0.0);
+
+    type time_array is array (positive range <>) of time;
+    variable activation_times : time_array(1 to 100);
+
+    -- end of code from book
+
+  begin
+
+    report real'image( origin(1) );
+    report real'image( origin(2) );
+    report real'image( origin(3) );
+    report real'image( origin.all(1) );
+
+    wait;
+  end process;
+
+
+  process is
+
+    type time_array is array (positive range <>) of time;
+
+    -- code from book:
+
+    type time_array_ptr is access time_array;
+
+    variable activation_times : time_array_ptr;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    activation_times := new time_array'(10 us, 15 us, 40 us);
+
+    activation_times := new time_array'( activation_times.all
+                                         & time_array'(70 us, 100 us) );
+
+    activation_times := new time_array(1 to 10);
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_06a.vhd
new file mode 100644
index 0000000..4322b31
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_06a.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_06a is
+
+end entity inline_06a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06a is
+begin
+
+
+  process is
+
+    -- code from book:
+
+    type value_cell is record
+        value : real_vector(0 to 3);
+        next_cell : value_ptr;
+      end record value_cell;
+
+    type value_ptr is access value_cell;
+
+    -- end of code from book
+
+  begin
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_07a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_07a.vhd
new file mode 100644
index 0000000..64b6337
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_07a.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_07a is
+
+end entity inline_07a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_07a is
+begin
+
+
+  process is
+
+    -- code from book:
+
+    type value_cell;
+
+    type value_ptr is access value_cell;
+
+    type value_cell is record
+        value : real_vector(0 to 3);
+        next_cell : value_ptr;
+      end record value_cell;
+
+    variable value_list : value_ptr;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    if value_list /= null then
+      -- . . .       -- do something with the list
+      -- not in book
+      report "value_list /= null";
+      -- end not in book
+    end if;
+
+    value_list := new value_cell'( real_vector'(0.0, 5.0, 0.0, 42.0), value_list );
+
+    value_list := new value_cell'( real_vector'(3.3, 2.2, 0.27, 1.9), value_list );
+
+    value_list := new value_cell'( real_vector'(2.9, 0.1, 21.12, 8.3), value_list );
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_08.vhd
new file mode 100644
index 0000000..9533f4f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_08.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_08 is
+
+  type T is (t1, t2, t3);
+
+  -- code from book:
+
+  type T_ptr is access T;
+
+  procedure deallocate ( P : inout T_ptr );
+
+  -- end of code from book
+
+  procedure deallocate ( P : inout T_ptr ) is
+  begin
+    null;
+  end procedure deallocate;
+
+begin
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_09.vhd
new file mode 100644
index 0000000..d570cee
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/inline_09.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+
+begin
+
+  process is
+
+    type value_cell;
+
+    type value_ptr is access value_cell;
+
+    type value_cell is record
+        value : bit_vector(0 to 3);
+        next_cell : value_ptr;
+      end record value_cell;
+
+    variable value_list, cell_to_be_deleted : value_ptr;
+
+  begin
+    value_list := new value_cell'( B"1000", value_list );
+    value_list := new value_cell'( B"0010", value_list );
+    value_list := new value_cell'( B"0000", value_list );
+
+    -- code from book:
+
+    cell_to_be_deleted := value_list;
+    value_list := value_list.next_cell;
+    deallocate(cell_to_be_deleted);
+
+    while value_list /= null loop
+      cell_to_be_deleted := value_list;
+      value_list := value_list.next_cell;
+      deallocate(cell_to_be_deleted);
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_search.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_search.vhd
new file mode 100644
index 0000000..5720898
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_search.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity list_search is
+
+end entity list_search;
+
+
+----------------------------------------------------------------
+
+
+architecture test of list_search is
+
+  signal s : bit_vector(0 to 3);
+
+begin
+
+  process is
+
+    type value_cell;
+
+    type value_ptr is access value_cell;
+
+    type value_cell is record
+        value : bit_vector(0 to 3);
+        next_cell : value_ptr;
+      end record value_cell;
+
+    variable value_list, current_cell : value_ptr;
+    variable search_value : bit_vector(0 to 3);
+
+  begin
+    value_list := new value_cell'( B"1000", value_list );
+    value_list := new value_cell'( B"0010", value_list );
+    value_list := new value_cell'( B"0000", value_list );
+
+    search_value := B"0010";
+
+    -- code from book:
+
+    current_cell := value_list;
+    while current_cell /= null
+        and current_cell.value /= search_value loop
+      current_cell := current_cell.next_cell;
+    end loop;
+    assert current_cell /= null
+      report "search for value failed";
+
+    -- end of code from book
+
+    search_value := B"1111";
+
+    current_cell := value_list;
+    while current_cell /= null
+        and current_cell.value /= search_value loop
+      current_cell := current_cell.next_cell;
+    end loop;
+    assert current_cell /= null
+      report "search for value failed";
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_traversal.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_traversal.vhd
new file mode 100644
index 0000000..4c0dedd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/list_traversal.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity list_traversal is
+
+end entity list_traversal;
+
+
+----------------------------------------------------------------
+
+
+architecture test of list_traversal is
+
+  signal s : bit_vector(0 to 3);
+
+begin
+
+  process is
+
+    type value_cell;
+
+    type value_ptr is access value_cell;
+
+    type value_cell is record
+        value : bit_vector(0 to 3);
+        next_cell : value_ptr;
+      end record value_cell;
+
+    variable value_list, current_cell : value_ptr;
+
+  begin
+    value_list := new value_cell'( B"1000", value_list );
+    value_list := new value_cell'( B"0010", value_list );
+    value_list := new value_cell'( B"0000", value_list );
+
+    -- code from book:
+
+    current_cell := value_list;
+    while current_cell /= null loop
+      s <= current_cell.value;
+      wait for 10 ns;
+      current_cell := current_cell.next_cell;
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/ordered_collection_adt.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/ordered_collection_adt.vhd
new file mode 100644
index 0000000..5a01174
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/ordered_collection_adt.vhd
@@ -0,0 +1,163 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package «element_type_simple_name»_ordered_collection_adt is
+
+  -- template: fill in the placeholders to specialize for a particular type
+
+  alias element_type is «element_type»;
+  alias key_type is «key_type»;
+  alias key_of is «key_function» [ element_type return key_type ];
+  alias "<" is «less_than_function» [ key_type, key_type return boolean ];
+
+  -- types provided by the package
+
+  type ordered_collection_object;    -- private
+  type position_object;              -- private
+
+  type ordered_collection is access ordered_collection_object;
+  type position is access position_object;
+
+  -- operations on ordered collections
+
+  function new_ordered_collection return ordered_collection;
+  -- returns an empty ordered collection of element_type values
+
+  procedure insert ( c : inout ordered_collection;  e : in element_type );
+  -- inserts e into c in position determined by key_of(e)
+
+  procedure get_element ( variable p : in position;  e : out element_type );
+  -- returns the element value at position p in its collection
+
+  procedure test_null_position ( variable p : in position;  is_null : out boolean );
+  -- test whether p refers to no position in its collection
+
+  procedure search ( variable c : in ordered_collection;  k : in key_type;
+                     p : out position );
+  -- searches for an element with key k in c, and returns the position of
+  -- that element, or, if not found, a position for which test_null_position
+  -- returns true
+
+  procedure find_first ( variable c : in ordered_collection;  p : out position );
+  -- returns the position of the first element of c
+
+  procedure advance ( p : inout position );
+  -- advances p to the next element in its collection,
+  -- or if there are no more, sets p so that test_null_position returns true
+
+  procedure delete ( p : inout position );
+  -- deletes the element at position p from its collection, and advances p
+
+  -- private types: pretend these are not visible
+
+  type ordered_collection_object is
+    record
+      element : element_type;
+      next_element, prev_element : ordered_collection;
+    end record ordered_collection_object;
+
+  type position_object is
+    record
+      the_collection : ordered_collection;
+      current_element : ordered_collection;
+    end record position_object;
+
+end package «element_type_simple_name»_ordered_collection_adt;
+
+
+package body «element_type_simple_name»_ordered_collection_adt is
+
+  function new_ordered_collection return ordered_collection is
+    variable result : ordered_collection := new ordered_collection_object;
+  begin
+    result.next_element := result;
+    result.prev_element := result;
+    return result;
+  end function new_ordered_collection;
+
+  procedure insert ( c : inout ordered_collection;  e : in element_type ) is
+    variable current_element : ordered_collection := c.next_element;
+    variable new_element : ordered_collection;
+  begin
+    while current_element /= c
+      and key_of(current_element.element) < key_of(e) loop
+      current_element := current_element.next_element;
+    end loop;
+    -- insert new element before current_element
+    new_element := new ordered_collection_object'(
+                         element => e,
+                         next_element => current_element,
+                         prev_element => current_element.prev_element );
+    new_element.next_element.prev_element := new_element;
+    new_element.prev_element.next_element := new_element;
+  end procedure insert;
+
+  procedure get_element ( variable p : in position;  e : out element_type ) is
+  begin
+    e := p.current_element.element;
+  end procedure get_element;
+
+  procedure test_null_position ( variable p : in position;  is_null : out boolean ) is
+  begin
+    is_null := p.current_element = p.the_collection;
+  end procedure test_null_position;
+
+  procedure search ( variable c : in ordered_collection;  k : in key_type;
+                     p : out position ) is
+    variable current_element : ordered_collection := c.next_element;
+  begin
+    while current_element /= c
+        and key_of(current_element.element) < k loop
+      current_element := current_element.next_element;
+    end loop;
+    if current_element = c or k < key_of(current_element.element) then
+      p := new position_object'(c, c);  -- null position
+    else
+      p := new position_object'(c, current_element);
+    end if;
+  end procedure search;
+
+  procedure find_first ( variable c : in ordered_collection;  p : out position ) is
+  begin
+    p := new position_object'(c, c.next_element);
+  end procedure find_first;
+
+  procedure advance ( p : inout position ) is
+    variable is_null : boolean;
+  begin
+    test_null_position(p, is_null);
+    if not is_null then
+      p.current_element := p.current_element.next_element;
+    end if;
+  end procedure advance;
+
+  procedure delete ( p : inout position ) is
+    variable is_null : boolean;
+  begin
+    test_null_position(p, is_null);
+    if not is_null then
+      p.current_element.next_element.prev_element
+        := p.current_element.prev_element;
+      p.current_element.prev_element.next_element
+        := p.current_element.next_element;
+      p.current_element := p.current_element.next_element;
+    end if;
+  end procedure delete;
+
+end package body «element_type_simple_name»_ordered_collection_adt;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/receiver.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/receiver.vhd
new file mode 100644
index 0000000..e7aad31
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/receiver.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity receiver is
+end entity receiver;
+
+
+
+architecture test of receiver is
+begin
+
+  -- code from book
+
+  receiver : process is
+
+    use work.bounded_buffer_adt.all;
+
+    variable receive_buffer : bounded_buffer := new_bounded_buffer(2048);
+    variable buffer_overrun, buffer_underrun : boolean;
+    -- . . .
+
+    -- not in book
+    variable received_byte, check_byte : byte;
+    -- end not in book
+
+  begin
+    -- . . .
+
+    test_full(receive_buffer, buffer_overrun);
+    if not buffer_overrun then
+      write(receive_buffer, received_byte);
+    end if;
+    -- . . .
+
+    test_empty(receive_buffer, buffer_underrun);
+    if not buffer_underrun then
+      read(receive_buffer, check_byte);
+    end if;
+    -- . . .
+
+  end process receiver;
+
+  -- end code from book
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/stimulus_types-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/stimulus_types-1.vhd
new file mode 100644
index 0000000..a7d9245
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/stimulus_types-1.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package stimulus_types is
+
+  constant stimulus_vector_length : positive := 4;
+
+  type stimulus_element is record
+      application_time : delay_length;
+      pattern : real_vector(0 to stimulus_vector_length - 1);
+    end record stimulus_element;
+
+  function stimulus_key ( stimulus : stimulus_element ) return delay_length;
+
+end package stimulus_types;
+
+----------------------------------------------------------------
+
+package body stimulus_types is
+
+  function stimulus_key ( stimulus : stimulus_element ) return delay_length is
+  begin
+    return stimulus.application_time;
+  end function stimulus_key;
+
+end package body stimulus_types;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/tb_bounded_buffer_adt.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/tb_bounded_buffer_adt.vhd
new file mode 100644
index 0000000..9da5aa2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/tb_bounded_buffer_adt.vhd
@@ -0,0 +1,100 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_bounded_buffer_adt is
+end entity tb_bounded_buffer_adt;
+
+
+architecture test of tb_bounded_buffer_adt is
+begin
+
+  process is
+
+    use work.bounded_buffer_adt.all;
+
+    variable buf : bounded_buffer := new_bounded_buffer(4);
+    variable empty, full : boolean;
+    variable d : byte;
+
+  begin
+    test_empty(buf, empty);
+    assert empty;
+    test_full(buf, full);
+    assert not full;
+
+    write(buf, X"01");
+    write(buf, X"02");
+
+    test_empty(buf, empty);
+    assert not empty;
+    test_full(buf, full);
+    assert not full;
+
+    write(buf, X"03");
+    write(buf, X"04");
+
+    test_empty(buf, empty);
+    assert not empty;
+    test_full(buf, full);
+    assert full;
+
+    write(buf, X"05");
+
+    read(buf, d);
+    read(buf, d);
+
+    test_empty(buf, empty);
+    assert not empty;
+    test_full(buf, full);
+    assert not full;
+
+    read(buf, d);
+    read(buf, d);
+
+    test_empty(buf, empty);
+    assert empty;
+    test_full(buf, full);
+    assert not full;
+
+    read(buf, d);
+
+    write(buf, X"06");
+    write(buf, X"07");
+    write(buf, X"08");
+    read(buf, d);
+    read(buf, d);
+    write(buf, X"09");
+    read(buf, d);
+    write(buf, X"0A");
+    read(buf, d);
+    write(buf, X"0B");
+    read(buf, d);
+    write(buf, X"0C");
+    read(buf, d);
+    write(buf, X"0D");
+    read(buf, d);
+    write(buf, X"0E");
+    read(buf, d);
+    write(buf, X"0F");
+    read(buf, d);
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/test_bench-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/test_bench-1.vhd
new file mode 100644
index 0000000..00ef8bd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/access-types/test_bench-1.vhd
@@ -0,0 +1,224 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+package stimulus_element_ordered_collection_adt is
+
+  -- template: fill in the placeholders to specialize for a particular type
+
+  alias element_type is work.stimulus_types.stimulus_element;
+  alias key_type is delay_length;
+  alias key_of is work.stimulus_types.stimulus_key [ element_type return key_type ];
+  alias "<" is std.standard."<" [ key_type, key_type return boolean ];
+
+  -- types provided by the package
+
+  type ordered_collection_object;    -- private
+  type position_object;              -- private
+
+  type ordered_collection is access ordered_collection_object;
+  type position is access position_object;
+
+  -- operations on ordered collections
+
+  function new_ordered_collection return ordered_collection;
+  -- returns an empty ordered collection of element_type values
+
+  procedure insert ( c : inout ordered_collection;  e : in element_type );
+  -- inserts e into c in position determined by key_of(e)
+
+  procedure get_element ( variable p : in position;  e : out element_type );
+  -- returns the element value at position p in its collection
+
+  procedure test_null_position ( variable p : in position;  is_null : out boolean );
+  -- test whether p refers to no position in its collection
+
+  procedure search ( variable c : in ordered_collection;  k : in key_type;
+                     p : out position );
+  -- searches for an element with key k in c, and returns the position of
+  -- that element, or, if not found, a position for which test_null_position
+  -- returns true
+
+  procedure find_first ( variable c : in ordered_collection;  p : out position );
+  -- returns the position of the first element of c
+
+  procedure advance ( p : inout position );
+  -- advances p to the next element in its collection,
+  -- or if there are no more, sets p so that test_null_position returns true
+
+  procedure delete ( p : inout position );
+  -- deletes the element at position p from its collection, and advances p
+
+  -- private types: pretend these are not visible
+
+  type ordered_collection_object is
+    record
+      element : element_type;
+      next_element, prev_element : ordered_collection;
+    end record ordered_collection_object;
+
+  type position_object is
+    record
+      the_collection : ordered_collection;
+      current_element : ordered_collection;
+    end record position_object;
+
+end package stimulus_element_ordered_collection_adt;
+
+
+
+package body stimulus_element_ordered_collection_adt is
+
+  function new_ordered_collection return ordered_collection is
+    variable result : ordered_collection := new ordered_collection_object;
+  begin
+    result.next_element := result;
+    result.prev_element := result;
+    return result;
+  end function new_ordered_collection;
+
+  procedure insert ( c : inout ordered_collection;  e : in element_type ) is
+    variable current_element : ordered_collection := c.next_element;
+    variable new_element : ordered_collection;
+  begin
+    while current_element /= c
+      and key_of(current_element.element) < key_of(e) loop
+      current_element := current_element.next_element;
+    end loop;
+    -- insert new element before current_element
+    new_element := new ordered_collection_object'(
+                         element => e,
+                         next_element => current_element,
+                         prev_element => current_element.prev_element );
+    new_element.next_element.prev_element := new_element;
+    new_element.prev_element.next_element := new_element;
+  end procedure insert;
+
+  procedure get_element ( variable p : in position;  e : out element_type ) is
+  begin
+    e := p.current_element.element;
+  end procedure get_element;
+
+  procedure test_null_position ( variable p : in position;  is_null : out boolean ) is
+  begin
+    is_null := p.current_element = p.the_collection;
+  end procedure test_null_position;
+
+  procedure search ( variable c : in ordered_collection;  k : in key_type;
+                     p : out position ) is
+    variable current_element : ordered_collection := c.next_element;
+  begin
+    while current_element /= c
+        and key_of(current_element.element) < k loop
+      current_element := current_element.next_element;
+    end loop;
+    if current_element = c or k < key_of(current_element.element) then
+      p := new position_object'(c, c);  -- null position
+    else
+      p := new position_object'(c, current_element);
+    end if;
+  end procedure search;
+
+  procedure find_first ( variable c : in ordered_collection;  p : out position ) is
+  begin
+    p := new position_object'(c, c.next_element);
+  end procedure find_first;
+
+  procedure advance ( p : inout position ) is
+    variable is_null : boolean;
+  begin
+    test_null_position(p, is_null);
+    if not is_null then
+      p.current_element := p.current_element.next_element;
+    end if;
+  end procedure advance;
+
+  procedure delete ( p : inout position ) is
+    variable is_null : boolean;
+  begin
+    test_null_position(p, is_null);
+    if not is_null then
+      p.current_element.next_element.prev_element
+        := p.current_element.prev_element;
+      p.current_element.prev_element.next_element
+        := p.current_element.next_element;
+      p.current_element := p.current_element.next_element;
+    end if;
+  end procedure delete;
+
+end package body stimulus_element_ordered_collection_adt;
+
+
+
+entity test_bench is
+end entity test_bench;
+
+-- end not in book
+
+
+architecture initial_test of test_bench is
+
+  use work.stimulus_types.all;
+
+  -- . . .    -- component and signal declarations
+
+  -- not in book
+  signal dut_signals : real_vector(0 to stimulus_vector_length - 1);
+  -- end not in book
+
+begin
+
+  -- . . .    -- instantiate design under test
+
+  stimulus_generation : process is
+
+    use work.stimulus_element_ordered_collection_adt.all;
+
+    variable stimulus_list : ordered_collection := new_ordered_collection;
+    variable next_stimulus_position : position;
+    variable next_stimulus : stimulus_element;
+    variable position_is_null : boolean;
+
+  begin
+    insert(stimulus_list, stimulus_element'(0 ns, real_vector'(0.0, 5.0, 0.0, 2.0)));
+    insert(stimulus_list, stimulus_element'(200 ns, real_vector'(3.3, 2.1, 0.0, 2.0)));
+    insert(stimulus_list, stimulus_element'(300 ns, real_vector'(3.3, 2.1, 1.1, 3.3)));
+    insert(stimulus_list, stimulus_element'(50 ns, real_vector'(3.3, 3.3, 2.2, 4.0)));
+    insert(stimulus_list, stimulus_element'(60 ns, real_vector'(5.0, 3.3, 4.0, 2.2)));
+    -- . . .
+    -- not in book
+    insert(stimulus_list, stimulus_element'(100 ns, real_vector'(0.0, 0.0, 0.0, 0.0)));
+    search(stimulus_list, 100 ns, next_stimulus_position);
+    delete(next_stimulus_position);
+    get_element(next_stimulus_position, next_stimulus);
+    -- end not in book
+    find_first(stimulus_list, next_stimulus_position);
+    loop
+      test_null_position(next_stimulus_position, position_is_null);
+      exit when position_is_null;
+      get_element(next_stimulus_position, next_stimulus);
+      wait for next_stimulus.application_time - now;
+      dut_signals <= next_stimulus.pattern;
+      advance(next_stimulus_position);
+    end loop;
+    wait;
+  end process stimulus_generation;
+
+end architecture initial_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller.vhd
new file mode 100644
index 0000000..532d65c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity DMA_controller is
+end entity DMA_controller;
+
+-- end not in book
+
+
+
+architecture behavioral of DMA_controller is
+
+  use work.DMA_controller_types_and_utilities.all;
+
+begin
+
+  behavior : process is
+
+    variable address_reg0, address_reg1 : word;
+    variable count_reg0, count_reg1 : word;
+    -- . . .
+
+  begin
+    -- . . .
+    address_reg0 := address_reg0 + X"0000_0004";
+    -- . . .
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd
new file mode 100644
index 0000000..95d300e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/DMA_controller_types_and_utilities.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package cpu_types is
+
+  constant word_size : positive := 16;
+
+  subtype word is bit_vector(word_size - 1 downto 0);
+
+  type status_value is ( halted, idle, fetch, mem_read, mem_write,
+                         io_read, io_write, int_ack );
+
+end package cpu_types;
+
+
+
+package bit_vector_unsigned_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+end package bit_vector_unsigned_arithmetic;
+
+
+package body bit_vector_unsigned_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
+
+    alias norm1 : bit_vector(1 to bv1'length) is bv1;
+    alias norm2 : bit_vector(1 to bv2'length) is bv2;
+
+    variable result : bit_vector(1 to bv1'length);
+    variable carry : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report "arguments of different length" severity failure;
+    else
+      for index in norm1'reverse_range loop
+        result(index) := norm1(index) xor norm2(index) xor carry;
+        carry := ( norm1(index) and norm2(index) )
+              or ( carry and ( norm1(index) or norm2(index) ) );
+      end loop;
+    end if;
+    return result;
+  end function "+";
+
+end package body bit_vector_unsigned_arithmetic;
+
+
+
+
+-- code from book
+
+package DMA_controller_types_and_utilities is
+
+  alias word is work.cpu_types.word;
+  alias status_value is work.cpu_types.status_value;
+
+  alias "+" is work.bit_vector_unsigned_arithmetic."+"
+            [ bit_vector, bit_vector return bit_vector ];
+
+  -- . . .
+
+end package DMA_controller_types_and_utilities;
+
+-- end code from book
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/controller_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/controller_system.vhd
new file mode 100644
index 0000000..87f5d99
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/controller_system.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+package alu_types is
+
+  constant data_width : positive := 32;
+
+end package alu_types;
+
+
+package io_types is
+
+  constant data_width : positive := 32;
+
+end package io_types;
+
+
+entity controller_system is
+end entity controller_system;
+
+-- end not in book
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.alu_types.all, work.io_types.all;
+
+architecture structural of controller_system is
+
+  alias alu_data_width is work.alu_types.data_width;
+  alias io_data_width is work.io_types.data_width;
+
+  signal alu_in1, alu_in2,
+         alu_result : std_logic_vector(0 to alu_data_width - 1);
+  signal  io_data : std_logic_vector(0 to io_data_width - 1);
+  -- . . .
+
+  -- not in book
+  -- following should not analyze: data_width not directly visible
+  -- constant test : positive := data_width;
+  -- end not in book
+
+begin
+
+  -- . . .
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/function_plus.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/function_plus.vhd
new file mode 100644
index 0000000..ddf330d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/function_plus.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package function_plus is
+
+  -- code from book (in text)
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+  -- end code from book
+
+end package function_plus;
+
+
+
+package body function_plus is
+
+  -- code from book
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
+
+    alias norm1 : bit_vector(1 to bv1'length) is bv1;
+    alias norm2 : bit_vector(1 to bv2'length) is bv2;
+
+    variable result : bit_vector(1 to bv1'length);
+    variable carry : bit := '0';
+
+  begin
+    if bv1'length /= bv2'length then
+      report "arguments of different length" severity failure;
+    else
+      for index in norm1'reverse_range loop
+        result(index) := norm1(index) xor norm2(index) xor carry;
+        carry := ( norm1(index) and norm2(index) )
+              or ( carry and ( norm1(index) or norm2(index) ) );
+      end loop;
+    end if;
+    return result;
+  end function "+";
+
+  -- end code from book
+
+end package body function_plus;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/index-ams.txt
new file mode 100644
index 0000000..9d6e755
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/index-ams.txt
@@ -0,0 +1,28 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                               Chapter 11 - Aliases
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+controller_system.vhd                           package alu_types                       --                              --
+--                                              package io_types                        --                              --
+--                                              entity controller_system                structural                      Figure 11-1
+safety_switch.vhd                               entity safety_switch                    basic                           Figure 11-2
+function_plus.vhd                               package function_plus                   body                            Figure 11-3
+DMA_controller_types_and_utilities.vhd          package cpu_types                       --                              --
+--                                              package bit_vector_unsigned_arithmetic  body                            --
+--                                              package DMA_controller_types_and_utilities  --                          Figure 11-4
+DMA_controller.vhd                              entity DMA_controller                   behavioral                      Figure 11-5
+inline_01a.vhd                                  entity inline_01a                       test                            Section 11.1
+inline_02.vhd                                   entity inline_02                        test                            Section 11.1
+inline_03a.vhd                                  entity inline_03a                       test                            Section 11.1
+inline_04.vhd                                   entity inline_04                        test                            Section 11.2
+inline_05.vhd                                   package system_types                    --                              Section 11.2
+--                                              entity inline_05                        test                            Section 11.2
+inline_06.vhd                                   package arithmetic_ops                  body                            Section 11.2
+--                                              entity inline_06                        test                            Section 11.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_function_plus.vhd                            entity tb_function_plus                 test                            tb_function_plus.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_01a.vhd
new file mode 100644
index 0000000..e2cda9e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_01a.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.mechanical_systems.all;
+                        
+entity inline_01a is
+
+end entity inline_01a;
+
+
+architecture test of inline_01a is
+
+  -- code from book
+
+  alias ground is electrical_ref;
+
+  --
+
+  alias anchor is translational_ref;
+
+  -- end code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_02.vhd
new file mode 100644
index 0000000..40c3f54
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_02.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+begin
+
+
+  process_1_a : process is
+
+    -- code from book:
+
+    type register_array is array (0 to 15) of bit_vector(31 downto 0);
+
+    type register_set is record
+        general_purpose_registers : register_array;
+        program_counter : bit_vector(31 downto 0);
+        program_status : bit_vector(31 downto 0);
+      end record;
+
+    variable CPU_registers : register_set;
+
+    alias PSW is CPU_registers.program_status;
+    alias PC is CPU_registers.program_counter;
+    alias GPR is CPU_registers.general_purpose_registers;
+
+    alias SP is CPU_registers.general_purpose_registers(15);
+
+    alias interrupt_level is PSW(30 downto 26);
+
+    -- end of code from book
+
+    procedure procedure_1_b is
+
+      -- code from book:
+
+      alias SP is GPR(15);
+
+      alias interrupt_level : bit_vector(4 downto 0) is PSW(30 downto 26);
+
+      -- end of code from book
+
+    begin
+    end procedure procedure_1_b;
+
+  begin
+    wait;
+  end process process_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_03a.vhd
new file mode 100644
index 0000000..ce51a86
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_03a.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_03a is
+
+end entity inline_03a;
+
+
+architecture test of inline_03a is
+
+  -- code from book
+
+  nature electrical_bus is
+    record
+      strobe : electrical;
+      databus : electrical_vector(0 to 7);
+    end record;
+  terminal ebus : electrical_bus;
+  quantity bus_voltages across ebus to ground;
+
+  --
+
+  alias e_strobe is bus_voltages.strobe;
+  alias e_data is bus_voltages.databus;
+
+  -- end code from book
+
+begin
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_04.vhd
new file mode 100644
index 0000000..a17356c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_04.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_04 is
+
+end entity inline_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04  is
+begin
+
+
+  process_2_a : process is
+
+    -- code from book:
+
+    alias binary_string is bit_vector;
+
+    variable s1, s2 : binary_string(0 to 7);
+    -- . . .
+
+    -- end of code from book
+
+  begin
+
+    s1 := "10101010";
+    s2 := "11110000";
+
+    -- code from book:
+
+    s1 := s1 and not s2;
+
+    -- end of code from book
+
+    wait;
+  end process process_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_05.vhd
new file mode 100644
index 0000000..8480a95
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_05.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package system_types is
+
+  -- code from book
+
+  type system_status is (idle, active, overloaded);
+
+  -- end code from book
+
+end package system_types;
+
+
+
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+  -- code from book
+
+  alias status_type is work.system_types.system_status;
+
+  -- end code from book
+
+begin
+
+
+  process_2_b : process is
+
+    variable status : status_type := idle;
+
+  begin
+    wait for 10 ns;
+    status := active;
+    wait for 10 ns;
+    status := overloaded;
+
+    wait;
+  end process process_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_06.vhd
new file mode 100644
index 0000000..70b2c2b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/inline_06.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package arithmetic_ops is
+
+  -- code from book
+
+  procedure increment ( bv : inout bit_vector;  by : in integer := 1 );
+
+  procedure increment ( int : inout integer;  by : in integer := 1 );
+
+  -- end code from book
+
+end package arithmetic_ops;
+
+
+
+package body arithmetic_ops is
+
+  procedure increment ( bv : inout bit_vector;  by : in integer := 1 ) is
+  begin
+  end procedure increment;
+
+  procedure increment ( int : inout integer;  by : in integer := 1 ) is
+  begin
+  end procedure increment;
+
+end package body arithmetic_ops;
+
+
+
+----------------------------------------------------------------
+
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+library util;  use util.stimulus_generators.all;
+
+architecture test of inline_06 is
+
+  -- code from book
+
+  alias bv_increment is work.arithmetic_ops.increment [ bit_vector, integer ];
+
+  alias int_increment is work.arithmetic_ops.increment [ integer, integer ];
+
+  alias "*" is "and" [ bit, bit return bit ];
+
+  alias "+" is "or" [ bit, bit return bit ];
+
+  alias "-" is "not" [ bit return bit ];
+
+  alias high is std.standard.'1' [ return bit ];
+
+  -- end code from book
+
+  signal a, b, c, s : bit := '0';
+  signal test_vector : bit_vector(1 to 3);
+  signal test_high : bit := high;
+
+begin
+
+  -- code from book
+
+  s <= a * b + (-a) * c;
+
+  -- end code from book
+
+  stimulus : all_possible_values ( bv => test_vector,
+				   delay_between_values => 10 ns );
+
+  (a, b, c) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd
new file mode 100644
index 0000000..fb3caad
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/safety_switch.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all, ieee_proposed.mechanical_systems.all;
+
+entity safety_switch is
+  port ( terminal neutral : electrical;
+         terminal relay_actuator : translational );
+end entity safety_switch;
+
+-- code from book
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all, ieee_proposed.mechanical_systems.all;
+
+architecture basic of safety_switch is
+  
+  quantity neutral_potential across neutral to ground;
+  quantity relay_position across relay_actuator to anchor;
+  -- ...
+  
+begin
+  -- ...
+end architecture basic;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/tb_function_plus.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/tb_function_plus.vhd
new file mode 100644
index 0000000..4acb948
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/tb_function_plus.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_function_plus is
+end entity tb_function_plus;
+
+
+architecture test of tb_function_plus is
+
+  use work.function_plus.all;
+
+begin
+
+  stimulus : process is
+    use std.textio.all;
+    variable L : line;
+  begin
+    write(L, X"0002" + X"0000");
+    writeline(output, L);
+    write(L, X"0002" + X"0005");
+    writeline(output, L);
+    write(L, X"0002" + X"FFFE");
+    writeline(output, L);
+    
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd
new file mode 100644
index 0000000..7e29c44
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/analog_switch.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity analog_switch is
+  port ( terminal n1, n2 : electrical;
+         signal control : in std_ulogic );
+end entity analog_switch;
+
+----------------------------------------------------------------
+
+architecture ideal of analog_switch is
+  quantity v across i through n1 to n2;
+begin
+  
+  if control = '1' or control = 'H' use
+    v == 0.0;
+  else
+    i == 0.0;
+  end use;
+        
+  break on control;
+        
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd
new file mode 100644
index 0000000..a8583af
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.mechanical_systems.all;
+                        
+entity ball is
+end entity ball;
+
+----------------------------------------------------------------
+
+architecture bouncer of ball is
+  quantity v : velocity := 0.0;
+  quantity s : displacement := 10.0;
+  constant g : real := 9.81;
+  constant air_res : real := 0.1;
+begin
+  
+  if v'above(0.0) use
+    v'dot == -g - v**2*air_res;
+  else
+    v'dot == -g + v**2*air_res;
+  end use;
+        
+  reversal_tester : process is
+  begin
+    wait on s'above(0.0);
+    break v => -v when s < 0.0;
+  end process reversal_tester;
+        
+  s'dot == v;
+        
+end architecture bouncer;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd
new file mode 100644
index 0000000..27d9995
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/ball_wa.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+ENTITY ball_wa IS 
+END ENTITY ball_wa; 
+
+ARCHITECTURE simple OF ball_wa IS 
+	QUANTITY v: real; 
+	QUANTITY s: real; 
+	CONSTANT G: real := 9.81; 
+	CONSTANT Air_Res: real := 0.1; 
+	SIGNAL damping: real := -0.7; 
+	signal v_at_impact : real:= 0.0; 
+	signal impact: boolean; 
+BEGIN 
+	if domain = quiescent_domain use 
+		v == 0.0; 
+		s == 30.0; 
+	elsif impact use 
+		v == damping*v_at_impact; 
+		s == 0.0; 
+	else 
+		s'dot == v; 
+		v'dot == -G; 
+	end use; 
+	process begin 
+		wait until not s'above(0.0); 
+		if v < -1.0e-9 then 
+			v_at_impact <= v; 
+			impact <= true, false after 1 us; 
+		else 
+			damping <= 0.0; 
+			impact <= true; 
+		end if; 
+	end process; 
+	break on impact; 
+END architecture simple; 
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd
new file mode 100644
index 0000000..94e7d9e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity bit_to_analog is
+  port ( d : in bit;
+         terminal a : electrical ); 
+end entity bit_to_analog;
+
+----------------------------------------------------------------
+
+architecture ideal of bit_to_analog is
+  constant v_low : real := 0.0;
+  constant v_high : real := 5.0;
+  signal v_in : real := 0.0;
+  quantity v_out across i_out through a to electrical_ref;
+begin
+  
+  v_in <= v_high when d = '1' else v_low;
+  v_out == v_in'ramp(1.0e-9);
+  
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd
new file mode 100644
index 0000000..06c3754
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/capacitor.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity capacitor is 
+  port ( terminal node1, node2 : electrical );
+end entity capacitor;
+
+architecture leakage of capacitor is
+  constant c : real := 1.0E-6;
+  constant r_leak : real := 10.0E6;
+  quantity v_cap across i_cap, i_leak through node1 to node2;
+begin
+  i_cap == c * v_cap'dot; 
+  i_leak == v_cap / r_leak;
+end architecture leakage;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd
new file mode 100644
index 0000000..c2cba71
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator-1.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library IEEE_proposed;  use IEEE_proposed.electrical_systems.all;
+                        
+entity comparator is
+  port ( terminal plus_in, minus_in : electrical;
+         signal output : out std_ulogic );
+end entity comparator;
+
+----------------------------------------------------------------
+
+architecture hysteresis of comparator is
+  
+  constant threshold_margin : real := 0.2;
+  quantity v_in across plus_in to minus_in;
+        
+begin
+  
+  comp_behavior : process is
+    variable threshold : real := threshold_margin;
+  begin
+    if v_in > threshold then
+      output <= '1' after 10 ns;
+      threshold := -threshold_margin;
+    else
+      output <= '0' after 10 ns;
+      threshold := threshold_margin;
+    end if;
+    wait on v_in'above(threshold);
+  end process comp_behavior;
+                                
+end architecture hysteresis;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd
new file mode 100644
index 0000000..3f5437f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/comparator.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity comparator is
+  port ( terminal a : electrical;
+         signal d : out std_ulogic );
+end entity comparator;
+
+----------------------------------------------------------------
+
+architecture ideal of comparator is
+  constant ref_voltage : real := 5.0;
+  quantity vin across a;
+begin
+
+  comparator_behavior : process is
+  begin
+    if vin > ref_voltage / 2.0 then
+      d <= '1' after 5 ns;
+    else
+      d <= '0' after 5 ns;
+    end if;
+    wait on vin'above(ref_voltage / 2.0);
+  end process comparator_behavior;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd
new file mode 100644
index 0000000..b4fa8b7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/control_system.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity control_system is
+  port ( quantity feedback, target : in voltage;
+         quantity output : out voltage );
+end entity control_system;
+
+----------------------------------------------------------------
+
+architecture simple_feedback of control_system is
+  constant gain : real := 2.0;
+begin
+  output == gain * ( target - feedback );
+end architecture simple_feedback;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd
new file mode 100644
index 0000000..5d762e8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/dac_12_bit.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity dac_12_bit is
+  port ( signal  bus_in : in std_ulogic_vector (11 downto 0); 
+         terminal analog_out :  electrical );
+end entity dac_12_bit;
+
+----------------------------------------------------------------
+
+architecture behavioral of dac_12_bit is
+  
+  constant v_max : real := 3.3;
+  signal s_out : real := 0.0;
+  quantity v_out across i_out through analog_out to electrical_ref;
+        
+begin
+  
+  convert : process ( bus_in ) is
+    variable sum : natural;
+  begin
+    sum  := 0;
+    for i in bus_in'range loop
+      sum := sum * 2 + boolean'pos( bus_in(i) = '1' or bus_in(i) = 'H' );
+    end loop;
+    s_out <= v_max * real(sum) / real(2**12 - 1);
+  end process convert;
+                                     
+  v_out == s_out'ramp(1.0E-6);
+                                     
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd
new file mode 100644
index 0000000..aeb24de
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/diode.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee, ieee_proposed;
+use ieee.math_real.all;
+use ieee_proposed.energy_systems.all;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.thermal_systems.all;
+
+entity diode is
+  port ( terminal p, m : electrical;
+         terminal j : thermal );
+end entity diode;
+
+----------------------------------------------------------------
+
+architecture one of diode is
+  
+  constant area : real := 1.0e-3;
+  constant Dn : real := 30.0; 		-- electron diffusion coefficient
+  constant Dp : real := 15.0; 		-- hole diffusion coefficient
+  constant np : real := 6.77e-5;	-- minority charge density
+  constant pn : real := 6.77e-6;	-- minority charge density
+  constant Ln : real := 5.47e-6;	-- diffusion length for electrons
+  constant Lp : real := 12.25e-6;	-- diffusion length for holes
+  quantity v across id through p to m;
+  quantity vt : voltage := 1.0;		-- threshold voltage
+  quantity temp across power through j;
+        
+begin
+  
+  vt == temp * K / Q;
+  
+  id == Q * area * (Dp * (pn / Lp) + Dn * (np / Ln)) * (exp(v / vt) - 1.0);
+
+  power == v * id;
+  
+end architecture one;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/index-ams.txt
new file mode 100644
index 0000000..887fe94
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/index-ams.txt
@@ -0,0 +1,84 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                      Chapter 6 - Analog Modeling Constructs
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+control_system.vhd                              entity control_system                   simple_feedback                 Figure 6-2
+comparator.vhd                                  entity comparator                       ideal                           Figure 6-9
+variable_comparator.vhd                         entity variable_comparator              ideal                           Figure 6-10
+transmission_line.vhd                           entity transmission_line                abstract                        Figure 6-11
+transmission_line_wa.vhd                        entity transmission_line_wa             abstract                        --
+inductor.vhd                                    entity inductor                         ideal                           Figure 6-12
+piston.vhd                                      entity piston                           simple                          Figure 6-13
+inductor-1.vhd                                  entity inductor                         integral_form                   Figure 6-14
+moving_mass.vhd                                 entity moving_mass                      behavioral                      Figure 6-15
+moving_mass_wa.vhd                              entity moving_mass_wa                   behavioral                      --
+opamp.vhd                                       entity opamp                            slew_limited                    Figure 6-17
+quad_opamp.vhd                                  entity quad_opamp                       slew_limited                    Figure 6-19
+quad_opamp_wa.vhd                               entity quad_opamp_wa                    slew_limited                    --
+bit_to_analog.vhd                               entity bit_to_analog                    ideal                           Figure 6-21
+std_logic_to_analog.vhd                         entity std_logic_to_analog              ideal                           Figure 6-23
+opamp-1.vhd                                     entity opamp                            saturating                      Figure 6-24
+opamp_wa-1.vhd                                  entity opamp_wa                         saturating                      --
+resistor.vhd                                    entity resistor                         ideal                           Figure 6-26
+capacitor.vhd                                   entity capacitor                        leakage                         Figure 6-26
+inverting_integrator.vhd                        entity inverting_integrator             structural                      Figure 6-27
+timer.vhd                                       entity timer                            behavioral                      Figure 6-29
+ball.vhd                                        entity ball                             bouncer                         Figure 6-30
+ball_wa.vhd                                     entity ball_wa                          simple                          --
+analog_switch.vhd                               entity analog_switch                    ideal                           Figure 6-31
+pendulum.vhd                                    entity pendulum                         constrained                     Figure 6-33
+pendulum_wa.vhd                                 entity pendulum_wa                      constrained                     --
+triangle_waveform.vhd                           entity triangle_waveform                ideal                           Figure 6-34
+triangle_waveform_wa.vhd                        entity triangle_waveform_wa             ideal                           --
+comparator-1.vhd                                entity comparator                       hysteresis                      Figure 6-35
+dac_12_bit.vhd                                  entity dac_12_bit                       behavioral                      Figure 6-36
+diode.vhd                                       entity diode                            one                             Figure 6-38
+inline_01a.vhd                                  entity inline_01a                       test                            Section 6.1
+inline_02a.vhd                                  entity inline_02a                       test                            Section 6.1
+inline_03a.vhd                                  entity temperature_dependent_resistor   linear_approx                   Section 6.1
+inline_04a.vhd                                  entity inline_04a                       test                            Section 6.2
+inline_05a.vhd                                  entity inline_05a                       test                            Section 6.2
+inline_06a.vhd                                  entity inline_06a                       test                            Section 6.2
+inline_07a.vhd                                  entity battery                          --                              Section 6.2
+--                                              entity ADC                              --                              Section 6.2
+--                                              entity diode_thermal                    --                              Section 6.2
+inline_08a.vhd                                  entity inline_08a                       test                            Section 6.3
+inline_09a.vhd                                  entity inline_09a                       test                            Section 6.4
+inline_10a.vhd                                  entity inline_10a                       test                            Section 6.4
+inline_11a.vhd                                  entity inline_11a                       test                            Section 6.4
+inline_12a.vhd                                  entity inline_12a                       test                            Section 6.4
+inline_13a.vhd                                  entity inline_13a                       test                            Section 6.4
+inline_14a.vhd                                  entity inline_14a                       test                            Section 6.4
+inline_15a.vhd                                  entity inline_15a                       test                            Section 6.5
+inline_16a.vhd                                  package inline_16a_types                --                              Section 6.5
+--                                              entity seven_segment_led                basic_optics                    Section 6.5
+--                                              entity inline_16a                       test                            Section 6.5
+inline_17a.vhd                                  entity adc_with_ref                     signal_flow                     Section 6.5
+--                                              entity inline_17a                       test                            Section 6.5
+inline_18a.vhd                                  entity inline_18a                       test                            Section 6.6
+inline_19a.vhd                                  entity inline_19a                       test                            Section 6.6
+inline_20a.vhd                                  entity inline_20a                       test                            Section 6.6
+inline_21a.vhd                                  entity inline_21a                       test                            Section 6.7
+inline_22a.vhd                                  entity inline_22a                       test                            Section 6.8
+inline_23a.vhd                                  entity inline_23a                       test                            Section 6.8
+inline_24a.vhd                                  entity inline_24a                       test                            Section 6.9
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_control_system.vhd                           entity tb_control_system                TB_control_system               control_system.vhd
+tb_comparator.vhd                               entity tb_comparator                    TB_comparator                   comparator.vhd
+tb_variable_comparator.vhd                      entity tb_variable_comparator           TB_variable_comparator          variable_comparator.vhd
+tb_transmission_line.vhd                        entity tb_transmission_line             TB_transmission_line            transmission_line_wa.vhd
+tb_piston.vhd                                   entity tb_piston                        TB_piston                       piston.vhd
+tb_moving_mass.vhd                              entity tb_moving_mass                   TB_moving_mass                  moving_mass_wa.vhd
+tb_quad_opamp.vhd                               entity tb_quad_opamp                    TB_quad_opamp                   quad_opamp_wa.vhd
+tb_bit_to_analog.vhd                            entity tb_bit_to_analog                 TB_bit2analog                   bit_to_analog.vhd
+tb_std_logic_to_analog.vhd                      entity tb_std_logic_to_analog           TB_std_logic2analog             std_logic_to_analog.vhd
+tb_inv_integrator.vhd                           entity tb_inv_integrator                TB_inv_integrator               inverting_integrator.vhd
+tb_analog_switch.vhd                            entity tb_analog_switch                 TB_analog_switch                analog_switch.vhd
+tb_triangle_waveform.vhd                        entity tb_triangle_waveform             TB_triangle_waveform            triangle_waveform.vhd
+tb_comparator-1.vhd                             entity tb_comparator                    TB_comparator                   comparator-1.vhd
+tb_diode.vhd                                    entity tb_diode                         TB_diode                        diode.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd
new file mode 100644
index 0000000..15d12f2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor-1.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inductor is
+  port (terminal n1, n2: electrical);
+end entity inductor;
+
+----------------------------------------------------------------
+
+architecture integral_form of inductor is
+  constant L: inductance := 0.5;
+  quantity branch_voltage across branch_current through n1 to n2;
+begin
+  branch_current == branch_voltage'integ / L;
+end architecture integral_form;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd
new file mode 100644
index 0000000..9f3fbd2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inductor.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inductor is
+  port (terminal n1, n2: electrical);
+end entity inductor;
+
+----------------------------------------------------------------
+
+architecture ideal of inductor is
+  constant L: inductance := 0.5;
+  quantity branch_voltage across branch_current through n1 to n2;
+begin
+  branch_voltage == L* branch_current'dot;
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd
new file mode 100644
index 0000000..d6b0709
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_01a.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01a is
+
+end entity inline_01a;
+
+
+architecture test of inline_01a is
+
+  quantity capacitor_voltage : real;
+  constant capacitance : real := 1.0e-9;
+
+  subtype current is real;
+  
+  -- code from book
+
+  subtype charge is real tolerance "default_charge";
+  quantity capacitor_charge : charge;
+
+  --
+
+  quantity engine_power : real tolerance "approximate_power";
+
+  --
+
+  quantity I_sense : current := 0.15; -- initial value is 150mA
+
+  --
+
+  quantity amplifier_gains : real_vector (3 downto 0) := (1.0, 1.0, 1.0, 0.5);
+
+  -- end code from book
+
+begin
+
+  -- code from book
+
+  capacitor_charge == capacitor_voltage * capacitance;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd
new file mode 100644
index 0000000..c46a6a0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_02a.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+architecture test of inline_02a is
+begin
+
+  block_1 : block is
+
+    -- code from book
+
+    quantity input1, input2, output : real;
+    quantity amplified_input1, amplified_input2 : real;
+
+    constant gain1 : real := 2.0;
+    constant gain2 : real := 4.0;
+
+    -- end code from book
+
+  begin
+
+    -- code from book
+
+    amplified_input1 == input1 * gain1;
+    amplified_input2 == input2 * gain2;
+    output == amplified_input1 * amplified_input2;
+
+    -- end code from book
+
+  end block block_1;
+
+
+  block_2 : block is
+
+    quantity input1, input2, output : real;
+
+    constant gain1 : real := 2.0;
+    constant gain2 : real := 4.0;
+
+  begin
+
+    -- code from book
+
+    output == input1 * gain1 * input2 * gain2;
+
+    -- end code from book
+
+  end block block_2;
+
+  
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd
new file mode 100644
index 0000000..b73e207
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_03a.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.thermal_systems.all;
+
+entity temperature_dependent_resistor is
+  port ( terminal n1, n2 : electrical;
+         quantity temp : in temperature );
+end entity temperature_dependent_resistor;
+
+architecture linear_approx of temperature_dependent_resistor is
+  constant resistance_at_0 : real := 1.0E6;
+  constant resistance_drop_per_kelvin : real := 100.0;
+  quantity resistance : real;
+  quantity V across I through n1 to n2;
+begin
+  resistance == resistance_at_0 - temp * resistance_drop_per_kelvin;
+  V == I * resistance;
+end architecture linear_approx;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd
new file mode 100644
index 0000000..9050b0d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_04a.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+architecture test of inline_04a is
+begin
+
+  block_1 : block is
+
+    -- code from book
+
+    subtype voltage is real tolerance "low_voltage";
+    subtype current is real tolerance "low_current";
+    nature electrical is voltage across current through electrical_ref reference;
+    terminal anode, cathode : electrical;
+
+    --
+
+    subtype illuminance is real tolerance "default_illuminance";
+    subtype optic_flux is real tolerance "default_optic_flux";
+    nature radiant is illuminance across optic_flux through radiant_ref reference;
+    terminal light_bulb, light_emitting_diode : radiant;
+
+    --
+
+    nature electrical_vector is array (natural range <>) of electrical;
+    terminal a_bus : electrical_vector(1 to 8);
+
+    --
+
+    quantity light_illuminance across light_bulb;
+    quantity LED_flux through light_emitting_diode;
+
+    -- end code from book
+
+    terminal n1, n2 : electrical;
+
+    -- code from book
+
+    quantity voltage_drop across
+             inductive_current, capacitive_current, resistive_current through
+             n1 to n2;
+ 
+    -- end code from book
+
+  begin
+  end block block_1;
+
+
+
+  block_2 : block is
+
+    subtype voltage is real tolerance "low_voltage";
+    subtype current is real tolerance "low_current";
+    nature electrical is voltage across current through electrical_ref reference;
+
+    -- code from book
+
+    terminal anode, cathode : electrical;
+
+    --
+
+    quantity battery_voltage across battery_current through anode to cathode;
+    quantity leakage_voltage across leakage_current through anode;
+
+    -- end code from book
+
+  begin
+  end block block_2;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd
new file mode 100644
index 0000000..f0ed183
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_05a.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity inline_05a is
+
+end entity inline_05a;
+
+
+architecture test of inline_05a is
+
+begin
+
+  block_1 : block is
+
+    constant cap : real := 1.0e-9;
+    constant rleak : real := 1.0E6;
+
+    -- code from book
+
+    terminal p1, p2 : electrical;
+    quantity vcap across icap, ileak through p1 to p2;
+
+    -- end code from book
+
+  begin
+
+    -- code from book
+
+    icap == cap * vcap'dot;
+  
+    ileak == vcap / rleak;
+
+    -- end code from book
+
+  end block block_1;
+
+
+  block_2 : block is
+
+    -- code from book
+
+    nature electrical_vector is array (natural range <>) of electrical;
+    terminal a_bus : electrical_vector(1 to 8);
+    terminal signal_ground : electrical;
+
+    --
+
+    quantity bus_drops across bus_currents through a_bus to signal_ground;
+
+    --
+
+    terminal p1 : electrical_vector(0 to 3);
+    terminal p2 : electrical;
+  
+    quantity v across i through p1 to p2;
+
+    --
+
+    constant tc1 : real := 1.0e-3; -- Linear temperature coefficient
+    constant tc2 : real := 1.0e-6; -- Second-order temperature coefficient
+    constant temp : real := 27.0; -- Ambient temperature
+    constant tnom : real := 50.0; -- Nominal temperature
+    constant res : real_vector := (1.0e3, 2.0e3, 4.0e3, 8.0e3); -- Nominal resistances
+
+    --
+
+    constant res_factor : real := (1.0 + tc1*(temp-tnom) + tc2*(temp-tnom)**2);
+
+    -- end code from book
+
+  begin
+
+    -- code from book
+
+    v(0) == i(0) * res(0) * res_factor;
+    v(1) == i(1) * res(1) * res_factor;
+    v(2) == i(2) * res(2) * res_factor;
+    v(3) == i(3) * res(3) * res_factor;
+
+    -- end code from book
+
+  end block block_2;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd
new file mode 100644
index 0000000..0c69a05
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_06a.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity inline_06a is
+
+end entity inline_06a;
+
+
+architecture test of inline_06a is
+
+  -- code from book
+
+  terminal a_bus : electrical_vector(1 to 8);
+  terminal b_bus : electrical_vector(8 downto 1);
+
+  --
+
+  quantity a_to_b_drops across a_to_b_currents through a_bus to b_bus;
+
+  --
+
+  nature electrical_bus is
+    record
+      strobe: electrical;
+      databus : electrical_vector(0 to 7);
+    end record;
+  
+  terminal t1, t2 : electrical_bus;
+
+  --
+
+  quantity bus_voltages across t1 to t2;
+
+  --
+
+  terminal p1, p2 : electrical_vector(0 to 3);
+  
+  quantity v across i through p1 to p2;
+
+  -- end code from book
+
+
+begin
+
+  block_1 : block is
+                    
+    terminal anode, cathode : electrical;
+
+    -- code from book
+
+    quantity battery_voltage tolerance "battery_tolerance" across
+             battery_current tolerance "battery_tolerance" through anode to cathode;
+
+    -- end code from book
+
+  begin
+  end block block_1;
+
+
+  block_2 : block is
+                    
+    terminal anode, cathode : electrical;
+
+    -- code from book
+
+    quantity battery_volts := 5.0 across
+             battery_amps := 0.0 through
+             anode to cathode;
+
+    -- end code from book
+
+  begin
+  end block block_2;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd
new file mode 100644
index 0000000..e126536
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_07a.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity battery is
+  port ( terminal anode, cathode : electrical );
+end entity battery;
+
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity ADC is
+  port ( terminal a : electrical;
+         signal d : out bit );
+end entity ADC;
+
+
+
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all, ieee_proposed.thermal_systems.all;
+
+entity diode_thermal is
+  port ( terminal p, m : electrical;
+         terminal j : thermal );
+end entity diode_thermal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd
new file mode 100644
index 0000000..9915d4f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_08a.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_08a is
+
+end entity inline_08a;
+
+
+architecture test of inline_08a is
+
+  -- code from book
+
+  terminal bias_node : electrical;
+
+  --
+
+  subnature accurate_electrical is electrical
+    tolerance "accurate_voltage" across "accurate_current" through;
+
+  --
+
+  terminal n1, n2 : accurate_electrical;
+
+  --
+
+  quantity n1_n2_voltage across n1_n2_current through n1 to n2;
+
+  --
+
+  quantity internal_voltage : voltage tolerance n1_n2_voltage'tolerance;
+  quantity internal_current : current tolerance n1_n2_current'tolerance;
+
+  --
+
+  terminal bus_a_end, bus_b_end : electrical_vector(15 downto 0);
+  quantity bus_currents through bus_a_end to bus_b_end;
+
+  -- end code from book
+
+begin
+
+  -- code from book
+
+  bias_node'reference == 0.5;
+
+  -- end code from book
+  
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd
new file mode 100644
index 0000000..fc3e334
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_09a.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.mechanical_systems.all;
+                        
+entity inline_09a is
+
+end entity inline_09a;
+
+
+architecture test of inline_09a is
+
+
+  constant R : real := 1.0e3;
+  constant k : real := 10.0;
+
+  -- code from book
+
+  terminal p, m : electrical;
+  quantity v across i through p to m;
+
+  --
+
+  terminal node1, node2 : translational;
+  quantity d across f through node1 to node2;
+
+  -- end code from book
+
+begin
+
+  -- code from book
+
+  v == i * R;
+
+  --
+
+  f == d * k;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd
new file mode 100644
index 0000000..a6c3191
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_10a.vhd
@@ -0,0 +1,217 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_10a is
+
+end entity inline_10a;
+
+
+architecture test of inline_10a is
+
+  constant R : real := 10_000.0;
+  constant R1 : real := 10_000.0;
+  constant R2 : real := 10_000.0;
+
+  -- code from book
+
+  nature electrical_bus is
+    record
+      strobe: electrical;
+      databus : electrical_vector(0 to 7);
+    end record;
+
+  -- end code from book
+
+begin
+
+  block_1 : block is
+
+    -- code from book
+
+    terminal bus_end1, bus_end2 : electrical_bus;
+    quantity bus_v across bus_i through bus_end1 to bus_end2;
+
+    -- end code from book
+
+  begin
+
+    -- code from book
+
+    bus_v == bus_i * R;
+
+    -- end code from book
+
+  end block block_1;
+
+
+  block_2 : block is
+
+    terminal bus_end1, bus_end2 : electrical_bus;
+    quantity bus_v across bus_i through bus_end1 to bus_end2;
+
+  begin
+
+    -- code from book
+
+    bus_v.strobe == bus_i.strobe * R;
+    bus_v.databus(0) == bus_i.databus(0) * R;
+    bus_v.databus(1) == bus_i.databus(1) * R;
+    --  ...
+    -- not in book
+    bus_v.databus(2) == bus_i.databus(2) * R;
+    bus_v.databus(3) == bus_i.databus(3) * R;
+    bus_v.databus(4) == bus_i.databus(4) * R;
+    bus_v.databus(5) == bus_i.databus(5) * R;
+    bus_v.databus(6) == bus_i.databus(6) * R;
+    -- end not in book
+    bus_v.databus(7) == bus_i.databus(7) * R;
+
+    -- end code from book
+
+  end block block_2;
+
+
+  block_3 : block is
+
+    terminal p, m : electrical;
+    quantity v across i through p to m;
+
+  begin
+
+    -- code from book
+
+    v == i * R;
+
+    -- end code from book
+
+  end block block_3;
+
+
+  block_4 : block is
+
+    terminal p, m : electrical;
+    quantity v across i through p to m;
+
+  begin
+
+    -- code from book
+
+    v / R == i;
+
+    -- end code from book
+
+  end block block_4;
+
+
+  block_5 : block is
+
+    terminal bus_end1, bus_end2 : electrical_bus;
+    quantity bus_v across bus_i through bus_end1 to bus_end2;
+
+  begin
+
+    -- code from book
+
+    bus_v.strobe == bus_i.strobe * R;
+    bus_v.databus(0) == bus_i.databus(0) * R;
+
+    -- end code from book
+
+    bus_v.databus(1) == bus_i.databus(1) * R;
+    bus_v.databus(2) == bus_i.databus(2) * R;
+    bus_v.databus(3) == bus_i.databus(3) * R;
+    bus_v.databus(4) == bus_i.databus(4) * R;
+    bus_v.databus(5) == bus_i.databus(5) * R;
+    bus_v.databus(6) == bus_i.databus(6) * R;
+    bus_v.databus(7) == bus_i.databus(7) * R;
+
+  end block block_5;
+
+
+  block_6 : block is
+
+    terminal p1, m1, p2, m2 : electrical;
+    quantity v1 across i1 through p1 to m1;
+    quantity v2 across i2 through p2 to m2;
+
+  begin
+
+    -- code from book
+
+    i1 * R1 == i2 * R2; -- illegal
+
+    -- end code from book
+
+  end block block_6;
+
+
+  block_7 : block is
+
+    terminal p1, m1, p2, m2 : electrical;
+    quantity v1 across i1 through p1 to m1;
+    quantity v2 across i2 through p2 to m2;
+
+  begin
+
+    -- code from book
+
+    i1 * R1 == i2 * R2 tolerance "current_tolerance";
+
+    -- end code from book
+
+  end block block_7;
+
+
+  block_8 : block is
+
+    terminal p1, m1, p2, m2 : electrical;
+    quantity v1 across i1 through p1 to m1;
+    quantity v2 across i2 through p2 to m2;
+
+  begin
+
+    -- code from book
+
+    i1 * R1 == i2 * R2 tolerance i2'tolerance;
+
+    -- end code from book
+
+  end block block_8;
+
+
+  block_9 : block is
+
+    terminal p, m : electrical;
+    quantity v across i through p to m;
+
+  begin
+
+    -- code from book
+
+    v == i * R tolerance i'tolerance;
+
+    -- end code from book
+
+  end block block_9;
+
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd
new file mode 100644
index 0000000..67589bc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_11a.vhd
@@ -0,0 +1,98 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_11a is
+
+end entity inline_11a;
+
+
+architecture test of inline_11a is
+
+  constant v_pos : voltage := 15.0;
+  constant v_neg : voltage := -15.0;
+  terminal input : electrical;
+  quantity v_in across input;
+  quantity v_amplified : voltage;
+  constant gain : real := 1.0;
+
+  constant threshold_voltage : voltage := 0.6;
+  constant k : real := 0.0125;
+  terminal gate, source, drain : electrical;
+  quantity vds across ids through drain to source;
+  quantity vsd across source to drain;
+  quantity vgs across gate to source;
+  quantity vgd across gate to drain;
+  
+  constant r_charge : resistance := 10_000.0;
+  constant r_discharge : resistance := 10_000.0;
+  constant charging : boolean := true;
+  terminal cap, plus, minus : electrical;
+  quantity v_plus := 10.0 across plus;
+  quantity v_minus := 0.0 across minus;
+  quantity v_cap across cap;
+  quantity i_charge through plus to cap;
+  quantity i_discharge through cap to minus;
+
+begin
+
+  -- code from book
+
+  if v_in * gain > v_pos use -- incorrect
+    v_amplified == v_pos;
+  elsif v_in * gain < v_neg use -- incorrect
+    v_amplified == v_neg;
+  else
+    v_amplified == gain * v_in;
+  end use;
+
+  --
+
+  if vds'above(0.0) use -- transistor is forward biased
+    if not vgs'above(threshold_voltage) use -- cutoff region
+      ids == 0.0;
+    elsif vds'above(vgs - threshold_voltage) use -- saturation region
+      ids == 0.5 * k * (vgs - threshold_voltage)**2;
+    else -- linear/triode region
+      ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
+    end use;
+  else -- transistor is reverse biased
+    if not vgd 'above(threshold_voltage) use -- cutoff region
+      ids == 0.0;
+    elsif vsd'above(vgd - threshold_voltage) use -- saturation region
+      ids == -0.5 * k * (vgd - threshold_voltage)**2;
+    else -- linear/triode region
+      ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
+    end use;
+  end use;
+
+  --
+
+  if charging use
+    i_charge == ( v_plus - v_cap ) / r_charge;
+    i_discharge == 0.0;
+  else
+    i_charge == 0.0;
+    i_discharge == ( v_cap - v_minus ) / r_discharge;
+  end use;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd
new file mode 100644
index 0000000..a9c08e4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_12a.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_12a is
+
+end entity inline_12a;
+
+
+architecture test of inline_12a is
+
+  -- code from book
+
+  type biases is (forward, reverse);
+  type regions is (cutoff, saturation, linear);
+  
+  signal bias : biases;
+  signal region : regions;
+
+  -- end code from book
+
+  constant threshold_voltage : voltage := 0.6;
+  constant k : real := 0.0125;
+  terminal gate, source, drain : electrical;
+  quantity vds across ids through drain to source;
+  quantity vsd across source to drain;
+  quantity vgs across gate to source;
+  quantity vgd across gate to drain;
+  
+begin
+
+  -- code from book
+
+  case bias use
+    when forward =>
+      case region use
+        when cutoff =>
+          ids == 0.0;
+        when saturation =>
+          ids == 0.5 * k * (vgs - threshold_voltage)**2;
+        when linear =>
+          ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
+      end case;
+    when reverse =>
+      case region use
+        when cutoff =>
+          ids == 0.0;
+        when saturation =>
+          ids == -0.5 * k * (vgd - threshold_voltage)**2;
+        when linear =>
+          ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
+      end case;
+  end case;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd
new file mode 100644
index 0000000..d2a9c79
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_13a.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_13a is
+
+end entity inline_13a;
+
+
+architecture test of inline_13a is
+
+  -- code from book
+
+  quantity v : voltage;
+  -- ...
+
+  -- end code from book
+
+begin
+
+  -- code from book
+
+  if v'above(0.0) and not v'above(0.6) use
+    -- ...
+  elsif v'above(0.6) and not v'above(2.7) use
+    -- ...
+  else
+    -- ...
+  end use;
+
+  --
+
+  case v use -- illegal
+    when 0.0 to 0.6 =>
+      -- ...;
+    when 0.6 to 2.7 =>
+      --...;
+    when others =>
+      --...;
+  end case;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd
new file mode 100644
index 0000000..db70d94
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_14a.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_14a is
+
+end entity inline_14a;
+
+
+architecture test of inline_14a is
+
+  terminal p : electrical;
+  quantity v across i through p;
+  constant R : resistance := 10_000.0;
+
+  type modeling_mode_type is (ideal, non_ideal);
+  constant modeling_mode : modeling_mode_type := ideal;
+
+begin
+
+  -- code from book
+
+  if modeling_mode = ideal use
+    v == i * R;
+  else
+    null; -- still need to include resistor with thermal effects!
+  end use;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd
new file mode 100644
index 0000000..639e7a4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_15a.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.thermal_systems.all;
+                        
+entity inline_15a is
+
+end entity inline_15a;
+
+
+architecture test of inline_15a is
+
+  -- code from book
+
+  terminal bridge1, bridge2 : electrical;
+  quantity ambient : temperature;
+
+  -- end code from book
+
+begin
+
+  ambient == 300.0;
+
+  -- code from book
+
+  resistor1 : entity work.temperature_dependent_resistor(linear_approx)
+    port map ( n1 => bridge1, n2 => bridge2, temp => ambient );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd
new file mode 100644
index 0000000..7cb1801
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_16a.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package inline_16a_types is
+
+   subtype ILLUMINANCE is REAL tolerance "DEFAULT_ILLUMINANCE";
+   subtype OPTIC_FLUX  is REAL tolerance "DEFAULT_OPTIC_FLUX";
+
+   nature RADIANT is
+      ILLUMINANCE across
+      OPTIC_FLUX  through
+      RADIANT_REF reference;
+
+   subtype VOLTAGE     is REAL tolerance "DEFAULT_VOLTAGE";
+   subtype CURRENT     is REAL tolerance "DEFAULT_CURRENT";
+
+   nature ELECTRICAL is
+      VOLTAGE        across
+      CURRENT        through
+      ELECTRICAL_REF reference;
+
+  -- code from book
+
+  type illuminance_vector is array ( natural range <> ) of illuminance;
+  nature electrical_vector is array ( natural range <> ) of electrical;
+
+  -- end code from book
+
+end package inline_16a_types;
+
+
+
+use work.inline_16a_types.all;
+
+-- code from book
+
+entity seven_segment_led is
+  port ( terminal segment_anodes : electrical_vector ( 1 to 7 );
+         terminal common_cathode : electrical;
+         quantity segment_illuminances : out illuminance_vector ( 1 to 7 ) );
+end entity seven_segment_led;
+
+-- end code from book
+
+
+
+architecture basic_optics of seven_segment_led is
+begin
+end architecture basic_optics;
+
+
+                        
+use work.inline_16a_types.all;
+
+entity inline_16a is
+
+end entity inline_16a;
+
+
+architecture test of inline_16a is
+
+  -- code from book
+
+  terminal hour_anode_2, hour_anode_3 : electrical;
+  terminal anodes_unused : electrical_vector(1 to 5);
+  terminal hour_display_source_2, hour_display_source_3 : radiant;
+  quantity hour_illuminance_2 across hour_display_source_2;
+  quantity hour_illuminance_3 across hour_display_source_3;
+  quantity illuminances_unused : illuminance_vector(1 to 5);
+
+  -- end code from book
+
+begin
+
+  -- code from book
+
+  hour_digit : entity work.seven_segment_led(basic_optics)
+    port map ( segment_anodes(2) => hour_anode_2,
+               segment_anodes(3) => hour_anode_3,
+               segment_anodes(1) => anodes_unused(1),
+               segment_anodes(4 to 7) => anodes_unused(2 to 5),
+               common_cathode => electrical_ref,
+               segment_illuminances(2) => hour_illuminance_2,
+               segment_illuminances(3) => hour_illuminance_3,
+               segment_illuminances(1) => illuminances_unused(1),
+               segment_illuminances(4 to 7) => illuminances_unused(2 to 5) );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd
new file mode 100644
index 0000000..08dbf5d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_17a.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity adc_with_ref is
+  port ( quantity v_in : in voltage;
+         signal d_out : out bit;
+         quantity v_ref : in voltage := 1.0 );
+end entity adc_with_ref;
+
+-- end code from book
+
+
+architecture signal_flow of adc_with_ref is
+begin
+end architecture signal_flow;
+
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_17a is
+
+end entity inline_17a;
+
+
+architecture test of inline_17a is
+
+begin
+
+  block_1 : block is
+
+    quantity sensor_in : voltage;
+    signal sensor_data_out : bit;
+
+  begin
+    
+    sensor_in == 5.0;
+
+    -- code from book
+
+    default_adc : entity work.adc_with_ref(signal_flow)
+      port map ( sensor_in, sensor_data_out );
+
+    -- end code from book
+
+  end block block_1;
+
+
+  block_2 : block is
+
+    quantity sensor_in : voltage;
+    signal sensor_data_out : bit;
+    constant v_supply : voltage := 10.0;
+
+  begin
+    
+    sensor_in == 5.0;
+
+    -- code from book
+
+    fixed_adc : entity work.adc_with_ref(signal_flow)
+      port map ( sensor_in, sensor_data_out, v_ref => v_supply / 2.0 );
+
+    -- end code from book
+
+  end block block_2;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd
new file mode 100644
index 0000000..00d7390
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_18a.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_18a is
+
+end entity inline_18a;
+
+
+architecture test of inline_18a is
+
+begin
+
+  process is
+  begin
+
+    -- code from book
+
+    break;
+
+    -- end code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd
new file mode 100644
index 0000000..2e95900
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_19a.vhd
@@ -0,0 +1,110 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_19a is
+
+end entity inline_19a;
+
+
+architecture test of inline_19a is
+
+  signal reset, trigger_n : std_ulogic;
+  terminal rc_ext : electrical;
+  quantity v_rc_ext across rc_ext;
+  constant half_vdd : voltage := 2.5;
+  
+begin
+
+  block_1 : block is
+
+    signal q, q_n : std_ulogic;
+
+  begin
+
+    process is
+    begin
+
+      -- code from book
+
+      -- ...
+      if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
+        q <= '0'; q_n <= '1';
+        break;
+      elsif trigger_n = '0' or trigger_n = 'L' then
+        q <= '1'; q_n <= '0';
+        break;
+      end if;
+      -- ...
+
+      -- end code from book
+
+      wait;
+    end process;
+
+  end block block_1;
+
+
+  block_2 : block is
+
+    signal q, q_n : std_ulogic;
+
+  begin
+
+    process is
+    begin
+
+      -- code from book
+
+      q_n <= '1' after 20 ns;
+      break;
+ 
+      -- end code from book
+
+      wait;
+    end process;
+
+  end block block_2;
+
+
+  block_3 : block is
+
+    signal q, q_n : std_ulogic;
+
+  begin
+
+    process is
+    begin
+
+      -- code from book
+
+      q_n <= '1';
+      break;
+
+      -- end code from book
+
+      wait;
+    end process;
+
+  end block block_3;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd
new file mode 100644
index 0000000..8b6b66c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_20a.vhd
@@ -0,0 +1,315 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.mechanical_systems.all;
+                        
+entity inline_20a is
+
+end entity inline_20a;
+
+
+architecture test of inline_20a is
+
+  signal trigger, discharge, clk : bit;
+  constant capacitance : real := 1.0e-9;
+
+begin
+
+
+  block_1 : block is
+
+    terminal cap : electrical;
+    quantity v_cap across i_cap through cap;
+    
+  begin
+
+    -- code from book
+  
+    i_cap == capacitance * v_cap'dot;
+
+    --
+
+    trigger_reset : process (trigger) is
+    begin
+      if trigger = '1' then
+        break v_cap => 0.0;
+      end if;
+    end process trigger_reset;
+
+    -- end code from book
+
+  end block block_1;
+
+
+  block_2 : block is
+
+    constant mass : real := 1.0;
+    terminal n : translational_v;
+    quantity v across n;
+    quantity applied_force : real;
+    quantity acceleration : real;
+
+    quantity vx, vy : real;
+
+  begin
+
+    acceleration == v'dot;
+    
+    -- code from book
+
+    applied_force == mass * acceleration;
+
+    -- end code from book
+
+    process is
+    begin
+
+      -- code from book
+
+      break acceleration'integ => - acceleration'integ;
+
+      --
+
+      break vx => 0.0, vy => 0.0;
+      
+      -- end code from book
+
+      wait;
+    end process;
+
+  end block block_2;
+
+
+  block_3 : block is
+
+    terminal cap : electrical;
+    quantity v_cap across i_cap through cap;
+    
+  begin
+
+    i_cap == capacitance * v_cap'dot;
+
+    -- code from book
+
+    trigger_reset : process (trigger) is
+    begin
+      break v_cap => 0.0 when trigger = '1';
+    end process trigger_reset;
+
+    -- end code from book
+
+  end block block_3;
+
+
+  block_4 : block is
+
+    terminal cap : electrical;
+    quantity v_cap across i_cap through cap;
+    quantity charge : real;
+    
+  begin
+
+    -- code from book
+
+    charge == capacitance * v_cap;
+    
+    i_cap == charge'dot;
+
+    --
+    
+    trigger_reset : process (trigger) is
+    begin
+      if trigger = '1' then
+        break for charge use v_cap => 0.0;
+      end if;
+    end process trigger_reset;
+
+    -- end code from book
+
+  end block block_4;
+
+
+  block_5 : block is
+
+    terminal cap : electrical;
+    quantity v_cap across i_cap through cap;
+    quantity charge : real;
+    
+  begin
+
+    charge == capacitance * v_cap;
+    i_cap == charge'dot;
+
+    -- code from book
+
+    trigger_reset : process (trigger) is
+    begin
+      break for charge use v_cap => 0.0 when trigger = '1';
+    end process trigger_reset;
+
+    -- end code from book
+
+  end block block_5;
+
+
+  block_6 : block is
+
+    terminal cap : electrical;
+    quantity v_cap across i_cap through cap;
+    quantity cap_charge : real;
+    
+  begin
+
+    cap_charge == capacitance * v_cap;
+    i_cap == cap_charge'dot;
+
+    -- code from book
+
+    discharge_cap : break cap_charge => 0.0
+                      on clk when discharge = '1' and clk = '1';
+
+    -- end code from book
+
+  end block block_6;
+
+
+  block_7 : block is
+
+    terminal cap : electrical;
+    quantity v_cap across i_cap through cap;
+    quantity cap_charge : real;
+    
+  begin
+
+    cap_charge == capacitance * v_cap;
+    i_cap == cap_charge'dot;
+
+    -- code from book
+
+    discharge_cap : process is
+    begin
+      break cap_charge => 0.0 when discharge = '1' and clk = '1';
+      wait on clk;
+    end process discharge_cap;
+
+    -- end code from book
+
+  end block block_7;
+
+
+  block_8 : block is
+
+    terminal cap : electrical;
+    quantity v_cap across i_cap through cap;
+    quantity charge : real;
+    
+  begin
+
+    charge == capacitance * v_cap;
+    i_cap == charge'dot;
+
+    -- code from book
+
+    trigger_reset : break for charge use v_cap => 0.0 when trigger = '1';
+
+    -- end code from book
+
+  end block block_8;
+
+
+  block_9 : block is
+
+    terminal cap : electrical;
+    quantity v_cap across i_cap through cap;
+    quantity charge : real;
+    
+  begin
+
+    charge == capacitance * v_cap;
+    i_cap == charge'dot;
+
+    -- code from book
+
+    trigger_reset : process is
+    begin
+      break for charge use v_cap => 0.0 when trigger = '1';
+      wait on trigger;
+    end process trigger_reset;
+
+    -- end code from book
+
+  end block block_9;
+
+
+  block_10 : block is
+
+    quantity q : real;
+    constant new_q : real := 0.0;
+    
+  begin
+
+    -- code from book
+
+    useless_break : break q => new_q when q < 0.0 or q > 3.0;
+
+    -- end code from book
+
+  end block block_10;
+
+
+  block_11 : block is
+
+    quantity q : real;
+    constant new_q : real := 0.0;
+    
+  begin
+
+    -- code from book
+
+    useless_break : process is
+    begin
+      break q => new_q when q < 0.0 or q > 3.0;
+      wait;
+    end process useless_break;
+
+    -- end code from book
+
+  end block block_11;
+
+
+  block_12 : block is
+
+    quantity q : real;
+    constant new_q : real := 0.0;
+    
+  begin
+
+    -- code from book
+
+    correct_break : break q => new_q on q'above(0.0), q'above(3.0)
+      when q < 0.0 or q > 3.0;
+
+    -- end code from book
+
+  end block block_12;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd
new file mode 100644
index 0000000..81f5e4f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_21a.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.mechanical_systems.all;
+                        
+entity inline_21a is
+
+end entity inline_21a;
+
+
+architecture test of inline_21a is
+
+  -- code from book
+
+  quantity d : displacement;
+  
+  limit d : displacement with 0.001;
+
+  --
+
+  quantity drive_shaft_av, axle_av, wheel_av : angular_velocity;
+
+  --
+
+  limit drive_shaft_av, axle_av, wheel_av : angular_velocity with 0.01;
+
+  --
+
+  limit all : angular_velocity with 0.01;
+
+  --
+
+  quantity input, preamp_out, mixer_out, agc_out : voltage;
+  
+  limit input, preamp_out : voltage with 1.0E-9;
+  limit others : voltage with 1.0E-7;
+
+  --
+
+  terminal bus1 : electrical_vector(1 to 8);
+  terminal bus2 : electrical_vector(1 to 8);
+  quantity v_bus across bus1 to bus2;
+  limit v_bus : voltage_vector with 1.0E-3;
+
+  -- end code from book
+
+begin
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd
new file mode 100644
index 0000000..e53a30c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_22a.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_22a is
+
+end entity inline_22a;
+
+
+architecture test of inline_22a is
+
+  signal clock : bit;
+  quantity q : real;
+  signal sample : integer;
+  signal average : real;
+
+  quantity v_in : real;
+  constant v_il : real := 0.8;
+  constant v_ih : real := 2.0;
+  signal data : std_ulogic;
+
+begin
+
+  -- code from book
+
+  sampler : process ( clock ) is
+    constant num_levels : real := 64.0;
+    constant max_val : real := 5.0;
+  begin
+    if clock = '1' then
+      sample <= integer(q * num_levels / max_val) after 5 ns;
+    end if;
+  end process sampler;
+
+  --
+
+  compute_running_average : process (clock) is
+    variable num_samples : integer := 0;
+    variable total : real := 0.0;
+    variable running_average : real := 0.0;
+  begin
+    if clock = '1' then
+      total := total + q;
+      num_samples := num_samples + 1;
+      running_average := total / real(num_samples);
+      average <= running_average after 5 ns;
+    end if;
+  end process compute_running_average;
+
+  --
+
+  analog_to_std_logic : process (v_in'above(v_il), v_in'above(v_ih)) is
+  begin
+    if not v_in'above(v_il) then
+      data <= '0';
+    elsif v_in'above(v_ih) then
+      data <= '1';
+    else
+      data <= 'X';
+    end if;
+  end process analog_to_std_logic;
+  
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd
new file mode 100644
index 0000000..88a8025
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_23a.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_23a is
+
+end entity inline_23a;
+
+
+architecture test of inline_23a is
+
+  signal digital_level : integer;
+  constant num_levels : integer := 63;
+  constant max_voltage : real := 10.0;
+  
+begin
+
+  block_1 : block is
+
+    quantity analog_voltage : real;
+
+  begin
+    
+    -- code from book
+
+    analog_voltage == real(digital_level) / real(num_levels) * max_voltage;
+
+    -- end code from book
+
+  end block block_1;
+
+
+  block_2 : block is
+
+    signal real_digital_level : real;
+    quantity analog_voltage : real;
+
+  begin
+    
+    -- code from book
+
+    real_digital_level <= real(digital_level);
+    analog_voltage == real_digital_level'ramp(1.0E-6) / real(num_levels) * max_voltage;
+
+    -- end code from book
+
+  end block block_2;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd
new file mode 100644
index 0000000..66f0030
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inline_24a.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all;
+use ieee_proposed.mechanical_systems.all;
+                        
+entity inline_24a is
+
+end entity inline_24a;
+
+
+architecture test of inline_24a is
+
+  -- code from book
+
+  terminal plus, minus : electrical;
+  quantity v across i through plus to minus;
+  
+  terminal shaft : rotational_v;
+  quantity applied_torque through shaft;
+
+  -- end code from book
+
+begin
+
+  -- code from book
+
+  applied_torque == v * i;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd
new file mode 100644
index 0000000..3edb975
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/inverting_integrator.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inverting_integrator is 
+  port ( terminal input, output : electrical );
+end entity inverting_integrator;
+
+----------------------------------------------------------------
+
+architecture structural of inverting_integrator is
+  terminal internal : electrical;
+begin
+  
+  r1 : entity work.resistor(ideal)
+    port map ( node1 => input, node2 => internal ) ;
+        
+  c1 : entity work.capacitor(leakage)
+    port map ( node1 => internal, node2 => output );
+        
+  amp : entity work.opamp(slew_limited)
+    port map ( plus_in => electrical_ref, minus_in => internal,
+               output => output );
+        
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd
new file mode 100644
index 0000000..586eaef
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.mechanical_systems.all;
+                        
+entity moving_mass is
+  port ( terminal external_attachment : translational );
+end entity moving_mass;
+
+----------------------------------------------------------------
+
+architecture behavioral of moving_mass is
+  constant mass : real := 10.0;
+  constant stiffness : real := 2.0;
+  constant damping : real := 5.0;
+  quantity position across driving_force through external_attachment;
+  quantity velocity : real;
+begin
+  position == velocity'integ;
+  mass * velocity'dot == driving_force - stiffness * velocity'integ - damping * velocity
+    tolerance velocity'tolerance;
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd
new file mode 100644
index 0000000..fc897f5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/moving_mass_wa.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.mechanical_systems.all;
+                       
+entity moving_mass_wa is
+  port ( terminal external_attachment : translational );
+end entity moving_mass_wa;
+
+----------------------------------------------------------------
+
+architecture behavioral of moving_mass_wa is
+  constant mass : real := 10.0;
+  constant stiffness : real := 2.0;
+  constant damping : real := 5.0;
+  quantity position across driving_force through external_attachment;
+  quantity velocity : real;
+begin
+  velocity == position'dot;
+  driving_force == mass*velocity'dot + damping*velocity + stiffness*position; 
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd
new file mode 100644
index 0000000..a2a26fe
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp-1.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity opamp is
+  port ( terminal positive_supply, negative_supply : electrical;
+         terminal plus_in, minus_in, output : electrical );
+end entity opamp;
+
+----------------------------------------------------------------
+
+architecture saturating of opamp is
+  
+  constant gain : real := 50.0;
+  quantity v_pos across positive_supply;
+  quantity v_neg across negative_supply;
+  quantity v_in across plus_in to minus_in;
+  quantity v_out across i_out through output;
+  quantity v_amplified : voltage;
+  
+begin
+  
+  if v_in'above(v_pos / gain) use 
+    v_amplified == v_pos;
+  elsif not v_in'above(v_neg / gain) use
+    v_amplified == v_neg;
+  else 
+    v_amplified == gain * v_in;
+  end use;
+        
+  break on v_in'above(v_pos/gain), v_in'above(v_neg/gain);
+        
+  v_out == v_amplified'slew(1.0e6,-1.0e6);
+        
+end architecture saturating;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd
new file mode 100644
index 0000000..009e061
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity opamp is
+  port ( terminal plus_in, minus_in, output : electrical );
+end entity opamp;
+
+----------------------------------------------------------------
+
+architecture slew_limited of opamp is
+  
+  constant gain : real := 50.0;
+  quantity v_in across plus_in to minus_in;
+  quantity v_out across i_out through output;
+  quantity v_amplified : voltage;
+  
+begin
+  
+  v_amplified == gain * v_in;
+        
+  v_out == v_amplified'slew(1.0e6,-1.0e6);
+        
+end architecture slew_limited;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd
new file mode 100644
index 0000000..b5e7aa7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/opamp_wa-1.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity opamp_wa is
+  port ( terminal positive_supply, negative_supply : electrical;
+         terminal plus_in, minus_in, output : electrical );
+end entity opamp_wa;
+
+----------------------------------------------------------------
+
+architecture saturating of opamp_wa is
+  
+  constant gain : real := 50.0;
+  quantity v_pos := 15.0 across positive_supply;
+  quantity v_neg := -15.0 across negative_supply;
+  quantity v_in across plus_in to minus_in;
+  quantity v_out across i_out through output;
+  quantity v_amplified : voltage;
+        
+begin
+
+  if v_in'above(v_pos / gain) use 
+    v_amplified == v_pos;
+  elsif not v_in'above(v_neg / gain) use
+    v_amplified == v_neg;
+  else 
+    v_amplified == gain * v_in;
+  end use;
+
+  break on v_in'above(v_pos/gain), v_in'above(v_neg/gain);
+  
+  v_out == v_amplified; -- 'slew(1.0e6,-1.0e6);
+  
+end architecture saturating;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd
new file mode 100644
index 0000000..e782880
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+               
+entity pendulum is
+end entity pendulum;
+
+----------------------------------------------------------------
+
+architecture constrained of pendulum is
+  
+  constant mass : real := 10.0;
+  constant arm_length : real := 5.0;
+  constant pin_angle : real := 0.25 * math_pi;
+  constant pin_distance : real := 2.5;
+  constant damping : real := 1.0;
+  constant gravity : real := 9.81;
+  constant short_length : real := arm_length - pin_distance;
+  quantity phi : real := -0.5*math_pi;
+  quantity current_length : real := arm_length;
+        
+begin
+  
+  if phi'above(pin_angle) use
+    current_length == short_length;
+  else
+    current_length == arm_length;
+  end use;
+        
+  break phi'dot => phi'dot * arm_length/short_length
+    when phi'above(pin_angle);
+        
+  break phi'dot => phi'dot * short_length/arm_length
+    when not phi'above(pin_angle);
+        
+  mass * current_length * phi'dot'dot
+    == - mass * gravity * sin(phi) - damping * current_length * phi'dot;
+        
+end architecture constrained;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd
new file mode 100644
index 0000000..bf33811
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/pendulum_wa.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- Pendulum example. Look at velocity quantity, phi_dot, to see effects of 
+-- discontinuity. Run simulation for about 20 sec.
+
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+library ieee; use ieee.math_real.all;
+
+entity pendulum_wa is
+end entity pendulum_wa;
+
+-- ======================================================================================
+-- constrained architecture
+-- ======================================================================================
+architecture constrained of pendulum_wa is
+	constant mass : real := 10.0;
+	constant arm_length : real := 5.0;
+	constant pin_angle : real := 0.25*math_pi;
+	constant pin_distance : real := 2.5;
+	constant damping : real := 1.0;
+	constant gravity : real := 9.81;
+	constant short_length : real := arm_length-pin_distance;
+	quantity phi : real := -0.5*math_pi;
+	signal current_length : real := arm_length;
+	quantity acceleration, velocity : real;
+	quantity phi_dot : real;
+	signal pin_thresh : boolean;
+	signal phi_dot_at_pin_thresh : real := 0.0;
+	signal transition : boolean := false;
+
+begin
+    if domain = quiescent_domain use
+	    phi == -0.5*math_pi;
+		phi'dot == 0.0;
+	elsif transition and pin_thresh use
+		phi == pin_angle;
+		phi'dot == phi_dot_at_pin_thresh*arm_length/short_length;
+	elsif transition and not pin_thresh use
+		phi == pin_angle;
+		phi'dot == phi_dot_at_pin_thresh*short_length/arm_length;
+	else
+		mass*acceleration == -mass*gravity*sin(phi)-damping*velocity;
+		velocity == current_length*phi'dot;
+	end use;
+
+	acceleration == velocity'dot;
+	phi_dot == phi'dot;
+
+	pin_thresh <= phi'above(pin_angle);
+
+	process
+		begin
+		wait on pin_thresh;
+		phi_dot_at_pin_thresh <= phi_dot;
+		if pin_thresh = true then
+			current_length <= short_length;
+			transition <= true;
+		else
+			current_length <= arm_length;
+			transition <= true;
+		end if;
+		wait for 1 us;
+		transition <= false;
+	end process;
+	break on pin_thresh;
+	break on transition;
+	
+end architecture constrained;
+
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd
new file mode 100644
index 0000000..50f9db8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/piston.vhd
@@ -0,0 +1,33 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.mechanical_systems.all;
+                       
+entity piston is
+  port ( terminal motion : translational );
+end entity piston;
+
+--------------------------------------------------------------
+
+architecture simple of piston is
+  constant mass : real := 10.0;
+  quantity resultant_displacement across applied_force through motion;
+begin
+  applied_force == mass * resultant_displacement'dot'dot;
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd
new file mode 100644
index 0000000..0bf267f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity quad_opamp is
+  port ( terminal plus_in, minus_in, output : electrical_vector(1 to 4) );
+end entity quad_opamp;
+
+----------------------------------------------------------------
+
+architecture slew_limited of quad_opamp is
+  
+  constant gain : real := 50.0;
+  quantity v_in across plus_in to minus_in;
+  quantity v_out across i_out through output;
+  quantity v_amplified : real_vector(1 to 4);
+        
+begin
+
+  v_amplified(1) == gain * v_in(1);
+  v_amplified(2) == gain * v_in(2);
+  v_amplified(3) == gain * v_in(3);
+  v_amplified(4) == gain * v_in(4);
+  
+  real_vector(v_out) == v_amplified'slew(1.0e6,-1.0e6);
+  
+end architecture slew_limited;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd
new file mode 100644
index 0000000..221b3e9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/quad_opamp_wa.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity quad_opamp_wa is
+  port (terminal n1, n2, output : electrical_vector(1 to 4));
+end entity quad_opamp_wa ;
+
+----------------------------------------------------------------
+
+architecture slew_limited of quad_opamp_wa is
+  
+  quantity vin across n1 to n2;
+  quantity vout across iout through output;
+  quantity vamp1 : real;
+  quantity vamp2 : real;
+  quantity vamp3 : real;
+  quantity vamp4 : real;
+  constant gain : real := 50.0;
+        
+begin
+
+  vamp1 == gain*vin(1);	
+  vamp2 == gain*vin(2);
+  vamp3 == gain*vin(3);
+  vamp4 == gain*vin(4);
+
+  vout(1) == vamp1'slew(1.0e6,-1.0e6);
+  vout(2) == vamp2'slew(1.0e6,-1.0e6);
+  vout(3) == vamp3'slew(1.0e6,-1.0e6);
+  vout(4) == vamp4'slew(1.0e6,-1.0e6);
+
+end architecture slew_limited ;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd
new file mode 100644
index 0000000..2339f33
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/resistor.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity resistor is 
+  port ( terminal node1, node2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+  constant R : real := 1000.0;
+  quantity v across i through node1 to node2;
+begin
+  v == i * R; 
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd
new file mode 100644
index 0000000..a469e16
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/std_logic_to_analog.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity std_logic_to_analog is
+  port ( d : in std_logic;
+         terminal a : electrical ); 
+end entity std_logic_to_analog;
+
+----------------------------------------------------------------
+
+architecture ideal of std_logic_to_analog is
+  constant v_low : real := 0.0;
+  constant v_high : real := 5.0;
+  constant v_unknown : real := 2.0;
+  signal v_in : real := 0.0;
+  quantity v_out across i_out through a to electrical_ref;
+begin
+  
+  v_in <= v_high when d = '1' or d = 'H' else
+          v_low when d = '0' or d = 'L' else
+          v_unknown;
+  
+  v_out == v_in'slew(2.0e+9, -1.0e+9);
+        
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd
new file mode 100644
index 0000000..08cc1b7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_analog_switch.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity tb_analog_switch is
+end tb_analog_switch;
+
+architecture TB_analog_switch of tb_analog_switch is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_ana_src : electrical;
+	terminal in_switch : electrical;
+    signal clock_out : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    vdc1 : entity work.v_constant(ideal)
+        generic map(
+            level => 1.0
+        )
+        port map(
+            pos => in_ana_src,
+            neg => ELECTRICAL_REF
+        );
+    Clk1 : entity work.clock(ideal)
+        generic map(
+            period => 10.0ms
+        )        
+		port map(
+            clk_out => clock_out
+        );
+    R1 : entity work.resistor(ideal)
+        generic map(
+            res => 100.0
+        )        
+		port map(
+            p1 => in_ana_src,
+            p2 => in_switch
+        );
+    swtch : entity work.analog_switch(ideal)
+        port map(
+            n1 => in_switch,
+            n2 => ELECTRICAL_REF,
+			control => clock_out
+        );
+end TB_analog_switch;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd
new file mode 100644
index 0000000..2c3cb18
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_bit_to_analog is
+end tb_bit_to_analog;
+
+architecture TB_bit2analog of tb_bit_to_analog is
+    -- Component declarations
+    -- Signal declarations
+	terminal ana_out : electrical;
+    signal ina : bit;
+	signal ina_tmp : std_logic;
+
+begin
+    -- Signal assignments
+	ina <= To_bit(ina_tmp);		-- convert std_logic to bit
+    -- Component instances
+    d2a1 : entity work.bit_to_analog(ideal)
+        port map(
+           d => ina,			-- bit type pin
+           a => ana_out
+        );
+    clk1 : entity work.clock_duty(ideal)
+        generic map(
+            off_time => 2 ms,
+            on_time => 1 ms
+        )
+        port map(
+            CLOCK_OUT => ina_tmp	-- std_logic type pin
+        );
+    R1 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => ana_out,
+            p2 => electrical_ref
+        );
+end TB_bit2analog;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd
new file mode 100644
index 0000000..b3e3ef2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator-1.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_comparator is
+end tb_comparator;
+
+architecture TB_comparator of tb_comparator is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src : electrical;
+    signal cmp_out : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 100.0,
+            amplitude => 5.0
+        )
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+    C1 : entity work.comparator(hysteresis)
+        port map(
+            plus_in => in_src,
+            minus_in => electrical_ref,
+		output => cmp_out
+        );
+end TB_comparator;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd
new file mode 100644
index 0000000..33d8194
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_comparator.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity tb_comparator is
+end tb_comparator;
+
+architecture TB_comparator of tb_comparator is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src : electrical;
+    signal cmp_out : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 100.0,
+            amplitude => 5.0
+        )
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+    C1 : entity work.comparator(ideal)
+        port map(
+            a => in_src,
+            d => cmp_out
+        );
+end TB_comparator;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd
new file mode 100644
index 0000000..a4da70d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_control_system.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;
+
+entity tb_control_system is
+end tb_control_system;
+
+architecture TB_control_system of tb_control_system is
+    -- Component declarations
+    -- Signal declarations
+    quantity in_src, fb : real;
+    quantity output : real;
+begin
+    -- Signal assignments
+    -- Component instances
+    src3 : entity work.src_sine(ideal)
+        generic map(
+            freq => 100.0,
+            amplitude => 1.0
+        )
+        port map(
+            output => in_src
+        );
+    XCMP12 : entity work.control_system(simple_feedback)
+        port map(
+            target => in_src,
+            output => output,
+		feedback => fb
+        );
+	 gain1 : entity work.gain(simple)
+        generic map(
+            k => 1.0
+        )
+	  port map (
+		input => output,
+		output => fb
+		);
+end TB_control_system;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd
new file mode 100644
index 0000000..05c20a9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_diode.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.thermal_systems.all;
+entity tb_diode is
+end tb_diode;
+
+architecture TB_diode of tb_diode is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src : electrical;
+    terminal r1_d1 : electrical;
+	terminal temp_in : thermal;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 100.0,
+            amplitude => 5.0
+        )
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+    tmp : entity work.TempConstant(ideal)
+        generic map(
+            level => 100.0
+        )
+        port map(
+            th1 => temp_in,
+            th2 => thermal_REF
+        );
+    R1 : entity work.resistor(ideal)
+	        generic map(
+            res => 100.0
+       )
+        port map(
+            p1 => in_src,
+            p2 => r1_d1
+        );
+	D1 : entity work.diode(one)
+       port map(
+            p => r1_d1,
+            m => electrical_ref,
+			j => temp_in
+        );
+end TB_diode;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd
new file mode 100644
index 0000000..bcc236d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_inv_integrator.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_inv_integrator is
+end tb_inv_integrator;
+
+architecture TB_inv_integrator of tb_inv_integrator is
+    -- Component declarations
+    -- Signal declarations
+    terminal vin : electrical;
+    terminal vout : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    v1 : entity work.v_sine(ideal)
+        generic map(
+            amplitude => 0.2,
+            freq => 1.0e3
+        )
+        port map(
+            pos => vin,
+            neg => ELECTRICAL_REF
+        );
+    inverting_integ1 : entity work.inverting_integrator(structural)
+        port map(
+            output => vout,
+            input => vin
+        );
+    RLoad : entity work.load_res(ideal)
+        generic map(
+            R => 100.0
+        )
+        port map(
+            node1 => vout,
+            node2 => ELECTRICAL_REF
+        );
+end TB_inv_integrator;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd
new file mode 100644
index 0000000..8a44b78
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_moving_mass.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_moving_mass is
+end tb_moving_mass;
+
+architecture TB_moving_mass of tb_moving_mass is
+    -- Component declarations
+    -- Signal declarations
+    terminal msd_discrete, msd_mdl : translational;
+begin
+    -- Signal assignments
+    -- Component instances
+    mass1 : entity work.mass_t(ideal)
+        generic map(
+            m => 10.0
+        )
+        port map(
+            trans1 => msd_discrete
+        );
+    spring2 : entity work.spring_t(linear)
+        generic map(
+            k => 2.0
+        )
+        port map(
+            trans1 => msd_discrete,
+            trans2 => TRANSLATIONAL_REF
+        );
+    damper1 : entity work.damper_t(ideal)
+        generic map(
+            d => 5.0
+        )
+        port map(
+            trans1 => msd_discrete,
+            trans2 => TRANSLATIONAL_REF
+        );
+    Force1 : entity work.ForcePulse_t(ideal)
+        generic map(
+            initial => 0.0,
+            pulse => 20.0e-3,
+            ti2p => 1 ms,
+            tp2i => 1 ms,
+            delay => 1 ms,
+            width => 1 sec,
+            period => 3 sec
+        )
+        port map(
+            trans_pos => msd_discrete,
+            trans_neg => TRANSLATIONAL_REF
+        );
+    Force2 : entity work.ForcePulse_t(ideal)
+        generic map(
+            initial => 0.0,
+            pulse => 20.0e-3,
+            ti2p => 1 ms,
+            tp2i => 1 ms,
+            delay => 1 ms,
+            width => 1 sec,
+            period => 3 sec
+        )
+        port map(
+            trans_pos => msd_mdl,
+            trans_neg => TRANSLATIONAL_REF
+        );
+    moving_mass4 : entity work.moving_mass_wa(behavioral)
+        port map(
+            external_attachment => msd_mdl
+        );
+end TB_moving_mass;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd
new file mode 100644
index 0000000..5f238e4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_piston.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_piston is
+end tb_piston;
+
+architecture TB_piston of tb_piston is
+    -- Component declarations
+    -- Signal declarations
+    terminal n1, n2 : translational;
+begin
+    -- Signal assignments
+    -- Component instances
+    Force1 : entity work.ForcePulse_t(ideal)
+        generic map(
+            initial => 0.0,
+            pulse => 20.0e-3,
+            ti2p => 1 ms,
+            tp2i => 1 ms,
+            delay => 1 ms,
+            width => 1 sec,
+            period => 3 sec
+        )
+        port map(
+            trans_pos => n1,
+            trans_neg => TRANSLATIONAL_REF
+        );
+    mass1 : entity work.piston(simple)
+        port map(
+            motion => n1
+        );
+    Force2 : entity work.ForcePulse_t(ideal)
+        generic map(
+            initial => 0.0,
+            pulse => 20.0e-3,
+            ti2p => 1 ms,
+            tp2i => 1 ms,
+            delay => 1 ms,
+            width => 1 sec,
+            period => 3 sec
+        )
+        port map(
+            trans_pos => n2,
+            trans_neg => TRANSLATIONAL_REF
+        );
+    mass2 : entity work.mass_t(ideal)
+        generic map(
+            m => 10.0
+        )
+        port map(
+            trans1 => n2
+        );
+end TB_piston;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd
new file mode 100644
index 0000000..dc55ca3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_quad_opamp.vhd
@@ -0,0 +1,162 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_quad_opamp is
+end tb_quad_opamp ;
+
+architecture TB_quad_opamp of tb_quad_opamp is
+    -- Component declarations
+    -- Signal declarations
+    terminal amp_out : electrical_vector(1 to 4);
+    terminal inm : electrical_vector(1 to 4);
+    terminal inp : electrical_vector(1 to 4);
+begin
+    -- Signal assignments
+    -- Component instances
+    opamp_quad_slew1 : entity work.quad_opamp_wa(slew_limited)
+        port map(
+            n1 => inp,
+            n2 => inm,
+            output => amp_out
+        );
+    R4 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => ELECTRICAL_REF,
+            p2 => amp_out(4)
+        );
+    v4 : entity work.v_pulse(ideal)
+        generic map(
+            period => 200 us,
+            width => 100 us,
+            delay => 10 us,
+            tp2i => 0.9 us,
+            ti2p => 0.70 us,
+            pulse => 5.0
+        )
+        port map(
+            pos => inm(1),
+            neg => ELECTRICAL_REF
+        );
+    R5 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => ELECTRICAL_REF,
+            p2 => amp_out(3)
+        );
+    R6 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => ELECTRICAL_REF,
+            p2 => amp_out(2)
+        );
+    R7 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => ELECTRICAL_REF,
+            p2 => amp_out(1)
+        );
+    v5 : entity work.v_pulse(ideal)
+        generic map(
+            pulse => 5.0,
+            ti2p => 0.70 us,
+            tp2i => 0.9 us,
+            delay => 10 us,
+            width => 100 us,
+            period => 200 us
+        )
+        port map(
+            pos => inm(2),
+            neg => ELECTRICAL_REF
+        );
+    v6 : entity work.v_pulse(ideal)
+        generic map(
+            pulse => 5.0,
+            ti2p => 0.70 us,
+            tp2i => 0.9 us,
+            delay => 10 us,
+            width => 100 us,
+            period => 200 us
+        )
+        port map(
+            pos => inm(3),
+            neg => ELECTRICAL_REF
+        );
+    v7 : entity work.v_pulse(ideal)
+        generic map(
+            pulse => 5.0,
+            ti2p => 0.70 us,
+            tp2i => 0.9 us,
+            delay => 10 us,
+            width => 100 us,
+            period => 200 us
+        )
+        port map(
+            pos => inm(4),
+            neg => ELECTRICAL_REF
+        );
+    R8 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e-3
+        )
+        port map(
+            p1 => ELECTRICAL_REF,
+            p2 => inp(1)
+        );
+    R9 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e-3
+        )
+        port map(
+            p1 => ELECTRICAL_REF,
+            p2 => inp(2)
+        );
+    R10 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e-3
+        )
+        port map(
+            p1 => ELECTRICAL_REF,
+            p2 => inp(3)
+        );
+    R11 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e-3
+        )
+        port map(
+            p1 => ELECTRICAL_REF,
+            p2 => inp(4)
+        );
+end TB_quad_opamp ;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd
new file mode 100644
index 0000000..1059d6c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_std_logic_to_analog.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_std_logic_to_analog is
+end tb_std_logic_to_analog;
+
+architecture TB_std_logic2analog of tb_std_logic_to_analog is
+    -- Component declarations
+    -- Signal declarations
+	terminal ana_out : electrical ;
+    signal ina : std_logic ;
+
+begin
+    -- Signal assignments
+    -- Component instances
+    d2a1 : entity work.std_logic_to_analog(ideal)
+        port map(
+           d => ina,			-- bit type pin
+           a => ana_out
+        );
+    clk1 : entity work.clock_duty(ideal)
+        generic map(
+            off_time => 2 ms,
+            on_time => 1 ms
+        )
+        port map(
+            CLOCK_OUT => ina	-- std_logic type pin
+        );
+    R1 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => ana_out,
+            p2 => electrical_ref
+        );
+end TB_std_logic2analog;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd
new file mode 100644
index 0000000..c535fd7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_transmission_line.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_transmission_line is
+
+end tb_transmission_line;
+
+architecture TB_transmission_line of tb_transmission_line is
+    quantity in_src, line_out : voltage;
+    -- Component declarations
+    -- Signal declarations
+begin
+    -- Signal assignments
+    -- Component instances
+    q1 : entity work.src_pulse(ideal)
+        generic map(
+            initial => 0.0,
+            pulse => 1.0e1,
+			ti2p => 1.0e-12,
+			tp2i => 1.0e-12,
+			delay => 1 ps,
+			width => 20 ns,
+			period => 50 ns
+        )
+        port map(
+            output => in_src
+        );
+    
+    T1 : entity work.transmission_line_wa(abstract)
+        port map(
+            vin => in_src,
+            vout => line_out
+        );
+ 
+end TB_transmission_line;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd
new file mode 100644
index 0000000..ce33af8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_triangle_waveform.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity tb_triangle_waveform is
+end tb_triangle_waveform;
+
+architecture TB_triangle_waveform of tb_triangle_waveform is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.triangle_waveform_wa(ideal)
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+    R1 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e9
+        )
+        port map(
+            p1 => in_src,
+            p2 => ELECTRICAL_REF
+        );
+end TB_triangle_waveform;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd
new file mode 100644
index 0000000..9dc4367
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_variable_comparator.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+entity tb_variable_comparator is
+end tb_variable_comparator;
+
+architecture TB_variable_comparator of tb_variable_comparator is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src, v_ref : electrical;
+    signal cmp_out : std_logic;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 100.0,
+            amplitude => 5.0
+        )
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+    C1 : entity work.variable_comparator(ideal)
+        port map(
+            a => in_src,
+			ref => electrical_ref,
+            d => cmp_out
+        );
+end TB_variable_comparator;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd
new file mode 100644
index 0000000..8b151da
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/timer.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity timer is
+  port ( signal trigger_n, reset : in std_ulogic;  signal q : out std_ulogic;
+         terminal rc_ext : electrical );
+end entity timer;
+
+----------------------------------------------------------------
+
+architecture behavioral of timer is
+  
+  constant half_vdd : real := 2.5;
+  constant clamp_on_resistance : real := 0.01;
+  constant clamp_off_resistance : real := 10.0E6;
+  quantity v_rc_ext across i_clamp through rc_ext to electrical_ref;
+  signal q_n : std_ulogic := '1';
+        
+begin
+  
+  if q_n = '1' use
+    i_clamp == v_rc_ext / clamp_on_resistance;
+  else
+    i_clamp == v_rc_ext / clamp_off_resistance;
+  end use;
+        
+  timer_state : process ( trigger_n, reset, v_rc_ext'above(half_vdd) ) is
+  begin
+    if reset = '1' or reset = 'H' or v_rc_ext > half_vdd then
+      q <= '0';  q_n <= '1';
+    elsif trigger_n = '0' or trigger_n = 'L' then
+      q <= '1';  q_n <= '0';
+    end if;
+  end process timer_state;
+                
+  clamp_change : process ( q_n ) is
+  begin
+    break;
+  end process clamp_change;
+        
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd
new file mode 100644
index 0000000..0206b77
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity transmission_line is
+  port ( quantity vin : in voltage; 
+         quantity vout : out voltage); 
+end entity transmission_line;
+
+----------------------------------------------------------------
+
+architecture abstract of transmission_line is
+  constant propagation_time : real := 2.5E-9;
+  constant attenuation : real := 0.8;
+begin 
+  vout == attenuation * vin'delayed(propagation_time);
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd
new file mode 100644
index 0000000..accb393
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/transmission_line_wa.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity transmission_line_wa is
+  port ( quantity vin : in voltage; 
+         quantity vout : out voltage); 
+end entity transmission_line_wa;
+
+----------------------------------------------------------------
+
+architecture abstract of transmission_line_wa is
+  constant propagation_time : real := 2.5E-9;
+  constant attenuation : real := 0.8;
+  quantity vin_temp : real;
+begin 
+  vin_temp == vin;
+  vout == attenuation * vin_temp'delayed(propagation_time);
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd
new file mode 100644
index 0000000..6a7b82d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity triangle_waveform is
+  port ( terminal pos, neg : electrical );
+end entity triangle_waveform;
+
+----------------------------------------------------------------
+
+architecture ideal of triangle_waveform is
+  
+  constant freq : real := 10_000.0;  -- in Hz
+  constant period : real := 1.0 / freq;
+  constant amplitude : voltage := 5.0;
+  constant offset : voltage := 0.0;
+  signal square_wave : real := 0.0;
+  quantity v across i through pos to neg;
+  limit v : voltage with period / 10.0;
+        
+begin
+  
+  process is
+    variable state : bit := '0';
+  begin
+    if state = '1' then
+      square_wave <= 1.0;
+    else
+      square_wave <= 0.0;
+    end if;
+    state := not state;
+    wait for period / 2.0;
+  end process;
+        
+  v == offset + amplitude * square_wave'ramp(period / 2.0);
+        
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd
new file mode 100644
index 0000000..bebc5ae
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/triangle_waveform_wa.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity triangle_waveform_wa is
+  port ( terminal pos, neg : electrical );
+end entity triangle_waveform_wa;
+
+----------------------------------------------------------------
+
+architecture ideal of triangle_waveform_wa is
+  
+  constant freq : real := 10_000.0;  -- in Hz
+  constant period : real := 1.0 / freq;
+  constant amplitude : voltage := 5.0;
+  constant offset : voltage := 0.0;
+  signal square_wave : real := 0.0;
+  quantity v across i through pos to neg;
+--  limit v : voltage with period / 10.0;
+        
+begin
+  
+  process is
+    variable state : bit := '0';
+  begin
+    if state = '1' then
+      square_wave <= 1.0;
+    else
+      square_wave <= 0.0;
+    end if;
+    state := not state;
+    wait for period / 2.0;
+  end process;
+        
+  v == offset + amplitude * square_wave'ramp(period / 2.0);
+        
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd
new file mode 100644
index 0000000..fb26e87
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/variable_comparator.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity variable_comparator is
+  port ( terminal a : electrical;
+         terminal ref : electrical;
+         signal d : out std_ulogic );
+end entity variable_comparator;
+
+----------------------------------------------------------------
+
+architecture ideal of variable_comparator is
+  quantity v_ref across ref;
+  quantity vin across a;
+begin
+  
+  comparator_behavior : process is
+  begin
+    if vin > v_ref then
+      d <= '1' after 5 ns;
+    else
+      d <= '0' after 5 ns;
+    end if;
+    wait on vin'above(v_ref / 2.0);
+  end process comparator_behavior;
+  
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/74x138.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/74x138.vhd
new file mode 100644
index 0000000..dd3f902
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/74x138.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package physical_attributes is
+
+  -- code from book (in text)
+
+  attribute layout_ignore : boolean;
+  attribute pin_number : positive;
+
+  -- end code from book
+
+end package physical_attributes;
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.physical_attributes.all;
+
+entity \74x138\ is
+  generic ( Tpd : time );
+  port ( en1, en2a_n, en2b_n : in std_logic;
+         s0, s1, s2 : in std_logic;
+         y0, y1, y2, y3, y4, y5, y6, y7 : out std_logic );
+
+  attribute layout_ignore of Tpd : constant is true;
+
+  attribute pin_number of s0 : signal is 1;
+  attribute pin_number of s1 : signal is 2;
+  attribute pin_number of s2 : signal is 3;
+  attribute pin_number of en2a_n : signal is 4;
+  -- . . .
+
+end entity \74x138\;
+
+-- code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd
new file mode 100644
index 0000000..a475d11
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/CPU.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package cell_attributes is
+
+  type length is range 0 to integer'high
+    units nm;
+      um = 1000 nm;
+      mm = 1000 um;
+      mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+      x, y : length;
+    end record coordinate;
+
+  attribute cell_position : coordinate;
+
+end package cell_attributes;
+
+
+
+entity CPU is
+end entity CPU;
+
+
+-- code from book
+
+architecture cell_based of CPU is
+
+  component fpu is
+    port ( -- . . . );
+    -- not in book
+    port_name : bit := '0' );
+    -- end not in book
+  end component;
+
+  use work.cell_attributes.all;
+
+  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+
+  -- . . .
+
+begin
+
+  the_fpu : component fpu
+    port map ( -- . . . );
+    -- not in book
+    port_name => open );
+    -- end not in book
+
+  -- . . .
+
+end architecture cell_based;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/add_with_overflow.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/add_with_overflow.vhd
new file mode 100644
index 0000000..dd06f91
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/add_with_overflow.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity add_with_overflow is
+end entity add_with_overflow;
+
+
+architecture test of add_with_overflow is
+begin
+
+-- code from book
+
+process is
+
+  procedure add_with_overflow ( a, b : in integer;
+                                sum : out integer;
+                                overflow : out boolean ) is -- . . .
+
+    -- not in book
+    begin
+    end;
+    -- end not in book
+
+  procedure add_with_overflow ( a, b : in bit_vector;
+                                sum : out bit_vector;
+                                overflow : out boolean ) is -- . . .
+
+    -- not in book
+    begin
+    end;
+    -- end not in book
+
+  attribute built_in : string;
+
+  attribute built_in of
+    add_with_overflow [ integer, integer,
+                        integer, boolean ] : procedure is "int_add_overflow";
+
+  attribute built_in of
+    add_with_overflow [ bit_vector, bit_vector,
+                        bit_vector, boolean ] : procedure is "bit_vector_add_overflow";
+
+begin
+  -- . . .
+  -- not in book
+  wait;
+  -- end not in book
+end process;
+
+-- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/bottom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/bottom.vhd
new file mode 100644
index 0000000..0ddddd9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/bottom.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity bottom is
+  port ( -- . . . );
+    --
+      port_name : in bit := '0' );
+    --
+end entity bottom;
+
+--------------------------------------------------
+
+architecture bottom_arch of bottom is
+
+  signal bot_sig : -- . . .;          -- 5
+    --
+    bit;
+    --
+
+  procedure proc ( -- . . . ) is
+    --
+    param_name : in bit := '0' ) is
+    --
+    variable v : -- . . .;            -- 6
+    --
+    bit;
+    --
+  begin
+    -- . . .
+    --
+    report "--6: " & v'path_name;
+    report "--6: " & v'instance_name;
+    --
+  end procedure proc;
+
+begin
+
+  delays : block is
+    constant d : integer := 1;      -- 7
+  begin
+    -- . . .
+    --
+    assert false report "--7: " & d'path_name;
+    assert false report "--7: " & d'instance_name;
+    --
+  end block delays;
+
+  func : block is
+  begin
+
+    process is
+      variable v : -- . . .;          -- 8
+      --
+      bit;
+      --
+    begin
+      -- . . .
+      --
+      report "--5: " & bot_sig'path_name;
+      report "--5: " & bot_sig'instance_name;
+      report "--8: " & v'path_name;
+      report "--8: " & v'instance_name;
+      proc(param_name => open);
+      wait;
+      --
+      --
+    end process;
+
+  end block func;
+
+end architecture bottom_arch;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/clock_buffer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/clock_buffer.vhd
new file mode 100644
index 0000000..31683f7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/clock_buffer.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package constraints is
+
+  -- code from book (in text)
+
+  group port_pair is ( signal, signal );
+
+  attribute max_prop_delay : time;
+
+  -- end code from book
+
+end package constraints;
+
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.constraints.port_pair, work.constraints.max_prop_delay;
+
+entity clock_buffer is
+  port ( clock_in : in std_logic;
+         clock_out1, clock_out2, clock_out3 : out std_logic );
+
+  group clock_to_out1 : port_pair ( clock_in, clock_out1 );
+  group clock_to_out2 : port_pair ( clock_in, clock_out2 );
+  group clock_to_out3 : port_pair ( clock_in, clock_out3 );
+
+  attribute max_prop_delay of clock_to_out1 : group is 2 ns;
+  attribute max_prop_delay of clock_to_out2 : group is 2 ns;
+  attribute max_prop_delay of clock_to_out3 : group is 2 ns;
+
+end entity clock_buffer;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/controller.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/controller.vhd
new file mode 100644
index 0000000..c1953b5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/controller.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity controller is
+end entity controller;
+
+
+architecture test of controller is
+
+  signal clk : bit;
+
+  attribute synthesis_hint : string;
+
+begin
+
+  -- code from book
+
+  controller : process is
+
+    attribute synthesis_hint of control_loop : label is
+      "implementation:FSM(clk)";
+    -- . . .
+
+  begin
+    -- . . .    -- initialization
+    control_loop : loop
+      wait until clk = '1';
+      -- . . .
+    end loop;
+  end process controller;
+
+  -- end code fom book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/display_interface.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/display_interface.vhd
new file mode 100644
index 0000000..a279591
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/display_interface.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package display_interface is
+
+  -- . . .
+
+  -- not in book
+  type status_type is (t1, t2, t3);
+  -- end not in book
+
+  procedure create_window ( size_x, size_y : natural;
+                            status : out status_type );
+
+  attribute foreign of create_window : procedure is
+    "language Ada;  with window_operations;" &
+    "bind to window_operations.create_window;" &
+    "parameter size_x maps to size_x : in natural;" &
+    "parameter size_y maps to size_y : in natural;" &
+    "parameter status maps to status : out window_operations.status_type;" &
+    "others map to default";
+
+  -- . . .
+
+end package display_interface;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/flipflop.vhd
new file mode 100644
index 0000000..53d6c3b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/flipflop.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity flipflop is
+  generic ( Tsetup : delay_length );
+  port ( clk, d : in bit;  q : out bit );
+end entity flipflop;
+
+
+-- code from book
+
+architecture behavior of flipflop is
+begin
+
+  timing_check : process (clk) is
+  begin
+    if clk = '1' then
+      assert d'last_event >= Tsetup
+        report "set up violation detected in " & timing_check'path_name
+        severity error;
+    end if;
+  end process timing_check;
+
+  -- . . .    -- functionality
+
+end architecture behavior;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd
new file mode 100644
index 0000000..271dbbd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/gate_components.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- analyze into resource library graphics
+
+package graphics_pkg is
+
+  attribute graphic_symbol : string;
+  attribute graphic_style : string;
+
+end package graphics_pkg;
+
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+library graphics;
+
+package gate_components is
+
+  use graphics.graphics_pkg.graphic_symbol,
+    graphics.graphics_pkg.graphic_style;
+
+  component and2 is
+    generic ( prop_delay : delay_length );
+    port ( a, b : in std_logic;  y : out std_logic );
+  end component and2;
+
+  attribute graphic_symbol of and2 : component is "and2";
+  attribute graphic_style of and2 : component is "color:default, weight:bold";
+
+  -- . . .
+
+end package gate_components;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/index-ams.txt
new file mode 100644
index 0000000..90d6c36
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/index-ams.txt
@@ -0,0 +1,48 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                        Chapter 22 - Attributes and Groups
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+flipflop.vhd                                    entity flipflop                         behavior                        Figure 22-8
+mem_pkg.vhd                                     package mem_pkg                         body                            Figure 22-9
+top.vhd                                         entity top                              top_arch                        Figure 22-10
+bottom.vhd                                      entity bottom                           bottom_arch                     Figure 22-12
+add_with_overflow.vhd                           entity add_with_overflow                test                            Figure 22-14
+74x138.vhd                                      package physical_attributes             --                              Section 22.2
+--                                              entity \74x138\                         --                              Figure 22-15
+mem_read.vhd                                    entity mem_read                         test                            Figure 22-16
+gate_components.vhd                             package graphics_pkg                    --                              --
+--                                              package gate_components                 --                              Figure 22-17
+CPU.vhd                                         package cell_attributes                 --                              --
+--                                              entity CPU                              cell_based                      Figure 22-18
+controller.vhd                                  entity controller                       test                            Figure 22-19
+voltage_defs.vhd                                package voltage_defs                    --                              Figure 22-20
+sequencer.vhd                                   package timing_attributes               --                              --
+--                                              entity sequencer                        structural                      Figure 22-21
+display_interface.vhd                           package display_interface               --                              Figure 22-22
+clock_buffer.vhd                                package constraints                     --                              Section 20.3
+--                                              entity clock_buffer                     --                              Figure 20-23
+inline_01.vhd                                   package utility_definitions             --                              --
+--                                              entity inline_01                        test                            Section 22.1
+inline_02.vhd                                   entity inline_02                        test                            Section 22.1
+inline_03.vhd                                   package inline_03_defs                  --                              Section 22.2
+--                                              entity inline_03                        test                            Section 22.2
+inline_04.vhd                                   package inline_04                       --                              --
+--                                              entity flipflop                         std_cell                        Section 22.2
+--                                              package model_utilities                 --                              Section 22.2
+inline_05.vhd                                   entity inline_05                        test                            Section 22.2
+inline_06.vhd                                   entity inline_06                        test                            Section 22.2
+inline_07.vhd                                   entity inline_07                        test                            Section 22.2
+inline_08.vhd                                   entity inline_08                        test                            Section 22.2
+inline_09.vhd                                   package inline_09_defs                  --                              --
+--                                              entity e                                arch                            --
+--                                              entity inline_09                        test                            Section 22.2
+inline_10.vhd                                   package inline_10                       --                              Section 22.2
+--                                              entity and2                             accelerated                     Section 22.2
+inline_11.vhd                                   entity inline_11                        test                            Section 22.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_flipflop.vhd                                 entity tb_flipflop                      test                            flipflop.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_01.vhd
new file mode 100644
index 0000000..7516d53
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_01.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- analyze into resource library utilities
+
+package utility_definitions is
+
+  constant word_size : natural := 16;
+
+end package utility_definitions;
+
+
+
+library utilities;
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+  process is
+  begin
+
+    report
+
+    -- code from book:
+
+    utilities.utility_definitions.word_size'simple_name
+
+    -- end of code from book
+
+    ;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_02.vhd
new file mode 100644
index 0000000..36f102d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_02.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library project;
+
+entity inline_02 is
+end entity inline_02;
+
+
+architecture test of inline_02 is
+begin
+
+  process is
+
+    use project.mem_pkg;
+    use project.mem_pkg.all;
+    variable words : word_array(0 to 3);
+
+  begin
+    assert
+    -- code from book (in text)
+    mem_pkg'path_name = ":project:mem_pkg:"
+    -- end code from book
+    ;
+    report mem_pkg'path_name;
+
+    assert
+    -- code from book (in text)
+    word'path_name = ":project:mem_pkg:word"
+    -- end code from book
+    ;
+    report word'path_name;
+
+    assert
+    -- code from book (in text)
+    word_array'path_name = ":project:mem_pkg:word_array"
+    -- end code from book
+    ;
+
+    report word_array'path_name;
+
+    assert
+    -- code from book (in text)
+    load_array'path_name = ":project:mem_pkg:load_array"
+    -- end code from book
+    ;
+    report load_array'path_name;
+
+    load_array(words, "/dev/null");
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_03.vhd
new file mode 100644
index 0000000..749cbee
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_03.vhd
@@ -0,0 +1,102 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package inline_03_defs is
+
+  -- code from book:
+
+  attribute cell_name : string;
+  attribute pin_number : positive;
+  attribute max_wire_delay : delay_length;
+  attribute encoding : bit_vector;
+
+
+  type length is range 0 to integer'high
+    units nm;
+      um = 1000 nm;
+      mm = 1000 um;
+      mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+      x, y : length;
+    end record coordinate;
+
+  attribute cell_position : coordinate;
+
+  -- end of code from book
+
+end package inline_03_defs;
+
+
+
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture std_cell of inline_03 is
+
+  use work.inline_03_defs.all;
+
+  signal enable, clk : bit;
+
+  type state_type is (idle_state, other_state);
+
+  -- code from book:
+
+  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+  attribute pin_number of enable : signal is 14;
+  attribute max_wire_delay of clk : signal is 50 ps;
+  attribute encoding of idle_state : literal is b"0000";
+  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+
+  -- end of code from book
+
+begin
+
+  the_fpu : block is
+  begin
+  end block the_fpu;
+
+  process is
+    use std.textio.all;
+    variable L : line;
+  begin
+    write(L, std_cell'cell_name);
+    writeline(output, L);
+    write(L, enable'pin_number);
+    writeline(output, L);
+    write(L, clk'max_wire_delay);
+    writeline(output, L);
+    write(L, idle_state[return state_type]'encoding);
+    writeline(output, L);
+    write(L, length'image(the_fpu'cell_position.x));
+    write(L, ' ');
+    write(L, length'image(the_fpu'cell_position.y));
+    writeline(output, L);
+
+    wait;
+  end process;
+
+end architecture std_cell;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_04.vhd
new file mode 100644
index 0000000..5cd9ec2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_04.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package inline_04 is
+
+  attribute cell_name : string;
+
+end package inline_04;
+
+
+
+entity flipflop is
+
+end entity flipflop;
+
+
+
+use work.inline_04.all;
+
+-- code from book:
+
+architecture std_cell of flipflop is
+
+  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+
+  -- . . .       -- other declarations
+
+begin
+  -- . . .
+end architecture std_cell;
+
+-- end of code from book
+
+
+
+-- code from book:
+
+package model_utilities is
+
+  attribute optimize : string;
+  attribute optimize of model_utilities : package is "level_4";
+
+  -- . . .
+
+end package model_utilities;
+
+-- end of code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_05.vhd
new file mode 100644
index 0000000..340664b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_05.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+  type stimulus_list is array (natural range <>) of integer;
+
+
+  -- code from book:
+
+  function "&" ( a, b : stimulus_list ) return stimulus_list;
+
+  attribute debug : string;
+  attribute debug of
+    "&" [ stimulus_list, stimulus_list return stimulus_list ] : function is
+    "source_statement_step";
+
+
+  type mvl is ('X', '0', '1', 'Z');
+  type mvl_vector is array ( integer range <>) of mvl;
+  function resolve_mvl ( drivers : mvl_vector ) return mvl;
+
+  subtype resolved_mvl is resolve_mvl mvl;
+
+
+  type builtin_types is (builtin_bit, builtin_mvl, builtin_integer);
+  attribute builtin : builtin_types;
+  
+  attribute builtin of resolved_mvl : subtype is builtin_mvl;
+
+  -- end of code from book
+
+  function "&" ( a, b : stimulus_list ) return stimulus_list is
+  begin
+    return stimulus_list'(1 to 0 => 0);
+  end function "&";
+
+  function resolve_mvl ( drivers : mvl_vector ) return mvl is
+  begin
+    return drivers(drivers'left);
+  end function resolve_mvl;
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd
new file mode 100644
index 0000000..2d0b875
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_06.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+use std.textio.all;
+
+architecture test of inline_06 is
+
+  subtype encoding_type is bit_vector(1 downto 0);
+  attribute encoding : encoding_type;
+
+begin
+
+
+  process1 : process is
+
+    -- code from book:
+
+    type controller_state is (idle, active, fail_safe);
+    type load_level is (idle, busy, overloaded);
+
+    attribute encoding of idle [ return controller_state ] : literal is b"00";
+    attribute encoding of active [ return controller_state ] : literal is b"01";
+    attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
+
+    -- end of code from book
+
+    variable L : line;
+
+  begin
+    write(L, string'("process1"));
+    writeline(output, L);
+    write(L, idle [ return controller_state ] ' encoding);
+    writeline(output, L);
+    write(L, active [ return controller_state ] ' encoding);
+    writeline(output, L);
+    write(L, fail_safe [ return controller_state ] ' encoding);
+    writeline(output, L);
+    wait;
+  end process process1;
+
+
+  process2 : process is
+
+    type controller_state is (idle, active, fail_safe);
+    type load_level is (idle, busy, overloaded);
+
+    attribute encoding of idle : literal is b"11";
+
+    variable L : line;
+
+  begin
+    write(L, string'("process2"));
+    writeline(output, L);
+    write(L, idle [ return controller_state ] ' encoding);
+    writeline(output, L);
+    write(L, idle [ return load_level ] ' encoding);
+    writeline(output, L);
+    wait;
+  end process process2;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_07.vhd
new file mode 100644
index 0000000..6ed29d9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_07.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_07 is
+
+  component multiplier is
+  end component multiplier;
+
+  type length is range 0 to integer'high
+    units nm;
+      um = 1000 nm;
+      mm = 1000 um;
+      mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+      x, y : length;
+    end record coordinate;
+
+  type orientation_type is (up, down, left, right);
+
+  attribute cell_allocation : string;
+  attribute cell_position : coordinate;
+  attribute cell_orientation : orientation_type;
+
+  -- code from book:
+
+  attribute cell_allocation of mult : label is "wallace_tree_multiplier";
+  attribute cell_position of mult : label is ( 1200 um, 4500 um );
+  attribute cell_orientation of mult : label is down;
+
+  -- end of code from book
+
+begin
+
+  mult : component multiplier;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd
new file mode 100644
index 0000000..2005094
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_08.vhd
@@ -0,0 +1,117 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture std_cell of inline_08 is
+
+  attribute cell_name : string;
+  attribute pin_number : positive;
+  attribute max_wire_delay : delay_length;
+  attribute encoding : bit_vector;
+
+  type length is range 0 to integer'high
+    units nm;
+      um = 1000 nm;
+      mm = 1000 um;
+      mil = 25400 nm;
+    end units length;
+
+  type coordinate is record
+      x, y : length;
+    end record coordinate;
+
+  attribute cell_position : coordinate;
+
+  type built_in_type is (bv_incr, std_incr);
+  attribute built_in : built_in_type;
+
+  signal enable, clk : bit;
+
+  type state_type is (idle_state, other_state);
+
+  type speed_range is (high, other_speed);
+  type coolant_level is (high, other_level);
+
+  attribute representation : string;
+
+  function increment ( vector : in bit_vector ) return bit_vector is
+  begin
+  end;
+
+  function increment ( vector : in std_logic_vector ) return std_logic_vector is
+  begin
+  end;
+
+  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
+  attribute pin_number of enable : signal is 14;
+  attribute max_wire_delay of clk : signal is 50 ps;
+  attribute encoding of idle_state : literal is b"0000";
+  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
+  attribute built_in of
+    increment [ bit_vector return bit_vector ] : function is bv_incr;
+  attribute built_in of
+    increment [ std_logic_vector return std_logic_vector ] : function is std_incr;
+  attribute representation of high [ return speed_range ] : literal is "byte";
+  attribute representation of high [ return coolant_level ] : literal is "word";
+
+begin
+
+  the_fpu : block is
+  begin
+  end block the_fpu;
+
+  process is
+    variable v1 : string(1 to 11);
+    variable v2 : positive;
+    variable v3 : time;
+    variable v4 : bit_vector(0 to 3);
+    variable v5 : coordinate;
+    variable v6, v7 : built_in_type;
+    variable v8, v9 : string(1 to 4);
+  begin
+
+    -- code from book included...
+
+    v1 := std_cell'cell_name ;
+    v2 := enable'pin_number ;
+    v3 := clk'max_wire_delay ;
+    v4 := idle_state'encoding ;
+    v5 := the_fpu'cell_position ;
+
+    v6 := increment [ bit_vector return bit_vector ] 'built_in ;
+    v7 := increment [ std_logic_vector return std_logic_vector ] 'built_in ;
+
+    v8 := high [ return speed_range ] 'representation ;
+    v9 := high [ return coolant_level ] 'representation ;
+
+    -- end code from book
+
+    wait;
+  end process;
+
+end architecture std_cell;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_09.vhd
new file mode 100644
index 0000000..7ecccaa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_09.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package inline_09_defs is
+
+  attribute attr : integer;
+
+end package inline_09_defs;
+
+
+
+use work.inline_09_defs.all;
+
+entity e is
+  port ( p : in bit );
+  attribute attr of p : signal is 1;
+end entity e;
+
+
+architecture arch of e is
+begin
+
+  assert false report integer'image(p'attr);
+
+end architecture arch;
+
+
+
+use work.inline_09_defs.all;
+
+entity inline_09 is
+end entity inline_09;
+
+
+
+architecture test of inline_09 is
+
+  signal s : bit;
+
+  attribute attr of s : signal is 2;
+
+begin
+
+  -- code from book
+
+  c1 : entity work.e(arch)
+    port map ( p => s );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_10.vhd
new file mode 100644
index 0000000..267f4ae
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_10.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package inline_10 is
+
+  -- code from book
+
+  attribute foreign : string;
+
+  -- end code from book
+
+end package inline_10;
+
+
+
+entity and2 is
+end entity and2;
+
+
+-- code from book
+
+architecture accelerated of and2 is
+  attribute foreign of accelerated : architecture is
+    "accelerate/function:and_2in/nocheck";
+begin
+end architecture accelerated;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_11.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_11.vhd
new file mode 100644
index 0000000..11d66ca
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/inline_11.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_11 is
+
+end entity inline_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_11 is
+
+  component comp is
+  end component comp;
+
+  signal clk_phase1, clk_phase2 : bit;
+
+  -- code from book:
+
+  group signal_pair is (signal, signal);
+
+  group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
+
+  attribute max_skew : time;
+
+  attribute max_skew of clock_pair : group is 200 ps;
+
+  group component_instances is ( label <> );
+
+  group U1 : component_instances ( nand1, nand2, nand3 );
+  group U2 : component_instances ( inv1, inv2 );
+
+  attribute IC_allocation : string;
+
+  attribute IC_allocation of U1 : group is "74LS00";
+  attribute IC_allocation of U2 : group is "74LS04";
+
+  -- end of code from book
+
+begin
+
+
+  nand1 : component comp;
+  nand2 : component comp;
+  nand3 : component comp;
+  inv1 : component comp;
+  inv2 : component comp;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_pkg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_pkg.vhd
new file mode 100644
index 0000000..3965503
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_pkg.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package mem_pkg is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (natural range <>) of word;
+
+  procedure load_array ( words : out word_array;  file_name : string );
+
+end package mem_pkg;
+
+--------------------------------------------------
+
+package body mem_pkg is
+
+  procedure load_array ( words : out word_array;  file_name : string ) is
+    -- words'path_name = ":project:mem_pkg:load_array:words"
+
+    use std.textio.all;
+    file load_file : text open read_mode is file_name;
+    -- load_file'path_name = ":project:mem_pkg:load_array:load_file"
+
+    procedure read_line is
+    -- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
+      variable current_line : line;
+      -- current_line'path_name =
+      --    ":project:mem_pkg:load_array:read_line:current_line"
+    begin
+      -- . . .
+      -- not in book
+      report current_line'path_name;
+      -- end not in book
+    end procedure read_line;
+
+  begin  -- load_array
+    -- . . .
+    -- not in book
+    report mem_pkg'path_name;
+    report words'path_name;
+    report load_file'path_name;
+    report read_line'path_name;
+    read_line;
+    -- end not in book
+  end procedure load_array;
+
+end package body mem_pkg;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_read.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_read.vhd
new file mode 100644
index 0000000..a320a42
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/mem_read.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity mem_read is
+end entity mem_read;
+
+
+architecture test of mem_read is
+
+  attribute trace : string;
+
+  subtype byte is bit_vector(7 downto 0);
+  type byte_vector is array (natural range <>) of byte;
+
+  type ram_bus is record
+      d : byte;
+      cmd, status, clk : bit;
+    end record ram_bus;
+
+  -- code from book
+
+  procedure mem_read ( address : in natural;
+                       result : out byte_vector;
+                       signal memory_bus : inout ram_bus ) is
+
+    attribute trace of address : constant is "integer/hex";
+    attribute trace of result : variable is "byte/multiple/hex";
+    attribute trace of memory_bus : signal is
+      "custom/command=rambus.cmd";
+    -- . . .
+
+  begin
+    -- . . .
+    -- not in book
+    report address'trace;
+    report result'trace;
+    report memory_bus'trace;
+    -- end not in book
+  end procedure mem_read;
+
+  -- end code from book
+
+  signal memory_bus : ram_bus;
+
+begin
+
+  process is
+    variable address : natural;
+    variable result : byte_vector(0 to 3);
+  begin
+    mem_read ( address, result, memory_bus );
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/sequencer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/sequencer.vhd
new file mode 100644
index 0000000..f35a75a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/sequencer.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package timing_attributes is
+
+  attribute max_wire_delay : delay_length;
+
+end package timing_attributes;
+
+
+entity sequencer is
+end entity sequencer;
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.timing_attributes.all;
+
+architecture structural of sequencer is
+
+  signal recovered_clk1, recovered_clk2 : std_logic;
+  signal test_enable : std_logic;
+  signal test_data : std_logic_vector(0 to 15);
+
+  attribute max_wire_delay of
+    recovered_clk1, recovered_clk2 : signal is 100 ps;
+
+  attribute max_wire_delay of others : signal is 200 ps;
+
+  -- . . .
+
+begin
+  -- . . .
+  -- not in book
+  assert false report time'image(recovered_clk1'max_wire_delay) severity note;
+  assert false report time'image(recovered_clk2'max_wire_delay) severity note;
+  assert false report time'image(test_enable'max_wire_delay) severity note;
+  assert false report time'image(test_data'max_wire_delay) severity note;
+  -- end not in book
+end architecture structural;
+
+-- code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/tb_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/tb_flipflop.vhd
new file mode 100644
index 0000000..f1aacab
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/tb_flipflop.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+
+entity tb_flipflop is
+end entity tb_flipflop;
+
+
+architecture test of tb_flipflop is
+
+  signal clk, d, q : bit;
+
+begin
+
+  dut : entity work.flipflop(behavior)
+    generic map ( Tsetup => 3 ns )
+    port map ( clk => clk, d => d, q => q );
+
+  clk <= '1' after 10 ns, '0' after 20 ns;
+
+  d <= '1' after 8 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/top.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/top.vhd
new file mode 100644
index 0000000..46c69c6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/top.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity top is
+end entity top;
+
+--------------------------------------------------
+
+architecture top_arch of top is
+
+  signal top_sig : -- . . .;                  -- 1
+    --
+    bit;
+    --
+
+begin
+
+  stimulus : process is
+    variable var : -- . . .;                  -- 2
+    --
+    bit;
+    --
+  begin
+    -- . . .
+    --
+    report "--1: " & top'path_name;
+    report "--1: " & top'instance_name;
+    report "--1: " & top_sig'path_name;
+    report "--1: " & top_sig'instance_name;
+    report "--2: " & stimulus'path_name;
+    report "--2: " & stimulus'instance_name;
+    report "--2: " & var'path_name;
+    report "--2: " & var'instance_name;
+    wait;
+    --
+  end process stimulus;
+
+  rep_gen : for index in 0 to 7 generate
+  begin
+
+    end_gen : if index = 7 generate
+      signal end_sig : -- . . .;              -- 3
+      --
+      bit;
+      --
+    begin
+      -- . . .
+      assert false report "--3: " & end_sig'path_name;
+      assert false report "--3: " & end_sig'instance_name;
+      --
+    end generate end_gen;
+
+    other_gen : if index /= 7 generate
+      signal other_sig : -- . . .;            -- 4
+      --
+      bit;
+      --
+    begin
+      other_comp : entity work.bottom(bottom_arch)
+        port map ( -- . . . );
+      --
+          port_name => open );
+      assert false report "--4: " & other_sig'path_name;
+      assert false report "--4: " & other_sig'instance_name;
+      --
+    end generate other_gen;
+
+  end generate rep_gen;
+
+end architecture top_arch;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/voltage_defs.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/voltage_defs.vhd
new file mode 100644
index 0000000..e0774e6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/attributes-and-groups/voltage_defs.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package voltage_defs is
+
+  type voltage is range -2e9 to +2e9
+    units
+      nV;
+      uV = 1000 nV;
+      mV = 1000 uV;
+      V = 1000 mV;
+    end units voltage;
+
+  attribute resolution : real;
+
+  attribute resolution of nV : units is 1.0;
+  attribute resolution of uV : units is 0.01;
+  attribute resolution of mV : units is 0.01;
+  attribute resolution of V : units is 0.001;
+
+end package voltage_defs;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/compliant.exp b/testsuite/vests/vhdl-ams/ashenden/compliant/compliant.exp
new file mode 100644
index 0000000..f4d0f08
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/compliant.exp
@@ -0,0 +1,586 @@
+
+# Copyright (C) 2003-2004 University of Cincinnati
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  
+
+# Please email any bugs, comments, and/or additions to this file to:
+# vests@cliftonlabs.com
+
+# Authors: Philip A. Wilsey	philip.wilsey@ieee.org
+# 	   Dale E. Martin	dmartin@cliftonlabs.com
+
+setup_test_group "Ashenden:VHDL-AMS Compliant Cases" "vhdl-ams"
+
+build_compliant_test util/clock_duty.vhd
+build_compliant_test util/gain.vhd
+build_compliant_test util/resistor.vhd
+build_compliant_test util/src_constant.vhd
+build_compliant_test util/src_pulse.vhd
+build_compliant_test util/src_sine.vhd
+build_compliant_test util/sum2.vhd
+build_compliant_test util/stimulus_generators.vhd
+
+build_compliant_test AMS_CS1_Mixed_Sig/switch_dig_2in.vhd
+build_compliant_test AMS_CS1_Mixed_Sig/a2d_nbit.vhd
+build_compliant_test AMS_CS1_Mixed_Sig/dac_10_bit.vhd
+build_compliant_test AMS_CS1_Mixed_Sig/tb_2in_switch.vhd
+build_compliant_test AMS_CS1_Mixed_Sig/tb_a2d_d2a.vhd
+build_compliant_test AMS_CS1_Mixed_Sig/tb_CS1.vhd
+
+build_compliant_test AMS_CS2_Mixed_Tech/gain.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/gain_e.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/sum2.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/limiter.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/lpf_1.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/lead_lag.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/DC_Motor.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/gear_rv_r.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/stop_r.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/lead_lag_ztf.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/lead_lag_diff.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/tb_CS2_Mech_Domain.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_Diff.vhd
+build_compliant_test AMS_CS2_Mixed_Tech/tb_CS2_Z_Domain_ZTF.vhd
+
+build_compliant_test AMS_CS3_Power_Systems/tb_BuckConverter.vhd
+build_compliant_test AMS_CS3_Power_Systems/capacitor.vhd
+build_compliant_test AMS_CS3_Power_Systems/switch_dig.vhd
+build_compliant_test AMS_CS3_Power_Systems/buck_sw.vhd
+build_compliant_test AMS_CS3_Power_Systems/sw_LoopCtrl.vhd
+build_compliant_test AMS_CS3_Power_Systems/sw_LoopCtrl_wa.vhd
+build_compliant_test AMS_CS3_Power_Systems/comp_2p2z.vhd
+build_compliant_test AMS_CS3_Power_Systems/pwl_load.vhd
+build_compliant_test AMS_CS3_Power_Systems/pwl_load_wa.vhd
+build_compliant_test AMS_CS3_Power_Systems/CalcBuckParams.vhd
+build_compliant_test AMS_CS3_Power_Systems/CalcBuckParams_wa.vhd
+build_compliant_test AMS_CS3_Power_Systems/tb_CalcBuckParams.vhd
+build_compliant_test AMS_CS3_Power_Systems/tb_CS3_BuckConverter_average.vhd
+
+build_compliant_test AMS_CS4_RF_IC/bfsk.vhd
+build_compliant_test AMS_CS4_RF_IC/bfsk_wa.vhd
+build_compliant_test AMS_CS4_RF_IC/MeasFreq.vhd
+build_compliant_test AMS_CS4_RF_IC/v_BPF.vhd
+build_compliant_test AMS_CS4_RF_IC/v_Sum.vhd
+build_compliant_test AMS_CS4_RF_IC/PLL.vhd
+build_compliant_test AMS_CS4_RF_IC/tb_pll.vhd
+build_compliant_test AMS_CS4_RF_IC/tb_CS4_CommSys_PLL.vhd
+build_compliant_test AMS_CS4_RF_IC/tb_CS4_CommSys_det.vhd
+
+build_compliant_test AMS_CS5_RC_Airplane/amp_lim.vhd
+build_compliant_test AMS_CS5_RC_Airplane/pwl_functions.vhd
+build_compliant_test AMS_CS5_RC_Airplane/prop_pwl.vhd
+build_compliant_test AMS_CS5_RC_Airplane/tb_CS5_Amp_Lim.vhd
+build_compliant_test AMS_CS5_RC_Airplane/tb_CS5_Prop.vhd
+build_compliant_test AMS_CS5_RC_Airplane/tb_CS5_CC_Rudder.vhd
+build_compliant_test AMS_CS5_RC_Airplane/tb_CS5_Rudder_Power.vhd
+build_compliant_test AMS_CS5_RC_Airplane/tb_CS5_HCL.vhd
+
+build_compliant_test access-types/list_traversal.vhd
+build_compliant_test access-types/list_search.vhd
+build_compliant_test access-types/bounded_buffer_adt.vhd
+build_compliant_test access-types/receiver.vhd
+build_compliant_test access-types/ordered_collection_adt.vhd
+build_compliant_test access-types/stimulus_types-1.vhd
+build_compliant_test access-types/test_bench-1.vhd
+build_compliant_test access-types/inline_01.vhd
+build_compliant_test access-types/inline_02a.vhd
+build_compliant_test access-types/inline_03.vhd
+build_compliant_test access-types/inline_04a.vhd
+build_compliant_test access-types/inline_05.vhd
+build_compliant_test access-types/inline_06a.vhd
+build_compliant_test access-types/inline_07a.vhd
+build_compliant_test access-types/inline_08.vhd
+build_compliant_test access-types/inline_09.vhd
+build_compliant_test access-types/tb_bounded_buffer_adt.vhd
+
+build_compliant_test aliases/controller_system.vhd
+build_compliant_test aliases/safety_switch.vhd
+build_compliant_test aliases/function_plus.vhd
+build_compliant_test aliases/DMA_controller_types_and_utilities.vhd
+build_compliant_test aliases/DMA_controller.vhd
+build_compliant_test aliases/inline_01a.vhd
+build_compliant_test aliases/inline_02.vhd
+build_compliant_test aliases/inline_03a.vhd
+build_compliant_test aliases/inline_04.vhd
+build_compliant_test aliases/inline_05.vhd
+build_compliant_test aliases/inline_06.vhd
+build_compliant_test aliases/tb_function_plus.vhd
+
+build_compliant_test analog-modeling/control_system.vhd
+build_compliant_test analog-modeling/comparator.vhd
+build_compliant_test analog-modeling/variable_comparator.vhd
+build_compliant_test analog-modeling/transmission_line.vhd
+build_compliant_test analog-modeling/transmission_line_wa.vhd
+build_compliant_test analog-modeling/inductor.vhd
+build_compliant_test analog-modeling/piston.vhd
+build_compliant_test analog-modeling/inductor-1.vhd
+build_compliant_test analog-modeling/moving_mass.vhd
+build_compliant_test analog-modeling/moving_mass_wa.vhd
+build_compliant_test analog-modeling/opamp.vhd
+build_compliant_test analog-modeling/quad_opamp.vhd
+build_compliant_test analog-modeling/quad_opamp_wa.vhd
+build_compliant_test analog-modeling/bit_to_analog.vhd
+build_compliant_test analog-modeling/std_logic_to_analog.vhd
+build_compliant_test analog-modeling/opamp-1.vhd
+build_compliant_test analog-modeling/opamp_wa-1.vhd
+build_compliant_test analog-modeling/resistor.vhd
+build_compliant_test analog-modeling/capacitor.vhd
+build_compliant_test analog-modeling/inverting_integrator.vhd
+build_compliant_test analog-modeling/timer.vhd
+build_compliant_test analog-modeling/ball.vhd
+build_compliant_test analog-modeling/ball_wa.vhd
+build_compliant_test analog-modeling/analog_switch.vhd
+build_compliant_test analog-modeling/pendulum.vhd
+build_compliant_test analog-modeling/pendulum_wa.vhd
+build_compliant_test analog-modeling/triangle_waveform.vhd
+build_compliant_test analog-modeling/triangle_waveform_wa.vhd
+build_compliant_test analog-modeling/comparator-1.vhd
+build_compliant_test analog-modeling/dac_12_bit.vhd
+build_compliant_test analog-modeling/diode.vhd
+build_compliant_test analog-modeling/inline_01a.vhd
+build_compliant_test analog-modeling/inline_02a.vhd
+build_compliant_test analog-modeling/inline_03a.vhd
+build_compliant_test analog-modeling/inline_04a.vhd
+build_compliant_test analog-modeling/inline_05a.vhd
+build_compliant_test analog-modeling/inline_06a.vhd
+build_compliant_test analog-modeling/inline_07a.vhd
+build_compliant_test analog-modeling/inline_08a.vhd
+build_compliant_test analog-modeling/inline_09a.vhd
+build_compliant_test analog-modeling/inline_10a.vhd
+build_compliant_test analog-modeling/inline_11a.vhd
+build_compliant_test analog-modeling/inline_12a.vhd
+build_compliant_test analog-modeling/inline_13a.vhd
+build_compliant_test analog-modeling/inline_14a.vhd
+build_compliant_test analog-modeling/inline_15a.vhd
+build_compliant_test analog-modeling/inline_16a.vhd
+build_compliant_test analog-modeling/inline_17a.vhd
+build_compliant_test analog-modeling/inline_18a.vhd
+build_compliant_test analog-modeling/inline_19a.vhd
+build_compliant_test analog-modeling/inline_20a.vhd
+build_compliant_test analog-modeling/inline_21a.vhd
+build_compliant_test analog-modeling/inline_22a.vhd
+build_compliant_test analog-modeling/inline_23a.vhd
+build_compliant_test analog-modeling/inline_24a.vhd
+build_compliant_test analog-modeling/tb_control_system.vhd
+build_compliant_test analog-modeling/tb_comparator.vhd
+build_compliant_test analog-modeling/tb_variable_comparator.vhd
+build_compliant_test analog-modeling/tb_transmission_line.vhd
+build_compliant_test analog-modeling/tb_piston.vhd
+build_compliant_test analog-modeling/tb_moving_mass.vhd
+build_compliant_test analog-modeling/tb_quad_opamp.vhd
+build_compliant_test analog-modeling/tb_bit_to_analog.vhd
+build_compliant_test analog-modeling/tb_std_logic_to_analog.vhd
+build_compliant_test analog-modeling/tb_inv_integrator.vhd
+build_compliant_test analog-modeling/tb_analog_switch.vhd
+build_compliant_test analog-modeling/tb_triangle_waveform.vhd
+build_compliant_test analog-modeling/tb_comparator-1.vhd
+build_compliant_test analog-modeling/tb_diode.vhd
+
+build_compliant_test attributes-and-groups/flipflop.vhd
+build_compliant_test attributes-and-groups/mem_pkg.vhd
+build_compliant_test attributes-and-groups/top.vhd
+build_compliant_test attributes-and-groups/bottom.vhd
+build_compliant_test attributes-and-groups/add_with_overflow.vhd
+build_compliant_test attributes-and-groups/74x138.vhd
+build_compliant_test attributes-and-groups/mem_read.vhd
+build_compliant_test attributes-and-groups/gate_components.vhd
+build_compliant_test attributes-and-groups/CPU.vhd
+build_compliant_test attributes-and-groups/controller.vhd
+build_compliant_test attributes-and-groups/voltage_defs.vhd
+build_compliant_test attributes-and-groups/sequencer.vhd
+build_compliant_test attributes-and-groups/display_interface.vhd
+build_compliant_test attributes-and-groups/clock_buffer.vhd
+build_compliant_test attributes-and-groups/inline_01.vhd
+build_compliant_test attributes-and-groups/inline_02.vhd
+build_compliant_test attributes-and-groups/inline_03.vhd
+build_compliant_test attributes-and-groups/inline_04.vhd
+build_compliant_test attributes-and-groups/inline_05.vhd
+build_compliant_test attributes-and-groups/inline_06.vhd
+build_compliant_test attributes-and-groups/inline_07.vhd
+build_compliant_test attributes-and-groups/inline_08.vhd
+build_compliant_test attributes-and-groups/inline_09.vhd
+build_compliant_test attributes-and-groups/inline_10.vhd
+build_compliant_test attributes-and-groups/inline_11.vhd
+build_compliant_test attributes-and-groups/tb_flipflop.vhd
+
+build_compliant_test components-and-configs/opamp.vhd
+build_compliant_test components-and-configs/automotive_valve_defs.vhd
+build_compliant_test components-and-configs/automotive_valve.vhd
+build_compliant_test components-and-configs/brake_system.vhd
+build_compliant_test components-and-configs/opamp_mosfets.vhd
+build_compliant_test components-and-configs/notch_filter.vhd
+build_compliant_test components-and-configs/notch_filter_down_to_device_level.vhd
+build_compliant_test components-and-configs/notch_filter_full.vhd
+build_compliant_test components-and-configs/fm_radio.vhd
+build_compliant_test components-and-configs/successive_approx_adc.vhd
+build_compliant_test components-and-configs/sensor_interface.vhd
+build_compliant_test components-and-configs/sensor_interface_with_timing.vhd
+build_compliant_test components-and-configs/computer_system.vhd
+build_compliant_test components-and-configs/decoder_3_to_8.vhd
+build_compliant_test components-and-configs/reg-1.vhd
+build_compliant_test components-and-configs/computer_structure.vhd
+build_compliant_test components-and-configs/single_board_computer.vhd
+build_compliant_test components-and-configs/intermediate.vhd
+build_compliant_test components-and-configs/logic_block.vhd
+build_compliant_test components-and-configs/control_section.vhd
+build_compliant_test components-and-configs/controller_with_timing-1.vhd
+build_compliant_test components-and-configs/interlock_control.vhd
+build_compliant_test components-and-configs/interlock_control_with_estimates.vhd
+build_compliant_test components-and-configs/misc_logic.vhd
+build_compliant_test components-and-configs/misc_logic_reconfigured.vhd
+build_compliant_test components-and-configs/inline_02a.vhd
+build_compliant_test components-and-configs/inline_04a.vhd
+build_compliant_test components-and-configs/inline_05.vhd
+
+build_compliant_test composite-data/coeff_ram.vhd
+build_compliant_test composite-data/transmission_lines.vhd
+build_compliant_test composite-data/modem_controller.vhd
+build_compliant_test composite-data/and_multiple.vhd
+build_compliant_test composite-data/tb_and_multiple.vhd
+build_compliant_test composite-data/byte_swap.vhd
+build_compliant_test composite-data/computer.vhd
+build_compliant_test composite-data/inline_01.vhd
+build_compliant_test composite-data/inline_02a.vhd
+build_compliant_test composite-data/inline_03.vhd
+build_compliant_test composite-data/inline_04a.vhd
+build_compliant_test composite-data/inline_05.vhd
+build_compliant_test composite-data/inline_06a.vhd
+build_compliant_test composite-data/inline_07a.vhd
+build_compliant_test composite-data/inline_08.vhd
+build_compliant_test composite-data/inline_09a.vhd
+build_compliant_test composite-data/inline_10.vhd
+build_compliant_test composite-data/inline_11a.vhd
+build_compliant_test composite-data/inline_12.vhd
+build_compliant_test composite-data/inline_13.vhd
+build_compliant_test composite-data/inline_14a.vhd
+build_compliant_test composite-data/inline_15.vhd
+build_compliant_test composite-data/inline_16.vhd
+build_compliant_test composite-data/inline_17a.vhd
+build_compliant_test composite-data/tb_coeff_ram.vhd
+build_compliant_test composite-data/tb_byte_swap.vhd
+
+build_compliant_test design-processing/inverting_integrator.vhd
+build_compliant_test design-processing/dff.vhd
+build_compliant_test design-processing/volume_sensor.vhd
+build_compliant_test design-processing/active_filter.vhd
+build_compliant_test design-processing/inline_01a.vhd
+build_compliant_test design-processing/inline_02a.vhd
+build_compliant_test design-processing/inline_03a.vhd
+build_compliant_test design-processing/inline_04a.vhd
+build_compliant_test design-processing/inline_05a.vhd
+build_compliant_test design-processing/tb_volume_sensor.vhd
+
+build_compliant_test digital-modeling/program_rom.vhd
+build_compliant_test digital-modeling/and_or_inv.vhd
+build_compliant_test digital-modeling/clock_gen.vhd
+build_compliant_test digital-modeling/mux.vhd
+build_compliant_test digital-modeling/edge_triggered_Dff.vhd
+build_compliant_test digital-modeling/mux2.vhd
+build_compliant_test digital-modeling/clock_gen-1.vhd
+build_compliant_test digital-modeling/clock_gen-2.vhd
+build_compliant_test digital-modeling/computer_system.vhd
+build_compliant_test digital-modeling/asym_delay.vhd
+build_compliant_test digital-modeling/and2.vhd
+build_compliant_test digital-modeling/zmux.vhd
+build_compliant_test digital-modeling/zmux-1.vhd
+build_compliant_test digital-modeling/scheduler.vhd
+build_compliant_test digital-modeling/alu.vhd
+build_compliant_test digital-modeling/full_adder.vhd
+build_compliant_test digital-modeling/S_R_flipflop.vhd
+build_compliant_test digital-modeling/S_R_flipflop-1.vhd
+build_compliant_test digital-modeling/rom.vhd
+build_compliant_test digital-modeling/reg4.vhd
+build_compliant_test digital-modeling/counter.vhd
+build_compliant_test digital-modeling/microprocessor.vhd
+build_compliant_test digital-modeling/inline_01.vhd
+build_compliant_test digital-modeling/inline_02.vhd
+build_compliant_test digital-modeling/inline_03.vhd
+build_compliant_test digital-modeling/inline_04.vhd
+build_compliant_test digital-modeling/inline_05.vhd
+build_compliant_test digital-modeling/inline_06.vhd
+build_compliant_test digital-modeling/inline_07.vhd
+build_compliant_test digital-modeling/inline_08.vhd
+build_compliant_test digital-modeling/inline_09.vhd
+build_compliant_test digital-modeling/inline_10.vhd
+build_compliant_test digital-modeling/inline_11.vhd
+build_compliant_test digital-modeling/inline_12.vhd
+build_compliant_test digital-modeling/inline_13.vhd
+build_compliant_test digital-modeling/inline_14.vhd
+build_compliant_test digital-modeling/inline_15.vhd
+build_compliant_test digital-modeling/inline_16.vhd
+build_compliant_test digital-modeling/inline_17.vhd
+build_compliant_test digital-modeling/inline_18.vhd
+build_compliant_test digital-modeling/inline_19.vhd
+build_compliant_test digital-modeling/inline_20.vhd
+build_compliant_test digital-modeling/inline_21.vhd
+build_compliant_test digital-modeling/inline_22.vhd
+build_compliant_test digital-modeling/inline_23.vhd
+build_compliant_test digital-modeling/inline_24.vhd
+build_compliant_test digital-modeling/inline_28a.vhd
+build_compliant_test digital-modeling/tb_and_or_inv.vhd
+build_compliant_test digital-modeling/tb_edge_triggered_Dff.vhd
+build_compliant_test digital-modeling/tb_mux2.vhd
+build_compliant_test digital-modeling/tb_and2.vhd
+build_compliant_test digital-modeling/tb_full_adder.vhd
+build_compliant_test digital-modeling/tb_S_R_flipflop.vhd
+build_compliant_test digital-modeling/tb_S_R_flipflop-1.vhd
+build_compliant_test digital-modeling/tb_rom.vhd
+build_compliant_test digital-modeling/tb_reg4.vhd
+build_compliant_test digital-modeling/tb_counter.vhd
+
+build_compliant_test files-and-IO/ROM.vhd
+build_compliant_test files-and-IO/stimulate_network.vhd
+build_compliant_test files-and-IO/CPU.vhd
+build_compliant_test files-and-IO/cache.vhd
+build_compliant_test files-and-IO/read_array.vhd
+build_compliant_test files-and-IO/stimulus_generator.vhd
+build_compliant_test files-and-IO/read_transform.vhd
+build_compliant_test files-and-IO/textio.vhd
+build_compliant_test files-and-IO/stimulus_interpreter-1.vhd
+build_compliant_test files-and-IO/bus_monitor.vhd
+build_compliant_test files-and-IO/inline_01.vhd
+build_compliant_test files-and-IO/inline_02.vhd
+build_compliant_test files-and-IO/inline_03.vhd
+build_compliant_test files-and-IO/inline_04.vhd
+build_compliant_test files-and-IO/inline_05.vhd
+build_compliant_test files-and-IO/inline_06.vhd
+build_compliant_test files-and-IO/inline_08.vhd
+build_compliant_test files-and-IO/inline_09.vhd
+build_compliant_test files-and-IO/inline_10.vhd
+build_compliant_test files-and-IO/tb_ROM.vhd
+build_compliant_test files-and-IO/tb_cache.vhd
+
+build_compliant_test frequency-modeling/v_source.vhd
+build_compliant_test frequency-modeling/v_source-1.vhd
+build_compliant_test frequency-modeling/nmos_transistor.vhd
+build_compliant_test frequency-modeling/nmos_transistor_wa.vhd
+build_compliant_test frequency-modeling/lowpass-1.vhd
+build_compliant_test frequency-modeling/lowpass-2.vhd
+build_compliant_test frequency-modeling/lowpass-3.vhd
+build_compliant_test frequency-modeling/opamp.vhd
+build_compliant_test frequency-modeling/opamp_2pole.vhd
+build_compliant_test frequency-modeling/opamp_2pole_res.vhd
+build_compliant_test frequency-modeling/lowpass-4.vhd
+build_compliant_test frequency-modeling/lowpass-5.vhd
+build_compliant_test frequency-modeling/lowpass.vhd
+build_compliant_test frequency-modeling/inline_01a.vhd
+build_compliant_test frequency-modeling/inline_02a.vhd
+build_compliant_test frequency-modeling/inline_03a.vhd
+build_compliant_test frequency-modeling/tb_v_source.vhd
+build_compliant_test frequency-modeling/tb_mosfet_noisy.vhd
+build_compliant_test frequency-modeling/tb_opamp.vhd
+build_compliant_test frequency-modeling/tb_opamp_2pole.vhd
+build_compliant_test frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd
+build_compliant_test frequency-modeling/tb_lpf_dot_ltf_ztf.vhd
+
+build_compliant_test fundamental/adc.vhd
+build_compliant_test fundamental/resistor.vhd
+build_compliant_test fundamental/vc_amp.vhd
+build_compliant_test fundamental/comparator.vhd
+build_compliant_test fundamental/d_ff.vhd
+build_compliant_test fundamental/propulsion.vhd
+build_compliant_test fundamental/test_bench-1.vhd
+build_compliant_test fundamental/tb_adc.vhd
+
+build_compliant_test generators/led_bar_display.vhd
+build_compliant_test generators/resistor_pack.vhd
+build_compliant_test generators/graphics_engine.vhd
+build_compliant_test generators/memory_board.vhd
+build_compliant_test generators/carry_chain.vhd
+build_compliant_test generators/computer_system.vhd
+build_compliant_test generators/fanout_tree.vhd
+build_compliant_test generators/computer_system-1.vhd
+build_compliant_test generators/architectural.vhd
+build_compliant_test generators/identical_devices.vhd
+build_compliant_test generators/down_to_chips.vhd
+build_compliant_test generators/last_pass_spice.vhd
+build_compliant_test generators/inline_01.vhd
+build_compliant_test generators/inline_02.vhd
+
+build_compliant_test generics/control_unit.vhd
+build_compliant_test generics/timer.vhd
+build_compliant_test generics/reg.vhd
+build_compliant_test generics/multiple_opamp.vhd
+build_compliant_test generics/inline_01.vhd
+build_compliant_test generics/inline_02a.vhd
+build_compliant_test generics/inline_03.vhd
+build_compliant_test generics/inline_05a.vhd
+build_compliant_test generics/inline_06.vhd
+build_compliant_test generics/inline_07.vhd
+build_compliant_test generics/inline_08.vhd
+build_compliant_test generics/inline_09a.vhd
+build_compliant_test generics/tb_timer_w_stim.vhd
+
+build_compliant_test guards-and-blocks/computer_system.vhd
+build_compliant_test guards-and-blocks/processor.vhd
+build_compliant_test guards-and-blocks/resolve.vhd
+build_compliant_test guards-and-blocks/tri_state_reg.vhd
+build_compliant_test guards-and-blocks/data_logger.vhd
+build_compliant_test guards-and-blocks/reg_read_selector.vhd
+build_compliant_test guards-and-blocks/processor_node.vhd
+build_compliant_test guards-and-blocks/latch.vhd
+build_compliant_test guards-and-blocks/computer_system-1.vhd
+build_compliant_test guards-and-blocks/sensor.vhd
+build_compliant_test guards-and-blocks/example_entity.vhd
+build_compliant_test guards-and-blocks/circuit.vhd
+build_compliant_test guards-and-blocks/full.vhd
+build_compliant_test guards-and-blocks/inline_01.vhd
+build_compliant_test guards-and-blocks/inline_02.vhd
+build_compliant_test guards-and-blocks/inline_03.vhd
+build_compliant_test guards-and-blocks/inline_04.vhd
+build_compliant_test guards-and-blocks/inline_05.vhd
+build_compliant_test guards-and-blocks/tb_full.vhd
+build_compliant_test guards-and-blocks/inline_06.vhd
+build_compliant_test guards-and-blocks/tb_tri_state_reg.vhd
+build_compliant_test guards-and-blocks/tb_latch.vhd
+build_compliant_test guards-and-blocks/tb_sensor.vhd
+
+build_compliant_test misc-topics/count2-1.vhd
+build_compliant_test misc-topics/limit_checker.vhd
+build_compliant_test misc-topics/test_bench.vhd
+build_compliant_test misc-topics/processor.vhd
+build_compliant_test misc-topics/SR_flipflop.vhd
+build_compliant_test misc-topics/inline_01.vhd
+build_compliant_test misc-topics/inline_02.vhd
+build_compliant_test misc-topics/inline_04a.vhd
+build_compliant_test misc-topics/tb_count2.vhd
+build_compliant_test misc-topics/tb_limit_checker.vhd
+build_compliant_test misc-topics/tb_SR_flipflop.vhd
+
+build_compliant_test packages/cpu_types.vhd
+build_compliant_test packages/address_decoder.vhd
+build_compliant_test packages/clock_power_pkg.vhd
+build_compliant_test packages/io_controller-1.vhd
+build_compliant_test packages/bus_sequencer-1.vhd
+build_compliant_test packages/analog_output_interface.vhd
+build_compliant_test packages/cpu_types-1.vhd
+build_compliant_test packages/cpu.vhd
+build_compliant_test packages/bit_vector_signed_arithmetic.vhd
+build_compliant_test packages/cpu-1.vhd
+build_compliant_test packages/lessthan.vhd
+build_compliant_test packages/test_alu.vhd
+build_compliant_test packages/inline_01.vhd
+build_compliant_test packages/inline_02.vhd
+build_compliant_test packages/inline_03.vhd
+build_compliant_test packages/inline_04a.vhd
+build_compliant_test packages/inline_05.vhd
+build_compliant_test packages/inline_06.vhd
+build_compliant_test packages/inline_08.vhd
+build_compliant_test packages/inline_09.vhd
+build_compliant_test packages/tb_address_decoder.vhd
+build_compliant_test packages/tb_bit_vector_signed_arithmetic.vhd
+
+build_compliant_test resolution/resolve_tri_state_logic.vhd
+build_compliant_test resolution/MVL4.vhd
+build_compliant_test resolution/tri_state_buffer.vhd
+build_compliant_test resolution/misc_logic.vhd
+build_compliant_test resolution/words.vhd
+build_compliant_test resolution/computer_system.vhd
+build_compliant_test resolution/memory_system.vhd
+build_compliant_test resolution/resolved.vhd
+build_compliant_test resolution/bus_based_system.vhd
+build_compliant_test resolution/synchronize.vhd
+build_compliant_test resolution/synchronized_module.vhd
+build_compliant_test resolution/inline_01.vhd
+build_compliant_test resolution/inline_02.vhd
+build_compliant_test resolution/inline_03.vhd
+
+build_compliant_test scalar-data/ent.vhd
+build_compliant_test scalar-data/int_types.vhd
+build_compliant_test scalar-data/small_adder.vhd
+build_compliant_test scalar-data/inline_01a.vhd
+
+build_compliant_test sequential-statements/thermostat-1.vhd
+build_compliant_test sequential-statements/mux4.vhd
+build_compliant_test sequential-statements/counter.vhd
+build_compliant_test sequential-statements/counter-1.vhd
+build_compliant_test sequential-statements/cos.vhd
+build_compliant_test sequential-statements/SR_flipflop.vhd
+build_compliant_test sequential-statements/max3.vhd
+build_compliant_test sequential-statements/edge_triggered_register.vhd
+build_compliant_test sequential-statements/inline_01.vhd
+build_compliant_test sequential-statements/inline_02.vhd
+build_compliant_test sequential-statements/inline_03.vhd
+build_compliant_test sequential-statements/inline_04a.vhd
+build_compliant_test sequential-statements/inline_05.vhd
+build_compliant_test sequential-statements/inline_06.vhd
+build_compliant_test sequential-statements/inline_07.vhd
+build_compliant_test sequential-statements/inline_08.vhd
+build_compliant_test sequential-statements/inline_09.vhd
+build_compliant_test sequential-statements/inline_10a.vhd
+build_compliant_test sequential-statements/inline_11.vhd
+build_compliant_test sequential-statements/inline_12.vhd
+build_compliant_test sequential-statements/inline_13.vhd
+build_compliant_test sequential-statements/inline_14.vhd
+build_compliant_test sequential-statements/inline_15.vhd
+build_compliant_test sequential-statements/inline_16.vhd
+build_compliant_test sequential-statements/inline_17.vhd
+build_compliant_test sequential-statements/inline_18.vhd
+build_compliant_test sequential-statements/inline_19.vhd
+build_compliant_test sequential-statements/tb_mux4.vhd
+build_compliant_test sequential-statements/tb_counter.vhd
+build_compliant_test sequential-statements/tb_counter-1.vhd
+build_compliant_test sequential-statements/tb_cos.vhd
+build_compliant_test sequential-statements/tb_cos-1.vhd
+build_compliant_test sequential-statements/tb_SR_flipflop.vhd
+build_compliant_test sequential-statements/tb_max3.vhd
+build_compliant_test sequential-statements/tb_edge_triggered_register.vhd
+
+build_compliant_test subprograms/average_samples.vhd
+build_compliant_test subprograms/control_processor.vhd
+build_compliant_test subprograms/instruction_interpreter.vhd
+build_compliant_test subprograms/control_sequencer.vhd
+build_compliant_test subprograms/instruction_interpreter-1.vhd
+build_compliant_test subprograms/do_arith_op.vhd
+build_compliant_test subprograms/addu.vhd
+build_compliant_test subprograms/negate.vhd
+build_compliant_test subprograms/receiver.vhd
+build_compliant_test subprograms/signal_generator.vhd
+build_compliant_test subprograms/increment.vhd
+build_compliant_test subprograms/find_first_set.vhd
+build_compliant_test subprograms/bv_lt.vhd
+build_compliant_test subprograms/check_setup.vhd
+build_compliant_test subprograms/generate_clock.vhd
+build_compliant_test subprograms/limited.vhd
+build_compliant_test subprograms/bv_to_natural.vhd
+build_compliant_test subprograms/network_driver.vhd
+build_compliant_test subprograms/hold_time_checker.vhd
+build_compliant_test subprograms/v_source.vhd
+build_compliant_test subprograms/freq_detect.vhd
+build_compliant_test subprograms/mixer.vhd
+build_compliant_test subprograms/mixer_wa.vhd
+build_compliant_test subprograms/motor_system.vhd
+build_compliant_test subprograms/motor_system_wa.vhd
+build_compliant_test subprograms/reg_ctrl.vhd
+build_compliant_test subprograms/ent.vhd
+build_compliant_test subprograms/cache.vhd
+build_compliant_test subprograms/p1.vhd
+build_compliant_test subprograms/inline_01.vhd
+build_compliant_test subprograms/inline_02.vhd
+build_compliant_test subprograms/inline_03.vhd
+build_compliant_test subprograms/inline_04a.vhd
+build_compliant_test subprograms/inline_05a.vhd
+build_compliant_test subprograms/inline_06a.vhd
+build_compliant_test subprograms/inline_07.vhd
+build_compliant_test subprograms/inline_08.vhd
+build_compliant_test subprograms/tb_v_source.vhd
+build_compliant_test subprograms/tb_freq_detect.vhd
+build_compliant_test subprograms/tb_mixer.vhd
+build_compliant_test subprograms/tb_motor_system.vhd
+build_compliant_test subprograms/tb_reg_ctrl.vhd
+
+end_test_group
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd
new file mode 100644
index 0000000..71b19f5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+use work.automotive_valve_defs.all;
+
+entity automotive_valve is
+  port ( terminal p1, p2 : valve_fluidic;
+         terminal control : valve_translational );
+end entity automotive_valve;
+
+
+-- not in book
+
+architecture test of automotive_valve is
+begin
+end architecture test;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd
new file mode 100644
index 0000000..bf41f48
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve_defs.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.fluidic_systems.all, ieee_proposed.mechanical_systems.all;
+
+package automotive_valve_defs is
+  
+  subnature valve_fluidic is fluidic
+    tolerance "valve_pressure" across "valve_vflow_rate" through;
+
+  subnature valve_translational is translational
+    tolerance "valve_displacement" across "valve_force" through;
+
+  -- ...  -- other useful declarations
+  
+  component automotive_valve is
+    port ( terminal p1, p2 : valve_fluidic;
+           terminal control : valve_translational );
+  end component automotive_valve;
+
+end package automotive_valve_defs;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd
new file mode 100644
index 0000000..0d7a4ad
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/brake_system.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+use work.automotive_valve_defs.all;
+
+entity brake_system is
+end entity brake_system;
+
+-- end not in book
+
+
+
+architecture structure of brake_system is
+
+  use work.automotive_valve_defs.all;
+
+  -- ...  -- declarations of other components, terminals, etc
+
+  -- not in book
+  terminal master_reservoir, brake_line : valve_fluidic;
+  terminal brake_pedal : valve_translational;
+  -- end not in book
+
+begin
+  
+  pedal_valve : component automotive_valve
+    port map ( p1 => master_reservoir,
+               p2 => brake_line,
+               control => brake_pedal );
+    
+  -- ...  -- other component instances
+      
+end architecture structure;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd
new file mode 100644
index 0000000..d0ee652
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_structure.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+configuration computer_structure of computer_system is
+
+  for structure
+
+    for interface_decoder : decoder_2_to_4
+      use entity work.decoder_3_to_8(basic)
+      generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
+      port map ( s0 => in0, s1 => in1, s2 => '0',
+                 enable => '1',
+                 y0 => out0, y1 => out1, y2 => out2, y3 => out3,
+                 y4 => open, y5 => open, y6 => open, y7 => open );
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration computer_structure;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd
new file mode 100644
index 0000000..df8a7b6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/computer_system.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+
+library util;  use util.stimulus_generators.all;
+
+-- end not in book
+
+
+architecture structure of computer_system is
+
+  component decoder_2_to_4 is
+    generic ( prop_delay : delay_length );
+    port ( in0, in1 : in bit;
+           out0, out1, out2, out3 : out bit );
+  end component decoder_2_to_4;
+
+  -- . . .
+
+  -- not in book
+
+  signal addr : bit_vector(5 downto 4);
+  signal interface_a_select, interface_b_select,
+         interface_c_select, interface_d_select : bit;
+  -- end not in book
+
+begin
+
+  interface_decoder : component decoder_2_to_4
+    generic map ( prop_delay => 4 ns )
+    port map ( in0 => addr(4), in1 => addr(5),
+               out0 => interface_a_select, out1 => interface_b_select,
+               out2 => interface_c_select, out3 => interface_d_select );
+
+  -- . . .
+
+  -- not in book
+
+  all_possible_values(addr, 10 ns);
+
+  -- end not in book
+
+end architecture structure;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd
new file mode 100644
index 0000000..3729acb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/control_section.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity control_section is
+end entity control_section;
+
+-- end not in book
+
+
+architecture structural of control_section is
+
+  component reg is
+    generic ( width : positive );
+    port ( clk : in std_logic;
+           d : in std_logic_vector(0 to width - 1);
+           q : out std_logic_vector(0 to width - 1) );
+  end component reg;
+
+  for flag_reg : reg
+    use entity work.reg(gate_level)
+    port map ( clock => clk, data_in => d, data_out => q );
+
+  -- . . .
+
+  -- not in book
+  signal clock_phase1, zero_result, neg_result, overflow_result,
+         zero_flag, neg_flag, overflow_flag : std_logic;
+  -- end not in book
+
+begin
+
+  flag_reg : component reg
+    generic map ( width => 3 )
+    port map ( clk => clock_phase1,
+               d(0) => zero_result, d(1) => neg_result,
+               d(2) => overflow_result,
+               q(0) => zero_flag, q(1) => neg_flag,
+               q(2) => overflow_flag );
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    clock_phase1 <= '0';
+    zero_result <= '0'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
+    clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    zero_result <= '0'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
+    clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    zero_result <= '0'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
+    clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    zero_result <= '0'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
+    clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    zero_result <= '1'; neg_result <= '0'; overflow_result <= '0'; wait for 10 ns;
+    clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    zero_result <= '1'; neg_result <= '0'; overflow_result <= '1'; wait for 10 ns;
+    clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    zero_result <= '1'; neg_result <= '1'; overflow_result <= '0'; wait for 10 ns;
+    clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    zero_result <= '1'; neg_result <= '1'; overflow_result <= '1'; wait for 10 ns;
+    clock_phase1 <= '1', '0' after 5 ns;  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd
new file mode 100644
index 0000000..d7b8ac4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+configuration controller_with_timing of control_section is
+
+  for structural
+
+    for flag_reg : reg
+      generic map ( t_setup => 200 ps, t_hold => 150 ps,
+                    t_pd => 150 ps, width => width )
+      port map ( reset_n => '1' );
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration controller_with_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd
new file mode 100644
index 0000000..eba7230
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/decoder_3_to_8.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity decoder_3_to_8 is
+  generic ( Tpd_01, Tpd_10 : delay_length );
+  port ( s0, s1, s2 : in bit;
+         enable : in bit;
+         y0, y1, y2, y3, y4, y5, y6, y7 : out bit );
+end entity decoder_3_to_8;
+
+
+-- not in book
+
+architecture basic of decoder_3_to_8 is
+begin
+
+  process (enable, s2, s1, s0) is
+  begin
+    if enable = '0' then
+      (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000000");
+    else
+      case bit_vector'(s2, s1, s0) is
+        when "000" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000001");
+        when "001" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000010");
+        when "010" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000100");
+        when "011" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00001000");
+        when "100" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00010000");
+        when "101" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00100000");
+        when "110" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("01000000");
+        when "111" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("10000000");
+      end case;
+    end if;
+  end process;
+
+end architecture basic;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd
new file mode 100644
index 0000000..2c4163b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/fm_radio.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity fm_radio is
+end entity fm_radio;
+
+-- end not in book
+
+
+
+architecture top_level of fm_radio is
+
+  terminal left_decoded, left_filtered : electrical;
+  terminal right_decoded, right_filtered : electrical;
+  -- ...
+
+begin
+
+  left_pilot_filter : configuration work.notch_filter_down_to_device_level
+    port map ( input => left_decoded, output => left_filtered,
+               vdd => vdd, vss => vss, gnd => gnd );
+
+  -- ...
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/index-ams.txt
new file mode 100644
index 0000000..58e31b1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/index-ams.txt
@@ -0,0 +1,47 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                    Chapter 16 - Components and Configurations
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+opamp.vhd                                       entity bulk_cmos_nfet                   basic, detailed                 --
+--                                              entity opamp                            struct                          Figure 16-1
+automotive_valve_defs.vhd                       package automotive_valve_defs           --                              Figure 16-2
+automotive_valve.vhd                            entity automotive_valve                 test                            Figure 16-3
+brake_system.vhd                                entity brake_system                     structure                       Figure 16-4
+opamp_mosfets.vhd                               configuration opamp_mosfets             --                              Figure 16-5
+notch_filter.vhd                                entity notch_filter                     opamp_based                     Figure 16-6
+notch_filter_down_to_device_level.vhd           configuration notch_filter_down_to_device_level  --                     Figure 16-7
+notch_filter_full.vhd                           configuration full                      --                              Figure 16-8
+fm_radio.vhd                                    entity fm_radio                         top_level                       Figure 16-9
+successive_approx_adc.vhd                       entity successive_approx_adc            struct                          Figure 16-10
+sensor_interface.vhd                            entity sensor_interface                 structural                      Figure 16-11
+sensor_interface_with_timing.vhd                configuration sensor_interface_with_timing  --                          Figure 16-12
+computer_system.vhd                             entity computer_system                  structure                       Figure 16-13
+decoder_3_to_8.vhd                              entity decoder_3_to_8                   basic                           Figure 16-14
+computer_structure.vhd                          configuration computer_structure        --                              Figure 16-15
+single_board_computer.vhd                       entity single_board_computer            structural                      Figure 16-17
+intermediate.vhd                                entity XYZ3000_cpu                      full_function                   --
+--                                              entity memory_array                     behavioral                      --
+--                                              configuration intermediate              --                              Figure 16-18
+logic_block.vhd                                 entity nand3                            behavioral                      --
+--                                              entity logic_block                      ideal                           Figure 16-19
+reg-1.vhd                                       entity reg                              gate_level                      Figure 16-21
+control_section.vhd                             entity control_section                  structural                      Figure 16-20
+controller_with_timing-1.vhd                    configuration controller_with_timing    --                              Figure 16-22
+interlock_control.vhd                           entity not_gate                         primitive                       --
+--                                              entity interlock_control                detailed_timing                 Figure 16-23
+interlock_control_with_estimates.vhd            configuration interlock_control_with_estimates  --                      Figure 16-24
+--                                              configuration interlock_control_with_actual  --                         Figure 16-24
+misc_logic.vhd                                  entity misc_logic                       gate_level                      Figure 16-25
+misc_logic_reconfigured.vhd                     configuration misc_logic_reconfigured   --                              Figure 16-26
+inline_02a.vhd                                  configuration inline_02a                --                              Section 16.2
+inline_04a.vhd                                  entity inline_04a                       test                            --
+--                                              configuration inline_04a_test           --                              Section 16.2
+inline_05.vhd                                   entity inline_05                        test                            Section 16.2
+--                                              entity nand2                            --                              Section 16.2
+--                                              configuration inline_05_test            --                              Section 16.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd
new file mode 100644
index 0000000..41f40cb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_02a.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+configuration inline_02a of opamp is
+
+  for struct
+
+    -- code from book (in text)
+
+    for m1, m2 : nfet
+      use entity work.bulk_cmos_nfet(basic);
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration inline_02a;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd
new file mode 100644
index 0000000..9447cb3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_04a.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity inline_04a is
+end entity inline_04a;
+
+
+architecture test of inline_04a is
+
+  component opamp is
+    port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
+  end component opamp;
+
+  terminal plus_in, minus_in, output, vdd, vss, gnd : electrical;
+
+begin
+
+  voltage_amp : component opamp
+    port map ( plus_in => plus_in, minus_in => minus_in, output => output,
+               vdd => vdd, vss => vss, gnd => gnd );
+
+end architecture test;
+
+
+configuration inline_04a_test of inline_04a is
+
+  for test
+
+    -- code from book (in text)
+
+    for voltage_amp : opamp
+      use configuration work.opamp_mosfets;
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration inline_04a_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd
new file mode 100644
index 0000000..ec39f8d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/inline_05.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05 is
+end entity inline_05;
+
+
+architecture test of inline_05 is
+
+  -- code from book
+
+  component nand3 is
+    port ( a, b, c : in bit := '1';  y : out bit );
+  end component nand3;
+
+  -- end code from book
+
+  signal s1, s2, s3 : bit;
+
+begin
+
+  -- code from book
+
+  gate1 : component nand3
+    port map ( a => s1, b => s2, c => open, y => s3 );
+
+  -- end code from book
+
+end architecture test;
+
+
+
+-- code from book
+
+entity nand2 is
+  port ( a, b : in bit := '1';  y : out bit );
+end entity nand2;
+
+-- end code from book
+
+
+
+
+configuration inline_05_test of inline_05 is
+
+  for test
+
+    -- code from book
+
+    for gate1 : nand3
+      use entity work.nand2(basic);
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration inline_05_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd
new file mode 100644
index 0000000..fe566b0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control.vhd
@@ -0,0 +1,113 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity nor_gate is
+  generic ( width : positive;
+            Tpd01, Tpd10 : delay_length );
+  port ( input : in std_logic_vector(0 to width - 1);
+         output : out std_logic );
+end entity nor_gate;
+
+
+architecture primitive of nor_gate is
+
+  function max ( a, b : delay_length ) return delay_length is
+  begin
+    if a > b then
+      return a;
+    else
+      return b;
+    end if;
+  end function max;
+
+begin
+
+  reducer : process (input) is
+    variable result : std_logic;
+  begin
+    result := '0';
+    for index in input'range loop
+      result := result or input(index);
+    end loop;
+    if not result = '1' then
+      output <= not result after Tpd01;
+    elsif not result = '0' then
+      output <= not result after Tpd10;
+    else
+      output <= not result after max(Tpd01, Tpd10);
+    end if;
+  end process reducer;
+
+end architecture primitive;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+library cell_lib;
+
+entity interlock_control is
+end entity interlock_control;
+
+
+-- code from book
+
+architecture detailed_timing of interlock_control is
+
+  component nor_gate is
+    generic ( input_width : positive );
+    port ( input : in std_logic_vector(0 to input_width - 1);
+           output : out std_logic );
+  end component nor_gate;
+
+  for ex_interlock_gate : nor_gate
+    use entity cell_lib.nor_gate(primitive)
+    generic map ( width => input_width,
+                  Tpd01 => 250 ps, Tpd10 => 200 ps );  -- estimates
+
+  -- . . .
+
+  -- not in book
+  signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
+  -- end not in book
+
+begin
+
+  ex_interlock_gate : component nor_gate
+    generic map ( input_width => 2 )
+    port map ( input(0) => reg_access_hazard,
+               input(1) => load_hazard,
+               output => stall_ex_n);
+
+  -- . . .
+
+  -- not in book
+
+  reg_access_hazard <= '0' after 10 ns, '1' after 20 ns, 'X' after 30 ns;
+
+  load_hazard <= '0' after 2 ns, '1' after 4 ns, 'X' after 6 ns,
+                 '0' after 12 ns, '1' after 14 ns, 'X' after 16 ns,
+                 '0' after 22 ns, '1' after 24 ns, 'X' after 26 ns,
+                 '0' after 32 ns, '1' after 34 ns, 'X' after 36 ns;
+
+  -- end not in book
+
+end architecture detailed_timing;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd
new file mode 100644
index 0000000..f6d4a51
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+configuration interlock_control_with_estimates of interlock_control is
+
+  for detailed_timing
+
+  end for;
+
+  -- . . .
+
+end configuration interlock_control_with_estimates;
+
+--------------------------------------------------
+
+configuration interlock_control_with_actual of interlock_control is
+
+  for detailed_timing
+
+    for ex_interlock_gate : nor_gate
+      generic map ( Tpd01 => 320 ps, Tpd10 => 230 ps );
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration interlock_control_with_actual;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd
new file mode 100644
index 0000000..53342b4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/intermediate.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- analyze into resource library chips
+
+entity XYZ3000_cpu is
+  port ( clock : in bit;  addr_data : inout bit_vector(31 downto 0);
+         other_port : in bit := '0' );
+end entity XYZ3000_cpu;
+
+
+architecture full_function of XYZ3000_cpu is
+begin
+end architecture full_function;
+
+
+-- analyze into work library
+
+entity memory_array is
+  port ( addr : in bit_vector(25 downto 0);  other_port : in bit := '0' );
+end entity memory_array;
+
+
+architecture behavioral of memory_array is
+begin
+end architecture behavioral;
+
+
+
+-- code from book
+
+library chips;
+
+configuration intermediate of single_board_computer is
+
+  for structural
+
+    for cpu : processor
+      use entity chips.XYZ3000_cpu(full_function)
+      port map ( clock => clk, addr_data => a_d, -- . . . );
+      -- not in book
+                 other_port => open );
+      -- end not in book
+    end for;
+
+    for main_memory : memory
+      use entity work.memory_array(behavioral);
+    end for;
+
+    for all : serial_interface
+      use open;
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration intermediate;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd
new file mode 100644
index 0000000..a1d95b8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/logic_block.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book (in text)
+
+entity nand3 is
+  port ( a, b, c : in bit;  y : out bit );
+end entity nand3;
+
+-- end code from book
+
+architecture behavioral of nand3 is
+begin
+  y <= not (a and b and c);
+end architecture behavioral;
+
+
+
+entity logic_block is
+end entity logic_block;
+
+
+-- code from book
+
+library gate_lib;
+
+architecture ideal of logic_block is
+
+  component nand2 is
+    port ( in1, in2 : in bit;  result : out bit );
+  end component nand2;
+
+  for all : nand2
+    use entity gate_lib.nand3(behavioral)
+    port map ( a => in1, b => in2, c => '1', y => result );
+
+  -- . . .    -- other declarations
+
+  -- not in book
+  signal s1, s2, s3 : bit := '0';
+
+begin
+
+  gate1 : component nand2
+    port map ( in1 => s1, in2 => s2, result => s3 );
+
+  -- . . .    -- other concurrent statements
+
+  -- not in book
+
+  s1 <= '1' after 20 ns;
+
+  s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
+
+  -- end not in book
+
+end architecture ideal;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd
new file mode 100644
index 0000000..da51c58
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library project_lib;
+library util;  use util.stimulus_generators.all;
+
+entity misc_logic is
+end entity misc_logic;
+
+
+-- code from book
+
+architecture gate_level of misc_logic is
+
+  component nand3 is
+    generic ( Tpd : delay_length );
+    port ( a, b, c : in bit;  y : out bit );
+  end component nand3;
+
+  for all : nand3
+    use entity project_lib.nand3(basic);
+
+  -- . . .
+
+  -- not in book
+  signal sig1, sig2, sig3, out_sig : bit;
+  signal test_vector : bit_vector(1 to 3);
+  -- end not in book
+
+begin
+
+  gate1 : component nand3
+    generic map ( Tpd => 2 ns )
+    port map ( a => sig1, b => sig2, c => sig3, y => out_sig );
+
+  -- . . .
+
+  -- not in book
+
+  all_possible_values(test_vector, 10 ns);
+
+  (sig1, sig2, sig3) <= test_vector;
+
+  -- end not in book
+
+end architecture gate_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd
new file mode 100644
index 0000000..7a4a735
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/misc_logic_reconfigured.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+configuration misc_logic_reconfigured of misc_logic is
+
+  for gate_level
+
+    for gate1 : nand3
+      generic map ( Tpd => 1.6 ns )
+      port map ( a => c, c => a, b => b, y => y );
+    end for;
+
+  end for;
+
+end configuration misc_logic_reconfigured;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd
new file mode 100644
index 0000000..00842f4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity notch_filter is
+  port ( terminal input, output, vdd, vss, gnd : electrical );
+end entity notch_filter;
+
+----------------------------------------------------------------
+
+architecture opamp_based of notch_filter is
+  
+  component simple_opamp is
+    port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
+  end component simple_opamp;
+  -- ...
+  
+  terminal opamp1_in, opamp1_out, opamp2_in, -- ...
+    -- not in book
+    other_terminal
+    -- end not in book
+    : electrical;
+
+begin
+  
+  opamp1 : component simple_opamp
+    port map ( plus_in => gnd, minus_in => opamp1_in, output => opamp1_out,
+               vdd => vdd, vss => vss, gnd => gnd );
+
+    opamp2 : component simple_opamp
+      port map ( plus_in => gnd, minus_in => opamp2_in, output => output,
+                 vdd => vdd, vss => vss, gnd => gnd );
+
+  -- other component instances
+  -- ...
+  
+end architecture opamp_based;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd
new file mode 100644
index 0000000..0d30980
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_down_to_device_level.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+configuration notch_filter_down_to_device_level of notch_filter is
+  
+  for opamp_based
+  
+    for all : simple_opamp
+      use configuration work.opamp_mosfets;
+    end for;
+
+    -- ...  -- bindings for other component instances
+  
+  end for;  -- end of architecture opamp_based
+
+end configuration notch_filter_down_to_device_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd
new file mode 100644
index 0000000..93eee76
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/notch_filter_full.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library cmos_lib;  use cmos_lib.bulk_cmos_nfet;
+
+configuration full of notch_filter is
+  
+  for opamp_based  -- architecture of notch_filter
+  
+    for all : simple_opamp
+      use entity work.opamp(struct);
+
+      for struct  -- architecture of opamp
+  
+        for m1, m2 : nfet
+          use entity bulk_cmos_nfet(detailed);
+        end for;
+
+        for others : nfet
+          use entity bulk_cmos_nfet(basic);
+        end for;
+
+        -- ...
+  
+      end for;  -- end of architecture struct
+
+    end for;
+
+    -- ...  -- bindings for other component instances
+  
+  end for;  -- end of architecture opamp_based
+
+end configuration full;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd
new file mode 100644
index 0000000..f680592
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity bulk_cmos_nfet is
+  generic ( Vt : real;
+            transconductance : real );
+  port ( terminal gate, drain, source : electrical );
+end entity bulk_cmos_nfet;
+
+
+architecture basic of bulk_cmos_nfet is
+begin
+end architecture basic;
+
+
+architecture detailed of bulk_cmos_nfet is
+begin
+end architecture detailed;
+
+
+-- code from book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity opamp is
+  port ( terminal plus_in, minus_in, output, vdd, vss, gnd : electrical );
+end entity opamp;
+
+----------------------------------------------------------------
+
+architecture struct of opamp is
+
+  component nfet is
+    generic ( Vt : real;
+              transconductance : real );
+    port ( terminal gate, drain, source : electrical );
+  end component nfet;
+
+  terminal int_1, int_2, int_3, -- ...
+    -- not in book
+    other_terminal
+    -- end not in book
+    : electrical;
+
+begin
+
+  m1 : component nfet
+    generic map ( Vt => 0.026, transconductance => 1.0 )
+    port map ( gate => plus_in, drain => int_1, source => int_2 );
+
+  m2 : component nfet
+    generic map ( Vt => 0.026, transconductance => 1.0 )
+    port map ( gate => minus_in, drain => int_1, source => int_3 );
+
+  -- other component instances
+  -- ...
+
+end architecture struct;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd
new file mode 100644
index 0000000..42f2382
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/opamp_mosfets.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library cmos_lib;
+use cmos_lib.bulk_cmos_nfet;
+
+configuration opamp_mosfets of opamp is
+
+  for struct -- architecture of opamp
+
+    for m1, m2 : nfet
+      use entity bulk_cmos_nfet(detailed);
+    end for;
+
+    for others : nfet
+      use entity bulk_cmos_nfet(basic);
+    end for;
+
+    -- ...
+
+  end for; -- end of architecture struct
+
+end configuration opamp_mosfets;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd
new file mode 100644
index 0000000..445b888
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/reg-1.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity reg is
+  generic ( t_setup, t_hold, t_pd : delay_length;
+            width : positive );
+  port ( clock : in std_logic;
+         reset_n : in std_logic := 'H';
+         data_in : in std_logic_vector(0 to width - 1);
+         data_out : out std_logic_vector(0 to width - 1) );
+end entity reg;
+
+
+
+-- not in book
+
+architecture gate_level of reg is
+
+begin
+
+  store : process (clock, reset_n) is
+  begin
+    if reset_n = '0' or reset_n = 'L' then
+      data_out <= (others => '0') after t_pd;
+    elsif rising_edge(clock) then
+      data_out <= data_in after t_pd;
+    end if;
+  end process store;
+
+end architecture gate_level;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd
new file mode 100644
index 0000000..d676652
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity sensor_interface is
+
+end entity sensor_interface;
+
+-- end not in book
+
+
+
+architecture structural of sensor_interface is
+  
+  component adc is
+    generic ( width : positive );
+    port ( terminal analog_in : electrical;
+           signal clock : in std_logic;
+           signal start : in std_logic;
+           signal eoc : out std_logic;
+           signal data_out : out std_logic_vector(0 to width - 1) );
+  end component adc;
+
+  -- ...
+
+  -- not in book
+  terminal sensor_input : electrical;
+  signal clk, start_conversion, end_conversion : std_logic;
+  signal sensor_data : std_logic_vector(0 to 7);
+  -- end not in book
+  
+begin
+  
+  sensor_adc : component adc
+    generic map ( width => sensor_data'length )
+    port map ( analog_in => sensor_input,
+               clock => clk,
+               start => start_conversion,
+               eoc => end_conversion,
+               data_out => sensor_data );
+
+  -- ...
+  
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd
new file mode 100644
index 0000000..c7a03a3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/sensor_interface_with_timing.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+configuration sensor_interface_with_timing of sensor_interface is
+
+  for structural
+
+    for sensor_adc : adc
+      use entity work.successive_approx_adc(struct)
+        generic map ( t_setup => 200 ps, t_hold => 150 ps, t_pd => 150 ps,
+                      width => width );
+    end for;
+
+    -- ...
+
+  end for;
+
+end configuration sensor_interface_with_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd
new file mode 100644
index 0000000..10be488
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/single_board_computer.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+entity single_board_computer is
+end entity single_board_computer;
+-- end not in book
+
+
+architecture structural of single_board_computer is
+
+  -- . . .    -- type and signal declarations
+
+  -- not in book
+
+  subtype word is bit_vector(31 downto 0);
+  signal sys_clk : bit;
+  signal cpu_a_d, latched_addr : word;
+
+  -- end not in book
+
+  component processor is
+    port ( clk : in bit;  a_d : inout word; -- . . . );
+    -- not in book
+           other_port : in bit := '0' );
+    -- end not in book
+  end component processor;
+
+  component memory is
+    port ( addr : in bit_vector(25 downto 0); -- . . . );
+    -- not in book
+           other_port : in bit := '0' );
+    -- end not in book
+  end component memory;
+
+  component serial_interface is
+    port ( clk : in bit;  address : in bit_vector(3 downto 0); -- . . . );
+    -- not in book
+           other_port : in bit := '0' );
+    -- end not in book
+  end component serial_interface;
+
+begin
+
+  cpu : component processor
+    port map ( clk => sys_clk, a_d => cpu_a_d, -- . . . );
+    -- not in book
+               other_port => open );
+    -- end not in book
+
+  main_memory : component memory
+    port map ( addr => latched_addr(25 downto 0), -- . . . );
+    -- not in book
+               other_port => open );
+    -- end not in book
+
+  serial_interface_a : component serial_interface
+    port map ( clk => sys_clk, address => latched_addr(3 downto 0), -- . . . );
+    -- not in book
+               other_port => open );
+    -- end not in book
+
+  -- . . .
+
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd
new file mode 100644
index 0000000..18de792
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/successive_approx_adc.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity successive_approx_adc is
+  generic ( t_setup, t_hold, t_pd : delay_length;
+            width : positive );
+  port ( terminal analog_in : electrical;
+         signal clock : in std_logic;
+         signal start : in std_logic;
+         signal eoc : out std_logic;
+         signal data_out : out std_logic_vector(0 to width - 1) );
+end entity successive_approx_adc;
+
+
+-- not in book
+
+architecture struct of successive_approx_adc is
+
+begin
+
+end architecture struct;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd
new file mode 100644
index 0000000..5982329
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/and_multiple.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity and_multiple is
+  port ( i : in bit_vector;  y : out bit );
+end entity and_multiple;
+
+--------------------------------------------------
+
+architecture behavioral of and_multiple is
+begin
+
+  and_reducer : process ( i ) is
+    variable result : bit;
+  begin
+    result := '1';
+    for index in i'range loop
+      result := result and i(index);
+    end loop;
+    y <= result;
+  end process and_reducer;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd
new file mode 100644
index 0000000..105f11f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/byte_swap.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book:
+
+package byte_swap_types is
+
+  subtype halfword is bit_vector(0 to 15);
+
+end package byte_swap_types;
+
+
+use work.byte_swap_types.all;
+
+-- end not in book:
+
+
+entity byte_swap is
+  port (input : in halfword;  output : out halfword);
+end entity byte_swap;
+
+--------------------------------------------------
+
+architecture behavior of byte_swap is
+
+begin
+
+  swap : process (input)
+  begin
+    output(8 to 15) <= input(0 to 7);
+    output(0 to 7) <= input(8 to 15);
+  end process swap;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd
new file mode 100644
index 0000000..8650058
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/coeff_ram.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book:
+
+package coeff_ram_types is
+
+  subtype coeff_ram_address is integer range 0 to 63;
+
+end package coeff_ram_types;
+
+
+
+use work.coeff_ram_types.all;
+
+-- end not in book
+
+
+entity coeff_ram is
+  port ( rd, wr : in bit;  addr : in coeff_ram_address;
+         d_in : in real;  d_out : out real );
+end entity coeff_ram;
+
+--------------------------------------------------
+
+architecture abstract of coeff_ram is
+begin
+
+  memory : process is
+    type coeff_array is array (coeff_ram_address) of real;
+    variable coeff : coeff_array;
+  begin
+    for index in coeff_ram_address loop
+      coeff(index) := 0.0;
+    end loop;
+    loop
+      wait on rd, wr, addr, d_in; 
+      if rd = '1' then
+        d_out <= coeff(addr);
+      end if;
+      if wr = '1' then
+        coeff(addr) := d_in;
+      end if;
+    end loop;
+  end process memory;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd
new file mode 100644
index 0000000..2fd0f47
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book:
+
+entity computer is
+
+end entity computer;
+
+-- end not in book
+
+
+architecture system_level of computer is
+
+  type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, -- . . .);
+  -- not in book:
+                                                                  nop);
+  -- end not in book
+  type reg_number is range 0 to 31;
+  constant r0 : reg_number := 0;  constant r1 : reg_number := 1;  -- . . .
+  -- not in book:
+  constant r2 : reg_number := 2;
+  -- end not in book
+
+  type instruction is record
+      opcode : opcodes;
+      source_reg1, source_reg2, dest_reg : reg_number;
+      displacement : integer;
+    end record instruction;
+
+  type word is record
+      instr : instruction;
+      data : bit_vector(31 downto 0);
+    end record word;
+
+  signal address : natural;
+  signal read_word, write_word : word;
+  signal mem_read, mem_write : bit := '0';
+  signal mem_ready : bit := '0';
+
+begin
+
+  cpu : process is
+    variable instr_reg : instruction;
+    variable PC : natural;
+    -- . . .    -- other declarations for register file, etc.
+  begin
+    address <= PC;
+    mem_read <= '1';
+    wait until mem_ready = '1';
+    instr_reg := read_word.instr;
+    mem_read <= '0';
+    -- not in book:
+    wait until mem_ready = '0';
+    -- end not in book
+    PC := PC + 4;
+    case instr_reg.opcode is  -- execute the instruction
+      -- . . .
+      -- not in book:
+      when others => null;
+      -- end not in book
+    end case;
+  end process cpu;
+
+  memory : process is
+    subtype address_range is natural range 0 to 2**14 - 1;
+    type memory_array is array (address_range) of word;
+    variable store : memory_array :=
+      (  0  => ( ( ld, r0, r0, r2, 40 ), X"00000000" ),
+        1  => ( ( breq, r2, r0, r0, 5 ), X"00000000" ),
+        -- . . .
+        40  => ( ( nop, r0, r0, r0, 0 ), X"FFFFFFFE"),
+        others => ( ( nop, r0, r0, r0, 0 ), X"00000000") );
+  begin
+    -- . . .
+    -- not in book:
+    wait until mem_read = '1';
+    read_word <= store(address);
+    mem_ready <= '1';
+    wait until mem_read = '0';
+    mem_ready <= '0';
+    -- end not in book
+  end process memory;
+
+end architecture system_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/index-ams.txt
new file mode 100644
index 0000000..9bcec81
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/index-ams.txt
@@ -0,0 +1,39 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                         Chapter 4 - Composite Data Types
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+coeff_ram.vhd                                   package coeff_ram_types                 --                              Section 4.1
+--                                              entity coeff_ram                        abstract                        Figure 4-1
+transmission_lines.vhd                          package transmission_lines_types        --                              Section 4.1
+--                                              entity transmission_lines               abstract                        Figure 4-2
+modem_controller.vhd                            entity modem_controller                 test                            Figure 4-4
+and_multiple.vhd                                entity and_multiple                     behavioral                      Figure 4-5
+tb_and_multiple.vhd                             tb_and_multiple                         test_behavioral                 Section 4.2
+byte_swap.vhd                                   package byte_swap_types                 --                              Section 4.3
+--                                              entity byte_swap                        behavior                        Figure 4-6
+computer.vhd                                    entity computer                         system_level                    Figure 4-7
+inline_01.vhd                                   entity inline_01                        test                            Section 4.1
+inline_02a.vhd                                  entity inline_02a                       test                            Section 4.1
+inline_03.vhd                                   entity inline_03                        test                            Section 4.1
+inline_04a.vhd                                  entity inline_04a                       test                            Section 4.1
+inline_05.vhd                                   entity inline_05                        test                            Section 4.1
+inline_06a.vhd                                  entity inline_06a                       test                            Section 4.1
+inline_07a.vhd                                  entity inline_07a                       test                            Section 4.1
+inline_08.vhd                                   entity inline_08                        test                            Section 4.2
+inline_09a.vhd                                  entity inline_09a                       test                            Section 4.2
+inline_10.vhd                                   entity inline_10                        test                            Section 4.2
+inline_11a.vhd                                  entity inline_11a                       test                            Section 4.2
+inline_12.vhd                                   entity inline_12                        test                            Section 4.3
+inline_13.vhd                                   entity inline_13                        test                            Section 4.3
+inline_14a.vhd                                  entity inline_14a                       test                            Section 4.3
+inline_15.vhd                                   entity inline_15                        test                            Section 4.3
+inline_16.vhd                                   entity inline_16                        test                            Section 4.4
+inline_17a.vhd                                  entity inline_17a                       test                            Section 4.4
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_coeff_ram.vhd                                entity tb_coeff_ram                     test_abstract                   coeff_ram.vhd
+tb_byte_swap.vhd                                entity tb_byte_swap                     test_behavior                   byte_swap.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd
new file mode 100644
index 0000000..4997a79
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_01.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+  block_1_a : block is
+
+    -- code from book:
+
+    type word is array (0 to 31) of bit;
+
+    --
+
+    type controller_state is (initial, idle, active, error);
+
+    type state_counts is array (idle to error) of natural;
+
+    -- end of code from book
+
+  begin
+  end block block_1_a;
+
+
+  process_1_a : process is
+
+    -- code from book:
+
+    type word is array (31 downto 0) of bit;
+
+    --
+
+    type controller_state is (initial, idle, active, error);
+
+    --
+
+    type state_counts is
+      array (controller_state range idle to error) of natural;
+
+    --
+
+    subtype coeff_ram_address is integer range 0 to 63;
+    type coeff_array is array (coeff_ram_address) of real;
+
+    --
+
+    variable buffer_register, data_register : word;
+    variable counters : state_counts;
+    variable coeff : coeff_array;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    coeff(0) := 0.0;
+
+    counters(active) := counters(active) + 1;
+
+    data_register := buffer_register;
+
+    -- end of code from book
+
+    wait;
+  end process process_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd
new file mode 100644
index 0000000..cac5cfb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_02a.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+use ieee_proposed.fluidic_systems.all;
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02a is
+begin
+
+
+  block_1_a : block is
+
+    -- code from book:
+
+    nature electrical_bus is array (0 to 31) of electrical;
+
+    -- end of code from book
+
+  begin
+  end block block_1_a;
+
+
+  block_1_b : block is
+
+    -- code from book:
+
+    nature electrical_bus is array (31 downto 0) of electrical;
+
+    -- end of code from book
+
+  begin
+  end block block_1_b;
+
+
+  block_1_c : block is
+
+    -- code from book:
+
+    type engine_nodes is (intake, compressor, combustion, exhaust);
+
+    --
+
+    nature engine_flows is array (intake to exhaust) of fluidic;
+    
+    --
+
+    subtype bus_lines is integer range 0 to 31;
+    nature electrical_bus is array (bus_lines) of electrical;
+
+    --
+
+    subtype pressure is real tolerance "default_pressure";
+    subtype pipes is integer range 0 to 15;
+
+    --
+
+    type gas_pressures is array (pipes) of pressure;
+
+    --
+
+    terminal system_bus : electrical_bus;
+    terminal ferrari_engine, chevy_engine : engine_flows;
+
+    --
+
+    quantity bus_voltages across bus_currents through
+	     system_bus to electrical_ref;
+
+    -- end of code from book
+
+  begin
+  end block block_1_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd
new file mode 100644
index 0000000..5414554
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_03.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+begin
+
+
+  process_1_b : process is
+
+    -- code from book:
+
+    type symbol is ('a', 't', 'd', 'h', digit, cr, error);
+    type state is range 0 to 6;
+
+    type transition_matrix is array (state, symbol) of state;
+
+    variable transition_table : transition_matrix;
+
+    -- end of code from book
+	
+    variable next_state : state;
+
+    -- code from book:
+
+    type point is array (1 to 3) of real;
+    type matrix is array (1 to 3, 1 to 3) of real;
+
+    variable p, q : point;
+    variable transform : matrix;
+
+    -- end of code from book
+
+  begin
+
+    next_state := 
+    -- code from book:
+
+    transition_table(5, 'd');
+
+
+    -- end of code from book
+
+    for i in 1 to 3 loop
+      for j in 1 to 3 loop
+        if i = j then
+          transform(i, j) := -1.0;
+        else
+          transform(i, j) := 0.0;
+        end if;
+      end loop;
+    end loop;
+    p := (1.0, 2.0, 3.0);
+
+    -- code from book:
+
+    for i in 1 to 3 loop
+      q(i) := 0.0;
+      for j in 1 to 3 loop
+        q(i) := q(i) + transform(i, j) * p(j);
+      end loop;
+    end loop;
+    -- end of code from book
+
+    wait;
+  end process process_1_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd
new file mode 100644
index 0000000..6b44e1d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_04a.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.mechanical_systems.all;
+use ieee_proposed.fluidic_systems.all;
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04a is
+
+  -- code from book:
+        
+  type engine_nodes is (intake, compressor, combustion, exhaust);
+  type engines is range 1 to 4;
+  nature aircraft_engine_flows is array (engine_nodes, engines) of fluidic;
+        
+  --
+
+  nature sensor_matrix is array (1 to 100, 1 to 100) of translational;
+  
+  --
+
+  terminal sensor_grid : sensor_matrix;
+  
+  --
+
+  quantity sensor_data across sensor_grid to translational_ref;
+
+  -- end of code from book
+
+begin
+
+
+  process_1_b : process is
+    variable total_displacement, average_displacement : real;
+  begin
+
+    -- code from book:
+    
+    total_displacement := 0.0;
+    for x in 1 to 100 loop
+      for y in 1 to 100 loop
+        total_displacement := total_displacement + sensor_data(x, y);
+      end loop;
+    end loop;
+    average_displacement := total_displacement / 10000.0;
+    
+    --end code from book
+
+    wait;
+  end process process_1_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd
new file mode 100644
index 0000000..c3e1239
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_05.vhd
@@ -0,0 +1,125 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+  subtype coeff_ram_address is integer range 0 to 63;
+
+  -- code from book:
+
+  type coeff_array is array (coeff_ram_address) of real;
+
+  -- end of code from book
+
+  
+begin
+
+
+  process_1_c : process is
+
+    -- code from book:
+
+    type point is array (1 to 3) of real;
+    constant origin : point := (0.0, 0.0, 0.0);
+    variable view_point : point := (10.0, 20.0, 0.0);
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process process_1_c;
+
+
+  process_1_d : process is
+
+    type point is array (1 to 3) of real;
+
+    -- code from book:
+
+    variable view_point : point := (1 => 10.0, 2 => 20.0, 3 => 0.0);
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process process_1_d;
+
+
+  process_1_e : process is
+
+    -- code from book:
+
+    variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, 3 to 63 => 0.0);
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process process_1_e;
+
+
+  process_1_f : process is
+
+    -- code from book:
+
+    variable coeff : coeff_array := (0 => 1.6, 1 => 2.3, 2 => 1.6, others => 0.0);
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process process_1_f;
+
+
+  process_1_g : process is
+
+    -- code from book:
+
+    variable coeff : coeff_array := (0 | 2 => 1.6, 1 => 2.3, others => 0.0);
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process process_1_g;
+
+
+  process_1_h : process is
+
+    -- code from book:
+
+    -- error: Associations in array aggregate must be all named or all positional
+    -- variable coeff : coeff_array := (1.6, 2.3, 2 => 1.6, others => 0.0);  -- illegal
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process process_1_h;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd
new file mode 100644
index 0000000..317ea13
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_06a.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_06a is
+
+end entity inline_06a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06a is
+
+  -- code from book:
+
+  subtype resistance is real tolerance "default_resistance";
+  type resistance_array is array (1 to 4) of resistance;
+  quantity resistances : resistance_array := (10.0, 20.0, 50.0, 75.0);
+
+  -- end of code from book
+
+
+begin
+
+
+  block_1_f : block is
+
+    -- code from book:
+
+    quantity resistances : resistance_array := (1 => 10.0, 2 => 20.0, 3 => 50.0, 4 => 75.0);
+
+    -- end of code from book
+
+  begin
+  end block block_1_f;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd
new file mode 100644
index 0000000..1a3daf3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_07a.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_07a is
+
+end entity inline_07a;
+
+
+----------------------------------------------------------------
+
+
+library ieee_proposed;  use ieee_proposed.thermal_systems.all;
+
+architecture test of inline_07a is
+
+  -- code from book:
+
+  type A is array (1 to 4, 31 downto 0) of boolean;
+
+  nature B is array (1 to 10, 19 downto 0) of thermal;
+
+  -- end of code from book
+
+begin
+
+
+  process_1_i : process is
+
+    variable free_map : bit_vector(1 to 10) := "0011010110";
+    variable count : natural;
+
+  begin
+
+    -- code from book (just the conditions):
+
+    assert A'low(1) = 1;                       assert B'left(1) = 1;
+    assert A'high(2) = 31;                     assert B'right(2) = 0;
+
+--  assert A'reverse_range(2) is 0 to 31;      assert B'range(1) is 1 to 10;
+
+    assert A'length(2) = 32;                   assert B'length(1) = 10;
+
+    assert A'ascending(2) = false;             assert B'ascending(1) = true;
+
+    assert A'low = 1;                          assert A'length = 4;
+    assert B'high = 10;                        assert B'length = 10;
+
+  --
+
+    count := 0;
+    for index in free_map'range loop
+      if free_map(index) = '1' then
+        count := count + 1;
+      end if;
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_1_i;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd
new file mode 100644
index 0000000..51d617f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_08.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_08 is
+begin
+
+
+  process_2_a : process is
+
+    -- code from book:
+
+    type sample is array (natural range <>) of integer;
+
+    variable short_sample_buf : sample(0 to 63);
+
+    subtype long_sample is sample(0 to 255);
+    variable new_sample_buf, old_sample_buf : long_sample;
+
+    constant lookup_table : sample := ( 1 => 23, 3 => -16, 2 => 100, 4 => 11);
+
+    constant beep_sample : sample := ( 127, 63, 0, -63, -127, -63, 0, 63 );
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process process_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd
new file mode 100644
index 0000000..7b4c161
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_09a.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_09a is
+
+end entity inline_09a;
+
+
+----------------------------------------------------------------
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+architecture test of inline_09a is
+
+  -- code from book:
+
+  nature electrical_vector is array (natural range <>) of electrical;
+
+  terminal local_bus : electrical_vector(15 downto 0);
+  
+  subnature long_bus is electrical_vector(7 downto 0);
+  terminal remote_bus : long_bus;
+    
+  -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd
new file mode 100644
index 0000000..b5dc185
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_10.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_10 is
+
+end entity inline_10;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.std_ulogic;
+
+architecture test of inline_10 is
+
+  -- code from book:
+
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+  
+  --
+  
+  subtype std_ulogic_word is std_ulogic_vector(0 to 31);
+  
+  --
+  
+  signal csr_offset : std_ulogic_vector(2 downto 1);
+
+  -- end of code from book
+
+begin
+
+
+  process_2_b : process is
+
+    -- code from book:
+
+    type string is array (positive range <>) of character;
+
+    --
+
+    constant LCD_display_len : positive := 20;
+    subtype LCD_display_string is string(1 to LCD_display_len);
+    variable LCD_display : LCD_display_string := (others => ' ');
+
+    --
+
+    type bit_vector is array (natural range <>) of bit;
+
+    --
+    
+    subtype byte is bit_vector(7 downto 0);
+
+    --
+
+    variable channel_busy_register : bit_vector(1 to 4);
+
+    --
+
+    constant ready_message  : string := "Ready     ";
+
+    --
+
+    variable current_test : std_ulogic_vector(0 to 13) := "ZZZZZZZZZZ----";
+
+    --
+
+    constant all_ones : std_ulogic_vector(15 downto 0) := X"FFFF";
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    channel_busy_register := b"0000";
+
+    -- end of code from book
+
+    wait;
+  end process process_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd
new file mode 100644
index 0000000..1ba0a34
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_11a.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_11a is
+
+end entity inline_11a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_11a is
+
+  -- code from book:
+
+  type real_vector is array (natural range <>) of real;
+  
+  --
+  
+  subtype gains is real_vector(15 downto 0);
+  
+  --
+  
+  quantity max_temperatures : real_vector(1 to 10);
+
+  -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd
new file mode 100644
index 0000000..84c242f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_12.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_12 is
+
+end entity inline_12;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_12 is
+begin
+
+
+  process_3_a : process is
+
+    -- code from book:
+
+    subtype pixel_row is bit_vector (0 to 15);
+    variable current_row, mask : pixel_row;
+
+    -- end of code from book
+
+  begin
+
+    current_row := "0000000011111111";
+    mask := "0000111111110000";
+
+    -- code from book:
+
+    current_row := current_row and not mask;
+    current_row := current_row xor X"FFFF";
+
+    -- end of code from book
+
+    -- code from book (conditions only):
+
+    assert B"10001010" sll 3  =  B"01010000";
+    assert B"10001010" sll -2  =  B"00100010";
+
+    assert B"10010111" srl 2  = B"00100101";
+    assert B"10010111" srl -6  =  B"11000000";
+
+    assert B"01001011" sra 3  =  B"00001001";
+    assert B"10010111" sra 3  =  B"11110010";
+    assert B"00001100" sla 2  =  B"00110000";
+    assert B"00010001" sla 2  =  B"01000111";
+
+    assert B"00010001" sra -2  =  B"01000111";
+    assert B"00110000" sla -2  =  B"00001100";
+
+    assert B"10010011" rol 1  =  B"00100111";
+    assert B"10010011" ror 1  =  B"11001001";
+
+    assert "abc" & 'd'  =  "abcd";
+    assert 'w' & "xyz"  =  "wxyz";
+    assert 'a' & 'b'  =  "ab";
+
+    -- end of code from book
+
+    wait;
+  end process process_3_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd
new file mode 100644
index 0000000..9eef5af
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_13.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_13 is
+
+end entity inline_13;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_13 is
+begin
+
+
+  process_3_b : process is
+
+    -- code from book:
+
+    type array1 is array (1 to 100) of integer;
+    type array2 is array (100 downto 1) of integer;
+
+    variable a1 : array1;
+    variable a2 : array2;
+
+    -- end of code from book
+
+  begin
+
+    a1(11 to 20) := a1(11 to 20);
+    a2(50 downto 41) := a2(50 downto 41);
+
+    a1(10 to 1) := a1(10 to 1);
+    a2(1 downto 10) := a2(1 downto 10);
+
+    a1(10 downto 1) := a1(10 downto 1);  -- illegal
+    a2(1 to 10) := a2(1 to 10);  -- illegal;
+
+    wait;
+  end process process_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd
new file mode 100644
index 0000000..ab0fa8b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_14a.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_14a is
+
+end entity inline_14a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_14a is
+
+  -- code from book:
+
+  type array3 is array (10 downto 1) of real tolerance "default";
+
+  quantity a3 : array3;
+
+  -- end of code from book
+  
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd
new file mode 100644
index 0000000..cd58766
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_15.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_15 is
+
+end entity inline_15;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_15 is
+begin
+
+
+  process_3_c : process is
+
+    -- code from book:
+
+    subtype name is string(1 to 20);
+    type display_string is array (integer range 0 to 19) of character;
+
+    variable item_name : name;
+    variable display : display_string;
+
+    --
+
+    subtype big_endian_upper_halfword is bit_vector(0 to 15);
+    subtype little_endian_upper_halfword is bit_vector(31 downto 16);
+
+    variable big : big_endian_upper_halfword;
+    variable little : little_endian_upper_halfword;
+
+    -- end of code from book
+
+  begin
+
+    -- error: Incompatible types for assignment
+    -- display := item_name;  -- ilegal
+
+    item_name := (others => 'A');
+
+    little := x"AAAA";
+
+    -- code from book:
+
+    display := display_string(item_name);
+
+    --
+
+    big := little;
+    little := big;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_c;
+
+
+  ----------------
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd
new file mode 100644
index 0000000..3ffbd2c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_16.vhd
@@ -0,0 +1,106 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_16 is
+
+end entity inline_16;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_16 is
+
+  -- code from book:
+
+  type time_stamp is record
+      seconds : integer range 0 to 59;
+      minutes : integer range 0 to 59;
+      hours : integer range 0 to 23;
+    end record time_stamp;
+
+  -- end of code from book
+
+begin
+
+
+  process_4_a : process is
+
+    -- code from book:
+
+    variable sample_time, current_time : time_stamp;
+
+    --
+
+    constant midday : time_stamp := (0, 0, 12);
+
+    -- end of code from book
+
+    constant clock : integer := 79;
+    variable sample_hour : integer;
+
+  begin
+
+    current_time := (30, 15, 2);
+
+    -- code from book:
+
+    sample_time := current_time;
+
+    sample_hour := sample_time.hours;
+
+    current_time.seconds := clock mod 60;
+
+    -- end of code from book
+
+    wait;
+  end process process_4_a;
+
+
+  process_4_b : process is
+
+    type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop);
+    type reg_number is range 0 to 31;
+
+    type instruction is record
+        opcode : opcodes;
+        source_reg1, source_reg2, dest_reg : reg_number;
+        displacement : integer;
+      end record instruction;
+
+    -- code from book:
+
+    constant midday : time_stamp := (hours => 12, minutes => 0, seconds => 0);
+
+    --
+
+    constant nop_instr : instruction :=
+        ( opcode => addu,
+          source_reg1 | source_reg2 | dest_reg => 0,
+          displacement => 0 );
+
+    variable latest_event : time_stamp := (others => 0); -- initially midnight
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process process_4_b;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd
new file mode 100644
index 0000000..a3f4a69
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/inline_17a.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_17a is
+
+end entity inline_17a;
+
+
+----------------------------------------------------------------
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+architecture test of inline_17a is
+
+  -- code from book:
+
+  nature electrical_bus is record
+      strobe : electrical;
+      bus_lines : electrical_vector(0 to 15);
+    end record electrical_bus;
+
+  terminal address_bus, data_bus : electrical_bus;
+  
+  quantity data_voltages across data_currents through data_bus;
+
+  -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd
new file mode 100644
index 0000000..3a4af64
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/modem_controller.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity modem_controller is
+
+end entity modem_controller;
+
+
+----------------------------------------------------------------
+
+
+architecture test of modem_controller is
+begin
+
+  -- code from book:
+
+  modem_controller : process is
+
+    type symbol is ('a', 't', 'd', 'h', digit, cr, other);
+    type symbol_string is array (1 to 20) of symbol;
+    type state is range 0 to 6;
+    type transition_matrix is array (state, symbol) of state;
+
+    constant next_state : transition_matrix :=
+      ( 0 => ('a' => 1, others => 6),
+        1 => ('t' => 2, others => 6),
+        2 => ('d' => 3, 'h' => 5, others => 6),
+        3 => (digit => 4, others => 6),
+        4 => (digit => 4, cr => 0, others => 6),
+        5 => (cr => 0, others => 6),
+        6 => (cr => 0, others => 6) );
+
+    variable command : symbol_string;
+    variable current_state : state := 0;
+
+    -- not in book:
+    type sample_array is array (positive range <>) of symbol_string;
+    constant sample_command : sample_array :=
+      ( 1 => ( 'a', 't', 'd', digit, digit, cr, others => other ),
+        2 => ( 'a', 't', 'h', cr, others => other ),
+        3 => ( 'a', 't', other, other, cr, others => other ) );
+    -- end not in book
+
+  begin
+    -- . . .
+    -- not in book:
+    for command_index in sample_command'range loop
+      command := sample_command(command_index);
+    -- end not in book
+    for index in 1 to 20 loop
+      current_state := next_state( current_state, command(index) );
+      case current_state is
+        -- . . .
+        -- not in book:
+        when 0 => exit;
+        when others => null;
+        -- end not in book
+      end case;
+    end loop;
+    -- . . .
+    -- not in book:
+    end loop;
+    wait;
+    -- end not in book
+  end process modem_controller;
+
+  -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd
new file mode 100644
index 0000000..6723631
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_and_multiple.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_and_multiple is
+
+end entity tb_and_multiple;
+
+
+----------------------------------------------------------------
+
+
+architecture test_behavioral of tb_and_multiple is
+
+  -- code from book:
+
+  signal count_value : bit_vector(7 downto 0);
+  signal terminal_count : bit;
+
+  -- end of code from book
+
+begin
+
+  -- code from book:
+
+  tc_gate : entity work.and_multiple(behavioral)
+    port map ( i => count_value, y => terminal_count);
+
+  -- end of code from book
+
+  stumulus : process is
+  begin
+    			wait for 10 ns;
+    count_value <= "10000000";	wait for 10 ns;
+    count_value <= "11111110";	wait for 10 ns;
+    count_value <= "01111111";	wait for 10 ns;
+    count_value <= "11111111";	wait for 10 ns;
+    count_value <= "00000000";	wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd
new file mode 100644
index 0000000..865378a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_byte_swap.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_byte_swap is
+
+end entity tb_byte_swap;
+
+
+----------------------------------------------------------------
+
+
+use work.byte_swap_types.all;
+
+
+architecture test_behavior of tb_byte_swap is
+
+  signal input, output : halfword := x"0000";
+
+begin
+
+  dut : entity work.byte_swap(behavior)
+    port map ( input => input, output => output );
+
+  stumulus : process is
+  begin
+			wait for 10 ns;
+    input <= x"ff00";	wait for 10 ns;
+    input <= x"00ff";	wait for 10 ns;
+    input <= x"aa33";	wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd
new file mode 100644
index 0000000..0b7fd1f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/tb_coeff_ram.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_coeff_ram is
+
+end entity tb_coeff_ram;
+
+
+----------------------------------------------------------------
+
+
+architecture test_abstract of tb_coeff_ram is
+
+  use work.coeff_ram_types.all;
+
+  signal rd, wr : bit := '0';
+  signal addr : coeff_ram_address := 0;
+  signal d_in, d_out : real := 0.0;
+
+begin
+
+  dut : entity work.coeff_ram(abstract)
+    port map ( rd => rd, wr => wr,
+	       addr => addr,
+	       d_in => d_in, d_out => d_out );
+
+  stumulus : process is
+
+  begin
+    wait for 100 ns;
+
+    addr <= 10;  d_in <= 10.0;  wait for 10 ns;
+    wr <= '1';			wait for 10 ns;
+    d_in <= 20.0;  		wait for 10 ns;
+    wr <= '0';			wait for 70 ns;
+
+    addr <= 20;			wait for 10 ns;
+    rd <= '1';			wait for 10 ns;
+    addr <= 10;			wait for 10 ns;
+    rd <= '0';			wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd
new file mode 100644
index 0000000..200e587
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/transmission_lines.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+package transmission_lines_types is
+
+  type word is array (0 to 31) of bit;
+
+  subtype bus_lines is integer range 0 to 31;
+  nature electrical_bus is array (bus_lines) of electrical;
+
+end package transmission_lines_types;
+
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+use work.transmission_lines_types.all;
+
+-- end not in book
+
+entity transmission_lines is
+  port ( terminal data_bus : electrical_bus;
+         signal clk : in bit;  signal data_out : out word );
+end entity transmission_lines;
+
+----------------------------------------------------------------
+
+architecture abstract of transmission_lines is
+  constant threshold : voltage := 1.5;
+  quantity bus_voltages across bus_currents through
+           data_bus to electrical_ref;
+begin
+  
+  logic_value_maps : process (clk) is
+  begin
+    if clk = '1' then
+      for index in bus_lines loop
+        if bus_voltages(index) > threshold then
+          data_out(index) <= '1';
+        else
+          data_out(index) <= '0';
+        end if;
+      end loop;
+    end if;
+  end process logic_value_maps;
+  
+  -- additional VHDL-AMS code to describe reflections and attenuation
+  -- ...
+  
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd
new file mode 100644
index 0000000..f52bcb8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/active_filter.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+  port ( terminal node1, node2 : electrical );
+end entity resistor;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity capacitor is
+  port ( terminal node1, node2 : electrical );
+end entity capacitor;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity LF353_opamp is
+  port ( terminal plus, minus, output, pos_supply, neg_supply : electrical );
+end entity LF353_opamp;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity active_filter is
+end entity active_filter;
+
+-- end not in book
+
+
+
+library widget_parts, wasp_lib;
+
+architecture component_based of active_filter is
+  
+  -- declaration of signals, terminals, quantities, etc
+  -- ...
+  
+  -- not in book
+
+  terminal input, node2, node3, node4, node7, node15, Vdd, Vss : electrical;
+
+  -- end not in book
+
+begin
+  
+  R1 : entity wasp_lib.resistor
+    port map ( node1 => input, node2 => node2 );
+
+  C1 : entity widget_parts.capacitor
+    port map ( node1 => node3, node2 => ground );
+
+  Amp1 : entity work.LF353_opamp
+    port map ( plus => node4, minus => node7, output => node15,
+               pos_supply => Vdd, neg_supply => Vss );
+
+  -- other component instantiations
+  -- ...
+  
+end architecture component_based;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd
new file mode 100644
index 0000000..9532e9c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/dff.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+               
+entity dff is
+  port ( signal d, clk : in std_ulogic;  q : out std_ulogic );
+end entity dff;
+
+----------------------------------------------------------------
+
+architecture behav of dff is
+begin
+  
+  storage : process ( clk ) is
+  begin
+    if clk'event and (clk = '1' or clk = 'H') then
+      q <= d after 5 ns;
+    end if;
+  end process storage;
+        
+end architecture behav;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/index-ams.txt
new file mode 100644
index 0000000..a01c376
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/index-ams.txt
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                          Chapter 7 - Design Processing
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+inverting_integrator.vhd                        entity inverting_integrator             structural                      Figure 7-3
+dff.vhd                                         entity dff                              behav                           Figure 7-4
+volume_sensor.vhd                               entity volume_sensor                    structural                      Figure 7-5
+active_filter.vhd                               entity resistor                         --                              --
+--                                              entity capacitor                        --                              --
+--                                              entity LF353_opamp                      --                              --
+--                                              entity active_filter                    component_based                 Figure 7-7
+inline_01a.vhd                                  entity inline_01a                       test                            Section 7.1
+inline_02a.vhd                                  entity inline_02a                       test                            Section 7.1
+inline_03a.vhd                                  entity bottom                           bottom_arch                     Section 7.2
+--                                              entity other_ent                        other_arch                      --
+--                                              entity inline_03a                       test                            Section 7.2
+inline_04a.vhd                                  entity battery                          wrong, correct                  Section 7.2
+--                                              entity inline_04a                       test                            Section 7.2
+inline_05a.vhd                                  entity inline_05a                       test                            Section 7.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_volume_sensor.vhd                            entity tb_volume_sensor                 test_bench                      volume_sensor.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd
new file mode 100644
index 0000000..09ff947
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_01a.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_01a is
+
+end entity inline_01a;
+
+
+----------------------------------------------------------------
+
+
+-- code from book:
+
+library widget_parts, wasp_lib;
+
+use widget_parts.capacitor;
+
+-- end of code from book
+
+
+architecture test of inline_01a is
+
+  terminal node3 : electrical;
+
+begin
+
+  -- code from book:
+
+  C1 : entity capacitor
+    port map ( node1 => node3, node2 => ground );
+
+  -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd
new file mode 100644
index 0000000..f1b8e8a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_02a.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+----------------------------------------------------------------
+
+
+library wasp_lib;
+
+-- code from book:
+
+use wasp_lib.all;
+
+-- end of code from book
+
+
+architecture test of inline_02a is
+begin
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd
new file mode 100644
index 0000000..3b2ac9f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_03a.vhd
@@ -0,0 +1,121 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+-- code from book
+
+entity bottom is
+  port ( terminal Tb : electrical; -- ... );
+  -- not in book
+         terminal Tz : electrical );
+  -- end not in book
+end entity bottom;
+
+-- end code from book
+
+
+architecture bottom_arch of bottom is
+
+  -- code from book
+
+  quantity -- ...
+           i_b1 through Tb to Tz; -- ...;
+  quantity -- ...
+           i_b2 through Tb to Tz; -- ...;
+  quantity -- ...
+           i_b3 through Tz to Tb; -- ... to Tb;
+  quantity -- ...
+           i_b4 through Tz to Tb; -- ... to Tb;
+
+  -- end code from book
+
+begin
+
+  assert
+  -- code from book
+  Tb'contribution = ( i_b1 + i_b2 ) - ( i_b3 + i_b4 )
+  -- end code from book
+  ;
+
+end architecture bottom_arch;
+
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity other_ent is
+  port ( terminal Tx, Tz : electrical );
+end entity other_ent;
+
+
+architecture other_arch of other_ent is
+begin
+end architecture other_arch;
+
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_03a is
+
+end entity inline_03a;
+
+
+architecture test of inline_03a is
+
+  terminal Ty, Tb, Tx : electrical;
+
+  -- code from book
+
+  terminal T : electrical;
+  quantity -- ...
+           i_t1, i_t2 through T to Ty; -- ...;
+  quantity -- ...
+           i_t3 through Ty to T; -- ... to T;
+  -- ...
+
+  -- end code from book
+
+begin
+
+  -- code from book
+
+  comp1 : entity work.bottom(bottom_arch)
+    port map ( Tb => T, -- ... );
+    -- not in book
+               Tz => Ty );
+    -- end not in book
+  
+  comp2 : entity work.other_ent(other_arch)
+    port map ( Tx => T, -- ... );
+    -- not in book
+               Tz => Ty );
+    -- end not in book
+ 
+  -- end code from book
+
+
+  assert
+  -- code from book
+    T'contribution = ( i_t1 + i_t2 ) - ( i_t3 ) + ( Tb'contribution + Tx'contribution )
+  -- end code from book
+  ;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd
new file mode 100644
index 0000000..a3e8cf0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_04a.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+-- code from book
+
+entity battery is
+  port ( terminal plus, minus : electrical );
+end entity battery;
+
+architecture wrong of battery is
+  constant v_nominal : real := 9.0;
+  quantity v across plus to minus;
+begin
+  v == v_nominal;
+end architecture wrong;
+
+--
+
+architecture correct of battery is
+  constant v_nominal : real := 9.0;
+  quantity v across i through plus to minus;
+begin
+  v == v_nominal;
+end architecture correct;
+
+-- end code from book
+
+                        
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_04a is
+
+end entity inline_04a;
+
+
+architecture test of inline_04a is
+
+  signal clamp : bit;
+  quantity v1, v2 : real;
+
+begin
+
+  -- code from book
+
+  if clamp = '1' use
+    v1 == 5.0;
+    v2 == 0.0;
+  else
+    v1 == v2;
+  end use;
+
+  -- end code from book
+
+end architecture test;
+                        
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd
new file mode 100644
index 0000000..7cfd1fc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inline_05a.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05a is
+
+end entity inline_05a;
+
+
+architecture test of inline_05a is
+
+  -- code from book
+
+  type domain_type is (quiescent_domain, time_domain, frequency_domain);
+  
+  signal domain : domain_type := quiescent_domain;
+
+  -- end code from book
+
+begin
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd
new file mode 100644
index 0000000..82e86c0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/inverting_integrator.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inverting_integrator is 
+  port ( terminal input, output : electrical;
+         signal rst : in std_ulogic );
+end entity inverting_integrator;
+
+----------------------------------------------------------------
+
+architecture structural of inverting_integrator is
+  terminal internal : electrical;
+begin
+  
+  r1 : entity work.resistor(ideal)
+    port map ( node1 => input, node2 => internal);
+  
+  c1 : entity work.capacitor(leakage)
+    port map ( node1 => internal, node2 => output );
+  
+  amp : entity work.opamp(slew_limited)
+    port map ( plus_in => electrical_ref, minus_in => internal,
+               output => output);
+  
+  switch : entity work.analog_switch(ideal)
+    port map ( n1 => internal, n2 => output, control => rst );
+  
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd
new file mode 100644
index 0000000..82307fa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/tb_volume_sensor.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- created by: Veribest WaveBench Version 16.00.00.02
+library work; use work.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+library ieee; use ieee.std_logic_1164.all;
+
+entity  tb_volume_sensor is
+end  tb_volume_sensor;
+
+architecture test_bench of tb_volume_sensor is
+    -- Component declarations
+    -- Signal declarations
+  signal	clk, full, rst : std_logic;
+  terminal	flow, minus_ref : electrical;
+
+begin
+    -- Signal assignments
+    -- Component instances
+
+    vol1 : entity work.volume_sensor(structural)
+        port map(
+            clk => clk,
+            full => full,
+			rst => rst,
+			flow => flow,
+			minus_ref => minus_ref
+        );
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 1.0,
+            amplitude => 16.0
+        )
+        port map(
+            pos => flow,
+            neg => ELECTRICAL_REF
+        );
+    vm_ref : entity work.v_constant(ideal)
+        generic map(
+            level => -10.0
+        )
+        port map(
+            pos => minus_ref,
+            neg => ELECTRICAL_REF
+        );
+-- Test code generation processes  
+  -- clk
+    P_clk :
+    process
+    begin
+        clk <= '1';
+        wait for 500000.000 ns;
+        clk <= '0';
+        wait for 500000.000 ns;
+    end process P_clk;
+
+  -- rst
+    P_rst :
+    process
+    begin
+    	wait for 0.0 ms;	rst <=  '0';
+  		wait for 2.0 ms;	rst <=  '1';
+		wait for 2.0 ms;	rst <=  '0';
+		wait;
+    end process;
+
+  end test_bench;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd
new file mode 100644
index 0000000..6791450
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/design-processing/volume_sensor.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity volume_sensor is
+  port ( terminal flow, minus_ref : electrical;
+         signal clk, rst : in std_ulogic;
+         signal full : out std_ulogic );
+end entity volume_sensor;
+
+----------------------------------------------------------------
+
+architecture structural of volume_sensor is
+  
+  terminal minus_volume : electrical;
+  signal async_full, sync1_full : std_ulogic;
+  
+begin
+  
+  int : entity work.inverting_integrator(structural)
+    port map ( input => flow, output => minus_volume, rst => rst );
+        
+  comp : entity work.comparator(hysteresis)
+    port map ( plus_in => minus_volume, minus_in => minus_ref,
+               output => async_full );
+        
+  sync1 : entity work.dff(behav)
+    port map ( d => async_full, clk => clk, q => sync1_full );
+        
+  sync2 : entity work.dff(behav)
+    port map ( d => sync1_full, clk => clk, q => full );
+        
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd
new file mode 100644
index 0000000..9702b97
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop-1.vhd
@@ -0,0 +1,28 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity S_R_flipflop is
+  port ( s, r : in bit;  q, q_n : out bit );
+
+begin
+
+  check : assert not (s = '1' and r = '1')
+            report "Incorrect use of S_R_flip_flop: s and r both '1'";
+
+end entity S_R_flipflop;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd
new file mode 100644
index 0000000..a726b73
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/S_R_flipflop.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity S_R_flipflop is
+  port ( s, r : in bit;  q, q_n : out bit );
+end entity S_R_flipflop;
+
+--------------------------------------------------
+
+architecture functional of S_R_flipflop is
+
+begin
+
+  q <= '1' when s = '1' else
+       '0' when r = '1';
+
+  q_n <= '0' when s = '1' else
+         '1' when r = '1';
+
+  check : assert not (s = '1' and r = '1')
+            report "Incorrect use of S_R_flip_flop: s and r both '1'";
+
+end architecture functional;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd
new file mode 100644
index 0000000..4d9e5ca
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/alu.vhd
@@ -0,0 +1,138 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity alu is
+end entity alu;
+
+
+architecture test of alu is
+
+  constant Tpd : delay_length := 2 ns;
+
+  function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    alias op1 : bit_vector(1 to bv1'length) is bv1;
+    alias op2 : bit_vector(1 to bv2'length) is bv2;  
+    variable result : bit_vector(1 to bv1'length);
+    variable carry_in : bit;
+    variable carry_out : bit := '0';
+
+  begin
+    for index in result'reverse_range loop
+      carry_in := carry_out;  -- of previous bit
+      result(index) := op1(index) xor op2(index) xor carry_in;
+      carry_out := (op1(index) and op2(index))
+      	      	   or (carry_in and (op1(index) xor op2(index)));
+    end loop;
+    return result;
+  end function "+";
+
+  function "-" ( bv1, bv2 : in bit_vector ) return bit_vector is
+
+    -- subtraction implemented by adding ((not bv2) + 1), ie -bv2
+
+    alias op1 : bit_vector(1 to bv1'length) is bv1;
+    alias op2 : bit_vector(1 to bv2'length) is bv2;  
+    variable result : bit_vector(1 to bv1'length);
+    variable carry_in : bit;
+    variable carry_out : bit := '1';
+
+  begin
+    for index in result'reverse_range loop
+      carry_in := carry_out;  -- of previous bit
+      result(index) := op1(index) xor (not op2(index)) xor carry_in;
+      carry_out := (op1(index) and (not op2(index)))
+      	      	   or (carry_in and (op1(index) xor (not op2(index))));
+    end loop;
+    return result;
+  end function "-";
+
+  type alu_function_type is (alu_pass_a, alu_add, alu_sub,
+			     alu_add_unsigned, alu_sub_unsigned,
+			     alu_and, alu_or);
+
+  signal alu_function : alu_function_type := alu_pass_a;
+  signal a, b : bit_vector(15 downto 0);
+  signal functional_result, equivalent_result : bit_vector(15 downto 0);
+
+begin
+
+  functional_alu : block is
+    port ( result : out bit_vector(15 downto 0) );
+    port map ( result => functional_result );
+  begin
+
+    -- code from book
+
+    alu : with alu_function select
+            result <=  a + b after Tpd   when alu_add | alu_add_unsigned,
+                       a - b after Tpd   when alu_sub | alu_sub_unsigned,
+                       a and b after Tpd when alu_and,
+                       a or b after Tpd  when alu_or,
+                       a after Tpd       when alu_pass_a;
+
+    -- end code from book
+
+  end block functional_alu;
+
+  --------------------------------------------------
+    
+  equivalent_alu : block is
+    port ( result : out bit_vector(15 downto 0) );
+    port map ( result => equivalent_result );
+  begin
+
+    -- code from book
+
+    alu : process is
+    begin
+      case alu_function is
+        when alu_add | alu_add_unsigned =>  result <= a + b after Tpd;
+        when alu_sub | alu_sub_unsigned =>  result <= a - b after Tpd;
+        when alu_and                    =>  result <= a and b after Tpd;
+        when alu_or                     =>  result <= a or b after Tpd;
+        when alu_pass_a                 =>  result <= a after Tpd;
+      end case;
+      wait on alu_function, a, b;
+    end process alu;
+
+    -- end code from book
+
+  end block equivalent_alu;
+
+  --------------------------------------------------
+
+  stimulus : process is
+  begin
+    alu_function <= alu_add;	wait for 10 ns;
+    a <= X"000A";		wait for 10 ns;
+    b <= X"0003";		wait for 10 ns;
+    alu_function <= alu_sub;	wait for 10 ns;
+    alu_function <= alu_and;	wait for 10 ns;
+    alu_function <= alu_or;	wait for 10 ns;
+    alu_function <= alu_pass_a;	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  verifier :
+  assert functional_result = equivalent_result
+    report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd
new file mode 100644
index 0000000..479c3af
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and2.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity and2 is
+  port ( a, b : in std_ulogic;  y : out std_ulogic );
+end entity and2;
+
+--------------------------------------------------
+
+architecture detailed_delay of and2 is
+
+  signal result : std_ulogic;
+
+begin
+
+  gate : process (a, b) is
+  begin
+    result <= a and b;
+  end process gate;
+
+  delay : process (result) is
+  begin
+    if result = '1' then
+      y <= reject 400 ps inertial '1' after 1.5 ns;
+    elsif result = '0' then
+      y <= reject 300 ps inertial '0' after 1.2 ns;
+    else
+      y <= reject 300 ps inertial 'X' after 500 ps;
+    end if;
+  end process delay;
+
+end architecture detailed_delay;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd
new file mode 100644
index 0000000..15c325d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/and_or_inv.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity and_or_inv is
+  port ( a1, a2, b1, b2 : in bit := '1';
+	 y : out bit );
+end entity and_or_inv;
+
+-- end not in book
+
+
+architecture primitive of and_or_inv is
+
+  signal and_a, and_b : bit;
+  signal or_a_b : bit;
+
+begin
+
+  and_gate_a : process (a1, a2) is
+  begin
+    and_a <= a1 and a2;
+  end process and_gate_a;
+
+  and_gate_b : process (b1, b2) is
+  begin
+    and_b <= b1 and b2;
+  end process and_gate_b;
+
+  or_gate : process (and_a, and_b) is
+  begin
+    or_a_b <= and_a or and_b;
+  end process or_gate;
+
+  inv : process (or_a_b) is
+  begin
+    y <= not or_a_b;
+  end process inv;
+
+end architecture primitive;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd
new file mode 100644
index 0000000..122e95c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/asym_delay.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity asym_delay is
+end entity asym_delay;
+
+
+
+architecture test of asym_delay is
+
+  signal a, z : bit;
+
+begin
+
+  -- code from book
+
+  asym_delay : process (a) is
+    constant Tpd_01 : time := 800 ps;
+    constant Tpd_10 : time := 500 ps;
+  begin
+    if a = '1' then
+      z <= transport a after Tpd_01;
+    else  -- a = '0'
+      z <= transport a after Tpd_10;
+    end if;
+  end process asym_delay;
+
+  -- end code from book
+
+
+  stimulus : process is
+  begin
+    a <= '1' after 2000 ps,
+         '0' after 4000 ps,
+         '1' after 6000 ps,
+         '0' after 6200 ps;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd
new file mode 100644
index 0000000..e1ff36b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-1.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity clock_gen is
+end entity clock_gen;
+
+architecture test of clock_gen is
+
+  constant T_pw : time := 10 ns;
+
+  signal clk : bit;
+
+begin
+
+  -- code from book
+
+  clock_gen : process is
+  begin
+    clk <= '1' after T_pw, '0' after 2*T_pw;
+    wait until clk = '0';
+  end process clock_gen;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd
new file mode 100644
index 0000000..af7a7d4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen-2.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity clock_gen is
+end entity clock_gen;
+
+architecture test of clock_gen is
+
+  constant T_pw : time := 10 ns;
+
+  signal clk : bit;
+
+begin
+
+  -- code from book
+
+  clock_gen : process is
+  begin
+    clk <= '1' after T_pw, '0' after 2*T_pw;
+    wait for 2*T_pw;
+  end process clock_gen;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd
new file mode 100644
index 0000000..10b54b4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/clock_gen.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity clock_gen is
+end entity clock_gen;
+
+architecture test of clock_gen is
+
+  constant T_pw : time := 10 ns;
+
+  signal clk : bit;
+
+begin
+
+  -- code from book
+
+  clock_gen : process (clk) is
+  begin
+    if clk = '0' then
+      clk <= '1' after T_pw, '0' after 2*T_pw;
+    end if;
+  end process clock_gen;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd
new file mode 100644
index 0000000..15753d1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/computer_system.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+architecture abstract of computer_system is
+
+  subtype word is bit_vector(31 downto 0);
+
+  signal address : natural;
+  signal read_data, write_data : word;
+  signal mem_read, mem_write : bit := '0';
+  signal mem_ready : bit := '0';
+
+begin
+
+  cpu : process is
+    variable instr_reg : word;
+    variable PC : natural;
+    -- . . .    -- other declarations
+  begin
+    loop
+      address <= PC;
+      mem_read <= '1';
+      wait until mem_ready = '1';
+      instr_reg := read_data;
+      mem_read <= '0';
+      wait until mem_ready = '0';
+      PC := PC + 4;
+      -- . . .    -- execute the instruction
+    end loop;
+  end process cpu;
+
+  memory : process is
+    type memory_array is array (0 to 2**14 - 1) of word;
+    variable store : memory_array := (
+				       -- . . .
+				       -- not in book
+				       0 => X"0000_0000",
+				       1 => X"0000_0004",
+				       2 => X"0000_0008",
+				       3 => X"0000_000C",
+				       4 => X"0000_0010",
+				       5 => X"0000_0014",
+				       others => X"0000_0000"
+				        -- end not in book
+				     );
+  begin
+    wait until mem_read = '1' or mem_write = '1';
+    if mem_read = '1' then
+      read_data <= store( address / 4 );
+      mem_ready <= '1';
+      wait until mem_read = '0';
+      mem_ready <= '0';
+    else
+      -- . . .    -- perform write access
+    end if;
+  end process memory;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd
new file mode 100644
index 0000000..faf5f14
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/counter.vhd
@@ -0,0 +1,137 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+package counter_types is
+
+  -- code in book (in text)
+
+  subtype digit is bit_vector(3 downto 0);
+
+  -- end code in book (in text)
+
+end package counter_types;
+
+
+entity add_1 is
+  port ( d0, d1, d2, d3 : in bit;
+         y0, y1, y2, y3 : out  bit );
+end entity add_1;
+
+
+architecture boolean_eqn of add_1 is
+begin
+
+  y0 <= not d0 after 4 ns;
+
+  y1 <= (not d1 and d0)
+        or (d1 and not d0) after 4 ns;
+
+  y2 <= (not d2 and d1 and d0)
+	or (d2 and not (d1 and d0)) after 4 ns;
+
+  y3 <= (not d3 and d2 and d1 and d0)
+	or (d3 and not (d2 and d1 and d0)) after 4 ns;
+
+end architecture boolean_eqn;
+
+
+entity buf4 is
+  port ( a0, a1, a2, a3 : in bit;
+         y0, y1, y2, y3 : out  bit );
+end entity buf4;
+
+
+architecture basic of buf4 is
+begin
+
+  y0 <= a0 after 2 ns;
+  y1 <= a1 after 2 ns;
+  y2 <= a2 after 2 ns;
+  y3 <= a3 after 2 ns;
+
+end architecture basic;
+  
+
+use work.counter_types.all;
+
+-- end not in book
+
+
+entity counter is
+  port ( clk, clr : in bit;
+         q0, q1 : out digit );
+end entity counter;
+
+--------------------------------------------------
+
+architecture registered of counter is
+
+  signal current_val0, current_val1, next_val0, next_val1 : digit;
+
+begin
+
+  val0_reg : entity work.reg4(struct)
+    port map ( d0 => next_val0(0), d1 => next_val0(1),
+               d2 => next_val0(2), d3 => next_val0(3),
+               q0 => current_val0(0), q1 => current_val0(1),
+               q2 => current_val0(2), q3 => current_val0(3),
+               clk => clk, clr => clr );
+
+  val1_reg : entity work.reg4(struct)
+    port map ( d0 => next_val1(0), d1 => next_val1(1),
+               d2 => next_val1(2), d3 => next_val1(3),
+               q0 => current_val1(0), q1 => current_val1(1),
+               q2 => current_val1(2), q3 => current_val1(3),
+               clk => clk, clr => clr );
+
+  incr0 : entity work.add_1(boolean_eqn) -- . . .;
+    -- not in book
+    port map ( d0 => current_val0(0), d1 => current_val0(1),
+               d2 => current_val0(2), d3 => current_val0(3),
+	       y0 => next_val0(0), y1 => next_val0(1),
+               y2 => next_val0(2), y3 => next_val0(3) );
+    -- end not in book
+
+  incr1 : entity work.add_1(boolean_eqn) -- . . .;
+    -- not in book
+    port map ( d0 => current_val1(0), d1 => current_val1(1),
+               d2 => current_val1(2), d3 => current_val1(3),
+	       y0 => next_val1(0), y1 => next_val1(1),
+               y2 => next_val1(2), y3 => next_val1(3) );
+    -- end not in book
+
+  buf0 : entity work.buf4(basic) -- . . .;
+    -- not in book
+    port map ( a0 => current_val0(0), a1 => current_val0(1),
+               a2 => current_val0(2), a3 => current_val0(3),
+	       y0 => q0(0), y1 => q0(1),
+               y2 => q0(2), y3 => q0(3) );
+    -- end not in book
+
+  buf1 : entity work.buf4(basic) -- . . .;
+    -- not in book
+    port map ( a0 => current_val1(0), a1 => current_val1(1),
+               a2 => current_val1(2), a3 => current_val1(3),
+	       y0 => q1(0), y1 => q1(1),
+               y2 => q1(2), y3 => q1(3) );
+    -- end not in book
+
+end architecture registered;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd
new file mode 100644
index 0000000..d061a39
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/edge_triggered_Dff.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity edge_triggered_Dff is
+  port ( D : in bit;  clk : in bit;  clr : in bit;
+         Q : out bit );
+end entity edge_triggered_Dff;
+
+--------------------------------------------------
+
+architecture behavioral of edge_triggered_Dff is
+begin
+
+  state_change : process (clk, clr) is
+  begin
+    if clr = '1' then
+      Q <= '0' after 2 ns;
+    elsif clk'event and clk = '1' then
+      Q <= D after 2 ns;
+    end if;
+  end process state_change;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd
new file mode 100644
index 0000000..9b17dc1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/full_adder.vhd
@@ -0,0 +1,38 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity full_adder is
+  port ( a, b, c_in : bit;  s, c_out : out bit );
+end entity full_adder;
+
+
+architecture truth_table of full_adder is
+begin
+
+  with bit_vector'(a, b, c_in) select
+    (c_out, s) <= bit_vector'("00") when "000",
+                  bit_vector'("01") when "001",
+                  bit_vector'("01") when "010",
+                  bit_vector'("10") when "011",
+                  bit_vector'("01") when "100",
+                  bit_vector'("10") when "101",
+                  bit_vector'("10") when "110",
+                  bit_vector'("11") when "111";
+
+end architecture truth_table;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/index-ams.txt
new file mode 100644
index 0000000..aa17bf4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/index-ams.txt
@@ -0,0 +1,82 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                     Chapter 5 - Digital Modeling Constructs
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+program_rom.vhd                                 entity program_rom                      --                              Figure 5-1
+and_or_inv.vhd                                  entity and_or_inv                       primitive                       Figure 5-2
+clock_gen.vhd                                   entity clock_gen                        test                            Figure 5-3
+mux.vhd                                         entity mux                              test                            Figure 5-4
+edge_triggered_Dff.vhd                          entity edge_triggered_Dff               behavioral                      Figure 5-5
+mux2.vhd                                        entity mux2                             behavioral                      Figure 5-6
+clock_gen-1.vhd                                 entity clock_gen                        test                            Figure 5-7
+clock_gen-2.vhd                                 entity clock_gen                        test                            Figure 5-8
+computer_system.vhd                             entity computer_system                  abstract                        Figure 5-9
+asym_delay.vhd                                  entity asym_delay                       test                            Figure 5-12
+and2.vhd                                        entity and2                             detailed_delay                  Figure 5-16
+zmux.vhd                                        entity zmux                             test                            Figure 5-17
+zmux-1.vhd                                      entity zmux                             test                            Figure 5-18
+scheduler.vhd                                   entity scheduler                        test                            Figure 5-19
+alu.vhd                                         entity alu                              test                            Figure 5-20
+full_adder.vhd                                  entity full_adder                       truth_table                     Figure 5-21
+S_R_flipflop.vhd                                entity S_R_flipflop                     functional                      Figure 5-22
+S_R_flipflop-1.vhd                              entity S_R_flipflop                     --                              Figure 5-23
+rom.vhd                                         entity rom                              --                              Figure 5-24
+reg4.vhd                                        entity reg4                             struct                          Figure 5-25
+counter.vhd                                     package counter_types                   --                              Section 5.4
+--                                              entity add_1                            boolean_eqn                     --
+--                                              entity buf4                             basic                           --
+--                                              counter                                 registered                      Figure 5-27
+microprocessor.vhd                              reg                                     --                              Figure 5-28
+--                                              microprocessor                          RTL                             Figure 5-28
+inline_01.vhd                                   package adder_types                     --                              --
+--                                              entity adder                            --                              Section 5.1
+inline_02.vhd                                   package adder_types                     --                              --
+--                                              entity adder                            --                              Section 5.1
+inline_03.vhd                                   entity and_or_inv                       --                              Section 5.1
+inline_04.vhd                                   entity top_level                        --                              Section 5.1
+inline_05.vhd                                   --                                      abstract                        Section 5.2
+inline_06.vhd                                   entity inline_06                        test                            Section 5.3
+inline_07.vhd                                   entity inline_07                        test                            Section 5.3
+inline_08.vhd                                   entity inline_08                        test                            Section 5.3
+inline_09.vhd                                   entity inline_09                        test                            Section 5.3
+inline_10.vhd                                   entity inline_10                        test                            Section 5.3
+inline_11.vhd                                   entity inline_11                        test                            Section 5.3
+inline_12.vhd                                   entity inline_12                        test                            Section 5.3
+inline_13.vhd                                   entity inline_13                        test                            Section 5.3
+inline_14.vhd                                   entity inline_14                        test                            Section 5.3
+inline_15.vhd                                   entity inline_15                        test                            Section 5.3
+inline_16.vhd                                   entity inline_16                        test                            Section 5.3
+inline_17.vhd                                   entity inline_17                        test                            Section 5.3
+inline_18.vhd                                   entity DRAM_controller                  fpld                            Section 5.4
+--                                              entity inline_18                        test                            Section 5.4
+inline_19.vhd                                   package inline_19                       --                              Section 5.4
+inline_20.vhd                                   package inline_20_types                 --                              Section 5.4
+--                                              entity FIFO                             --                              --
+--                                              entity inline_20                        test                            Section 5.4
+inline_21.vhd                                   entity and_gate                         behavioral                      Section 5.4
+--                                              entity inline_21                        test                            Section 5.4
+inline_22.vhd                                   entity mux4                             functional                      Section 5.4
+--                                              entity inline_22                        test                            Section 5.4
+inline_23.vhd                                   entity and_or_inv                       functional                      Section 5.4
+--                                              entity inline_23                        test                            Section 5.4
+inline_24.vhd                                   entity and3                             functional                      Section 5.4
+--                                              entity inline_24                        test                            Section 5.4
+inline_28a.vhd                                  entity inline_28a                       test                            Section 5.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_and_or_inv.vhd                               entity tb_and_or_inv                    test                            and_or_inv.vhd
+tb_edge_triggered_Dff.vhd                       entity tb_edge_triggered_Dff            test                            edge_triggered_Dff.vhd
+tb_mux2.vhd                                     entity tb_mux2                          test                            mux2.vhd
+tb_and2.vhd                                     entity tb_and2                          test                            and2.vhd
+tb_full_adder.vhd                               entity tb_full_adder                    test                            full_adder.vhd
+tb_S_R_flipflop.vhd                             entity tb_S_R_flipflop                  test                            S_R_flipflop.vhd
+tb_S_R_flipflop-1.vhd                           --                                      functional                      S_R_flipflop.vhd
+--                                              entity tb_S_R_flipflop                  test                            --
+tb_rom.vhd                                      --                                      do_nothing                      rom.vhd
+--                                              entity tb_rom                           test                            --
+tb_reg4.vhd                                     entity tb_reg4                          test                            reg4.vhd
+tb_counter.vhd                                  entity tb_counter                       test                            counter.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd
new file mode 100644
index 0000000..adb54ff
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_01.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+package adder_types is
+
+  subtype word is integer;
+
+end package adder_types;
+
+
+use work.adder_types.all;
+
+-- end not in book
+
+entity adder is
+  port ( a : in word;
+         b : in word;
+         sum : out word );
+end entity adder;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd
new file mode 100644
index 0000000..898acfe
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_02.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+package adder_types is
+
+  subtype word is integer;
+
+end package adder_types;
+
+
+use work.adder_types.all;
+
+-- end not in book
+
+entity adder is
+  port ( a, b : in word;
+         sum : out word );
+end entity adder;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd
new file mode 100644
index 0000000..2708126
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_03.vhd
@@ -0,0 +1,23 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity and_or_inv is
+  port ( a1, a2, b1, b2 : in bit := '1';
+         y : out bit );
+end entity and_or_inv;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd
new file mode 100644
index 0000000..7b83355
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_04.vhd
@@ -0,0 +1,21 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity top_level is
+end entity top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd
new file mode 100644
index 0000000..a1ef02c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_05.vhd
@@ -0,0 +1,28 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+architecture abstract of adder is
+begin
+
+  add_a_b : process (a, b) is
+  begin
+    sum <= a + b;
+  end process add_a_b;
+
+end architecture abstract;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd
new file mode 100644
index 0000000..3fbe1ed
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_06.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+  signal y : bit := '0';
+  signal or_a_b : bit := '0';
+  signal clk : bit := '0';
+
+begin
+
+
+  process_3_a : process is
+  begin
+
+    -- code from book:
+
+    y <= not or_a_b after 5 ns;
+
+    -- end of code from book
+
+    wait on or_a_b;
+  end process process_3_a;
+
+
+  stimulus_3_a : process is
+  begin
+    or_a_b <= '1' after 20 ns,
+              '0' after 40 ns;
+    wait;
+  end process stimulus_3_a;
+
+
+  process_3_b : process is
+    constant T_pw : delay_length := 10 ns;
+  begin
+
+    -- code from book:
+
+    clk <= '1' after T_pw, '0' after 2*T_pw;
+
+    -- end of code from book
+
+    wait for 2*T_pw;
+  end process process_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd
new file mode 100644
index 0000000..8a4554d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_07.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of inline_07 is
+
+  signal clk, d : std_ulogic;
+
+  constant Tpw_clk : delay_length := 10 ns;
+  constant Tsu : delay_length := 4 ns;
+
+begin
+
+
+  process_3_c : process (clk, d) is
+  begin
+
+    -- code from book:
+
+    if clk'event and (clk = '1' or clk = 'H')
+                 and (clk'last_value = '0' or clk'last_value = 'L') 
+    then
+      assert d'last_event >= Tsu
+        report "Timing error: d changed within setup time of clk";
+    end if;
+
+    -- end of code from book
+
+  end process process_3_c;
+
+
+  ----------------
+
+
+  process_3_d : process (clk, d) is
+  begin
+
+    -- code from book:
+
+    assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
+      report "Clock frequency too high";
+
+    -- end of code from book
+
+  end process process_3_d;
+
+
+  ----------------
+
+
+  process_3_e : process is
+  begin
+
+    -- code from book:
+
+    wait until clk = '1';
+
+    -- end of code from book
+
+    report "clk changed to '1'";
+  end process process_3_e;
+
+
+  ----------------
+
+
+  stimulus_3_c_d : process is
+  begin
+
+    clk <= '1' after  15 ns,
+           '0' after  30 ns,
+           '1' after  40 ns,
+           '0' after  50 ns,
+           'H' after  60 ns,
+           '0' after  70 ns,
+           '1' after  80 ns,
+           'L' after  90 ns,
+           'H' after 100 ns,
+           'L' after 120 ns,
+           '1' after 125 ns, -- should cause error
+           '0' after 130 ns; -- should cause error
+
+    d <= '1' after  35 ns,
+         '0' after  77 ns, -- should cause error
+         '1' after 102 ns;
+
+    wait;
+  end process stimulus_3_c_d;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd
new file mode 100644
index 0000000..bcc6d1a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_08.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+library util;  use util.stimulus_generators.all;
+
+architecture test of inline_08 is
+
+  constant T_pd : delay_length := 5 ns;
+
+  signal a, b : bit := '0';
+  signal test_inputs : bit_vector(1 to 2);
+
+begin
+
+
+  block_3_f : block is
+
+    signal sum, carry : bit;
+
+  begin
+
+    -- code from book:
+
+    half_add : process is
+    begin
+      sum <= a xor b after T_pd;
+      carry <= a and b after T_pd;
+      wait on a, b;
+    end process half_add;
+
+    -- end of code from book
+
+  end block block_3_f;
+
+
+  ----------------
+
+
+  block_3_g : block is
+
+    signal sum, carry : bit;
+
+  begin
+
+    -- code from book:
+
+    half_add : process (a, b) is
+    begin
+      sum <= a xor b after T_pd;
+      carry <= a and b after T_pd;
+    end process half_add;
+
+    -- end of code from book
+
+  end block block_3_g;
+
+
+  ----------------
+
+
+  stimulus_3_f_g :
+    all_possible_values(test_inputs, 20 ns);
+
+  (a, b) <= test_inputs;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd
new file mode 100644
index 0000000..7839e85
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_09.vhd
@@ -0,0 +1,119 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+
+  signal clk, reset, trigger, test0, test1 : bit := '0';
+
+begin
+
+
+  process_3_h : process is
+  begin
+
+    -- code from book:
+
+    wait until clk = '1';
+
+    -- end of code from book
+
+    report "clk rising edge detected";
+
+  end process process_3_h;
+
+
+  ----------------
+
+
+  process_3_i : process is
+  begin
+
+    -- code from book:
+
+    wait on clk until reset = '0';
+
+    -- end of code from book
+
+    report "synchronous reset detected";
+
+  end process process_3_i;
+
+
+  ----------------
+
+
+  process_3_j : process is
+  begin
+
+    -- code from book:
+
+    wait until trigger = '1' for 1 ms;
+
+    -- end of code from book
+
+    if trigger'event and trigger = '1' then
+      report "trigger rising edge detected";
+    else
+      report "trigger timeout";
+    end if;
+
+  end process process_3_j;
+
+
+  ----------------
+
+
+  -- code from book:
+
+  test_gen : process is
+  begin
+    test0 <= '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns;
+    test1 <= '0' after 10 ns, '1' after 30 ns;
+    wait;
+  end process test_gen;
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus_3_h_i_j : process is
+  begin
+    clk <= '1' after 10 ns, '0' after 20 ns,
+           '1' after 30 ns, '0' after 40 ns,
+           '1' after 50 ns, '0' after 60 ns,
+           '1' after 70 ns, '0' after 80 ns;
+    reset <= '1' after 45 ns, '0' after 75 ns;
+    trigger <= '1' after 10 ns, '0' after 20 ns,
+               '1' after 30 ns, '0' after 40 ns;
+           
+    wait;
+  end process stimulus_3_h_i_j;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd
new file mode 100644
index 0000000..bca36c8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_10.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_10 is
+
+end entity inline_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_10 is
+
+  signal data : bit_vector(7 downto 0) := X"FF";
+  signal s : bit := '0';
+
+begin
+
+
+  process_3_l : process is
+  begin
+    wait for 10 ns;
+
+    -- code from book:
+
+   data <= X"00";
+
+    -- end of code from book
+
+    wait for 10 ns;
+
+    -- code from book:
+
+    s <= '1';
+    -- . . .
+    if s = '1' then -- . . .
+    -- not in book
+      report "s is '1'";
+    else
+      report "s is '0'";
+    end if;
+    -- end not in boook
+
+    -- end of code from book
+
+    wait;
+  end process process_3_l;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd
new file mode 100644
index 0000000..c86fd0a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_11.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_11 is
+
+end entity inline_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_11 is
+
+  signal line_in, line_out : bit := '0';
+
+begin
+
+
+  -- code from book:
+
+  transmission_line : process (line_in) is
+  begin
+    line_out <= transport line_in after 500 ps;
+  end process transmission_line;
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    line_in <= '1' after 2000 ps,
+               '0' after 4000 ps,
+               '1' after 6000 ps,
+               '0' after 6200 ps,
+               '1' after 8000 ps,
+               '0' after 8200 ps,
+               '1' after 8300 ps,
+               '0' after 8400 ps;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd
new file mode 100644
index 0000000..3892d65
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_12.vhd
@@ -0,0 +1,96 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_12 is
+
+end entity inline_12;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_12 is
+
+  signal top_a, bottom_a : bit := '0';
+  signal top_y, bottom_y : bit;
+
+begin
+
+
+  block_3_m : block is
+    port ( a : in bit;  y : out bit := '1' );
+    port map ( a => top_a, y => top_y );
+
+  begin
+
+    -- code from book:
+
+    inv : process (a) is
+    begin
+      y <= inertial not a after 3 ns;
+    end process inv;
+
+    -- end of code from book
+
+  end block block_3_m;
+
+
+  ----------------
+
+
+  block_3_n : block is
+    port ( a : in bit;  y : out bit := '1' );
+    port map ( a => bottom_a, y => bottom_y);
+
+  begin
+
+    -- code from book:
+
+    inv : process (a) is
+    begin
+      y <= reject 2 ns inertial not a after 3 ns;
+    end process inv;
+
+    -- end of code from book
+
+  end block block_3_n;
+
+
+  ----------------
+
+
+  stimulus_3_m_n : process is
+  begin
+    top_a <= '1' after 1 ns,
+             '0' after 6 ns,
+             '1' after 8 ns;
+    bottom_a <= '1' after 1 ns,
+                '0' after 6 ns,
+                '1' after 9 ns,
+                '0' after 11.5 ns,
+                '1' after 16 ns,
+                '0' after 18 ns,
+                '1' after 19 ns,
+                '0' after 20 ns;
+
+    wait;
+  end process stimulus_3_m_n;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd
new file mode 100644
index 0000000..54acc11
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_13.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_13 is
+
+end entity inline_13;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of inline_13 is
+
+  signal s : std_ulogic;
+
+begin
+
+
+  process_3_o : process is
+  begin
+    s <= '1' after 11 ns,
+         'X' after 12 ns,
+         '1' after 14 ns,
+         '0' after 15 ns,
+         '1' after 16 ns,
+         '1' after 17 ns,
+         '1' after 20 ns,
+         '0' after 25 ns;
+    wait for 10 ns;
+
+    -- code from book:
+
+    s <= reject 5 ns inertial '1' after 8 ns;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_o;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd
new file mode 100644
index 0000000..359f880
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_14.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_14 is
+
+end entity inline_14;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_14 is
+
+  signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
+
+begin
+
+
+  block_3_p : block is
+    port ( next_PC : out integer );
+    port map ( next_PC => functional_next_PC );
+  begin
+
+    -- code from book:
+
+    PC_incr : next_PC <= PC + 4 after 5 ns;
+
+    -- end of code from book
+
+  end block block_3_p;
+
+
+  ----------------
+
+
+  block_3_q : block is
+    port ( next_PC : out integer );
+    port map ( next_PC => equivalent_next_PC );
+  begin
+
+    -- code from book:
+
+    PC_incr : process is
+    begin
+      next_PC <= PC + 4 after 5 ns;
+      wait on PC;
+    end process PC_incr;
+
+    -- end of code from book
+
+  end block block_3_q;
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    for i in 1 to 10 loop
+      PC <= i after 20 ns;
+      wait for 20 ns;
+    end loop;
+    wait;
+  end process stimulus;
+
+  verifier :
+  assert functional_next_PC = equivalent_next_PC
+    report "Functional and equivalent models give different results";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd
new file mode 100644
index 0000000..a0cd6e8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_15.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_15 is
+  generic ( extended_reset : boolean := false );
+end entity inline_15;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_15 is
+
+  signal functional_reset, equivalent_reset : bit := '0';
+
+begin
+
+
+  block_3_r : block is
+    port ( reset : out bit );
+    port map ( reset => functional_reset );
+  begin
+
+    -- code from book:
+
+    reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
+                         '1', '0' after 50 ns;
+
+    -- end of code from book
+
+  end block block_3_r;
+
+
+  ----------------
+
+
+  block_3_s : block is
+    port ( reset : out bit );
+    port map ( reset => equivalent_reset );
+  begin
+
+    -- code from book:
+
+    reset_gen : process is
+    begin
+      if extended_reset then
+        reset <= '1', '0' after 200 ns;
+      else
+        reset <= '1', '0' after 50 ns;
+      end if;
+      wait;
+    end process reset_gen;
+
+    -- end of code from book
+
+  end block block_3_s;
+
+
+  ----------------
+
+
+  verifier :
+  assert functional_reset = equivalent_reset
+    report "Functional and equivalent models give different results";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd
new file mode 100644
index 0000000..8be519e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_16.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_16 is
+
+end entity inline_16;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_16 is
+
+  constant Tpd_01 : time := 800 ps;
+  constant Tpd_10 : time := 500 ps;
+
+  signal a, z : bit;
+
+begin
+
+
+  -- code from book:
+
+  asym_delay : z <= transport a after Tpd_01 when a = '1' else
+                              a after Tpd_10;
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    a <= '1' after 2000 ps,
+         '0' after 4000 ps,
+         '1' after 6000 ps,
+         '0' after 6200 ps;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd
new file mode 100644
index 0000000..f0a40ce
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_17.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_17 is
+
+end entity inline_17;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_17 is
+
+  signal s, r, q, q_n : bit := '0';
+
+begin
+
+  q <= '1' when s = '1' else
+       '0' when r = '1';
+
+  q_n <= '0' when s = '1' else
+         '1' when r = '1';
+
+
+  -- code from book:
+
+  check : process is
+  begin
+    assert not (s = '1' and r = '1')
+      report "Incorrect use of S_R_flip_flop: s and r both '1'";
+    wait on s, r;
+  end process check;
+
+  -- end of code from book
+
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd
new file mode 100644
index 0000000..dee1aae
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_18.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book:
+
+entity DRAM_controller is
+  port ( rd, wr, mem : in bit;
+         ras, cas, we, ready : out bit  );
+end entity DRAM_controller;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture fpld of DRAM_controller is
+begin
+end architecture fpld;
+
+
+----------------------------------------------------------------
+
+
+entity inline_18 is
+
+end entity inline_18;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_18 is
+
+
+
+begin
+
+
+  block_4_a : block is
+    signal cpu_rd, cpu_wr, cpu_mem,
+           mem_ras, mem_cas, mem_we, cpu_rdy : bit;
+  begin
+
+    -- code from book:
+
+    main_mem_controller : entity work.DRAM_controller(fpld)
+      port map ( cpu_rd, cpu_wr, cpu_mem,
+                 mem_ras, mem_cas, mem_we, cpu_rdy );
+
+    -- end of code from book
+
+  end block block_4_a;
+
+
+  ----------------
+
+
+  block_4_b : block is
+    signal cpu_rd, cpu_wr, cpu_mem,
+           mem_ras, mem_cas, mem_we, cpu_rdy : bit;
+  begin
+
+    -- code from book:
+
+    main_mem_controller : entity work.DRAM_controller(fpld)
+      port map ( rd => cpu_rd, wr => cpu_wr,
+                 mem => cpu_mem, ready => cpu_rdy,
+                 ras => mem_ras, cas => mem_cas, we => mem_we );
+
+    -- end of code from book
+
+  end block block_4_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd
new file mode 100644
index 0000000..b24c90f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_19.vhd
@@ -0,0 +1,28 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package inline_19 is
+
+  -- code from book:
+
+  subtype digit is bit_vector(3 downto 0);
+
+  -- end of code from book
+
+end package inline_19;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd
new file mode 100644
index 0000000..ab99cf8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_20.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package inline_20_types is
+
+  -- code from book:
+
+  type FIFO_status is record
+      nearly_full, nearly_empty, full, empty : bit;
+    end record FIFO_status;
+
+  -- end of code from book
+
+end package inline_20_types;
+
+
+----------------------------------------------------------------
+
+
+use work.inline_20_types.all;
+
+entity FIFO is
+  port ( status : out FIFO_status;
+         other_ports : out bit );
+end entity FIFO;
+
+
+----------------------------------------------------------------
+
+
+entity inline_20 is
+
+end entity inline_20;
+
+
+----------------------------------------------------------------
+
+
+use work.inline_20_types.all;
+
+architecture test of inline_20 is
+
+  signal start_flush, end_flush, DMA_buffer_full, DMA_buffer_empty : bit;
+
+begin
+
+  -- code from book:
+
+  DMA_buffer : entity work.FIFO
+    port map ( -- . . ., 
+               status.nearly_full => start_flush,
+               status.nearly_empty => end_flush,
+               status.full => DMA_buffer_full,
+               status.empty => DMA_buffer_empty, -- . . . );
+               -- not in book
+               other_ports => open );
+               -- end not in book
+
+  -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd
new file mode 100644
index 0000000..d760218
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_21.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book:
+
+entity and_gate is
+  port ( i : in bit_vector;  y : out bit );
+end entity and_gate;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture behavioral of and_gate is
+begin
+
+  reducer : process (i) is
+    constant Tpd : delay_length := 2 ns;
+    variable result : bit;
+  begin
+    result := '1';
+    for index in i'range loop
+      result := result and i(index);
+    end loop;
+    y <= result after Tpd;
+  end process reducer;
+
+end architecture behavioral;
+
+
+----------------------------------------------------------------
+
+
+entity inline_21 is
+
+end entity inline_21;
+
+
+----------------------------------------------------------------
+
+
+library util;  use util.stimulus_generators.all;
+
+architecture test of inline_21 is
+
+  -- code from book:
+
+  signal serial_select, write_en, bus_clk, serial_wr : bit;
+
+  -- end of code from book
+
+  signal test_input : bit_vector(2 downto 0);
+
+begin
+
+  -- code from book:
+
+  serial_write_gate : entity work.and_gate
+    port map ( i(1) => serial_select,
+               i(2) => write_en,
+               i(3) => bus_clk,
+               y => serial_wr );
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : all_possible_values( bv => test_input,
+                                  delay_between_values => 10 ns );
+
+  (serial_select, write_en, bus_clk) <= test_input;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd
new file mode 100644
index 0000000..bcdf9bd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_22.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book:
+
+entity mux4 is
+  port ( i0, i1, i2, i3, sel0, sel1 : in bit;
+         z : out bit );
+end entity mux4;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture functional of mux4 is
+begin
+
+  out_select : process (sel0, sel1, i0, i1, i2, i3) is
+    subtype bits_2 is bit_vector(1 downto 0);
+  begin
+    case bits_2'(sel1, sel0) is
+      when "00" =>  z <= i0;
+      when "01" =>  z <= i1;
+      when "10" =>  z <= i2;
+      when "11" =>  z <= i3;
+    end case;
+  end process out_select;
+
+end architecture functional;
+
+
+----------------------------------------------------------------
+
+
+entity inline_22 is
+
+end entity inline_22;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_22 is
+
+  signal select_line, line0, line1, result_line : bit;
+
+begin
+
+
+  -- code from book:
+
+  a_mux : entity work.mux4
+    port map ( sel0 => select_line, i0 => line0, i1 => line1,
+               z => result_line,
+               sel1 => '0', i2 => '1', i3 => '1' );
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    wait for 5 ns;
+    line0 <= '1';				wait for 5 ns;
+    line1 <= '1';				wait for 5 ns;
+    			select_line <= '1';	wait for 5 ns;
+    line1 <= '0';				wait for 5 ns;
+    line0 <= '0';				wait for 5 ns;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd
new file mode 100644
index 0000000..3f9ebc5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_23.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book:
+
+entity and_or_inv is
+  port ( a1, a2, b1, b2 : in bit := '1';
+         y : out bit );
+end entity and_or_inv;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture functional of and_or_inv is
+begin
+
+  func : y <= not ((a1 and a2) or (b1 and b2));
+
+end architecture functional;
+
+
+----------------------------------------------------------------
+
+
+entity inline_23 is
+
+end entity inline_23;
+
+
+----------------------------------------------------------------
+
+
+library util;  use util.stimulus_generators.all;
+
+architecture test of inline_23 is
+
+  signal A, B, C, F : bit;
+  signal test_input : bit_vector(2 downto 0);
+
+begin
+
+
+  -- code from book:
+
+  f_cell : entity work.and_or_inv
+    port map ( a1 => A, a2 => B, b1 => C, b2 => open, y => F );
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : all_possible_values( bv => test_input,
+				  delay_between_values => 10 ns );
+
+  (A, B, C) <= test_input;
+
+  verifier :
+    postponed assert F = not ((A and B) or C)
+      report "function model produced unexpected result";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd
new file mode 100644
index 0000000..b3658c0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_24.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book:
+
+entity and3 is
+  port ( a, b, c : in bit := '1';
+         z, not_z : out bit);
+end entity and3;
+
+-- end of code from book
+
+
+----------------------------------------------------------------
+
+
+architecture functional of and3 is
+begin
+
+  non_inverting:
+    z <= a and b and c;
+
+  inverting:
+    not_z <= not (a and b and c);
+
+end architecture functional;
+
+
+----------------------------------------------------------------
+
+
+entity inline_24 is
+
+end entity inline_24;
+
+
+----------------------------------------------------------------
+
+
+library util;  use util.stimulus_generators.all;
+
+architecture test of inline_24 is
+
+  signal s1, s2, ctrl1_a, ctrl1_b : bit;
+  signal test_input : bit_vector(1 to 2);
+
+begin
+
+
+  block_4_a : block is
+    port ( ctrl1 : out bit );
+    port map ( ctrl1 => ctrl1_a );
+  begin
+
+    -- code from book:
+
+    g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1 );
+
+    -- end of code from book
+
+  end block block_4_a;
+
+
+  ----------------
+
+
+  block_4_b : block is
+    port ( ctrl1 : out bit );
+    port map ( ctrl1 => ctrl1_b );
+  begin
+
+    -- code from book:
+
+    g1 : entity work.and3 port map ( a => s1, b => s2, not_z => ctrl1,
+                                     c => open, z => open );
+
+    -- end of code from book
+
+  end block block_4_b;
+
+
+  ----------------
+
+
+  stimulus : all_possible_values( bv => test_input,
+				  delay_between_values => 10 ns );
+
+  (s1, s2) <= test_input;
+
+  verifier :
+    assert ctrl1_a = ctrl1_b
+      report "versions differ";
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd
new file mode 100644
index 0000000..d0f0b21
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/inline_28a.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_28a is
+
+end entity inline_28a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_28a is
+
+  quantity disp : real;
+  constant min_high : real := 2.5;
+
+begin
+
+
+  process_3_h : process is
+  begin
+
+    -- code from book:
+
+    wait until disp'above(min_high) for 2.0;
+
+    -- end of code from book
+
+    wait;
+  end process process_3_h;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd
new file mode 100644
index 0000000..14bf0b9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/microprocessor.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity reg is
+  port ( d : in bit_vector(7 downto 0);
+         q : out bit_vector(7 downto 0);
+         clk : in bit );
+end entity reg;
+
+--------------------------------------------------
+
+-- not in book
+
+entity microprocessor is
+end entity microprocessor;
+
+-- end not in book
+
+architecture RTL of microprocessor is
+
+  signal interrupt_req : bit;
+  signal interrupt_level : bit_vector(2 downto 0);
+  signal carry_flag, negative_flag, overflow_flag, zero_flag : bit;
+  signal program_status : bit_vector(7 downto 0);
+  signal clk_PSR : bit;
+  -- . . .
+
+begin
+
+  PSR : entity work.reg
+    port map ( d(7) => interrupt_req,
+               d(6 downto 4) => interrupt_level,
+               d(3) => carry_flag,     d(2) => negative_flag,
+               d(1) => overflow_flag,  d(0) => zero_flag,
+               q => program_status,
+               clk => clk_PSR );
+  -- . . .
+
+end architecture RTL;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd
new file mode 100644
index 0000000..7baf357
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux.vhd
@@ -0,0 +1,68 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity mux is
+end entity mux;
+
+architecture test of mux is
+
+  constant prop_delay : time := 5 ns;
+
+  signal a, b, sel, z : bit;
+
+begin
+
+  -- code from book
+
+  mux : process (a, b, sel) is
+  begin
+    case sel is
+      when '0' =>
+	z <= a after prop_delay;
+      when '1' =>
+	z <= b after prop_delay;
+    end case;
+  end process mux;
+
+  -- end code from book
+
+
+  stimulus : process is
+    subtype stim_vector_type is bit_vector(0 to 3);
+    type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+    constant stim_vector : stim_vector_array
+      := ( "0000",
+	   "0010",
+           "0100",
+	   "0111",
+           "1001",
+	   "1010",
+           "1101",
+	   "1111" );
+  begin
+    for i in stim_vector'range loop
+      (a, b, sel) <= stim_vector(i)(0 to 2);
+      wait for 10 ns;
+      assert z = stim_vector(i)(3);
+    end loop;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd
new file mode 100644
index 0000000..2b3b0f1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity mux2 is
+  port ( a, b, sel : in bit;
+         z : out bit );
+end entity mux2;
+
+--------------------------------------------------
+
+architecture behavioral of mux2 is
+
+  constant prop_delay : time := 2 ns;
+
+begin
+
+  slick_mux : process is
+  begin
+    case sel is
+      when '0' =>
+        z <= a after prop_delay;
+        wait on sel, a;
+      when '1' =>
+        z <= b after prop_delay;
+        wait on sel, b;
+    end case;
+  end process slick_mux;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd
new file mode 100644
index 0000000..34d3d35
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/program_rom.vhd
@@ -0,0 +1,43 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+-- end not in book
+
+
+entity program_ROM is
+  port ( address : in std_ulogic_vector(14 downto 0);
+         data : out std_ulogic_vector(7 downto 0);
+         enable : in std_ulogic );
+
+  subtype instruction_byte is bit_vector(7 downto 0);
+  type program_array is array (0 to 2**14 - 1) of instruction_byte;
+  constant program : program_array
+    := ( X"32", X"3F", X"03",  -- LDA  $3F03
+         X"71", X"23",         -- BLT    $23
+         -- not in book
+         others => X"00"
+         -- end not in book
+         -- . . .
+       );
+
+end entity program_ROM;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd
new file mode 100644
index 0000000..4451f4f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity reg4 is
+  port ( clk, clr, d0, d1, d2, d3 : in bit;
+         q0, q1, q2, q3 : out bit );
+end entity reg4;
+
+----------------------------------------------
+
+architecture struct of reg4 is
+begin
+
+  bit0 : entity work.edge_triggered_Dff(behavioral)
+    port map (d0, clk, clr, q0);
+  bit1 : entity work.edge_triggered_Dff(behavioral)
+    port map (d1, clk, clr, q1);
+  bit2 : entity work.edge_triggered_Dff(behavioral)
+    port map (d2, clk, clr, q2);
+  bit3 : entity work.edge_triggered_Dff(behavioral)
+    port map (d3, clk, clr, q3);
+
+end architecture struct;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd
new file mode 100644
index 0000000..9c1165b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/rom.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity ROM is
+  port ( address : in natural;
+         data : out bit_vector(0 to 7);
+         enable : in bit );
+
+begin
+
+  trace_reads : process (enable) is
+  begin
+    if enable = '1' then
+      report "ROM read at time " & time'image(now)
+             & " from address " & natural'image(address);
+    end if;
+  end process trace_reads;
+
+end entity ROM;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd
new file mode 100644
index 0000000..9309901
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/scheduler.vhd
@@ -0,0 +1,108 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity scheduler is
+end entity scheduler;
+
+
+architecture test of scheduler is
+
+  constant scheduling_delay : delay_length := 5 ns;
+
+  subtype request_type is natural range 0 to 20;
+  type server_status_type is (ready, busy);
+
+  signal first_priority_request,
+         first_normal_request,
+         reset_request : request_type := 0;
+  signal functional_request, equivalent_request : request_type;
+  signal priority_waiting : boolean := false;
+  signal server_status : server_status_type := busy;
+
+begin
+
+  functional_scheduler : block is
+    port ( request : out request_type );
+    port map ( request => functional_request );
+  begin
+
+    -- code from book
+
+    scheduler :
+      request <= first_priority_request after scheduling_delay
+                   when priority_waiting and server_status = ready else
+                 first_normal_request after scheduling_delay
+                   when not priority_waiting and server_status = ready else
+                 unaffected
+                   when server_status = busy else
+                 reset_request after scheduling_delay;
+
+    -- end code from book
+
+  end block functional_scheduler;
+
+  --------------------------------------------------
+
+  equivalent_scheduler : block is
+    port ( request : out request_type );
+    port map ( request => equivalent_request );
+  begin
+
+    -- code from book
+
+    scheduler : process is
+    begin
+      if priority_waiting and server_status = ready then
+        request <= first_priority_request after scheduling_delay;
+      elsif not priority_waiting and server_status = ready then
+        request <= first_normal_request after scheduling_delay;
+      elsif server_status = busy then
+        null;
+      else
+        request <= reset_request after scheduling_delay;
+      end if;
+      wait on first_priority_request, priority_waiting, server_status,
+              first_normal_request, reset_request;
+    end process scheduler;
+
+    -- end code from book
+
+  end block equivalent_scheduler;
+
+  --------------------------------------------------
+
+  stimulus : process is
+  begin
+    first_priority_request <= 10;	wait for 20 ns;
+    first_normal_request <= 5;		wait for 20 ns;
+    server_status <= ready;		wait for 20 ns;
+    server_status <= busy;		wait for 20 ns;
+    priority_waiting <= true;		wait for 20 ns;
+    server_status <= ready;		wait for 20 ns;
+    first_normal_request <= 7;		wait for 20 ns;
+    first_priority_request <= 12;	wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  verifier :
+  assert functional_request = equivalent_request
+    report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd
new file mode 100644
index 0000000..0c747f6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop-1.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+architecture functional of S_R_flipflop is
+
+begin
+
+  q <= '1' when s = '1' else
+       '0' when r = '1';
+
+  q_n <= '0' when s = '1' else
+         '1' when r = '1';
+
+end architecture functional;
+
+
+entity tb_S_R_flipflop is
+end entity tb_S_R_flipflop;
+
+
+architecture test of tb_S_R_flipflop is
+
+  signal s, r : bit := '0';
+  signal q, q_n : bit;
+
+begin
+
+  dut : entity work.S_R_flipflop(functional)
+    port map ( s => s, r => r, q => q, q_n => q_n );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd
new file mode 100644
index 0000000..b694ff1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_S_R_flipflop.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_S_R_flipflop is
+end entity tb_S_R_flipflop;
+
+
+architecture test of tb_S_R_flipflop is
+
+  signal s, r : bit := '0';
+  signal q, q_n : bit;
+
+begin
+
+  dut : entity work.S_R_flipflop(functional)
+    port map ( s => s, r => r, q => q, q_n => q_n );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+    s <= '1';	wait for 10 ns;
+    r <= '1';	wait for 10 ns;
+    s <= '0';	wait for 10 ns;
+    r <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd
new file mode 100644
index 0000000..f1da3ee
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and2.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_and2 is
+end entity tb_and2;
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of tb_and2 is
+
+  signal a, b : std_ulogic := '0';
+  signal y : std_ulogic;
+
+begin
+
+  dut : entity work.and2(detailed_delay)
+    port map ( a => a, b => b, y => y );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    a <= '1';	wait for 10 ns;
+    b <= '1';	wait for 10 ns;
+    b <= '0';	wait for 10 ns;
+
+    b <= '1', '0' after  250 ps;   wait for 10 ns;
+    b <= '1', '0' after  350 ps;   wait for 10 ns;
+    b <= '1', '0' after  450 ps;   wait for 10 ns;
+    b <= '1', '0' after  550 ps;   wait for 10 ns;
+    b <= '1', '0' after  650 ps;   wait for 10 ns;
+    b <= '1', '0' after  750 ps;   wait for 10 ns;
+    b <= '1', '0' after  850 ps;   wait for 10 ns;
+
+    b <= '1';	wait for 10 ns;
+    b <= '0', '1' after  250 ps;   wait for 10 ns;
+    b <= '0', '1' after  350 ps;   wait for 10 ns;
+    b <= '0', '1' after  450 ps;   wait for 10 ns;
+
+    b <= 'X';  wait for 10 ns;
+    b <= '0';  wait for 10 ns;
+    b <= 'X', '0' after 250 ps;   wait for 10 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd
new file mode 100644
index 0000000..3d2cb6a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_and_or_inv.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_and_or_inv is
+end entity tb_and_or_inv;
+
+
+architecture test of tb_and_or_inv is
+
+  signal a1, a2, b1, b2, y : bit;
+
+begin
+
+  dut : entity work.and_or_inv(primitive)
+    port map ( a1 => a1, a2 => a2, b1 => b1, b2 => b2,
+	       y => y );
+
+  stimulus : process is
+    subtype stim_vector_type is bit_vector(0 to 3);
+    type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+    constant stim_vector : stim_vector_array
+      := ( "0000",
+	   "0001",
+	   "0010",
+	   "0011",
+           "0100",
+	   "0101",
+	   "0110",
+	   "0111",
+           "1000",
+	   "1001",
+	   "1010",
+	   "1011",
+           "1100",
+	   "1101",
+	   "1110",
+	   "1111" );
+  begin
+    for i in stim_vector'range loop
+      (a1, a2, b1, b2) <= stim_vector(i);
+      wait for 10 ns;
+      assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1))
+	               or (stim_vector(i)(2) and stim_vector(i)(3)) );
+    end loop;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd
new file mode 100644
index 0000000..31fb9c0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_counter.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_counter is
+end entity tb_counter;
+
+
+use work.counter_types.all;
+
+architecture test of tb_counter is
+
+  signal clk, clr : bit := '0';
+  signal q0, q1 : digit;
+
+begin
+
+  dut : entity work.counter(registered)
+    port map ( clk => clk, clr => clr,
+               q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 20 ns;
+
+  clr_gen : clr <= '1' after 95 ns,
+		   '0' after 135 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd
new file mode 100644
index 0000000..725520a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_edge_triggered_Dff.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_edge_triggered_Dff is
+end entity tb_edge_triggered_Dff;
+
+
+architecture test of tb_edge_triggered_Dff is
+
+  signal D, clk, clr, Q : bit := '0';
+
+begin
+
+  dut : entity work.edge_triggered_Dff(behavioral)
+    port map ( D => D, clk => clk, clr => clr,
+	       Q => Q );
+
+  stimulus : process is
+  begin
+    D <= '1';	wait for 10 ns;
+    clk <= '1';	wait for 10 ns;
+    D <= '0';	wait for 10 ns;
+    clk <= '0';	wait for 10 ns;
+    D <= '1';	wait for 10 ns;
+    clr <= '1';	wait for 10 ns;
+    clk <= '1';	wait for 10 ns;
+    clr <= '0';	wait for 10 ns;
+    clk <= '0';	wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd
new file mode 100644
index 0000000..f4f8c00
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_full_adder.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_full_adder is
+end entity tb_full_adder;
+
+
+library util;  use util.stimulus_generators.all;
+
+architecture test of tb_full_adder is
+
+  signal a, b, c_in, s, c_out : bit;
+  signal test_vector : bit_vector(1 to 3);
+
+begin
+
+  dut : entity work.full_adder
+    port map ( a => a, b => b, c_in => c_in, s => s, c_out => c_out );
+
+  all_possible_values ( test_vector, 10 ns );
+
+  (a, b, c_in) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd
new file mode 100644
index 0000000..e7bd163
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_mux2.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_mux2 is
+end entity tb_mux2;
+
+architecture test of tb_mux2 is
+
+  signal a, b, sel, z : bit;
+
+begin
+
+  dut : entity work.mux2(behavioral)
+    port map ( a => a, b => b, sel => sel, z => z );
+
+  stimulus : process is
+    subtype stim_vector_type is bit_vector(0 to 3);
+    type stim_vector_array is array ( natural range <> ) of stim_vector_type;
+    constant stim_vector : stim_vector_array
+      := ( "0000",
+           "0100",
+           "1001",
+           "1101",
+	   "0010",
+	   "0111",
+	   "1010",
+	   "1111" );
+  begin
+    for i in stim_vector'range loop
+      (a, b, sel) <= stim_vector(i)(0 to 2);
+      wait for 10 ns;
+      assert z = stim_vector(i)(3);
+    end loop;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd
new file mode 100644
index 0000000..d05be9c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_reg4.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_reg4 is
+end entity tb_reg4;
+
+
+architecture test of tb_reg4 is
+
+  signal clk, clr, d0, d1, d2, d3 : bit := '0';
+  signal q0, q1, q2, q3 : bit;
+
+begin
+
+  dut : entity work.reg4(struct)
+    port map ( clk => clk, clr => clr,
+	       d0 => d0, d1 => d1, d2 => d2, d3 => d3,
+	       q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
+
+  stimulus : process is
+  begin
+    (d3, d2, d1, d0) <= bit_vector'(b"1010");	wait for 10 ns;
+    clk <= '1';					wait for 10 ns;
+    (d3, d2, d1, d0) <= bit_vector'(b"0101");	wait for 10 ns;
+    clk <= '0';					wait for 10 ns;
+    (d3, d2, d1, d0) <= bit_vector'(b"1111");	wait for 10 ns;
+    clr <= '1';					wait for 10 ns;
+    clk <= '1';					wait for 10 ns;
+    clr <= '0';					wait for 10 ns;
+    clk <= '0';					wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd
new file mode 100644
index 0000000..d69e8b7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/tb_rom.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+architecture do_nothing of ROM is
+begin
+end architecture do_nothing;
+
+
+entity tb_rom is
+end entity tb_rom;
+
+
+architecture test of tb_rom is
+
+  signal address : natural := 0;
+  signal data : bit_vector(0 to 7);
+  signal enable : bit := '0';
+
+begin
+
+  dut : entity work.ROM(do_nothing)
+    port map ( address => address, data => data, enable => enable );
+
+  stimulus : process is
+  begin
+    wait for 100 ns;
+    address <= 1000;  wait for 10 ns;
+    enable <= '1', '0' after 10 ns;  wait for 90 ns;
+    address <= 1004;  wait for 10 ns;
+    enable <= '1', '0' after 10 ns;  wait for 90 ns;
+    address <= 1008;  wait for 10 ns;
+    enable <= '1', '0' after 10 ns;  wait for 90 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd
new file mode 100644
index 0000000..a42ae12
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux-1.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity zmux is
+end entity zmux;
+
+
+library util;  use util.stimulus_generators.all;
+
+architecture test of zmux is
+
+  signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
+  signal functional_z, equivalent_z : bit;
+
+begin
+
+  functional_mux : block is
+    port ( z : out bit );
+    port map ( z => functional_z );
+  begin
+
+    -- code from book
+
+    zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
+                d1 when sel1 = '0' and sel0 = '1' else
+                d2 when sel1 = '1' and sel0 = '0' else
+                d3;
+
+    -- end code from book
+
+  end block functional_mux;
+
+  --------------------------------------------------
+
+  equivalent_mux : block is
+    port ( z : out bit );
+    port map ( z => equivalent_z );
+  begin
+
+    -- code from book
+
+    zmux : process is
+    begin
+      if sel1 = '0' and sel0 = '0' then
+        z <= d0;
+      elsif sel1 = '0' and sel0 = '1' then
+        z <= d1;
+      elsif sel1 = '1' and sel0 = '0' then
+        z <= d2;
+      else
+        z <= d3;
+      end if;
+      wait on d0, d1, d2, d3, sel0, sel1;
+    end process zmux;
+
+    -- end code from book
+
+  end block equivalent_mux;
+
+  --------------------------------------------------
+
+  stimulus :
+    all_possible_values( bv(0) => sel0, bv(1) => sel1,
+			 bv(2) => d0, bv(3) => d1,
+			 bv(4) => d2, bv(5) => d3,
+			 delay_between_values => 10 ns );
+
+  verifier :
+  assert functional_z = equivalent_z
+    report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd
new file mode 100644
index 0000000..2f27a8c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/zmux.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity zmux is
+end entity zmux;
+
+
+library util;  use util.stimulus_generators.all;
+
+architecture test of zmux is
+
+  signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
+  signal functional_z, equivalent_z : bit;
+
+begin
+
+  functional_mux : block is
+    port ( z : out bit );
+    port map ( z => functional_z );
+  begin
+
+    -- code from book
+
+    zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
+                d1 when sel1 = '0' and sel0 = '1' else
+                d2 when sel1 = '1' and sel0 = '0' else
+                d3 when sel1 = '1' and sel0 = '1';
+
+    -- end code from book
+
+  end block functional_mux;
+
+  --------------------------------------------------
+
+  equivalent_mux : block is
+    port ( z : out bit );
+    port map ( z => equivalent_z );
+  begin
+
+    -- code from book
+
+    zmux : process is
+    begin
+      if sel1 = '0' and sel0 = '0' then
+        z <= d0;
+      elsif sel1 = '0' and sel0 = '1' then
+        z <= d1;
+      elsif sel1 = '1' and sel0 = '0' then
+        z <= d2;
+      elsif sel1 = '1' and sel0 = '1' then
+        z <= d3;
+      end if;
+      wait on d0, d1, d2, d3, sel0, sel1;
+    end process zmux;
+
+    -- end code from book
+
+  end block equivalent_mux;
+
+  --------------------------------------------------
+
+  stimulus :
+    all_possible_values( bv(0) => sel0, bv(1) => sel1,
+			 bv(2) => d0, bv(3) => d1,
+			 bv(4) => d2, bv(5) => d3,
+			 delay_between_values => 10 ns );
+
+  verifier :
+  assert functional_z = equivalent_z
+    report "Functional and equivalent models give different results";
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/CPU.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/CPU.vhd
new file mode 100644
index 0000000..59c5d45
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/CPU.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.numeric_bit.all;
+
+package CPU_types is
+
+  subtype word is unsigned(0 to 31);
+  subtype byte is unsigned(0 to 7);
+
+  alias convert_to_natural is
+    to_integer [ unsigned return natural ];
+
+  constant halt_opcode : byte := "00000000";
+
+  type code_array is array (natural range <>) of word;
+  constant code : code_array := ( X"01000000", X"01000000", X"02000000",
+				  X"01000000", X"01000000", X"02000000",
+				  X"00000000" );
+
+end package CPU_types;
+
+
+
+use work.CPU_types.all;
+
+entity CPU is
+end entity CPU;
+
+
+-- code from book
+
+architecture instrumented of CPU is
+
+  type count_file is file of natural;
+  file instruction_counts : count_file open write_mode is "instructions";
+
+begin
+
+  interpreter : process is
+
+    variable IR : word;
+    alias opcode : byte is IR(0 to 7);
+    variable opcode_number : natural;
+    type counter_array is array (0 to 2**opcode'length - 1) of natural;
+    variable counters : counter_array := (others => 0);
+    -- . . .
+
+    -- not in book
+    variable code_index : natural := 0;
+    -- end not in book
+
+  begin
+
+    -- . . .    -- initialize the instruction set interpreter
+
+    instruction_loop : loop
+
+      -- . . .    -- fetch the next instruction into IR
+
+      -- not in book
+      IR := code(code_index);
+      code_index := code_index + 1;
+      -- end not in book
+
+      -- decode the instruction
+      opcode_number := convert_to_natural(opcode);
+      counters(opcode_number) := counters(opcode_number) + 1;
+      -- . . .
+
+      -- execute the decoded instruction
+      case opcode is
+        -- . . .
+        when halt_opcode => exit instruction_loop;
+        -- . . .
+        -- not in book
+        when others => null;
+        -- end not in book
+      end case;
+
+    end loop instruction_loop;
+
+    for index in counters'range loop
+      write(instruction_counts, counters(index));
+    end loop;
+    wait;  -- program finished, wait forever
+
+  end process interpreter;
+
+end architecture instrumented;
+
+-- code from book
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/ROM.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/ROM.vhd
new file mode 100644
index 0000000..8d033db
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/ROM.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity ROM is
+  generic ( load_file_name : string );
+  port ( sel : in std_logic;
+         address : in std_logic_vector;
+         data : inout std_logic_vector );
+end entity ROM;
+
+--------------------------------------------------
+
+architecture behavioral of ROM is
+
+begin
+
+  behavior : process is
+
+    subtype word is std_logic_vector(0 to data'length - 1);
+    type storage_array is
+      array (natural range 0 to 2**address'length - 1) of word;
+    variable storage : storage_array;
+    variable index : natural;
+    -- . . .    -- other declarations
+
+    type load_file_type is file of word;
+    file load_file : load_file_type open read_mode is load_file_name;
+
+  begin
+
+    -- load ROM contents from load_file
+    index := 0;
+    while not endfile(load_file) loop
+      read(load_file, storage(index));
+      index := index + 1;
+    end loop;
+
+    -- respond to ROM accesses
+    loop
+      -- . . .
+    end loop;
+
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd
new file mode 100644
index 0000000..df3116c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity bus_monitor is
+end entity bus_monitor;
+
+
+
+architecture test of bus_monitor is
+
+  subtype byte is bit_vector(7 downto 0);
+  type byte_array is array (natural range <>) of byte;
+
+  function resolve_bytes ( drivers : in byte_array ) return byte is
+  begin
+    return drivers(drivers'left);
+  end function resolve_bytes;
+
+  function resolve_bits ( drivers : in bit_vector ) return bit is
+  begin
+    return drivers(drivers'left);
+  end function resolve_bits;
+
+  -- code from book (in text)
+
+  signal address : bit_vector(15 downto 0);
+  signal data : resolve_bytes byte;
+  signal rd, wr, io : bit;    -- read, write, io/mem select
+  signal ready : resolve_bits bit;
+
+  -- end code from book
+
+begin
+
+-- code from book
+
+bus_monitor : process is
+
+  constant header : string(1 to 44)
+    := FF & "      Time   R/W I/M  Address          Data";
+
+  use std.textio.all;
+
+  file log : text open write_mode is "buslog";
+  variable trace_line : line;
+  variable line_count : natural := 0;
+
+begin
+
+  if line_count mod 60 = 0 then
+    write ( trace_line, header );
+    writeline ( log, trace_line );
+    writeline ( log, trace_line );    -- empty line
+  end if;
+  wait until (rd = '1' or wr = '1') and ready = '1';
+  write ( trace_line, now, justified => right, field => 10, unit => us );
+  write ( trace_line, string'("    ") );
+  if rd = '1' then
+    write ( trace_line, 'R' );
+  else
+    write ( trace_line, 'W' );
+  end if;
+  write ( trace_line, string'("   ") );
+  if io = '1' then
+    write ( trace_line, 'I' );
+  else
+    write ( trace_line, 'M' );
+  end if;
+  write ( trace_line, string'("   ") );
+  write ( trace_line, address );
+  write ( trace_line, ' ');
+  write ( trace_line, data );
+  writeline ( log, trace_line );
+  line_count := line_count + 1;
+
+end process bus_monitor;
+
+-- end code from book
+
+  stimulus : process is
+  begin
+    wait for 0.4 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0000";
+    data <= B"10011110";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 0.9 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0001";
+    data <= B"00010010";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 2.0 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0014";
+    data <= B"11100111";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 2.7 us - now;
+    wr <= '1', '0' after 10 ns;
+    io <= '1', '0' after 10 ns;
+    address <= X"0007";
+    data <= X"00";
+    ready <= '1', '0' after 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd
new file mode 100644
index 0000000..b357670
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity cache is
+  generic ( cache_size, block_size, associativity : positive;
+            benchmark_name : string(1 to 10) );
+  port ( halt : in bit );
+end entity cache;
+
+
+
+architecture instrumented of cache is
+
+begin
+
+  -- code from book
+
+  cache_monitor : process is
+
+    type measurement_record is
+      record
+        cache_size, block_size, associativity : positive;
+        benchmark_name : string(1 to 10);
+        miss_rate : real;
+        ave_access_time : delay_length;
+      end record;
+    type measurement_file is file of measurement_record;
+    file measurements : measurement_file
+      open append_mode is "cache-measurements";
+    -- . . .
+
+    -- not in book
+    constant miss_count : natural := 100;
+    constant total_accesses : natural := 1000;
+    constant total_delay : delay_length := 2400 ns;
+    -- end not in book
+
+  begin
+    -- . . .
+    loop
+      -- . . .
+      -- not in book
+      wait on halt;
+      -- end not in book
+      exit when halt = '1';
+      -- . . .
+    end loop;
+
+    write ( measurements,
+            measurement_record'(
+              -- write values of generics for this run
+              cache_size, block_size, associativity, benchmark_name,
+              -- calculate performance metrics
+              miss_rate => real(miss_count) / real(total_accesses),
+              ave_access_time => total_delay / total_accesses ) );
+    wait;
+
+  end process cache_monitor;
+
+  -- end code from book
+
+end architecture instrumented;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/index-ams.txt
new file mode 100644
index 0000000..2a5e797
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/index-ams.txt
@@ -0,0 +1,38 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                       Chapter 21 - Files and Input/Output
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+ROM.vhd                                         entity ROM                              behavioral                      Figure 21-1
+stimulate_network.vhd                           entity stimulate_network_write_data     writer                          --
+--                                              entity stimulate_network                test                            Figure 21-2
+CPU.vhd                                         package CPU_types                       --                              --
+--                                              entity CPU                              instrumented                    Figure 21-3
+cache.vhd                                       entity cache                            instrumented                    Figure 21-4
+read_array.vhd                                  entity read_array_write_data            writer                          --
+--                                              entity read_array                       test                            Section 21.1, Figure 21-5
+stimulus_generator.vhd                          entity stimulus_generator               test                            Figure 21-6
+read_transform.vhd                              entity read_transform_write_data        writer                          --
+--                                              entity read_transform                   test                            Section 21.1, Figure 21-7
+textio.vhd                                      package textio                          --                              Figure 21-8
+stimulus_interpreter-1.vhd                      entity stimulus_interpreter             test                            Figure 21-9
+bus_monitor.vhd                                 entity bus_monitor                      test                            Figure 21-10
+inline_01.vhd                                   entity inline_01                        test                            Section 21.1
+inline_02.vhd                                   entity inline_02_write_data             writer                          --
+--                                              entity inline_02                        test                            Section 21.1
+inline_03.vhd                                   entity inline_03                        test                            Section 21.1
+inline_04.vhd                                   entity inline_04                        test                            Section 21.1
+inline_05.vhd                                   entity inline_05                        test                            Section 21.1
+inline_06.vhd                                   entity inline_06                        test                            Section 21.1
+inline_08.vhd                                   entity inline_08                        test                            Section 21.2
+inline_09.vhd                                   entity inline_09                        test                            Section 21.2
+inline_10.vhd                                   entity inline_10                        test                            Section 21.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_ROM.vhd                                      entity tb_ROM_write_data                writer                          --
+--                                              entity tb_ROM                           test                            ROM.vhd
+tb_cache.vhd                                    entity tb_cache                         test                            cache.vhd
+--                                              entity tb_cache_read_data               reader                          --
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd
new file mode 100644
index 0000000..3b7bf15
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+  process is
+
+    -- code from book:
+
+    type integer_file is file of integer;
+
+    file lookup_table_file : integer_file is "lookup-values";
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    -- code from book:
+
+    type file_open_kind is (read_mode, write_mode, append_mode);
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    type element_type is (t1, t2, t3);
+
+    -- code from book:
+
+    type file_type is file of element_type;
+
+    procedure read ( file f : file_type;  value : out element_type );
+
+    function endfile ( file f : file_type ) return boolean;
+
+    -- end of code from book
+
+    procedure read ( file f : file_type;  value : out element_type ) is
+    begin
+    end;
+
+    function endfile ( file f : file_type ) return boolean is
+    begin
+    end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_02.vhd
new file mode 100644
index 0000000..f31a157
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_02.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02_write_data is
+end entity inline_02_write_data;
+
+
+architecture writer of inline_02_write_data is
+begin
+
+  process is
+    type bit_vector_file is file of bit_vector;
+    file vectors : bit_vector_file open write_mode is "vectors.dat";
+  begin
+    write(vectors, bit_vector'(""));
+    write(vectors, bit_vector'("1"));
+    write(vectors, bit_vector'("10"));
+    write(vectors, bit_vector'("011"));
+    write(vectors, bit_vector'("0100"));
+    write(vectors, bit_vector'("00101"));
+    write(vectors, bit_vector'("000110"));
+    write(vectors, bit_vector'("0000111"));
+    write(vectors, bit_vector'("00001000"));
+    write(vectors, bit_vector'("111111111111111111111111111111111111111111111111111111111111111111111111"));
+    wait;
+  end process;
+
+end architecture writer;
+
+
+----------------------------------------------------------------
+
+
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+begin
+
+
+  process is
+
+   type element_type is (t1, t2, t3);
+   type file_type is file of element_type;
+
+    -- code from book:
+
+    type bit_vector_file is file of bit_vector;
+
+    procedure read ( file f : file_type;
+                     value : out element_type;  length : out natural );
+
+    -- end of code from book
+
+    procedure read ( file f : file_type;
+                     value : out element_type;  length : out natural ) is
+    begin
+    end;
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    type bit_vector_file is file of bit_vector;
+
+    -- code from book:
+
+    file vectors : bit_vector_file open read_mode is "vectors.dat";
+    variable next_vector : bit_vector(63 downto 0);
+    variable actual_len : natural;
+
+    -- end of code from book
+
+    variable lost : boolean;
+
+  begin
+    while not endfile(vectors) loop
+
+      -- code from book:
+
+      read(vectors, next_vector, actual_len);
+
+      -- end of code from book
+
+      lost :=
+      -- code from book:
+
+      actual_len > next_vector'length
+
+      -- end of code from book
+      ;
+
+    end loop;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_03.vhd
new file mode 100644
index 0000000..3813e24
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_03.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+begin
+
+
+  process is
+
+    type element_type is (t1, t2, t3);
+
+    type file_type is file of element_type;
+
+    -- code from book:
+
+    procedure write ( file f : file_type;  value : in element_type );
+
+    -- end of code from book
+
+    procedure write ( file f : file_type;  value : in element_type ) is
+    begin
+    end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_04.vhd
new file mode 100644
index 0000000..725af8a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_04.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_04 is
+
+end entity inline_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04 is
+begin
+
+
+  process is
+
+    type data_file_type is file of character;
+    variable ch : character;
+
+    -- code from book:
+
+    procedure write_to_file is
+      file data_file : data_file_type open write_mode is "datafile";
+    begin
+      -- . . .
+      -- not in book
+      write(data_file, ch);
+      -- end not in book
+    end procedure write_to_file;
+
+    -- end of code from book
+
+  begin
+    ch := 'A';
+    write_to_file;
+    ch := 'B';
+    write_to_file;
+    ch := 'C';
+    write_to_file;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_05.vhd
new file mode 100644
index 0000000..bcbe6bd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_05.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+  type log_file is file of string;
+
+  -- code from book:
+
+  file log_info : log_file open write_mode is "logfile";
+
+  -- end of code from book
+
+begin
+
+
+  process is
+  begin
+    write(log_info, string'("AAAA"));
+    wait for 1 ns;
+    write(log_info, string'("BBBB"));
+    wait;
+  end process;
+
+
+  process is
+  begin
+    write(log_info, string'("CCCC"));
+    wait for 1 ns;
+    write(log_info, string'("DDDD"));
+    wait;
+  end process;
+
+
+end architecture test;	  
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd
new file mode 100644
index 0000000..2086041
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd
@@ -0,0 +1,142 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+  type integer_file is file of integer;
+
+begin
+
+
+  process is
+
+    -- code from book:
+
+    file lookup_table_file, result_file : integer_file;
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    type element_type is (t1, t2, t3);
+
+    -- code from book:
+
+    type file_type is file of element_type;
+
+    procedure file_open ( file f : file_type;
+                          external_name : in string;
+                          open_kind : in file_open_kind := read_mode );
+
+    -- end of code from book
+
+    procedure file_open ( file f : file_type;
+                          external_name : in string;
+                          open_kind : in file_open_kind := read_mode ) is
+    begin
+    end;
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    -- code from book:
+
+    file lookup_table_file : integer_file open read_mode is "lookup-values";
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    -- code from book:
+
+    file lookup_table_file : integer_file;
+    -- . . .
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    file_open ( lookup_table_file,
+                external_name => "lookup-values", open_kind => read_mode );
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+  process is
+
+    type element_type is (t1, t2, t3);
+    type file_type is file of element_type;
+
+    -- code from book:
+
+    type file_open_status is (open_ok, status_error, name_error, mode_error);
+
+    procedure file_open ( status : out file_open_status;
+                          file f : file_type;
+                          external_name : in string;
+                          open_kind : in file_open_kind := read_mode );
+
+    procedure file_close ( file f : file_type );
+
+    -- end of code from book
+
+    procedure file_open ( status : out file_open_status;
+                          file f : file_type;
+                          external_name : in string;
+                          open_kind : in file_open_kind := read_mode ) is
+    begin
+    end;
+
+    procedure file_close ( file f : file_type ) is
+    begin
+    end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_08.vhd
new file mode 100644
index 0000000..e43c83f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_08.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_08 is
+begin
+
+
+  process is
+
+    use std.textio.all;
+    file f : text open read_mode is "inline_08.dat";
+    variable L : line;
+    variable ch : character;
+    variable s : string(1 to 5);
+    variable i : integer;
+    variable r : real;
+
+  begin
+
+    readline(f, L);
+    read(L, ch);
+    report character'image(ch);
+    read(L, ch);
+    report character'image(ch);
+
+    readline(f, L);
+    read(L, s);
+    report '"' & s & '"';
+    read(L, s);
+    report '"' & s & '"';
+
+    readline(f, L);
+
+    -- code from book:
+
+    if L'length < s'length then
+      read(L, s(1 to L'length));
+    else
+      read(L, s);
+    end if;
+
+    -- end of code from book
+
+    report '"' & s & '"';
+
+    readline(f, L);
+    read(L, i);
+    report integer'image(i);
+    read(L, r);
+    report real'image(r);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_09.vhd
new file mode 100644
index 0000000..f2cccc4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_09.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+begin
+
+
+  process is
+
+    use std.textio.all;
+    variable L : line;
+
+  begin
+
+    write(L, 42, justified => left, field => 5);
+    writeline(output, L);
+    write(L, 42, justified => right, field => 5);
+    writeline(output, L);
+    write(L, 123, field => 2);
+    writeline(output, L);
+
+    -- code from book:
+
+    write ( L, string'( "fred" ) );
+    write ( L, ' ' );
+    write ( L, bit_vector'( X"3A" ) );
+
+    -- end of code from book
+
+    writeline(output, L);
+
+    write(L, 3.14159, digits => 2);
+    writeline(output, L);
+    write(L, 123.4567, digits => 0);
+    writeline(output, L);
+
+    write(L, 40 ns, unit => ps);
+    writeline(output, L);
+    write(L, 23 us, unit => ms);
+    writeline(output, L);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_10.vhd
new file mode 100644
index 0000000..059075f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_10.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_10 is
+
+end entity inline_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_10 is
+begin
+
+
+  process is
+
+    use std.textio.all;
+    variable L : line;
+
+    -- code from book:
+
+    type speed_category is (stopped, slow, fast, maniacal);
+    variable speed : speed_category;
+
+    -- end of code from book
+
+  begin
+
+    speed := stopped;
+
+    -- code from book:
+
+    write ( L, speed_category'image(speed) );
+
+    -- end of code from book
+
+    writeline(output, L);
+
+    speed := slow;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+    speed := fast;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+    speed := maniacal;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+
+    -- code from book:
+
+    readline( input, L );
+    speed := speed_category'value(L.all);
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd
new file mode 100644
index 0000000..dbec796
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity read_array_write_data is
+end entity read_array_write_data;
+
+
+architecture writer of read_array_write_data is
+begin
+
+  process is
+
+    type integer_file is file of integer;
+    file data_file : integer_file open write_mode is "coeff-data";
+
+  begin
+    write(data_file, 0);
+    write(data_file, 1);
+    write(data_file, 2);
+    write(data_file, 3);
+    write(data_file, 4);
+    write(data_file, 5);
+    write(data_file, 6);
+    write(data_file, 7);
+    write(data_file, 8);
+    write(data_file, 9);
+    write(data_file, 10);
+    write(data_file, 11);
+    write(data_file, 12);
+    write(data_file, 13);
+    write(data_file, 14);
+    write(data_file, 15);
+    write(data_file, 16);
+    write(data_file, 17);
+    write(data_file, 18);
+
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+entity read_array is
+end entity read_array;
+
+
+architecture test of read_array is
+begin
+
+  process is
+
+    -- code from book (in text)
+
+    type integer_vector is array (integer range <>) of integer;
+
+    -- end code from book
+
+    -- code from book (in Figure)
+
+    impure function read_array ( file_name : string;  array_length : natural )
+                               return integer_vector is
+      type integer_file is file of integer;
+      file data_file : integer_file open read_mode is file_name;
+      variable result : integer_vector(1 to array_length) := (others => 0);
+      variable index : integer := 1;
+    begin
+      while not endfile(data_file) and index <= array_length loop
+        read(data_file, result(index));
+        index := index + 1;
+      end loop;
+      return result;
+    end function read_array;
+
+    -- end code from book
+
+    -- code from book (in text)
+
+    constant coeffs : integer_vector := read_array("coeff-data", 16);
+
+    -- end code from book
+
+  begin
+    wait;
+  end process;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_transform.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_transform.vhd
new file mode 100644
index 0000000..74f1d72
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_transform.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity read_transform_write_data is
+end entity read_transform_write_data;
+
+
+architecture writer of read_transform_write_data is
+begin
+
+  process is
+    type transform_file is file of real;
+    file initial_transforms : transform_file open write_mode is "transforms.ini";
+  begin
+    for i in 1 to 50 loop
+      write(initial_transforms, real(i));
+    end loop;
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+
+entity read_transform is
+end entity read_transform;
+
+
+architecture test of read_transform is
+begin
+
+  process is
+
+    -- code from book (in text)
+
+    type transform_array is array (1 to 3, 1 to 3) of real;
+    variable transform1, transform2 : transform_array;
+
+    type transform_file is file of real;
+    file initial_transforms : transform_file open read_mode is "transforms.ini";
+
+    -- end code from book
+
+    -- code from book (in Figure)
+
+    procedure read_transform ( file f : transform_file;
+                               variable transform : out transform_array ) is
+    begin
+      for i in transform'range(1) loop
+        for j in transform'range(2) loop
+          if endfile(f) then
+            report "unexpected end of file in read_transform - "
+                   & "some array elements not read"
+              severity error;
+            return;
+          end if;
+          read ( f, transform(i, j) );
+        end loop;
+      end loop;
+    end procedure read_transform;
+
+    -- end code from book
+
+  begin
+
+    -- code from book (in text)
+
+    read_transform ( initial_transforms, transform1 );
+    read_transform ( initial_transforms, transform2 );
+
+    -- end code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulate_network.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulate_network.vhd
new file mode 100644
index 0000000..a7e7184
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulate_network.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity stimulate_network_write_data is
+end entity stimulate_network_write_data;
+
+
+architecture writer of stimulate_network_write_data is
+begin
+
+  process is
+    type packet_file is file of bit_vector;
+    file stimulus_file : packet_file open write_mode is "test packets";
+  begin
+    write(stimulus_file, X"6C");
+    write(stimulus_file, X"05");
+    write(stimulus_file, X"3");
+
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+entity stimulate_network is
+end entity stimulate_network;
+
+
+architecture test of stimulate_network is
+
+  signal stimulus_network, stimulus_clock : bit;
+
+begin
+
+  clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
+
+  -- code from book
+
+  stimulate_network : process is
+
+    type packet_file is file of bit_vector;
+    file stimulus_file : packet_file open read_mode is "test packets";
+
+    -- variable packet : bit_vector(1 to 2048);
+    -- not in book (for testing only)
+    variable packet : bit_vector(1 to 8);
+    -- end not in book
+    variable packet_length : natural;
+
+  begin
+
+    while not endfile(stimulus_file) loop
+
+      read(stimulus_file, packet, packet_length);
+      if packet_length > packet'length then
+        report "stimulus packet too long - ignored" severity warning;
+      else
+        for bit_index in 1 to packet_length loop
+          wait until stimulus_clock = '1';
+          stimulus_network <= not stimulus_network;
+          wait until stimulus_clock = '0';
+          stimulus_network <= stimulus_network xor packet(bit_index);
+        end loop;
+      end if;
+
+    end loop;
+
+    wait;  -- end of stimulation: wait forever
+
+  end process stimulate_network;
+
+  -- code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_generator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_generator.vhd
new file mode 100644
index 0000000..0393ff7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_generator.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity stimulus_generator is
+end entity stimulus_generator;
+
+
+architecture test of stimulus_generator is
+
+
+
+begin
+
+  -- code from book
+
+  stimulus_generator : process is
+
+    type directory_file is file of string;
+    file directory : directory_file open read_mode is "stimulus-directory";
+    variable file_name : string(1 to 50);
+    variable file_name_length : natural;
+    variable open_status : file_open_status;
+
+    subtype stimulus_vector is std_logic_vector(0 to 9);
+    type stimulus_file is file of stimulus_vector;
+    file stimuli : stimulus_file;
+    variable current_stimulus : stimulus_vector;
+    -- . . .
+
+  begin
+    file_loop : while not endfile(directory) loop
+      read( directory, file_name, file_name_length );
+      if file_name_length > file_name'length then
+        report "file name too long: " & file_name & "... - file skipped"
+          severity warning;
+        next file_loop;
+      end if;
+      file_open ( open_status, stimuli,
+                  file_name(1 to file_name_length), read_mode );
+      if open_status /= open_ok then
+        report file_open_status'image(open_status) & " while opening file "
+               & file_name(1 to file_name_length) & " - file skipped"
+          severity warning;
+        next file_loop;
+      end if;
+      stimulus_loop : while not endfile(stimuli) loop
+        read(stimuli, current_stimulus);
+        -- . . .    -- apply the stimulus
+      end loop stimulus_loop;
+      file_close(stimuli);
+    end loop file_loop;
+    wait;
+  end process stimulus_generator;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_interpreter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_interpreter-1.vhd
new file mode 100644
index 0000000..138ece8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_interpreter-1.vhd
@@ -0,0 +1,150 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity stimulus_interpreter is
+end entity stimulus_interpreter;
+
+
+architecture test of stimulus_interpreter is
+
+  quantity temperature : real;
+  signal temp_sig, setting : real;
+  signal enable, heater_fail : bit;
+
+begin
+
+-- code from book
+
+stimulus_interpreter : process is
+
+  use std.textio.all;
+
+  file control : text open read_mode is "control";
+
+  variable command : line;
+  variable read_ok : boolean;
+  variable next_time : time;
+  variable whitespace : character;
+  variable signal_id : string(1 to 4);
+  variable temp_value, set_value : real;
+  variable on_value, fail_value : bit;
+
+begin
+
+  command_loop : while not endfile(control) loop
+
+    readline ( control, command );
+
+    -- read next stimulus time, and suspend until then
+    read ( command, next_time, read_ok );
+    if not read_ok then
+      report "error reading time from line: " & command.all
+        severity warning;
+      next command_loop;
+    end if;
+    wait for next_time - now;
+
+    -- skip whitespace
+    while command'length > 0
+      and ( command(command'left) = ' '    -- ordinary space
+            or command(command'left) = ' '  -- non-breaking space
+            or command(command'left) = HT ) loop
+      read ( command, whitespace );
+    end loop;
+
+    -- read signal identifier string
+    read ( command, signal_id, read_ok );
+    if not read_ok then
+      report "error reading signal id from line: " & command.all
+        severity warning;
+      next command_loop;
+    end if;
+    -- dispatch based on signal id
+    case signal_id is
+
+      when "temp" =>
+        read ( command, temp_value, read_ok );
+        if not read_ok then
+          report "error reading temperature value from line: "
+                 & command.all
+            severity warning;
+          next command_loop;
+        end if;
+        temp_sig <= temp_value;
+
+      when "set " =>
+        -- . . .    -- similar to "temp"
+
+        -- not in book
+        read ( command, set_value, read_ok );
+        if not read_ok then
+          report "error reading setting value from line: "
+                 & command.all
+            severity warning;
+          next command_loop;
+        end if;
+        setting <= set_value;
+        -- end not in book
+
+      when "on  " =>
+        read ( command, on_value, read_ok );
+        if not read_ok then
+          report "error reading on value from line: "
+                 & command.all
+            severity warning;
+          next command_loop;
+        end if;
+        enable <= on_value;
+
+      when "fail" =>
+        -- . . .    -- similar to "on  "
+
+        -- not in book
+        read ( command, fail_value, read_ok );
+        if not read_ok then
+          report "error reading fail value from line: "
+                 & command.all
+            severity warning;
+          next command_loop;
+        end if;
+        heater_fail <= fail_value;
+        -- end not in book
+
+      when others =>
+        report "invalid signal id in line: " & signal_id
+          severity warning;
+        next command_loop;
+
+    end case;
+
+  end loop command_loop;
+
+  wait;
+
+end process stimulus_interpreter;
+
+-- end code from book
+
+-- code from book (in text)
+
+temperature == temp_sig'ramp;
+
+-- end code from book (in text)
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_ROM.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_ROM.vhd
new file mode 100644
index 0000000..7aece5f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_ROM.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity tb_ROM_write_data is
+end entity tb_ROM_write_data;
+
+
+architecture writer of tb_ROM_write_data is
+begin
+
+  process is
+
+    subtype word is std_logic_vector(0 to 7);
+    type load_file_type is file of word;
+    file load_file : load_file_type open write_mode is "tb_ROM.dat";
+
+  begin
+    write(load_file, word'(X"00"));
+    write(load_file, word'(X"01"));
+    write(load_file, word'(X"02"));
+    write(load_file, word'(X"03"));
+    write(load_file, word'(X"04"));
+    write(load_file, word'(X"05"));
+    write(load_file, word'(X"06"));
+    write(load_file, word'(X"07"));
+    write(load_file, word'(X"08"));
+    write(load_file, word'(X"09"));
+    write(load_file, word'(X"0A"));
+    write(load_file, word'(X"0B"));
+    write(load_file, word'(X"0C"));
+    write(load_file, word'(X"0D"));
+    write(load_file, word'(X"0E"));
+    write(load_file, word'(X"0F"));
+
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity tb_ROM is
+end entity tb_ROM;
+
+
+architecture test of tb_ROM is
+
+  signal sel : std_logic;
+  signal address : std_logic_vector(3 downto 0);
+  signal data : std_logic_vector(0 to 7);
+
+begin
+
+  dut : entity work.ROM(behavioral)
+    generic map ( load_file_name => "tb_ROM.dat" )
+    port map ( sel, address, data );
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd
new file mode 100644
index 0000000..0759010
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_cache is
+end entity tb_cache;
+
+
+
+architecture test of tb_cache is
+
+  signal halt : bit := '0';
+
+begin
+
+  dut : entity work.cache(instrumented)
+    generic map ( cache_size => 128*1024, block_size => 16,
+                  associativity => 2, benchmark_name => "dhrystone " )
+    port map ( halt => halt );
+
+  halt <= '1' after 10 ns;
+
+end architecture test;
+
+
+
+entity tb_cache_read_data is
+end entity tb_cache_read_data;
+
+
+architecture reader of tb_cache_read_data is
+begin
+
+  process is
+
+    type measurement_record is
+      record
+        cache_size, block_size, associativity : positive;
+        benchmark_name : string(1 to 10);
+        miss_rate : real;
+        ave_access_time : delay_length;
+      end record;
+    type measurement_file is file of measurement_record;
+    file measurements : measurement_file open read_mode is "cache-measurements";
+    variable measurement : measurement_record;
+
+    use std.textio.all;
+    variable L : line;
+
+  begin
+    while not endfile(measurements) loop
+      read(measurements, measurement);
+      write(L, measurement.cache_size);
+      write(L, ' ');
+      write(L, measurement.block_size);
+      write(L, ' ');
+      write(L, measurement.associativity);
+      write(L, ' ');
+      write(L, measurement.benchmark_name);
+      write(L, ' ');
+      write(L, measurement.miss_rate);
+      write(L, ' ');
+      write(L, measurement.ave_access_time);
+      writeline(output, L);
+
+    end loop;
+
+    wait;
+  end process;
+
+end architecture reader;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/textio.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/textio.vhd
new file mode 100644
index 0000000..7b5cffe
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/textio.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package textio is
+
+  type line is access string;
+
+  type text is file of string;
+
+  type side is (right, left);
+
+  subtype width is natural;
+
+  file input : text open read_mode is "std_input";
+  file output : text open write_mode is "std_output";
+
+  -- use this declaration for VHDL-2001
+  procedure readline(file f: text; l: inout line);
+
+  -- use this declaration for VHDL-AMS
+  procedure readline(file f: text; l: out line);
+
+  procedure read ( L : inout line;  value: out bit;  good : out boolean );
+  procedure read ( L : inout line;  value: out bit );
+
+  procedure read ( L : inout line;  value: out bit_vector;  good : out boolean );
+  procedure read ( L : inout line;  value: out bit_vector );
+
+  procedure read ( L : inout line;  value: out boolean;  good : out boolean );
+  procedure read ( L : inout line;  value: out boolean );
+
+  procedure read ( L : inout line;  value: out character;  good : out boolean );
+  procedure read ( L : inout line;  value: out character );
+
+  procedure read ( L : inout line;  value: out integer;  good : out boolean );
+  procedure read ( L : inout line;  value: out integer );
+
+  procedure read ( L : inout line;  value: out real;  good : out boolean );
+  procedure read ( L : inout line;  value: out real );
+
+  procedure read ( L : inout line;  value: out string;  good : out boolean );
+  procedure read ( L : inout line;  value: out string );
+
+  procedure read ( L : inout line;  value: out time;  good : out boolean );
+  procedure read ( L : inout line;  value: out time );
+
+  procedure writeline ( file f : text;  L : inout line );
+
+  procedure write ( L : inout line;  value : in bit;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in bit_vector;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in boolean;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in character;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in integer;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in real;
+                    justified: in side := right;  field: in width := 0;
+                    digits: in natural := 0 );
+
+  procedure write ( L : inout line;  value : in string;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in time;
+                    justified: in side := right;  field: in width := 0;
+                    unit: in time := ns );
+
+end package textio;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/index-ams.txt
new file mode 100644
index 0000000..16e7ad5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/index-ams.txt
@@ -0,0 +1,36 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                              Chapter 13 - Frequency and Transfer Function Modeling
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+v_source.vhd                                    entity v_source                         behavior                        Figure 13-3
+v_source-1.vhd                                  entity v_source                         behavior                        Figure 13-4
+nmos_transistor.vhd                             entity NMOS_transistor                  noisy                           Figure 13-5
+nmos_transistor_wa.vhd                          entity nmos_transistor_wa               noisy                           --
+lowpass-1.vhd                                   entity resistor                         ideal                           --
+--                                              entity capacitor                        ideal                           --
+--                                              entity lowpass                          RC                              Figure 13-7
+lowpass-2.vhd                                   entity lowpass                          dot                             Figure 13-9
+lowpass-3.vhd                                   entity lowpass                          ltf                             Figure 13-11
+opamp.vhd                                       entity opamp                            slew_limited                    Figure 13-13
+opamp_2pole.vhd                                 entity opamp_2pole                      dot, ltf                        Figure 13-15
+opamp_2pole_res.vhd                             entity opamp_2pole_res                  ltf                             Figure 13-16
+lowpass-4.vhd                                   entity lowpass                          z_minus_1                       Figure 13-17
+lowpass-5.vhd                                   entity lowpass                          ztf                             Figure 13-19
+lowpass.vhd                                     entity lowpass                          RC, dot, ltf, z_minus_1, ztf    Figure 13-22
+inline_01a.vhd                                  entity inline_01a                       test                            Section 13.1
+inline_02a.vhd                                  entity inline_02a                       test                            Section 13.2
+inline_03a.vhd                                  entity inline_03a                       test                            Section 13.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_v_source.vhd                                 entity tb_v_source                      TB_v_source                     v_source.vhd
+tb_mosfet_noisy.vhd                             entity tb_mosfet_noisy                  TB_mosfet_noisy                 nmos_transistor_wa.vhd
+tb_opamp.vhd                                    entity tb_opamp                         TB_opamp                        opamp.vhd
+tb_opamp_2pole.vhd                              entity tb_opamp_2pole                   TB_opamp_2pole                  opamp_2pole.vhd
+tb_lpf_dot_ltf_ztf-1.vhd                        entity tb_lpf_dot_ltf_ztf               TB_lpf_dot_ltf_ztf              lowpass-1.vhd, lowpass-2.vhd,
+--                                                                                                                      lowpass-3.vhd, lowpass-4.vhd,
+--                                                                                                                      lowpass-5.vhd
+tb_lpf_dot_ltf_ztf.vhd                          entity tb_lpf_dot_ltf_ztf               TB_lpf_dot_ltf_ztf              lowpass.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd
new file mode 100644
index 0000000..c6e2a9c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_01a.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+library ieee;  use ieee.math_real.all;
+
+entity inline_01a is
+
+end entity inline_01a;
+
+
+architecture test of inline_01a is
+
+  function inverse_exp ( x : real ) return real is
+  begin
+    return 10.0 * exp(-2.0e-6 * x);
+  end function inverse_exp;
+
+  -- code from book
+
+  type domain_type is (quiescent_domain, time_domain, frequency_domain);
+
+  --
+
+  quantity spec_source : real spectrum 2.5, math_pi / 2.0;
+
+  --
+
+  function frequency return real;
+
+  --
+
+  quantity source1 : real spectrum inverse_exp(frequency), math_pi / 4.0;
+
+  --
+
+  quantity source2 : real spectrum 5.0, 1.0E-6 * frequency / math_pi;
+
+  -- end code from book
+
+  function frequency return real is
+  begin
+    return std.standard.frequency;
+  end function frequency;
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd
new file mode 100644
index 0000000..6864aaa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_02a.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+use ieee_proposed.energy_systems.all;
+
+
+entity inline_02a is
+
+end entity inline_02a;
+
+
+architecture test of inline_02a is
+
+  constant k_Boltzmann : real := K;
+  constant temp : real := 300.0;
+  constant res : real := 10_000.0;
+  terminal r_p1, r_p2 : electrical;
+  quantity resistor_voltage across resistor_current through r_p1 to r_p2;
+
+  constant k_noise : real := 1.0;
+
+  function G ( f : real ) return real is
+  begin
+    return 1.0;
+  end function G;
+
+  constant k_flicker : real := 1.0;
+  constant ids : real := 0.01;
+  constant af : real := 1.0;
+
+  -- code from book
+
+  quantity thermal_noise_source : real noise 4.0 * k_Boltzmann * temp * res;
+
+  --
+  
+  quantity shaped_noise_source : real noise k_noise * temp * G(frequency);
+  
+  --
+  
+  quantity flicker_noise_source : real noise k_flicker * ids**af / frequency;
+  
+  -- end code from book
+
+begin
+
+  -- code from book
+
+  resistor_voltage == resistor_current * res + thermal_noise_source;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd
new file mode 100644
index 0000000..e9889f0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/inline_03a.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+library ieee;  use ieee.math_real.all;
+               
+entity inline_03a is
+
+end entity inline_03a;
+
+
+architecture test of inline_03a is
+
+  -- code from book
+
+  constant fp : real := 10.0;            -- filter pole in hertz
+  constant wp : real := math_2_pi * fp;  -- filter pole in rad/s
+  constant tp : real := 1.0 / wp;        -- filter time constant
+
+  -- end code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd
new file mode 100644
index 0000000..c47c772
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-1.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+  generic ( res : resistance );
+  port ( terminal p1, p2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+  quantity v across i through p1 to p2;
+begin
+  v == i * res;
+end architecture ideal;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity capacitor is
+  generic ( cap : resistance );
+  port ( terminal p1, p2 : electrical );
+end entity capacitor;
+
+architecture ideal of capacitor is
+  quantity v across i through p1 to p2;
+begin
+  i == cap * v'dot;
+end architecture ideal;
+
+-- end not in book
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity lowpass is
+  port ( terminal input : electrical;
+         terminal output : electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture RC of lowpass is
+begin
+
+  R : entity work.resistor(ideal)
+    generic map ( res => 15.9e3 )
+    port map ( p1 => input, p2 => output );
+
+  C : entity work.capacitor(ideal)
+    generic map ( cap => 1.0e-6 )
+    port map ( p1 => output, p2 => electrical_ref );
+
+end architecture RC;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd
new file mode 100644
index 0000000..5162470
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-2.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity lowpass is
+  port ( terminal input : electrical;
+         terminal output : electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture dot of lowpass is
+
+  quantity vin across input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+  constant tp : real := 15.9e-3;  -- filter time constant
+
+begin
+
+  vin == vout + tp * vout'dot;
+
+end architecture dot; 
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd
new file mode 100644
index 0000000..9a1cbfa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-3.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+library ieee;  use ieee.math_real.all;
+
+entity lowpass is
+  port ( terminal input : electrical;
+         terminal output : electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture ltf of lowpass is
+
+  quantity vin across input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+  constant wp : real := 10.0 * math_2_pi;   -- pole in rad/s
+  constant num : real_vector := (0 => wp);  -- numerator in s
+  constant den : real_vector := (wp, 1.0);  -- denominator in s
+  
+begin
+
+  vout == vin'ltf(num, den);
+
+end architecture ltf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd
new file mode 100644
index 0000000..666d100
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-4.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity lowpass is
+  generic ( fp : real := 10.0;	      -- pole in Hz for 'zoh, 'delayed
+            Fsmp : real := 10.0e3 );  -- sample frequency for 'zoh, 'delayed
+  port ( terminal input : electrical;
+         terminal output: electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture z_minus_1 of lowpass is
+
+  quantity vin across input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+  quantity vin_sampled : real;		  -- discrete sample of input quantity
+  quantity vin_zm1, vout_zm1 : real; 	  -- z**-1 
+  constant Tsmp : real := 1.0 / Fsmp;	  -- sample period
+  constant wp : real := fp * math_2_pi;   -- pole in rad/s
+  constant n0 : real := Tsmp * wp;        -- z0 numerator coefficient
+  constant n1 : real := Tsmp * wp;        -- z-1 numerator coefficient
+  constant d0 : real := Tsmp * wp + 2.0;  -- z0 denominator coefficient
+  constant d1 : real := Tsmp * wp - 2.0;  -- z-1 denominator coefficient
+
+begin
+
+  vin_sampled  == vin'zoh(Tsmp);
+
+  vin_zm1  == vin_sampled'delayed(Tsmp);
+
+  vout_zm1 == vout'delayed(Tsmp);
+
+  vout == vin_sampled * n0 / d0 + n1 * vin_zm1 / d0 - d1 * vout_zm1 / d0;
+
+end z_minus_1;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd
new file mode 100644
index 0000000..d1f655c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass-5.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity lowpass is
+  generic ( fp : real := 10.0;	     -- pole in Hz for 'ztf
+            Fsmp : real := 10.0e3);  -- sample frequency for 'ztf 
+  port ( terminal input: electrical;
+         terminal output: electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture ztf of lowpass is
+
+  quantity vin across input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+  constant Tsmp : real := 1.0 / Fsmp;	  -- sample period
+  constant wp : real := fp * math_2_pi;	  -- pole in rad/s
+  constant n0 : real := Tsmp * wp; 	  -- z0 numerator coefficient (a)
+  constant n1 : real := Tsmp * wp; 	  -- z-1 numerator coefficient (b)
+  constant d0 : real := Tsmp * wp + 2.0;  -- z0 denominator coefficient (c)
+  constant d1 : real := Tsmp * wp - 2.0;  -- z-1 denominator coefficient (d)
+  constant num : real_vector := (n0, n1); 
+  constant den : real_vector := (d0, d1);
+
+begin
+
+  vout == vin'ztf(num, den, Tsmp);
+
+end ztf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd
new file mode 100644
index 0000000..e553f17
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/lowpass.vhd
@@ -0,0 +1,170 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+  generic ( res : resistance );
+  port ( terminal p1, p2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+  quantity v across i through p1 to p2;
+begin
+  v == i * res;
+end architecture ideal;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity capacitor is
+  generic ( cap : resistance );
+  port ( terminal p1, p2 : electrical );
+end entity capacitor;
+
+architecture ideal of capacitor is
+  quantity v across i through p1 to p2;
+begin
+  i == cap * v'dot;
+end architecture ideal;
+
+-- end not in book
+
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity lowpass is
+  generic ( gain : real := 1.0;	      -- gain for 'dot, 'ltf, and 'ztf
+            fp : real := 10.0;	      -- pole in Hz for 'dot, 'ltf, and 'ztf
+            Fsmp : real := 10.0e3 );  -- sample frequency for ztf
+  port ( terminal input: electrical;
+         terminal output: electrical );
+end entity lowpass;
+
+----------------------------------------------------------------
+
+architecture RC of lowpass is
+
+  constant cap : real := 1.0e-6;
+  constant res : real := 1.0 / (math_2_pi * cap * fp);
+
+begin
+
+  assert false
+    report "gain is ignored in architecture RC" severity note;
+  assert false
+    report "Fsmp is not used in architecture RC" severity note;
+
+  R : entity work.resistor(ideal)
+    generic map( res => res )
+    port map( p1 => input, p2 => output );
+
+  C : entity work.capacitor(ideal)
+    generic map( cap => cap )
+    port map( p1 => output, p2 => electrical_ref );
+
+end architecture RC;
+
+----------------------------------------------------------------
+
+architecture dot of lowpass is
+
+  quantity vin across input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+  constant wp : real := fp * math_2_pi;  -- pole in rad/s
+  constant tp : real := 1.0 / wp;        -- time constant
+
+begin
+
+  assert false
+    report "Fsmp is not used in architecture dot" severity note;
+
+  vin == (vout + tp * vout'dot) / gain;
+
+end architecture dot;
+
+----------------------------------------------------------------
+
+architecture ltf of lowpass is
+
+  quantity vin across input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+  constant wp : real := fp * math_2_pi;     -- pole in rad/s
+  constant num : real_vector := (0 => wp); 
+  constant den : real_vector := (wp, 1.0);
+
+begin
+
+  assert false
+    report "Fsmp is not used in architecture ltf" severity note;
+
+  vout == gain*vin'ltf(num, den);
+
+end architecture ltf;
+
+----------------------------------------------------------------
+
+architecture z_minus_1 of lowpass is
+
+  quantity vin across input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+  quantity vin_sampled : real;		  -- sampled input 
+  quantity vin_zm1, vout_zm1 : real; 	  -- z**-1 
+  constant Tsmp : real := 1.0 / Fsmp;	  -- sample period
+  constant wp : real := fp * math_2_pi;   -- pole in rad/s
+  constant n0 : real := Tsmp * wp;    	  -- z0 numerator coefficient
+  constant n1 : real := Tsmp * wp;    	  -- z-1 numerator coefficient
+  constant d0 : real := Tsmp * wp + 2.0;  -- z0 denominator coefficient
+  constant d1 : real := Tsmp * wp - 2.0;  -- z-1 denominator coefficient
+
+begin
+
+  vin_sampled  == gain*vin'zoh(Tsmp);
+
+  vin_zm1  == vin_sampled'delayed(Tsmp);
+
+  vout_zm1 == vout'delayed(Tsmp);
+
+  vout == vin_sampled * n0 / d0 + n1 * vin_zm1 / d0 - d1 * vout_zm1 / d0;
+
+end z_minus_1;
+
+----------------------------------------------------------------
+
+architecture ztf of lowpass is
+  
+  quantity vin across input to electrical_ref;
+  quantity vout across iout through output to electrical_ref;
+  constant Tsmp : real := 1.0 / Fsmp;	  -- sample period
+  constant wp : real := fp * math_2_pi;	  -- pole in rad/s
+  constant n0 : real := Tsmp * wp; 	  -- z0 numerator coefficient
+  constant n1 : real := Tsmp * wp; 	  -- z-1 numerator coefficient
+  constant d0 : real := Tsmp * wp + 2.0;  -- z0 denominator coefficient
+  constant d1 : real := Tsmp * wp - 2.0;  -- z-1 denominator coefficient
+  constant num : real_vector := (n0, n1); 
+  constant den : real_vector := (d0, d1);
+  
+begin
+  
+  vout == gain*vin'ztf(num, den, Tsmp);
+  
+end ztf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd
new file mode 100644
index 0000000..763e46d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity NMOS_transistor is
+  generic ( Cgs : real := 1.0e-6;   	-- gate to source capacitance
+            Cgd : real := 1.0e-6;   	-- gate to drain capacitance
+            gm : real := 5.0e-4;	-- transconductance
+            temp : real := 1.0;         -- termperature
+            Ro : real := 500.0e3;       -- ro resistance
+            af : real := 1.0;           -- flicker noise exponent constant
+            k_flicker : real := 1.0 );	-- flicker noise constant
+  port ( terminal gate, drain, source : electrical );
+end entity NMOS_transistor;
+
+----------------------------------------------------------------
+
+architecture noisy of NMOS_transistor is
+
+  quantity vgs across igs through gate to source;
+  quantity vds across ids through drain to source;
+  quantity vsd across source to drain;
+  quantity vgd across igd through gate to drain;
+  constant threshold_voltage : voltage := 1.0;
+  constant k : real := 1.0e-5;
+  -- declare quantity in frequency domain for AC analysis
+  quantity MOS_noise_source : real noise 
+			      4.0*K*temp/Ro +               -- thermal noise
+			      k_flicker*ids**af/frequency;  -- flicker noise
+
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+
+    if vds >= 0.0 use  -- transistor is forward biased
+      if vgs < threshold_voltage use  -- cutoff region
+        ids == 0.0;
+      elsif vds > vgs - threshold_voltage use  -- saturation region
+        ids == 0.5 * k * (vgs - threshold_voltage)**2;
+      else  -- linear/triode region
+        ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
+      end use;
+    else  -- transistor is reverse biased
+      if vgd < threshold_voltage use  -- cutoff region
+        ids == 0.0;
+      elsif vsd > vgd - threshold_voltage use  -- saturation region
+        ids == -0.5 * k * (vgd - threshold_voltage)**2;
+      else  -- linear/triode region
+        ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
+      end use;
+    end use;
+
+    igs == 0.0;
+    igd == 0.0;
+
+  else  -- noise and frequency model
+
+    igs == Cgs*vgs'dot;
+    igd == Cgd*vgd'dot;
+    ids == gm*vgs + vds/Ro + MOS_noise_source;
+
+  end use;
+
+end architecture noisy;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd
new file mode 100644
index 0000000..f5223e6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/nmos_transistor_wa.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity NMOS_transistor_wa is
+  port ( terminal gate, drain, source : electrical );
+end entity NMOS_transistor_wa;
+
+----------------------------------------------------------------
+
+architecture noisy of NMOS_transistor_wa is
+  
+  quantity vgs across igs through gate to source;
+  quantity vds across ids through drain to source;
+  quantity vsd across source to drain;
+  quantity vgd across igd through gate to drain;
+  constant threshold_voltage : voltage := 1.0;
+  constant k : real := 1.0e-5;
+  -- declare quantity in frequency domain for AC analysis
+        
+begin
+
+  if vds >= 0.0 use  -- transistor is forward biased
+    if vgs < threshold_voltage use  -- cutoff region
+      ids == 0.0;
+    elsif vds > vgs - threshold_voltage use  -- saturation region
+      ids == 0.5 * k * (vgs - threshold_voltage)**2;
+    else  -- linear/triode region
+      ids == k * (vgs - threshold_voltage - 0.5*vds) * vds;
+    end use;
+  else  -- transistor is reverse biased
+    if vgd < threshold_voltage use  -- cutoff region
+      ids == 0.0;
+    elsif vsd > vgd - threshold_voltage use  -- saturation region
+      ids == -0.5 * k * (vgd - threshold_voltage)**2;
+    else  -- linear/triode region
+      ids == -k * (vgd - threshold_voltage - 0.5*vsd) * vsd;
+    end use;
+  end use;
+
+  igs == 0.0;
+  igd == 0.0;
+
+end architecture noisy;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd
new file mode 100644
index 0000000..4a7799c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity opamp is
+  port ( terminal plus_in, minus_in, output : electrical );
+end entity opamp;
+
+----------------------------------------------------------------
+
+architecture slew_limited of opamp is
+
+  constant gain : real := 50.0;
+  quantity v_in across plus_in to minus_in;
+  quantity v_out across i_out through output;
+  quantity v_amplified : voltage;
+
+begin
+
+  v_amplified == gain * v_in;
+
+  v_out == v_amplified'slew(1.0e6,-1.0e6);
+
+end architecture slew_limited;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd
new file mode 100644
index 0000000..8bef2bb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity opamp_2pole is
+  port ( terminal in_pos, in_neg, output : electrical );
+end entity opamp_2pole;
+
+----------------------------------------------------------------
+
+architecture dot of opamp_2pole is
+
+  constant A : real := 1.0e6;                      -- open loop gain
+  constant fp1 : real := 5.0;                      -- first pole
+  constant fp2 : real := 9.0e5;                    -- second pole
+  constant tp1 : real := 1.0 / (fp1 * math_2_pi);  -- first time constant
+  constant tp2 : real := 1.0 / (fp2 * math_2_pi);  -- second time constant
+  quantity v_in across in_pos to in_neg;					
+  quantity v_out across i_out through output;
+
+begin
+
+  v_in == (tp1 * tp2) * v_out'dot'dot / A
+          + (tp1 + tp2) * v_out'dot / A + v_out / A;
+
+end architecture dot;
+
+----------------------------------------------------------------
+
+architecture ltf of opamp_2pole is
+
+  constant A : real := 1.0e6;		   -- open loop gain
+  constant fp1 : real := 5.0;		   -- first pole (Hz)
+  constant fp2 : real := 9.0e5;		   -- second pole (Hz)
+  constant wp1 : real := fp1 * math_2_pi;  -- first pole (rad/s)
+  constant wp2 : real := fp2 * math_2_pi;  -- second pole (rad/s)
+  constant num : real_vector := (0 => wp1 * wp2 * A);
+  constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0);
+  quantity v_in across in_pos to in_neg;
+  quantity v_out across i_out through output;
+
+begin
+
+  v_out == v_in'ltf(num, den);
+
+end architecture ltf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd
new file mode 100644
index 0000000..60ac210
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/opamp_2pole_res.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity opamp_2pole_res is
+  generic ( A : real := 1.0e6;	    -- open loop gain
+            rin : real := 1.0e6;    -- input resistance
+            rout : real := 100.0;   -- output resistance
+            fp1 : real := 5.0;	    -- first pole
+            fp2 : real := 9.0e5 );  -- second pole
+  port ( terminal in_pos, in_neg, output : electrical );
+end entity opamp_2pole_res;
+
+----------------------------------------------------------------
+
+architecture ltf of opamp_2pole_res is
+
+  constant wp1 : real := fp1 * math_2_pi;
+  constant wp2 : real := fp2 * math_2_pi;
+  constant num : real_vector := (0 => wp1 * wp2 * A);
+  constant den : real_vector := (wp1 * wp2, wp1 + wp2, 1.0);
+  quantity v_in across i_in through in_pos to in_neg;
+  quantity v_out across i_out through output;
+
+begin
+
+  i_in  == v_in / rin;  -- input current
+
+  v_out == v_in'ltf(num, den) + i_out * rout;
+
+end architecture ltf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd
new file mode 100644
index 0000000..a26499e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf-1.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_lpf_dot_ltf_ztf is
+end tb_lpf_dot_ltf_ztf;
+
+architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src : electrical;
+    terminal out_dot, out_ltf, out_ztf1, out_ztf4, out_RC : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 100.0,
+            amplitude => 5.0
+        )
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+
+	RC1 : entity work.lowpass(RC)
+
+		port map(
+            input => in_src,
+			output => out_RC
+        );
+	dot1 : entity work.lowpass(dot)
+
+		port map(
+            input => in_src,
+			output => out_dot
+        );
+    ltf1 : entity work.lowpass(ltf)
+
+    	port map(
+            input => in_src,
+			output => out_ltf
+        );
+    ztf1 : entity work.lowpass(ztf)
+ 
+    	port map(
+            input => in_src,
+			output => out_ztf1
+        );
+    ztf4 : entity work.lowpass(z_minus_1)
+ 
+    	port map(
+            input => in_src,
+			output => out_ztf4
+        );
+end TB_lpf_dot_ltf_ztf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd
new file mode 100644
index 0000000..be639a4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_lpf_dot_ltf_ztf.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_lpf_dot_ltf_ztf is
+end tb_lpf_dot_ltf_ztf;
+
+architecture TB_lpf_dot_ltf_ztf of tb_lpf_dot_ltf_ztf is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src : electrical;
+    terminal out_dot, out_ltf, out_ztf1, out_ztf2, out_ztf3, out_ztf4, out_RC : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 100.0,
+            amplitude => 5.0
+        )
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+	RC1 : entity work.lowpass(RC)
+        generic map(
+            gain => 1.0,
+            fp => 1.0e1,
+		Fsmp => 10.0e3
+        )
+		port map(
+            input => in_src,
+		output => out_RC
+        );
+	dot1 : entity work.lowpass(dot)
+        generic map(
+            gain => 1.0,
+            fp => 1.0e1,
+		Fsmp => 10.0e3
+        )
+		port map(
+            input => in_src,
+		output => out_dot
+        );
+    ltf1 : entity work.lowpass(ltf)
+        generic map(
+            gain => 1.0,
+            fp => 1.0e1,
+		Fsmp => 10.0e3
+        )
+    	port map(
+            input => in_src,
+		output => out_ltf
+        );
+    ztf1 : entity work.lowpass(ztf)
+        generic map(
+            gain => 1.0,
+            fp => 1.0e1,
+		Fsmp => 10.0e3
+        )
+    	port map(
+            input => in_src,
+		output => out_ztf1
+        );
+    ztf2 : entity work.lowpass(ztf)
+        generic map(
+            gain => 1.0,
+            fp => 1.0e1,
+		Fsmp => 1000.0
+        )
+    	port map(
+            input => in_src,
+		output => out_ztf2
+        );
+    ztf3 : entity work.lowpass(ztf)
+        generic map(
+            gain => 1.0,
+            fp => 1.0e1,
+		Fsmp => 100.0
+        )
+    	port map(
+            input => in_src,
+		output => out_ztf3
+        );
+    ztf4 : entity work.lowpass(z_minus_1)
+        generic map(
+            gain => 1.0,
+            fp => 1.0e1,
+		Fsmp => 10.0e3
+        )
+    	port map(
+            input => in_src,
+		output => out_ztf4
+        );
+end TB_lpf_dot_ltf_ztf;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd
new file mode 100644
index 0000000..ebc4990
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_mosfet_noisy.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_mosfet_noisy is
+end tb_mosfet_noisy ;
+
+architecture TB_mosfet_noisy of tb_mosfet_noisy is
+    -- Component declarations
+    -- Signal declarations
+    terminal d : electrical;
+    terminal g : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    mosfet1 : entity work.nmos_transistor_wa(noisy)
+        port map(
+            gate => g,
+            drain => d,
+            source => ELECTRICAL_REF
+        );
+    v1 : entity work.v_constant(ideal)
+        generic map(
+            level => 4.0
+        )
+        port map(
+            pos => g,
+            neg => ELECTRICAL_REF
+        );
+    mosfet2 : entity work.nmos_transistor_wa(noisy)
+        port map(
+            gate => g,
+            drain => ELECTRICAL_REF,
+            source => d
+        );
+    v4 : entity work.v_pulse(ideal)
+        generic map(
+            initial => 0.0,
+            pulse => 5.0,
+            ti2p => 1 ms,
+            tp2i => 1 ms,
+            delay => 1 us,
+            width => 1 us,
+            period => 2.002 ms
+        )
+        port map(
+            pos => d,
+            neg => ELECTRICAL_REF
+        );
+end TB_mosfet_noisy ;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd
new file mode 100644
index 0000000..9be54df
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp.vhd
@@ -0,0 +1,74 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE; use IEEE.std_logic_1164.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_opamp is
+end tb_opamp;
+
+architecture TB_opamp of tb_opamp is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src, op_neg2, out_opamp2 : electrical;
+    terminal out_opamp1, op_neg1, op_neg3, out_opamp3, out_opamp3_res, op_neg3_res : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 100.0,
+            amplitude => 5.0e-3
+        )
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+
+    OP1 : entity work.opamp(slew_limited)
+    	port map(
+            plus_in => electrical_ref,
+            minus_in => op_neg1,
+		output => out_opamp1
+        );
+    R1in : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => in_src,
+            p2 => op_neg1
+        );
+    R1F : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e9
+        )
+        port map(
+            p1 => op_neg1,
+            p2 => out_opamp1
+        );
+    Rload1 : entity work.resistor(ideal)
+        generic map(
+            res => 1.0e3
+        )
+        port map(
+            p1 => out_opamp1,
+            p2 => electrical_ref
+        );
+end TB_opamp;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd
new file mode 100644
index 0000000..ddb9c5e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_opamp_2pole.vhd
@@ -0,0 +1,134 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE; use IEEE.std_logic_1164.all;
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_opamp_2pole is
+end tb_opamp_2pole;
+
+architecture TB_opamp_2pole of tb_opamp_2pole is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src, op_neg2, out_opamp2 : electrical;
+    terminal out_opamp1, op_neg1, out_opamp3_res, op_neg3_res : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 100.0,
+            amplitude => 5.0
+        )
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+
+    OP1 : entity work.opamp_2pole(dot)
+    	port map(
+            in_pos => electrical_ref,
+            in_neg => op_neg1,
+		output => out_opamp1
+        );
+    R1in : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => in_src,
+            p2 => op_neg1
+        );
+    R1F : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => op_neg1,
+            p2 => out_opamp1
+        );
+    Rload1 : entity work.resistor(ideal)
+        generic map(
+            res => 1.0e3
+        )
+        port map(
+            p1 => out_opamp1,
+            p2 => electrical_ref
+        );
+	OP2 : entity work.opamp_2pole(ltf)
+    	port map(
+            in_pos => electrical_ref,
+            in_neg => op_neg2,
+		output => out_opamp2
+        );
+    R2in : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => in_src,
+            p2 => op_neg2
+        );
+    R2F : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => op_neg2,
+            p2 => out_opamp2
+        );
+    Rload2 : entity work.resistor(ideal)
+        generic map(
+            res => 1.0e3
+        )
+        port map(
+            p1 => out_opamp2,
+            p2 => electrical_ref
+        );
+	OP3R : entity work.opamp_2pole_res(ltf)
+    	port map(
+            in_pos => electrical_ref,
+            in_neg => op_neg3_res,
+			output => out_opamp3_res
+        );
+    Rin3R : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => in_src,
+            p2 => op_neg3_res
+        );
+    R3F : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => op_neg3_res,
+            p2 => out_opamp3_res
+        );
+    Rload3R : entity work.resistor(ideal)
+        generic map(
+            res => 1.0e3
+        )
+        port map(
+            p1 => out_opamp3_res,
+            p2 => electrical_ref
+        );
+end TB_opamp_2pole;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd
new file mode 100644
index 0000000..17a7765
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/tb_v_source.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_v_source is
+
+end tb_v_source ;
+
+architecture TB_v_source of tb_v_source is
+    terminal sin_out1, sin_out2 : electrical;
+    -- Component declarations
+    -- Signal declarations
+begin
+    -- Signal assignments
+    -- Component instances
+    v1 : entity work.v_source(behavior)
+        port map(
+            pos => sin_out1,
+            neg => ELECTRICAL_REF
+        );
+
+    R1 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => sin_out1,
+            p2 => electrical_ref
+        );
+    v2 : entity work.v_constant(ideal)
+        generic map(
+            level => 1.0
+        )
+   		port map(
+            pos => sin_out2,
+            neg => ELECTRICAL_REF
+        );
+
+    R2 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => sin_out2,
+           p2 => electrical_ref
+        );
+end TB_v_source ;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd
new file mode 100644
index 0000000..46264eb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source-1.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity v_source is
+  generic ( DC : voltage := 1.0;        -- output peak amplitude
+            min_freq : real := 10.0;	-- minimum frequency for spectral source
+            max_freq : real := 1.0e4;	-- maximum frequency for spectral source
+            ac_mag : voltage := 1.0;    -- AC magnitude
+            ac_phase : real := 0.0 );   -- AC phase [degree]
+  port ( terminal pos, neg : electrical );
+end entity v_source;
+
+----------------------------------------------------------------
+
+architecture behavior of v_source is
+
+  function g (freq : real) return real is
+  begin
+    if (freq > min_freq and freq < max_freq) then
+      return 1.0;
+    else
+      return 0.0;
+    end if;
+  end function g;
+  
+  quantity vout across iout through pos to neg;
+  -- declare quantity in frequency domain for AC analysis
+  quantity ac_spec : real spectrum ac_mag*g(frequency),
+		          math_2_pi*ac_phase/360.0;
+
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+    vout == DC;
+  else
+    vout == ac_spec;  -- used for frequency (AC) analysis
+  end use;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd
new file mode 100644
index 0000000..c8f12e0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/frequency-modeling/v_source.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity v_source is
+  generic ( DC : voltage := 1.0;        -- output peak amplitude
+            ac_mag : voltage := 1.0;    -- AC magnitude
+            ac_phase : real := 0.0 );   -- AC phase [degree]
+  port ( terminal pos, neg : electrical );
+end entity v_source;
+
+----------------------------------------------------------------
+
+architecture behavior of v_source is
+  
+  quantity vout across iout through pos to neg;
+  -- declare quantity in frequency domain for AC analysis
+  quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
+        
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+    vout == DC;
+  else
+    vout == ac_spec;  -- used for frequency (AC) analysis
+  end use;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd
new file mode 100644
index 0000000..089ea0d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/adc.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+                       
+entity adc is
+  port ( quantity gain : in voltage;
+         terminal a : electrical;
+         signal clk : in bit;
+         signal d_out : out bit );
+end entity adc;
+
+architecture ideal of adc is
+  
+  constant ref : real := 5.0;
+  quantity v_in across a;
+  quantity v_amplified : voltage;
+  
+begin
+  
+  v_amplified == v_in * gain;
+  
+  adc_behavior: process is
+    variable stored_d : bit;
+  begin 
+    if clk = '1' then
+      if v_amplified > ref / 2.0 then
+        stored_d := '1';
+      else
+        stored_d := '0';
+      end if;
+    end if;
+    d_out <= stored_d after 5 ns;
+    wait on clk;
+  end process adc_behavior;
+  
+end architecture ideal;
+
+architecture struct of adc is
+  
+  terminal a_amplified, ref, half_ref: electrical;
+  quantity v_ref across i_ref through ref;
+  signal d : bit;
+  
+begin
+  
+  res1 : entity work.resistor(ideal)
+    port map ( ref, half_ref);
+  
+  res2 : entity work.resistor(ideal)
+    port map ( half_ref, electrical_ref );
+  
+  amp : entity work.vc_amp(ideal)
+    port map ( gain, a, a_amplified );
+  
+  comp : entity work.comparator(ideal)
+    port map ( a_amplified, half_ref, d);
+  
+  ff : entity work.d_ff(basic)
+    port map ( d, clk, d_out );
+  
+  v_ref == 5.0;
+  
+end architecture struct;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd
new file mode 100644
index 0000000..7c3bb4d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/comparator.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity comparator is
+  port ( terminal plus, minus : electrical;
+         signal value : out bit );
+end entity comparator;
+
+architecture ideal of comparator is
+  quantity diff across plus to minus;
+begin
+  
+  comp_behavior: process is
+  begin
+    if diff > 0.0 then
+      value <= '1' after 5 ns;
+    else
+      value <= '0' after 5 ns;
+    end if;
+    wait on diff'above(0.0);
+  end process comp_behavior;
+  
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd
new file mode 100644
index 0000000..b586f69
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity d_ff is
+  port ( d, clk : in bit;  q : out bit );
+end d_ff;
+
+architecture basic of d_ff is
+begin
+  
+  ff_behavior : process is
+  begin
+    if clk = '1' then
+      q <= d after 2 ns;
+    end if;
+    wait on clk;
+  end process ff_behavior;
+  
+end architecture basic;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/index-ams.txt
new file mode 100644
index 0000000..d4fed24
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/index-ams.txt
@@ -0,0 +1,18 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                        Chapter 1 - Fundamental Concepts
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+adc.vhd                                         entity adc                              ideal, struct                   Figures 1-13, 1-14, 1-17
+resistor.vhd                                    entity resistor                         ideal                           Figure 1-16
+vc_amp.vhd                                      entity vc_amp                           ideal                           Figure 1-16
+comparator.vhd                                  entity comparator                       ideal                           Figure 1-16
+d_ff.vhd                                        entity d_ff                             basic                           Figure 1-16
+propulsion.vhd                                  entity propulsion                       mixed                           Figure 1-18
+test_bench-1.vhd                                entity test_bench                       example                         Figure 1-19
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_adc.vhd                                      entity tb_adc                           tb_adc                          adc.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd
new file mode 100644
index 0000000..a96bb0d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/propulsion.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.mechanical_systems.all;
+use ieee_proposed.electrical_systems.all;
+
+entity propulsion is
+  port ( signal clk, reset : in bit;    -- control inputs
+         signal rpm : in natural;       -- requested rpm
+         signal forward : in bit );     -- requested direction
+end entity propulsion;
+
+architecture mixed of propulsion is
+  terminal p1, p2 : electrical;
+  terminal shaft1, shaft2, shaft3 : rotational_v;
+  signal forward_gear : bit;
+  -- ...
+begin
+
+  motor : entity work.dc_motor(ideal)
+    port map ( p1, p2, shaft1 );
+
+  gear : entity work.gear_av(ideal)
+    port map ( forward_gear, shaft1, shaft2 );
+
+  intertia : entity work.inertia_av(ideal)
+    port map ( shaft2, shaft3 );
+
+  prop : entity work.propeller(ideal)
+    port map ( shaft3 );
+
+  control_section : process is
+    -- variable declarations for control_section to control voltage inputs
+    -- and gear shifting
+    -- ...
+  begin
+    -- ...
+    wait on clk, reset;
+  end process control_section;
+
+  -- ...
+
+end architecture mixed;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd
new file mode 100644
index 0000000..5f492f4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/resistor.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity resistor is
+  port ( terminal p1, p2 : electrical );
+end entity resistor ;
+
+architecture ideal of resistor is
+  quantity v across i through p1 to p2;
+  constant resistance : real := 10000.0;
+begin
+  v == i * resistance;
+end architecture ideal;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd
new file mode 100644
index 0000000..ef2517f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/tb_adc.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE; use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+
+entity tb_adc is
+end tb_adc;
+
+architecture tb_adc of tb_adc is
+    -- Component declarations
+    -- Signal declarations
+    	signal clk_in : bit;
+	signal clk_in_tmp : std_logic;
+    	signal dig_out1, dig_out2 : bit;
+    	terminal sine_in : electrical;
+	quantity gain : real;
+begin
+    -- Signal assignments
+	clk_in <= To_bit(clk_in_tmp);	-- convert std_logic to bit
+    -- Component instances
+    v1 : entity work.v_sine(ideal)
+        generic map(
+            freq => 1.0,
+            amplitude => 5.0
+        )
+        port map(
+            pos => sine_in,
+            neg => ELECTRICAL_REF
+        );
+    adc25 : entity work.adc(struct)
+        port map(
+			gain => gain,
+            a => sine_in,
+            d_out => dig_out1,
+            clk => clk_in
+        );
+    adc26 : entity work.adc(ideal)
+        port map(
+			gain => gain,
+            a => sine_in,
+            d_out => dig_out2,
+            clk => clk_in
+        );
+    clock1 : entity work.clock_duty(ideal)
+        generic map(
+            on_time => 1 ms,
+            off_time => 0.5 ms
+        )
+        port map(
+            CLOCK_OUT => clk_in_tmp
+        );
+    src1 : entity work.src_constant(ideal)
+        generic map(
+            level => 1.0
+        )
+        port map(
+            output => gain
+        );
+end tb_adc;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd
new file mode 100644
index 0000000..eff53a3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/test_bench-1.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.mechanical_systems.all;
+use ieee_proposed.electrical_systems.all;
+
+entity test_bench is
+end entity test_bench;
+
+architecture example of test_bench is
+  
+  signal clk, reset: bit;
+  signal rpm : natural;
+  signal forward : bit;
+        
+begin
+  dut : entity work.propulsion(mixed)
+    port map ( clk, reset, rpm, forward );
+  
+  stimulus: process is
+  begin
+    clk <= '1'; reset <= '0'; rpm <= 0; forward <= '1'; wait for 10 sec;
+    clk <= '0'; wait for 10 sec;
+    clk <= '1'; rpm <= 50; wait for 20 sec;
+    clk <= '0'; wait for 20 sec;
+    clk <= '1'; rpm <= 0; wait for 20 sec;
+    clk <= '0'; wait for 20 sec;
+    clk <= '1'; rpm <= 50; forward <= '0'; wait for 20 sec;
+    clk <= '0'; wait for 20 sec;
+    -- ...
+    wait;
+  end process stimulus;
+  
+end architecture example;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd
new file mode 100644
index 0000000..5347c28
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/vc_amp.vhd
@@ -0,0 +1,32 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                       
+entity vc_amp is
+  port ( quantity g : in voltage;
+         terminal a, o : electrical );
+end entity vc_amp;
+
+architecture ideal of vc_amp is
+  quantity v_in across a;
+  quantity v_out across i_out through o;
+begin
+  v_out == v_in * g;
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd
new file mode 100644
index 0000000..6398be1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+configuration architectural of computer_system is
+
+  for block_level
+
+    -- . . .    -- component configurations for cpu and memory, etc
+
+    for instrumentation
+
+      for cpu_bus_monitor : bus_monitor_pkg.bus_monitor
+        use entity work.bus_monitor(general_purpose)
+        generic map ( verbose => true, dump_stats => true );
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration architectural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd
new file mode 100644
index 0000000..faf4b2a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity nmos is
+  port ( terminal gate, source, drain : electrical );
+end entity nmos;
+
+architecture ideal of nmos is
+begin
+end architecture ideal;
+
+architecture spice_equivalent of nmos is
+begin
+end architecture spice_equivalent;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity pmos is
+  port ( terminal gate, source, drain : electrical );
+end entity pmos;
+
+architecture ideal of pmos is
+begin
+end architecture ideal;
+
+
+
+-- code from book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity carry_chain is
+  generic ( n : positive );
+  port ( terminal clk, c_in, c_out, vdd, vss : electrical;
+         terminal p, g : electrical_vector (1 to n) );
+end entity carry_chain;
+
+----------------------------------------------------------------
+
+architecture device_level of carry_chain is
+
+  component nmos is
+    port ( terminal gate, source, drain : electrical );
+  end component nmos;
+
+  component pmos is
+    port ( terminal gate, source, drain : electrical );
+  end component pmos;
+
+  terminal c_neg : electrical_vector(0 to n-1);
+
+begin
+
+  bit_array : for index in 0 to n generate
+    terminal clk_pulldown_drain : electrical;
+  begin
+
+    clk_pulldown : component nmos
+      port map ( clk, vss, clk_pulldown_drain );
+
+    bit_0 : if index = 0 generate
+    begin
+      clk_precharge : component pmos
+        port map ( clk, c_neg(index), vdd );
+      g_pulldown : component nmos
+        port map ( c_in, clk_pulldown_drain, c_neg(index) );
+    end generate bit_0;
+
+    middle_bit : if index /= 0 and index /= n generate
+    begin
+      clk_precharge : component pmos
+        port map ( clk, c_neg(index), vdd );
+      g_pulldown : component nmos
+        port map ( g(index), clk_pulldown_drain, c_neg(index) );
+      p_pass : component nmos
+        port map ( p(index), c_neg(index - 1), c_neg(index) );
+    end generate middle_bit;
+
+    bit_n : if index = n generate
+    begin
+      clk_precharge : component pmos
+        port map ( clk, c_out, vdd );
+      g_pulldown : component nmos
+        port map ( g(index), clk_pulldown_drain, c_out );
+      p_pass : component nmos
+        port map ( p(index), c_neg(index - 1), c_out );
+    end generate bit_n;
+
+  end generate bit_array;
+
+end architecture device_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd
new file mode 100644
index 0000000..972be8b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd
@@ -0,0 +1,188 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package bus_monitor_pkg is
+
+  type stats_type is record
+      ifetch_freq, write_freq, read_freq : real;
+    end record stats_type;
+
+  component bus_monitor is
+    generic ( verbose, dump_stats : boolean := false );
+    port ( mem_req, ifetch, write : in bit;
+           bus_stats : out stats_type );
+  end component bus_monitor;
+
+end package bus_monitor_pkg;
+
+
+use work.bus_monitor_pkg.all;
+
+entity bus_monitor is
+  generic ( verbose, dump_stats : boolean := false );
+  port ( mem_req, ifetch, write : in bit;
+         bus_stats : out stats_type );
+end entity bus_monitor;
+
+
+architecture general_purpose of bus_monitor is
+begin
+
+  access_monitor : process is
+
+    variable access_count, ifetch_count,
+             write_count, read_count : natural := 0;
+      use std.textio;
+      variable L : textio.line;
+
+  begin
+    wait until mem_req = '1';
+    if ifetch = '1' then
+      ifetch_count := ifetch_count + 1;
+        if verbose then
+          textio.write(L, string'("Ifetch"));
+          textio.writeline(textio.output, L);
+        end if;
+    elsif write = '1' then
+      write_count := write_count + 1;
+        if verbose then
+          textio.write(L, string'("Write"));
+          textio.writeline(textio.output, L);
+        end if;
+    else
+      read_count := read_count + 1;
+        if verbose then
+          textio.write(L, string'("Read"));
+          textio.writeline(textio.output, L);
+        end if;
+    end if;
+    access_count := access_count + 1;
+    bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count);
+    bus_stats.write_freq <= real(write_count) / real(access_count);
+    bus_stats.read_freq <= real(read_count) / real(access_count);
+      if dump_stats and access_count mod 5 = 0 then
+        textio.write(L, string'("Ifetch frequency = "));
+        textio.write(L, real(ifetch_count) / real(access_count));
+        textio.writeline(textio.output, L);
+        textio.write(L, string'("Write frequency = "));
+        textio.write(L, real(write_count) / real(access_count));
+        textio.writeline(textio.output, L);
+        textio.write(L, string'("Read frequency = "));
+        textio.write(L, real(read_count) / real(access_count));
+        textio.writeline(textio.output, L);
+      end if;
+  end process access_monitor;
+
+end architecture general_purpose;
+
+
+
+-- code from book (in text)
+
+entity computer_system is
+  generic ( instrumented : boolean := false );
+  port ( -- . . . );
+  -- not in book
+         other_port : in bit := '0' );
+  -- end not in book
+end entity computer_system;
+
+-- end code from book
+
+
+-- code from book
+
+architecture block_level of computer_system is
+
+  -- . . .    -- type and component declarations for cpu and memory, etc.
+
+  signal clock : bit;    -- the system clock
+  signal mem_req : bit;  -- cpu access request to memory
+  signal ifetch : bit;   -- indicates access is to fetch an instruction
+  signal write : bit;    -- indicates access is a write
+  -- . . .                  -- other signal declarations
+
+begin
+
+  -- . . .    -- component instances for cpu and memory, etc.
+
+  instrumentation : if instrumented generate
+
+    use work.bus_monitor_pkg;
+    signal bus_stats : bus_monitor_pkg.stats_type;
+
+  begin
+
+    cpu_bus_monitor : component bus_monitor_pkg.bus_monitor
+      port map ( mem_req, ifetch, write, bus_stats );
+
+  end generate instrumentation;
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    ifetch <= '1';  write <= '0';
+    mem_req <= '1', '0' after 10 ns;
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '1';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture block_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd
new file mode 100644
index 0000000..19a5efc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book (in text)
+
+entity computer_system is
+  generic ( instrumented : boolean := false );
+  port ( -- . . . );
+  -- not in book
+         other_port : in bit := '0' );
+  -- end not in book
+end entity computer_system;
+
+-- end code from book
+
+
+-- code from book
+
+architecture block_level of computer_system is
+
+  -- . . .    -- type and component declarations for cpu and memory, etc
+
+  signal clock : bit;    -- the system clock
+  signal mem_req : bit;  -- cpu access request to memory
+  signal ifetch : bit;   -- indicates access is to fetch an instruction
+  signal write : bit;    -- indicates access is a write
+  -- . . .                  -- other signal declarations
+
+begin
+
+  -- . . .    -- component instances for cpu and memory, etc
+
+  instrumentation : if instrumented generate
+
+    signal ifetch_freq, write_freq, read_freq : real := 0.0;
+
+  begin
+
+    access_monitor : process is
+      variable access_count, ifetch_count,
+               write_count, read_count : natural := 0;
+    begin
+      wait until mem_req = '1';
+      if ifetch = '1' then
+        ifetch_count := ifetch_count + 1;
+      elsif write = '1' then
+        write_count := write_count + 1;
+      else
+        read_count := read_count + 1;
+      end if;
+      access_count := access_count + 1;
+      ifetch_freq <= real(ifetch_count) / real(access_count);
+      write_freq <= real(write_count) / real(access_count);
+      read_freq <= real(read_count) / real(access_count);
+    end process access_monitor;
+
+  end generate instrumentation;
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    ifetch <= '1';  write <= '0';
+    mem_req <= '1', '0' after 10 ns;
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '1';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture block_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd
new file mode 100644
index 0000000..a6c82e0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity DRAM_4M_by_4 is
+  port ( a :  in std_logic_vector(0 to 10);
+         d :  inout std_logic_vector(0 to 3);
+         cs, we, ras, cas : in std_logic );
+end entity DRAM_4M_by_4;
+
+
+architecture chip_function of DRAM_4M_by_4 is
+begin
+  d <= (others => 'Z');
+end architecture chip_function;
+
+
+-- code from book
+
+library chip_lib;  use chip_lib.all;
+
+configuration down_to_chips of memory_board is
+
+  for chip_level
+
+    for bank_array
+
+      for nibble_array
+
+        for a_DRAM : DRAM
+          use entity DRAM_4M_by_4(chip_function);
+        end for;
+
+      end for;
+
+    end for;
+
+    -- . . .    -- configurations of other component instances
+
+  end for;
+
+end configuration down_to_chips;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd
new file mode 100644
index 0000000..4d0cfa8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity buf is
+  port ( a : in std_logic;  y : out std_logic );
+end entity buf;
+
+
+architecture basic of buf is
+begin
+  y <= a;
+end architecture basic;
+
+
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity fanout_tree is
+  generic ( height : natural );
+  port ( input : in std_logic;
+         output : out std_logic_vector (0 to 2**height - 1) );
+end entity fanout_tree;
+
+--------------------------------------------------
+
+architecture recursive of fanout_tree is
+
+begin
+
+  degenerate_tree : if height = 0 generate
+  begin
+    output(0) <= input;
+  end generate degenerate_tree;
+
+  compound_tree : if height > 0 generate
+    signal buffered_input_0, buffered_input_1 : std_logic;
+  begin
+
+    buf_0 : entity work.buf(basic)
+      port map ( a => input, y => buffered_input_0 );
+
+    subtree_0 : entity work.fanout_tree(recursive)
+      generic map ( height => height - 1 )
+      port map ( input => buffered_input_0,
+                 output => output(0 to 2**(height - 1) - 1) );
+
+    buf_1 : entity work.buf(basic)
+      port map ( a => input, y => buffered_input_1 );
+
+    subtree_1 : entity work.fanout_tree(recursive)
+      generic map ( height => height - 1 )
+      port map ( input => buffered_input_1,
+                 output => output(2**(height - 1) to 2**height - 1) );
+
+  end generate compound_tree;
+
+end architecture recursive;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd
new file mode 100644
index 0000000..88b11ac
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity graphics_engine is
+end entity graphics_engine;
+
+-- end not in book
+
+
+architecture behavioral of graphics_engine is
+
+  type point is array (1 to 3) of real;
+  type transformation_matrix is array (1 to 3, 1 to 3) of real;
+
+  signal p, transformed_p : point;
+  signal a : transformation_matrix;
+  signal clock : bit;
+  -- . . .
+
+begin
+
+  transform_stage : for i in 1 to 3 generate
+  begin
+
+    cross_product_transform : process is
+      variable result1, result2, result3 : real := 0.0;
+    begin
+      wait until clock = '1';
+      transformed_p(i) <= result3;
+      result3 := result2;
+      result2 := result1;
+      result1 :=  a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
+    end process cross_product_transform;
+
+  end generate transform_stage;
+
+  -- . . .    -- other stages in the pipeline, etc
+
+  -- not in book
+
+  clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
+
+  stimulus : process is
+  begin
+    a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
+    p <= ( 10.0, 10.0, 10.0 );
+    wait until clock = '0';
+    p <= ( 20.0, 20.0, 20.0 );
+    wait until clock = '0';
+    p <= ( 30.0, 30.0, 30.0 );
+    wait until clock = '0';
+    p <= ( 40.0, 40.0, 40.0 );
+    wait until clock = '0';
+    p <= ( 50.0, 50.0, 50.0 );
+    wait until clock = '0';
+    p <= ( 60.0, 60.0, 60.0 );
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd
new file mode 100644
index 0000000..2e9e460
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library device_lib;
+
+configuration identical_devices of led_bar_display is
+
+  for device_level
+
+    for device_array
+
+      for limiting_resistor : resistor
+        use entity device_lib.resistor(ideal);
+      end for;
+
+      for segment_led : led
+        use entity device_lib.led(ideal);
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration identical_devices;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/index-ams.txt
new file mode 100644
index 0000000..bfbcd59
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/index-ams.txt
@@ -0,0 +1,33 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                         Chapter 17 - Generate Statements
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+led_bar_display.vhd                             entity resistor                         ideal                           --
+--                                              entity led                              ideal                           --
+--                                              entity led_bar_display                  device_level                    Figure 17-2
+resistor_pack.vhd                               entity resistor_pack                    coupled                         Figure 17-3
+graphics_engine.vhd                             entity graphics_engine                  behavioral                      Figure 17-4
+memory_board.vhd                                entity DRAM                             empty                           --
+--                                              entity memory_board                     chip_level                      Figure 17-5
+carry_chain.vhd                                 entity nmos                             ideal, spice_equivalent         --
+--                                              entity carry_chain                      device_level                    Figure 17-8
+computer_system.vhd                             entity computer_system                  block_level                     Section 17.2, Figure 17-9
+fanout_tree.vhd                                 entity buf                              basic                           --
+--                                              entity fanout_tree                      recursive                       Figure 17-11
+computer_system-1.vhd                           package bus_monitor_pkg                 --                              --
+--                                              entity bus_monitor                      general_purpose                 --
+--                                              entity computer_system                  block_level                     Figure 17-12
+architectural.vhd                               configuration architectural             --                              Figure 17-13
+identical_devices.vhd                           configuration identical_devices         --                              Figure 17-14
+down_to_chips.vhd                               entity DRAM_4M_by_4                     chip_function                   --
+--                                              configuration down_to_chips             --                              Figure 17-15
+last_pass_spice.vhd                             configuration last_pass_spice           --                              Figure 17-16
+inline_01.vhd                                   entity inline_01                        test                            --
+--                                              configuration inline_01_test            --                              Section 17.2
+inline_02.vhd                                   entity inline_02                        test                            Section 17.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd
new file mode 100644
index 0000000..61342d7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+end entity inline_01;
+
+
+architecture test of inline_01 is
+
+  component computer_system is
+    port ( other_port : in bit := '0' );
+  end component computer_system;
+
+begin
+
+  system_under_test : component computer_system
+    port map ( other_port => open );
+
+end architecture test;
+
+
+
+configuration inline_01_test of inline_01 is
+
+  for test
+
+    -- code from book (in text)
+
+    for system_under_test : computer_system
+      use entity work.computer_system(block_level)
+      generic map ( instrumented => true )
+      -- . . .
+      -- not in book
+      ;
+      -- end not in book
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration inline_01_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd
new file mode 100644
index 0000000..b6f9aba
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity inline_02 is
+end entity inline_02;
+
+
+architecture test of inline_02 is
+
+  signal unbuffered_clock : std_logic;
+  signal buffered_clock_array : std_logic_vector(0 to 7);
+
+begin
+
+  -- code from book (in text)
+
+  clock_buffer_tree : entity work.fanout_tree(recursive)
+    generic map ( height => 3 )
+    port map ( input => unbuffered_clock,
+               output => buffered_clock_array );
+
+  -- end code from book
+
+  clock_gen : process is
+  begin
+    unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
+    wait for 10 ns;
+  end process clock_gen;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd
new file mode 100644
index 0000000..dae9ff2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library device_lib;
+
+configuration last_pass_spice of carry_chain is
+
+  for device_level
+
+    for bit_array ( 0 to n - 1 )
+
+      for bit_0
+        for all : nmos
+          use entity device_lib.nmos(ideal);
+        end for;
+        for all : pmos
+          use entity device_lib.pmos(ideal);
+        end for;
+      end for;
+
+      for middle_bit
+        for all : nmos
+          use entity device_lib.nmos(ideal);
+        end for;
+        for all : pmos
+          use entity device_lib.pmos(ideal);
+        end for;
+      end for;
+
+    end for;
+
+    for bit_array ( n )
+
+      for bit_n
+        for p_pass : nmos
+          use entity device_lib.nmos(spice_equivalent);
+        end for;
+        for others : nmos
+          use entity device_lib.nmos(ideal);
+        end for;
+        for all : pmos
+          use entity device_lib.pmos(ideal);
+        end for;
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration last_pass_spice;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd
new file mode 100644
index 0000000..d17e5a1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- analyze into resource library device_lib
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+  port ( terminal p1, p2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+begin
+end architecture ideal;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity led is
+  port ( terminal anode, cathode : electrical );
+end entity led;
+
+architecture ideal of led is
+begin
+end architecture ideal;
+
+
+
+-- code from book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity led_bar_display is
+  generic ( width : positive );
+  port ( terminal anodes : electrical_vector(1 to width);
+         terminal common_cathode : electrical );
+end entity led_bar_display;
+
+----------------------------------------------------------------
+
+architecture device_level of led_bar_display is
+
+  component resistor is
+    port ( terminal p1, p2 : electrical );
+  end component resistor;
+
+  component led is
+    port ( terminal anode, cathode : electrical );
+  end component led;
+
+begin
+
+  device_array : for segment in 1 to width generate
+
+    terminal led_anode : electrical;
+
+  begin
+
+    limiting_resistor : component resistor
+      port map ( p1 => anodes(segment), p2 => led_anode );
+
+    segment_led : component led
+      port map ( anode => led_anode, cathode => common_cathode );
+
+  end generate device_array;
+
+end architecture device_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd
new file mode 100644
index 0000000..65a35f1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity DRAM is
+  port ( a :  in std_logic_vector(0 to 10);
+         d :  inout std_logic_vector(0 to 3);
+         cs, we, ras, cas : in std_logic );
+end entity DRAM;
+
+
+architecture empty of DRAM is
+begin
+  d <= (others => 'Z');
+end architecture empty;
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity memory_board is
+end entity memory_board;
+
+-- end not in book
+
+
+architecture chip_level of memory_board is
+
+  component DRAM is
+    port ( a :  in std_logic_vector(0 to 10);
+           d :  inout std_logic_vector(0 to 3);
+           cs, we, ras, cas : in std_logic );
+  end component DRAM;
+
+  signal buffered_address : std_logic_vector(0 to 10);
+  signal DRAM_data : std_logic_vector(0 to 31);
+  signal bank_select : std_logic_vector(0 to 3);
+  signal buffered_we, buffered_ras, buffered_cas : std_logic;
+
+  -- . . .    -- other declarations
+
+begin
+
+  bank_array : for bank_index in 0 to 3 generate
+  begin
+
+    nibble_array : for nibble_index in 0 to 7 generate
+
+      constant data_lo : natural := nibble_index * 4;
+      constant data_hi : natural := nibble_index * 4 + 3;
+
+    begin
+
+      a_DRAM : component DRAM
+        port map ( a => buffered_address,
+                   d => DRAM_data(data_lo to data_hi),
+                   cs => bank_select(bank_index),
+                   we => buffered_we,
+                   ras => buffered_ras,
+                   cas => buffered_cas );
+
+    end generate nibble_array;
+
+  end generate bank_array;
+
+  -- . . .    -- other component instances, etc
+
+  -- not in book
+
+  buffered_address <= "01010101010";
+  DRAM_data <= X"01234567";
+
+  -- end not in book
+
+end architecture chip_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/resistor_pack.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/resistor_pack.vhd
new file mode 100644
index 0000000..42dec93
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/resistor_pack.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all, ieee_proposed.thermal_systems.all;
+
+entity resistor_pack is
+  generic ( resistances_at_298K : real_vector;
+            temperature_coeff : real := 0.0 );
+  port ( terminal p1, p2 : electrical_vector(1 to resistances_at_298K'length);
+         quantity package_temp : in temperature );
+end entity resistor_pack;
+
+----------------------------------------------------------------
+
+architecture coupled of resistor_pack is
+
+  quantity v across i through p1 to p2;
+  quantity effective_resistance : real_vector(1 to resistances_at_298K'length);
+
+begin
+
+  resistor_array : for index in 1 to resistances_at_298K'length generate
+
+    effective_resistance(index)
+      == resistances_at_298K(index)
+          + ( package_temp - 298.0 ) * temperature_coeff;
+
+    v(index ) == i(index) * effective_resistance(index);
+
+  end generate resistor_array;
+
+end architecture coupled;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/control_unit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/control_unit.vhd
new file mode 100644
index 0000000..1fda52a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/control_unit.vhd
@@ -0,0 +1,39 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book
+
+entity control_unit is
+
+  generic ( Tpd_clk_out, Tpw_clk : delay_length;
+            debug : boolean := false );
+
+  port ( clk : in bit;
+         ready : in bit;
+         control1, control2 : out bit );
+
+end entity control_unit;
+
+-- end code from book
+
+
+
+architecture test of control_unit is
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/index-ams.txt
new file mode 100644
index 0000000..7be1d36
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/index-ams.txt
@@ -0,0 +1,23 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                          Chapter 9 - Generic Constants
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+control_unit.vhd                                entity control_unit                     test                            Figure 12-1
+timer.vhd                                       entity timer                            behavioral                      Figure 12-2
+reg.vhd                                         entity reg                              behavioral                      Figure 12-3
+multiple_opamp.vhd                              entity multiple_opamp                   ideal                           Figure 12-4
+inline_01.vhd                                   entity inline_01                        test                            Section 12.1
+inline_02a.vhd                                  entity resistor                         simple                          Section 12.1
+inline_03.vhd                                   entity inline_03                        test                            Section 12.1
+inline_05a.vhd                                  entity inline_05a                       test                            Section 12.1
+inline_06.vhd                                   entity inline_06                        test                            Section 12.2
+inline_07.vhd                                   entity inline_07                        test                            Section 12.2
+inline_08.vhd                                   entity inline_08                        test                            Section 12.2
+inline_09a.vhd                                  entity inline_09a                       test                            Section 12.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_timer_w_stim.vhd                             entity tb_timer_w_stim                  TB_timer_w_stim                 timer.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_01.vhd
new file mode 100644
index 0000000..b3ae86a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_01.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book
+
+entity and2 is
+  generic ( Tpd : time );
+  port ( a, b : in bit;  y : out bit );
+end entity and2;
+
+
+architecture simple of and2 is
+begin
+
+  and2_function :
+    y <= a and b after Tpd;
+
+end architecture simple;
+
+-- end code from book
+
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+library util;  use util.stimulus_generators.all;
+
+architecture test of inline_01 is
+
+  signal a1, b1, sig1, sig2, sig_out : bit;
+  signal test_vector : bit_vector(1 to 3);
+
+begin
+
+  -- code from book
+
+  gate1 : entity work.and2(simple)
+    generic map ( Tpd => 2 ns )
+    port map ( a => sig1,  b => sig2,  y => sig_out );
+
+  gate2 : entity work.and2(simple)
+    generic map ( Tpd => 3 ns )
+    port map ( a => a1,  b => b1,  y => sig1 );
+
+  -- end code from book
+
+  stimulus : all_possible_values ( bv => test_vector,
+				   delay_between_values => 10 ns );
+
+  (sig2, a1, b1) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_02a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_02a.vhd
new file mode 100644
index 0000000..fa207c9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_02a.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed; use ieee_proposed.electrical_systems.all;
+
+-- code from book
+                       
+entity resistor is
+  generic ( resistance : real );
+  port ( terminal pos, neg : electrical );
+end entity resistor;
+
+architecture simple of resistor is
+  quantity v across i through pos to neg;
+begin
+  v == i * resistance;
+end architecture simple;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_03.vhd
new file mode 100644
index 0000000..a86e7af
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_03.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_03 is
+end entity inline_03;
+
+
+
+architecture test of inline_03 is
+
+  signal clk, ready : bit;
+
+begin
+
+  dut1 : entity work.control_unit
+    -- code from book (in text)
+    generic map ( 200 ps, 1500 ps, false )
+    -- end code from book
+    port map ( clk, ready, open, open );
+
+  dut2 : entity work.control_unit
+    -- code from book (in text)
+    generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
+    -- end code from book
+    port map ( clk, ready, open, open );
+
+  dut3 : entity work.control_unit
+    -- code from book (in text)
+    generic map ( 200 ps, 1500 ps, debug => open )
+    -- end code from book
+    port map ( clk, ready, open, open );
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_05a.vhd
new file mode 100644
index 0000000..54ac662
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_05a.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_05a is
+end entity inline_05a;
+
+
+
+architecture test of inline_05a is
+
+  signal start_n, reset, time_out : std_ulogic;
+  terminal interval_rc : electrical;
+
+begin
+
+  -- code from book (in text)
+
+  interval_timer : entity work.timer(behavioral)
+    generic map ( threshold => 2.5,
+                  clamp_on_resistance => 0.01,
+                  clamp_off_resistance => 10.0E+6 )
+    port map ( trigger_n => start_n, reset => reset, q => time_out,
+               rc_ext => interval_rc );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd
new file mode 100644
index 0000000..baf7405
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_06.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book
+
+entity reg is
+  port ( d : in bit_vector;  q : out bit_vector;  -- . . . );
+  -- not in book
+         other_port : in bit := '0' );
+  -- end not in book
+end entity reg;
+
+-- end code from book
+
+
+architecture test of reg is
+begin
+  q <= d;
+end architecture test;
+
+
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+  -- code from book
+
+  signal small_data : bit_vector(0 to 7);
+  signal large_data : bit_vector(0 to 15);
+  -- . . .
+
+  -- end code from book
+
+
+begin
+
+  -- code from book
+
+  problem_reg : entity work.reg
+    port map ( d => small_data,  q => large_data, -- . . . );
+    -- not in book
+               other_port => open );
+    -- end not in book
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_07.vhd
new file mode 100644
index 0000000..c59b06c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_07.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book
+
+entity reg is
+  generic ( width : positive );
+  port ( d : in bit_vector(0 to width - 1);
+         q : out bit_vector(0 to width - 1);
+         -- . . . );
+  -- not in book
+         other_port : in bit := '0' );
+  -- end not in book
+end entity reg;
+
+-- end code from book
+
+
+architecture test of reg is
+begin
+  q <= d;
+end architecture test;
+
+
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_07 is
+
+  constant bus_size : positive := 16;
+
+  -- code from book
+
+  signal in_data, out_data : bit_vector(0 to bus_size - 1);
+  -- . . .
+
+  -- end code from book
+
+
+begin
+
+  -- code from book
+
+  ok_reg : entity work.reg
+    generic map ( width => bus_size )
+    port map ( d => in_data,  q => out_data, -- . . . );
+    -- not in book
+               other_port => open );
+    -- end not in book
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_08.vhd
new file mode 100644
index 0000000..b1fea64
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_08.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_08 is
+end entity inline_08;
+
+
+architecture test of inline_08 is
+
+  -- code from book
+
+  subtype state_vector is bit_vector(1 to 5);
+
+  -- end code from book
+
+  signal clk, reset : bit := '0';
+  signal word_in, word_out : bit_vector(0 to 31);
+  signal state_in, state_out : state_vector;
+
+begin
+
+  -- code from book
+
+  word_reg : entity work.reg(behavioral)
+    generic map ( width => 32 )
+    port map ( -- . . . );
+    -- not in book
+               d => word_in, q => word_out, clk => clk, reset => reset );
+    -- end not in book
+
+  state_reg : entity work.reg(behavioral)
+    generic map ( width => state_vector'length )
+    port map ( -- . . . );
+    -- not in book
+               d => state_in, q => state_out, clk => clk, reset => reset );
+
+  -- end code from book
+
+  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+
+  reset_gen : reset <= '1' after 80 ns, '0' after 105 ns;
+
+  stimulus_word : word_in <= X"11111111" after 25 ns,
+                             X"22222222" after 65 ns,
+		             X"33333333" after 85 ns,
+		             X"44444444" after 125 ns;
+
+  stimulus_state : state_in <= "00001" after 25 ns,
+                               "00010" after 65 ns,
+		               "00011" after 85 ns,
+		               "00100" after 125 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_09a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_09a.vhd
new file mode 100644
index 0000000..3ef59fb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/inline_09a.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity inline_09a is
+
+end entity inline_09a;
+
+
+architecture test of inline_09a is
+
+  -- code from book
+
+  constant num_sensors : positive := 8;
+  terminal sensors_raw,
+           sensors_buffered : electrical_vector(num_sensors - 1 downto 0);
+  -- ...
+
+  -- end code from book
+
+begin
+
+  -- code from book
+
+  buf_amps : entity work.multiple_opamp(ideal)
+    generic map ( size => num_sensors,
+                  gains => real_vector'(num_sensors - 1 downto 0 => 1.0) )
+    port map ( sensors_raw, sensors_buffered );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/multiple_opamp.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/multiple_opamp.vhd
new file mode 100644
index 0000000..ff3167b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/multiple_opamp.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity multiple_opamp is
+  generic ( size : positive;
+            gains : real_vector );
+  port ( terminal inputs, outputs : electrical_vector(1 to size) );
+end entity multiple_opamp;
+
+----------------------------------------------------------------
+
+architecture ideal of multiple_opamp is
+  
+  quantity v_in across i_in through inputs to electrical_ref;
+  quantity v_out across outputs to electrical_ref;
+  alias gains_alias : real_vector(1 to size) is gains;
+        
+begin
+  
+  assert gains'length = size
+    report "gains vector size differs from input/output size";
+        
+  amplify : procedural is
+  begin
+    for index in 1 to size loop
+      v_out(index) := v_in(index) * gains_alias(index);
+    end loop;
+  end procedural amplify;
+        
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd
new file mode 100644
index 0000000..181064e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/reg.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity reg is
+  generic ( width : positive );
+  port ( d :  in  bit_vector(0 to width - 1);
+         q :  out  bit_vector(0 to width - 1);
+         clk, reset : in bit );
+end entity reg;
+
+--------------------------------------------------
+
+architecture behavioral of reg is
+begin
+
+  behavior : process (clk, reset) is
+    constant zero : bit_vector(0 to width - 1) := (others => '0');
+  begin
+    if reset = '1' then
+      q <= zero;
+    elsif clk'event and clk = '1' then
+      q <= d;
+    end if;
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd
new file mode 100644
index 0000000..21d4b38
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/tb_timer_w_stim.vhd
@@ -0,0 +1,115 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
+library IEEE; use IEEE.std_logic_1164.all;
+
+entity tb_timer_w_stim is
+
+end tb_timer_w_stim;
+
+architecture TB_timer_w_stim of tb_timer_w_stim is
+    -- Component declarations
+    -- Signal declarations
+    terminal in_src, rc_ext : electrical;
+	signal trig, rst : std_ulogic;
+	signal tim_out :  std_ulogic;
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_constant(ideal)
+        generic map(
+            level => 5.0
+        )
+        port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+    R1 : entity work.resistor(simple)
+        generic map(
+            resistance => 10.0e3
+        )
+        port map(
+            pos => in_src,
+            neg => rc_ext
+        );
+    C1 : entity work.capacitor(ideal)
+        generic map(
+            cap => 10.0e-6
+        )
+        port map(
+            p1 => rc_ext,
+            p2 => electrical_ref
+        );
+    timer1 : entity work.timer(behavioral)
+        generic map(
+            threshold => 2.0,
+		clamp_on_resistance => 1.0e-3,
+		clamp_off_resistance => 1.0e6
+        )        
+		port map(
+      trigger_n => trig,
+	reset => rst,
+	q => tim_out,
+	rc_ext => rc_ext
+        );
+  -- rst
+    P_rst :
+    process
+    begin
+
+    wait for 0.000 ns;      rst <=  '1';
+      
+    wait for 1.000 ms;      rst <=  '0';
+      
+    wait for 100.000 ms;      rst <=  '1';
+    
+    wait for 1.000 ms;      rst <=  '0';
+      
+    wait;
+    end process;
+
+  -- trig
+    P_trig :
+    process
+    begin
+	wait for 0.0 ns;		trig <= '0';
+      
+    	wait for 5.000 ms;      trig <=  '1';
+      
+    	wait for 1.0 ms;      trig <=  '0';
+    
+	wait for 1.0 ms;      trig <=  '1';
+
+   	wait for 40.0 ms;      trig <=  '1';
+     
+   	wait for 1.0 ms;      trig <=  '0';
+    
+	wait for 1.0 ms;      trig <=  '1';
+
+  	wait for 40.0 ms;      trig <=  '1';
+    
+   	wait for 1.0 ms;      trig <=  '0';
+    
+   	wait for 1.0 ms;      trig <=  '1';
+      wait;
+    end process;
+end TB_timer_w_stim;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generics/timer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/timer.vhd
new file mode 100644
index 0000000..793a9e5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generics/timer.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity timer is
+  generic ( threshold : real;
+            clamp_on_resistance, clamp_off_resistance : real );
+  port ( signal trigger_n, reset : in std_ulogic;  signal q : out std_ulogic;
+         terminal rc_ext : electrical );
+end entity timer;
+
+----------------------------------------------------------------
+
+architecture behavioral of timer is
+  
+  quantity v_rc_ext across i_clamp through rc_ext to electrical_ref;
+  signal q_n : std_ulogic := '1';
+        
+begin
+  
+  if q_n = '1' use
+    i_clamp == v_rc_ext / clamp_on_resistance;
+  else
+    i_clamp == v_rc_ext / clamp_off_resistance;
+  end use;
+        
+  timer_state : process ( trigger_n, reset, v_rc_ext'above(threshold) ) is
+  begin
+    if reset = '1' or reset = 'H' or v_rc_ext > threshold then
+      q <= '0';  q_n <= '1';
+    elsif trigger_n = '0' or trigger_n = 'L' then
+      q <= '1';  q_n <= '0';
+    end if;
+  end process timer_state;
+        
+  break on q_n;
+        
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd
new file mode 100644
index 0000000..c4707cd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/circuit.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity circuit is
+  generic ( inpad_delay, outpad_delay : delay_length );
+  port ( in1, in2, in3 : in bit;  out1, out2 : out bit );
+end entity circuit;
+
+--------------------------------------------------
+
+architecture with_pad_delays of circuit is
+
+  component subcircuit is
+    port ( a, b : in bit;  y1, y2 : out bit );
+  end component subcircuit;
+
+  signal delayed_in1, delayed_in2, delayed_in3 : bit;
+  signal undelayed_out1, undelayed_out2 : bit;
+
+begin
+
+  input_delays : block is
+  begin
+    delayed_in1 <= in1 after inpad_delay;
+    delayed_in2 <= in2 after inpad_delay;
+    delayed_in3 <= in3 after inpad_delay;
+  end block input_delays;
+
+  functionality : block is
+    signal intermediate : bit;
+  begin
+    cell1 : component subcircuit
+      port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate );
+    cell2 : component subcircuit
+      port map ( intermediate, delayed_in3, undelayed_out2, open );
+  end block functionality;
+
+  output_delays : block is
+  begin
+    out1 <= undelayed_out1 after outpad_delay;
+    out2 <= undelayed_out2 after outpad_delay;
+  end block output_delays;
+
+end architecture with_pad_delays;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system-1.vhd
new file mode 100644
index 0000000..dded8af
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system-1.vhd
@@ -0,0 +1,99 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity computer_system_abstract is
+end entity computer_system_abstract;
+
+
+-- code from book
+
+architecture abstract of computer_system_abstract is
+
+  -- not in book
+
+  subtype word is bit_vector(31 downto 0);
+  type word_vector is array (natural range <>) of word;
+
+  function resolve_word ( drivers : word_vector ) return word is
+  begin
+    if drivers'length > 0 then
+      return drivers(drivers'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_word;
+
+  -- end not in book
+
+  -- . . .
+
+  signal address_bus : resolve_word word bus;
+  signal hold_req : bit;
+  -- . . .
+
+  -- not in book
+  signal clk : bit := '0';
+  -- end not in book
+
+begin
+
+  cpu : block is
+
+    signal guard : boolean := false;
+    signal cpu_internal_address : word;
+    -- . . .
+
+  begin
+
+    cpu_address_driver:
+      address_bus <= guarded cpu_internal_address;
+
+    -- . . .    -- other bus drivers
+
+    controller : process is
+      -- . . .
+    begin
+      -- . . .
+      -- . . .    -- determine when to disable cpu bus drivers
+      guard <= false;
+      wait on clk until hold_req = '0' and clk = '1';
+      guard <= true;  -- reenable cpu bus drivers
+      -- . . .
+      -- not in book
+      wait until clk = '1';
+      -- end not in book
+    end process controller;
+
+    -- . . .    -- cpu data-path processes
+
+    -- not in book
+    cpu_internal_address <= X"11111111";
+    -- end not in book
+
+  end block cpu;
+
+  -- . . .    -- blocks for DMA and other modules
+
+  -- not in book
+  clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+  -- end not in book
+
+end architecture abstract;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system.vhd
new file mode 100644
index 0000000..8b71df4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/computer_system.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+architecture top_level of computer_system is
+
+  function resolve_bits ( bits : bit_vector ) return bit is
+    variable result : bit := '0';
+  begin
+    for index in bits'range loop
+      result := result or bits(index);
+      exit when result = '1';
+    end loop;
+    return result;
+  end function resolve_bits;
+
+  signal write_en : resolve_bits bit bus;
+  -- . . .
+
+  -- not in book
+  constant Tpd : delay_length := 2 ns;
+  signal clock, hold_req : bit := '0';
+  -- end not in book
+
+begin
+
+  CPU : process is
+    -- . . .
+  begin
+    write_en <= '0' after Tpd;
+    -- . . .
+    loop
+      wait until clock = '1';
+      if hold_req = '1' then
+        write_en <= null after Tpd;
+        wait on clock until clock = '1' and hold_req = '0';
+        write_en <= '0' after Tpd;
+      end if;
+      -- . . .
+    end loop;
+  end process CPU;
+
+  -- . . .
+
+  -- not in book
+
+  clock_gen : clock <= '1' after 5 ns, '0' after 10 ns when clock = '0';
+
+  stimulus : hold_req <= '1' after 40 ns, '0' after 80 ns;
+
+  process is
+  begin
+    write_en <= null, '1' after 50 ns, '0' after 60 ns, null after 70 ns;
+    wait;
+  end process;
+
+  -- end not in book
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/data_logger.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/data_logger.vhd
new file mode 100644
index 0000000..22a42df
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/data_logger.vhd
@@ -0,0 +1,95 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity data_logger is
+end entity data_logger;
+
+
+-- code from book
+
+architecture high_level of data_logger is
+
+  subtype byte is bit_vector(7 downto 0);
+
+  type byte_array is array (integer range <>) of byte;
+
+  function resolver ( bytes : byte_array ) return byte is
+  begin
+    if bytes'length > 0 then
+      return bytes( bytes'left );
+    else
+      return X"00";
+    end if;
+  end function resolver;
+
+  subtype resolved_byte is resolver byte;
+
+  procedure reg ( signal clock, out_enable : in bit;
+                  signal d : in byte;
+                  signal q : out resolved_byte ) is
+    variable stored_byte : byte;
+  begin
+    loop
+      if clock = '1' then
+        stored_byte := d;
+      end if;
+      if out_enable = '1' then
+        q <= stored_byte;
+      else
+        q <= null;
+      end if;
+      wait on clock, out_enable, d;
+    end loop;
+  end procedure reg;
+
+  signal data_bus : resolved_byte bus;
+  -- . . .
+
+  -- not in book
+  signal a_reg_clk, b_reg_clk, a_reg_read, b_reg_read : bit := '0';
+  signal port_a, port_b : byte := X"00";
+  -- end not in book
+
+begin
+
+  a_reg : reg (a_reg_clk, a_reg_read, port_a, data_bus);
+
+  b_reg : reg (b_reg_clk, b_reg_read, port_b, data_bus);
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    port_a <= X"11";  a_reg_clk <= '1', '0' after 5 ns;  wait for 10 ns;
+    a_reg_read <= '1', '0' after 5 ns;  wait for 10 ns;
+    port_b <= X"21";  b_reg_clk <= '1', '0' after 5 ns;  wait for 10 ns;
+    b_reg_read <= '1', '0' after 5 ns;  wait for 10 ns;
+    a_reg_read <= '1', '0' after 5 ns;
+    b_reg_read <= '1', '0' after 5 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture high_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/example_entity.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/example_entity.vhd
new file mode 100644
index 0000000..819d6e4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/example_entity.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity example_entity is
+end entity example_entity;
+
+-- end not in book
+
+
+architecture contrived of example_entity is
+
+  constant sig_width : positive := 16;
+  signal s1, s2, s3 : bit_vector (0 to sig_width - 1);
+  signal sel : bit;
+  -- . . .
+
+begin
+
+  mux : block is
+    generic ( width : positive );
+    generic map ( width => sig_width );
+    port ( d0, d1 : in bit_vector(0 to width - 1);
+           y : out bit_vector(0 to width - 1);
+           sel : in bit);
+    port map ( d0 => s1, d1=> s2, y => s3, sel => sel );
+
+    constant zero : bit_vector(0 to width - 1) := ( others => '0' );
+    signal gated_d0, gated_d1 : bit_vector(0 to width - 1);
+
+  begin
+    gated_d0 <= d0 when sel = '0' else zero;
+    gated_d1 <= d1 when sel = '1' else zero;
+    y <= gated_d0 or gated_d1;
+  end block mux;
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    s1 <= X"1111";  s2 <= X"2222";  sel <= '0';  wait for 10 ns;
+    s1 <= X"0101";  wait for 10 ns;
+    s2 <= X"0202";  wait for 10 ns;
+    sel <= '1';  wait for 10 ns;
+    s1 <= X"0001";  wait for 10 ns;
+    s2 <= X"0002";  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture contrived;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/full.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/full.vhd
new file mode 100644
index 0000000..bb46694
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/full.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity real_subcircuit is
+  port ( a, b : in bit;  y1, y2 : out bit );
+end entity real_subcircuit;
+
+
+architecture basic of real_subcircuit is
+begin
+  y1 <= a and b after 10 ns;
+  y2 <= a nand b after 10 ns;
+end architecture basic;
+
+
+
+-- code from book
+
+configuration full of circuit is
+
+  for with_pad_delays  -- configure the architecture
+
+    for functionality    -- configure the block
+
+      for all : subcircuit
+        use entity work.real_subcircuit(basic);
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration full;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/index-ams.txt
new file mode 100644
index 0000000..fa600e3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/index-ams.txt
@@ -0,0 +1,34 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                          Chapter 19 - Guards and Blocks
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+computer_system.vhd                             entity computer_system                  top_level                       Figure 19-1
+processor.vhd                                   entity processor                        rtl                             Figure 19-2
+resolve.vhd                                     package resolve                         body                            Section 19.1, Figure 19-4
+tri_state_reg.vhd                               entity tri_state_reg                    behavioral                      Section 19.1, Figure 19-5
+data_logger.vhd                                 entity data_logger                      high_level                      Figure 19-6
+reg_read_selector.vhd                           entity reg_read_selector                test                            Figure 19-7
+processor_node.vhd                              entity processor_node                   dataflow                        Figure 19-8
+latch.vhd                                       entity latch                            behavioral                      Figure 19-9
+computer_system-1.vhd                           entity computer_system_abstract         abstract                        Figure 19-10
+sensor.vhd                                      entity sensor                           detailed_timing                 Figures 19-12, 19-13
+example_entity.vhd                              entity example_entity                   contrived                       Figure 19-14
+circuit.vhd                                     entity circuit                          with_pad_delays                 Figure 19-15
+full.vhd                                        entity real_subcircuit                  basic                           --
+--                                              configuration full                      --                              Figure 19-16
+inline_01.vhd                                   entity inline_01                        test                            Section 19.1
+inline_02.vhd                                   entity inline_02                        test                            Section 19.1
+inline_03.vhd                                   entity inline_03                        test                            Section 19.1
+inline_04.vhd                                   entity inline_04                        test                            Section 19.2
+inline_05.vhd                                   entity inline_05                        test                            Section 19.2
+inline_06.vhd                                   entity inline_06                        test                            Section 19.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_tri_state_reg.vhd                            entity tb_tri_state_reg                 test                            tri_state_reg.vhd
+tb_latch.vhd                                    entity tb_latch                         test                            latch.vhd
+tb_sensor.vhd                                   entity tb_sensor                        tb_sensor                       sensor.vhd
+tb_full.vhd                                     entity tb_full                          test                            full.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_01.vhd
new file mode 100644
index 0000000..27b98a6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_01.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+
+  function pulled_up ( drivers : bit_vector ) return bit is
+  begin
+    for index in drivers'range loop
+      if drivers(index) = '0' then
+        return '0';
+      end if;
+    end loop;
+    return '1';
+  end function pulled_up;
+
+  type state_type is (init_state, state1, state2, state3);
+  type state_vector is array (integer range <>) of state_type;
+
+  function resolve_state ( drivers : state_vector ) return state_type is
+  begin
+    return drivers(drivers'left);
+  end function resolve_state;
+
+
+  -- code from book:
+
+  signal interrupt_request : pulled_up bit bus;
+
+  signal stored_state : resolve_state state_type register := init_state;
+
+  -- end of code from book
+
+begin
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_02.vhd
new file mode 100644
index 0000000..1a2c612
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_02.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+
+  -- code from book:
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word;
+
+  signal s : resolve_words word bus;
+
+  -- end of code from book
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  constant T_delay : delay_length := 2 ns;
+
+begin
+
+
+  process is
+  begin
+
+    -- code from book (should fail)
+
+    s(0 to 15) <= X"003F" after T_delay;
+    s(16 to 31) <= null after T_delay;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_03.vhd
new file mode 100644
index 0000000..a1498ab
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_03.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+
+  function pulled_up ( drivers : bit_vector ) return bit is
+  begin
+    for index in drivers'range loop
+      if drivers(index) = '0' then
+        return '0';
+      end if;
+    end loop;
+    return '1';
+  end function pulled_up;
+
+  signal s : pulled_up bit bus;
+
+begin
+
+
+  process is
+  begin
+
+    s <= '1' after 11 ns, '0' after 16 ns, '1' after 18 ns,
+         null after 19 ns, '0' after 25 ns;
+    wait for 10 ns;
+
+    -- code from book:
+
+    s <= reject 3 ns inertial null after 10 ns;
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_04.vhd
new file mode 100644
index 0000000..eefda27
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_04.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_04 is
+
+end entity inline_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04 is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  subtype resolved_word is resolve_words word;
+
+  -- code from book:
+
+  signal memory_data_bus : resolved_word bus;
+  disconnect memory_data_bus : resolved_word after 3 ns;
+
+  -- end of code from book
+
+  signal mem_sel, mem_write : boolean;
+  signal cache_data_bus : word;
+
+begin
+
+
+  -- code from book:
+
+  mem_write_buffer : block (mem_sel and mem_write) is
+  begin
+    memory_data_bus <=
+      guarded reject 2 ns inertial cache_data_bus after 4 ns;
+  end block mem_write_buffer;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    cache_data_bus <= X"DDDDDDDD";
+    wait for 10 ns;
+    mem_sel <= true;  mem_write <= true;
+    wait for 10 ns;
+    cache_data_bus <= X"AAAAAAAA";
+    wait for 10 ns;
+    mem_sel <= false;  mem_write <= false;
+    wait for 10 ns;
+    cache_data_bus <= X"11111111";
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_05.vhd
new file mode 100644
index 0000000..5788454
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_05.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+architecture test of inline_05 is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  subtype resolved_word is resolve_words word;
+
+  -- code from book:
+
+  signal source_bus_1, source_bus_2 : resolved_word bus;
+  signal address_bus : resolved_word bus;
+
+  disconnect all : resolved_word after 2 ns;
+
+  -- end of code from book
+
+  signal s : word;
+  signal g : boolean;
+
+begin
+
+
+  b : block (g) is
+  begin
+    source_bus_1 <= guarded s after 4 ns;
+    source_bus_2 <= guarded s after 4 ns;
+    address_bus <= guarded s after 4 ns;
+  end block b;
+
+  stimulus : process is
+  begin
+    s <= X"DDDDDDDD";
+    wait for 10 ns;
+    g <= true;
+    wait for 10 ns;
+    s <= X"AAAAAAAA";
+    wait for 10 ns;
+    g <= false;
+    wait for 10 ns;
+    s <= X"11111111";
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_06.vhd
new file mode 100644
index 0000000..00534b5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/inline_06.vhd
@@ -0,0 +1,83 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+  subtype word is bit_vector(0 to 31);
+  type word_array is array (integer range <>) of word;
+
+  function resolve_words ( words : word_array ) return word is
+  begin
+    if words'length > 0 then
+      return words(words'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_words;
+
+  subtype resolved_word is resolve_words word;
+
+  signal source_bus_1, source_bus_2 : resolved_word bus;
+  signal address_bus : resolved_word bus;
+
+  -- code from book:
+
+  disconnect address_bus : resolved_word after 3 ns;
+
+  disconnect others : resolved_word after 2 ns;
+
+  -- end of code from book
+
+  signal s : word;
+  signal g : boolean;
+
+begin
+
+
+  b : block (g) is
+  begin
+    source_bus_1 <= guarded s after 4 ns;
+    source_bus_2 <= guarded s after 4 ns;
+    address_bus <= guarded s after 4 ns;
+  end block b;
+
+  stimulus : process is
+  begin
+    s <= X"DDDDDDDD";
+    wait for 10 ns;
+    g <= true;
+    wait for 10 ns;
+    s <= X"AAAAAAAA";
+    wait for 10 ns;
+    g <= false;
+    wait for 10 ns;
+    s <= X"11111111";
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/latch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/latch.vhd
new file mode 100644
index 0000000..aaceb5c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/latch.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity latch is
+  generic ( width : positive );
+  port ( enable : in bit;
+         d : in bit_vector(0 to width - 1);
+         q : out bit_vector(0 to width - 1) );
+end entity latch;
+
+--------------------------------------------------
+
+architecture behavioral of latch is
+begin
+
+  transfer_control : block ( enable = '1' ) is
+  begin
+    q <= guarded d;
+  end block transfer_control;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd
new file mode 100644
index 0000000..412f9e3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity processor is
+end entity processor;
+
+
+
+-- code from book
+
+architecture rtl of processor is
+
+  subtype word is bit_vector(0 to 31);
+  type word_vector is array (natural range <>) of word;
+
+  function resolve_unique ( drivers : word_vector ) return word is
+  begin
+    return drivers(drivers'left);
+  end function resolve_unique;
+
+  signal source1, source2 : resolve_unique word register;
+  -- . . .
+
+  -- not in book
+
+  type alu_op_type is (pass1, pass2, add, subtract);
+
+  procedure perform_alu_op ( signal alu_opcode : in alu_op_type;
+			     signal source1, source2 : in word;
+			     signal destination : out word;
+			     constant ignored : in integer := 0 ) is
+  begin
+    null;
+  end procedure perform_alu_op;
+
+  signal phase1, source1_reg_out_en,other_signal : bit;
+  signal alu_opcode : alu_op_type;
+  signal destination : word;
+
+  -- end not in book
+
+begin
+
+  source1_reg : process (phase1, source1_reg_out_en, -- . . .) is
+    -- not in book
+      other_signal) is
+    -- end not in book
+    variable stored_value : word;
+  begin
+    -- . . .
+    if source1_reg_out_en = '1' and phase1 = '1' then
+      source1 <= stored_value;
+      -- not in book
+      stored_value := not stored_value;
+      -- end not in book
+    else
+      source1 <= null;
+    end if;
+  end process source1_reg;
+
+  alu : perform_alu_op ( alu_opcode, source1, source2, destination, -- . . . );
+    -- not in book
+      open );
+    -- end not in book
+
+  -- . . .
+
+  -- not in book
+
+  process is
+  begin
+    wait for 10 ns;
+    source1_reg_out_en <= '1';
+    phase1 <= '1', '0' after 10 ns;
+    wait for 20 ns;
+    source1_reg_out_en <= '1';
+    phase1 <= '1', '0' after 10 ns;
+    wait;
+  end process;
+
+  -- end not in book
+
+end architecture rtl;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor_node.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor_node.vhd
new file mode 100644
index 0000000..20c7827
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/processor_node.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity processor_node is
+end entity processor_node;
+
+
+-- code from book
+
+architecture dataflow of processor_node is
+
+  -- not in book
+
+  subtype word is bit_vector(31 downto 0);
+  type word_vector is array (natural range <>) of word;
+
+  function resolve_unique ( drivers : word_vector ) return word is
+  begin
+    if drivers'length > 0 then
+      return drivers(drivers'left);
+    else
+      return X"00000000";
+    end if;
+  end function resolve_unique;
+
+  -- end not in book
+
+  signal address_bus : resolve_unique word bus;
+  -- . . .
+
+  -- not in book
+  signal cache_miss, dirty, replace_section,
+         snoop_hit, flag_update : bit := '0';
+  constant tag_section0 : bit_vector(11 downto 0) := X"000";
+  constant tag_section1 : bit_vector(11 downto 0) := X"001";
+  constant set_index : bit_vector(15 downto 0) := X"6666";
+  constant snoop_address : word := X"88888888";
+  -- end not in book
+
+begin
+
+  cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is
+  begin
+    address_bus <= guarded
+      tag_section0 & set_index & B"0000" when replace_section = '0' else
+      tag_section1 & set_index & B"0000";
+  end block cache_to_address_buffer;
+
+  snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is
+  begin
+    address_bus <= guarded snoop_address(31 downto 4) & B"0000";
+  end block snoop_to_address_buffer;
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    dirty <= '0';  cache_miss <= '1', '0' after 5 ns;  wait for 10 ns;
+    dirty <= '1';  cache_miss <= '1', '0' after 5 ns;  wait for 10 ns;
+    replace_section <= '1';
+    cache_miss <= '1', '0' after 5 ns;  wait for 10 ns;
+    flag_update <= '0'; snoop_hit <= '1', '0' after 5 ns;  wait for 10 ns;
+    flag_update <= '1'; snoop_hit <= '1', '0' after 5 ns;  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture dataflow;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd
new file mode 100644
index 0000000..569fe03
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity reg_read_selector is
+end entity reg_read_selector;
+
+
+architecture test of reg_read_selector is
+
+  constant reg0 : std_logic_vector(7 downto 0) := "00000000";
+  constant reg1 : std_logic_vector(7 downto 0) := "11111111";
+  signal dbus : std_logic_vector(7 downto 0);
+  signal reg_sel, read, reg_addr : X01 := '0';
+
+begin
+
+  -- code from book
+
+  reg_read_selector : block (reg_sel = '1' and read = '1') is
+  begin
+    dbus <= reg0 when guard and reg_addr = '0' else
+            reg1 when guard and reg_addr = '1' else
+            "ZZZZZZZZ";
+  end block reg_read_selector;
+
+  -- end code from book
+
+  stimulus : process is
+  begin
+    reg_sel <= '1';  wait for 10 ns;
+    read <= '1', '0' after 5 ns;  wait for 10 ns;
+    reg_sel <= '0';  wait for 10 ns;
+    read <= '1', '0' after 5 ns;  wait for 10 ns;
+    reg_addr <= '1';  wait for 10 ns;
+    reg_sel <= '1';  wait for 10 ns;
+    read <= '1', '0' after 5 ns;  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/resolve.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/resolve.vhd
new file mode 100644
index 0000000..4cdeeb5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/resolve.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package resolve is
+
+  -- code from book (in text)
+
+  subtype byte is bit_vector(0 to 7);
+  type byte_array is array (integer range <>) of byte;
+  function resolve ( bytes : byte_array ) return byte;
+  subtype resolved_byte is resolve byte;
+
+  -- end code from book
+
+end package resolve;
+
+
+package body resolve is
+
+  -- code from book
+
+  function resolve ( bytes : byte_array ) return byte is
+    variable result : byte := b"0000_0000";
+  begin
+    for index in bytes'range loop
+      result := result or bytes(index);
+    end loop;
+    return result;
+  end function resolve;
+
+  -- end code from book
+
+end package body resolve;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd
new file mode 100644
index 0000000..1a27df3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/sensor.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity sensor is
+
+  generic ( threshold : real;		-- voltage threshold
+            tipd_clk : delay_length;	-- input prop delay on clk
+            tipd_input : real;	        -- input prop delay on sensor input
+            topd_q : delay_length );	-- output prop delay on q
+
+  port ( terminal input : electrical;   -- sensor analog input
+         signal clk : in bit;	        -- edge–triggered clock input
+         signal q : out bit );	        -- sensor digital output
+
+end entity sensor;
+
+
+architecture detailed_timing of sensor is
+
+  quantity vin across input;	 -- analog input values
+  quantity v_delayed : voltage;	 -- input voltage delayed
+  signal clk_delayed : bit;	 -- clk input port delayed
+  signal q_int : bit;		 -- q output with zero delay
+
+begin
+
+  input_port_delay : block is
+  begin
+    v_delayed == vin'delayed(tipd_input);
+    clk_delayed <= clk'delayed(tipd_clk);
+  end block input_port_delay;
+
+  AD_conversion : block is
+  begin
+    q_int <= '1' when vin'above(threshold) else
+             '0';
+  end block AD_conversion;
+
+  output_port_delay : block is
+  begin
+    q <= q_int'delayed(topd_q);
+  end block output_port_delay;
+
+end architecture detailed_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_full.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_full.vhd
new file mode 100644
index 0000000..bc6300a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_full.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_full is
+end entity tb_full;
+
+
+library util;  use util.stimulus_generators.all;
+
+architecture test of tb_full is
+
+  signal in1, in2, in3, out1, out2 : bit;
+  signal test_vector : bit_vector(1 to 3);
+
+begin
+
+  dut : configuration work.full
+    generic map ( inpad_delay => 2 ns, outpad_delay => 3 ns )
+    port map ( in1 => in1, in2 => in2, in3 => in3, out1 => out1, out2 => out2 );
+
+  stimulus : all_possible_values ( test_vector, 50 ns );
+
+  (in1, in2, in3) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_latch.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_latch.vhd
new file mode 100644
index 0000000..e6fb12f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_latch.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_latch is
+end entity tb_latch;
+
+
+architecture test of tb_latch is
+
+ signal enable : bit := '0';
+ signal d, q : bit_vector(0 to 7);
+
+begin
+
+  dut : entity work.latch(behavioral)
+    generic map ( width => 8 )
+    port map ( enable => enable, d => d, q => q );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    d <= X"11";  wait for 10 ns;
+    enable <= '1';  wait for 10 ns;
+    d <= X"AA";  wait for 10 ns;
+    enable <= '0';  wait for 10 ns;
+    d <= X"00";  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_sensor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_sensor.vhd
new file mode 100644
index 0000000..de3d130
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_sensor.vhd
@@ -0,0 +1,84 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+use IEEE_proposed.mechanical_systems.all;
+
+entity tb_sensor is
+end tb_sensor;
+
+architecture tb_sensor of tb_sensor is
+    -- Component declarations
+    -- Signal declarations
+    terminal vin : electrical;
+    signal clk, q : bit;
+    signal  lclclkinitwire : bit := '0';
+begin
+    -- Signal assignments
+    -- Component instances
+    v1 : entity work.v_sine(ideal)
+        generic map(
+           freq => 10.0,
+           amplitude => 1.0
+        )
+        port map(
+            pos => vin,
+			neg => electrical_ref
+        );
+    sens1 : entity work.sensor_wa(detailed_timing)
+        generic map(
+		threshold => 0.25,
+            tipd_clk => 10 ns,
+            tipd_input => 20.0e-9,
+            topd_q => 10 ns
+        )
+        port map(
+            input => vin,
+            clk => clk,
+            q => q
+        );
+  -- ctrl
+    P_ctrl :
+    process
+    begin
+      if (lclclkinitwire /= '1')
+      then
+        clk <= '0';
+        wait for 1000.000 ns;
+      else
+        clk <= '1';
+        wait for 5240.000 ns;
+        clk <= '0';
+        wait for 34760.000 ns;
+      end if;
+    end process P_ctrl;
+
+    KillerProc :
+    process
+    begin
+      wait for 1 ns;
+      lclclkinitwire <= '1';
+      wait;
+    end process;
+end tb_sensor;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_tri_state_reg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_tri_state_reg.vhd
new file mode 100644
index 0000000..993cdf4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tb_tri_state_reg.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+use work.resolve.all;
+
+entity tb_tri_state_reg is
+end entity tb_tri_state_reg;
+
+
+architecture test of tb_tri_state_reg is
+
+  signal d1, d2, q : resolved_byte := X"00";
+  signal clk1, clk2, oe1, oe2 : bit := '0';
+
+begin
+
+  dut1 : entity work.tri_state_reg(behavioral)
+    port map ( d => d1, q => q, clock => clk1, out_enable => oe1 );
+
+  dut2 : entity work.tri_state_reg(behavioral)
+    port map ( d => d2, q => q, clock => clk2, out_enable => oe2 );
+
+  stimulus : process is
+  begin
+    d1 <= X"11";  clk1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    oe1 <= '1', '0' after 5 ns;  wait for 10 ns;
+    d2 <= X"21";  clk2 <= '1', '0' after 5 ns;  wait for 10 ns;
+    oe2 <= '1', '0' after 5 ns;  wait for 10 ns;
+    oe1 <= '1', '0' after 5 ns;
+    oe2 <= '1', '0' after 5 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd
new file mode 100644
index 0000000..8c0bd7a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/tri_state_reg.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+use work.resolve.all;
+
+-- code from book (in text)
+
+entity tri_state_reg is
+  port ( d : in resolved_byte;
+         q : out resolved_byte bus;
+         clock, out_enable : in bit );
+end entity tri_state_reg;
+
+-- end code from book
+
+
+
+-- code from book
+
+architecture behavioral of tri_state_reg is
+begin
+
+  reg_behavior : process (d, clock, out_enable) is
+    variable stored_byte : byte;
+  begin
+    if clock'event and clock = '1' then
+      stored_byte := d;
+    end if;
+    if out_enable = '1' then
+      q <= stored_byte;
+    else
+      q <= null;
+    end if;
+  end process reg_behavior;
+
+end architecture behavioral;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd
new file mode 100644
index 0000000..863f9e9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/SR_flipflop.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity SR_flipflop is
+  port ( s_n, r_n : in bit;  q, q_n : inout bit );
+
+begin
+
+  postponed process (q, q_n) is
+  begin
+    assert now = 0 fs or q = not q_n
+      report "implementation error: q /= not q_n";
+  end postponed process;
+
+end entity SR_flipflop;
+
+--------------------------------------------------
+
+architecture dataflow of SR_flipflop is
+begin
+
+  gate_1 : q <= s_n nand q_n;
+  gate_2 : q_n <= r_n nand q;
+
+end architecture dataflow;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/count2-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/count2-1.vhd
new file mode 100644
index 0000000..e810c66
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/count2-1.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity D_flipflop is
+  port ( clk, d : in bit;  q : buffer bit );
+end entity D_flipflop;
+
+
+architecture behavioral of D_flipflop is
+begin
+  q <= d when clk'event and clk = '1';
+end architecture behavioral;
+
+
+
+entity inverter is
+  port ( a : in bit;  y : out bit );
+end entity inverter;
+
+
+architecture behavioral of inverter is
+begin
+  y <= not a;
+end architecture behavioral;
+
+
+
+-- code from book
+
+entity count2 is
+  port ( clk : in bit;  q0, q1 : buffer bit );
+end entity count2;
+
+--------------------------------------------------
+
+architecture buffered_outputs of count2 is
+
+  component D_flipflop is
+    port ( clk, d : in bit;  q : buffer bit );
+  end component D_flipflop;
+
+  component inverter is
+    port ( a : in bit;  y : out bit );
+  end component inverter;
+
+  signal q0_n, q1_n : bit;
+
+begin
+
+  bit0 : component D_flipflop
+    port map ( clk => clk, d => q0_n, q => q0 );
+
+  inv0 : component inverter
+    port map ( a => q0, y => q0_n );
+
+  bit1 : component D_flipflop
+    port map ( clk => q0_n, d => q1_n, q => q1 );
+
+  inv1 : component inverter
+    port map ( a => q1, y => q1_n );
+
+end architecture buffered_outputs;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/index-ams.txt
new file mode 100644
index 0000000..9e0658e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/index-ams.txt
@@ -0,0 +1,25 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                        Chapter 24 - Miscellaneous Topics
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+count2-1.vhd                                    entity D_flipflop                       behavioral                      --
+--                                              entity inverter                         behavioral                      --
+--                                              entity count2                           buffered_outputs                Figure 24-1
+limit_checker.vhd                               package project_util                    body                            Section 24.2
+--                                              entity limit_checker                    behavioral                      Figure 24-2
+test_bench.vhd                                  entity random_source                    fudged                          Section 24.2
+--                                              entity test_bench                       random_test                     Figure 24-3
+processor.vhd                                   entity processor                        rtl                             Figure 24-4
+SR_flipflop.vhd                                 entity SR_flipflop                      dataflow                        Figure 24-5
+inline_01.vhd                                   entity inline_01                        test                            Section 24.2
+inline_02.vhd                                   entity inline_02                        test                            Section 24.3
+inline_04a.vhd                                  entity controller                       instrumented                    Section 24.4
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_count2.vhd                                   entity tb_count2                        test                            count2.vhd
+tb_limit_checker.vhd                            entity tb_limit_checker                 test                            limit_checker.vhd
+tb_SR_flipflop.vhd                              entity tb_SR_flipflop                   test                            SR_flipflop.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_01.vhd
new file mode 100644
index 0000000..2cc6670
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_01.vhd
@@ -0,0 +1,42 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+
+  type std_ulogic is (t1, t2, t3);
+  subtype std_logic is std_ulogic;
+
+  -- code from book:
+
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+
+  type std_logic_vector is array ( natural range <>) of std_logic;
+
+  -- end of code from book
+
+begin
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_02.vhd
new file mode 100644
index 0000000..e087f5b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_02.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+
+  signal s : bit;
+
+begin
+
+  -- code from book:
+
+  p : postponed process is
+    -- . . .
+  begin
+    -- . . .
+    wait until s = '1';
+    -- . . .       -- s may not be '1'!!
+    -- not in book
+    report bit'image(s);
+    wait;
+    -- end not in book
+  end postponed process p;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    s <= '1';
+    wait for 0 ns;
+    s <= '0';
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_04a.vhd
new file mode 100644
index 0000000..4e18034
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/inline_04a.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity controller is
+end entity controller;
+
+
+-- code from book
+
+architecture instrumented of controller is
+
+  shared variable operation_count : natural := 0;
+  -- . . .
+
+begin
+  -- . . .
+end architecture instrumented;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/limit_checker.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/limit_checker.vhd
new file mode 100644
index 0000000..dca1437
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/limit_checker.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+package project_util is
+
+  -- code from book (in text)
+
+  function "<" ( bv1, bv2 : bit_vector ) return boolean;
+
+  subtype word is std_logic_vector(31 downto 0);
+
+  -- end code from book
+
+end package project_util;
+
+
+package body project_util is
+
+  function "<" ( bv1, bv2 : bit_vector ) return boolean is
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+  begin
+    assert bv1'length = bv2'length
+      report "vectors are of different length in ""<"" comparison"
+      severity failure;
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return std.standard."<" ( tmp1, tmp2 );
+  end function "<";
+
+end package body project_util;
+
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.project_util.all;
+
+entity limit_checker is
+  port ( input, lower_bound, upper_bound : in word;
+         out_of_bounds : out std_logic );
+end entity limit_checker;
+
+--------------------------------------------------
+
+architecture behavioral of limit_checker is
+
+  subtype bv_word is bit_vector(31 downto 0);
+
+  function word_to_bitvector ( w : in word ) return bv_word is
+  begin
+    return To_bitvector ( w, xmap => '0' );
+  end function word_to_bitvector;
+
+begin
+
+  algorithm : process (input, lower_bound, upper_bound) is
+  begin
+    if "<" ( bv1 => word_to_bitvector(input),
+             bv2 => word_to_bitvector(lower_bound) )
+       or "<" ( bv1 => word_to_bitvector(upper_bound),
+                bv2 => word_to_bitvector(input) ) then
+      out_of_bounds <= '1';
+    else
+      out_of_bounds <= '0';
+    end if;
+  end process algorithm;
+
+end architecture behavioral;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/processor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/processor.vhd
new file mode 100644
index 0000000..94b5beb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/processor.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity processor is
+end entity processor;
+
+
+-- code from book
+
+architecture rtl of processor is
+
+  component latch is
+    generic ( width : positive );
+    port ( d : in std_ulogic_vector(0 to width - 1);
+           q : out std_ulogic_vector(0 to width - 1);
+           -- . . . );
+           -- not in book
+           other_port : in std_ulogic := '-' );
+           -- end not in book
+  end component latch;
+
+  component ROM is
+    port ( d_out : out std_ulogic_vector;  -- . . . );
+           -- not in book
+           other_port : in std_ulogic := '-' );
+           -- end not in book
+  end component ROM;
+
+  subtype std_logic_word is std_logic_vector(0 to 31);
+
+  signal source1, source2, destination : std_logic_word;
+  -- . . .
+
+begin
+
+  temp_register : component latch
+    generic map ( width => 32 )
+    port map ( d => std_ulogic_vector(destination),
+               std_logic_vector(q) => source1, -- . . . );
+               -- not in book
+               other_port => open );
+               -- end not in book
+
+  constant_ROM : component ROM
+    port map ( std_logic_word(d_out) => source2, -- . . . );
+               -- not in book
+               other_port => open );
+               -- end not in book
+
+  -- . . .
+
+end architecture rtl;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_SR_flipflop.vhd
new file mode 100644
index 0000000..f729f0b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_SR_flipflop.vhd
@@ -0,0 +1,41 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_SR_flipflop is
+end entity tb_SR_flipflop;
+
+
+architecture test of tb_SR_flipflop is
+
+  signal s_n, r_n, q, q_n : bit;
+
+begin
+
+  dut : entity work.SR_flipflop
+    port map ( s_n, r_n, q, q_n );
+
+  s_n <= '1',
+         '0' after 10 ns, '1' after 15 ns,
+         '0' after 30 ns, '1' after 40 ns;
+
+  r_n <= '0', '1' after 5 ns,
+         '0' after 20 ns, '1' after 25 ns,
+         '0' after 30 ns, '1' after 35 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_count2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_count2.vhd
new file mode 100644
index 0000000..7fd2e9c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_count2.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_count2 is
+end entity tb_count2;
+
+
+architecture test of tb_count2 is
+
+  signal clk, q0, q1 : bit;
+
+begin
+
+  dut : entity work.count2(buffered_outputs)
+    port map ( clk => clk, q0 => q0, q1 => q1 );
+
+  clk_gen : clk <= not clk after 10 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_limit_checker.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_limit_checker.vhd
new file mode 100644
index 0000000..42cebc0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/tb_limit_checker.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+use work.project_util.all;
+
+entity tb_limit_checker is
+end entity tb_limit_checker;
+
+
+architecture test of tb_limit_checker is
+
+  signal input : word;
+  signal out_of_bounds : std_logic;
+
+begin
+
+  dut : entity work.limit_checker(behavioral)
+    port map ( input => input,
+               lower_bound => X"FFFFFFF0", upper_bound => X"00000010",
+	       out_of_bounds => out_of_bounds );
+
+  stimulus : input <= X"00000000",
+                      X"00000008" after 10 ns,
+                      X"00000010" after 20 ns,
+                      X"00000018" after 30 ns,
+                      X"FFFFFFF8" after 40 ns,
+                      X"FFFFFFF0" after 50 ns,
+                      X"FFFFFF00" after 60 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/test_bench.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/test_bench.vhd
new file mode 100644
index 0000000..01a9235
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/misc-topics/test_bench.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book (in text)
+
+entity random_source is
+  generic ( min, max : natural;
+            seed : natural;
+            interval : delay_length );
+  port ( number : out natural );
+end entity random_source;
+
+-- end code from book
+
+
+architecture fudged of random_source is
+begin
+
+  process is
+    variable next_number : natural := seed;
+  begin
+    if next_number > max then
+      next_number := min;
+    end if;
+    number <= next_number;
+    next_number := next_number + 1;
+    wait for interval;
+  end process;
+
+end architecture fudged;
+
+
+
+entity test_bench is
+end entity test_bench;
+
+
+-- code from book
+
+architecture random_test of test_bench is
+
+  subtype bv11 is bit_vector(10 downto 0);
+
+  function natural_to_bv11 ( n : natural ) return bv11 is
+    variable result : bv11 := (others => '0');
+    variable remaining_digits : natural := n;
+  begin
+    for index in result'reverse_range loop
+      result(index) := bit'val(remaining_digits mod 2);
+      remaining_digits := remaining_digits / 2;
+      exit when remaining_digits = 0;
+    end loop;
+    return result;
+  end function natural_to_bv11;
+
+  signal stimulus_vector : bv11;
+  -- . . .
+
+begin
+
+  stimulus_generator : entity work.random_source
+    generic map ( min => 0, max => 2**10 - 1, seed => 0,
+                  interval => 100 ns )
+    port map ( natural_to_bv11(number) => stimulus_vector );
+
+  -- . . .
+
+end architecture random_test;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/address_decoder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/address_decoder.vhd
new file mode 100644
index 0000000..14c20b0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/address_decoder.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity address_decoder is
+  port ( addr : in work.cpu_types.address;
+         status : in work.cpu_types.status_value;
+         mem_sel, int_sel, io_sel : out bit );
+end entity address_decoder;
+
+--------------------------------------------------
+
+architecture functional of address_decoder is
+
+  constant mem_low : work.cpu_types.address := X"000000";
+  constant mem_high : work.cpu_types.address := X"EFFFFF";
+  constant io_low : work.cpu_types.address := X"F00000";
+  constant io_high : work.cpu_types.address := X"FFFFFF";
+
+begin
+
+  mem_decoder :
+    mem_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.fetch)
+                          or work.cpu_types."="(status, work.cpu_types.mem_read)
+                          or work.cpu_types."="(status, work.cpu_types.mem_write) )
+                        and addr >= mem_low
+                        and addr <= mem_high else
+               '0';
+
+  int_decoder :
+    int_sel <= '1' when work.cpu_types."="(status, work.cpu_types.int_ack) else
+               '0';
+
+  io_decoder :
+    io_sel <= '1' when ( work.cpu_types."="(status, work.cpu_types.io_read)
+                         or work.cpu_types."="(status, work.cpu_types.io_write) )
+                       and addr >= io_low
+                       and addr <= io_high else
+              '0';
+
+end architecture functional;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/analog_output_interface.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/analog_output_interface.vhd
new file mode 100644
index 0000000..604a989
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/analog_output_interface.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity analog_output_interface is
+  port ( signal wr : in std_ulogic;
+         signal data : std_ulogic_vector(7 downto 0);
+         terminal analog_out : electrical );
+end entity analog_output_interface;
+
+
+----------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity analog_interface_dac is
+  port ( signal d_in : std_ulogic_vector(7 downto 0);
+         terminal output : electrical;
+         terminal plus_supply, minus_supply : electrical );
+end entity analog_interface_dac;
+
+
+architecture macroblock of analog_interface_dac is
+
+begin
+
+end architecture macroblock;
+
+-- end not in book
+
+
+
+
+architecture structural of analog_output_interface is
+  
+  -- This architecture implements the interface as a register connected to a DAC.
+  -- NOTE: it uses the analog power supply terminals from clock_power_pkg
+  -- to supply the DAC.
+  
+  signal register_out : -- . . .;
+  -- not in book
+    std_ulogic_vector(7 downto 0);
+  -- end not in book
+
+begin
+
+  -- ...
+  
+  dac : entity work.analog_interface_dac(macroblock)
+    port map ( d_in => register_out, output => analog_out,
+               plus_supply => work.clock_power_pkg.analog_plus_supply,
+               minus_supply => work.clock_power_pkg.analog_ground );
+  
+end architecture structural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bit_vector_signed_arithmetic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bit_vector_signed_arithmetic.vhd
new file mode 100644
index 0000000..80ce3c0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bit_vector_signed_arithmetic.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package bit_vector_signed_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+  function "-" ( bv : bit_vector ) return bit_vector;
+
+  function "*" ( bv1, bv2 : bit_vector ) return bit_vector;
+
+  -- . . .
+
+end package bit_vector_signed_arithmetic;
+
+--------------------------------------------------
+
+-- not in book
+library ieee;  use ieee.numeric_bit.all;
+-- end not in book
+
+package body bit_vector_signed_arithmetic is
+
+  function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
+  -- not in book
+  begin
+    return bit_vector( "+"(signed(bv1), signed(bv2)) );
+  end function "+";
+  -- end not in book
+
+  function "-" ( bv : bit_vector ) return bit_vector is -- . . .
+  -- not in book
+  begin
+    return bit_vector( "-"(signed(bv)) );
+  end function "-";
+  -- end not in book
+
+  function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is
+    -- . . .
+  begin
+    -- not in book
+    -- . . .
+    return bit_vector( "*"(unsigned(bv1), unsigned(bv2)) );
+    -- end not in book
+  end function mult_unsigned;
+
+  function "*" ( bv1, bv2 : bit_vector ) return bit_vector is
+  begin
+    if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then
+      return mult_unsigned(bv1, bv2);
+    elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then
+      return -mult_unsigned(bv1, -bv2);
+    elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then
+      return -mult_unsigned(-bv1, bv2);
+    else
+      return mult_unsigned(-bv1, -bv2);
+    end if;
+  end function "*";
+
+  -- . . .
+
+end package body bit_vector_signed_arithmetic;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.vhd
new file mode 100644
index 0000000..fda35f2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/bus_sequencer-1.vhd
@@ -0,0 +1,79 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity bus_sequencer is
+  port ( rd, wr, sel, width, burst : out std_ulogic;
+         addr_low_4 : out std_ulogic_vector(3 downto 0);
+         ready : out std_ulogic;
+         control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+         analog_out_wr_0,
+         other_signal : out std_ulogic );
+end entity bus_sequencer;
+
+----------------
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity state_register is
+  port ( phi1, phi2 : in std_ulogic;
+         next_state : in std_ulogic_vector(3 downto 0);
+         current_state : out std_ulogic_vector(3 downto 0) );
+end entity state_register;
+
+
+architecture std_cell of state_register is
+
+begin
+
+end architecture std_cell;
+
+-- end not in book
+
+
+
+
+architecture fsm of bus_sequencer is
+
+  -- This architecture implements the sequencer as a finite-state machine.
+  -- NOTE: it uses the clock signals from clock_power_pkg to synchronize the fsm.
+
+  signal next_state_vector : -- . . .;
+  -- not in book
+    std_ulogic_vector(3 downto 0);
+  signal current_state_vector : std_ulogic_vector(3 downto 0);
+  -- end not in book
+
+begin
+
+  bus_sequencer_state_register : entity work.state_register(std_cell)
+    port map ( phi1 => work.clock_power_pkg.clock_phase1,
+               phi2 => work.clock_power_pkg.clock_phase2,
+               next_state => next_state_vector,
+               -- . . . );
+               -- not in book
+               current_state => current_state_vector );
+               -- end not in book
+
+  -- . . .
+
+end architecture fsm;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/clock_power_pkg.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/clock_power_pkg.vhd
new file mode 100644
index 0000000..2b7edcf
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/clock_power_pkg.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+package clock_power_pkg is
+
+  constant Tpw : delay_length := 4 ns;
+
+  signal clock_phase1, clock_phase2 : std_ulogic;
+
+  terminal analog_plus_supply, analog_ground : electrical;
+
+end package clock_power_pkg;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd
new file mode 100644
index 0000000..e2fbe12
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu-1.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity cpu is
+end entity cpu;
+
+-- end not in book
+
+
+
+
+architecture behavioral of cpu is
+begin
+
+  interpreter : process is
+
+    use work.cpu_types.all;
+
+    variable instr_reg : word;
+    variable instr_opcode : opcode;
+
+  begin
+    -- . . .    -- initialize
+    loop
+      -- . . .    -- fetch instruction
+      instr_opcode := extract_opcode ( instr_reg );
+      case instr_opcode is
+        when op_nop => null;
+        when op_breq => -- . . .
+        -- . . .
+        -- not in book
+        when others => null;
+        -- end not in book
+      end case;
+    end loop;
+  end process interpreter;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu.vhd
new file mode 100644
index 0000000..c961c88
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity cpu is
+end entity cpu;
+
+-- end not in book
+
+
+
+
+architecture behavioral of cpu is
+begin
+
+  interpreter : process is
+
+    variable instr_reg : work.cpu_types.word;
+    variable instr_opcode : work.cpu_types.opcode;
+
+  begin
+    -- . . .    -- initialize
+    loop
+      -- . . .    -- fetch instruction
+      instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
+      case instr_opcode is
+        when work.cpu_types.op_nop => null;
+        when work.cpu_types.op_breq => -- . . .
+        -- . . .
+        -- not in book
+        when others => null;
+        -- end not in book
+      end case;
+    end loop;
+  end process interpreter;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types-1.vhd
new file mode 100644
index 0000000..bf0bebd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types-1.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package cpu_types is
+
+  constant word_size : positive := 16;
+  constant address_size : positive := 24;
+
+  subtype word is bit_vector(word_size - 1 downto 0);
+  subtype address is bit_vector(address_size - 1 downto 0);
+
+  type status_value is ( halted, idle, fetch, mem_read, mem_write,
+                         io_read, io_write, int_ack );
+
+  subtype opcode is bit_vector(5 downto 0);
+
+  function extract_opcode ( instr_word : word ) return opcode;
+
+  constant op_nop : opcode := "000000";
+  constant op_breq : opcode := "000001";
+  constant op_brne : opcode := "000010";
+  constant op_add : opcode := "000011";
+  -- . . .
+
+end package cpu_types;
+
+
+
+-- not in book
+
+package body cpu_types is
+
+  function extract_opcode ( instr_word : word ) return opcode is
+  begin
+    return work.cpu_types.op_nop;
+  end function extract_opcode;
+
+end package body cpu_types;
+
+-- end not in book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types.vhd
new file mode 100644
index 0000000..10d497c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/cpu_types.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book
+
+package cpu_types is
+
+  constant word_size : positive := 16;
+  constant address_size : positive := 24;
+
+  subtype word is bit_vector(word_size - 1 downto 0);
+  subtype address is bit_vector(address_size - 1 downto 0);
+
+  type status_value is ( halted, idle, fetch, mem_read, mem_write,
+                         io_read, io_write, int_ack );
+
+end package cpu_types;
+
+-- end code from book
+
+
+
+package cpu_types_test is
+
+  constant status :
+    -- code from book
+    work.cpu_types.status_value
+    -- end code from book
+    :=
+    -- code from book
+    work.cpu_types.status_value'(work.cpu_types.fetch)
+    -- end code from book
+    ;
+
+end package cpu_types_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/index-ams.txt
new file mode 100644
index 0000000..4e8165c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/index-ams.txt
@@ -0,0 +1,39 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                              Chapter 10 - Packages
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+cpu_types.vhd                                   package cpu_types                       --                              Figure 10-1
+--                                              package cpu_types_test                  --                              Section 10.1
+address_decoder.vhd                             entity address_decoder                  functional                      Figure 10-2
+clock_power_pkg.vhd                             package clock_power_pkg                 --                              Figure 10-3
+io_controller-1.vhd                             entity phase_locked_clock_gen           std_cell                        --
+--                                              entity regulator                        device_level                    --
+--                                              entity io_controller                    top_level                       Figure 10-4
+bus_sequencer-1.vhd                             entity state_register                   std_cell                        --
+--                                              entity bus_sequencer                    fsm                             Figure 10-5
+analog_output_interface.vhd                     entity analog_interface_dac             macroblock                      --
+--                                              entity analog_output_interface          structural                      Figure 10-6
+cpu_types-1.vhd                                 package cpu_types                       --                              Figure 10-7
+cpu.vhd                                         entity cpu                              behavioral                      Figure 10-8
+bit_vector_signed_arithmetic.vhd                package bit_vector_signed_arithmetic    body                            Figure 10-9
+cpu-1.vhd                                       entity cpu                              behavioral                      Figure 10-10
+lessthan.vhd                                    entity lessthan                         test                            Figure 10-11
+test_alu.vhd                                    package alu_types                       --                              Section 10.5
+--                                              entity ALU                              structural                      Section 10.5
+--                                              test_alu                                random_test                     Figure 10-14
+inline_01.vhd                                   entity inline_01                        test                            Section 10.1
+inline_02.vhd                                   package inline_02                       body                            Section 10.1
+inline_03.vhd                                   entity inline_03                        test                            Section 10.3
+inline_04a.vhd                                  entity inline_04a                       test                            Section 10.3
+inline_05.vhd                                   entity logic_block                      --                              Section 10.3
+inline_06.vhd                                   entity inline_06                        test                            Section 10.4
+inline_08.vhd                                   package inline_08                       --                              Section 10.5
+inline_09.vhd                                   entity inline_09                        test                            Section 10.5
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_address_decoder.vhd                          entity tb_address_decoder               test                            address_decoder.vhd
+tb_bit_vector_signed_arithmetic.vhd             tb_bit_vector_signed_arithmetic         test                            bit_vector_signed_arithmetic.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_01.vhd
new file mode 100644
index 0000000..641ba6b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_01.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+library ieee;
+
+architecture test of inline_01 is
+
+begin
+
+  process_1_a : process is
+
+    -- code from book:
+
+    variable stored_state : ieee.std_logic_1164.std_ulogic;
+
+    -- end of code from book
+
+  begin
+
+    wait;
+  end process process_1_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_02.vhd
new file mode 100644
index 0000000..0019d2e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_02.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package inline_02 is
+
+  -- code from book
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  procedure add ( a, b : in word32;
+                  result : out word32;  overflow : out boolean );
+
+  function "<" ( a, b : in word32 ) return boolean;
+
+  constant max_buffer_size : positive;
+
+  -- end code from book
+
+end package inline_02;
+
+
+package body inline_02 is
+
+  -- code from book
+
+  constant max_buffer_size : positive := 4096;
+
+  -- end code from book
+
+end package body inline_02;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd
new file mode 100644
index 0000000..640c35e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_03.vhd
@@ -0,0 +1,69 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+library ieee;
+
+architecture test of inline_03 is
+begin
+
+
+  process_3_a : process is
+
+    -- code from book:
+
+    use work.cpu_types;
+
+    variable data_word : cpu_types.word;
+    variable next_address : cpu_types.address;
+
+    -- end of code from book
+
+  begin
+   wait;
+  end process process_3_a;
+
+
+  ----------------
+
+
+  process_3_b : process is
+
+    -- code from book:
+
+    use work.cpu_types.word, work.cpu_types.address;
+
+    variable data_word : word;
+    variable next_address : address;
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process process_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_04a.vhd
new file mode 100644
index 0000000..6d695d0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_04a.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+----------------------------------------------------------------
+
+
+library ieee_proposed;
+
+architecture test of inline_04a is
+begin
+
+
+  block_3_c : block is
+
+    -- code from book:
+
+    use ieee_proposed.electrical_systems.all;
+
+    -- end of code from book
+
+  begin
+  end block block_3_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_05.vhd
new file mode 100644
index 0000000..c8b9f9e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_05.vhd
@@ -0,0 +1,25 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.std_ulogic;
+
+entity logic_block is
+  port ( a, b : in std_ulogic;
+         y, z : out std_ulogic );
+end entity logic_block;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_06.vhd
new file mode 100644
index 0000000..c6e2f6e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_06.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book:
+
+library std, work;  use std.standard.all;
+
+-- end of code from book
+
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+begin
+
+
+  process_4_a : process is
+
+    constant a : integer := 10;
+    constant b : integer := 20;
+    variable result : boolean;
+
+  begin
+
+    -- code from book:
+
+    result := std.standard."<" ( a, b );
+
+    -- end of code from book
+
+    wait;
+  end process process_4_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_08.vhd
new file mode 100644
index 0000000..9c6bdf4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_08.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package inline_08 is
+
+  -- code from book
+
+  procedure uniform ( variable seed1, seed2 : inout positive;
+                      variable x : out real);
+
+  -- end code from book
+
+end package inline_08;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_09.vhd
new file mode 100644
index 0000000..c26ede7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/inline_09.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+begin
+
+  process_5_c : process is
+
+    use ieee.math_real.all;
+
+    -- code from book
+
+    type complex is record
+        re : real;    -- Real part
+        im : real;    -- Imaginary part
+      end record;
+
+    subtype positive_real is real range 0.0 to real'high;
+    subtype principal_value is real range -math_pi to math_pi;
+
+    type complex_polar is record
+        mag : positive_real;      -- Magnitude
+        arg : principal_value;    -- Angle in radians; -math_pi is illegal
+      end record;
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process process_5_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd
new file mode 100644
index 0000000..56fb1fa
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/io_controller-1.vhd
@@ -0,0 +1,116 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity phase_locked_clock_gen is
+  port ( ref_clock : in std_ulogic;
+         phi1, phi2 : out std_ulogic );
+end entity phase_locked_clock_gen;
+
+
+architecture std_cell of phase_locked_clock_gen is
+
+  use work.clock_power_pkg.Tpw;
+
+begin
+
+  phi1_gen : phi1 <= '1', '0' after Tpw when rising_edge(ref_clock);
+
+  phi2_gen : phi2 <= '1', '0' after Tpw when falling_edge(ref_clock);
+
+end architecture std_cell;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity regulator is
+  port ( terminal plus_in, minus_in, plus_out, minus_out : electrical );
+end entity regulator;
+
+
+architecture device_level of regulator is
+begin
+end architecture device_level;
+
+
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+-- end not in book
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity io_controller is
+  port ( signal ref_clock : in std_ulogic;
+         terminal ext_supply, ext_ground : electrical;  -- . . . );
+         -- not in book
+         other_port : in std_ulogic );
+         -- end not in book
+end entity io_controller;
+
+--------------------------------------------------
+
+architecture top_level of io_controller is
+
+  -- . . .
+
+  -- not in book
+  signal rd, wr, sel, width, burst : std_ulogic;
+  signal addr : std_ulogic_vector(3 downto 0);
+  signal ready : std_ulogic;
+  signal control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+         other_signal : std_ulogic;
+
+  signal analog_out_wr_0 : std_ulogic;
+  signal internal_data : std_ulogic_vector(7 downto 0);
+  terminal analog_out_0 : electrical;
+  -- end not in book
+
+begin
+
+  internal_clock_gen : entity work.phase_locked_clock_gen(std_cell)
+    port map ( ref_clock => ref_clock,
+               phi1 => work.clock_power_pkg.clock_phase1,
+               phi2 => work.clock_power_pkg.clock_phase2 );
+  
+  internal_analog_regulator : entity work.regulator(device_level)
+    port map ( plus_in => ext_supply, minus_in => ext_ground,
+               plus_out => work.clock_power_pkg.analog_plus_supply,
+               minus_out => work.clock_power_pkg.analog_ground );
+
+  the_bus_sequencer : entity work.bus_sequencer(fsm)
+    port map ( rd, wr, sel, width, burst, addr(3 downto 0), ready,
+               control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
+               analog_out_wr_0, -- . . . );
+               -- not in book
+               other_signal );
+               -- not in book
+
+  analog_output_interface_0 : entity work.analog_output_interface(structural)
+    port map ( analog_out_wr_0, internal_data(7 downto 0), analog_out_0 );
+  
+  -- . . .
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/lessthan.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/lessthan.vhd
new file mode 100644
index 0000000..4a97200
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/lessthan.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity lessthan is
+end entity lessthan;
+
+
+
+architecture test of lessthan is
+
+  -- code from book
+
+  function "<" ( a, b : bit_vector ) return boolean is
+    variable tmp1 : bit_vector(a'range) := a;
+    variable tmp2 : bit_vector(b'range) := b;
+  begin
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    return std.standard."<" ( tmp1, tmp2 );
+  end function "<";
+
+  -- end code from book
+
+  signal a, b : bit_vector(7 downto 0);
+  signal result : boolean;
+
+begin
+
+  dut : result <= a < b;
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    a <= X"02";  b <= X"04";  wait for 10 ns;
+    a <= X"02";  b <= X"02";  wait for 10 ns;
+    a <= X"02";  b <= X"01";  wait for 10 ns;
+    a <= X"02";  b <= X"FE";  wait for 10 ns;
+    a <= X"FE";  b <= X"02";  wait for 10 ns;
+    a <= X"FE";  b <= X"FE";  wait for 10 ns;
+    a <= X"FE";  b <= X"FC";  wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_address_decoder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_address_decoder.vhd
new file mode 100644
index 0000000..7be5b79
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_address_decoder.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_address_decoder is
+end entity tb_address_decoder;
+
+
+architecture test of tb_address_decoder is
+
+  use work.cpu_types.all;
+
+  signal addr : address := X"000000";
+  signal status : status_value := idle;
+  signal mem_sel, int_sel, io_sel : bit;
+
+begin
+
+  dut : entity work.address_decoder
+    port map ( addr => addr, status => status,
+               mem_sel => mem_sel, int_sel => int_sel, io_sel => io_sel );
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    addr <= X"EFFFFF";    wait for 10 ns;
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    addr <= X"F00000";    wait for 10 ns;
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    addr <= X"FFFFFF";    wait for 10 ns;
+    status <= fetch;      wait for 10 ns;
+    status <= mem_read;   wait for 10 ns;
+    status <= mem_write;  wait for 10 ns;
+    status <= io_read;    wait for 10 ns;
+    status <= io_write;   wait for 10 ns;
+    status <= int_ack;    wait for 10 ns;
+    status <= idle;       wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_bit_vector_signed_arithmetic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_bit_vector_signed_arithmetic.vhd
new file mode 100644
index 0000000..130f1dc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/tb_bit_vector_signed_arithmetic.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_bit_vector_signed_arithmetic is
+end entity tb_bit_vector_signed_arithmetic;
+
+
+architecture test of tb_bit_vector_signed_arithmetic is
+begin
+
+  stimulus : process is
+    use work.bit_vector_signed_arithmetic.all;
+    use std.textio.all;
+    variable L : line;
+  begin
+    write(L, X"0002" + X"0005");
+    writeline(output, L);
+    write(L, X"0002" + X"FFFE");
+    writeline(output, L);
+    write(L, - X"0005");
+    writeline(output, L);
+    write(L, - X"FFFE");
+    writeline(output, L);
+    write(L, X"0002" * X"0005");
+    writeline(output, L);
+    write(L, X"0002" * X"FFFD");
+    writeline(output, L);
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/packages/test_alu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/test_alu.vhd
new file mode 100644
index 0000000..3ed4d1a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/packages/test_alu.vhd
@@ -0,0 +1,101 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;
+
+package alu_types is
+
+  -- code from book (in text)
+
+  use ieee.numeric_bit.all;
+  subtype ALU_func is unsigned(3 downto 0);
+  subtype data_word is unsigned(15 downto 0);
+  -- . . .
+
+  -- end code from book (in text)
+
+end package alu_types;
+
+
+
+use work.alu_types.all;
+
+-- code from book (in text)
+
+entity ALU is
+  port ( a, b : in data_word;  func : in ALU_func;
+         result : out data_word;  carry : out bit );
+end entity ALU;
+
+-- end code from book (in text)
+
+
+
+architecture structural of ALU is
+begin
+end architecture structural;
+
+
+entity test_ALU is
+end entity test_ALU;
+
+
+
+library ieee;
+use work.alu_types.all;
+
+-- code from book
+
+architecture random_test of test_ALU is
+
+  use ieee.numeric_bit.all;
+  use ieee.math_real.uniform;
+
+  signal a, b, result : data_word;
+  signal func : ALU_func;
+  signal carry : bit;
+
+begin
+
+  dut : entity work.ALU(structural)
+    port map ( a, b, func, result, carry );
+
+  stimulus : process is
+    variable seed1, seed2 : positive := 1;
+    variable a_real, b_real, func_real : real;
+  begin
+    wait for 100 ns;
+    uniform ( seed1, seed2, a_real );
+    uniform ( seed1, seed2, b_real );
+    uniform ( seed1, seed2, func_real );
+    a <= to_unsigned( natural(a_real * real(2**integer'(data_word'length)) - 0.5),
+                      data_word'length );
+    b <= to_unsigned( natural(b_real * real(2**integer'(data_word'length)) - 0.5),
+                      data_word'length );
+    func <= to_unsigned( natural(func_real
+                                 * real(2**integer'(ALU_func'length)) - 0.5),
+                         ALU_func'length );
+  end process stimulus;
+
+  -- . . .  --verification process to check result and carry
+
+end architecture random_test;
+
+-- end code from book
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd
new file mode 100644
index 0000000..82c5826
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/MVL4.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package MVL4 is
+
+  type MVL4_ulogic is ('X', '0', '1', 'Z');  -- unresolved logic type
+
+  type MVL4_ulogic_vector is array (natural range <>) of MVL4_ulogic;
+
+  function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
+                        return MVL4_ulogic;
+
+  subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
+
+  -- code from book (in text)
+
+  type MVL4_logic_vector is array (natural range <>) of MVL4_logic;
+
+  -- end code from book
+
+end package MVL4;
+
+--------------------------------------------------
+
+package body MVL4 is
+
+  type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
+
+  constant resolution_table : table :=
+    --  'X'  '0'  '1'  'Z'
+    --  ------------------
+    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
+      ( 'X', '0', 'X', '0' ),    -- '0'
+      ( 'X', 'X', '1', '1' ),    -- '1'
+      ( 'X', '0', '1', 'Z' ) );  -- 'Z'
+
+  function resolve_MVL4 ( contribution : MVL4_ulogic_vector )
+                        return MVL4_ulogic is
+    variable result : MVL4_ulogic := 'Z';
+  begin
+    for index in contribution'range loop
+      result := resolution_table(result, contribution(index));
+    end loop;
+    return result;
+  end function resolve_MVL4;
+
+end package body MVL4;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd
new file mode 100644
index 0000000..8efe10e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/bus_based_system.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity bus_module is
+  port ( synch : inout std_ulogic;  -- . . . );
+  -- not in book
+         other_port : in std_ulogic := 'U' );
+  -- end not in book
+end entity bus_module;
+
+--------------------------------------------------
+
+-- not in book
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity bus_based_system is
+end entity bus_based_system;
+
+-- end not in book
+
+
+architecture top_level of bus_based_system is
+
+  signal synch_control : std_logic;
+  -- . . .
+
+begin
+
+  synch_control_pull_up : synch_control <= 'H';
+
+  bus_module_1 : entity work.bus_module(behavioral)
+    port map ( synch => synch_control, -- . . . );
+      -- not in book
+               other_port => open );
+      -- end not in book
+
+  bus_module_2 : entity work.bus_module(behavioral)
+    port map ( synch => synch_control, -- . . . );
+      -- not in book
+               other_port => open );
+      -- end not in book
+
+  -- . . .
+
+end architecture top_level;
+
+
+
+architecture behavioral of bus_module is
+begin
+
+  behavior : process is
+    -- . . .
+    -- not in book
+    constant Tdelay_synch : delay_length := 10 ns;
+    constant wait_delay : delay_length := 100 ns;
+    -- end not in book
+  begin
+    synch <= '0'  after Tdelay_synch;
+    -- . . .
+    -- not in book
+    wait for wait_delay;
+    -- end not in book
+    -- ready to start operation
+    synch <= 'Z' after Tdelay_synch;
+    wait until synch = 'H';
+    -- proceed with operation
+    -- . . .
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd
new file mode 100644
index 0000000..6bd829c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/computer_system.vhd
@@ -0,0 +1,118 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+use work.words.all;
+
+entity cpu is
+  port ( address : out uword;  data : inout uword;  -- . . . );
+  -- not in book
+         other_port : in X01Z := 'Z' );
+  -- end not in book
+end entity cpu;
+
+
+-- not in book
+
+architecture behavioral of cpu is
+begin
+end architecture behavioral;
+
+-- end not in book
+
+
+--------------------------------------------------
+
+use work.words.all;
+
+entity memory is
+  port ( address : in uword;  data : inout uword; -- . . . );
+  -- not in book
+         other_port : in X01Z := 'Z' );
+  -- end not in book
+end entity memory;
+
+
+-- not in book
+
+architecture behavioral of memory is
+begin
+end architecture behavioral;
+
+-- end not in book
+
+
+--------------------------------------------------
+
+
+-- not in book
+
+use work.words.all;
+
+entity ROM is
+  port ( a : in uword;  d : out ubyte;  other_port : in X01Z := 'Z' );
+end entity ROM;
+
+
+architecture behavioral of ROM is
+begin
+end architecture behavioral;
+
+
+entity computer_system is
+end entity computer_system;
+
+-- end not in book
+
+
+
+architecture top_level of computer_system is
+
+  use work.words.all;
+
+  signal address : uword;
+  signal data : word;
+  -- . . .
+
+begin
+
+  the_cpu : entity work.cpu(behavioral)
+    port map ( address, data, -- . . . );
+    -- not in book
+               open );
+    -- end not in book
+
+  the_memory : entity work.memory(behavioral)
+    port map ( address, data, -- . . . );
+    -- not in book
+               open );
+    -- end not in book
+
+  -- . . .
+
+  -- code from book (in text)
+
+--   boot_rom : entity work.ROM(behavioral)
+--     port map ( a => address, d => data(24 to 31), -- . . . );  -- illegal
+--     -- not in book
+--                other_port => open );
+--     -- end not in book
+
+  -- end code from book
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/index-ams.txt
new file mode 100644
index 0000000..433c310
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/index-ams.txt
@@ -0,0 +1,30 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                          Chapter 15 - Resolved Signals
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+resolve_tri_state_logic.vhd                     entity resolve_tri_state_logic          test                            Section 15.1, Figure 15-1
+MVL4.vhd                                        package MVL4                            body                            Section 15.1, Figure 15-2
+tri_state_buffer.vhd                            entity tri_state_buffer                 behavioral                      Figure 15.3
+misc_logic.vhd                                  entity misc_logic                       gate_level                      Figure 15.4
+words.vhd                                       package words                           body                            Figure 15.5
+computer_system.vhd                             entity cpu                              behavioral                      Figure 15.6
+--                                              entity memory                           behavioral                      Figure 15.6
+--                                              entity ROM                              behavioral                      --
+--                                              entity computer_system                  top_level                       Figure 15.6
+memory_system.vhd                               entity ROM                              behavioral                      Figure 15-7
+--                                              entity SIMM                             behavioral                      Figure 15-7
+--                                              entity memory_system                    detailed                        Figure 15-7
+resolved.vhd                                    package resolved                        body                            Figure 15-8
+bus_based_system.vhd                            entity bus_module                       behavioral                      Figures 15-9, 15-10
+--                                              entity bus_based_system                 top_level                       Figure 15-9
+synchronize.vhd                                 package synchronize                     body                            Figure 15-12
+synchronized_module.vhd                         entity synchronized_module              test                            Figure 15-13
+inline_01.vhd                                   entity inline_01                        test                            Section 15.1
+inline_02.vhd                                   package inline_02                       test                            Section 15.2
+inline_03.vhd                                   entity IO_section                       --                              Section 15.3
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd
new file mode 100644
index 0000000..84df14a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_01.vhd
@@ -0,0 +1,76 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+
+  type MVL4_ulogic is ('X', '0', '1', 'Z');  -- unresolved logic type
+
+  -- code from book:
+
+  type small_int is range 1 to 4;
+  type small_array is array (small_int range <>) of -- . . . ;
+    -- not in book
+    MVL4_ulogic;
+    -- end not in book
+
+  -- end of code from book
+
+  type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
+  constant resolution_table : table :=
+    --  'X'  '0'  '1'  'Z'
+    --  ------------------
+    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
+      ( 'X', '0', 'X', '0' ),    -- '0'
+      ( 'X', 'X', '1', '1' ),    -- '1'
+      ( 'X', '0', '1', 'Z' ) );  -- 'Z'
+
+  function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is
+    variable result : MVL4_ulogic := 'Z';
+  begin
+    for index in contribution'range loop
+      result := resolution_table(result, contribution(index));
+    end loop;
+    return result;
+  end function resolve_MVL4;
+
+  subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
+
+  signal s : MVL4_logic;
+
+begin
+
+  driver_1 : s <= 'Z';
+
+  driver_2 : s <= 'Z';
+
+  driver_3 : s <= 'Z';
+
+  driver_4 : s <= 'Z';
+
+  driver_5 : s <= 'Z';
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd
new file mode 100644
index 0000000..5c5fb5d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_02.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package inline_02 is
+
+  -- code from book
+
+  type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
+
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+
+  function resolved ( s : std_ulogic_vector ) return std_ulogic;
+
+  subtype std_logic is resolved std_ulogic;
+
+  type std_logic_vector is array ( natural range <>) of std_logic;
+
+  subtype X01 is resolved std_ulogic range 'X' to '1'; -- ('X','0','1')
+  subtype X01Z is resolved std_ulogic range 'X' to 'Z'; -- ('X','0','1','Z')
+  subtype UX01 is resolved std_ulogic range 'U' to '1'; -- ('U','X','0','1')
+  subtype UX01Z is resolved std_ulogic range 'U' to 'Z'; -- ('U','X','0','1','Z')
+
+  -- end code from book
+
+end package inline_02;
+
+
+
+package body inline_02 is
+
+  function resolved ( s : std_ulogic_vector ) return std_ulogic is
+  begin
+    return 'U';
+  end function resolved;
+
+end package body inline_02;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd
new file mode 100644
index 0000000..c459a8f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/inline_03.vhd
@@ -0,0 +1,27 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity IO_section is
+  port ( data_ack : inout std_logic;  -- . . . );
+  -- not in book
+         other_port : in std_ulogic := 'U' );
+  -- end not in book
+end entity IO_section;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd
new file mode 100644
index 0000000..53f6797
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/memory_system.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+use work.MVL4.all;
+
+entity ROM is
+  port ( a : in MVL4_ulogic_vector(15 downto 0);
+         d : inout MVL4_logic_vector(7 downto 0);
+         rd : in MVL4_ulogic );
+end entity ROM;
+
+-- not in book
+architecture behavioral of ROM is
+begin
+end architecture behavioral;
+-- end not in book
+
+--------------------------------------------------
+
+use work.MVL4.all;
+
+entity SIMM is
+  port ( a : in MVL4_ulogic_vector(9 downto 0);
+         d : inout MVL4_logic_vector(31 downto 0);
+         ras, cas, we, cs : in MVL4_ulogic );
+end entity SIMM;
+
+-- not in book
+architecture behavioral of SIMM is
+begin
+end architecture behavioral;
+-- end not in book
+
+--------------------------------------------------
+
+-- not in book
+
+use work.MVL4.all;
+
+entity memory_subsystem is
+end entity memory_subsystem;
+
+-- end not in book
+
+architecture detailed of memory_subsystem is
+
+  signal internal_data : MVL4_logic_vector(31 downto 0);
+  -- . . .
+
+  -- not in book
+  signal internal_addr : MVL4_ulogic_vector(31 downto 0);
+  signal main_mem_addr : MVL4_ulogic_vector(9 downto 0);
+  signal ROM_select : MVL4_ulogic;
+  -- end not in book
+
+begin
+
+  boot_ROM : entity work.ROM(behavioral)
+    port map ( a => internal_addr(15 downto 0),
+               d => internal_data(7 downto 0),
+               rd => ROM_select );
+
+  main_mem : entity work.SIMM(behavioral)
+    port map ( a => main_mem_addr, d => internal_data, -- . . . );
+    -- not in book
+               ras => '0', cas => '0', we => '0', cs => '0' );
+    -- end not in book
+
+  -- . . .
+
+end architecture detailed;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd
new file mode 100644
index 0000000..34b6f84
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/misc_logic.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity misc_logic is
+end entity misc_logic;
+
+-- end not in book
+
+
+
+use work.MVL4.all;
+
+architecture gate_level of misc_logic is
+
+  signal src1, src1_enable : MVL4_ulogic;
+  signal src2, src2_enable : MVL4_ulogic;
+  signal selected_val : MVL4_logic;
+  -- . . .
+
+begin
+
+  src1_buffer : entity work.tri_state_buffer(behavioral)
+    port map ( a => src1, enable => src1_enable, y => selected_val );
+
+  src2_buffer : entity work.tri_state_buffer(behavioral)
+    port map ( a => src2, enable => src2_enable, y => selected_val );
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    wait for 10 ns;
+    src1_enable <= '0';  src2_enable <= '0';  wait for 10 ns;
+    src1 <= '0';         src2 <= '1';         wait for 10 ns;
+    src1_enable <= '1';                       wait for 10 ns;
+    src1 <= 'Z';                              wait for 10 ns;
+    src1 <= '1';                              wait for 10 ns;
+    src1_enable <= '0';                       wait for 10 ns;
+                         src2_enable <= '1';  wait for 10 ns;
+                         src2 <= 'Z';         wait for 10 ns;
+                         src2 <= '0';         wait for 10 ns;
+                         src2_enable <= '0';  wait for 10 ns;
+    src1_enable <= '1';  src2_enable <= '1';  wait for 10 ns;
+    src1 <= '0';                              wait for 10 ns;
+    src1 <= 'X';                              wait for 10 ns;
+    src1 <= '1';         src2 <= '1';         wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture gate_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd
new file mode 100644
index 0000000..233339a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolve_tri_state_logic.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity resolve_tri_state_logic is
+end entity resolve_tri_state_logic;
+
+
+
+architecture test of resolve_tri_state_logic is
+
+  -- code from book (in text)
+
+  type tri_state_logic is ('0', '1', 'Z');
+
+  type tri_state_logic_array is array (integer range <>) of tri_state_logic;
+
+  -- end code from book
+
+
+  -- code from book
+
+  function resolve_tri_state_logic ( values : in tri_state_logic_array )
+                                   return tri_state_logic is
+    variable result : tri_state_logic := 'Z';
+  begin
+    for index in values'range loop
+      if values(index) /= 'Z' then
+        result := values(index);
+      end if;
+    end loop;
+    return result;
+  end function resolve_tri_state_logic;
+
+  -- end code from book
+
+
+  -- code from book (in text)
+
+  signal s1 : resolve_tri_state_logic tri_state_logic;
+
+  subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
+
+  signal s2, s3 : resolved_logic;
+
+  -- end code from book
+
+begin
+
+  source_1 : s1 <= 'Z',
+                   '0' after 10 ns,
+                   'Z' after 20 ns,
+                   '1' after 30 ns,
+                   'Z' after 40 ns,
+	           '1' after 200 ns,
+	           'Z' after 220 ns;
+
+  source_2 : s1 <= 'Z',
+                   '0' after 110 ns,
+                   'Z' after 120 ns,
+                   '1' after 130 ns,
+                   'Z' after 140 ns,
+	           '1' after 200 ns,
+	           '0' after 210 ns,
+	           'Z' after 220 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd
new file mode 100644
index 0000000..21db858
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/resolved.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package resolved is
+
+  type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');
+  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
+  function resolved ( s : std_ulogic_vector ) return std_ulogic;
+
+end package resolved;
+
+
+package body resolved is
+
+  -- code from book
+
+  type stdlogic_table is array (std_ulogic, std_ulogic) of std_ulogic;
+  constant resolution_table : stdlogic_table :=
+    -- ---------------------------------------------
+    --  'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
+    -- ---------------------------------------------
+    ( ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ),  --  'U'
+      ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),  --  'X'
+      ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ),  --  '0'
+      ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ),  --  '1'
+      ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ),  --  'Z'
+      ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ),  --  'W'
+      ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ),  --  'L'
+      ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ),  --  'H'
+      ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' )   --  '-'
+    );
+
+  function resolved ( s : std_ulogic_vector ) return std_ulogic is
+    variable result : std_ulogic := 'Z';  -- weakest state default
+  begin
+    if s'length = 1 then
+      return s(s'low);
+    else
+      for i in s'range loop
+        result := resolution_table(result, s(i));
+      end loop;
+    end if;
+    return result;
+  end function resolved;
+
+  -- end code from book
+
+end package body resolved;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd
new file mode 100644
index 0000000..1591023
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronize.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+package synchronize is
+
+  procedure init_synchronize ( signal synch : out std_logic );
+
+  procedure begin_synchronize ( signal synch : inout std_logic;
+                                Tdelay : in delay_length := 0 fs );
+
+  procedure end_synchronize ( signal synch : inout std_logic;
+                              Tdelay : in delay_length := 0 fs );
+
+end package synchronize;
+
+
+
+package body synchronize is
+
+  -- code from book
+
+  procedure init_synchronize ( signal synch : out std_logic ) is
+  begin
+    synch <= '0';
+  end procedure init_synchronize;
+
+  procedure begin_synchronize ( signal synch : inout std_logic;
+                                Tdelay : in delay_length := 0 fs ) is
+  begin
+    synch <= 'Z' after Tdelay;
+    wait until synch = 'H';
+  end procedure begin_synchronize;
+
+  procedure end_synchronize ( signal synch : inout std_logic;
+                              Tdelay : in delay_length := 0 fs ) is
+  begin
+    synch <= '0' after Tdelay;
+    wait until synch = '0';
+  end procedure end_synchronize;
+
+  -- end code from book
+
+end package body synchronize;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd
new file mode 100644
index 0000000..99649ca
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/synchronized_module.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity synchronized_module is
+end entity synchronized_module;
+
+
+
+architecture test of synchronized_module is
+
+  use work.synchronize.all;
+
+  signal barrier : std_logic;
+
+begin
+
+  pullup : barrier <= 'H';
+
+  -- code from book
+
+  synchronized_module : process is
+    -- . . .
+  begin
+    init_synchronize(barrier);
+    -- . . .
+    loop
+      -- . . .
+      begin_synchronize(barrier);
+      -- . . .    -- perform operation, synchronized with other processes
+      end_synchronize(barrier);
+      -- . . .
+    end loop;
+  end process synchronized_module;
+
+  -- end code from book
+
+  another_synchronized_module : process is
+  begin
+    init_synchronize(barrier);
+    loop
+      wait for 10 ns;
+      begin_synchronize(barrier);
+      -- . . .    -- perform operation, synchronized with other processes
+      end_synchronize(barrier);
+    end loop;
+  end process another_synchronized_module;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd
new file mode 100644
index 0000000..a4b3d1d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/tri_state_buffer.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+use work.MVL4.all;
+
+entity tri_state_buffer is
+  port ( a, enable : in MVL4_ulogic;  y : out MVL4_ulogic );
+end entity tri_state_buffer;
+
+--------------------------------------------------
+
+architecture behavioral of tri_state_buffer is
+begin
+
+  y <= 'Z' when enable = '0' else
+       a   when enable = '1' and (a = '0' or a = '1') else
+       'X';
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd
new file mode 100644
index 0000000..d5ccffc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/resolution/words.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package words is
+
+  type X01Z is ('X', '0', '1', 'Z');
+  type uword is array (0 to 31) of X01Z;
+
+  type uword_vector is array (natural range <>) of uword;
+
+  function resolve_word ( contribution : uword_vector ) return uword;
+
+  subtype word is resolve_word uword;
+
+  -- not in book
+  type ubyte is array (0 to 7) of X01Z;
+  -- end not in book
+
+end package words;
+
+--------------------------------------------------
+
+package body words is
+
+  type table is array (X01Z, X01Z) of X01Z;
+
+  constant resolution_table : table :=
+    --  'X'  '0'  '1'  'Z'
+    --  ------------------
+    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
+      ( 'X', '0', 'X', '0' ),    -- '0'
+      ( 'X', 'X', '1', '1' ),    -- '1'
+      ( 'X', '0', '1', 'Z' ) );  -- 'Z'
+
+  function resolve_word ( contribution : uword_vector ) return uword is
+    variable result : uword := (others => 'Z');
+  begin
+    for index in contribution'range loop
+      for element in uword'range loop
+        result(element) :=
+          resolution_table( result(element), contribution(index)(element) );
+      end loop;
+    end loop;
+    return result;
+  end function resolve_word;
+
+end package body words;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/ent.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/ent.vhd
new file mode 100644
index 0000000..9815cbd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/ent.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity ent is
+
+end entity ent;
+
+architecture sample of ent is
+
+  constant pi : real := 3.14159;
+
+begin
+
+  process is
+    variable counter : integer;
+  begin
+    -- . . .         --  statements using pi and counter
+  end process;
+
+end architecture sample;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/index-ams.txt
new file mode 100644
index 0000000..7140942
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/index-ams.txt
@@ -0,0 +1,14 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                             Chapter 2 - Scalar Data
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure
+-----------                                     ------------                            --------------                  -------
+ent.vhd                                         entity ent                              sample                          Figure 2-1
+int_types.vhd                                   package int_types                       --                              Section 2.2
+small_adder.vhd                                 entity small_adder                      --                              Section 2.2
+inline_01a.vhd                                  entity inline_01a                       test                            Sections 2.1-2.5
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                   TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/inline_01a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/inline_01a.vhd
new file mode 100644
index 0000000..f9c854b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/inline_01a.vhd
@@ -0,0 +1,784 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01a is
+
+end entity inline_01a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01a is
+begin
+
+
+  section_1_a : process is
+
+    -- code from book:
+
+    constant number_of_bytes : integer := 4;
+    constant number_of_bits : integer := 8 * number_of_bytes;
+    constant e : real := 2.718281828;
+    constant prop_delay : time := 3 ns;
+    constant q : real :=  1.60218E-19;
+    constant resistivity : real := 2.5E5;
+
+    --
+
+    variable index : integer := 0;
+    variable temperature : real;
+    variable start, finish : time := 0 ns; 
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process section_1_a;
+
+
+  ----------------
+
+
+  section_1_b : process is
+
+    -- code from book:
+
+    variable start : time := 0 ns; 
+    variable finish : time := 0 ns; 
+
+    -- end of code from book
+
+    variable program_counter : integer;
+    variable index : integer;
+    variable resonance_frequency : real;
+    constant L, C : real := 0.0;
+
+  begin
+
+    -- code from book:
+
+    program_counter := 0;
+    index := index + 1;
+    resonance_frequency := L * C;
+
+    -- end of code from book
+
+    wait;
+  end process section_1_b;
+
+
+  ----------------
+
+
+  section_2_a : process is
+
+    -- code from book:
+
+    type apples is range 0 to 100;
+    type oranges is range 0 to 100;
+
+    --
+
+    type day_of_month is range 0 to 31;
+    type year is range 0 to 2100;
+
+    variable today : day_of_month := 9;
+    variable start_year : year := 1987;
+
+    --
+
+    constant number_of_bits : integer := 32;
+    type bit_index is range 0 to number_of_bits - 1;
+
+    --
+
+    type set_index_range is range 21 downto 11;
+    type mode_pos_range is range 5 to 7;
+    variable set_index : set_index_range;
+    variable mode_pos : mode_pos_range;
+
+    --
+
+    type input_level is range -10.0 to +10.0;
+    type probability is range 0.0 to 1.0;
+
+    --
+
+    variable input_A : input_level;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    -- error: Incompatible types for assignment
+    -- start_year := today;
+
+    -- end of code from book
+
+    wait;
+  end process section_2_a;
+
+
+  ----------------
+
+
+  section_2_b : process is
+
+    -- code from book:
+
+    type resistance is range 0 to 1E9
+      units
+        ohm;
+      end units resistance;
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process section_2_b;
+
+
+  ----------------
+
+
+  section_2_c : process is
+
+    -- code from book:
+
+    type resistance is range 0 to 1E9
+      units
+        ohm;
+        kohm = 1000 ohm;
+        Mohm = 1000 kohm;
+      end units resistance;
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process section_2_c;
+
+
+  ----------------
+
+
+  section_2_d : process is
+
+    -- code from book:
+
+    type length is range 0 to 1E9
+      units
+        um;			-- primary unit: micron
+        mm = 1000 um;		-- metric units
+        m = 1000 mm;
+        inch = 25400 um;        -- imperial units
+        foot = 12 inch;
+      end units length;
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process section_2_d;
+
+
+  ----------------
+
+
+  section_2_e : process is
+
+    -- code from book:
+
+    -- type time is range implementation_defined
+    type time is range integer'low to integer'high
+      units
+        fs;
+        ps = 1000 fs;
+        ns = 1000 ps;
+        us = 1000 ns;
+        ms = 1000 us;
+        sec = 1000 ms;
+        min = 60 sec;
+        hr = 60 min;
+      end units;
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process section_2_e;
+
+
+  ----------------
+
+
+  section_2_f : process is
+
+    -- code from book:
+
+    type transistor_region is (linear, saturation);
+
+    --
+
+    type octal_digit is ('0', '1', '2', '3', '4', '5', '6', '7');
+
+    --
+
+    variable transistor_state : transistor_region;
+    variable last_digit : octal_digit := '0';
+
+    --
+
+    type logic_level is (unknown, low, undriven, high);
+    variable control : logic_level;
+    type water_level is (dangerously_low, low, ok);
+    variable water_sensor : water_level;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    transistor_state := linear;
+    last_digit := '7';
+
+    --
+
+    control := low;
+    water_sensor := low;
+
+    -- end of code from book
+
+    wait;
+  end process section_2_f;
+
+
+  ----------------
+
+
+  section_2_g : process is
+
+    -- code from book:
+
+    type severity_level is (note, warning, error, failure);
+    type file_open_status is (open_ok, status_error, name_error, mode_error);
+    type file_open_kind is (read_mode, write_mode, append_mode);
+    type domain_type is (quiescent_domain, time_domain, frequency_domain);
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process section_2_g;
+
+
+  ----------------
+
+
+  section_2_g1 : process is
+
+    -- code from book:
+
+    type character is (
+      nul, soh,  stx,  etx,  eot,  enq,  ack,  bel,
+      bs,  ht,  lf,  vt,  ff,  cr, so, si,
+      dle,  dc1,  dc2,  dc3,  dc4,  nak,  syn,  etb,
+      can,  em,  sub,  esc,  fsp,  gsp,  rsp,  usp,
+      ' ',  '!',  '"',  '#',  '$',  '%',  '&',  ''',
+      '(',  ')',  '*',  '+',  ',',  '-',  '.',  '/',
+      '0',  '1',  '2',  '3',  '4',  '5',  '6',  '7',
+      '8',  '9',  ':',  ';',  '<',  '=',  '>',  '?',
+      '@',  'A',  'B',  'C',  'D',  'E',  'F',  'G',
+      'H',  'I',  'J',  'K',  'L',  'M',  'N',  'O',
+      'P',  'Q',  'R',  'S',  'T',  'U',  'V',  'W',
+      'X',  'Y',  'Z',  '[',  '\',  ']',  '^',  '_', 
+      '`',  'a',  'b',  'c',  'd',  'e',  'f',  'g',
+      'h',  'i',  'j',  'k',  'l',  'm',  'n',  'o',
+      'p',  'q',  'r',  's',  't',  'u',  'v',  'w',
+      'x',  'y',  'z',  '{',  '|',  '}',  '~',  DEL,
+      c128,  c129,  c130,  c131,  c132,  c133,  c134,  c135,
+      c136,  c137,  c138,  c139,  c140,  c141,  c142,  c143,
+      c144,  c145,  c146,  c147,  c148,  c149,  c150,  c151,
+      c152,  c153,  c154,  c155,  c156,  c157,  c158,  c159,
+      ' ',  '¡',  '¢',  '£',  '¤',  '¥',  '¦',  '§',
+      '¨',  '©',  'ª',  '«',  '¬',  '­',  '®',  '¯',
+      '°',  '±',  '²',  '³',  '´',  'µ',  '¶',  '·',
+      '¸',  '¹',  'º',  '»',  '¼',  '½',  '¾',  '¿',
+      'À',  'Á',  'Â',  'Ã',  'Ä',  'Å',  'Æ',  'Ç',
+      'È',  'É',  'Ê',  'Ë',  'Ì',  'Í',  'Î',  'Ï',
+      'Ð',  'Ñ',  'Ò',  'Ó',  'Ô',  'Õ',  'Ö',  '×',
+      'Ø',  'Ù',  'Ú',  'Û',  'Ü',  'Ý',  'Þ',  'ß',
+      'à',  'á',  'â',  'ã',  'ä',  'å',  'æ',  'ç',
+      'è',  'é',  'ê',  'ë',  'ì',  'í',  'î',  'ï',
+      'ð',  'ñ',  'ò',  'ó',  'ô',  'õ',  'ö',  '÷',
+      'ø',  'ù',  'ú',  'û',  'ü',  'ý',  'þ',  'ÿ');
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process section_2_g1;
+
+
+  ----------------
+
+
+  section_2_h : process is
+
+    -- code from book:
+
+    variable cmd_char, terminator : character;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    cmd_char := 'P';
+    terminator := cr;
+
+    -- end of code from book
+
+    wait;
+  end process section_2_h;
+
+
+  ----------------
+
+
+  section_2_i : process is
+
+    -- code from book:
+
+    type boolean is (false, true);
+
+    --
+
+    type bit is ('0', '1');
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process section_2_i;
+
+
+  ----------------
+
+
+  section_2_j : process is
+
+    variable write_enable_n, select_reg_n, write_reg_n : bit;
+
+  begin
+
+    -- code from book:
+
+    write_reg_n := not ( not write_enable_n and not select_reg_n );
+
+    -- end of code from book
+
+    wait;
+  end process section_2_j;
+
+
+  ----------------
+
+
+  section_2_k : process is
+
+    -- code from book:
+
+    type std_ulogic is ( 'U',	-- Uninitialized
+                         'X',	-- Forcing Unknown
+                         '0',	-- Forcing zero
+                         '1',	-- Forcing one
+                         'Z',	-- High Impedance
+                         'W',	-- Weak Unknown
+                         'L',	-- Weak zero
+                         'H',	-- Weak one
+                         '-' );	-- Don't care
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process section_2_k;
+
+
+  ----------------
+
+
+  section_3_a : process is
+
+    -- code from book:
+
+    subtype small_int is integer range -128 to 127;
+
+    --
+
+    variable deviation : small_int;
+    variable adjustment : integer;
+
+    --
+
+    subtype bit_index is integer range 31 downto 0;
+
+    -- end of code from book
+
+  begin
+
+    deviation := 0;
+    adjustment := 0;
+
+    -- code from book:
+
+    deviation := deviation + adjustment;
+
+    -- end of code from book
+
+    wait;
+  end process section_3_a;
+
+
+  ----------------
+
+
+  section_3_b : process is
+
+    constant highest_integer : integer := integer'high;
+
+    constant highest_time : time := time'high;
+
+    -- code from book:
+
+    subtype pressure is real tolerance "default_pressure";
+
+    --
+
+    subtype natural is integer range 0 to highest_integer;
+    subtype positive is integer range 1 to highest_integer;
+
+    --
+
+    subtype delay_length is time range 0 fs to highest_time;
+
+    -- end of code from book
+
+  begin
+     wait;
+ end process section_3_b;
+
+
+  ----------------
+
+
+  section_3_c : process is
+
+    -- code from book:
+
+    type logic_level is (unknown, low, undriven, high);
+    type transistor_state is (unknown, unsaturated, saturated);
+
+    --
+
+    subtype valid_level is logic_level range low to high;
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process section_3_c;
+
+
+  ----------------
+
+
+  section_4_a : block is
+
+    -- code from book:
+
+    subtype voltage is real tolerance "default_voltage";
+    subtype current is real tolerance "default_current";
+
+    nature electrical is
+      voltage across
+      current through
+      electrical_ref reference;
+    
+    --
+
+    terminal in_plus, in_minus, preamp_out : electrical;
+
+    --
+
+    quantity signal_level across in_plus to in_minus;
+    quantity output_level across output_current through preamp_out;
+
+    -- end of code from book
+
+  begin
+  end block section_4_a;
+
+
+  ----------------
+
+
+  section_4_b : block is
+
+    -- code from book:
+
+    subtype temperature is real tolerance "default_temperature";
+    subtype heat_flow is real tolerance "default_heat_flow";
+    subtype cryo_temp is real tolerance "default_temperature";
+    subtype cryo_flow is real tolerance "default_heat_flow";
+
+    nature thermal is
+      temperature across
+      heat_flow through
+      thermal_ref reference;
+
+    nature cryogenic is
+      cryo_temp across
+      cryo_flow through
+      cryo_ref reference;
+
+    --
+
+    subtype illuminance is real tolerance "default_illuminance";
+    subtype optic_flux is real tolerance "default_optic_flux";
+
+    nature radiant is
+      illuminance across
+      optic_flux through
+      radiant_ref reference;
+
+    -- end of code from book
+
+  begin
+  end block section_4_b;
+
+
+  ----------------
+
+
+  section_4_c : block is
+
+    subtype voltage is real tolerance "default_voltage";
+    subtype current is real tolerance "default_current";
+
+    nature electrical is
+      voltage across
+      current through
+      electrical_ref reference;
+    
+    -- code from book:
+
+    subnature coarse_electrical is electrical
+      tolerance "coarse_voltage" across "coarse_current" through;
+
+    terminal supply_plus, supply_minus : coarse_electrical;
+    terminal bias : electrical;
+
+    quantity bias_pullup_v across supply_plus to bias;
+    quantity bias_pulldown_v across bias to supply_minus;
+
+    -- end of code from book
+
+  begin
+  end block section_4_c;
+
+
+----------------
+
+
+  section_5_a : process is
+
+    -- code from book:
+
+    type resistance is range 0 to 1E9
+      units
+        ohm;
+        kohm = 1000 ohm;
+        Mohm = 1000 kohm;
+      end units resistance;
+
+    type set_index_range is range 21 downto 11;
+
+    type logic_level is (unknown, low, undriven, high);
+
+    -- end of code from book
+
+  begin
+
+    -- output from vsim: "2000"
+    report resistance'image(2 kohm);
+
+    -- code from book:
+
+    assert resistance'left = 0 ohm;
+    assert resistance'right = 1E9 ohm;
+    assert resistance'low = 0 ohm;
+    assert resistance'high = 1E9 ohm;
+    assert resistance'ascending = true;
+    assert resistance'image(2 kohm) = "2000 ohm";
+    assert resistance'value("5 Mohm") = 5_000_000 ohm;
+
+    assert set_index_range'left = 21;
+    assert set_index_range'right = 11;
+    assert set_index_range'low = 11;
+    assert set_index_range'high = 21;
+    assert set_index_range'ascending = false;
+    assert set_index_range'image(14) = "14";
+    assert set_index_range'value("20") = 20;
+
+    assert logic_level'left = unknown;
+    assert logic_level'right = high;
+    assert logic_level'low = unknown;
+    assert logic_level'high = high;
+    assert logic_level'ascending = true;
+    assert logic_level'image(undriven) = "undriven";
+    assert logic_level'value("Low") = low;
+
+    --
+
+    assert logic_level'pos(unknown) = 0;
+    assert logic_level'val(3) = high;
+    assert logic_level'succ(unknown) = low;
+    assert logic_level'pred(undriven) = low;
+
+    --
+
+    assert time'pos(4 ns) = 4_000_000;
+
+    -- end of code from book
+
+    wait;
+  end process section_5_a;
+
+
+  ----------------
+
+
+  section_5_b : process is
+
+    -- code from book:
+
+    type length is range integer'low to integer'high
+      units
+        mm;
+      end units length;
+
+    type area is range integer'low to integer'high
+      units
+        square_mm;
+      end units area;
+
+    --
+
+    variable L1, L2 : length;
+    variable A : area;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    -- error: No feasible entries for infix op: "*"
+    -- A := L1 * L2;      -- this is incorrect
+
+    --
+
+    A := area'val( length'pos(L1) * length'pos(L2) );
+
+    -- end of code from book
+
+    wait;
+  end process section_5_b;
+
+
+  ----------------
+
+
+  section_5_c : process is
+
+    -- code from book:
+
+    subtype voltage is real tolerance "default_voltage";
+    subtype high_current is real tolerance "coarse_current";
+
+    --
+
+    type gear is (unknown, park, reverse, neutral, first, second, third, fourth, fifth);
+    subtype forward is gear range first to fifth;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    assert voltage'tolerance = "default_voltage";
+    assert high_current'tolerance = "coarse_current";
+
+    --
+
+    assert forward'base'left = unknown;
+    assert forward'base'succ(reverse) = neutral;
+
+    -- end of code from book
+
+    wait;
+  end process section_5_c;
+
+
+  ----------------
+
+
+  section_5_d : block is
+
+
+    -- code from book:
+
+    subtype displacement is real tolerance "default_displacement";
+    subtype force is real tolerance "default_force";
+    nature translational is
+      displacement across
+      force through
+      translational_ref reference;
+
+    --
+
+    quantity qdisp : translational'across;  -- declares quantity of type displacement
+    quantity qforce : translational'through;  -- declares quantity of type force
+
+    -- end of code from book
+
+  begin
+  end block section_5_d;
+ 
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/int_types.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/int_types.vhd
new file mode 100644
index 0000000..90a87fd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/int_types.vhd
@@ -0,0 +1,24 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package int_types is
+
+  type small_int is range 0 to 255;
+
+end package int_types;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/small_adder.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/small_adder.vhd
new file mode 100644
index 0000000..8edf4dd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/scalar-data/small_adder.vhd
@@ -0,0 +1,24 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+use work.int_types.all;
+
+entity small_adder is
+  port ( a, b : in small_int;  s : out small_int );
+end entity small_adder;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/SR_flipflop.vhd
new file mode 100644
index 0000000..5715c84
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/SR_flipflop.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity SR_flipflop is
+  port ( S, R : in bit;  Q : out bit );
+end entity SR_flipflop;
+
+--------------------------------------------------
+
+architecture checking of SR_flipflop is
+begin
+
+    set_reset : process (S, R) is
+    begin
+      assert S = '1' nand R = '1';
+      if S = '1' then
+        Q <= '1';
+      end if;
+      if R = '1' then
+        Q <= '0';
+      end if;
+    end process set_reset;
+
+end architecture checking;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd
new file mode 100644
index 0000000..508f683
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/cos.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity cos is
+  port ( theta : in real;  result : out real );
+end entity cos;
+
+--------------------------------------------------
+
+architecture series of cos is
+begin
+
+  summation : process (theta) is
+    variable sum, term : real;
+    variable n : natural;
+  begin
+    sum := 1.0;
+    term := 1.0;
+    n := 0;
+    while abs term > abs (sum / 1.0E6) loop
+      n := n + 2;
+      term := (-term) * theta**2 / real(((n-1) * n));
+      sum := sum + term;
+    end loop;
+    result <= sum;
+  end process summation;
+
+end architecture series;
+
+
+architecture fixed_length_series of cos is
+begin
+
+  summation : process (theta) is
+    variable sum, term : real;
+  begin
+    sum := 1.0;
+    term := 1.0;
+    for n in 1 to 9 loop
+      term := (-term) * theta**2 / real(((2*n-1) * 2*n));
+      sum := sum + term;
+    end loop;
+    result <= sum;
+  end process summation;
+
+end architecture fixed_length_series;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter-1.vhd
new file mode 100644
index 0000000..359a22e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter-1.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity counter is
+  port ( clk, reset : in bit;  count : out natural );
+end entity counter;
+
+--------------------------------------------------
+
+architecture behavior of counter is
+begin
+
+  incrementer : process is
+    variable count_value : natural := 0;
+  begin
+    count <= count_value;
+    loop
+      loop
+        wait until clk = '1' or reset = '1';
+        exit when reset = '1';
+        count_value := (count_value + 1) mod 16;
+        count <= count_value;
+      end loop;
+      -- at this point, reset = '1'
+      count_value := 0;
+      count <= count_value;
+      wait until reset = '0';
+    end loop;
+  end process incrementer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd
new file mode 100644
index 0000000..37c586c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/counter.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity counter is
+  port ( clk : in bit;  count : out natural );
+end entity counter;
+
+--------------------------------------------------
+
+architecture behavior of counter is
+begin
+
+  incrementer : process is
+    variable count_value : natural := 0;
+  begin
+    count <= count_value;
+    loop
+      wait until clk = '1';
+      count_value := (count_value + 1) mod 16;
+      count <= count_value;
+    end loop;
+  end process incrementer;
+
+end architecture behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/edge_triggered_register.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/edge_triggered_register.vhd
new file mode 100644
index 0000000..b8bdf9b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/edge_triggered_register.vhd
@@ -0,0 +1,45 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity edge_triggered_register is
+  port ( clock : in bit; 
+         d_in : in real;  d_out : out real );
+end entity edge_triggered_register;
+
+--------------------------------------------------
+
+architecture check_timing of edge_triggered_register is
+begin
+
+  store_and_check : process (clock) is
+    variable stored_value : real;
+    variable pulse_start : time;
+  begin
+    case clock is
+      when '1' =>
+        pulse_start := now;
+        stored_value := d_in;
+        d_out <= stored_value;
+      when '0' =>
+        assert now = 0 ns or (now - pulse_start) >= 5 ns
+          report "clock pulse too short"; 
+    end case;
+  end process store_and_check;
+
+end architecture check_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/index-ams.txt
new file mode 100644
index 0000000..25a2efc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/index-ams.txt
@@ -0,0 +1,47 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                        Chapter 3 - Sequential Statements
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure
+-----------                                     ------------                            --------------                  -------
+thermostat-1.vhd                                entity thermostat                       example                         Figure 3-1
+mux4.vhd                                        package mux4_types                      body                            Section 3.2
+--                                              entity mux4                             demo                            Figure 3-2
+counter.vhd                                     entity counter                          behavior                        Figure 3-3
+counter-1.vhd                                   entity counter                          behavior                        Figure 3-4
+cos.vhd                                         entity cos                              series                          Figure 3-5
+--                                                                                      fixed_length_series             Figure 3-6
+SR_flipflop.vhd                                 entity SR_flipflop                      checking                        Figure 3-7
+max3.vhd                                        entity max3                             check_error                     Figure 3-8
+edge_triggered_register.vhd                     entity edge_triggered_register          check_timing                    Figure 3-9
+inline_01.vhd                                   entity inline_01                        test                            Section 3.1
+inline_02.vhd                                   entity inline_02                        test                            Section 3.1
+inline_03.vhd                                   entity inline_03                        test                            Section 3.1
+inline_04a.vhd                                  entity inline_04a                       test                            Section 3.1
+inline_05.vhd                                   entity inline_05                        test                            Section 3.1
+inline_06.vhd                                   entity inline_06                        test                            Section 3.2
+inline_07.vhd                                   entity inline_07                        test                            Section 3.2
+inline_08.vhd                                   entity inline_08                        test                            Section 3.2
+inline_09.vhd                                   entity inline_09                        test                            Section 3.2
+inline_10a.vhd                                  entity inline_10a                       test                            Section 3.3
+inline_11.vhd                                   entity inline_11                        test                            Section 3.3
+inline_12.vhd                                   entity inline_12                        test                            Section 3.4
+inline_13.vhd                                   entity inline_13                        test                            Section 3.4
+inline_14.vhd                                   entity inline_14                        test                            Section 3.4
+inline_15.vhd                                   entity inline_15                        test                            Section 3.4
+inline_16.vhd                                   entity inline_16                        test                            Section 3.4
+inline_17.vhd                                   entity inline_17                        test                            Section 3.4
+inline_18.vhd                                   entity inline_18                        test                            Section 3.5
+inline_19.vhd                                   entity inline_19                        test                            Section 3.5
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_mux4.vhd                                     entity tb_mux4                          test_demo                       mux4.vhd
+tb_counter.vhd                                  entity tb_counter                       test_behavior                   counter.vhd
+tb_counter-1.vhd                                entity tb_counter                       test_behavior                   counter-1.vhd
+tb_cos.vhd                                      entity tb_cos                           test_series                     cos.vhd
+tb_cos-1.vhd                                    entity tb_cos                           test_fixed_length_series        cos.vhd
+tb_SR_flipflop.vhd                              tb_SR_flipflop                          test_checking                   SR_flipflop.vhd
+tb_max3.vhd                                     entity tb_max3                          test_check_error                max3.vhd
+tb_edge_triggered_register.vhd                  entity tb_edge_triggered_register       test_check_timing               edge_triggered_register.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_01.vhd
new file mode 100644
index 0000000..022459e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_01.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+
+  signal en : bit := '0';
+  signal data_in : integer := 0;
+
+begin
+
+  process_1_a : process (en, data_in) is
+
+    variable stored_value : integer := 0;
+
+  begin
+
+    -- code from book:
+
+    if en = '1' then
+      stored_value := data_in;
+    end if;
+
+    -- end of code from book
+
+  end process process_1_a;
+
+  stimulus : process is
+  begin
+    en <= '1' after 10 ns, '0' after 20 ns;
+    data_in <= 1 after 5 ns, 2 after 15 ns, 3 after 25 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd
new file mode 100644
index 0000000..fa2e324
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_02.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+
+  signal sel : integer range 0 to 1 := 0;
+  signal input_0 : integer := 0;
+  signal input_1 : integer := 10;
+  signal result : integer;
+
+begin
+
+  process_1_b : process (sel, input_0, input_1) is
+  begin
+
+    -- code from book:
+
+    if sel = 0 then
+      result <= input_0;  -- executed if sel = 0
+    else
+      result <= input_1;  -- executed if sel /= 0
+    end if;
+
+    -- end of code from book
+
+  end process process_1_b;
+
+  stimulus : process is
+  begin
+    sel <= 1 after 40 ns;
+    input_0 <= 1 after 10 ns, 2 after 30 ns, 3 after 50 ns;
+    input_1 <= 11 after 15 ns, 12 after 35 ns, 13 after 55 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd
new file mode 100644
index 0000000..f997c91
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_03.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+begin
+
+  process_1_c : process is
+
+    type mode_type is (immediate, other_mode);
+    type opcode_type is (load, add, subtract, other_opcode);
+
+    variable mode : mode_type;
+    variable opcode : opcode_type;
+    constant immed_operand : integer := 1;
+    constant memory_operand : integer := 2;
+    constant address_operand : integer := 3;
+    variable operand : integer;
+
+    procedure procedure_1_c is
+    begin
+
+      -- code from book:
+
+      if mode = immediate then
+        operand := immed_operand;
+      elsif opcode = load or opcode = add or opcode = subtract then
+        operand := memory_operand;
+      else
+        operand := address_operand;
+      end if;
+
+      -- end of code from book
+
+    end procedure_1_c;
+
+  begin
+    mode := immediate;
+    procedure_1_c;
+
+    mode := other_mode;
+    opcode := load;
+    procedure_1_c;
+
+    opcode := add;
+    procedure_1_c;
+
+    opcode := subtract;
+    procedure_1_c;
+
+    opcode := other_opcode;
+    procedure_1_c;
+
+    wait;
+  end process process_1_c;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_04a.vhd
new file mode 100644
index 0000000..ae1c5af
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_04a.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04a is
+
+  type gear_type is (gear_1, gear_2, neutral);
+  signal gear : gear_type := gear_1;
+
+  signal gear_engaged : boolean := false;
+
+begin
+
+  process_1_d : process (gear) is
+
+    variable max_acceleration : real := 0.0;
+    variable reverse_indicator : boolean := true;
+
+  begin
+
+    -- code from book:
+
+    if gear = neutral then
+      max_acceleration := 0.0;
+      reverse_indicator := false;
+      gear_engaged <= false;
+    end if;
+
+    -- end of code from book
+
+  end process process_1_d;
+
+  stimulus : process is
+  begin
+    gear <= gear_2 after 100 ns, neutral after 200 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_05.vhd
new file mode 100644
index 0000000..30c2765
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_05.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+  type phase_type is (wash, other_phase);
+  signal phase : phase_type := other_phase;
+
+  type cycle_type is (delicate_cycle, other_cycle);
+  signal cycle_select : cycle_type := delicate_cycle;
+
+  type speed_type is (slow, fast);
+  signal agitator_speed : speed_type := slow;
+
+  signal agitator_on : boolean := false;
+
+begin
+
+  process_1_e : process (phase, cycle_select) is
+  begin
+
+    -- code from book:
+
+    if phase = wash then
+      if cycle_select = delicate_cycle then
+        agitator_speed <= slow;
+      else
+        agitator_speed <= fast;
+      end if;
+      agitator_on <= true;
+    end if;
+
+    -- end of code from book
+
+  end process process_1_e;
+
+  stimulus : process is
+  begin
+    cycle_select <= other_cycle;	wait for 100 ns;
+    phase <= wash;			wait for 100 ns;
+    cycle_select <= delicate_cycle;	wait for 100 ns;
+    cycle_select <= other_cycle;	wait for 100 ns;
+    phase <= other_phase;		wait for 100 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_06.vhd
new file mode 100644
index 0000000..5fb91e4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_06.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+  -- code from book:
+  
+  type alu_func is (pass1, pass2, add, subtract);
+  
+  -- end of code from book
+  
+  signal func : alu_func := pass1;
+  signal operand1 : integer := 10;
+  signal operand2 : integer := 3;
+
+begin
+
+  process_2_a : process (func, operand1, operand2) is
+
+    variable result : integer := 0;
+
+  begin
+
+    -- code from book:
+
+    case func is
+      when pass1 =>
+        result := operand1;
+      when pass2 =>
+        result := operand2;
+      when add =>
+        result := operand1 + operand2;
+      when subtract =>
+        result := operand1 - operand2;
+    end case;
+
+    -- end of code from book
+
+  end process process_2_a;
+
+
+  stimulus : process is
+  begin
+    func <= pass2 after 10 ns,
+	    add after 20 ns,
+	    subtract after 30 ns;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_07.vhd
new file mode 100644
index 0000000..4613630
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_07.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_07 is
+begin
+
+  process_2_b : process is
+
+    -- code from book:
+
+    subtype index_mode is integer range 0 to 3;
+
+    variable instruction_register : integer range 0 to 2**16 - 1;
+
+    -- end of code from book
+
+    variable index_value : integer;
+    constant accumulator_A : integer := 1;
+    constant accumulator_B : integer := 2;
+    constant index_register : integer := 3;
+
+  begin
+
+    for i in index_mode loop
+      instruction_register := i * 2**12;
+
+      -- code from book:
+
+      case index_mode'((instruction_register / 2**12) rem 2**2) is
+        when 0 =>
+          index_value := 0;
+        when 1 =>
+          index_value := accumulator_A;
+        when 2 =>
+          index_value := accumulator_B;
+        when 3 =>
+          index_value := index_register;
+      end case;
+
+      -- end of code from book
+
+    end loop;
+
+    wait;
+  end process process_2_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_08.vhd
new file mode 100644
index 0000000..7c5496a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_08.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_08 is
+begin
+
+  process_2_c : process is
+
+    -- code from book:
+
+    type opcodes is
+      (nop, add, subtract, load, store, jump, jumpsub, branch, halt);
+
+    subtype control_transfer_opcodes is opcodes range jump to branch;
+
+    -- end of code from book
+
+    variable opcode : opcodes;
+    variable operand : integer;
+    constant memory_operand : integer := 1;
+    constant address_operand : integer := 2;
+
+  begin
+
+    for i in opcodes loop
+      opcode := i;
+
+      -- code from book:
+
+      case opcode is
+        when load | add | subtract =>
+          operand := memory_operand;
+        when store | jump | jumpsub | branch =>
+          operand := address_operand;
+        when others =>
+          operand := 0;
+      end case;
+
+      --
+
+      case opcode is
+        when add to load =>
+          operand := memory_operand;
+        when branch downto store =>
+          operand := address_operand;
+        when others =>
+          operand := 0;
+      end case;
+
+      -- end of code from book
+
+      case opcode is
+        when add to load =>
+          operand := memory_operand;
+        -- code from book:
+        when control_transfer_opcodes | store =>
+          operand := address_operand;
+        -- end of code from book
+        when others =>
+          operand := 0;
+      end case;
+
+    end loop;
+
+    wait;
+  end process process_2_c;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd
new file mode 100644
index 0000000..9539cca
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_09.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+begin
+
+
+  process_2_d : process is
+
+    -- code from book:
+
+    variable N : integer := 1;
+
+    --
+
+    constant C : integer := 1;
+
+    -- end of code from book
+
+    constant expression : integer := 7;
+
+  begin
+
+    -- code from book:
+
+    -- error: Case choice must be a locally static expression
+
+    -- case expression is         -- example of an illegal case statement
+    --   when N | N+1 => -- . . .
+    --   when N+2 to N+5 => -- . . .
+    --   when others => -- . . .
+    -- end case;
+
+    --
+
+    case expression is
+      when C | C+1 => -- . . .
+      when C+2 to C+5 => -- . . .
+      when others => -- . . .
+    end case;
+
+    -- end of code from book
+
+    wait;
+  end process process_2_d;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd
new file mode 100644
index 0000000..8911f43
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_10a.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_10a is
+
+end entity inline_10a;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_10a is
+
+  -- code from book:
+
+  type stick_position is (down, center, up);
+
+  -- end of code from book
+
+  signal throttle : stick_position;
+
+begin
+
+
+  process_3_a : process (throttle) is
+
+    variable speed : integer := 0;
+    constant decrement : integer := 1;
+    constant increment : integer := 1;
+
+  begin
+
+    -- code from book:
+
+    case throttle is
+      when down =>
+        speed := speed - decrement;
+      when up =>
+        speed := speed + increment;
+      when center =>
+        null; -- no change to speed
+    end case;
+
+    -- end of code from book
+
+  end process process_3_a;
+
+
+  stimulus : process is
+  begin
+    throttle <= down after 10 ns, center after 20 ns, up after 30 ns;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd
new file mode 100644
index 0000000..a03dfa7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_11.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_11 is
+
+end entity inline_11;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_11 is
+
+  signal sensitivity_list : bit := '0';
+
+begin
+
+
+  -- code from book:
+
+  -- make "sensitivity_list" roman italic
+  control_section : process ( sensitivity_list ) is
+  begin
+    null;
+  end process control_section;
+
+  -- end of code from book
+
+  stimulus : process is
+  begin
+    sensitivity_list <= '1' after 10 ns, '0' after 20 ns;
+    wait;
+  end process stimulus;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_12.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_12.vhd
new file mode 100644
index 0000000..c617047
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_12.vhd
@@ -0,0 +1,130 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_12 is
+
+end entity inline_12;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_12 is
+begin
+
+
+  process_4_a : process is
+
+    constant condition, condition_1,
+             condition_2, condition_3 : boolean := true;
+    variable index : integer;
+
+  begin
+
+    -- code from book: syntax check only
+
+    -- change "condition" to roman italic
+
+    -- not in book:
+    loop
+    -- end not in book
+
+    if condition then
+      exit;
+    end if;
+
+    -- not in book:
+    end loop;
+    -- end not in book
+
+    --
+
+    -- change "condition" to roman italic
+
+    loop
+      -- . . .
+      exit when condition;
+      -- . . .
+    end loop;
+    -- . . .      -- control transferred to here
+                  -- when condition becomes true within the loop
+
+    --
+
+    loop_name : loop
+      -- . . .
+      exit loop_name;
+      -- . . .
+    end loop loop_name ;
+
+    --
+
+    -- change conditions to roman italic with hyphens
+
+    outer : loop
+      -- . . .
+      inner : loop
+         -- . . .
+        exit outer when condition_1; -- exit 1
+        -- . . .
+        exit when condition_2;       -- exit 2
+        -- . . .
+      end loop inner;
+      -- . . .                      -- target A
+      exit outer when condition_3;   -- exit 3
+       -- . . .
+    end loop outer;
+    -- . . .                        -- target B
+
+    --
+
+    -- "statement..." in roman italic with hyphens
+
+    loop
+      -- statement_1;
+      next when condition;
+      -- statement_2;
+    end loop;
+
+    --
+
+    -- "statement..." in roman italic with hyphens
+
+    loop
+      -- statement_1;
+      if not condition then
+        -- statement_2;
+      end if;
+    end loop;
+
+    --
+
+    while index > 0 loop
+      -- . . .      -- statement A: do something with index
+    end loop;
+    -- . . .    -- statement B
+
+
+    -- end of code from book
+
+    wait;
+  end process process_4_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_13.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_13.vhd
new file mode 100644
index 0000000..b2ab596
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_13.vhd
@@ -0,0 +1,52 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_13 is
+
+end entity inline_13;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_13 is
+
+  signal count_out : integer;
+
+begin
+
+
+  process_4_b : process is
+  begin
+
+    -- code from book:
+
+    for count_value in 0 to 127 loop
+      count_out <= count_value;
+      wait for 5 ns;
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_4_b;
+
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_14.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_14.vhd
new file mode 100644
index 0000000..09ee787
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_14.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_14 is
+
+end entity inline_14;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_14 is
+
+    -- code from book:
+
+    type controller_state is (initial, idle, active, error);
+
+    -- end of code from book
+
+  signal current_state : controller_state := initial;
+
+begin
+
+
+  process_4_c : process is
+  begin
+
+    -- code from book:
+
+    for state in controller_state loop
+      -- . . .
+      -- not in book:
+      current_state <= state;
+      wait for 10 ns;
+      -- end not in book
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_4_c;
+
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_15.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_15.vhd
new file mode 100644
index 0000000..7086066
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_15.vhd
@@ -0,0 +1,46 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_15 is
+
+end entity inline_15;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_15 is
+begin
+
+  -- code from book:
+
+  erroneous : process is
+    variable i, j : integer;
+  begin
+    i := loop_param;          -- error!
+    for loop_param in 1 to 10 loop
+      loop_param := 5;        -- error!
+    end loop;
+    j := loop_param;          -- error!
+  end process erroneous;
+
+  -- end of code from book
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_16.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_16.vhd
new file mode 100644
index 0000000..f75a6ce
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_16.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_16 is
+
+end entity inline_16;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_16 is
+begin
+
+  -- code from book:
+
+  hiding_example : process is
+    variable a, b : integer;
+  begin
+    a := 10;
+    for a in 0 to 7 loop
+      b := a;
+    end loop;
+    -- a = 10, and b = 7
+    -- . . .
+    -- not in book:
+    wait;
+    -- end not in book
+  end process hiding_example;
+
+  -- end of code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_17.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_17.vhd
new file mode 100644
index 0000000..f498384
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_17.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_17 is
+
+end entity inline_17;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_17 is
+begin
+
+
+  process_4_f : process is
+  begin
+
+    -- code from book:
+
+    for i in 10 to 1 loop
+      -- . . .
+    end loop;
+
+    for i in 10 downto 1 loop
+      -- . . .
+    end loop;
+
+    -- end of code from book
+
+    wait;
+  end process process_4_f;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd
new file mode 100644
index 0000000..87917a5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_18.vhd
@@ -0,0 +1,92 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_18 is
+
+end entity inline_18;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_18 is
+begin
+
+
+  process_5_a : process is
+
+    constant initial_value : natural := 10;
+    constant max_value : natural := 8;
+    constant current_character : character := 'A';
+    constant input_string : string := "012ABC";
+    constant free_memory : natural := 0;
+    constant low_water_limit : natural := 1024;
+    constant packet_length : natural := 0;
+    constant clock_pulse_width : delay_length := 10 ns;
+    constant min_clock_width : delay_length := 20 ns;
+    constant last_position : natural := 10;
+    constant first_position : natural := 5;
+    constant number_of_entries : natural := 0;
+
+  begin
+
+    -- code from book:
+
+    assert initial_value <= max_value;
+
+    --
+
+    assert initial_value <= max_value
+      report "initial value too large";
+
+    --
+
+    assert current_character >= '0' and current_character <= '9'
+      report "Input number " & input_string & " contains a non-digit";
+
+    --
+
+    assert free_memory >= low_water_limit
+      report "low on memory, about to start garbage collect"
+      severity note;
+
+    --
+
+    assert packet_length /= 0
+      report "empty network packet received"
+      severity warning;
+
+    --
+
+    assert clock_pulse_width >= min_clock_width
+      severity error;
+
+    --
+
+    assert (last_position - first_position + 1) = number_of_entries
+      report "inconsistency in buffer model"
+      severity failure;
+
+    -- end of code from book
+
+    wait;
+  end process process_5_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_19.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_19.vhd
new file mode 100644
index 0000000..6a3c959
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/inline_19.vhd
@@ -0,0 +1,57 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_19 is
+
+end entity inline_19;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_19 is
+
+  subtype data_type is integer;
+
+  signal transmit_data : data_type := 0;
+
+begin
+
+
+  -- code from book:
+  
+  transmit_element : process (transmit_data) is
+    -- . . .      -- variable declarations
+  begin
+    report "transmit_element: data = "
+        & data_type'image(transmit_data);
+    -- . . .
+  end process transmit_element;
+
+  -- end of code from book
+
+
+  stimulus : process is
+  begin
+    transmit_data <= 10 after 10 ns, 20 after 20 ns;
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/max3.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/max3.vhd
new file mode 100644
index 0000000..cf515d4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/max3.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity max3 is
+  port ( a, b, c : in integer;  z : out integer );
+end entity max3;
+
+--------------------------------------------------
+
+architecture check_error of max3 is
+begin
+
+    maximizer : process (a, b, c)
+      variable result : integer;
+    begin
+      if a > b then
+        if a > c then
+          result := a;
+        else
+          result := a;  -- Oops!  Should be: result := c;
+        end if;
+      elsif  b > c then
+        result := b;
+      else
+        result := c;
+      end if;
+      assert result >= a and result >= b and result >= c
+        report "inconsistent result for maximum"
+        severity failure;
+      z <= result;
+    end process maximizer;
+
+end architecture check_error;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd
new file mode 100644
index 0000000..da18319
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- test code:
+
+package mux4_types is
+
+  -- code from book:
+
+  type sel_range is range 0 to 3;
+
+  -- end of code from book
+
+end package mux4_types;
+
+
+
+use work.mux4_types.all;
+
+-- end test code
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity mux4 is
+  port ( sel : in sel_range;
+         d0, d1, d2, d3 : in std_ulogic;
+         z : out std_ulogic );
+end entity mux4;
+
+--------------------------------------------------
+
+architecture demo of mux4 is
+begin
+
+  out_select : process (sel, d0, d1, d2, d3) is
+  begin
+    case sel is
+      when 0 => 
+        z <= d0;
+      when 1 => 
+        z <= d1;
+      when 2 => 
+        z <= d2;
+      when 3 => 
+        z <= d3;
+    end case;
+  end process out_select;
+
+end architecture demo;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_SR_flipflop.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_SR_flipflop.vhd
new file mode 100644
index 0000000..dc67dcd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_SR_flipflop.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_SR_flipflop is
+
+end entity tb_SR_flipflop;
+
+
+----------------------------------------------------------------
+
+
+architecture test_checking of tb_SR_flipflop is
+
+  signal S, R, Q : bit := '0';
+
+begin
+
+  dut : entity work.SR_flipflop(checking)
+    port map ( S => S, R => R, Q => Q );
+
+  stumulus : process is
+
+  begin
+    wait for 10 ns;
+    S <= '1';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+    S <= '1';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+    R <= '1';			wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    R <= '1';			wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    S <= '1';	R <= '1';	wait for 10 ns;
+    R <= '0';			wait for 10 ns;
+    S <= '0';			wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_checking;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos-1.vhd
new file mode 100644
index 0000000..45799a0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos-1.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_cos is
+
+end entity tb_cos;
+
+
+----------------------------------------------------------------
+
+
+architecture test_fixed_length_series of tb_cos is
+
+  signal theta, result : real := 0.0;
+
+begin
+
+  dut : entity work.cos(fixed_length_series)
+    port map ( theta => theta, result => result );
+
+  stimulus : process is
+
+    constant pi : real := 3.1415927;
+
+  begin
+    wait for 10 ns;
+    theta <= pi / 6.0;		wait for 10 ns;
+    theta <= pi / 4.0;		wait for 10 ns;
+    theta <= pi / 3.0;		wait for 10 ns;
+    theta <= pi / 2.0;		wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_fixed_length_series;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos.vhd
new file mode 100644
index 0000000..ab0afea
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_cos.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_cos is
+
+end entity tb_cos;
+
+
+----------------------------------------------------------------
+
+
+architecture test_series of tb_cos is
+
+  signal theta, result : real := 0.0;
+
+begin
+
+  dut : entity work.cos(series)
+    port map ( theta => theta, result => result );
+
+  stimulus : process is
+
+    constant pi : real := 3.1415927;
+
+  begin
+    wait for 10 ns;
+    theta <= pi / 6.0;		wait for 10 ns;
+    theta <= pi / 4.0;		wait for 10 ns;
+    theta <= pi / 3.0;		wait for 10 ns;
+    theta <= pi / 2.0;		wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_series;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd
new file mode 100644
index 0000000..383732a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter-1.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_counter is
+
+end entity tb_counter;
+
+
+----------------------------------------------------------------
+
+
+architecture test_behavior of tb_counter is
+
+  signal clk, reset : bit := '0';
+  signal count : natural;
+
+begin
+
+  dut : entity work.counter(behavior)
+    port map ( clk => clk, reset => reset, count => count );
+
+  stimulus : process is
+  begin
+
+    for cycle_count in 1 to 5 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    reset <= '1' after 15 ns;
+    for cycle_count in 1 to 5 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    reset <= '0' after 15 ns;
+    for cycle_count in 1 to 30 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    wait;
+  end process stimulus;
+
+end architecture test_behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd
new file mode 100644
index 0000000..aa0dafc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_counter.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_counter is
+
+end entity tb_counter;
+
+
+----------------------------------------------------------------
+
+
+architecture test_behavior of tb_counter is
+
+  signal clk : bit := '0';
+  signal count : natural;
+
+begin
+
+  dut : entity work.counter(behavior)
+    port map ( clk => clk, count => count );
+
+  stimulus : process is
+  begin
+    for cycle_count in 1 to 100 loop
+      wait for 20 ns;
+      clk <= '1', '0' after 10 ns;
+    end loop;
+
+    wait;
+  end process stimulus;
+
+end architecture test_behavior;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_edge_triggered_register.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_edge_triggered_register.vhd
new file mode 100644
index 0000000..bacfd02
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_edge_triggered_register.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_edge_triggered_register is
+
+end entity tb_edge_triggered_register;
+
+
+----------------------------------------------------------------
+
+
+architecture test_check_timing of tb_edge_triggered_register is
+
+  signal clock : bit := '0'; 
+  signal d_in, d_out : real := 0.0;
+
+begin
+
+  dut : entity work.edge_triggered_register(check_timing)
+    port map ( clock => clock, d_in => d_in, d_out => d_out );
+
+  stumulus : process is
+
+  begin
+    wait for 20 ns;
+
+    d_in <= 1.0;			wait for 10 ns;
+    clock <= '1', '0' after 10 ns;	wait for 20 ns;
+
+    d_in <= 2.0;			wait for 10 ns;
+    clock <= '1', '0' after 5 ns;	wait for 20 ns;
+
+    d_in <= 3.0;			wait for 10 ns;
+    clock <= '1', '0' after 4 ns;	wait for 20 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_check_timing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_max3.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_max3.vhd
new file mode 100644
index 0000000..d8096eb
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_max3.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_max3 is
+
+end entity tb_max3;
+
+
+----------------------------------------------------------------
+
+
+architecture test_check_error of tb_max3 is
+
+  signal a, b, c, z : integer := 0;
+
+begin
+
+  dut : entity work.max3(check_error)
+    port map ( a => a, b => b, c => c, z => z );
+
+  stumulus : process is
+
+  begin
+    wait for 10 ns;
+    a <= 7;				wait for 10 ns;
+		b <= 10;		wait for 10 ns;
+    			    c <= 15;	wait for 10 ns;
+    a <= 12;				wait for 10 ns;
+    a <= 20;				wait for 10 ns;
+
+    wait;
+  end process stumulus;
+
+end architecture test_check_error;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_mux4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_mux4.vhd
new file mode 100644
index 0000000..5e76e43
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_mux4.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_mux4 is
+
+end entity tb_mux4;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+
+architecture test_demo of tb_mux4 is
+
+  signal sel : work.mux4_types.sel_range := 0;
+  signal d0, d1, d2, d3, z : std_ulogic;
+
+begin
+
+  dut : entity work.mux4(demo)
+    port map ( sel => sel,
+               d0 => d0, d1 => d1, d2 => d2, d3 => d3,
+               z => z );
+
+  stimulus : process is
+  begin
+    wait for 5 ns;
+    d0 <= '1';			wait for 5 ns;
+    d1 <= 'H';			wait for 5 ns;
+    		sel <= 1;	wait for 5 ns;
+    d1 <= 'L';			wait for 5 ns;
+    		sel <= 2;	wait for 5 ns;
+    d0 <= '0';			wait for 5 ns;
+    d2 <= '1';			wait for 5 ns;
+    d2 <= '0';			wait for 5 ns;
+    		sel <= 3;	wait for 5 ns;
+    d3 <= '1';			wait for 5 ns;
+    d3 <= '0';			wait for 5 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test_demo;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/thermostat-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/thermostat-1.vhd
new file mode 100644
index 0000000..356e7d1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/thermostat-1.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.thermal_systems.all;
+
+entity thermostat is
+  port ( quantity sensor_temp : in temperature;
+         signal desired_temp : in real;
+         signal heater_on : out boolean );
+end entity thermostat;
+
+----------------------------------------------------
+
+architecture example of thermostat is
+begin
+
+  controller : process ( desired_temp, 
+                         sensor_temp'above(desired_temp + 2.0),
+                         sensor_temp'above(desired_temp - 2.0) ) is
+  begin
+    if sensor_temp < desired_temp - 2.0 then
+      heater_on <= true;
+    elsif sensor_temp > desired_temp + 2.0 then
+      heater_on <= false;
+    end if;
+  end process controller;
+
+end architecture example;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/addu.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/addu.vhd
new file mode 100644
index 0000000..377f266
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/addu.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity addu is
+end entity addu;
+
+
+architecture test of addu is
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  -- code in book
+
+  procedure addu ( a, b : in word32;
+                   result : out word32;  overflow : out boolean ) is
+    variable sum : word32;
+    variable carry : bit := '0';
+  begin
+    for index in sum'reverse_range loop
+      sum(index) := a(index) xor b(index) xor carry;
+      carry := ( a(index) and b(index) ) or ( carry and ( a(index) xor b(index) ) );
+    end loop;
+    result := sum;
+    overflow := carry = '1';
+  end procedure addu;
+
+  -- end code in book
+
+begin
+
+  stimulus : process is
+
+    -- code in book (in text)
+
+    variable PC, next_PC : word32;
+    variable overflow_flag : boolean;
+    -- . . .
+
+    -- end code in book
+
+  begin
+    PC := X"0000_0010";
+
+    -- code in book (in text)
+
+    addu ( PC, X"0000_0004", next_PC, overflow_flag);
+
+    -- end code in book
+
+    PC := X"FFFF_FFFC";
+    addu ( PC, X"0000_0004", next_PC, overflow_flag);
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/average_samples.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/average_samples.vhd
new file mode 100644
index 0000000..55d250c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/average_samples.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity average_sample is
+end entity average_sample;
+
+
+
+architecture test of average_sample is
+
+  procedure average_test is
+    
+    variable average : real := 0.0;
+    type sample_array is array (positive range <>) of real;
+    constant samples : sample_array :=
+      ( 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0 );
+
+    -- code from book
+  
+    procedure average_samples is
+      variable total : real := 0.0;
+    begin
+      assert samples'length > 0 severity failure;
+      for index in samples'range loop
+        total := total + samples(index);
+      end loop;
+      average := total / real(samples'length);
+    end procedure average_samples;
+  
+    -- end code from book
+
+  begin
+
+    -- code from book (in text)
+
+    average_samples;
+
+    -- end code from book
+
+  end procedure average_test;
+
+  
+begin
+
+  average_test;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd
new file mode 100644
index 0000000..bbcf283
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_lt.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity bv_lt is
+end entity bv_lt;
+
+
+
+architecture test of bv_lt is
+
+  -- code from book
+
+  procedure bv_lt ( bv1, bv2 : in bit_vector;  result : out boolean ) is
+    variable tmp1 : bit_vector(bv1'range) := bv1;
+    variable tmp2 : bit_vector(bv2'range) := bv2;
+  begin
+    tmp1(tmp1'left) := not tmp1(tmp1'left);
+    tmp2(tmp2'left) := not tmp2(tmp2'left);
+    result :=  tmp1 < tmp2;
+  end procedure bv_lt;
+
+  -- end code from book
+
+begin
+
+  stimulus : process is
+
+    subtype byte is bit_vector(0 to 7);
+    variable result : boolean;
+
+  begin
+    bv_lt( byte'(X"02"), byte'(X"04"), result );
+    assert result;
+
+    bv_lt( byte'(X"02"), byte'(X"02"), result );
+    assert not result;
+
+    bv_lt( byte'(X"02"), byte'(X"02"), result );
+    assert not result;
+
+    bv_lt( byte'(X"FC"), byte'(X"04"), result );
+    assert result;
+
+    bv_lt( byte'(X"04"), byte'(X"FC"), result );
+    assert not result;
+
+    bv_lt( byte'(X"FC"), byte'(X"FC"), result );
+    assert not result;
+
+    bv_lt( byte'(X"FC"), byte'(X"FE"), result );
+    assert result;
+
+    bv_lt( byte'(X"FE"), byte'(X"FC"), result );
+    assert not result;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_to_natural.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_to_natural.vhd
new file mode 100644
index 0000000..94fe982
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/bv_to_natural.vhd
@@ -0,0 +1,72 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity bv_to_natural is
+end entity bv_to_natural;
+
+
+
+architecture test of bv_to_natural is
+
+  -- code from book
+
+  function bv_to_natural ( bv : in bit_vector ) return natural is
+    variable result : natural := 0;
+  begin
+    for index in bv'range loop
+      result := result * 2 + bit'pos(bv(index));
+    end loop;
+    return result;
+  end function bv_to_natural;
+
+  -- end code from book
+
+  signal data : bit_vector(0 to 7);
+  constant address : bit_vector(0 to 3) := "0101";
+  constant Taccess : delay_length := 80 ns;
+
+begin
+
+  tester : process is
+
+    constant rom_size : natural := 8;
+    constant word_size : natural := 8;
+
+    -- code from book (in text)
+
+    type rom_array is array (natural range 0 to rom_size-1)
+                        of bit_vector(0 to word_size-1);
+    variable rom_data : rom_array;
+
+    -- end code from book
+
+  begin
+
+    rom_data := (X"00", X"01", X"02", X"03", X"04", X"05", X"06", X"07");
+
+    -- code from book (in text)
+
+    data <= rom_data ( bv_to_natural(address) ) after Taccess;
+
+    -- end code from book
+
+    wait;
+  end process tester;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/cache.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/cache.vhd
new file mode 100644
index 0000000..9df92fc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/cache.vhd
@@ -0,0 +1,111 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity cache is
+end entity cache;
+
+-- end not in book
+
+
+
+architecture behavioral of cache is
+  -- not in book
+  subtype word is bit_vector(0 to 31);
+  signal mem_addr : natural;
+  signal mem_data_in : word;
+  signal mem_read, mem_ack : bit := '0';
+  -- end not in book
+begin
+
+  behavior : process is
+
+    -- not in book
+    constant block_size : positive := 4;
+    type cache_block is array (0 to block_size - 1) of word;
+    type store_array is array (0 to 15) of cache_block;
+    variable data_store : store_array;
+    variable entry_index : natural := 1;
+    variable miss_base_address : natural := 16;
+    -- end not in book
+
+    -- . . .
+
+    procedure read_block( start_address : natural;
+                          entry : out cache_block ) is
+
+      variable memory_address_reg : natural;
+      variable memory_data_reg : word;
+
+      procedure read_memory_word is
+      begin
+        mem_addr <= memory_address_reg;
+        mem_read <= '1';
+        wait until mem_ack = '1';
+        memory_data_reg := mem_data_in;
+        mem_read <= '0';
+        wait until mem_ack = '0';
+      end procedure read_memory_word;
+
+    begin  -- read_block
+      for offset in 0 to block_size - 1 loop
+        memory_address_reg := start_address + offset;
+        read_memory_word;
+        entry(offset) := memory_data_reg;
+      end loop;
+    end procedure read_block;
+
+  begin  -- behavior
+     -- . . .
+    read_block( miss_base_address, data_store(entry_index) );
+     -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process behavior;
+
+
+  -- not in book
+
+  memory : process is
+
+    type store_array is array (0 to 31) of word;
+    constant store : store_array :=
+      ( X"00000000", X"00000001", X"00000002", X"00000003",
+        X"00000004", X"00000005", X"00000006", X"00000007",
+        X"00000008", X"00000009", X"0000000a", X"0000000b",
+        X"0000000c", X"0000000d", X"0000000e", X"0000000f",
+        X"00000010", X"00000011", X"00000012", X"00000013",
+        X"00000014", X"00000015", X"00000016", X"00000017",
+        X"00000018", X"00000019", X"0000001a", X"0000001b",
+        X"0000001c", X"0000001d", X"0000001e", X"0000001f" );
+
+  begin
+    wait until mem_read = '1';
+    mem_data_in <= store(mem_addr);
+    mem_ack <= '1';
+    wait until mem_read = '0';
+    mem_ack <= '0';
+  end process memory;
+
+  -- end not in book
+
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/check_setup.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/check_setup.vhd
new file mode 100644
index 0000000..3c93af7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/check_setup.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity check_setup is
+end entity check_setup;
+
+
+
+architecture test of check_setup is
+
+  -- code from book
+
+  procedure check_setup ( signal data, clock : in bit;
+                          constant Tsu : in time ) is
+  begin
+    if clock'event and clock = '1' then
+      assert data'last_event >= Tsu
+        report "setup time violation" severity error;
+    end if;
+  end procedure check_setup;
+
+  -- end code from book
+
+  signal ready, phi2 : bit := '0';
+  constant Tsu_rdy_clk : delay_length := 4 ns;
+
+begin
+
+  -- code from book (in text)
+
+  check_ready_setup : check_setup ( data => ready, clock => phi2,
+                                    Tsu => Tsu_rdy_clk );
+
+  -- end code from book
+
+  clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0';
+
+  stimulus : ready <= '1' after 4 ns,
+                      '0' after 56 ns,
+                      '1' after 87 ns,
+                      '0' after 130 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_processor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_processor.vhd
new file mode 100644
index 0000000..950971a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_processor.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity control_processor is
+  generic ( Tpd : delay_length := 3 ns );
+end entity control_processor;
+
+-- end not in book
+
+
+
+architecture rtl of control_processor is
+
+  type func_code is (add, subtract);
+
+  signal op1, op2, dest : integer;
+  signal Z_flag : boolean;
+  signal func : func_code;
+  -- . . .
+
+begin
+
+  alu : process is
+
+    procedure do_arith_op is
+      variable result : integer;
+    begin
+      case func is
+        when add =>
+          result := op1 + op2;
+        when subtract =>
+          result := op1 - op2;
+      end case;
+      dest  <=  result after Tpd;
+      Z_flag  <=  result = 0 after Tpd;
+    end procedure do_arith_op;
+
+  begin
+    -- . . .
+    do_arith_op;
+    -- . . .
+    -- not in book
+    wait on op1, op2, func;
+    -- end not in book
+  end process alu;
+
+  -- . . .
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    op1 <= 0;  op2 <= 0;	wait for 10 ns;
+    op1 <= 10; op2 <= 3;	wait for 10 ns;
+    func <= subtract;		wait for 10 ns;
+    op2 <= 10;			wait for 10 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture rtl;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_sequencer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_sequencer.vhd
new file mode 100644
index 0000000..521a2f6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/control_sequencer.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity control_sequencer is
+end entity control_sequencer;
+
+
+
+architecture test of control_sequencer is
+
+  signal phase1, phase2, reg_file_write_en,
+         A_reg_out_en, B_reg_out_en, C_reg_load_en : bit := '0';
+
+begin
+
+  -- code from book
+
+  control_sequencer : process is
+
+    procedure control_write_back is
+    begin
+      wait until phase1 = '1';
+      reg_file_write_en <= '1';
+      wait until phase2 = '0';
+      reg_file_write_en <= '0';
+    end procedure control_write_back;
+
+    procedure control_arith_op is
+    begin
+      wait until phase1 = '1';
+      A_reg_out_en <= '1';
+      B_reg_out_en <= '1';
+      wait until phase1 = '0';
+      A_reg_out_en <= '0';
+      B_reg_out_en <= '0';
+      wait until phase2 = '1';
+      C_reg_load_en <= '1';
+      wait until phase2 = '0';
+      C_reg_load_en <= '0';
+      control_write_back;        -- call procedure
+    end procedure control_arith_op;
+
+    -- . . .
+
+  begin
+    -- . . .
+    control_arith_op;          -- call procedure
+    -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process control_sequencer;
+
+  -- end code from book
+
+
+  clock_gen : process is
+  begin
+    phase1 <= '1' after 10 ns, '0' after 20 ns;
+    phase2 <= '1' after 30 ns, '0' after 40 ns;
+    wait for 40 ns;
+  end process clock_gen;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd
new file mode 100644
index 0000000..78435f8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/do_arith_op.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity do_arith_op is
+end entity do_arith_op;
+
+
+architecture test of do_arith_op is
+
+  type func_code is (add, subtract);
+
+  signal op1 : integer := 10;
+  signal op2 : integer := 3;
+  signal dest : integer := 0;
+  signal func : func_code := add;
+
+  signal Z_flag : boolean := false;
+
+  constant Tpd : delay_length := 3 ns;
+
+begin
+
+  stimulus : process is
+
+    -- code from book
+
+    procedure do_arith_op ( op : in func_code ) is
+      variable result : integer;
+    begin
+      case op is
+        when add =>
+          result := op1 + op2;
+        when subtract =>
+          result := op1 - op2;
+      end case;
+      dest  <=  result after Tpd;
+      Z_flag  <=  result = 0 after Tpd;
+    end procedure do_arith_op;
+
+    -- end code from book
+
+  begin
+    wait for 10 ns;
+
+    -- code from book (in text)
+
+    do_arith_op ( add );
+
+    -- end code from book
+
+    wait for 10 ns;
+
+    -- code from book (in text)
+
+    do_arith_op ( func );
+
+    -- end code from book
+
+    wait for 10 ns;
+    do_arith_op ( subtract );
+    wait for 10 ns;
+    op2 <= 10;
+    wait for 10 ns;
+    do_arith_op ( subtract );
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/ent.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/ent.vhd
new file mode 100644
index 0000000..0bebf8a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/ent.vhd
@@ -0,0 +1,54 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+architecture arch of ent is
+
+  type t is . . .;
+
+  signal s : t;
+
+  procedure p1 ( . . . ) is
+    variable v1 : t;
+  begin
+    v1 := s;
+  end procedure p1;
+
+begin  -- arch
+
+  proc1 : process is
+
+    variable v2 : t;
+
+    procedure p2 ( . . . ) is
+      variable v3 : t;
+    begin
+      p1 ( v2, v3, . . . );
+    end procedure p2;
+
+  begin  -- proc1
+    p2 ( v2, . . . );
+  end process proc1;
+
+  proc2 : process is
+    . . .
+  begin  -- proc2
+    p1 ( . . . );
+  end process proc2;
+
+end architecture arch;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/find_first_set.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/find_first_set.vhd
new file mode 100644
index 0000000..a4efe78
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/find_first_set.vhd
@@ -0,0 +1,89 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity find_first_set is
+end entity find_first_set;
+
+
+
+architecture test of find_first_set is
+
+  -- code from book
+
+  procedure find_first_set ( v : in bit_vector;
+                             found : out boolean;
+                             first_set_index : out natural ) is
+  begin
+    for index in v'range loop
+      if v(index) = '1' then
+        found := true;
+        first_set_index := index;
+        return;
+      end if;
+    end loop;
+    found := false;
+  end procedure find_first_set;
+
+  -- end code from book
+
+begin
+
+  stimulus : process is
+
+    -- code from book (in text)
+
+    variable int_req : bit_vector (7 downto 0);
+    variable top_priority : natural;
+    variable int_pending : boolean;
+    -- . . .
+
+    -- end code from book
+
+    constant block_count : natural := 16;
+
+    -- code from book (in text)
+
+    variable free_block_map : bit_vector(0 to block_count-1);
+    variable first_free_block : natural;
+    variable free_block_found : boolean;
+    -- . . .
+
+    -- end code from book
+
+  begin
+    int_req := "00010000";
+
+    -- code from book (in text)
+
+    find_first_set ( int_req, int_pending, top_priority );
+
+    -- end code from book
+
+    free_block_map := (others => '0');
+
+    -- code from book (in text)
+
+    find_first_set ( free_block_map, free_block_found, first_free_block );
+
+    -- end code from book
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/freq_detect.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/freq_detect.vhd
new file mode 100644
index 0000000..e001657
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/freq_detect.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity freq_detect is
+  port ( terminal input : electrical;
+         terminal freq_out : electrical );
+end entity freq_detect;
+
+----------------------------------------------------------------
+
+architecture threshold_crossing of freq_detect is
+  
+  quantity v_in across input to electrical_ref;
+  quantity v_out across i_out through freq_out to electrical_ref;
+  signal freq : real := 0.0;
+  constant threshold : real := 0.0;
+  constant scale_factor : real := 1.0e-6;
+        
+begin
+  
+  detect: process ( v_in'above(threshold) ) is
+    variable t_previous : real := real'low;
+  begin
+    if v_in > threshold then
+      freq <= scale_factor / ( now - t_previous );
+      t_previous := now;
+    end if;
+  end process detect;
+                
+  v_out == freq'ramp(1.0e-9, 1.0e-9);
+                
+end threshold_crossing;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd
new file mode 100644
index 0000000..c4cd40d
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/generate_clock.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity generate_clock is
+end entity generate_clock;
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture test of generate_clock is
+
+  -- code from book
+
+  procedure generate_clock ( signal clk : out std_ulogic;
+                             constant Tperiod, Tpulse, Tphase : in time ) is
+  begin
+    wait for Tphase;
+    loop
+      clk <= '1', '0' after Tpulse;
+      wait for Tperiod;
+    end loop;
+  end procedure generate_clock;
+
+  -- end code from book
+
+  -- code from book (in text)
+
+  signal phi1, phi2 : std_ulogic := '0';
+  -- . . .
+
+  -- end code from book
+
+begin
+
+  -- code from book (in text)
+
+  gen_phi1 : generate_clock ( phi1, Tperiod => 50 ns, Tpulse => 20 ns,
+                                    Tphase => 0 ns );
+
+  gen_phi2 : generate_clock ( phi2, Tperiod => 50 ns, Tpulse => 20 ns,
+                                    Tphase => 25 ns );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/hold_time_checker.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/hold_time_checker.vhd
new file mode 100644
index 0000000..e20b60b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/hold_time_checker.vhd
@@ -0,0 +1,55 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity hold_time_checker is
+end entity hold_time_checker;
+
+
+
+architecture test of hold_time_checker is
+
+  constant Thold_d_clk : delay_length := 3 ns;
+
+  signal clk, d : bit := '0';
+
+begin
+
+  -- code from book
+
+  hold_time_checker : process ( clk, d ) is
+    variable last_clk_edge_time : time := 0 fs;
+  begin
+    if clk'event and clk = '1' then
+      last_clk_edge_time := now;
+    end if;
+    if d'event then
+      assert now - last_clk_edge_time >= Thold_d_clk
+        report "hold time violation";
+    end if;
+  end process hold_time_checker;
+
+  -- end code from book
+
+  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
+
+  stimulus : d <= '1' after 15 ns,
+                  '0' after 53 ns,
+                  '1' after 72 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/increment.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/increment.vhd
new file mode 100644
index 0000000..b6aa145
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/increment.vhd
@@ -0,0 +1,65 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity increment is
+end entity increment;
+
+
+
+architecture test of increment is
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  -- code from book
+
+  procedure increment ( a : inout word32;  by : in word32 := X"0000_0001" ) is
+    variable sum : word32;
+    variable carry : bit := '0';
+  begin
+    for index in a'reverse_range loop
+      sum(index) := a(index) xor by(index) xor carry;
+      carry := ( a(index) and by(index) ) or ( carry and ( a(index) xor by(index) ) );
+    end loop;
+    a := sum;
+  end procedure increment;
+
+  -- end code from book
+
+begin
+
+  stimulus : process is
+
+    variable count : word32 := X"0001_1100";
+
+  begin
+
+    -- code from book (in text)
+
+    increment(count, X"0000_0004");
+
+    increment(count);
+
+    increment(count, by => open);
+
+    -- end code from book
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/index-ams.txt
new file mode 100644
index 0000000..2a966d2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/index-ams.txt
@@ -0,0 +1,52 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                             Chapter 9 - Subprograms
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+average_samples.vhd                             entity average_samples                  test                            Figure 9-1
+control_processor.vhd                           entity control_processor                rtl                             Figure 9-2
+instruction_interpreter.vhd                     entity instruction_interpreter          test                            Figure 9-3
+control_sequencer.vhd                           entity control_sequencer                test                            Figure 9-4
+instruction_interpreter-1.vhd                   entity instruction_interpreter          test                            Figure 9-5
+do_arith_op.vhd                                 entity do_arith_op                      test                            Figure 9-6
+addu.vhd                                        entity addu                             test                            Figure 9-7
+negate.vhd                                      entity negate                           test                            Figure 9-8
+receiver.vhd                                    entity receiver                         behavioral                      Figure 9-9
+signal_generator.vhd                            entity signal_generator                 top_level                       Figure 9-10
+increment.vhd                                   entity increment                        test                            Figure 9-11
+find_first_set.vhd                              entity find_first_set                   test                            Figure 9-12
+bv_lt.vhd                                       entity bv_lt                            test                            Figure 9-13
+check_setup.vhd                                 entity check_setup                      test                            Figure 9-14
+generate_clock.vhd                              entity generate_clock                   test                            Figure 9-15
+limited.vhd                                     entity limited                          test                            Figure 9-16
+bv_to_natural.vhd                               entity bv_to_natural                    test                            Figure 9-17
+network_driver.vhd                              entity network_driver                   test                            Figure 9-18
+hold_time_checker.vhd                           entity hold_time_checker                test                            Figure 9-19
+v_source.vhd                                    entity v_source                         source_sine                     Figure 9-20
+freq_detect.vhd                                 entity freq_detect                      threshold_crossing              Figure 9-21
+mixer.vhd                                       entity mixer                            weighted                        Figure 9-22
+mixer_wa.vhd                                    entity mixer_wa                         weighted                        --
+motor_system.vhd                                entity motor_control_system             state_space                     Figure 9-24
+motor_system_wa.vhd                             entity motor_control_system_wa          simple                          --
+reg_ctrl.vhd                                    entity reg_ctrl                         bool_eqn                        Figure 9-25
+ent.vhd                                         --                                      arch                            Figure 9-26
+cache.vhd                                       entity cache                            behavioral                      Figure 9-27
+p1.vhd                                          --                                      --                              Figure 9-28
+inline_01.vhd                                   entity inline_01                        test                            Section 9.2
+inline_02.vhd                                   entity inline_02                        test                            Section 9.3
+inline_03.vhd                                   entity inline_03                        test                            Section 9.4
+inline_04a.vhd                                  entity inline_04a                       test                            Section 9.4
+inline_05a.vhd                                  entity inline_05a                       test                            Section 9.4
+inline_06a.vhd                                  entity inline_06a                       --                              Section 9.4
+inline_07.vhd                                   entity inline_07                        test                            Section 9.6
+inline_08.vhd                                   entity inline_08                        test                            Section 9.6
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_v_source.vhd                                 entity tb_v_source                      TB_v_source                     v_source.vhd
+tb_freq_detect.vhd                              entity tb_freq_detect                   TB_freq_detect                  freq_detect.vhd
+tb_mixer.vhd                                    entity tb_mixer                         TB_mixer                        mixer_wa.vhd
+tb_motor_system.vhd                             entity tb_motor_system                  TB_motor_system                 motor_system_wa.vhd
+tb_reg_ctrl.vhd                                 entity tb_reg_ctrl                      test                            reg_ctrl.vhd
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_01.vhd
new file mode 100644
index 0000000..69a308e
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_01.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+  process_2_a : process is
+
+    type t1 is (t1_1, t1_2);
+    type t2 is (t2_1, t2_2);
+    type t3 is (t3_1, t3_2);
+    type t4 is (t4_1, t4_2);
+
+    constant v4 : t4 := t4_1;
+
+    constant val1 : t1 := t1_1;
+    constant val2 : t2 := t2_1;
+    variable var3 : t3 := t3_1;
+    constant val4 : t4 := t4_1;
+
+    -- code from book:
+
+    procedure p ( f1 : in t1;  f2 : in t2;  f3 : out t3;  f4 : in t4 := v4 ) is
+    begin
+      -- . . .
+    end procedure p;
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    p ( val1, val2, var3, val4 );
+    p ( f1 => val1, f2 => val2, f4 => val4, f3 => var3 );
+    p ( val1, val2, f4 => open, f3 => var3 );
+    p ( val1, val2, var3 );
+
+    -- end of code from book
+
+    wait;
+  end process process_2_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_02.vhd
new file mode 100644
index 0000000..ac3ece6
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_02.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+
+  constant val1 : integer := 1;
+
+  procedure p ( signal s1, s2 : in bit;  val1 : in integer ) is
+  begin
+    null;
+  end procedure p;
+
+begin
+
+
+  block_3_a : block is
+
+    signal s1, s2 : bit;
+
+  begin
+
+    -- code from book:
+
+    call_proc : p ( s1, s2, val1 );
+
+    -- end of code from book
+
+  end block block_3_a;
+
+
+  ----------------
+
+
+  block_3_b : block is
+
+    signal s1, s2 : bit;
+
+  begin
+
+    -- code from book:
+
+    call_proc : process is
+    begin
+      p ( s1, s2, val1 );
+      wait on s1, s2;
+    end process call_proc;
+
+    -- end of code from book
+
+  end block block_3_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_03.vhd
new file mode 100644
index 0000000..e9570b3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_03.vhd
@@ -0,0 +1,73 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.numeric_bit.all;
+
+architecture test of inline_03 is
+
+  constant T_delay_adder : delay_length := 10 ns;
+
+  -- code from book:
+
+  function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is
+  begin
+    -- . . .
+    -- not in book
+    return bit_vector(unsigned(bv1) + unsigned(bv2));
+    -- end not in book
+  end function bv_add;
+
+  signal source1, source2, sum : bit_vector(0 to 31);
+
+  -- end of code from book
+
+
+begin
+
+
+  -- code from book:
+
+  adder : sum <= bv_add(source1, source2) after T_delay_adder;
+
+  -- end of code from book
+
+
+  ----------------
+
+
+  stimulus : process is
+  begin
+    wait for 50 ns;
+    source1 <= X"00000002";  source2 <= X"00000003";  wait for 50 ns;
+                             source2 <= X"FFFFFFF0";  wait for 50 ns;
+    source1 <= X"00000010";                           wait for 50 ns;
+
+    wait;
+  end process stimulus;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_04a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_04a.vhd
new file mode 100644
index 0000000..21c42c0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_04a.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_04a is
+
+end entity inline_04a;
+
+
+architecture test of inline_04a is
+  
+  -- code from book
+  
+  function vector_multiply ( p : real_vector;  r : real ) return real_vector is 
+    variable result : real_vector(p'range);
+  begin
+    for index in p'range loop
+      result(index) := p(index) * r;
+    end loop;
+    return result;
+  end function vector_multiply;
+        
+  --
+  
+  quantity scale_factor : real;
+  quantity source_position, scaled_position : real_vector(1 to 3);
+
+  -- end code from book
+  
+begin
+
+  -- code from book
+  
+  scaled_position == vector_multiply ( source_position, scale_factor );
+
+  -- end code from book
+  
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_05a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_05a.vhd
new file mode 100644
index 0000000..d6eeefc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_05a.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05a is
+
+end entity inline_05a;
+
+
+architecture test of inline_05a is
+
+  function limited ( value, min, max : real ) return real is
+  begin
+    if value > max then
+      return max;
+    elsif value < min then
+      return min;
+    else
+      return value;
+    end if;
+  end function limited;
+
+  quantity v_in, v_amplified : real;
+  constant gain : real := 10.0;
+  constant v_neg : real := -10.0;
+  constant v_pos : real := 10.0;
+  
+begin
+
+  -- code from book
+
+  v_amplified == limited ( gain * v_in, v_neg, v_pos );
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_06a.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_06a.vhd
new file mode 100644
index 0000000..2f50845
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_06a.vhd
@@ -0,0 +1,44 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_06a is
+
+  -- code from book:
+
+  impure function now return delay_length;
+
+  -- end of code from book
+
+  impure function now return delay_length is
+  begin
+    return std.standard.now;
+  end function now;
+
+  -- code from book:
+
+  impure function now return real;
+
+  -- end of code from book
+
+  impure function now return real is
+  begin
+    return std.standard.now;
+  end function now;
+
+end entity inline_06a;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd
new file mode 100644
index 0000000..cf99a5b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_07.vhd
@@ -0,0 +1,82 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_07 is
+
+end entity inline_07;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.numeric_bit.all;
+
+architecture test of inline_07 is
+begin
+
+
+  process_5_a : process is
+
+    -- code from book:
+
+    procedure increment ( a : inout integer;   n : in integer := 1 ) is -- . . .
+    -- not in book
+    begin
+      a := a + n;
+    end procedure increment;
+    -- end not in book;
+
+    procedure increment ( a : inout bit_vector;  n : in bit_vector := B"1" ) is -- . . .
+    -- not in book
+    begin
+      a := bit_vector(signed(a) + signed(n));
+    end procedure increment;
+    -- end not in book;
+
+    procedure increment ( a : inout bit_vector;  n : in integer := 1 ) is -- . . .
+    -- not in book
+    begin
+      a := bit_vector(signed(a) + to_signed(n, a'length));
+    end procedure increment;
+    -- end not in book;
+
+    variable count_int : integer := 2;
+    variable count_bv : bit_vector (15 downto 0) := X"0002";
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    increment ( count_int, 2 );
+    increment ( count_int );
+
+    increment ( count_bv, X"0002");
+    increment ( count_bv, 1 );
+
+    -- increment ( count_bv );
+
+    -- end of code from book
+
+    wait;
+  end process process_5_a;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_08.vhd
new file mode 100644
index 0000000..01b5eb5
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/inline_08.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+library ieee;  use ieee.numeric_bit.all;
+
+architecture test of inline_08 is
+begin
+
+
+  process_5_b : process is
+
+    -- code from book:
+
+    function "+" ( left, right : in bit_vector ) return bit_vector is
+    begin
+      -- . . .
+      -- not in book
+      return bit_vector( "+"(signed(left), signed(right)) );
+      -- end not in book
+    end function "+";
+
+    variable addr_reg : bit_vector(31 downto 0);
+    -- . . .
+
+    -- end of code from book
+
+    -- code from book:
+
+    function "abs" ( right : in bit_vector ) return bit_vector is
+    begin
+      -- . . .
+      -- not in book
+      if right(right'left) = '0' then
+        return right;
+      else
+        return bit_vector( "-"(signed(right)) );
+      end if;
+      -- end not in book
+    end function "abs";
+
+    variable accumulator : bit_vector(31 downto 0);
+    -- . . .
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    addr_reg := addr_reg + X"0000_0004";
+
+    -- end of code from book
+
+    accumulator := X"000000FF";
+
+    -- code from book:
+
+    accumulator := abs accumulator;
+
+    -- end of code from book
+
+    accumulator := X"FFFFFFFE";
+    accumulator := abs accumulator;
+
+    wait;
+  end process process_5_b;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter-1.vhd
new file mode 100644
index 0000000..d72fe64
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter-1.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity instruction_interpreter is
+end entity instruction_interpreter;
+
+
+architecture test of instruction_interpreter is
+
+  subtype word is bit_vector(31 downto 0);
+
+  signal address_bus, data_bus_in : word := X"0000_0000";
+  signal mem_read, mem_request, mem_ready, reset : bit := '0';
+
+begin
+
+  -- code from book
+
+  instruction_interpreter : process is
+
+    -- . . .
+
+    -- not in book
+    variable mem_address_reg, mem_data_reg : word;
+    -- end not in book
+
+    procedure read_memory is
+    begin
+      address_bus <= mem_address_reg;
+      mem_read <= '1';
+      mem_request <= '1';
+      wait until mem_ready = '1' or reset = '1';
+      if reset = '1' then
+        return;
+      end if;
+      mem_data_reg := data_bus_in;
+      mem_request <= '0';
+      wait until mem_ready = '0';
+    end procedure read_memory;
+
+  begin
+    -- . . .    -- initialization
+    -- not in book
+    if reset = '1' then
+      wait until reset = '0';
+    end if;
+    -- end not in book
+    loop
+      -- . . .
+      read_memory;
+      exit when reset = '1';
+        -- . . .
+    end loop;
+  end process instruction_interpreter;
+
+  -- end code from book
+
+
+  memory : process is
+  begin
+    wait until mem_request = '1';
+    data_bus_in <= X"1111_1111";
+    mem_ready <= '1' after 10 ns;
+    wait until mem_request = '0';
+    mem_ready <= '0' after 10 ns;
+  end process memory;
+
+  reset <= '1' after 85 ns;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter.vhd
new file mode 100644
index 0000000..594ef76
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/instruction_interpreter.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity instruction_interpreter is
+end entity instruction_interpreter;
+
+
+library ieee;  use ieee.numeric_bit.all;
+
+architecture test of instruction_interpreter is
+
+  subtype word is unsigned(31 downto 0);
+
+  signal address_bus, data_bus_in : word := X"0000_0000";
+  signal mem_read, mem_request, mem_ready : bit := '0';
+
+begin
+
+  -- code from book
+
+  instruction_interpreter : process is
+
+    variable mem_address_reg, mem_data_reg,
+             prog_counter, instr_reg, accumulator, index_reg : word;
+    -- . . .
+    -- not in book
+    type opcode_type is (load_mem);
+    constant opcode : opcode_type := load_mem;
+    constant displacement : word := X"0000_0010";
+    -- end not in book
+
+    procedure read_memory is
+    begin
+      address_bus <= mem_address_reg;
+      mem_read <= '1';
+      mem_request <= '1';
+      wait until mem_ready = '1';
+      mem_data_reg := data_bus_in;
+      mem_request <= '0';
+      wait until mem_ready = '0';
+    end procedure read_memory;
+
+  begin
+    -- . . .  -- initialization
+    loop
+      -- fetch next instruction
+      mem_address_reg := prog_counter;
+      read_memory;                           -- call procedure
+      instr_reg := mem_data_reg;
+      -- . . .
+      case opcode is
+        -- . . .
+        when load_mem =>
+          mem_address_reg := index_reg + displacement;
+          read_memory;                        -- call procedure
+          accumulator := mem_data_reg;
+        -- . . .
+      end case;
+    end loop;
+  end process instruction_interpreter;
+
+  -- end code from book
+
+
+  memory : process is
+  begin
+    wait until mem_request = '1';
+    data_bus_in <= X"1111_1111";
+    mem_ready <= '1';
+    wait until mem_request = '0';
+    mem_ready <= '0';
+  end process memory;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/limited.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/limited.vhd
new file mode 100644
index 0000000..79f9e43
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/limited.vhd
@@ -0,0 +1,88 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity limited is
+end entity limited;
+
+
+
+architecture test of limited is
+
+  -- code from book
+
+  function limited ( value, min, max : real ) return real is
+  begin
+    if value > max then
+      return max;
+    elsif value < min then
+      return min;
+    else
+      return value;
+    end if;
+  end function limited;
+
+  -- end code from book
+
+begin
+
+  tester : process is
+
+    variable new_temperature, current_temperature, increment : real;
+    variable new_motor_speed, old_motor_speed,
+             scale_factor, error : real;
+
+  begin
+
+    current_temperature := 75.0;
+    increment := 10.0;
+
+    -- code from book (in text)
+
+    new_temperature := limited ( current_temperature + increment, 10.0, 100.0 );
+
+    -- end code from book
+
+    increment := 60.0;
+    new_temperature := limited ( current_temperature + increment, 10.0, 100.0 );
+    increment := -100.0;
+    new_temperature := limited ( current_temperature + increment, 10.0, 100.0 );
+
+    old_motor_speed := 1000.0;
+    scale_factor := 5.0;
+    error := 5.0;
+
+    -- code from book (in text)
+
+    new_motor_speed := old_motor_speed
+                       + scale_factor * limited ( error, -10.0, +10.0 );
+
+    -- end code from book
+
+    error := 15.0;
+    new_motor_speed := old_motor_speed
+                       + scale_factor * limited ( error, -10.0, +10.0 );
+
+    error := -20.0;
+    new_motor_speed := old_motor_speed
+                       + scale_factor * limited ( error, -10.0, +10.0 );
+
+    wait;
+  end process tester;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer.vhd
new file mode 100644
index 0000000..8dd8369
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer.vhd
@@ -0,0 +1,47 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity mixer is
+  port ( terminal inputs : electrical_vector(1 to 8);
+         terminal output : electrical );
+end entity mixer;
+
+----------------------------------------------------------------
+
+architecture weighted of mixer is
+  
+  quantity v_in across inputs;
+  quantity v_out across i_out through output;
+  constant gains : real_vector(1 to 8)
+    := ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 );
+  
+begin
+  
+  apply_weights : procedural is
+    variable sum : real := 0.0;
+  begin
+    for index in v_in'range loop
+      sum := sum + v_in(index) * gains(index);
+    end loop;
+    v_out := sum;
+  end procedural apply_weights;
+        
+end architecture weighted;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd
new file mode 100644
index 0000000..1f30454
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/mixer_wa.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity mixer_wa is
+  port ( terminal inputs : electrical_vector(1 to 8);
+         terminal output : electrical );
+end entity mixer_wa;
+
+----------------------------------------------------------------
+
+architecture weighted of mixer_wa is
+  
+  quantity v_in across inputs;
+  quantity v_out across i_out through output;
+  quantity v1, v2, v3, v4, v5, v6, v7, v8 : real;
+  constant gains : real_vector(1 to 8)
+    := ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 );
+        
+begin
+  
+	v1 == v_in(1) * gains(1);
+	v2 == v_in(2) * gains(2);
+	v3 == v_in(3) * gains(3);
+	v4 == v_in(4) * gains(4);
+	v5 == v_in(5) * gains(5);
+	v6 == v_in(6) * gains(6);
+	v7 == v_in(7) * gains(7);
+	v8 == v_in(8) * gains(8);
+        
+	v_out == v1 + v2 + v3 + v4 + v5 + v6 + v7 + v8;
+        
+end architecture weighted;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd
new file mode 100644
index 0000000..42f4d0f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system.vhd
@@ -0,0 +1,60 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+                        
+entity motor_system is
+  port ( terminal vp, vm : electrical;
+         terminal px : electrical_vector(1 to 3) );
+end entity motor_system;
+
+----------------------------------------------------------------
+
+architecture state_space of motor_system is
+  
+  quantity v_in across vp to vm;
+  quantity x across i_x through px to electrical_ref;
+  constant Tfb : real := 0.001;
+  constant Kfb : real := 1.0;
+  constant Te : real := 0.001;
+  constant Ke : real := 1.0;
+  constant Tm : real := 0.1;
+  constant Km : real := 1.0;
+        
+  type real_matrix is array (1 to 3, 1 to 3) of real;
+  constant c : real_matrix := ( ( -1.0/Tfb, 0.0, Kfb/Tfb ),
+                                ( -Ke/Te, -1.0/Te, 0.0 ),
+                                ( 0.0, Km/Tm, -1.0/Tm ) );
+        
+begin
+  
+  state_eqn : procedural is
+    variable sum : real_vector(1 to 3) := (0.0, 0.0, 0.0);
+  begin
+    for i in 1 to 3 loop
+      for j in 1 to 3 loop
+        sum(i) := sum(i) + c(i, j) * x(j);
+      end loop;
+    end loop;
+    x(1)'dot := sum(1);
+    x(2)'dot := sum(2) + (Ke/Te)*v_in;
+    x(3)'dot := sum(3);
+  end procedural state_eqn;
+        
+end architecture state_space;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system_wa.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system_wa.vhd
new file mode 100644
index 0000000..90c6110
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/motor_system_wa.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity motor_system_wa is  
+  port ( terminal vp, vm, px1, px2, px3 : electrical);  -- 2 inputs, 3 outputs
+end entity motor_system_wa;
+
+----------------------------------------------------------------
+
+architecture simple of motor_system_wa is
+  
+  quantity v_in across vp to vm;  -- Inout voltage/Current
+  quantity x1 across ix1 through px1 to electrical_ref;
+  quantity x2 across ix2 through px2 to electrical_ref;
+  quantity x3 across ix3 through px3 to electrical_ref;
+  constant Tfb : real := 0.001;
+  constant Kfb : real := 1.0;
+  constant Te : real := 0.001;
+  constant Ke : real := 1.0;
+  constant Tm : real := 0.1;
+  constant Km : real := 1.0;
+  constant c11 : real := -1.0/Tfb;
+  constant c12  : real := 0.0;
+  constant c13 : real := Kfb/Tfb;
+  constant c21 : real := -Ke/Te;
+  constant c22 : real := -1.0/Te;
+  constant c23 : real := 0.0;
+  constant c31 : real := 0.0;
+  constant c32 : real := Km/Tm;
+  constant c33 : real := -1.0/Tm;
+  
+begin  -- architecture simple
+  
+  x1'dot ==  c11*x1 + c12*x2 + c13*x3;
+  x2'dot ==  c21*x1 + c22*x2 + c23*x3  + (Ke/Te)*v_in;
+  x3'dot ==  c31*x1 + c32*x2 + c33*x3;
+  
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd
new file mode 100644
index 0000000..8c10cf0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/negate.vhd
@@ -0,0 +1,67 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity negate is
+end entity negate;
+
+
+architecture test of negate is
+
+  subtype word32 is bit_vector(31 downto 0);
+
+  -- code in book
+
+  procedure negate ( a : inout word32 ) is
+    variable carry_in : bit := '1';
+    variable carry_out : bit;
+  begin
+    a := not a;
+    for index in a'reverse_range loop
+      carry_out :=  a(index) and carry_in;
+      a(index) := a(index) xor carry_in;
+      carry_in := carry_out;
+    end loop;
+  end procedure negate;
+
+  -- end code in book
+
+begin
+
+  stimulus : process is
+
+    -- code in book (in text)
+
+    variable op1 : word32;
+    -- . . .
+
+    -- end code in book
+
+  begin
+   op1 := X"0000_0002";
+
+    -- code in book (in text)
+
+    negate ( op1 );
+
+    -- end code in book
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd
new file mode 100644
index 0000000..02461c8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity network_driver is
+end entity network_driver;
+
+
+architecture test of network_driver is
+
+  constant target_host_id : natural := 10;
+  constant my_host_id : natural := 5;
+  type pkt_types is (control_pkt, other_pkt);
+  type pkt_header is record
+      dest, src : natural;
+      pkt_type : pkt_types;
+      seq : natural;
+    end record;
+
+begin
+
+  -- code from book
+
+  network_driver : process is
+
+    constant seq_modulo : natural := 2**5;
+    subtype seq_number is natural range 0 to seq_modulo-1;
+    variable next_seq_number : seq_number := 0;
+    -- . . .
+    -- not in book
+    variable new_header : pkt_header;
+    -- end not in book
+
+    impure function generate_seq_number return seq_number is
+      variable number : seq_number;
+    begin
+      number := next_seq_number;
+      next_seq_number := (next_seq_number + 1) mod seq_modulo;
+      return number;
+    end function generate_seq_number;
+
+  begin  -- network_driver
+    -- not in book
+    wait for 10 ns;
+    -- end not in book
+    -- . . .
+    new_header := pkt_header'( dest => target_host_id,
+                               src => my_host_id,
+                               pkt_type => control_pkt,
+                               seq => generate_seq_number );
+    -- . . .
+  end process network_driver;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/p1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/p1.vhd
new file mode 100644
index 0000000..22627f9
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/p1.vhd
@@ -0,0 +1,36 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+procedure p1 is
+
+  variable v : integer;
+
+  procedure p2 is
+    variable v : integer;
+  begin  -- p2
+    . . .
+    v := v + 1;
+    . . .
+  end procedure p2;
+
+begin  -- p1
+  . . .
+  v := 2 * v;
+  . . .
+end procedure p1;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd
new file mode 100644
index 0000000..0c8a0b1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/receiver.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity receiver is
+end entity receiver;
+
+
+-- code from book
+
+architecture behavioral of receiver is
+
+  -- . . .    -- type declarations, etc
+
+  -- not in book
+
+  subtype packet_index_range is integer range 1 to 8;
+  type packet_array is array (packet_index_range) of bit;
+
+  -- end not in book
+
+  signal recovered_data : bit;
+  signal recovered_clock : bit;
+  -- . . .
+
+  procedure receive_packet ( signal rx_data : in bit;
+                             signal rx_clock : in bit;
+                             data_buffer : out packet_array ) is
+  begin
+    for index in packet_index_range loop
+      wait until rx_clock = '1';
+      data_buffer(index) := rx_data;
+    end loop;
+  end procedure receive_packet;
+
+begin
+
+  packet_assembler : process is
+    variable packet : packet_array;
+  begin
+    -- . . .
+    receive_packet ( recovered_data, recovered_clock, packet );
+    -- . . .
+  end process packet_assembler;
+
+  -- . . .
+
+
+  -- not in book
+
+  data_generator : recovered_data <= '1' after 5 ns,
+                                     '0' after 15 ns,
+                                     '1' after 25 ns,
+                                     '0' after 35 ns,
+                                     '0' after 45 ns,
+                                     '1' after 55 ns,
+                                     '0' after 65 ns,
+                                     '1' after 75 ns;
+
+  clock_generator : process is
+  begin
+    recovered_clock <= '0' after 2 ns, '1' after 10 ns;
+    wait for 10 ns;
+  end process clock_generator;
+
+  -- end not in book
+
+end architecture behavioral;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/reg_ctrl.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/reg_ctrl.vhd
new file mode 100644
index 0000000..8d9c884
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/reg_ctrl.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity reg_ctrl is
+  port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
+         reg_rd, reg_wr : out std_ulogic );
+end entity reg_ctrl;
+
+--------------------------------------------------
+
+architecture bool_eqn of reg_ctrl is
+begin
+
+  rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
+
+  rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
+                      and not cpu_clk;
+
+end architecture bool_eqn;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/signal_generator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/signal_generator.vhd
new file mode 100644
index 0000000..b61730f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/signal_generator.vhd
@@ -0,0 +1,64 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity signal_generator is
+  generic ( period : delay_length := 20 ns;
+            pulse_count : natural := 5 );
+end entity signal_generator;
+
+-- end not in book
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+architecture top_level of signal_generator is
+
+  signal raw_signal : std_ulogic;
+  -- . . .
+
+  procedure generate_pulse_train ( width, separation : in delay_length;
+                                   number : in natural;
+                                   signal s : out std_ulogic ) is
+  begin
+    for count in 1 to number loop
+      s <= '1', '0' after width;
+      wait for width + separation;
+    end loop;
+  end procedure generate_pulse_train;
+
+begin
+
+  raw_signal_generator : process is
+  begin
+    -- . . .
+    generate_pulse_train ( width => period / 2,
+                           separation => period - period / 2,
+                           number => pulse_count,
+                           s => raw_signal );
+    -- . . .
+    -- not in book
+    wait;
+    -- end not in book
+  end process raw_signal_generator;
+
+  -- . . .
+
+end architecture top_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd
new file mode 100644
index 0000000..2715117
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_freq_detect.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_freq_detect is
+
+end tb_freq_detect;
+
+architecture TB_freq_detect of tb_freq_detect is
+    terminal in_src, freq_out : electrical;
+    -- Component declarations
+    -- Signal declarations
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_sine(ideal)
+        generic map(
+            freq => 200.0,
+            amplitude => 5.0
+        )
+    	port map(
+            pos => in_src,
+            neg => ELECTRICAL_REF
+        );
+
+    freq1 : entity work.freq_detect(threshold_crossing)
+        port map(
+            input => in_src,
+            freq_out => freq_out
+        );
+end TB_freq_detect;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd
new file mode 100644
index 0000000..e0526b0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_mixer.vhd
@@ -0,0 +1,123 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_mixer is
+end tb_mixer;
+
+architecture TB_mixer of tb_mixer is
+    -- Component declarations
+    -- Signal declarations
+    terminal mix_in : electrical_vector(1 to 8);
+    terminal pseudo_gnd : electrical;
+begin
+    -- Signal assignments
+    -- Component instances
+    v3 : entity work.v_sine(ideal)
+        generic map(
+            amplitude => 5.0,
+            freq => 1.0e3
+        )
+        port map(
+            pos => mix_in(7),
+            neg => ELECTRICAL_REF
+        );
+    v4 : entity work.v_sine(ideal)
+        generic map(
+            amplitude => 4.0,
+            freq => 2.0e3
+        )
+        port map(
+            pos => mix_in(8),
+            neg => ELECTRICAL_REF
+        );
+    v9 : entity work.v_sine(ideal)
+        generic map(
+            freq => 1.0e3,
+            amplitude => 5.0
+        )
+        port map(
+            pos => mix_in(5),
+            neg => ELECTRICAL_REF
+        );
+    v10 : entity work.v_sine(ideal)
+        generic map(
+            freq => 2.0e3,
+            amplitude => 4.0
+        )
+        port map(
+            pos => mix_in(6),
+            neg => ELECTRICAL_REF
+        );
+    R2 : entity work.resistor(ideal)
+        generic map(
+            res => 1.0e3
+        )
+        port map(
+            p1 => pseudo_gnd,
+            p2 => ELECTRICAL_REF
+        );
+    mixer1 : entity work.mixer_wa(weighted)
+        port map(
+            inputs => mix_in,
+            output => pseudo_gnd
+        );
+    v14 : entity work.v_sine(ideal)
+        generic map(
+            amplitude => 4.0,
+            freq => 2.0e3
+        )
+        port map(
+            pos => mix_in(2),
+            neg => ELECTRICAL_REF
+        );
+    v15 : entity work.v_sine(ideal)
+        generic map(
+            amplitude => 5.0,
+            freq => 1.0e3
+        )
+        port map(
+            pos => mix_in(1),
+            neg => ELECTRICAL_REF
+        );
+    v16 : entity work.v_sine(ideal)
+        generic map(
+            freq => 2.0e3,
+            amplitude => 4.0
+        )
+        port map(
+            pos => mix_in(4),
+            neg => ELECTRICAL_REF
+        );
+    v17 : entity work.v_sine(ideal)
+        generic map(
+            freq => 1.0e3,
+            amplitude => 5.0
+        )
+        port map(
+            pos => mix_in(3),
+            neg => ELECTRICAL_REF
+        );
+end TB_mixer;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd
new file mode 100644
index 0000000..77fc0d4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_motor_system.vhd
@@ -0,0 +1,51 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_motor_system is
+end tb_motor_system ;
+
+architecture TB_motor_system of tb_motor_system is
+    -- Component declarations
+    -- Signal declarations
+	terminal in_src, x1_out, x2_out, x3_out : electrical;
+
+begin
+    v7 : entity work.v_sine(ideal)
+        generic map(
+            freq => 10.0,
+            amplitude => 1.0
+        )
+        port map(
+            pos => in_src,
+			neg => electrical_ref
+        );
+	state_var1: entity work.motor_system_wa(simple)
+		port map(
+            vp => in_src,
+            vm => ELECTRICAL_REF,
+			px1 => x1_out,
+			px2 => x2_out,
+			px3 => x3_out
+        );
+end TB_motor_system ;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_reg_ctrl.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_reg_ctrl.vhd
new file mode 100644
index 0000000..c08db00
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_reg_ctrl.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_reg_ctrl is
+end entity tb_reg_ctrl;
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+library util;
+
+architecture test of tb_reg_ctrl is
+
+  signal reg_addr_decoded, rd, wr, io_en,
+         cpu_clk, reg_rd, reg_wr : std_ulogic := '0';
+  signal test_vector : std_ulogic_vector(1 to 5);
+
+  use util.stimulus_generators.all;
+
+begin
+
+  dut : entity work.reg_ctrl
+    port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr );
+
+  stimulus : process is
+  begin
+    all_possible_values( bv => test_vector,
+                              delay_between_values => 10 ns );
+    wait;
+  end process stimulus;
+
+  (reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd
new file mode 100644
index 0000000..e509b55
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/tb_v_source.vhd
@@ -0,0 +1,50 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE_proposed;
+use IEEE_proposed.electrical_systems.all;
+
+entity tb_v_source is
+
+end tb_v_source ;
+
+architecture TB_v_source of tb_v_source is
+    terminal in_src, out_flt : electrical;
+    -- Component declarations
+    -- Signal declarations
+begin
+    -- Signal assignments
+    -- Component instances
+    vio : entity work.v_source(source_sine)
+        port map(
+            p => in_src,
+            m => ELECTRICAL_REF
+        );
+
+    R1 : entity work.resistor(ideal)
+        generic map(
+            res => 10.0e3
+        )
+        port map(
+            p1 => in_src,
+            p2 => electrical_ref
+        );
+end TB_v_source ;
+
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/v_source.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/v_source.vhd
new file mode 100644
index 0000000..845d65c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/v_source.vhd
@@ -0,0 +1,35 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+library ieee;  use ieee.math_real.all;
+               
+entity v_source is
+  port ( terminal p, m : electrical );
+end entity v_source;
+
+----------------------------------------------------------------
+
+architecture source_sine of v_source is
+  constant ampl : real := 1.0;
+  constant freq : real := 60.0;
+  quantity v across i through p to m;
+begin
+  v == ampl * sin(2.0 * math_pi * freq * now);
+end architecture source_sine;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/clock_duty.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/clock_duty.vhd
new file mode 100644
index 0000000..6538cb3
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/clock_duty.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- This digital clock allows user to specify the duty cycle using
+-- the parameters "on_time" and "off_time"
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity clock_duty is
+
+  generic ( on_time : time := 20 us;
+            off_time : time := 19.98 ms ); 
+  
+  port ( clock_out    : out std_logic := 'Z' );
+  
+end entity clock_duty;
+
+
+architecture ideal of clock_duty is
+
+begin
+
+  process
+  begin
+    wait for 1 us;
+    clock_out <= '1';
+    wait for on_time;
+    clock_out <= '0';
+    wait for off_time;
+  end process;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/gain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/gain.vhd
new file mode 100644
index 0000000..3c3af86
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/gain.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity gain is
+  generic ( k : real := 1.0 );  -- gain multiplier
+  port ( quantity input : in real;
+         quantity output : out real);
+end entity gain;
+
+architecture simple of gain is
+begin
+  output == k * input;
+end architecture simple;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/util/index-ams.txt
new file mode 100644
index 0000000..4e4d377
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/index-ams.txt
@@ -0,0 +1,18 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    Utilities
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+clock_duty.vhd                                  entity clock_duty                       ideal
+gain.vhd                                        entity gain                             simple
+resistor.vhd                                    entity resistor                         ideal
+src_constant.vhd                                entity src_constant                     ideal
+src_pulse.vhd                                   entity src_pulse                        ideal
+src_sine.vhd                                    entity src_sine                         ideal
+sum2.vhd                                        entity sum2                             simple
+stimulus_generators.vhd                         package stimulus_generators             body
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/resistor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/resistor.vhd
new file mode 100644
index 0000000..43d2765
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/resistor.vhd
@@ -0,0 +1,31 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+  port ( terminal p1, p2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+  quantity v across i through p1 to p2;
+  constant resistance : real := 10000.0;
+begin
+  v == i * resistance;
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_constant.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_constant.vhd
new file mode 100644
index 0000000..e7eb720
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_constant.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- Voltage Pulse Source (Includes Frequency Domain settings)
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity src_constant is
+  
+  generic ( level : real := 1.0;       -- Constant output value (V)
+            ac_mag : real := 1.0;      -- AC magnitude 
+            ac_phase : real := 0.0 );  -- AC phase (degrees)
+
+  port ( quantity output : out real );
+
+end entity src_constant;
+
+
+architecture ideal of src_constant is
+
+  -- Declare quantity in frequency domain for AC analysis 
+  quantity ac_spec : real spectrum ac_mag, math_2_pi * ac_phase / 360.0;
+
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+    output == level;
+  else	
+    output == ac_spec;  -- used for frequency (AC) analysis
+  end use;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_pulse.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_pulse.vhd
new file mode 100644
index 0000000..ba3c72f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_pulse.vhd
@@ -0,0 +1,71 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- Voltage Pulse Source (Includes Frequency Domain settings)
+
+library ieee;  use ieee.math_real.all;
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity src_pulse is
+  
+  generic ( initial : real := 0.0;     -- initial value
+            pulse : real;              -- pulsed value
+            ti2p : real;	       -- transition time - initial to pulse
+            tp2i : real;	       -- transition time - pulse to initial
+            delay : time := 0ms;       -- delay time
+            width : time;	       -- duration of pulse (includes ti2p)
+            period : time;	       -- period 
+            ac_mag : real := 1.0;      -- AC magnitude
+            ac_phase : real := 0.0 );  -- AC phase (degrees)
+
+  port ( quantity output : out real );
+
+end entity src_pulse;
+
+
+architecture ideal of src_pulse is
+
+  -- Declare quantity in frequency domain for AC analysis 
+  quantity ac_spec : real spectrum ac_mag, math_2_pi * ac_phase / 360.0;
+
+  -- Signal and constant used in process below  
+  signal pulse_signal : real := initial;
+  constant low_width: time := period - width;
+
+begin
+
+  if domain = quiescent_domain or domain = time_domain use
+    output == pulse_signal'ramp(ti2p, tp2i);
+  else
+    output == ac_spec;   -- used for frequency (AC) analysis
+  end use;
+
+  -- Process to create events on pulse_signal used for rise and fall edges
+  proc1 : process
+  begin
+    wait for delay;
+    loop
+      pulse_signal <= pulse;
+      wait for width;
+      pulse_signal <= initial;
+      wait for low_width;
+    end loop;
+  end process;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_sine.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_sine.vhd
new file mode 100644
index 0000000..f5b82c8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/src_sine.vhd
@@ -0,0 +1,56 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library IEEE;  use IEEE.MATH_REAL.all;
+library IEEE_proposed;  use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
+
+entity src_sine is
+
+  generic ( freq : real;              -- frequency [Hertz]
+            amplitude : voltage;      -- amplitude [Volts]
+            phase : real := 0.0;      -- initial phase [Degrees]
+            offset : voltage := 0.0;  -- DC value [Volts]
+            df : real := 0.0;         -- damping factor [1/second]
+            ac_mag : voltage := 1.0;  -- AC magnitude [Volts]
+            ac_phase : real := 0.0);  -- AC phase [Degrees]
+
+  port ( quantity output : out real );
+
+end entity src_sine;
+
+
+architecture ideal of src_sine is
+  
+  -- Declare quantity for phase in radians (calculated below)
+  quantity phase_rad : real;
+  -- Declare quantity in frequency domain for AC analysis
+  quantity ac_spec : real spectrum ac_mag, math_2_pi * ac_phase / 360.0;
+
+begin
+  
+  -- Convert phase to radians
+  phase_rad == math_2_pi *(freq * now + phase / 360.0);
+
+  if domain = quiescent_domain or domain = time_domain use
+    output == offset + amplitude * sin(phase_rad) * exp(-now * df);
+  else
+    output == ac_spec;  -- used for Frequency (AC) analysis
+  end use;
+
+end architecture ideal;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd
new file mode 100644
index 0000000..a5cdc0a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/stimulus_generators.vhd
@@ -0,0 +1,90 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+package stimulus_generators is
+
+  procedure all_possible_values ( signal bv : out bit_vector;
+				  delay_between_values : in delay_length );
+
+  procedure all_possible_values ( signal bv : out std_ulogic_vector;
+				  delay_between_values : in delay_length );
+
+  procedure all_possible_values ( signal bv : out std_logic_vector;
+				  delay_between_values : in delay_length );
+
+end package stimulus_generators;
+
+
+
+package body stimulus_generators is
+
+  type digit_table is array ( natural range 0 to 1 ) of bit;
+  constant digit : digit_table := ( '0', '1' );
+
+
+  function natural_to_bv ( nat : in natural;
+      	      	      	   length : in natural ) return bit_vector is
+
+    variable temp : natural := nat;
+    variable result : bit_vector(0 to length - 1);
+
+  begin
+    for index in result'reverse_range loop
+      result(index) := digit( temp rem 2 );
+      temp := temp / 2;
+    end loop;
+    return result;
+  end function natural_to_bv;
+
+
+  procedure all_possible_values ( signal bv : out bit_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= natural_to_bv(0, bv'length);
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= natural_to_bv(value, bv'length);
+    end loop;
+  end procedure all_possible_values;
+
+
+  procedure all_possible_values ( signal bv : out std_ulogic_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= To_StdULogicVector(natural_to_bv(0, bv'length));
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= To_StdULogicVector(natural_to_bv(value, bv'length));
+    end loop;
+  end procedure all_possible_values;
+
+
+  procedure all_possible_values ( signal bv : out std_logic_vector;
+				  delay_between_values : in delay_length ) is
+  begin
+    bv <= To_StdLogicVector(natural_to_bv(0, bv'length));
+    for value in 1 to 2**bv'length - 1 loop
+      wait for delay_between_values;
+      bv <= To_StdLogicVector(natural_to_bv(value, bv'length));
+    end loop;
+  end procedure all_possible_values;
+
+end package body stimulus_generators;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/util/sum2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/util/sum2.vhd
new file mode 100644
index 0000000..614f409
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/util/sum2.vhd
@@ -0,0 +1,29 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity sum2 is
+  generic ( k1, k2 : real := 1.0 );  	-- Optional gain multipliers
+  port ( quantity in1, in2 : in real;	-- Input quantity ports
+         quantity output : out real );	-- Output quantity port
+end entity sum2;
+
+architecture simple of sum2 is
+begin
+  output == k1 * in1 + k2 * in2;  -- Sum of inputs (with optional gain)
+end architecture simple;